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USER'S MANUAL

1. Address jr Bito6 Ss Bito2 eum Bitoo ame 0x00 SR 0x0000 RW op sme ser Fl T IN z V C oxot BSR 0x0000 Rw BSR 7 0 0x02 cPucon 0x0000 RW ar SW ber WUPS tO erst SMC 2 0 0x03 0x05 Reserve 0x06 PORTA 0x0000 Rw PORTA 15 0 0x07 PORTB 0x0000 RIW PORTB 7 0 0x08 Reserve 0x09 INTFO 0x0000 RAW DROMIF PWMPIF PWMDIF RTCIF3 RTCIF2 RTCIFI RTCIFO EXINTIF munal TF3 TVIF2 TiF2 mp mo EXINTIFO Ox0A Mm rang Rw SPLIMIF WDTIF 0x0B Reserve oxoc INTEO 0x0000 RW DROMIE PWMPIE PWMDIE AE RTCIE2 RTCIE1 RTCIEO EXINTIE1 b TIE3 TVIE2 TE2 Tet men EXINTIEO 0x0D we 0x0000 RW SPLIME WDTIE 0x0E 0x0F Reserve oxto PC 0x0000 RW PC 15 0 0x11 SPA Oxuuuu R W SPA 15 0 0x12 RCR ox0000 RW RCR 15 0 0x13 LcR oxooo0 Iw LCR 15 0 oxt4 Lsa 0x0000 Rw LSA 15 0 0x15 LEA 0x0000 RW LEA 15 0 oxt INTPO 0x0000 RAW DROMIP PWMPIP PWMDIP a RTCIP2 RTCIP1 RTCIPO EXINTIP1 ma tvip2 mal mPa Tipo EXINTIPO 0x17 INTP1 0x0000 RAW SPLIMIP WDTIP 0x18 Reserve 0x19 Eicon 0x0000 Rw EXINTIEN Exivripro EXINTOE EXINTO 1 0 orta FSR OxtFFF Rw FSR 9 0 0x1B SPLIM 0x0000 RW Stack point limited register address 15 0 0x1C 0x1F Reserve 0x20 0x22 Reserve 0x23 PDIRA 0x0000 RAW PDIRA 15 0 0x24 PCON1B 0x000
2. VCC 4 5V LS1 SPEAKER a 4 s 2 DACO lt O zoa no 1 200 SIE p o o KA ooo S S 886 222 CS gt gt 506 q d al dd lala 8 9g 8 Ads s Figure 5 2 eSLS 3V 4 5V Support Application Circuit Diagram 144 e Application Circuits eSL eSLS Series eSLZ000 User s Manual 5 3 eSLZ000 Application Circuit Chapter 5 Showing A D D A using BJT SPI RC OSC touch panel and PWM supporting 3V CC 3v LG 150 AVDD 3V R6 vec_3v An IC 0 1u C21 do Tel 0 14 alu 7 R Di e EM swi Ls2 uf 8 CRE a a ass EO E a KUKI E z zmo fa lt Woroa gt 5 Sa 36 a E 5099 Z Edo RS d e e ogg age 0 1u SPEAKER z z 2788 266 oses L 147 146 PALO 2 143 PAL a pa Dao PALI osci P VCC 3 E PA 3 C o PAL Cao PA S 31 U2 isg PA S osco ilz 8 ESCH PA 2 so HoD 5 12 pag sic LS C3 got 4 WP ScLK Fg 4324 Palio 26 rim GND SI ss HST PALM BTSO 53 2
3. 3 Sade It includes 32K 16 bit Program ROM RAM on chip ROM for both AA Reset Vector 0x0000 eSL amp eSLS Series or i 0x0002 nterrupt Vector RAM eSLZ000 only for your program and t a general data storage 7 utilization Program RO counter PC is the PI dedicated counter for E Ox3FFF Purpose q Registers program address andis 2 Um ege P 2 16 bi automatically modified 3 Linear memory R7 by control flow SES processing The eight general purpose registers can be used as y SE DETUR Program ROM or RAM 16 bit pointers Figure 2 2 eSL Series Program ROM Block Diagram 18 e Architecture eSL eSLS Series eSLZ000 User s Manual Pz Chapter 2 2 2 2 Data RAM and Bank Select Register The Figure 2 3 at right shows the organization in the eSL data RAM It ada consisted of six different ee addressing modes for the data memory cover Data RAM 16 0x01FF 8 bit 8 bit direct 1 cycle BSR address instruction Registers Indirect pointer e Indirect namely ia E e 16 bit direct ee AZ ies w e 8 bit direct Indirect ae RO with Displacement 16 cond e Indirect with Post decrement and R7 e Indirect with 0x07FF Post increment jx 0x1FFF 16 bit BSR Bank Select eSL amp eSLS eSLZ000 only Register is used for A Figure 2 3 eSL Series Data RAM Block Diagram M
4. RO 0X1FCO IO PWMD RO RO 0x7FCO IO PWMP RO RO 0X8C0C IO PWMCON RO Delay JMP Delay rd rd Set PWM register and output a square waveform to PORTAO Set PWMO A0 PWM1 A1 output Clear and disable PWM counter Set PWM duty 1 16384000 OX7F 1 7 8us Set PWM period 1 16384000 0x1FF 1 31 25us enable PWM reguar current volume 1 1 no repeat single ended mode left aligned both PWMO PWM1 output clock Fpll 1 Main loop eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 89 Chapter 3 Ve 3 5 Digital to Analog Converter DAC DAC is a 12 bit resolution current steering digital to analog converter used for voice and audio applications It can be directly terminated with resistive loads to produce voltage outputs In current mode DAC the power efficiency is very high since almost all power is dissipated in the load resistor at the output 3 5 1 Features e Special layout matrix for less sensitive to mismatch e Band gap circuit to generate current mirror source B DAC Attributes and Definitions Resource Timer0 1 interrupt DACD DACCON DACO Unsigned 2 s complement Clock source Usage register VO function pin Operation mode 3 5 2 Operation DA 11 0 Output Current FFF 4095 lis amp Imax 3m A FFE N N sp 001 ILsB 000 0 Itse The unit curr
5. Continued Function Algebra Assembly Operation wc UL Syntax If N 0 IF PL JMP Long_addr Long_addr gt PC mm IF PL JMP Short_addr ea PC 1 Offset gt PC If T 1 IF TS JMP Long_addr Long addr PC e If T 0 Long_addr gt PC If T 0 PC 1 Offset gt PC If Z N V 0 IF GT JMP Short addr Ten iat 1 1 2 T xd PC 1 Offset gt PC If N V IF GE JMP Long_addr Long a If N V 0 IF GE JMP Short_addr PC 1 Offset gt PC If C 1 IF HS JMP Long_addr Long_addr gt PC If C PC 1 Offset gt PC If Z 1 IF EQ JMP Long_addr Long_addr gt PC IF EQ JMP Short_addr na E PC 1 Offset gt PC IF NE JMP Long_addr ee Long addr5PC IF NE JMP Short addr Mane ut E PC 1 Offset gt PC Long pim IF LE JMP Short addr TELT SS PC 1 Offset gt PC If C 0 IF LO JMP Long_addr Longa addr gt PC IF LO JMP Short_add es a PC 14 Offset PC IF TC JMP Long_addr IF TC JMP Short_addr If T 1 IF TS JMP Short_addr PC 1 Offset gt PC IF HS JMP Short_addr S The short jump instruction 1 1 2 needs two cycles if jump is carried out and one cycle is needed if no jump is carried out eSL eSLS Series eSLZ000 User s Manual Instruction Set Summary e 155 Chapter 6 Ve Continued Function Algebra Assembly Operation wc D d d v c Syntax If C Z 1 2 2 IF LS JMP Long_add Long Sd IF LS JMP Short add Te Oe le PC 1 Offset gt PC IF LT JMP L dd Ne Me ong_a Long addr2PC IF LT
6. n 24 24 Miu queis cm 25 2 4 1 General Purpose Rena 26 24 2 Program Counter PC idees eiae roO aaa PUN UR Busan 26 24 3 St ck E AE 26 2 4 4 Repeat and Loop Register cile 26 2 4 5 MR 27 2 3 tee 29 2 5 1 Logic and Mathematic Instructions e ieeerererreereneeea 30 2 5 2 Conditional Branch istinti 31 2 5 3 Shift and Rotation Instructions 2scsavivssdssuwosoesstarsnndsotensadinsdescoomesstaxisedves 32 2 5 4 Data Transfer Instruction x iostcecasesssncesneseaccasiaanptasesssacedeubeatagndioadensaumneevinanerss 33 2 5 5 Bit Operation Instruction EE 34 2 5 6 Control Instructions PCT 35 dd DSPIDSIUCLDIO acari 36 2 0 Power Supply Circ it sissien isien a i 39 2 6 1 Power Supply Attributes and Features 39 2 7 E TE ALOE SY SUCII RO ROTE TU 40 2 7 1 BBC A UCET mU TES 40 PENES USC s 41 2 1 3 CPU Control ROBISIBES odii dien p aUas Ra teni EMI EUER gegen 44 PNE XN cu 44 2 8 1 pelare 45 20 OSE E 46 2 5 9 Power On Reset POR taria 47 2 8 4 Brown Out Reset BOR E 48 2 9 System Mode orali 49 29 1 Block Diagram T 49 E PAO illa 49 204 EE 50 2 9 5 System Mode Operation Erase 51 2 10 e S oe Low pasciu ev pare UY xtd CP T E ER 51 400 RESET sa AR 51 2 10 2 Trap Instr ction Eegeregie 51 2 10 53 lcs c IT 51 2 11 External Intetruptussteicuviseci Eugen 57 2 11 1 External Interrupt Control Resiste 57 iv e Contents eSL eSLS Serie
7. 5V Speaker esL Speaker Load Load DACO a Bad design b Good design Figure 3 25b I O Port Interfacing to BJT SV SV eSL eSL PB 5 PB 5 V a Bad design b Good design Figure 3 25c I O Port Driving a Relay eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 133 Chapter 3 En 3 12 Voltage Regulator 5V 3V Item T Resource Power supply pin RVIN RVOUT Normal mode 50mA output current Standby mode Low power consumption Operation mode The ELAN eSL Series chips are equipped with an on chip linear regulator with low quiescent current and small drop out voltage This regulator supports two operation modes i e Standby mode with low power consumption and Normal mode with 50mA output current If the system supply voltage is 3V the RVIN and RVOUT pins must be connected together to ground If the voltage is SV the IOVDD PWM IOVDD PB IOVDD PC are connected to 5V source voltage while VDD CPU VDD PM VDD OSC VDD ICE and AVDD AD AVDD DA must be connected to the regulator output voltage pin RVOUT to obtain a 3V power Power Supply IOVDD PWM IOVDD PB IOVDD PC VDD CPU VDD PM VDD OSC VDD ICE AVDD AD AVDD DA Support Voltage 5V and 3V both 3V only 134 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 AVSS_DA AVDD_DA AVSS_AD Od SSAOI gd SSAOI AVDD AD WM
8. WOST 132 PA 12 BTSI VCC 3v SPI Flash RO Mes 32 PA ersck 2 3 Bene D1258296124 SCL PA 14 BTCS IK 130 py te 195 P DROMD 0 1 NC DROMD 1 S l 18 NI 14 s RN1 PROMDI 198 1 16 u p 12 2 15 81 PBIO DROMDIA RS 1 5 34 a PBL1 DROMDIS 201 9 A 10 4 13 93 EBI DROMD 6 255 1 5 32 g4 PB 3 DROMDI7 203 17 p7 8 6 11 STE DROMD S 254 A EIE t 1 SMS 2 E 87 PBI7 DROMD 11 L 3 Ma 220 oY F ll DROMD 12 1 DI Dee Pls DROMD 13 L 1 Mo Sar PB 10 DROMD 14 43 gt S oz PB 11 DROMD 15 o3 PB 12 LN10304 Hor Feta jin 77129 PBL14 DROMA 0 72 DS PB 15 DROMA 1 CA DROMA 2 172 DROMA 3 175 eae BO E onou 3 71 eSLZ000 177 emm XP DROMAI6 178 E 69 DROMA 179 i 731 YN DROMA 8 30 YP DROMA 9 Hiet Touch Panel DROMA 10 155 cal cet RE in E an DROMA 13 E a DROMA 14 186 SL icemop DROMA 15 g7 DROMA 16 tas 168 DROMA 17 ag 169 SYSMODIO DROMA 18 190 15 1827 Se Motu DROMA 19 Hot DROMA 20 57 DROMA 21 H195 DROMA 22 154 DROMA 23 wes HE RDB e CEB AVDD_3V ro eta PD 1 Hey ro L R2 E 1640 2 2K PD 5 482 0 BoA 1670 AD CTRL PCI gg ce PC 1 gg 2 R3 Pe 84 D 10u 470 pera o PC 5 Pcie gio kA Mei pel a 4n C10 74 1 MIC il 2 Acc H T 76 R4 ca Z MICROPHONE AMPO Ee VCC_4 5V 39 22u DACO sak id SO 1 F1 o2 2 uso Ke RE 200 NNW 5 EI 2 P NNN gt gt 90000 666 SPEAKER Ld 3 lt gt gt gt gt ha Qi d s d dede BER Re NPN
9. 4 2 1 eSL and eSLS Parameter applicable Pins Condition Symbol Rate Value Unit Power Supply Voltage VDD Vpp TA 25 C ALL INPUT Vin TA 25 C 0 3 to 6 0 Input Voltage 0 3 to VDD 0 3 Operating Temperature Range 40 to 85 Storage Temperature Range 65 to 150 4 2 2 eSLZ000 Parameter Applicable Pins Symbol Condition Rate Value Unit Power Supply Voltage VDD Von TA 25 C ALL INPUT Vin TA 25 C 0 3 to 6 0 Input Voltage 0 3 to VDD 0 3 Operating Temperature Range 40 to 85 C Storage Temperature Range 65 to 150 138 e Electrical Characteristics eSL eSLS Series eSLZ000 User s Manual Pz Chapter 4 4 3 DC Characteristics Standard operation conditions VDD 3V GND 0V Ta 25 C unless otherwise stated 4 3 1 For eSLS and eSLZ000 Parameter Symbol Condition Fated Vale we wn TT a ees Unit Power supply voltage Input voltage PC 7 0 7 0 VPUOL Vin GND Pull up resistor except eSLS RESET VPUIL Vin GND rar 1000 1500 Refer to Section 3 12 Voltage Regulator 5V 3V for details eSL eSLS Series eSLZ000 User s Manual Electrical Characteristics e 139 Chapter 4 4 3 2 For eSL and eSLS Only Parameter PortA B C output high current Pins Symbol Condition PortA B C output low current IOHO IOHO VOH 2 4V
10. AGCEN Control Register Attributes and Definitions AGC VOX Application Field 0 Disable Disable 1 Disable Enable Sensor amplifier current amplifier 0 Enable Disable analog filter etc 1 Enable Enable Microphone front end circuit 120 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual En Chapter 3 3 9 1 1 Gain Amplifier The Gain Amplifier has two stages i e Pre Amplifier and Post Amplifier The Pre Amplifier has 20dB voltage gain The Post Amplifier is a non inverting type operation amplifier 3 9 1 2 AGC Function Located within the Pre amplifier stage is the Automatic Gain Control AGC unit The AGC has an adjustable time constant from external RC circuits When AGC is disabled AGCEN 0 this circuit will become a two stage OP Amplifier for other applications e g sensor amplifier current amplifier analog filter etc eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 121 Chapter 3 3 9 2 Examples BUF_PD DS 1 CODE POWERON RO 0 BUF PD RO RO IO PCONC RO RO OR 0x0C00 IO PCONC RO BS IO SR GIE BS IO INTE1 ADIE MIC ON 1 2 DA CON 0 0 7 AD SINGLE 5 1 BC BUF PD 0 ADC WAITS NOP NOP NOP BTEST BUF PD 0 IF TC JMP ADC WAIT5 RO PUE PD IO PORTA RO DA OUT RO Delay JMP Delay ADCINT USH IO LIB BSR USH IO _LIB SR USH RO D D mmm U O DO
11. Rs Ifthe result is 0 execute subtraction Otherwise addition is executed Initial XOR result is 0 2 Shift the register pair R1 RO one bit to the left Move the inverted result of XOR operation into the LSB 3 Compare the divisor and result sign bit XOR operation Output after completion lt _ Shift left one bit Divisor Rs DIVS DIV MSB of Divisor SUB ADD fe Dividend R1 Dividend RO Le il V MSB of ALU output Figure 2 17 Division Architecture Diagram eSL eSLS Series eSLZ000 User s Manual After repeating the process Steps 1 to 3 16 times the RO register will contain the quotient The eSL Series will then perform 32 bit by 16 bit division in a fractional format You can use the following instructions B DIV For unsigned division B DIVS For signed division In the fractional division the valid results are obtained only when the Dividend R1 RO is less or equal to Divisor Rs Ensure that the magnitude of the quotient is less than one 1 0 To perform the integer division you must shift the Dividend one bit to the left before dividing Architecture e 37 Chapter 2 38 e Architecture eSL eSLS Series eSLZ000 User s Manual Pz Chapter 2 2 6 Power Supply Circuit ELAN eSL Series power distribution network is designed to keep stable the power level on VDD and GND networks within
12. 1 Simple Jump if not equal If Z 0 then jump to PC n 1 Simple Jump if equal If Z 1 then jump to PC n 1 Simple Jump if plus If N 0 then jump to PC n 1 Simple Jump if minus If N 1 then jump to PC n 1 Simple Jump if test T clear If T 0 then jump to PC n 1 Simple Jump if test T set If T 1 then jump to PC n 1 Simple Jump if lower than If C 0 then jump to PC n 1 Unsigned Jump if higher or same If C 1 then jump to PC n 1 Unsigned Jump if lower or same If NNV 0 then jump to PC n 1 Unsigned Jump if greater than or equal If NNV 1 then jump to PC n 1 Signed Jump if greater than If ZI NAV 0 then jump to PC n 1 Signed Jump if less than or equal If ZI NAV 1 then jump to PC n 1 Signed Jump if less than If C 0 Z 1 then jump to PC n 1 Signed Always Jump Always jump to PC n 1 Simple The instruction code fetch and the program counter increment technique end with the following formula e PC new PC old 4 1 Offset When taking a short branch e PC new 16 bit LSB absolute address When taking a long branch eSL eSLS Series eSLZ000 User s Manual Architecture e 31 Chapter 2 2 5 3 Shift and Rotation Instructions The Shift and Rotation instructions are general purpose registers This Shift is capable of performing one bit shifting functions and the shifted out bits are all passed through the C flag bit The Rotation performs rotation operation though register an
13. 5 8 8 Kegel ex R Ebo S Figure 5 3 eSLZ000 3V Support Application Circuit Diagram eSL eSLS Series eSLZ000 User s Manual Application Circuits e 145 Chapter 5 146 e Application Circuits eSL eSLS Series eSLZ000 User s Manual Pz Chapter 6 Chapter 6 Instruction Set Summary 6 1 Symbol Summary 6 1 1 General Symbol Description Address Generator Address generator for data RAM ALU 16 bit signed unsigned arithmetic logic unit Multiplier 17x17 hardware multiplier Program Counter Program counter with 15 bits for 32K program ROM address Peripheral Control Peripheral control registers are useful for peripheral comment Registers including ADC DAC INT etc RAM 2K word internal RAM 0x0000 0x07FFF SR Status register contains carry zero overflow flag status Stack 16 bits address software stacks for subroutine call and interrupt WIC Word Cycle 6 1 2 Operand Description RO R7 General purpose register Rd Destination register RO R7 Rs Source register RO R7 Rt Second Source register RO R7 Rn The number of Repeat or Loop for counting RO R7 b Specific one of the operation bit of a Word exe R0 15 b 0 15 imm6 6 Bits Immediately Data 0 63 imm8 8 Bits Immediately Data 0 255 imm16 16 Bits IMmediately Data 0 65535 RAM16 The value of 16 Bits RAM Direct addressing RAM8 The value of 8 Bits RAM Direct a
14. 71 0 0 Differential reference mode 1 Single ended reference mode Clock Source this field determines the input clock frequency 000 Reserved 001 Feit 16 ADCLK 7 5 010 Fr 32 000 011 FPLL 64 100 Fr 128 101 Feu 256 110 Feu 512 111 TEXI2 Rising edge Chapter 3 B ADC Data ADCD Register Attributes and Definitions ADCD Bit DIR Description Reset Value ADCD 15 4 R A D conversion data Oxuuu 1 u unknown value When A D conversion is completed the conversion result can be read from the ADCD register Conversion result is ready and can be read only when ADIF 1 When touch panel pen down event occurs the PDTIF wil set to 1 if both TPEN and PDTEN are set to 1 Meanwhile system wake up occurs if TPEN PDTEN and PDTWK are all set to 1 3 6 3 Operation 3 6 3 1 Single Mode Under Single mode A D conversion is performed only once for the analog input on a specified single channel or as follows 1 A D conversion starts from the first channel when the A D Start ADST bit is set to 1 2 When A D conversion is completed the result is transferred to the AD data register ADCD 3 On completion of conversion the A D Interrupt Flag ADIF bit is set to 1 If at the same time the A D Interrupt Enable ADIE bit is also set to 1 an ADIF interrupt request is generated 4 The ADST bit remains set to 1 during A D conversion When A D conversion ends the ADST
15. Boot serial input Boot chip select Boot clock Boot serial output O Processor mode boot external SPI flash to internal program memory 1 ICE mode Introduction e 15 fe Chapter 2 Architecture Chapter 2 2 1 eSL System Block Diagram As shown in the block diagram below ELAN eSL Series eSL eSLS Series and eSLZ000 utilize a modified Harvard architecture in such a way that the memory is organized into two separated fields Program ROM and Data RAM As the memory is separated the central processing units can read write data at the same time Furthermore the I O space has an independent address i e the I O mapped I O The different configurations of each domain are explained in this chapter Program Counter Instruction Decoder i IMM 16 Control Unit Contol Signals ped OI Suissoppy T O Space SFR General Purpose Registers CH Port A D Suissoappy a 17x17 Multiplier Divider 16 bit ALU WDT Status Reg SPI Sumsoippy WVA i OSC PLL Petree eet d Figure 2 1 ELAN eSL Series System Block Diagram eSL eSLS Series eSLZ000 User s Manual Architecture e 17 Chapter 2 Va 2 2 Program ROM and Data RAM Description 2 2 1 Program ROM RAM
16. Crystal PALOI Vcc 6i ci cpu bai OSCI 10pF PA 2 OSCI PA 3 Yi FAM gevesHzL_ c2 m ra T PUES te PA 7 PA 15 PA 13 PA 8 E Leno a PAI PLLC PA 10 SPI Flash ROM HA d e mm PA 13 PDIO PA 14 PD EN S PA 15 PD 2 AVCC 3V BE PD 3 T E PD 4 DIR PD S m Foie s pr j eent eSL eAM Hel m soe D TR4 fo PBU 17 PBI2I _D TR5 18 PBS o o 18 PBl4 Site Ge 20 PBIS Pelo ge PB 6 PC 1 Pai PCI2 R3 D TR7 5 2 PRIA PES O 1u 2K ES D TR8 2 57 PBI PC 4 o o OF PB 10 PC 5 DS PB 11 PC 6 be OS PB 12 FCI cio al 5 a Go VCC 4 5V ee i S 2 9 PBL14 f L 5 O PB 15 MIC cs ol 51 MICROPHONE D XN AGC o xp SPEAKER 49 AMPO EmN E EM Q1 o lt 02 i NPN x O Son m 1 I amp OO as o o ei pet oa ZS S 838 zz E lt Soe oo Touch Panel id pl al als SR e B el Aos SES v Figure 5 1 eSL 4 5V Support Application Circuit Diagram eSL eSLS Series eSLZ000 User s Manual Application Circuits e 143 Chapter 5 5 2 eSLS Application Circuit Showing D A crystal OSC and PWM supporting 3V 5V For PWM driver Speaker LS1 VCC 4 5V RI 0 100hm Vcc cpu BATTERY Ext RESET Ti Vec cpu ou Vec_cpu H ci SPEAKER eta D TR1 lita D TR2 pra 5 D TR3 Do PAD OSCI 37 PA S PLLC OSCI 10pF Ya B azresuz L c2 i OSC 95 PASSI osco 14 eSLS DARA icine D TR5
17. Delay Lr Lr c RTCO interrupt function RTCOINT PUSH IO SR PUSH IO BSR PUSH RO PUSH R1 RO 0 IO BSR RO Change to RAM bankO dod d R1 SecData R1 SecData R1 SecData IO PORTD R1 PortD output SecData BC IO INTFO RTCIFO Clear RTCO Flag POP R1 POP RO POP IO BSR POP IO SR RETI 70 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 3 3 Timer 3 3 1 Timer 0 1 3 3 1 1 General Timer Timer 0 and 1 are 8 bit timers operating under Auto Reload Mode Each timer can be independent from each other with unique counting rates These general timers are used as time counter FPLL 12 bitPrescaler Clock Selector TCONO 1 ControlLogic TIFO TIF1 Figure 3 4 General Timer Function Block Diagram B Timer0 amp Timer Attributes and Resources Item Timer 0 Timer 1 Usage register TRLO TCONO TRL1 TCON1 Interrupt sources TIFO TIF1 Operation mode Auto reload Auto reload 3 3 1 2 Block Diagrams Feu 12 bitPresclar Clock Clock source source Timer0 Timer1 Figure 3 5a 12 Bit Prescaler Clock Selection Block Diagram eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 71 Chapter 3 Ve FromClock Set Timer Selector 8 bit Timer Counter TCNTO 1 Interrupt P Flagbit TIF 0 1 If equal Reset 8 bit comparator Timer Rel
18. Description Reset Value DROMHA 7 0 Data ROM High Address B DROMDELAY Control Register Setting Fsys Hz DROMDELAY 0 lt x lt 2M 00000 2M lt x lt 4M 00001 4M lt x lt 6M 00010 6M lt x lt 8M 00011 8M lt x lt 10M 00100 10M lt x lt 12M 00101 12M lt x lt 14M 00110 14M lt x lt 16M 01000 16M lt x lt 18M 01001 18M lt x lt 20M 01010 20M lt x lt 22M 01011 22M lt x lt 24M 01100 24M lt x lt 26M 01101 eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 101 Chapter 3 ps 3 7 4 Examples Read 128 word table data from ROM to RAM buffer DATA DataBuffer DS 128 Define RAM data buffer CODE POWERON RO 0x9009 Enable ROM read increase mode IO DROMCON RO RO table 65536 Set ROM high byte address IO DROMHA RO RO table 65536 Set ROM low byte address IO DROMLA RO R1 DataBuffer Get databuffer address R2 127 ROM table is 128 word LOOP R2 Read 128 word ROM data to RAM Databuffer NOP NOP NOP NOP Set ROM read delay time NOP NOP NOP NOP RO IO DROMD R1 RO ENDL _Delay Main loop JMP Delay 102 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Chapter 3 eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 103 Chapter 3 En 3 8 Serial Peripheral Interface eSL and eSLZ000 only 3 8 1 Features B 4 external pins MOSI MIS
19. Diagram 114 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual En Chapter 3 3 8 7 Master Mode Operation B SPI Master Mode Pin Definitions Pin Configuration SCK o Serial clock out MISO Po Serial data in MOSI BED Serial data out ISS I O YO pin this pin must hold low in master mode When a device is configured as a master MSTR 0 the SPI provides the serial clock on the SCK pin for the entire serial communications network The SPR 2 0 in the control register determines both transmit and receive bit transfer rate for the network The SPI supports 8 different data transfer rates Any data written to TDBR initiates data transmission on the SO pin if SPI module is enabled Simultaneously the received data is shifted through the SI pin into the LSB of SFDR When the selected number of bits has been transmitted the received data is loaded into the RDBR for software to read Data is stored right aligned in RDBR When the receive data transfer is completed which means that the specified number of data bits has been shifted through SFDR the following events will then occur 1 The SFDR contents are transferred to RDBR 2 The TCF bit is cleared to 0 3 If the SPI interrupt is enabled an interrupt is asserted see Section 2 10 3 Interrupts for more details eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 115 Chapter 3 En 3 8 8 Slave Mode Operation B SPI Slave Mo
20. Manual Introduction e 1 Chapter 1 1 2 Features B MCU 16 bit RISC CPU architecture CPU clock 20MHz 3 3V eSL and eSLS only CPU clock 18MHz a 3 3V eSLZ000 only Programmable PLL 4 CPU operation modes Fast Slow Green amp Sleep Powerful DSP Instruction Set MAC DIV RPT LOOP Saturation mode supported 8 general purpose registers GPR 20 interrupt sources with 2 level priority eSL and eSLZ000 only 17 interrupt source with 2 level priority eSLS only B Memory 32K word program memory 2K word data RAM eSL and eSLS only 8K word data RAM eSLZ000 only 32 128 256 512K word data ROM eSL only 128 256 512K word data ROM eSLS only External data ROM up to 32MB eSLZ000 only B Peripherals 2 e Introduction Real Time Clock RTC with wake up function Four 8 bit timers two general purpose timer two multiple function timer 8 bit Watch Dog Timer WDT with general purpose timer capability 40 GPIO 8 Output eSL and eSLZ000 only 24 GPIO eSLS only Serial Peripheral Interface eSL and eSLZ000 only 12 bit Analog to Digital Converter with touch panel and MIC inputs eSL and eSLZ000 only Built in regulator 12 bit current steering Digital to Analog Converter DAC 10 bit resolution Pulse Width Modulation PWM eSL eSLS Series eSLZ000 User s Manual Pz Chapter 1 1 3 Parts List and Properties 1 3 1 eSLZ000 and eSL ICs Parts List and Properties Product eSL032 eSL128 eSL256 eSL512
21. Ox1FF Ox1FF Fa Center frequency Ox3DE Ox3DE Fax Ox3DF Ox3DF Fax Ox3FF 0x3E0 Not Available Note that 32K frequency is from 32K RC X tal Oscillator Example X tal is used as oscillator and F32x 32 768 kHz then OxOFA F32x 8 MHz 0x177 Fsx 12 MHz 0x1F4 Fax 16 MHz 0x226 F32x 18 MHz 42 e Architecture eSL eSLS Series eSLZ000 User s Manual Pz Chapter 2 2 7 2 3 FSR Operation Examples It is strongly suggested that to use the library on FSR operation i e c pll set c pll get Refer to the library guide see eSL Series C Macro Reference Manual and eSL Series Assembler Reference Manual for further detailed information The folowing shows an example unsigned int pll value pll value c pll get Get PLL clock c pll set 0x020 Set PLL clock 1MHz eSL eSLS Series eSLZ000 User s Manual Architecture e 43 Chapter 2 2 7 3 CPU Control Registers CPUCON Bit Description Reset Value Slow mode changes to normal mode SLT 15 0 Un change 0 1 Mode changing Software reset I O control reset SW RST 7 0 Disable 0 1 Software reset active Warm up time selection It is available in Slow and Green mode For Sleep mode wake up always select 00 1 32K 1024 Sec 00 1 32K 1024 sec 01 1 32K 512 sec 10 1 32K 256 sec 11 1 32K 128 sec Division Ratio Select for Fsys 00 1 2 divides clock by 2 or Fsys FpLU2 SCS 01 1 4 d
22. Rd h Rd l un change Rd IO 18 Read IO port 18 to Rd Register IO OxA Rs Write Rs Register to IO port 10 0xA PUSH IO 7 Save the content of IO port 7 on the stack 2 5 5 Bit Operation Instruction These Operations instruction uses a mask value to test or change the value of individual bits in I O RAM or registers B Space Definitions Space RAM Direct 0x0000 0x0007 I O 0x00 OxOF B Bit Operating Definitions Mnemonic Description Operation Bitb setas 1 Mask OR b 1 others 0 Lothers 0 BC Bit b clear as 0 Mask AND b 0 others 1 BTEST Bit b test as 1 Mask AND b 1 others 0 Bit b toggle Mask XOR b 1 others 0 34 e Architecture eSL eSLS Series eSLZ000 User s Manual Pz Chapter 2 2 5 6 Control Instructions The instructions in this group are used for the program control flow CALL RET and RETI instructions provided subroutine and interrupt execution Unconditional overhead free program loop constructs are supported using the RPT and LOOP instructions B CALL Before jumping to target address the 16 bit return address PC 1 is pushed into the stack B RET Pop the return address to PC then return from subroutine B RETI Pop the return address to PC then return from interrupt service routine B RPT Repeat the next instruction B LOOP Zero overhead LOOP must include at least 3 instruction but the last instruction cannot be JMP CALL RETURN or RPT instruction See S
23. SP 1 RAM Space 0x0000 i 2 SPLIM CLL LLLLLLLLLLL OKOTFO 1 Esses SP RSX Ox07FF Ox 1 FFF Case d SP dynamic so short Error occur 1 SP dynamic range SP SPLIM 2 Data usable range SPLIM 1 0x0000 eSL amp eSLS eSLZ000 only Figure 2 27 Effect to RAM Memory with SPA amp SPLIM at Various Positions Block Diagram 60 e Architecture eSL eSLS Series eSLZ000 User s Manual En Chapter 2 2 12 3 Register Description The Stack Pointer Limit SPLIM register as defined in the table below shows its default value as Address 0x0000 of RAM If the Stack Pointer value equals that of SPLIM then SPLIMIF SPLIM Interrupt Frame is set and interrupt occurs SPLIM Bit DIR Description Reset Value The SPLIM range SPLIM 15 0 RW 0 0x07FF eSL and eSLS 0x0000 0 0x1FFF eSLZ000 only 2 12 4 Operation Description In reference to the above block diagram Figure 2 27 Cases a to c illustrate the program initial value setup before program starts Case d shows the SPA setup with SPLIM operation constraint for the reason that its SPA dynamic operational range is limited too short B Case a The first case shows a good example for keeping the SPA value at maximum which ensures value will not negatively exceed to less than Address 0x0000 of RAM memory The two reasons behind it are first the dynamic operative range of SPA is large enough for the required usage The other is
24. TCF 0 Setting SPICR SPIEN 1 Setting SPICR SPIEN 1 Write data to TDBR TXS 1 Write data toTDBR TXS 1 Is TDBR Is TDBR EM empty TXS 0 full TXS 1 Data transfer end D Transfer or receive complete TCF 0 YES YES Last data NJ complete TCF 0 YES Data transfer end YES SPI empty data transfer mode SPI complete data transfer mode Figure 3 22 SPI Complete Data Transfer Mode Flow Chart 3 8 10 SPI Boot Flash Interface and SPI Data Flash Interface The eSLZ000 supports both SPI boot flash and SPI data flash while eSL only supports SPI data flash eSLZ000 reads data into program memory from SPI boot flash first and then does the data transfer via SPI data flash see their respective Application Circuits in Chapter 5 eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 117 Chapter 3 3 8 11 Examples Read 8 word data from ROM to RAM buffer and write data to SPI device DATA SPI Temp Data DS 16 Hold Data RAM for SPI transfer CODE POWERON TESTDATA DW 0X0102 0X0304 0X0506 Define test data for SPI transfer DW 0X0708 0X090A 0X0B0C DW OXODOE O0XOF10 RO SPI Temp Data R1 TESTDATA R2 R0 0x0008 _COUNT RO P R1 Read 8 word data form data ROM to data RAM SPI Temp Data CMP RO R2 IF NE JMP COUNT SPI SECTOR ERASE 0x0000 0x0000 Erase fi
25. VDD 3V IOLO IOLO VOL 0 4V PortD output high current eSLS NOT supported SRI HI VOH 2 4V PortD output low current VDD 3V eSLS NOT supported ER loka VOL 0 4V PortA 12 15 high current HD enable Ps SR VOH 2 4V PortA 12 15 low current IOL2 IOL2 VDD 3V HD enable VOL 0 4V PWM PWM output high current Ge IPWMH VOH VDD 2 Max volume PWM PWM output low current S IPWML VOL VDD 2 PWM1 Max volume DAC output current DACO IDAC RVIN 4 5V Regulator output high RVOUT IOUTH RVOUT 3 0V current FAST SLOW RVIN 4 5V Regulator output low RVOUT IOUTL RVOUT 3 0V current GREEN SLEEP modes Fast mode current consumption increment IFAST No load per MHz Slow mode current ISLOW No load consumption Green mode current IGREEN consumption Sleep mode current ISLEEP consumption CPU operation frequency 140 e Electrical Characteristics eSL eSLS Series eSLZ000 User s Manual eSLS NOT supported PortC 4 3 3 For eSLZ000 Only Parameter Pins Symbol Condition PortA B C output high VDD 3V current o RHO VOH 2 4V PortA B C output low VDD 3V current VORO VORO VOL 0 4V PortD output high t IOH1 IOH1 ao ortD output high curren VOH 2 4V VDD 3V PortD output low current IOL1 IOL1 VOL 0 4V PortA 12 15 high current VDD 3V HD enable oe EE VOH 2 4V PortA 12 15 low current VDD 3V HD enable lobe Ss VOL 0 4V VDD 3V PWM output high current di IPWMH VOH VD
26. are made up of 4 registers 1 e Repeat Counter Loop Counter Loop Start Address and Loop End Address They are used as temporary registers when executing repeat or loop instruction The Repeat and Loop Counter stored the repeat time Furthermore it needs to store the start and end address in a loop operation 26 e Architecture eSL eSLS Series eSLZ000 User s Manual Chapter 2 2 4 5 Status Register SR ss contains the following system status bits Foe De Tz FA FA CCENT x Dont care Reserved for future enhancements Where B Carry C Flag C is set when a carry or borrow occurs during an arithmetic operation The Carry Flag bit is set or reset depending on the operation that is performed For ADD instructions C 1 Carry occurs C 0 No carry occurs For SUBTRACT instructions C 1 No borrow occurs C 0 Borrow occurs For COMPARE instructions Same as SUBTRACT instruction For ROTATION instructions The Carry flag is used as a link between the least significant bit LSB and most significant bit MSB B Overflow V Flag V is set when a two complement overflows occurs as a result of an operation V 1 Overflow occurred V 0 No overflow occurred B Zero Z flag The Z bit 1s set when all the resulting bits are Os Z 1 The result equals zero after operation RI RO 0 when under MAC operation E Negative N Flag The negative flag stores the state of the most significant bit of the outp
27. bit is automatically cleared to 0 and the A D converter enters into Wait state CHS 2 0 000 ADEN TEN ADST lt S H SH 1 1 fat al F AL 1 2 3 4 5 6 7 8 9 0 4 2 3 Al 1 2 DAO j J Software ADIF 7 clear to 0 eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 95 Figure 3 14 ADC Single Mode Timing Diagram Chapter 3 3 6 3 2 Free Run Mode In free run mode A D conversion is performed sequentially for the analog input on a specified channels as follows 1 ADST bit is set to 1 by software 2 When A D conversion is completed the result is sequentially transferred to the A D Data register 3 Every time A D conversion is completed the ADIF flag is set to 1 If at the same time the ADIE bit is also set to 1 an ADIF interrupt request is generated 4 The ADST bit is not automatically cleared to 0 Steps 2 and 3 are repeated as long as the ADST bit remains set at 1 When ADST bit is cleared to 0 A D conversion stops CHS 2 0 j 000 ADEN Ten ie ADST Fi 3 f4 5 6 7 s 9 10 11 2 13 4 71 2 4 6 DAO HM D11 DO
28. can NOT access PB 15 8 that are always high B Port B Control 1 Registers PCON1B PORTB DIR Description Reset Value Rm C MOS input mode C MOS output mode C MOS input mode EE PCON1B 11 10 PCON1B 13 12 PCON1B 15 14 B Port B Control 2 Registers eSL and eSLZ000 only PCON2B PORTB DIR Description Reset Value PCON2B 1 0 00 PCONZB 3 2 9 R W 00 C MOS input mode 00 01 C MOS output mode 00 10 C MOS input mode with 00 with pull up resistor and wake up enable MOS input m i RW pull up resistor PCON2B 9 8 12 11 C MOS input mode with 2 PCON2B 11 10 13 pull up resistor and 00 wake up enable 00 PCON2B 13 12 14 PCON2B 15 14 15 00 130 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 3 11 2 3 Port C eSL and eSLZ000 only B Port C Data ISO PORTC E Bit D Description Reset Value PORTC EZBETE Port C input and output data Register B Port C Control Registers PCONC Bit Description Reset Value C MOS input mode PCONC 0 C MOS output mode 00 C MOS input mode with pull up resistor reserved C MOS input mode PCONC 1 C MOS output mode 00 C MOS input mode with pull up resistor reserved 00 C MOS input mode 01 C MOS output mode PCONC 2 5 4 RW m 10 C MOS input mode with pull up resistor 11 ADC2 input 00 C MOS input mode PCONC 3 7 6 RW 01
29. dep 145 Chapter 6 147 Instruction Set Summary 147 6l Symbol SUMMA y s keina pad GI EE ees 147 GE General Symbol lla tee 147 02 E e E E A E EE 147 LE OI E Um t 148 6 1 4 Flagstatus SR Me rU 148 6 1 4 Operation EE ic urina 148 6 2 Instr ction Set Tables Pc SA 149 0 2 Data inistero 149 6 2 2 Arithmetic Operation Instructions iii 150 6 2 3 Logic Operation INSINICGHONS siii 152 6 2 4 Bit Operation Instead 153 6 2 5 Program Jump Jett 154 Appendix 157 eSL and eSLZ000 Special Function Registers 157 A 1 List of eSL amp eSLZ000 Special Function Registers 157 A 2 List of eSLS Special Function REPIstets rile 159 Appendix 161 Flash Memory Compatibility List 161 A 1 List of eSL amp eSLZ000 Flash Memory Compatibility esses 161 eSL eSLS Series eSLZ000 User s Manual Contents e vii Contents viii e Contents eSL eSLS Series eSLZ000 User s Manual User s Manual Revision History Doc Version Revision Description Official Version Release with following changes e Revised ADC Timing Diagram in Section 3 6 3 e Revised MOV description in Section 4 5 2 1 0 e Add clock system description in Section 2 5 e Add interrupt description in Section 2 8 3 e Revised SPI description in Section 3 4 e Revised Opening Temperature Range in Section 4 1 2 Contents 2006 12 11 Revised Appliation circuits in Section 4 2 2 Add comment in Section 4 3 2 Modified
30. eSL256SA eSL512SA UP to 2 channel speech with different channel sample rate or 1 channel speech 8 channel melody 0 8K 96K bps 8kHz 6KHz 48KHz Speed Pitch Control The product number with an A B C means the chip supports advanced algorithm A series support vocal high compress application B series support vocie recognition SI SD application C series support hand write recognition HWR application For further details refer to the pertinent eSL Series Assembler Reference Guide eSL Series C Macro Reference Guide and related Application note 8 e Introduction eSL eSLS Series eSLZ000 User s Manual En Chapter 1 1 5 Typical Applications Long Duration Speech and Melody Playback Voice Recognition Education Learning Products Recording and Playback Products Intelligent Interactive Talking Toys Caller ID DTMF FSK decoder Power Conversion and Motor Control General Purpose Controller eSL eSLS Series eSLZ000 User s Manual Introduction e 9 Chapter 1 Ve 1 6 Pin Descriptions 1 6 1 Power Supply Refer to Section 2 6 Power Supply Circuit for more detailed information Supported n Name Type Voltage Description VDD_CPU P 3V Positive power supply for CPU digital peripheral and DRAM Positive power supply for PROM DROM and POR eSL and eSLS VDD_PM P 3V only Positive power supply for PRAM and POR eSLZ000 only VDD OSC P 3V Positive power supply for Oscillator syst
31. eSLZ000 eSL032 eSL128 eSL256 eSL512 ni Se NBIC 1 No AIB Program 32K 16 SRAM 32K 16 32K 16 32K 16 32K 16 32K 16 32K 16 32K 16 32K 16 Data RAM 2K 16 2K 16 2K 16 2K 16 2K 16 2K 16 External x e Data ROM Up to 16M 16 32K 16 128K 16 256K 16 512K 16 32K 16 128K 16 256K 16 512K 16 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit 4 8 bit ELES ik 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit sP iset 1set 40 I O ports 8 Output ports Current The product number with an A B C means the chip supports advanced audio algorithm eSL eSLS Series eSLZ000 User s Manual Introduction e 3 Chapter 1 1 3 2 eSLS ICs Parts List and Properties Product No Pin Count Program ROM Data RAM Data ROM Watch Dog Current D A eSL128S 45 32K 16 2K 16 128K 16 4 8 bit Yes 10 bit 12 bit eSL256S 45 32K 16 2K 16 256K 16 4 8 bit Yes 10 bit 12 bit eSL512S eSL128SA 45 45 32K 16 32K 16 2K 16 2K 16 512K 16 128K 16 4 8 bit 4 8 bit Yes Yes 10 bit 10 bit 12 bit 12 bit 24 I O ports eSL256SA 45 32K 16 2K 16 256K 16 4 8 bit Yes 10 bit 12 bit The product number with an A means the chip supports advanced audio algorithm 4 e Introduction eSL512SA 45 32K 16 2K 16 512K 16 4 8 bit Yes 10 bit 12 bit eSL eS
32. is selected by OSCS pin 1 e 0 RC oscillator 1 Crystal oscillator B 32 8 kHz RC oscillator Chapter 2 A IMQ pull up resistor connects to OSCI pin and the OSCO pin should connect to ground B 32768Hz crystal oscillator The crystal connects between OSCI pin and OSCO pin The OSCI and OSCO pins connect to ground through a 20pF capacitor individually Voc R 1M For 32K Osc OSC OSCO 2 RC Oscillator OSCS C OD Y 32 768kHz RC X tal OSC OSCS Pin C Fazk OD OSC i 32 768kHz Fox RC Xtal OSC OSCO i OSCS Pin 1 E 32K Crystal Oscillator OSCS 1 a R 1M b C 10 to 22 pF Figure 2 19 RC X tal Oscillator Block Diagram eSL eSLS Series eSLZ000 User s Manual Architecture e 41 Chapter 2 ps 2 7 2 2 Phase Lock Loops PLL Up F32k gt FPLL Phase Loop detector filter Divide by N Figure 2 20 Phase Lock Loops Block Diagram Frequency Seclect Register FSR is the control register of Phase Locked Loop PLL and Target PLL frequency select register PLL frequency can be fine tuned from 1MHz to 32MHz Fein FSR Fox B The PLL Output Frequency Selections FSR Bit Description Reset Value Fett Frequency MHz selection 0x000 0x01F Not Available 0x020 0x020 Fax 0x021 0x021 F32k 9 0
33. limits and isolate the noise sensitive circuits from the any interference generated by the noisy circuits eSL Series devices provide eight power paths with different requirements such as high speed high current and noise immunity 2 6 1 Power Supply Attributes and Features Supply Feature PANER Applicable to eSL SERE CPU Digital peripherals DRAM Low current High speed eSLZ000 VSS_CPU rs SL IOVDD PWM GPO Port D High drive Output High current pm IOVSS PWM PWM Driver PortA 0 1 I O pad but high noise esLS IOVDD PB is w GPIO Port A and B I O pad General I O Pin eSLZ000 IOVSS PB eSLS IOVDD PC G I I O SL GPIO Port C I O pad Red e IOVSS PC ADC input channel eSLZ000 VDD PM PROM DROM POR esL VSS PM eSL and eSLS Noise immunity eSLZ000 PRAM POR eSLZ000 eSLS sua esL VDD OSC Oscillator system Noise immunity eSLZ000 VSS OSC 32K OSC And PLL High speed eSLS eSL For DAC circuit eSLZ000 esLS AVDD DA AVSS DA AOAN ADC circuit SSL AVSS_AD eSLZ000 VREF MIC circuit eSLZ000 RVIN eSL eSLZ000 eSLS eSL eSLZ000 eSLS Regulator Regulator power eSL eSLS Series eSLZ000 User s Manual Architecture e 39 Chapter 2 En 2 7 Oscillator System The eSL Series oscillator system consists of an F32 RC X tal oscillator internal RC oscillator with a phase locked loop PLL circuit a clock select circuit and system clock dividers The Clock system architecture includes the
34. with programmable high current GPIO lO General purpose input and output function with PA 13 programmable high current MOSI ue SPI function Master output Slave input with programmable high current GPIO lO General purpose input and output function with PA 14 programmable high current MISO lO SPI function Master input Slave output with programmable high current ao ia PA 15 SPI function in Master Mode used as serial clock output and SCK UO as serial clock input in Slave Mode with programmable high current NOT applicable to eSLS ICs 12 e Introduction eSL eSLS Series eSLZ000 User s Manual Chapter 1 1 6 5 2 Port B Attributes and Definitions B For eSL eSLS and eSLZ000 Name Function Type Description YO General purpose input and output function PB 7 0 GPIO I Wake up function with programmable pull up resistor B For eSL and eSLZ000 only Name Function Type Description General purpose input and output function PB 15 8 GPIO Wake up function with programmable pull up resistor 1 6 5 3 Port C Attributes and Definitions eSL and eSLZ000 only Function Type Description General purpose input and output function Input with programmable pull up resistor General purpose input and output function PC 7 2 Input with programmable pull up resistor Analog Input channels eSL eSLS Series eSLZ000 User s Manual In
35. 0 RAW geha Pine 1 0 Pin5 1 0 Pind 1 0 Pin3 1 0 Pin2 1 0 Pint 1 0 Pino 1 0 0x25 0x2F Reserve 0x30 TRLO 0x0000 Rw TRLO 7 0 Ox31 TCONO 0x0000 Rw TENO TCSO 2 0 0x32 TRL 0x0000 RAW TRL1 7 0 0x33 TCON4 0x0000 RAW TEN TCS1 2 0 0x34 TCNT2 0x0000 R TCNT2 7 0 0x35 TCCR2 0x0000 R TCCR2 7 0 0x36 TCON2 0x0000 R TEN2 Tc2 Tompo TM2 TCS2 2 0 0x37 TCNT3 0x0000 RAW TCNT3 7 0 0x38 TCCR3 0x0000 R TCCR3 7 0 0x39 TCON3 0x0000 RW TEN3 Tc3 TIOM3 1 0 TM3 TCS3 2 0 0x3A 0x3D Reserve Ox3E WDTCON 0x0000 Rw WDTEN DEI WDTC WDTPSR 1 0 0x3F RTCCON 0x0000 RW RTCEN RTC WKUP 3 0 RTC3 1 0 RTC2 1 0 RTC 1 0 RTCO 1 0 0x40 0x4F Reserve eSL eSLS Series eSLZ000 User s Manual Instruction Set Summary e 159 Chapter 6 Ve Continued Biti5 Bit14 Bit13 Bit12 Bit11 Bing Bit09 Big Bit07 Bit06 Bit05 Bit04 Bito Bit02 Bit01 Bitoo Register Initial g RIW Address Name value PWMD 0x000U PWMD 15 6 PWMP Ox7FCU PWMP 15 6 PWMCON 0x0000 PWMDEN PWMVOL 1 0 PWMCLR PWM RPT 2 0 PWM MOD PWMOEN 1 0 PWMPS 1 0 DROMD 0x0000 DROM DATA 15 0 DROMLA 0x0000 DROM LA 15 0 DROMHA 0x0000 DROM HA 7 0 DROMCON 0x0000 DROMEN ROM MODE 2 0 DROM DELAY COUNT 4 0 0x57 0x5 Reserve 0x60 DACD 0x0000
36. 000 User s Manual Pz Chapter 3 3 2 2 Real Time Clock Control Register Referring to the above block diagram Figure 3 2 F32x is divided by the divider for RTC clock which F32x value is contingent to the selected external RC X tal oscillator circuit For example if you want to use RTCS3 see table below with clock F32 2 then you need to set 1 Referring to the table below select the divider for RTCS3 clock 1 e Set RTCCON 7 6 01 with 2 as divider 2 Enable RTC set RTCCON 15 1 B The Real Time Clock Control RTCCON Register Attributes and Resources RTCCON IR Description W i D RTC enable disable RTCEN 15 R 0 Disable 1 Enable roueg 8 RW 1 RTOS enable wakeup 0 isane Fs2K divided by divider for RTCS3 clock 00 1 1 32 kHz RTCS3 7 6 01 1 2 16 kHz 10 1 4 8 kHz RTCS2 5 4 RTCS1 3 2 RTCSO 1 0 11 1 8 4 kHz 00 1 16 2 kHz eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 67 01 1 32 1 kHz 10 1 64 512 Hz Di Fa2k divided by divider for RTCS2 11 1 128 256 Hz RW F32k divided by divider for RTCS1 00 1 256 128 Hz RW 01 1 512 64 Hz 10 1 1K 32 Hz 11 1 2K 16 Hz F32K divided by divider for RTCSO 00 1 4K 8 Hz RW 01 1 8K 4 Hz 10 1 16K 2 Hz 11 1 32K 1 Hz Chapter 3 3 2 3 RTC Timing RTCO 3 Timer interrupts are invoked by rising edge of RTC clock RTC Timer wake up are invoked by risi
37. 000 User s Manual Instruction Set Summary e 153 Chapter 6 6 2 5 Program Jump Instructions Function Algebra Assembly Operation wic d d z v c yntax 1 SP 1 2 SP CALL Rd 2 PC 1 gt TOS CALL 3 Rd PC CALL Long ada Cal absouteaaaress 22 on Sh ar Poems F 12 1 Return from subroutine 1 2 RETI RETI Return from interrupt 1 2 RPT Rn Repeat next inst Rn 1 aa times RPT imm6 Repeat next inst M ES a times ROC Do loop to ENDL Rn 1 5 5 ENDL times LOOP imme Do loop to ENDL m ENDL imm6 1 times Lem ese ri me umPiongadr rono arse 22 IMP short aar RER EUR IF CS JMP L dd dun 2 2 ong_aadr Long_add gt PC IF CS JMP Short_addr er 1 1 2 PC 1 Offset gt PC oi If C 0 If C 0 2 IF CC JMP Short addr Ge 4 1 2 PRERE IF VS JMP L dd ee 2 2 ong acar Long_addr gt PC If V 1 2 IF VS JMP Short_addr lari 1 12 FEREE If V 0 IF VC JMP Long addr peu 2 2 If V 0 2 IF VC JMP Short addr ict 1 12 IF MI JMP L dd IAS 2 2 ong acer Long addr gt PC IF MI JMP Short add NM 1127 oraga PC 1 Offset gt PC 2 i These multi cycle instructions Word Cycle 1 2 1 become a single cycle instructions after the first iteration of a repeat RPT instruction The short jump instruction 1 1 2 needs two cycles if jump is carried out and one cycle is needed if no jump is carried out 154 e Instruction Set Summary eSL eSLS Series eSLZ000 User s Manual Chapter 6
38. 2 3 6 Modified mov instruction in Section 2 5 4 1 Added PortC DC characteristic in Section 4 1 3 1 4 2008 01 10 Modify LSA LEA initlal value in Appendix Modify Application Circuit diagram in Section 5 Added EXINT wake up comment in Section 2 11 1 5 Added FSR change comment in Section2 7 2 Add Regulator comment in Section 3 12 Added flash memory support table in Appendix Modified Algorithm support in Section 1 2 and 1 3 2008 10 15 eSL eSLS Series eSLZ000 User s Manual Contents e ix Contents Modified Regulator comment in Section 3 12 and Section 5 Modify WDT example in Section 3 1 3 1 6 Modify Definition of TCNT2 and TCNT3 in Appendix A 2009 04 15 Added Algorithm related section in Section 1 4 Modify DROM example code in Section 3 7 4 Modify PC 7 0 pull up resister in Section 4 3 1 Added ADC convertion time in Section 3 6 2 eee Added ADC enable timing in Section 3 6 2 US x e Contents eSL eSLS Series eSLZ000 User s Manual Contents eSL eSLS Series eSLZ000 User s Manual Contents e xi En Chapter 1 Chapter 1 Introduction 1 1 Introduction to eSL eSLS Series and eSLZ000 ICs The eSL eSLS Series and eSLZ000 ICs or eSL Series for short differ from each other in the following manner B eSL ICs fully comply with all features of the eSL Series B eSLS ICs isthe simplified version of the eSL ICs Hence these chips have simpler performance t
39. ADEND internal signal le Software ADIF i clear to 0 Figure 3 15 ADC Free Run Mode Timing Diagram 96 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 3 6 4 Examples Set ADC Single mode from Channel 0 and output the read data to PORTA DATA BUF PD DS CODE POWERON RO 0 BUF PD RO Clear data buffer BS IO SR GIE GIE active BS IO INTE1 ADIE ADC Interrupt active AD_ON Enable ADEN RO 64 RPT RO NOP AD SINGLE 0 3 Set ADC Single mode ch0 clk FPLL 64 _ADC WAIT NOP NOP NOP Wait ADC interrupt BTEST BUF PD 0 Check ADC conver end IF TC JMP_ADC WAIT RO BUF PD ADC trans OK Read data IO PORTA RO Out read data to PORT A Lr BC IO SR GIl BC IO INTE1 ADI Disable GIE Disable ADC Interrupt Lr AD OFF ADC OFF Delay Main loop JMP Delay ADC interrupt function ADCINT PUSH IO LIB BSR PUSH IO LIB SR PUSH AD READ ADC trans OK read date to RO BS R0 0 Set Flag BUF PD RO L Save to data bufer POP RO POP IO LIB SR POP IO LIB BSR eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 97 Chapter 3 BC IO INTF1 ADIF 98 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Chapter 3 PORTD DATA TP RAM D
40. AL FUNCTION REGISTER SFR Note means Register Notation Figure 2 13 ELAN eSL Series Register Organization eSL eSLS Series eSLZ000 User s Manual Architecture e 25 Chapter 2 En 2 4 1 General Purpose Registers Register space consists of 8 x 16 bit General Purposes Registers They are used as data address or offset registers They can address up to 64 K addressing space ROM RAM without any segmentation bank In addition to their general usage the Registers RO and R1 have some other functions These two registers are treated as a single double word 32 bit accumulator called Accumulator D that hold operands and results of the arithmetic calculations or data manipulations such as division and multiplication 2 4 2 Program Counter PC The Program Counter is a 16 bit wide register that holds the address of the next instruction to be executed Therefore the PC can address up to 64K instruction words Read only 2 4 3 Stack Pointer SP The Stack Pointer holds the 16 bit address of the last used stack location and is automatically modified by interrupt processing subroutine calls and returns You may reprogram the SP during initialization to any location within data RAM space The SP also can be used by in the user software PUSH and POP instructions but you should remember that the CPU also uses the SP 2 4 4 Repeat and Loop Registers These Repeat and Loop Registers actually
41. C MOS output mode ep 10 C MOS input mode with pull up resistor 11 ADC3 input C MOS input mode PCONC 4 9 8 RW C MOS output mode l l C MOS input mode with pull up resistor ADC4 input C MOS input mode PCONC 5 11 10 RAW EMOS Uma C MOS input mode with pull up resistor ADC5 input C MOS input mode PCONC 6 13 12 RW a MO Soup eae C MOS input mode with pull up resistor ADC6 input C MOS input mode PCONC 7 15 14 RAW EE l C MOS input mode with pull up resistor ADC7 input eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 131 Chapter 3 En 3 11 2 4 Port D eSL and eSLZ000 only B Port D Data Register PORTD Bit DIR Description Reset Value PORTD 7 0 Port D output data Register 0x00 B Port D Output Delay Register PCOND Bit DIR Description Reset Value 0 Without delay mnm mum E 3 11 3 Input Mode with Pull Up Resistor Delay Time The data rise time in input mode with pull up resistor is 1 1us For example the input data is ready to access after 16 cycles in 16MHz without frequency division as shown in the folowing example RO FOXAAAA IO PCON1B RO IO PCON2B RO RPT 16 NOP Ri IO PORTB 3 11 4 I O Port Application Examples a Bad design b Good design Figure 3 25a I O Port Driving an LED 132 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual En Chapter 3
42. Chapter 3 3 3 2 4 Timer 2 3 Operation The Timer 2 3 have two operating modes namely Capture mode and Compare mode Timer Counter TCNT can be cleared by compare match or by timer counter clear bit setting Furthermore it can be cleared by an external reset signal as well Ifthe count disable function is selected the counter is halted B Capture Mode Operation In Capture mode the timer can perform capture operation i e the Timer Counter TCNT value is captured into Capture register TCCR when an event trigger occurs on pin TCCP Capture can take place at rising edge falling edge or at both edges With the Capture function you can measure the time difference between external events If a valid trigger signal on the pin does not occur before overflow an overflow interrupt will be generated and the counter value is counted from 00h again If another Capture occurs before the TCCR register value is read the previous captured value will be lost TCCP has wake up functionality in GREEN and SLEEP modes Set Timer Overflow Interrupt Flag TVIFx Set Timer Clock 8 bit Timer Counter Interrupt source p From TCCPx TCNTx Flag TIFx Timer Capture Compare Register TCCRx x is the timer number 2 3 Figure 3 7a Capture Mode Operation Block Diagram 76 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual The Capture Timing diagram at right shows an example of a buf
43. Chapter 3 wo SPR SPI clock rate selection 3 bits SPR is used to set the bit transfer rate for a master device Note that if the SPI is configured as a slave the eSL slave SPI system frequency must be at least greater than eight times the master SPI serial clock frequency 3 8 4 5 SPI Status Register SPISR B SPI Status Register Attributes and Definitions Description Reset Value TDBR status flag TXS 2 R 0 TDBR is empty 0 1 TDBR is full Transfer complete flag TCF 0 R 0 Transfer is completed 0 1 Transfer is not completed TXS TDBR status flag The transmit buffer becomes full TXS 1 after it is written into It becomes empty TXS 0 when data transfer begins and the transmitted value is loaded into the Shift register H W set S W cleared TCF transfer complete flag The SPI hardware clears this bit to indicate that it has completed sending or receiving the last bit of data and is ready for the next task The received data is placed in the RDBR and this bit is cleared at the same time H W set H W cleared This flag causes an interrupt to be requested if the SPI interrupt is enabled Refer to Section 2 10 3 4 Interrupt Flag Register 0 INTFO for more details 3 8 5 SPI Transfer Format The SPI supports four different combinations of serial clock phase and polarity The user application code can select any of these combinations using the CPOL and CPHA bits in the Control register The clock po
44. D 2 PWM1 Max volume VDD 3V PWM output low current PMO IPWML VOL VDD 2 PWM1 Max volume DAC output current DACO IDAC VDD 2 2 3 3V Regulat isuttich RVIN 4 5V STESO RVOUT IOUTH RVOUT 3 0V current Fast Slow mode RVIN 4 5V Regulator output low RVOUT 3 0V RVOUT IOUTL current GREEN SLEEP mode Fast mode current VDD 3V consumption increment IFAST No load per MHz DAC off VDD 3V See ders SEN ISLOW No load ae DAC off consumption VDD 3V Regulat id Sleep mode current ISLEEP egulator on consumption VDD 3V Regulator off CPU operation frequency EEN Fsys VDD 3V eSL eSLS Series eSLZ000 User s Manual Chapter 4 Rated Value Min Soa je EF F Refer to Section 3 12 Voltage Regulator 5V 3V for details Electrical Characteristics e 141 Chapter 4 142 e Electrical Characteristics eSL eSLS Series eSLZ000 User s Manual Chapter 5 Chapter 5 Application Circuits 5 1 eSL Application Circuit Showing A D D A using BJT SPI Crystal OSC touch panel and PWM suppoting 4 5V VCC 4 5V R1 0 100hm 4 ES e BM BEAD i AVEC_IV T BATTERY AVCC 3V NA For PWM drive C12 c11 Dip Ls1 PAO Ext RESET PA Q 05 E zm lt o oa 2 D SPEAKER d a g99 8 o RSTB a a gQaa amp o9 A z BOB 9 oscs For
45. DACD 15 4 0x61 DACCON 0x0007 DAC2SC DACMOD 1 0 DACVOL 2 0 0x62 0x6F Reserve NOTE u under Initial Value column are unknown values 160 e Instruction Set Summary eSL eSLS Series eSLZ000 User s Manual Appendix Flash Memory Compatibility List A 1 List of eSL amp eSLZ000 Flash Memory Compatibility SPI flash Serial Vendor Part number Capacity PM25LV512 512K Bit PM25LV010 MX25L512 512K Bit MX25L4005 4M Bit MX25L1605 16M Bit MX25L3205 NOR flash Parallel 32M Bit 64M Bit Winbond NEX 512K Bit Part number EN29LV160 EON EN29LV800B 512K 16 MX29LV640BT B 8M 16 MXIC MX29LV160AT AB 1M 16 MX29LV800CT CB 512K 16 MBM29DL32XTE AMD AM29DL16xD AM29DL800B Vendor Capacity 512K 16 eSL eSLS Series eSLZ000 User s Manual Special Function Registers e 161
46. F2 TEN2 15 When TM2 1 Capture 00 Input capture at rising edge of the TCCP pin 01 Input capture at falling edge of the TCCP pin 1X Input capture at rising and falling edges of the TCCP pin Selects TCCR function 0 TCCR functions as an output compare register 1 TCCR functions as an input capture register Fei 256 Feu 512 E Fei 1024 H Fei 12048 Feu 4096 TEXI2 rising edge TEXI2 falling edge F32k OSC eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 81 Chapter 3 Ve B Timer 3 Capture and Compare TCCR3 Registers Attributes and Definitions TCCR3 Bit DIR Description TCCR3 7 0 RW Timer 3 Capture and Compare Registers 0x00 B Timer 3 Counter TCNT3 Registers Attributes and Definitions TCNTS Bit DIR Description TCNT3 7 0 oR Timer 3 Counter Registers B Timer 3 Control TCON3 Registers Attributes and Attributes and JE TCON3 Bit j Description Timer Enable this bit enables or disables Timer function 0 Disable Stop 1 Enable Start Timer counter clear TCNT 0 Not effect 1 Clear TCNT If TM3 0 Compare 00 No output at compare match TIF3 01 Output toggles to the TCCP pin and reset TCNT at TCCR compare match TIF3 10 Output toggles to the TCCP pin at TCCR compare match TIF3 TVIF3 11 Output simple PWM to the TCCP pin at TCCR compare match TIF3 TVIF3 15 If TM3 1 Capture 00 Inp
47. Gi D UF PD RO L POP RO POP IO LIB SR POP IO LIB BSR BC IO INTF1 ADIF RETI TA ADC interrupt Set MIC input with ADC Channel 5 PC5 set portc 5 ADC input GIE active ADC Interrupt active MIC ON AGC ON Gain 3 Set DAC Un Sign mode always pass mode vol 3mA max Set ADC Single mode FPLL 16 ch5 clki Wait ADC interrupt ADC trans OK Read data Out read data to PORT A Out data to DAC Main loop function ADC trans OK read date to RO Set Flag Save to data buffer 122 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 3 10 I O Pad Architecture Direction Remarks PORTB 15 8 IN OUT Se Babee ced 15 8 eSL and eSLZ000 only PORTC 7 0 IN OUT eee Fee 7 0 eSL and eSLZ000 only See Figure 3 24f PORTOLI eSL and eSLZ000 only WEB RDB CEB See Figure 3 24f TDO DROMA 23 0 eSLZ000 only See Figure 3 24g DROMD 15 0 IN OUT eSLZ000 only See Figure 3 24a TDI TCK TMS IN eSLZ000 only See Figure 3 24h RIA IN eSL and eSLZ000 only OSCS IN See Figure 3 24i WEB TDO BTCS OUT See Figure 3 24j BTSCLK BTSO eSLZ000 only See Figure 3 24k DROMD 15 0 IN OUT eSLZ000 only di PORTC 7 2 shares pin with ADC input no Schmitt Trigger Input when input from PORTC 7 2 SW must prohibit ADC enable when PORTC connect to 5V power eSL eSLS Series eSLZ000 User s Manual Peri
48. JMP Short add TRAC Jo 1 ora PC 1 Offset gt PC 1 PC 1 2 TOS 2 SP 1 gt SP TRAP imm6 3 imm6 vector number 2 gt PC 4 GIE gt 0 NOP No operation These multi cycle instructions Word Cycle 1 2 1 become a single cycle instructions after the first iteration of a repeat RPT instruction The short jump instruction 1 1 2 needs two cycles if jump is carried out and one cycle is needed if no jump is carried out 156 e Instruction Set Summary eSL eSLS Series eSLZ000 User s Manual Pz Chapter 6 Appendix eSL and eSLZ000 Special Function Registers A 1 List ofeSL amp eSLZ000 Special Function Registers Address Register Name Initial value R W Bit15 Bit14 Bit13 Bit12 Bit11 Bit07 Bito6 Bit04 Bit03 Bit02 Bit01 Bit00 0x00 SR 0x0000 R W GIE SME S6R F I T N Z V C 0x01 BSR 0x0000 R W BSR 7 0 0x02 CPUCON 0x0000 R W SLT SW_RST WUPS 1 0 SCS 1 0 SMC 2 0 0x03 0x05 Reserve 0x06 PORTA 0x0000 R W PORTA 15 0 0x07 PORTB 0x0000 RW PORTB 15 0 0x08 0x0000 PORTD 7 0 0x09 0x0000 DROMIF PWMPIF PWMDIF RTCIF3 RTCIF2 RTCIF1 RTCIFO EXINTIF1 TVIF2 TIF2 TIFO Ox0A 0x0000 PDTIF SPLIMIF 0x0B DC 0x0000 DROMIE PWMPIE PWMDIE RTCIE3 RTCIE2 RTCIE1 RTCIEO EXINTIE1
49. LS Series eSLZ000 User s Manual Pz Chapter 1 1 3 3 Properties Comparison between eSLZ000 eSL and eSLS ICs Product No eSLZ000 JTAG ICE Yes No Boot SPI Yes No oa 8 4 4 PortA 12 15 ADC Yes No eSL eSLS Series eSLZ000 User s Manual Introduction e 5 Chapter 1 fm 1 4 Algorithm Selection Table The ELAN eSL Series algorithm feature Built in software voice synthesizer 0 8K 96Kbps 8kHz Multiple flash with volume level option Control port output value directly by waveform waveform control port Support mark number in waveform with ROM optimized configuation Up to 2 channel speech with different channel sample rate or 1 channel speech 8 channel melody Voice recording in 12 16 20 and 32 Kbps 8KHz Support beat tracking function to detect music tempo Support speed control to adjust playback speed Support pitch control to change voice pitch Support sound source detection function to detect the angle of sound position Support speaker dependent recognition to recognize voice command amp control function which is dependent on speaker Support speaker independent recognition to recognize voice command amp control function which is independent on speaker Support handwriting recognition engine to recognize characters numeral symbols and gestures 1 4 1 eSLZ000 and eSL ICs Parts List and Properties Product No eSL032 eSL128 eSL256 eSL512 Audio Up to 2 channel spe
50. MIC AGC front end 3 6 2 Registers Start A D conversion is set with ADST bit In Single mode ADST bit is cleared to 0 automatically when conversion on the specified channel is completed In Free Run mode conversion continues sequentially on the specified channels until this bit is cleared to 0 by software by a reset or by a transition to Standby mode eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 93 Chapter 3 En B ADC Control Ww Register Attributes and Definitions ADCON Bit DIR Description Reset Value A D Enable this bit determines the ADEN 15 PDTWK 11 enable disable state of ADC 0 No operation Power down PDTEN 10 1 A D circuit enabled Touch panel pen down detection wake up enable disable 0 Disable 1 Enable Touch panel pen down detection enable disable 0 Disable 1 Enable Switch ON Touch panel function enable disable 0 Disable 1 Enable Analog Input Channel Select this field determines the channel of analog input 000 ADINO TPEN 1 XP 001 ADIN1 TPEN 1 YP 010 ADIN2 011 ADIN3 100 ADIN4 101 ADIN5 110 ADING 111 ADIN7 AD mode 0 Single mode 1 Free run mode 94 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual A D conversion state 0 conversion on the specified channel is completed 1 starts A D conversion Single or differential mode selection this bit 8 is active only when TPEN
51. O SCK and SS All four pins can be used as GPIO if the SPI module is disabled SPIEN 0 B Two operational modes Master and Slave B Baud rate 8 different programmable baud rates B Data Word length 8 or 16 bits Data must be left aligned when written to the transmit buffer register Data read back from receive buffer register is right aligned B Full duplex Simultaneous receive and transmit operation B Clocking 4 programmable clocking schemes B Interrupt polling Transmit and receive operations are accomplished by either interrupt driven or polling B SPI boot flash interface and SPI data flash interface The eSLZ000 supports both SPI boot flash and SPI data flash while eSL only supports SPI data flash see their respective Application Circuits in Chapter 5 B SPI wake up In SPI slave mode SCK has wake up functionality in GREEN and SLEEP modes 104 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual B SPI Attributes and Definitions Resource Fsys SPIF Master Slave Wakeup Clock source Usage register Interrupt sources VO function pin Operation mode eSL eSLS Series eSLZ000 User s Manual Chapter 3 Peripheral Control e 105 Chapter 3 Ve 3 8 2 Block Diagram TDBR SI MSB Transmit Data SFDR Buffer Register SS Shift Data Register RDBR SO Serial LSB Receive Data Control Buffer
52. O t d PER Wakeup Wakeup 3 3 2 2 Features B Selection of internal and external clock sources Timer 2 3 W Two interrupt sources 1 Counter overflow 2 Compare is matched or timer capture occurs B Capture mode Record Timer at a specified event Rising falling or at both edges B Compare mode Interval operation or change I O periodically B Generate simple PWM waveform Drive electronic machines by switching a power amplifier on and off Timer 2 3 Mm 16 bit timer available Timer 2 3 combination MSB Timer3 LSB Timer2 74 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual 3 3 2 3 Block Diagram Chapter 3 Set Timer Overflow Interrupt Flag bit TVIFx Set Timer Interrupt Flag bit TIFx Capture OR Compare Timer Capture Compare Register TCCRx Figure 3 6 Timer2 3 Function Block Diagram Where Prescaler The prescaler is a 12 stage divider chain providing frequencies based on the CLK input Each set of timers uses the same prescaler as its clock source TCNT Register is an 8 bit timer counter that increments each time a clock pulse is input TCCR Register Timer capture or compare register use for different operation modes Timer Overflow Interrupt Flag TVIF is set when Counter overflows Timer Interrupt Flag TIF is set when compare is matched or timer capture occurs eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 75
53. OAD or from register to memory STORE IN and OUT instructions are capable of moving data via I O space while PUSH and POP instructions provide a channel between register and stack or I O and stack There are two kind data memory mov instruction one is 8 bit mov instruction user need to set BSR and 8 bit direct address to do the mov operation the other is 16 bit long mov instruction user just need to set 16 bit direct address Please see the instruction table to understand the performance and space between this two instructions 2 5 4 2 Data Transfer Addressing Categories As the eSL Series architecture are register based the chips are powerful in moving data from register to any space as demonstrated in the following table RAM Indirect ROM Indirect UO Space Stack Register RAM Direct with Inc Dec with Inc Dec IN OUT PUSH POP Immediate Available Available Available Available Available Available Available RAM Indirect Available Available Available UO Space Available Stack Available eSL eSLS Series eSLZ000 User s Manual Architecture e 33 Chapter 2 Ve 2 5 4 3 Data Transfer Programming Examples Syntax Description Rd Rs Rs Register gt Rd Register Rd P Rs ROM address Rs gt Rd Register then Rs Rs 1 Rd Rs Rs Register gt RAM address Rd Rn 0x5a Load imm8 gt Rd l 05 Rd h Rn h 0xa5 Load imm8 gt
54. OF RO BS IO SR GII 0x0080 RO RLO RO 0x8007 IO TCONO R0 Lr BS IO INTEO TIE Delay JMP Delay R BC IO INTFO TIFO POP IO SR RETI Set Timer0 to count and output a include interruptvector def POWERON RO IO PORTA Timer0 interrupt function TimerOINT PUSH IO SI BTG IO POI square waveform to PORTA7 Set PORTA7 output Set timer0 reload value Enable timer0 clock source Fpll 4096 Enable GIE Enable timer0 interrupt Main loop RTA 7 PORTA7 Toggle output plus wide 1 16384000 4096 0x0F 1 4ms eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 73 Chapter 3 3 3 2 Timer 2 3 3 3 2 1 Multifunction Timer Timer 2 and Timer3 are 8 bit multifunction timers operating in Capture and Compare modes Each timer is independent from each other with unique counting rates and operation modes These two 8 bit timers can be combined to form a multifunction 16 bit timer used for counting events counting time measuring frequency capture function and generating analog like outputs PWM B Timer2 amp Timer3 Attributes and Resources Item Timer 2 Timer 3 Clock source Feit TEXI2 F32k Fert TEXI3 TVIF2 Usage register TCNT2 TCCR2 TCON2 TCNT3 TCCR3 TCON3 Interrupt sources TIF2 TVIF2 TIF3 TVIF3 I O function pin TEXI2 TCCP2 TEXI3 TCCP3 Capture Compare Capture Compare
55. OSCO in Section 2 7 2 1 Add comment in Selection table in Section 1 3 1 Modified Boot SPI in Section 1 3 3 1 1 Add RTC timing information in Section 3 2 Modified interrupt vector address width in Section 2 10 3 Modified description and figure in Section 2 12 Modified layout hierarchy in Section 4 Modified the Sampleing Rate Range in Section 1 3 1 Added the IOVDD IOVSS AVDD AVSS in Section 1 5 1 2007 03 26 Modified long MOV instruction description in Section 6 2 1 Modified DROM code example in Section 3 7 4 Added eSL032 Modified SPI transmitter receiver only in Section 3 8 7 and 3 8 8 Modified the Temperature Range in Section 4 2 Modified the Power supply voltage in Section 4 3 1 Modified the example in Section 3 6 4 and 3 5 5 Modified the IP attributes and definiations in Section 3 Added algorithm support such as beat tracking sound location speech control pitch control in Section 1 2 and 1 3 Added the note about power optimization in Section 2 9 2 and 3 4 4 Added ADC input resistance and capacitance in Section 3 6 1 2 2007 08 10 Added package information in Section 1 3 Modified PWMP and PWMD initial value in Section 3 4 4 Modified Application Circuit in Section 5 Modified Figure number in Section 3 10 1 3 2007 11 10 SPI serial clock consideration in Section 3 8 3 1 and 3 8 8 Modified PWM current in Section 4 3 Modified BSR description in Section 2 2 2 Modified data direct address mode in Section
56. OV instruction When user use 8 bit MOV instruction they must make sure the BSR is correct User doesn t care the BSR if they use 16 bit MOV instruction L Please see the data transfer instruction and appendix about code optimization eSL eSLS Series eSLZ000 User s Manual Architecture e 19 Chapter 2 2 3 Addressing Modes fm ELAN eSL Series supports powerful and efficient addressing modes A lot of instructions use several addressing modes The following sections will describe the available eSL Series addressing modes 2 3 1 Register Direct Addressing The operands are in the register file Example R1 R2 R3 General Purpose Registers OP Rd Rs Rt RO R7 Figure 2 4 Register Direct Addressing 2 3 2 Register Indirect Addressing Operand address is the contents of the registers used when accessing the RAM or ROM Example R3 R2 RI B and R3 P R1 General Purpose Register ROM RAM Space 65535 Figure 2 5 Register Indirect Addressing 20 e Architecture eSL eSLS Series eSLZ000 User s Manual En Chapter 2 2 3 3 Indirect Addressing with Post Decrement The indirect register pointer is decremented by 1 after operation Example R3 R5 and D R5 R6 US ROM RAM Space m Gen
57. Operator Equal Operator Direction Move Operator and swap respectively Repeat Counter Program Counter Top of Stack 148 e Instruction Set Summary Global Interrupt Enable flag eSL eSLS Series eSLZ000 User s Manual En 6 2 Instruction Set Tables Chapter 6 6 2 1 Data Transfer Instructions Function Rd Rs Rd Rs Algebra Assembly Syntax Operation Rs gt Rd Rs gt Rd Rd Rs Rd Rs Rd P Rs Rd P Rs Rd P Rs Rd P Rs Rd P Rs Rd P Rs Rs gt Rd Rs gt Rd P Rs gt Rd P Rs gt Rd P Rs gt Rd P Rs gt Rd P Rs gt Rd P Rs gt Rd Rd P Rs Rd P Rs Rd P Rs Rd Rs Rd Rs Rd Rs Rd RAM16 L RAM16 Rs L MOV P Rs gt Rd P Rs 2 Rd P Rs 2 Rd Rs 2 Rd Rs 2 Rd Rs gt Rd addr16 gt Rd Rs addr16 Rd imm16 Rd imm16 Rd l imm8 Rd h imm8 Rd RAM8 RAM8 Rs Rd R3 imm6 Rd R3 Rt imm16 gt Rd imm16 gt Rd imm8 gt Rd I 0 gt Rh imm8 gt Rd h addr8 gt Rd Rs gt addr8 1 1 R3 imm6 gt Rd R3 imm6 Rs R3 Rt Rs Rd IO Addr OUT IO Addr Rs Rs gt R3 Rt IO Addr gt Rd Rs gt IO Addr Rn2 TOS SP 1 gt SP PUSH Rn PUSH PUSH IO Add POP Rn POP IO Addr SP SP SP imm6 SP SP SP im
58. PIF 1 when the PWMCNT and PWMP compare match occurs and the PWMRPT underflows eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 85 Chapter 3 En 3 4 3 1 Left Edge Aligned PWM Left edge aligned PWM signals are produced by the module when the PWM time base is in the Free Running or Single Shot mode The left edge aligned output for a given PWM channel has a period specified by the value loaded in PWMP and a duty cycle specified by the appropriate duty cycle register see top figure of Figure 3 10 below 3 4 3 2 Center Aligned PWM Center aligned PWM signals are produced by the module when the PWM time base is configured in an Up Down Counting mode These signals have twice the period of left edge aligned PWM as illustrated at the bottom of the following figure PWM Interrupt Flag is set PWM Interrupt Flag is set PWM Interrupt Flag is set PWMP Value PWND Value Ps PWMPO Output a Lefi Edge Aligned PWM PWM Interrupt Flag is set PWM Interrupt Flag is set PWMP Value E A ed i Ac PWMD Value Le PWMPO Output b Center Aligned PWM Figure 3 11 PWM Output Waveforms Showing Alignment Setting as Left or Center 3 4 3 3 Single Ended PWM Single ended PWM is a method of reproducing waveform in audio applications It has a low power consumption but provides a higher resolution The MSB is a signed bit and its negative number is of 1 compl
59. PU Control Register for wake up time selection E The External Interrupt Attributes and Resources Item LI Resource Usage register EICON Interrupt sources EXINTIFO EXINTIF1 I O function pin EXINTO EXINT1 Operation made Rising edge Falling edge Low level Both edge Wakeup 2 11 1 External Interrupt Control Register B The External Interrupt Control Register Attributes and Definitions EICON Bit 3 Description 00 Rising edge triggered 1 0 RW 01 Falling edge triggered 10 Low level interrupt EXINTO 11 Both edge triggered EXINTO Wake up Enable Control 2 RW 0 Wake up Disable 1 Wake up Enable 00 Rising edge triggered 01 Falling edge triggered Pali BON 10 Low level interrupt EXINT1 11 Both edge triggered EXINT1 Wake up Enable Control 5 R W 0 Wake up Disable 1 Wake up Enable eSL eSLS Series eSLZ000 User s Manual Architecture e 57 Chapter 2 2 11 2 Application Examples The diagram below illustrates the external interrupt functionality The rising edge trigger function is shown in a falling edge trigger in b low level interrupt in c and both edge trigger in d Cleared by software EXINTIF 0 1 PortA 10 11 a Cleared by software EXINTIF 0 1 PortA 10 11 b Cleared by software EXINTIF 0 1 PortA 10 11 c Cleared by software Cleared by software EXINTIF 0 1 PortA 10 11 Figure 2 26 External Interrupt Function Diagram 58 e Architec
60. Register SCK DATA BUS Serial Clock Generator Figure 3 17 SPI Block Diagram 3 8 3 Pin Description SCK MOSI Miso PSE Device SS eSL series Slave device Flash memory eSL series Figure 3 18 SPI System Master amp Slave Device Block Diagram B SPI Pin Attributes and Definitions Description Serial clock out master mode Serial clock in slave mode Serial data out master mode MOSI VO Z Serial data in slave mode Serial data in master mode MIS VO Z Serial data out slave mode GPIO master mode ISS O Slave select input slave mode 106 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual En Chapter 3 3 8 3 1 Serial Clock SCK SCK is the Serial Peripheral Interface clock signal This control signal is driven by the master and controls the rate at which data is transferred The master may transmit data at a variety of clock rates SCK will cycle once for each bit that is transmitted It is an output signal if the device is configured as a master or it is an input signal if the device is configured as a slave The clock rate is selected by the SPI clock rate selects Bit SPR 2 0 in the SPICON of the master device The data is always shifted out at one edge of the clock and sampled at the opposite edge of the clock Clock polarity and clock phase relative to data are programmed into the SPICON control register and d
61. S 6 CODE POWERON TPAD INIT TP_RAM BS IO SR GII R7 0x02 DG TouchPad read R2 R2 OR 40x00 CMP R2 R7 TouchPad Out SWAP RO IO PORTC RO SWAP RI IO PORTD R1 SLEEP Mode SLEEPMODE PDTINT NOP PUSH IO SR PUSH RO PUSH R1 TPAD PDTINT 3 1 Set touchpad to enable POP R1 POP RO POP IO SR RETI and read X Y axis data to PORTC and Hold 6 word memory for touchpad macro Touch Padinitial EnableInterrupt Touch Pad No Touch response code TPAD ON 10 10 TP RAM Touch Pad Read end response code IF EQ JMP TouchPad Out Touch Pad No Touch response code IF EQ JMP SLEEP Mode JMP TouchPad read TP out data to IO port Out X axis B15 B8 Out Y axis B15 B8 Go into sleep mode TouchPad interrupt function TP RAM to Seet to PortD eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 99 Chapter 3 3 7 Data ROM ELAN eSL Series support data ROM for speech melody and user data storage It can work under very low supply voltage for low power consumption The eSL Series also provide data ROM delay to handle different access timing for different ROM sizes see Section 1 3 Parts List and Properties for the detailed ROM size data for each of the eSL Series chips 3 7 1 Features e Re
62. SHR ASR COM NEG Algebra Assembly Syntax Rd Rs AND Rt Rd Rs AND Rt Rd Rs AND Rt Rd Rd AND imm6 Operation Rs amp Rt gt Rd Rs amp Rt gt Rd Rs amp Rt gt Rd Rd amp imm6 gt Rd we TIN Z V c wv rir v Ee v FEIT x Rd Rs AND imm16 Rs amp imm16 gt Rd 1 1 2 2 SWAP Rd Rs AND imm16 Rs amp imm16 gt Rd 2 2 Rd Rs AND RAM16 Rs amp addr16 gt Rd 2 2 Rd Rs OR Rt Rs Rt 2 Rd 4A f Rd Rs OR Rt Rs Rt gt Rd 11 l Rd Rs OR Rt Rs Rt gt Rd 11 Rd Rd OR imm6 Rd imm6 gt Rd AH l Rd Rs OR imm16 Rs imm16 gt Rd 2 2 Rd Rs OR imm16 Rs imm16 gt Rd 2 2 Rd Rs OR RAM16 Rs addr16 gt Rd 2 2 Rd Rs XOR Rt Rs Rt gt Rd 11 Rd Rs XOR Rt Rs Rt gt Rd 41 Rd Rs XOR Rt Rs ARt gt Rd 1 l Rd Rd XOR imm6 Rd imm6 gt Rd 11 l Rd Rs XOR imm16 Rs imm16 gt Rd 2 2 Rd Rs XOR imm16 Rs imm16 gt Rd 2 2 Rd Rs XOR RAM16 Rs addr16 gt Rd 2 2 Rd ROL Rs Rd SHL Rs Rd ROR Rs Rd SHR Rs Rd ASR Rs Rd COM Rs Rd NEG Rs SWAP Rs 152 e Instruction Set Summary 1 Rs gt Rd 2 C gt Rd 0 Rd 14 0 2 Rq 15 1 Rd 15 2C 1 Rs gt Rd 2 02 Rd 0 Rd 14 0 2 Rq 15 1 Rd 15 2 C 1 Rs gt Rd 2 C gt Rd 15 Rd 15 1 gt Rd 14 0 Rd 0 2C 1 Rs gt Rd 2 02 Rd 15 Rd 15 1 2 Rd 14 0 Rd 0 2 C 1 Rs gt Rd 2 R
63. SL eSLS Series eSLZ000 User s Manual En Chapter 3 3 10 1 9 CMOS Schmitt Trigger Input Pads PAD xe Figure 3 24i Trigger Input Pad 3 10 1 10 CMOS Input Only Pads PAD XD Figure 3 24j Trigger Input Pad 3 10 1 11 CMOS Input Output Pads PAD Figure 3 24k Input Output Pads eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 127 Chapter 3 Ve 3 11 General Purpose Input Output 3 11 1 Features Pin Function I O Configuration PA 7 0 A GPIO Where DI Data Input PU Internal Pull Up DO Data Output WK Wake Up HD High Current Drive Sink Programmable high current Refer to Section 3 8 4 4 SPI Control Register SPICON for more details 128 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 3 11 2 I O Port Register Descriptions 3 11 2 1 Port A E Port A Data Register PORTA Bit DIR Description Reset Value PORTA 15 0 Port A input and output data Register 0x0000 B Port A Control Register PCONA Bit DIR Description Reset Value I O Port A direction control PDIRA 15 0 RW 0 Input 0x0000 1 Output eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 129 Chapter 3 Ve 3 11 2 2 Port B E Port B Data Register PORTB Bit DIR Description Reset Value Port B input and output data Register 0x0000 Port B input and output data Register eSL and eSLZ000 only 20000 NOTE eSLS
64. SLS Series eSLZ000 User s Manual Pz Chapter 2 2 4 5 3 MAC MAS Saturation Mode 32BIT Overflow V Carry C MAC Output Low po m 1 1 MAC Output 1 1 0 OX7FFFFFFF 2 5 Instruction Set There are two things which you must take note with the instruction set definitions First the to be completed instruction set must have no missing functionality Second the instructions should be orthogonal that is they must not be redundant unnecessarily ELAN eSL Series has a 16 bit instruction set 1 or 2 words It is organized into instruction categories grouped by function as shown in the table below There are only 60 instructions which make software development quite convenient Function Groups Instructions Logic and Mathematic AND OR XOR COM NEG CMP CLR ADD ADC SUB Instructions SUBB INC DEC Branch Instructions JCC JCS JLS JGE S JMP L JMP Shift Instructions SHL SHR ROL ROR ASR MOV R R R I 28 R h 8 R RAM In m R ROM In m RAM In m R R RAMname RAMname R IN R IO lt Add gt OUT IO lt Add gt R PUSH R IO POP R IO SWAP R h R Low Byte R I R High Byte Bit Operation Instructions BS BC BTEST BTGIO Register RAM Control Instructions S CALL L CALL NOP RET RETI RPT LOOP TRAP DSP Instructions MUL UU MUL US MUL SU MUL SS MAC MAS DIV DIVS Data Transfer Instructions eSL eSLS Series eSLZ000 User s Manual Architec
65. TVIE3 TIEO 0x0D 0x0000 SPLIMIE 0x0E 0x0F 0x10 0x0000 PC 15 0 0x11 Oxuuuu SPA 15 0 0x12 0x0000 RCR 15 0 0x0000 LCR 15 0 0x0000 LSA 15 0 0x0000 LEA 15 0 0x16 INTPO 0x0000 DROMIP PWMPIP PWMDIP RTCIP3 RTCIP2 RTCIP1 RTCIPO EXINTIP1 TVIP3 TIPO 0x17 INTP1 0x0000 SPLIMIP 0x18 Reserve 0x19 EICON 0x0000 EXINT1EN EXINTOEN EXINTO 1 0 Ox1A FSR Ox1FFF FSR 9 Ox1B SPLIM 0x0000 Stack point limited register address 15 0 Ox1C 0x Reserve 0x20 PORTC PORTC 7 0 0x21 Reserve 0x22 Reserve 0x0000 0x24 PCON1B 0x0000 RIW Pin7 1 0 Pin6 1 0 Pin5 1 0 Pin4 1 0 Pin3 1 0 Pin2 1 0 Pin1 1 0 Pin 1 0 0x25 PCON2B 0x0000 R W Pin15 1 0 Pin14 1 0 Pin13 1 0 Pin12 1 0 Pin11 1 0 Pin10 1 0 Pin9 1 0 Pin8 1 0 0x26 PCONC 0x0000 RW Pin 1 0 Pin6 1 0 Pin5 1 0 Pin4 1 0 Pin3 1 0 Pin2 1 0 Pin1 1 0 Pino 1 0 0x27 PCOND 0x0000 R W Delay 0x28 0x2F Reserve eSL eSLS Series eSLZ000 User s Manual Instruction Set Summary e 157 Chapter 6 Ve Continued Address Register Name Initial value R W Bit15 Bit14 Biti3 Bit12 Bit11 Bit10 Bit09 Bit08 Bit07 Bit06 Bit05 Bit04 Bit03 Bit02 Bit01 0x0000 TRLO 7 0 0x0000 TCSO 2 0 0x0000 7 0 0x0000 TCS1 2 0 0x0000 TCNT2 7 0 0x0000 TCCR2 7 0 0x0000 1 0 TM2 TCS2 2 0 0x37 TCNT3 0x0000 TCNT3 7 0 0x38 TCCR3 0x0000 TCCR3 7 0 0x39 TCON3 0
66. The three elements of an Interrupt are interrupt source interrupt vector and interrupt function The interrupt vector saves the interrupt function address The interrupt source provides the interrupt signal When an interrupt signal source occurs the program counter will jump to the pertinent interrupt function address vector to implement the interrupt function eSL eSLS Series eSLZ000 User s Manual Architecture e 51 Chapter 2 Ve As shown in the the table below the eSL ICs provide 20 interrupt sources while eSLS offers 17 The interrupt source has 2 level priorities Start Address 0x0000 0x0002 0x0004 Reserved 0x0006 External INTO EXINTIFO 0x000E Timer 2 overflow interrupt flag TOIF2 0x0014 EXINTIF1 0x0016 RTCIFO 0x0020 PWM period interrupt flag PWMPIF 0x0024 Data ROM ready DROMIF 0x0028 SPLIMIF 0x002E Reserved 0x003C Reserved 0x003D 0x003E 0x003F Do NOT use software to enable the interrupt in the eSLS ICs register Otherwise the whole system will reset when interrupt occurs Interrupt Interrupt Source Fla Priority Remarks Hardware Pin reset Reserved Except eSLS Except eSLS Except eSLS Reserved Reserved Reserved 52 e Architecture eSL eSLS Series eSLZ000 User s Manual En Chapter 2 Both eSL and eSLS interrupts can be partitioned into three categories such as hardware reset interrupt special function interrupt and reserved interru
67. WM Period Register e PWM Module Resource B Pulse Width Modulation Attributes and Resources Item Resource Clock source Fei Usage register PWMD PWMP PWMCON Interrupt sources PWMDIF PWMPIF I O function pin PWMO PWM1 H Bridge Single End Left aligned Center aligned Operation mode 84 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual iim Chapter 3 3 4 2 Block Diagram PWM Duty Register PWMD PWMD MSB of PWM Data Buffer Interrupt e PWM Duty Buffer Register Flag Register PWMDIF To PWMPO 10 bit comparator PWMP Prescaler PWMCNT Flag PWMPIF 10 bit comparator PWM Period Register PWMP Figure 3 10 PWM Function Block Diagram To PWMNO 3 4 3 Operation Setting the PWM Duty PWMD register as the main latch and PWMD buffer set as the Secondary latch will ensure a glitch less transition function of the PWM You must perform the following steps to configure the output compare module for PWM operation 1 Set the PWM period by writing to the PWM Period PWMP register 2 Set the PWM duty cycle by writing to the PWMD register 3 Configure the output compare module for PWMP PWMD operation 4 Set the PWMCNT prescaler value and enable the Timer 5 Operation must follow the following set rules e PWMP gt PWMD H bridge e PWMP gt PWMD Single ended PWMD x 0x7FCO0 e PWMP gt PWMD Single ended PWMD gt 0x8000 6 PWM
68. ading table of data in sequential address e Auto increase or auto decrease address after IO DROMD read instruction e Data available after interrupt trigger by hardware B Data ROM Attributes and Definitions Item Resource Usage register DROMCON DROMAH DROMLA DROMD Interrupt sources DROMIF DROMA DROMD WEB RDB CEB only in eSLZ000 Operation mode Auto increase Auto decrease YO function pin 3 7 2 Block Diagram ADDRESS CONTROL DROM interface Figure 3 16 Data ROM Block Diagram 100 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 3 7 3 Register Description E Data ROM Control DROMCON Register Attributes and Definitions DROMCON Bit Description Reset Value DROM function enable disable signal DROMEN 15 1 DROM enable 0 DROM disable power down Control mode 000 Not increase address DROMADDCON 14 12 001 Auto 1 address 010 Auto 1 address Others Reserved DROMDELAY 4 0 Delay clock cycle count B Data ROM Data Access DROMD Register Attributes and Definitions DROMD Bit DIR Description Reset Value DROMD 15 0 R Data ROM Data out 1 u unknown value B Data ROM Low Address DROMLA Register Attributes and Definitions DROMLA Bit DIR Description Reset Value DROMLA 15 0 Data ROM Low Address 0x0000 B Data ROM High Address DROMHA Register Attributes and Definitions DROMHA EEN DIR
69. ances devices or systems Use of ELAN Microelectronics product in such applications is not supported and is prohibited NO PART OF THIS PUBLICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS Ma ELAN MICROELECTRONICS CORPORATION Ke Headquarters No 12 Innovation Road 1 Hsinchu Science Park Hsinchu Taiwan 30077 Tel 886 3 563 9977 Fax 886 3 563 9966 http www emc com tw Hong Kong Elan HK Microelectronics Corporation Ltd Flat A 19 F World Tech Centre 95 How Ming Street Kwun Tong Kowloon HONG KONG Tel 852 2723 3376 Fax 852 2723 7780 elanhk emc com hk Shenzhen Elan Microelectronics Shenzhen Ltd 3F SSMEC Bldg Gaoxin S Ave Shenzhen Hi tech Industrial Park South Area Shenzhen CHINA Tel 86 755 2601 0565 Fax 86 755 2601 0500 USA Elan Information Technology Group USA 1821 Saratoga Ave Suite 250 Saratoga CA 95070 USA Tel 1 408 366 8225 Fax 1 408 366 8220 Shanghai Elan Microelectronics Shanghai Ltd 23 Bldg 115 Lane 572 Bibo Road Zhangjiang Hi Tech Park Shanghai CHINA Tel 86 21 5080 3866 Fax 86 21 5080 4600 En Contents Contents Contents iii Chapter 1 1 Introduction 1 1 1 Introduction to eSL eSLS Series and eSLZ000 IC 1 Falli 2 1 3 Parts E Ne 3 LAT eSLZ000 and eSL ICs Parts List and Properties 3 1 3 2 eSLS ICs Parts List and Properti
70. ata bit CPOL Clock polarity 0 SCK active high 0 1 SCK active low SIZE Word length 0 8 bits 0 1 16 bits MSTR Master Slave mode 0 SPI is in master mode 0 1 SPI is in slave mode SPI clock rate selection Fsys Divisor SPR2 SPR1 SPRO 000 Fsys 2 001 Fsys 4 010 Fsys 8 011 Fsys 16 100 Fsys 32 101 Fsys 64 110 Fsys 128 111 Fsys 256 Add SPIHDEN control bit for programmable high current output in PortA 15 12 Using the library about programmable high current control is recommended Refer to library guide see eSL Series C Macro Reference Manual and eSL Series Assembler Reference Manual for further detailed information 2 CPOL and CPHA clock scheme Note that the clock polarity and the clock phase should be identical for the master and slave devices involved in the communication link CPHA CPOL 0 0 Clock Scheme Description The SPI transmits data one half cycle ahead of the rising edge of SCK and receives data on the rising edge of SCK 0 1 The SPI transmits data one half cycle ahead of the falling edge of SCK and receives data on the falling edge of SCK 1 0 The SPI transmits data on the rising edge of SCK and receives data on the falling edge of SCK 1 1 The SPI transmits data on the falling edge of SCK and receives data on the rising edge of SCK 110 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual
71. basic frequency F32x the PLL clock frequency Eet and the system clock frequency Fsys The basic frequency F32x is used by eSL Series chips as multiplicand to obtain Fe CPU clock frequency slow mode clock frequency Real Time clock RTC frequency Watchdog counting frequency and reset system warm up frequency The F32x frequency is 32KHz Likewise the chips PLL clock frequency Fpry uses the basic frequency F3x as multiplicand see Section 2 7 2 2 to support frequencies used for Timer and Pulse Width Modulation PWM Note that the Fsys also sources its frequency from Een The system clock frequency Fsys which uses FpL as multiplicand to vary frequencies to reduce power consumption is used for CPU instruction clock frequency selection and for Serial Peripheral Interface SPI TX and RX data communication with eSL Series device and external flash or ROM Take note that the SPI function does not support eSLS B ELAN eSL Series Oscillator System Attributes and Resources E Item Il Resource Usage register FSR SCS SMC VO function pin OSCI OSCO OSCS PLLC 2 7 1 Block Diagram F32k Clock gp Switching SystemClock Fsys ose PIE Circuit Feu x ij 1 FSR PLLC SCS SMC Figure 2 18 ELAN eSL Series Oscillator System Block Diagram 40 e Architecture eSL eSLS Series eSLZ000 User s Manual 2 7 2 Operation 2 7 2 1 32K RC X tal Oscillator The RC 32 8 kHz or crystal 32768Hz oscillator
72. ccurs Interrupt Timing at Fast Slow mode 1 2F proy 32mMs gt Tobia period E 1 Frtex WKUP By Miss the WKUP By Miss the WKUP By RisingEdge FallingEdge Rising Edge FallingEdge Rising Edge Warm Up Interrupt Timing at Green mode 32 001ms E Warm up Process Sleep Figure 3 3b RTC Wake up Timing Diagram in Case b B Case c RTCI 01 Mode Timing Diagram RTCS1 01 and WUPS 00 Interrupt Occurs Interrupt Occurs Interrupt Occurs Only By Rising Edge Only By Falling Edge Only By Rising Edge Y Interrupt Timing at Intefrupt Fast Slow mode Oc urs 1 2 rcx 9ms T 1 2FRrcx T wake up period Warm up WKUP By WKUP By WKUP By Rising Edge FallingEdge Rising Edge Missthe Miss the Missthe Warm Up Interrupt Rising Edge FallingEdge Rising Edge Timing At Green mode 32 001ms q Warm up Process Sleep Figure 3 3c RTC Wake up Timing Diagram in Case c eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 69 Chapter 3 3 2 4 Examples Set RTCO to count once per second and output the SecData to PORTD DATA SecData DS 1 CODE include interruptvector def POWERON RO 0x0000 SecData R Initial SecData RO 0X8003 IO RTCCON RO enable RTC no wake up RTCO clock source 1 32k 1HZ BS IO SR GI Enable GIE BS IO INTEO RTCII Enable RTCO interrupt Delay Main loop JMP
73. d 15 gt Rd 15 Rd 15 1 gt Rd 14 0 Rd 0 2C Rs gt Rd Rs 1 gt Rd Rs 15 8 Rs 7 0 1 1 E E Ed E E i 1 1 1 i 1 1 1 1 um wp si espe dee eSL eSLS Series eSLZ000 User s Manual Pz Chapter 6 Continued Function Algebra Assembly n Operation wie IT nJz vjc Syntax CMP Rs Rt Rs Rt update SR register 1 1 CMPRs RU Re fR update SR register 1 1 Rs Rie CMP Rs Rt update SR register petit CMP Rs Rt seien update SR register Rs P Rt SME RSAIRI update SR register 1 21 CMP Rs PIRt eet R 4 2 1 update SR register Rs P Rt CMP Rs P Rt Reet a update SR register Rs P Rt CMP Rs P Rt er PIREA update SR register 1 Using RPT instruction to perform this operation only needs 1 cycle 6 2 4 Bit Operation Instructions Algebra Assembly Function Syntax Operation wic UMANE BS Rd b 12 Rd bit dj EREEEEE Bs Et ee BSRAM addrb 1 gt RAMaddrfbitb V1 BC Ban 0 gt Rafoit b 1 1 BC IO IO addr b 02 IO addr bit b BC RAM addr b 05 RAM addr bit b 1 1 TEL E BTG 1010 adaro iO addrb gt o sdb UT RAM addr b mmm mem IT BTEST Rd b Test Rd b gt Test Flag 1 1 ere inerzia DE Test RAM_ addr b BTEST RAM_addr b oo Test Flag IO addr 0x00 0x0F RAM addr 0x0000 0x0007 eSL eSLS Series eSLZ
74. d SSAOI VSS_OSC VDD_OSC VSS_PM VDD_PM VSS_CPU VDD_CPU Od CONOI RVOUT fd QGAOI WMd GONOI Figure 3 26a eSL Regulator under 3V and 5V Supply Voltage AVSS DA AVDD DA AVSS AD Od SSAOI gd SSAOI AVDD AD INMd SSAOI VSS_OSC VDD_OSC VSS_PM VDD_PM 0 9 SE Um v ZS mw Z Z VSS_CPU VDD_CPU Od ATAOI RVOUT Figure 3 26b eSL Regulator under 3V Supply Voltage Only eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 135 En Chapter A Chapter A Electrical Characteristics 4 1 CPU Voltage Frequency Graph The speed of a MOS device is dependent on voltage temperature and process variation Performance prediction is based on a combination of these three factors The central operating condition is characterized at 3 3V 25 C and typical process parameters Voltage Frequency Graph Voltage V 0 2 4 6 8 10 12 14 16 18 20 22 24 Frequency MHz Figure 4 1a eSL and eSLS Voltage vs Frequency Graph eSL eSLS Series eSLZ000 User s Manual Electrical Characteristics e 137 Chapter 4 ps Voltage Frequency Graph Voltage V 0 2 4 6 8 10 12 14 16 18 20 22 Frequency MHz Figure 4 1b eSLZ000 Voltage vs Frequency Graph 4 2 Absolute Maximum Ratings
75. d the C flag bit Use arithmetic shift right ASR for keeping the sign bit B Shift and Rotation Instructions Definition Mnemonic Description SHL Shift Left SHR Shift Right ROL Rotate Left ROR Rotate Right ASR Arithmetic Shift Right 15 0 Cle 0 SHL 15 0 0 gt Cc SHR 15 0 Che a ROL 15 0 _ gt C ROR 15 0 c ASR Figure 2 15 Shift Instructions Shifting Diagram 32 e Architecture eSL eSLS Series eSLZ000 User s Manual Source Destinat n Chapter 2 2 5 4 Data Transfer Instruction The Data Transfer instruction moves data from a source to a destination It provides indirect auto increase or decrease mode for moving large block of data around main memory The following table lists the functions within the Data Transfer instruction 2 5 4 1 Data Transfer Instruction Description Mnemonic Description Move from RHS to LHS Input from I O Output to UO PUSH Push to TOS POP Pop from TOS 1 RHS Right hand side LHS Left hand side TOS Top of stack MOV instruction provides the data transfer ability to move data from memory to register L
76. ddr16 C gt Rd 2 2 Rd Rs Rt Rs Rt gt Rd 1 1 Rd Rs Rt Rs Rt gt Rd 1 1 Rd Rs Rt Rs Rt gt Rd 1 1 Rd Rd imm6 Rd imm6 gt Rd 1 1 Rd Rs imm16 Rs imm16 gt Rd 2 2 Rd Rs imm16 Rs imm16 gt Rd 2 2 ele ae 4 Rd Rs RAM16 Rs addr16 gt Rd 2 2 Rd Rs Rt B Rs Rt C gt Rd 1 1 Rd Rs Rt B Rs Rt C gt Rd 1 1 Rd Rs Rt B Rs Rt C gt Rd 1 1 Rd Rd imm6 B Rd imm6 C gt Rd 1 1 rrr Rd Rs imm16 B Rs imm16 C gt Rd 2 2 Rd Rs imm16 B Rs imm16 C gt Rd 2 2 Rd Rs RAM16 B Rs addr16 C gt Rd 2 2 EEE EEE EEE EEB EEE EEE D Rs P Rt SS Rs S P Rt S gt D 1 Using RPT instruction to perform this operation only needs 1 cycle 150 e Instruction Set Summary eSL eSLS Series eSLZ000 User s Manual Continued Algebra Assembly Syntax Operation WIC T Chapter 6 N Z DERS RI SU eent v DRR Lpsmuag n D Rs Rt SU Rs s Rtu gt D Im D Rs Rt SU EEE MUL SU D Rs PIRISU DEE D Rs P Rt SU Rs S P Rt U gt D EEE D Rs P Rt SU Rs S P Rt U gt D ERE D Rs P Rt SU Rs S P Rt U gt D BEE D Rs R US ABE D Rs Rt US Rs U Rt S gt D D Rs Rt US Rs U Rt S g
77. ddressing B C the Invert of Carrier P Point to Program ROM IO Point to I O space lt abs ADD gt Absolute address 16 bits eSL eSLS Series eSLZ000 User s Manual Instruction Set Summary e 147 Chapter 6 6 1 3 Operator Description nn 303 gt The four fundamental operations of arithmetic Point to Data RAM The division instruction takes 16 cycles when in fractional mode and takes 17 cycles when in integer mode 6 1 4 Flag status SR Description T Test Flag N Negative Flag Z Zero Flag V Overflow Flag C Carry Flag Flag is Affected by instruction operation Flag is un change by instruction operation Flag is un defined Don t care by instruction operation 6 1 4 Operation Explainations These symbols which are written after a valid instruction are used to clarify such instructions only They do not operate as part of the instruction addr16 Description The value of 16 Bits RAM address It is not RAM address addr8 The value of 8 Bits RAM address It is not RAM address Long addr 16 bits absolute address for long jump Short addr 16 bits address with PC 1 9 offset for short jump L addr 16 bit absolute address for long call 14 bit address for short call The four fundamental operations of arithmetic Operator Logic operation as AND OR XOR and 1 s complement respectively
78. de Pin Definitions Configuration Serial clock in Slave select Serial data in Serial data out SS 0 High impendence SS 1 When a device is configured as a slave MSTR 1 the SCK pin is used as the input for the serial shift clock which is supplied from the external master The transfer rate is defined by this clock rate If data is to be transmitted by the slave simultaneously and TDBR has not been previously loaded the data must be written to TDBR before the beginning of the SCK signal The SS pin operates as the slave select pin An active low signal on the SS pin allows the slave SPI to transfer data to the serial data line An inactive high signal causes the slave SPI serial Shift register to stop and its serial output pin is placed into high impedance state This allows many slave devices to be tied together on the network although only one slave device is selected at a time 116 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual En Chapter 3 3 8 9 SPI Master Initial Flow Chart There are two data transfer modes under SPI master device namely Empty and Complete modes In Empty mode data transfer process occurs continuously as long as the TDBR empty flag TXS 0 remains enabled Under Complete mode data transfer is performed in batches i e writing data to TDBR can be done only when the current batch of data being transferred is completed
79. eSL eSLS Series eSLZ000 16 Bits DSP Sound Processor USER S MANUAL Trademark Acknowledgments IBM is a registered trademark and PS 2 is a trademark of IBM Windows is a trademark of Microsoft Corporation ELAN and ELAN logo ram are trademarks of ELAN Microelectronics Corporation Copyright 2006 2009 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this User s Manual publication are subject to change without further notice ELAN Microelectronics assumes no responsibility concerning the accuracy adequacy or completeness of this publication ELAN Microelectronics makes no commitment to update or to keep current the information and material contained in this publication Such information and material may change to conform to each confirmed order In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors omissions or other inaccuracies in the information or material contained in this publication ELAN Microelectronics shall not be liable for direct indirect special incidental or consequential damages arising from the use of such information or material The software if any described in this publication is furnished under a license or nondisclosure agreement and may be used or copied only in accordance with the terms of such agreement ELAN Microelectronics products are not intended for use in life support appli
80. ech with different channel sample rate or 1 channel speech 8 channel melody Coding Type 12K 16K 20K 32K 40K 48K 96K bps 8KHz Sampling Rate Range 6kHz 48KHz Recording Yes 6 e Introduction eSL eSLS Series eSLZ000 User s Manual Pz Chapter 1 o eSL032A eSL128A eSL256A eSL512A eSL032B eSL128B eSL256B eSL512B eSL512C Audio Up to 2 channel speech with different channel sample rate or 1 channel speech 8 channel melody 12K 16K 20K i 132K 40K d 0 8K 96K bps 8KHz Type 48K 96K bps 8KHz Sampling Rate 6kHz 48KHz Range Recording Yes Yes Yes Yes Yes Yes Yes Yes No Lana Yes Yes Yes Yes Yes Yes Yes Yes No Tracking Speaker Independent No No No No Yes Yes Yes Yes No Recognition Speaker Dependent No No No No Yes Yes Yes Yes No Recognition Recording Yes Yes Yes Yes Yes Yes Yes Yes No Sound Source Yes Yes Yes Yes Yes Yes Yes Yes No Detection Speech Speed Pitch Yes Yes Yes Yes Yes Yes Yes Yes Yes Control Hand Writing No No No No No No No No Yes Recognition eSL eSLS Series eSLZ000 User s Manual Introduction e 7 Chapter 1 Ve 1 4 2 eSLS ICs Parts List and Properties Product No eSL128S eSL256S eSL512S UP to 2 channel speech with different channel sample rate or 1 channel speech 8 channel melody 12K 16K 20K 24K 32K 40K 96K bps 8KHz 6KHz 48KHz eSL128SA
81. ection 2 5 6 2 below The Repeat RPT function may be tied in with such instructions as Multiply Accumulate MAC and Block Moves MOV to increase execution speed of RPT instruction These multicycle instructions effectively become single cycle instructions after the first iteration of a repeat instruction 2 5 6 1 Operating Instruction Example Syntax Original Cycle 2 PI Mnemonic Example Syntax MOV ADD R1 R2 R3 SUB R3 R2 R1 Number of cycles when instruction is not repeated 2 5 6 2 RPT and LOOP Instructions Limitations Some instructions cannot be repeated with RPT instruction and cannot be the last instruction in a LOOP These instructions are as below Mnemonic Description CALL Unconditional call JMP Instructi Branch instruction Ee Include unconditional or condition brach Return from subroutine RETI Return from interrupt Repeat next instruction eSL eSLS Series eSLZ000 User s Manual Architecture e 35 Chapter 2 En 2 5 7 DSP Instruction The hardware multiplier module supports four types of multiplication Multiplication is applicable for B 16 Bit unsigned x 16 Bit unsigned E 16 Bit unsigned x 16 Bit signed B 16 Bit signed x 16 Bit unsigned B 16 Bit signed x 16 Bit signed The multiplier deals with 16 bit signed unsigned numbers 17 bits are needed to represent the operand in both modes in 2s complement It can multiplex its output using a scale
82. efine the transfer format In SPI slave mode SPI SCK has wake up functionality in GREEN and SLEEP modes 3 8 3 2 Serial Data In SI The SI pin is a data receive input pin for receiving input data 3 8 3 3 Serial Data Out SO The SO pin is a data transmit output pin for transmitting output data The MISO pin of a slave device will be placed in the high impedance state if the slave device is not selected 3 8 3 4 Slave Select SS The SS is the Serial Peripheral Interface Slave Select input signal This is an active low signal used to enable a slave device This input only pin behaves like a chip select and is provided by the master device for the slave devices For master device the SS pin can be set as GPIO pin eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 107 Chapter 3 108 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual En Chapter 3 3 8 4 SPI Register B SPI Register Attributes and Definitions Name Function DIR Default RDBR 16 bit Receive Data Buffer Register TDBR 16 bit Transmit Data Buffer Register SPICON Serial Peripheral Control Register SPISR Serial Peripheral Status Register 3 8 4 1 Receive Data Buffer Register RDBR The Receive Data Buffer Register RDBR is a 16 bit read only RO register At the end of a data transfer the data in the shift register is loaded into RDBR SFDR 16 bit Data Shift Register 3 8 4 2 Transmit Data Buffer Reg
83. em and PLL Positive power supply for DROM ICE function and boot function I O MESSE i d pad eSLZ000 only Positive power supply for PortD and PWM I O pad IOVDD PWM P 3V 5V eSL and eSLZ000 only Positive power supply for PWM I O pad eSLS Seies only IOVDD PB P 3V 5V Positive power supply for PortA 2 15 and PortB I O pad IOVDD PC P 3V 5V Positive power supply for Port I O pad eSL Series and eSLZ000 IOVDD P 3V 5V Positive power supply eSLS Series only VSS_CPU P OV Negative power supply for CPU digital peripheral and DRAM Negative power supply for PROM DROM and POR eSL and eSLS VSS_PM P OV only Negative power supply for PRAM and POR eSLZ000 only VSS OSC P OV Negative power supply for Oscillator system and PLL Negative power supply for DROM ICE function and boot function I O VSS_ICE P ov oat sto PRA Negative power supply for PortD and PWM I O pad eSL and eSLZ000 IOVSS_PWM P OV only Negative power supply for PWM I O pad eSLS only IOVSS_PB P OV Negative power supply for PortA 2 15 and PortB I O pad IOVSS P OV Negative power supply eSLS Series only IOVSS PC P ov Negative power supply for PortC I O pad eSL and eSLZ000 only AVDD AD P 3V Positive power supply for A D eSL and eSLZ000 only AVDD_DA P 3V Positive power supply for D A AVDD P 3V Positive power supply eSLS Series only AVSS_AD P OV Negative power supply for A D eSL Series and eSLZ000 AVSS_DA P OV Negative po
84. ement The PWMP maximum value is OX 7FCO Therefore under the half PWM period Single ended PWM has the same resolution compared to H bridge see Figure 3 11 below 86 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual 3 4 3 4 H Bridge PWM H bridge PWM is a modulation method for motor control and audio applications The waveform is complementary at any time which makes it very suitable for motor control Since its power requirement is higher than single ended it may have a higher power consumption but the volume from H bridge PWM is higher than single ended The PWMP maximum value is Chapter 3 OxFFCO PWMD PWM 0 i PWMI l PWMD l PWM 0 PWM 1 l duty ratio I I duty ratio I I _Tr _l 00 0000 0000 je gt 00 0000 0000 le E je i 9000 001 LK 2 0000000001 P I rr II I 00 0000 0010 E 00 0000 0010 E 00 0000 mi BL IL l deal 00 0000 0011___ F n AT EMEND M E BEEN f d Soe emo FL P O1 1111 1111_ i ke gt L o nnan f l l l 10 0000 0000 gt 10 0000 0000 10 0000 0001 gt u H j 10 0000 0001 l l 10 0000 0010 3 10 0000 0010 10 0000 0011 Lu 1000000011 ST T_T UE 11 1111 1110 teeth nnn I aa 11 1111 1110 2 H n a fe gt ke ES 1 11 1111 1111 Jh Single ended A o I H bridge I I PWMP Ox7FCO PWMP OxFFCO Figure 3 12 Single Ended amp H Bridge PWM Output Waveforms at Various Duty Ratios 3 4 4 Regist
85. ent from current mirror Imax Full scale current 3 5 3 Registers B DAC Control DACCON Register Attributes and Definitions DACCON Bit DIR Description Reset Value RW The duty ratio of DAC channel Enable 0 DAC 2 complement mode control DAC2SC 5 RW 0 Unsigned mode 0 1 2 complement mode DAC Data 0 DACDO output mode 00 Always bypass DACMOD RAW 01 Trigger on Timer 0 interrupt flag 00 10 Trigger on Timer 1 interrupt flag 11 Trigger on Timer 0 1 interrupt flag DACVOL R W DAC volume control 111 90 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 B DAC Data DACD Register Attributes and Definitions Description Reset Value DACD 15 4 RW The duty ratio of DAC channel 0x000 3 5 4 Application Example Shunt a resistor at bipolar transistor base and emitter to reduce collector current VDD Figure 3 13 Using DAC Function to Drive a Speaker Circuit Diagram 3 5 5 Examples Set DAC output data from 0 to OxFFFO by adding 0x0010 POWERON DA CON 0 0 7 Set DAC Un Sign mode always pass mode vol 3mA max RO 0x0000 Clear data DAC ADDone DA OUT RO Out data to DAC IO PORTA RO Output data to PORT A R1 0x01FF Delay LOOP R1 NOP ENDL RO RO 16 Data 16 IF NE JMP DAC ADDone _Delay Main loop JMP Delay eSL eSLS Series eSLZ000 User s Manua
86. eral Purpose Register 0 A A da 65535 Figure 2 6 Indirect Addressing with Post Decrement 2 3 4 Indirect Addressing with Post Increment The indirect register pointer is incremented by 1 after operation The addressing mode is very powerful for bulk operation and for operations that need a lot of memory accesses The purpose of the addressing mode is to keep high MAC data path utilization Example D D R3 P R4 and R1 P R5 ROM RAM Space m gt General Purpose Register 0 I 65535 Figure 2 7 Indirect Addressing with Post Increment 2 3 5 I O Direct Addressing The address is contained in a 7 bit instruction word The second operand is either Rd or Rs destination or source register respectivley used by IN and OUT instructions to read from or write to the I O registers 1 Rd is the Destination Register of General Purpose Registers Rs is the Source Register of General Purpose Registers eSL eSLS Series eSLZ000 User s Manual Architecture e 21 Chapter 2 Example R6 IO PORTA and POP IO PORTC OP VO address I O Space 128 Figure 2 8 I O Direct Addressing 2 3 6 RAM Data Direct Addressing An 8 bit data address is contained in the 1 word instruction Rd or Rs specifies the destination or source register respectively For example R RAM bank A 16 bit data addre
87. ernal Reset a Power On and RESET pin open RESET Timer Overflow Warm up Time Out Internal Reset b Power On and RESET with a Capacitor Figure 2 23 Power On Reset POR Timing Diagram eSL eSLS Series eSLZ000 User s Manual Architecture e 47 Chapter 2 2 8 4 Brown Out Reset BOR When the power supply voltage is insufficient the eSL Series CPU may start to execute some instructions incorrectly To avoid this condition the CPU should be prevented from executing code during an insufficient voltage supply codition This is the best method of maintaining normal system operation when noise initiated power drop also known as Brown Out Reset or BOR occurs Any voltage supply that is below the fixed threshold voltage see Vgor in the Figure below the BOR forces the internal RESET to high active To avoid power drop noise due to motor SPK drop test or VDD short period spike noise application of the low voltage reset mechanism BOR ensures normal function of the chip logic and reset operation VDD VBOR C RESET Timer Timer H Clear i Overflow Warm up al Time Out Internal i E Reset d Brown Out RESET Figure 2 24a Brown Out Reset BOR Timing Diagram The diagram below shows an ideal DC mechanism When power goes below VBOR power on reset is activated Otherwise power goes up above VBOR and power on reset is c
88. ers B PWM Duty PWMD Register Attributes and Definitions PWMD Bit DIR Description Reset Value PWMD 15 6 The duty ratio of PWM channel 0000000000 doa Reseved Unknown eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 87 Chapter 3 B PWM Period PWMP Register Attributes and Definitions PWMP Bit 1 Description Reset Value PWMP The period of PWM channel 0111111111 Reserved Unknown PWMCON Bit DIR 15 RW The PWM enable 0 Output regular current 12 ee 1 Output large current Volume control 00 1 4 11 10 RW 01 1 2 10 3 4 11 1 1 9 R W PWM counter clear This field determines the number of PWMD buffer data usage The seven repeats means that each buffer data should be used in the Timer seven times before taking the 8 6 RW next data in PWMD 000 No effect 001 One repeat 010 Two repeats i 111 Seven repeats PWM output mode 5 RW O Single ended 1 H bridge 0 Left aligned 1 Center aligned The PWM output port enable 00 No output 3 2 RW 01 PWMO output only 10 PWM1 output only 11 both PWMO amp PWM are outputs The PWM pre scale selection 00 Fei 1 1 0 RW 01 Fo 2 10 Feit 14 11 Feu 8 4 R W 88 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual 3 4 5 Examples Chapter 3 POWERON RO 0X0003 IO PDIRA RO RO 0X0200 IO PWMCON R
89. es eSLZ000 User s Manual Chapter 3 0 Diagrams 1 CHPA kiss i ee EAEN 3 8 6 2 SPI Slave Mode Timing CPHA SCK CYCLE H E o eee db ss we ee ee tee gt O H 3 S EE kee See sen lee 3 H Q o x ERR E e cH PE sue E E mme a sN fossa o E e e 9 ERE S Bee sf HU tue IG D H 5 22 Arcem E merum mmm D DE t e N B e e S ee DEET dano pu usc cusa En ir e Se Li LE ti SS E E A fa E E E o A o U 2 5 tc 3 T e zi ee oO n ET T T a E 4 40 p p o E o E s 4E gi 2 E a s ME xE 2 6 E B sa a OF 5A O EO Q SA wn YO DO E AR 2 AL aL z d E a ae 2 292 40 z E E Peripheral Control e 113 1 Diagram Figure 3 20b SPI Slave Mode Timing CPHA eSL eSLS Series eSLZ000 User s Manual Chapter 3 Ve 3 8 6 3 Consecutively Receiving Bytes CPHA 1 CHPA 0 Timing Diagrams Write Write Write Write Bytel js Byte3 Byte4 Data writeto Read Read TDBR TXS B yeay ByteBy Dataread from RDBR SS SCK TTX Xe Ca SI TCF Figure 3 21a Consecutively Receiving Bytes Timing Master or Slave Mode CPOL 0 CPHA 1 Diagram Write Write Write Write Bytel Byte2 Byte3 Byte4 Data write to Read Read TDBR TXS ByteAy ByteBy Dataread from RDBR SS SCK wo ZC Xoo e Xe TCF Figure 3 21b Consecutively Receiving Bytes Timing Master or Slave Mode CPOL 0 CPHA 0
90. es aussen rasa asas 4 1 3 3 Properties Comparison between eSLZ000 eSL and eSLS ICs 5 1 4 Algorithm Selection ble 6 1 4 1 eSLZ000 and eSL ICs Parts List and Propetties sees 6 1 4 2 eSLS ICs Parts List and Properties iii iii 8 1 5 Typical Ape Ri 9 Lo Pin Descriptions T 10 1 6 1 Ee eessen E R E EEEE E REEE A 10 1 6 2 SIL 11 1 6 3 Ne 11 1 6 4 Two Stage Amplifier amp Touch Pad Positioning Supports eSL and eSLZ000 MSS OIA 11 los A E 12 1 6 6 Data ROM Interface eSLZ000 only ric 14 L6 7 ICE Interface 6S LZ 00D Oily ille 14 Chapter 2 17 Architecture 17 2d SSL Syst m Block Die la 17 2 2 Program ROM and Data RAM Description ene 18 2 2 Program ROM RAM Pr cc 18 2 2 2 Data RAM and Bank Select Register s icvscsscsdounesanvectacvervesteresavdsssseunneansivessdves 19 2 3 Addressing Molina 20 2 3 1 Register Direct 20 2 3 2 Register Indirect Addressing csrl 20 eSL eSLS Series eSLZ000 User s Manual Contents e iii Contents En 2 3 3 Indirect Addressing with Post Decrement 21 2 3 4 Indirect Addressing with Post Increment ii 21 2 3 3 VO Ditect Addressing lla 21 2 3 6 RAM Data Direct Addressing Liri 22 2 3 7 nda 23 2 3 8 Relative Program Addressing sese eene 23 2 3 9 Data Indirect Addressing with Displacement
91. ess is the result of the register contents added to the address contained in 5 bits of the instruction word For example R1 R3 10 R3 is the only register that can be the base register Example R1 R3 10 4 0 RAM Space OP Rs Offset 0 P GPR x rn NL 65535 Figure 2 12a Data Indirect with 5 Bit Displacement Addressing Operation Diagram Operand address is the result of the register contents added to another register Example R3 R1 R2 2 0 RAM Space OP Rs Rt 0 Y GPR GPR A ll 24 NE 65535 Figure 2 12b Data Indirect with 5 Bit Displacement Addressing Operation Diagram 24 e Architecture eSL eSLS Series eSLZ000 User s Manual Pz Chapter 2 2 4 Register Architecture The following figure shows the ELAN eSL Series register architecture Each of these Registers are discussed in details in the following pages 1 Register Space regs GENERAL PURPOSE REGISTER 15 0 RO R1 R2 R3 R4 R5 R6 R7 R1 RO ACCUMULATOR D D 2 1 0 Space regs 15 0 PROGRAM COUNTER PC 15 0 STACK POINTER SP 15 0 REPEAT COUNTER RC 15 0 LOOP COUNTER LC 15 0 LOOP START ADDRESS LSA LOOP END ADDRESS LEA 15 0 STATUS REGISTER SR 15 0 SPECI
92. fer operation when the TCCR is set as an Input Capture register TCNT operates as a free running counter and TCCP capture occurs at rising edge falling edge or at both edges of the input signal The TCNT value is stored in TCCR when Input Capture occurs eSL eSLS Series eSLZ000 User s Manual Chapter 3 Timer Overflow Interrupt TCNT Value Flag is set HFF HBF HTF HIE TCCP Input Timet Interrupt Flag is set TCCR Value DA HE X H BF X H7F a TIOM 00 Timer Overflow Interrupt TCNT Value Flagis set HFF H 7F HMF TCCP Input 7 Timer Interrupt Flag is set TCCRValue X H7F b TIOM 01 Timer Overflow Interrupt TCNT Value Flagis set HFF H BF H 7F HMF TCCP Input A Timer Interrupt Flag is set TCCRValue i HIE GEN HBF X HF Xm c TIOM 1X Figure 3 7b Capture Timing Diagram Peripheral Control e 77 Chapter 3 B Compare Mode Operation Under this mode a match signal is generated when the counter value is identical with the value written to the Timer Compare register TCCR It could be configured into following output waveforms by setting the TIOM Timer Input capture Output compare Matching e Interval Mode Timer Reload Mode e Compare Match and Overflow Mode e Simple PWM Mode However when configured as Compare Match and Overflow and Simple PWM modes of o
93. ggled In case of TIOM 10 as shown in the center figure b the TCCP toggles when match condition occurs but the counter value will only reset when overflow occurs In PWM mode PWM waveforms are generated by using TCNT as the Period register and TCCR as Duty registers PWM waveforms are output from the TCCP pin The figure at the bottom of the diagram c also shows an example of operation in Simple PWM mode when TIOM 11 The output signals goes to 1 and the TCNT is cleared at counter overflow then the output signals goes to 0 when TCNT compare match with TCNT Value Counter cleared by compare match TCCR Value TCCP Output N Da Timer Interrupt Flag is set a TIOM 01 Timer Overflow Interrupt TCNT Value Flag is set TCCR Value TCCP Output N i Timer Interrupt Flag is set b TIOM 10 Timer Overflow Interrupt TCNT Value Flag is set TCCR Value TCCP Output a Timer Interrupt Flag is set c TIOM 1 TCCR TCCP initial output values are set to 1 eSL eSLS Series eSLZ000 User s Manual Figure 3 8b Compare Timing Diagram Peripheral Control e 79 Chapter 3 B Clock Selection The clock source for each counter can be individually selected by writing the appropriate value in TCON Feu 12 Bit Prescaler TEXI3 e TEXI2 A MT EA TCS2 TCS3 C
94. han the eSL ICs B eSLZ000 IC is the eSLZ000 ICE kernel chip used to emulate the eSL eSLS Series ELAN eSL Series ICs are 16 bit DSP Sound Processor with multi channel speech and instrument playback based on Elan 16 bit DSP platform The series has a powerful 16 bit DSP architecture that handles most of the speech melody functions Speech and melody can be played back simultaneously with the speech synthesis implemented by software A wide range of compression bit rates and various volume levels are supported eSL Series chips are equipped with real instrument waveform which enable the chips to obtain good quality melody ELAN eSL peripherals include RTC Timer WDT DAC PWM etc The eSL Series ICs offer FAST SLEEP GREEN and SLOW modes of operation The use of GREEN and SLOW mode further reduces power consumption Moreover GREEN mode also provides RTC function for wake up propose The chips are designed as a cost effective processors offering optimized performance and are ideal for such applications as high compression rate digital voice signal high quality instrument melody voice recognition digital sound effect etc The eSL Series constructive features motivate exploration into wide variety of new creative ideas for more innovative products ELAN eSL Series perform extremely well in speech application based on powerful DSP architecture and are endowed with good algorithm for audio compression eSL eSLS Series eSLZ000 User s
95. her types of malfunctions To configure WDT the overflow signal from 5 bit prescaler should be fed into the 8 bit Watchdog Timer clock input as shown in the block diagram Figure 3 1 under Section 3 1 1 You can enable or disable the Watchdog Timer through software by configuring the WDTEN bit If you do not want to use the WDT the 5 bit Basic Timer can only perform as a normal interval timer to request for interrupt service B The Watchdog Timer Attributes and Resources Item Clock source Resource Usage register WDTCON Interrupt sources WDTIF Operation mode Overflow The WDT clock source is from 32kHz oscillator WDT time out will cause a CPU reset if WDTEN 1 and WDTREN 1 To prevent CPU reset from occurring the WDT value should be cleared by using WDTC bit before WDT time out Setting the WDTEN bit will enable WDT to run The initial state of WDT is disabled A prescaler is also available to generate several clock rates as clock source for WDT The prescaler ratio is defined by WDTPSRI amp WDTPSRO eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 63 Chapter 3 3 1 1 Block Diagram Overflow To 32K Hz 5 Bit e decido 8 Bit Watchdog Timer m Lt Figure 3 1 WDT Configuration Flow Block Diagram 3 1 2 Watchdog Control Register The Watchdog Timer starts counting upward when the WDTEN bit is set to 1 and stops when the WDTEN bit is cleared set to 0 The WDT
96. is disabled in the initial state When the WDT is not used clear the WDTEN bit to 0 Watchdog Overflow Enable WDTREN flag is enabled set to 1 to generate internal reset signal with the WDTEN bit set to 1 at the same time When disabled WDTREN 0 the Watchdog Timer functions only as timing interval to obtain WDT Interrupt Flag WDTIF value B Watchdog Timer Control WDTCON Register Attributes and Resources WDTCON Bit DIR Description Reset Value Enable disable watchdog timer function WDTEN 15 0 Disable 0 1 Enable Watchdog overflow enable disable WDTREN 3 0 Disable 0 1 Enable Watchdog Timer Reset Clearing conditions Reset by the internal RESET signal WDTC 2 When 0 is written to the WDT counter 0 0 No effect 1 Clear the WDT count value Select WDT clock source 00 F32x 4 WDTPSR 1 0 R W 01 Fa2k 8 si 00 10 F30x 16 11 F32k 32 The Fox frequency value is dictated by existing oscillator circuit RC or Xtal type 64 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Chapter 3 3 1 3 Examples B Example A Set WDTCON register to reset your system POWERON RO 0x0002 IO WDTCON RO Clear WDT timer RO 0x8004 Enable WDT enable overflow clock source 32768 4 IO WDTCON RO Reset time 32768 4 256 31 2ms Delay Main loop JMP Delay B Example B Set watchdog as general 8bit ti
97. ister TDBR The Transmit Data Buffer Register TDBR is a readable and writeable register Data is loaded into this register before being transmitted Just prior to the beginning of a data transfer the data in TDBR is loaded into the Shift Data SFDR register If multiple write to TDBR occurs while a data transfer is in progress only the last written data will be transmitted None of the intermediate values written to TDBR will be transmitted Multiple write to TDBR are possible but not recommended 3 8 4 3 Shift Data Register SFDR The Data Shift Register SFDR is the 16 bit data shift register it is not accessible by software The SFDR is buffered to prevent a write to TDBR from overwriting the shift register during an active transfer The data in SFDR is shifted out MSB on subsequent SCK cycles For every bit MSB shifted out of the SPI a bit is shifted into the LSB end of the shift register eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 109 Chapter 3 3 8 4 4 SPI Control Register SPICON SPICON Bit DIR Description Reset Value SPI enable disable Disable SPI SI SO SCK and SS are configured as GPIO 0 Enable SPI SI SO SCK and SS are configured as SPI special pins 15 SPIHDEN 14 Disable high current output Enable high current output CPHA Clock phase 0 SCK toggle starts at the middle of first data bit 1 SCK toggle starts at the beginning of first d
98. ivides clock by 4 or Fsys Fpii 4 00 10 1 8 divides clock by 8 or Fsys Feui 8 11 1 1 not divided System operation mode control 000 FAST mode SMC 001 SLOW mode 0x000 01X GREEN mode 1XX SLEEP mode Refer to Warm up TimeOut in Figure 2 22 Reset System Timing Diagram Section 2 8 2 WUPS 6 5 00 2 8 Reset System ELAN eSL Series provides four sources of reset B Power on Reset POR The power on reset circuit holds the device at reset state until VDD is greater than the VPOR Power on reset voltage Otherwise if the voltage supply is lower than the VPOR a reset will occur see further details in Section 2 8 3 below B External Reset Use the RESET pin as an External Reset B Watchdog Reset If Watch Dog Timer is enabled the WDT time out will cause the chip to reset To prevent such reset from occurring you should clear the WDT value by using WDTC bit before WDT time out 44 e Architecture eSL eSLS Series eSLZ000 User s Manual Chapter 2 B Brown Out Reset The MCU is reset when the supply voltage VCC is below the Brown out Reset threshold VBOR During reset all I O Registers are reset to their initial values and the program starts execution from Address 0x0000 The instruction placed at Address 0x0000 must be a Long JMP instruction to the reset handling routine If the program never enables an interrupt source the interrupt vectors and regular program code can be placed a
99. l Peripheral Control e 91 Chapter 3 En 3 6 Analog to Digital Converter eSL and eSLZ000 only Analog to Digital Converter ADC is a 12 bit data acquisition module that is embedded in the eSL voice chips It consisted of an 8 channel multiplexer a microphone pre amplifier an Automatic Gain Control AGC function with gain amplifier 12 bit Successive Approximation SAR Analog to digital converter ADC and a voltage reference There are 8 single ended analog input channels in the module The XP YP input channel which is integrated with the touch panel shares the common pins with two general analog inputs as ADINO ADINI The other 6 channel general analog inputs share their common pins with GPIO PORTC2 7 B Analog to Digital Converter Attributes and Definitions Item Resource Usage register ADCD ADCON Single Free run Operation mode TPAD Wakeup 92 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual En Chapter 3 3 6 1 Features E 8 channel single end analog inputs XP YP touch panel input and general analog input share with ADINO 1 6 channel ADIN2 7 and GPIO share with PORTC2 7 E 2 channel differential mode inputs touch panel pin E Supprts 4 wire resistance touch screen pen down detection and XY coordinates measurement m 12 bit SAR ADC Block e 12 bit SAR ADC e Up to 32kHz sampling rate e No miss code 11 bits e External reference supply VREF e Provide LG VREF internal reference for
100. larity and the clock phase should be identical for the master device and the slave device involved in the communication link The transfer format from the master may be changed between transfers to adjust to various requirements of a slave device For master a transfer begins when data is written to TDBR and ends when TCF is cleared For slave with CPHA 0 a transfer starts when SS goes low and ends when SS returns high In this case SPIF is set at the middle of the last SCK cycle when data is transferred from the shifter to the parallel data register but the transfer will keep on going until SS goes high On the other hand for slave with CPHA 1 a transfer starts with the first active edge of SCK and ends when TCF is cleared at the sampling edge of the last SCK cycle When each transfer is completed the TCF will be cleared and an interrupt will be generated if the SPI interrupt is enabled Refer to Section 2 10 3 4 Interrupt Flag Register O INTFO for more details eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 111 Chapter 3 En EE 3 8 6 SPI Timing Diagrams 3 8 6 1 SPI Master Mode Timing Diagram SCK CYCLE Pee WEE ER eS es Data write to i TBDR TXS eweca LP LP LE LE Ly Ly Lp cme SLUF Ly Lal we cm co I Li Li Li LE LE LE LE Lee n E CH ES EE HB Sample Strobe A A A 4 A A 4 4 TCF d i TI Figure 3 19 SPI Master Mode Timing Diagram 112 e Peripheral Control eSL eSLS Seri
101. lave Mode Operation vcascsaisvenasscenntaeacevsensvecexensentenssnendssunceavinnaciussnetncennwwes 116 3 8 9 SPI Master Initial Flow CMa rt EE 117 3 8 10 SPI Boot Flash Interface and SPI Data Flash Interface 117 3 5 1T aam obti imo d gh cui A aaa 118 3 9 Microphone Front End eSL and eSLZ000 only sees 119 SH TU eegent EES EeuEEE 119 DZ El c 122 SVG TAD Pad Aree Cir sans x digna 123 3 10 1 CMOS Pad Cofiguration Diagramas iussit pe etapa pete Mea esti Sesiones 124 3 11 General Purpose Input Output cruna dini ita 128 CNN AU uo err EUN 128 3 11 2 T O Port Register Descriptions sesion pnscse ein 129 3 11 3 Input Mode with Pull Up Resistor Delay Tume eese 132 3 11 4 VO Port Application Examples 132 3 12 Voltage Regulator 5V 3V aaa 134 Chapter 4 137 Electrical Characteristics 137 4 1 CPU Voltage Frequency tegen 137 4 2 Absolute Maximutii Ratings os amassado ga i i a iaia 138 421 CS Lica eS EE 138 42 E Ri O E 138 46 DC Cae SCE RET 139 4 3 1 POPES EE E A E 139 4 3 2 For eSL and eSLS E 140 4 3 3 Eegeregie 141 Chapter 5 143 vi e Contents eSL eSLS Series eSLZ000 User s Manual En Contents Application Circuits 143 D TEE EE 143 5 2 eSLS Application COU 144 5 3 SLZ000 Application COIEGUEL s uei is pri teerien ss eeen E EAE dead
102. le Disable Disable Disable Disable Except eSLS Do NOT use software to enable the interrupt in the eSLS ICs register Otherwise the whole system will reset when interrupt occurs 2 10 3 3 Interrupt Enable Register 1 INTE1 The INTE register is used to enable or disable external and internal interrupts B INTE Attributes and Definitions Bit DIR Description Reset Value Remarks Except esLS Except esLS Do NOT use software to enable the interrupt in the eSLS ICs register Otherwise the whole system will reset when interrupt occurs 54 e Architecture eSL eSLS Series eSLZ000 User s Manual Chapter 2 2 10 3 4 Interrupt Flag Register O INTFO The INTFO register is used to identify and clear active interrupts You must enter the interrupt subroutine to clear the interrupt flag eSL and eSLS chips will not do this automatically B INTFO Attributes and Definitions Description bad Remarks EXINTIFO 1 Interrupt flag is set 0 Clear TIFO 1 Interrupt flag is set 0 Clear 1 Interrupt flag is set 0 Clear 0 1 Interrupt flag is set 0 Clear oo 1 Interrupt flag is set 0 Clear 0 1 Interrupt flag is set 0 Clear oo 1 Interrupt flag is set 0 Clear nu EXINTIF1 1 Interrupt flag is set 0 Clear o RTCIFO 1 Interrupt flag is set 0 Clear nu RTCIF1 1 Interrupt flag is set 0 Clear nu RTCIF2 1 In
103. leared Power voltage VBORt VBOR lt gt lt pe Reset not work yet Reset is High i Warm up timer Start Figure 2 24b Brown Out Reset BOR Timing Diagram 48 e Architecture eSL eSLS Series eSLZ000 User s Manual En Chapter 2 2 9 System Mode Operation ELAN eSL Series system operates in five different modes i e RESET FAST SLOW GREEN and SLEEP modes The key scheme of the system mode operation is to allocate the system clock source or slow down clock frequency as required for each mode of operation By selecting optimal clock frequency strategy for a given mode the power consumption is further reduced by getting rid of unnecessary power utilization The following pages will describe each of the operation modes in detail The transition between the modes is not without restrictions Proper transitions among these modes are illustrated in the figure below 2 9 1 Block Diagram Reset Reset Release Set SMC 01X GREENMode 01X SLOWMode 001 Set SMC 01X To GREEN Mode Wake up Set SMC 1XX Set SMC 1XX SLEEP Mode 1XX Figure 2 25 ELAN eSL Series Modes Switching Operation Diagram 2 9 2 Operation B RESET mode During reset all I O registers are reset to their initial values and the program re starts execution from the Reset Vector 0x0000 WB FAST mode The eSL Series CPU and all on chip peripheral modules run under the sy
104. levels ni priority High Low m 2 priority Natural Order When two or more registers are all set with equal High Low priority priority is then determined by Natural Order that is in according with their bit value As indicated in the table below Bit 0 has the highest priority and Bit 16 the lowest B INTPO Attributes and Definitions Reset Value INTPO Bit DIR Description Remarks o o o o jo eo moer bg Rw RTCIP3 11 R W PWMDIP 12 PWMPIP 13 W SPIP 14 Do NOT use software to enable the interrupt in the eSLS ICs register Otherwise the whole system will reset when interrupt occurs 9 O jo jo o 4 e e o w R R R R R R R R R R R R R O 0 0 0 Except esLS 2 10 3 7 Interrupt Priority Register 1 INTP1 B INTPIAttributes and Definitions Reset Value Remarks INTP1 Bit Description WDTIP 0 SPLIMIP 1 RW ADIP 2 RW Except eSLS PDTIP 3 Except eSLS Do NOT use software to enable the interrupt in the eSLS ICs register Otherwise the whole system will reset when interrupt occurs 56 e Architecture eSL eSLS Series eSLZ000 User s Manual Pz Chapter 2 2 11 External Interrupt ELAN eSL Series support external interrupt with wake up function The I O pins are PortA 10 and 11 The external interrupts can wake up both in GREEN and SLEEP modes Refer to Section 2 7 3 C
105. lock Clock source T2 source T3 Figure 3 9 Clock Source Selection Once the counter is started restarted the circuit wait for a falling edge on the clock signal internally or externally to start counting The counter is modified at the clock rising edge When the counter starts at arrival of the pertinent selected clock the first counter clock may not be counted because the first falling edge is used for synchronization and counter preparations 3 3 2 5 Timer 2 3 Registers B Timer 2 Capture and Compare TCCR2 Register Attributes and Definitions TCCR2 Bit DIR Description Reset Value TCCR2 7 0 Timer 2 Capture and Compare Registers B Timer 2 Counter TCNT2 Register Attributes and Definitions TCNT2 Bit DIR Description Reset Value TCNT2 Do R Timer2 Counter Registers 80 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 B Timer 2 Control TCON2 Registers Attributes and Definitions TCON2 Bit Description Timer Enable this bit enables or disables Timer functions 0 Disable Stop 1 Enable Start Timer counter clear TCNT TC2 6 0 No effect 1 Clear TCNT When TM2 0 Compare 00 No output at compare match TIF2 01 Output toggles to the TCCP pin and reset TCNT at TCCR compare match TIF2 10 Output toggles to the TCCP pin at TCCR compare match TIF2 TVIF2 11 Output simple PWM to the TCCP pin at TCCR compare match TIF2 TVI
106. m6 YO gt TOS SP 1 gt SP SP 1 gt SP TOS gt Rn SP 1 gt SP TOS gt IO Addr SP imm6 gt SP SP imm6 gt SP 1 1 N A IM A IM Ah IM a E E E E E E E B R3 Rt gt Rd 1 1 Rs gt R3 imm6 1 1 E E E i Using RPT instruction to perform this operation only needs 1 cycle eSL eSLS Series eSLZ000 User s Manual Instruction Set Summary e 149 Chapter 6 6 2 2 Arithmetic Operation Instructions ADD ADC SUB SUBB MUL SS D Rs Rt SS D Rs Rt SS D Rs Rt SS D Rs Rt SS D Rs P Rt SS D Rs P Rt SS D Rs P Rt SS Rs S Rt S 3 D Rs S Rt S gt D Rs S Rt S gt D Rs S Rt S gt D Rs S P Rt S gt D Rs S P Rt S gt D Rs S P Rt S gt D 1 2 1 1 2 1 amo eta ae Operation wic I N z lv C yntax Rd Rs Rt Rs Rt gt Rd 1 1 Rd Rs Rt Rs Rt gt Rd 1 1 Rd Rs Rt Rs Rt gt Rd 1 1 Rd Rd imm6 Rd imm6 gt Rd 1 1 Rd Rs imm16 Rs imm16 gt Rd 2 2 mm Rd Rs imm16 Rs imm16 gt Rd 2 2 Rd Rs RAM16 Rs addr16 gt Rd 2 2 Rd Rd 1 2 Rd 11 Rd Rd 13 Rd 1 1 Rd Rs Rt C Rs Rt C gt Rd 1 1 Rd Rs Rt C Rs Rt C gt Rd 1 1 Rd Rs Rt C Rs Rt C gt Rd 1 1 Rd Rd imm6 C Rd imm6 C gt Rd 1 1 Rd Rs imm16 C Rs imm16 C gt Rd 2 2 Rd Rs imm16 C Rs imm16 C gt Rd 2 2 Rd Rs RAM16 C Rs a
107. mer no reset and output square waveform to PORTA7 include interruptvector def POWERON RO 0x0080 Set PORTA7 output IO PDIRA RO RO 0X0002 IO WDTCON RO Clear WDT timer RO 0x8000 IO WDTCON RO enable WDT Disable overflow no reset clock source 32768 4 BS IO SR GII Enable GIE BS IO INTE1 WDTII Enable WDT interrupt Delay Main loop JMP Delay Lr Lr Watchdog interrupt function WDTINT PUSH IO SR BTG IO PORTA 7 PA7 Toggle output plus wide 1 32768 4 s 122us BC IO INTF1 WDTIF POP IO SR ETI o eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 65 Chapter 3 En 3 2 Real Time Clock RTC Real Time Counter generates the necessary time delay for stable clock from 32K oscillator circuit An RTC unit works with an external 32 8k 32 768 kHz RC X tal oscillator and has the following features B Low power W Real Time Clock Interrupts These Operating modes are determined by setting the appropriate bit in the RTCCON Control register as explained in Section 3 2 2 Real Time Clock Control Register B The Real Time Clock Attributes and Resources Item Resource 3 2 1 Real Time Clock and Interrupt Block Diagram E 15 Bit Real Time Clock F32k RTCIFO RTCIF1 RTCIF2 RTCIF3 Figure 3 2 RTC and Interrupt Block Diagram 66 e Peripheral Control eSL eSLS Series eSLZ
108. ng falling both edge of RTC clock at Green mode When RTC wake up takes place from Green or Sleep mode to Fast mode and RTC interrupt enable flag is set the RTC interrupt is invoked at the same time The following are the equations on RTC wake up period 1 1 T Wakeup _ period if gt TWarm up gt Case a 2Frrcx 2 Frrrcx 1 TE TWakeup _ period if TWarm up gt Case b Frrcx 2Frrcx T ead plo er Case c Wakeup _ period 1 Warm up l Warmup Case c 2 Frrcx 2 Frrcx Where 1 Twakeup_ period 18 the wake up period at different conditions 2 Twarm up Warm up time is a variable that can be set by WUPS in CPUCON control register 3 Frrcx is the Frequency of RTCO 3 B Case a Timing Diagram RTCS0 00 and WUPS 00 Interrupt Occurs Interrupt Only By Rising Edge Occurs Interrupt Timing at Fast Slow mode 1 2F prox 64ms q gt T wakeup period 2F rcx gt WKUP By WKUP By WKUP By Rising Edge FallingEdge Rising Edge Warm Up Interrupt Timing at Green mode 32 001ms 32 001ms 48 h Warm up Process Sleep Warm up Process Sleep Figure 3 3a RTC Wake up Timing Diagram in Case a 68 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 B Case b Timing Diagram RTCS1 11 and WUPS 00 Interrupt Occurs Interrupt Interrupt Only By Rising Edge Occurs O
109. oad Register TRLO 1 Figure 3 5b Timer0 1 Function Block Diagram 3 3 1 3 Timer0 1 Control Register B Timer0 Reload TRLO Register Attributes and Definitions TRLO Bit Description ck Reset Value Used to store the auto reload value 8 bit of TimerO TRLO 7 0 B Timer0 Control TCONO Register Attributes and Definitions TCONO Bit DIR Description Reset Value Timer Enable this bit enables or disables Timer function H9 FUN 0 Disable Stop 9 1 Enable Start Clock divider of PLL clock source 000 Fp1 32 001 Fp 64 010 Fp1 128 2 0 R W 011 Fp1 256 000 100 Fp 512 101 Fp 1024 110 Fr 2048 111 Fp 4096 B Timer Reload TRL1 Register Attributes and Definitions TRL1 Bit DIR Description Reset Value Used to store the auto reload value TRL1 7 0 0x00 pre a 8 bit of Timert 72 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Chapter 3 B Timer Control TCONI Register Attributes and Definitions Bit TCON1 TEN1 15 R W RW 3 3 1 4 Examples DIR Timer Enable this bit enables or disables Timer function O Disable Stop 1 Enable Start Clock divider of PLL clock source 000 001 010 011 100 101 111 Description Reset Value Fe 32 Fpr 64 Fei 128 Fp1 256 FpL 512 Feu 1024 110 Fert 2048 a FpL 4096 000 RO IO 1 OX
110. peration the match signal does not clear the counter TCNT even if it generates a match interrupt similar to that of Interval mode This is because the match signal does not clear the counter value and the timer can run up to the overflow of counter value and generates an overflow interrupt at the same time After the counter value overflows the value will be counted from 0000h again TCNT is cleared by compare match or user command Set Timer Overflow Interrupt Flag TVIFx Clock source 8 bit Timer Counter gt TCNTx 8 bit comparator Capture Compare Register TCCRx Figure 3 8a Compare Mode Operation Block Diagram Set Timer Interrupt Flag TIFx To TCCPx Pin output In Interval mode a match signal should be generated when the counter value is identical to the value written in the timer Capture Compare register TCCR The match signal can generate a timer interrupt and clear counter value When a match condition occurs the timer output TCCP will be toggled 78 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Chapter 3 The Compare Timing diagram at right a shows an example of toggle output in Interval mode A match signal should be generated when the counter value is identical to the value written in the TCCR register The match signal can generate a timer match interrupt and clear the counter value When a match condition occurs the Timer Output TCCP is to
111. pheral Control e 123 Chapter 3 En 3 10 1 CMOS Pad Cofiguration Diagrams 3 10 1 1 CMOS Schmitt Trigger Input Pad with Pull Up Resistor PAD X S Figure 3 24a Input Pad with Pull Up Resistor 3 10 1 2 CMOS Schmitt Trigger Input Pad with Pull Down Resistor PAD Figure 3 24b Input Pad with Pull Down Resistor 3 10 1 3 CMOS Schmitt Trigger Input Output Pads OE I Figure 3 24c Input Output Pads NOTE OE is active high when OE 1 gt PAD 124 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 3 10 1 4 CMOS Input Output Pads with Pull Up Resistor PortB Figure 3 24d Input Output Pads PortB NOTE PORTB GPIO OE is active high when OE 1 gt PAD PU is active high when PU 1 Resistor ON 3 10 1 5 CMOS Input Output Pads with Pull Up Resistor PortC Figure 3 24e Input Output Pads PortC NOTE OE is active high when OE 1 gt PAD MOD is active high when MOD 0 PADO when MOD 1 Analog input PU is active high when PU 1 Resistor ON eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 125 Chapter 3 3 10 1 6 CMOS Output Only Pads PAD Figure 3 24f Output Only Pads 3 10 1 7 CMOS Input Output Only Pads OE PAD I Figure 3 24g Input Output Only Pads 3 10 1 8 Touch Panel Detection Pads Figure 3 24h Touch Panel Detection Pads NOTE SW 1 Switch ON XN_PAD Out SW 0 Switch OFF 0 gt Out 126 e Peripheral Control e
112. pt B The hardware reset interrupt is fixed by and for ELAN internal use only It cannot be change in the field Its interrupt source is Hardware pin reset and its interrupt vector is address 0x0000 W The reserved interrupt are reserved for future expansion of special function interrupts with eSL and eSLS ICs upgrade It may be used for user defined interrupt function together with user defined interrupt source in the program E The remaining special function interrupts are detailed in the following pages Each special function interrupt has its own interrupt source When using these interrupts be sure to initially enable Status Register Bit 15 GIE The Status Register Bit 15 SR 15 is the Global Interrupt Enable GIE bit explained in Section 2 4 5 Status Register SR It must be set to 1 for the interrupts to be enabled If reset all maskable interrupts are disabled The GIE bit is cleared by interrupts and restored by the RETI instruction e GIE I Interrupts enabled e GIE 0 Interrupts disabled 2 10 3 1 Interrupt Control Registers INTEO and INTEI are the Interrupt Enable registers for special function interrupt Through setup the interrupt source signal emission may be forbidden or permitted see next Sections 2 10 3 2 and 2 10 3 3 for more details INTFO and INTFI are the Interrupt Flag registers used to identify and clear active interrupts You must enter the interrupt subroutine to clear the interrup
113. pt wake up Timer2 3 capture mode PA 9 8 External Interrupt 0 1 PA 11 10 SPI wake up PA 15 and Touch PAD pen down detection XP YP XN YN 50 e Architecture eSL eSLS Series eSLZ000 User s Manual En Chapter 2 2 9 5 System Mode Operation Examples It is strongly suggested that to use the library on system mode i e FASTMODE SLOWMODE GRENMODE and SLEEPMODE Refer to the library guide see eSL Series C Macro Reference Manual and eSL Series Assembler Reference Manual for further detailed information The folowing shows an example SLOWMODE RO R1 R2 GREENMODE After wake up RO R1 R2 SLEEPMODE After wake up R4 R2 RS FASTMODE 2 10 Exception Handling Exception handling may be required by a Reset a Trap Instruction TRAP or by Interrupts 2 10 1 Reset A Reset has the highest exception priority Exception handling starts as soon as the Reset is cleared by the RESET pin The chip is also reset when the watchdog timer overflows and exception handling starts Exception handling is the same as exception handling by the RESET pin 2 10 2 Trap Instruction TRAP Exception handling starts when a trap instruction TRAP is executed The TRAP instruction generates a vector address corresponding to a vector number as specified in the instruction code Exception handling can be executed all the time under program execution state 2 10 3 Interrupts
114. r controlled by I O instruction to support either fractional or integer results Under the fractional operation the result is shifted one bit to the left Under the integer operation the result is not shifted L 17X17 MUL a S S6R Shifter Kg 32 Bit Accumulator 16 bit Adder 16 bit ALU OP Select R1 Figure 2 16 DSP Architecture Diagram The same multiplier is used to support the MAC and MAS instructions The 16 bit adder combines with 16 bit ALU to perform 32 bit operations 36 e Architecture eSL eSLS Series eSLZ000 User s Manual Chapter 2 Division is more complex than multiplication Some algorithms use division a lot Hence the eSL Series implemented the division in hardware For low cost implementation where the chip size must be minimized Sequential Division architectures is applied The most common techniques used in Sequential Division are the Restoring Divide and Non Restoring Divide The restoring division has timing issues problem For this reason eSL Series implemented a Non Restoring conditional add subtract division architecture The division can be signed or unsigned To perform the division R1 and RO store the 32 bit dividend Rs stores the 16 bit divisor then execute the following operation refer to Figure 2 17 below 1 Use XOR result to determine if the dividend should be added to or subtracted from the divisor
115. rst sector SPI_WREN Enable SPI write SPI PPGM WORD 0 0 0x8 SPI Temp Data Write 8 word data form RAM to SPI device 0x00 0x07 SPI WRDI Disable SPI write Delay Main loop JMP Delay 118 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual En Chapter 3 3 9 Microphone Front End eSL and eSLZ000 only The eSL and eSLZ000 have an on chip Microphone Front End MIC circuit consisted of an Amplifier and an Automatic Gain Control AGC which are designed for Voice Recorder amp Speech Recognition application When AGC is disabled AGCEN 0 this circuit will become a two stage OP Amplifier for other applications e g sensor amplifier current amplifier analog filter etc AVDD 2 2K AGCEN AMPEN 10u 77 470 l AGC luo REF MICIN da ps 1n 77 n 22uF 68K Lm Figure 3 23 Microphone Front End Block Diagram B Microphone Frnot End Attributes and Definitions Item Resource Usage register MICCON I O function pin MICIN VREF AMPO AGC Operation mode Auto Gain control 3 9 1 Registers B MIC Control Registers Attributes and Definitions Description Reset Value Amplifier enable AGC enable Gain selection 00 Max gain 01 2 gain 10 3 gain 11 Min gain eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 119 Chapter 3 p BE AMPEN
116. s eSLZ000 User s Manual Gia 2 11 2 Application Examples aci 2 12 Stack Pointer Limit GPULIM ZAZA General DIGSeHIDDOL sr 2 12 2 Block Dig Oram ana 2 12 3 Register A RRE ER ERR e E Chapter 3 Peripheral Control 3 1 Watchdog Timer WDT aiar AJ Block Dafne 3 1 2 Watchdog Control Beglster ia cse eroi onis retina ns 3 1 3 Examples CET 3 2 Real Time Clock RI parasitas n pn n a Er nds 3 2 1 Real Time Clock and Interrupt Block Diagram 3 2 2 Real Time Clock Control Register Scie Ri E liu 3 3 1 KEE RR KE E 3 4 Pulse Width Modulation PWM i Al Ice 3 4 2 Block Diagram lalla 3 4 3 Operation Ms LEE MuR E T T Vo ade 3 5 Digital to Analog Converter DACI E NR e A EEEE EEEE 300 2 EEN Povia 3 5 4 Application E Dis JERAMIDIES c 3 6 Analog to Digital Converter eSL and eSLZ000 only sl Uu c r EA 3 60 27 CET I UU Tm UU m 340 3 OP aa 37 Data ROM ao anen n E ENTE EEES Lil ala eSL eSLS Series eSLZ000 User s Manual Contents Contents ev Contents En 3 Bl k Eeer eege 100 il Register DeSCHQUOB seas saben d veu ple n DURO ere 101 STA EXAMPLES EE 102 3 8 Serial Peripheral Interface eSL and eSLZ000 ont 104 el Faccia 104 3 8 2 Blok Dialisi 106 5 80 Pith Destopion isprcllaaaa 106 3 8 4 SPI Registe em m 109 3 8 5 SPI Transfer Print NTC 111 3 8 6 SPI Timing Diagrams serie erp innn aa 112 3 8 7 JMaster Mode Operaio 115 3 8 8 S
117. s recommended for professional programmers only Furthermore under Case c you may use BS and BC in RAM Address 0x0000 to 0x0007 as its memory management is user definable E Cases a to d Examples RR RARA RARA ke e A Set the value of SP and SPLIM as in Case a KCKCKCkCk kCkCkCkCkck kCk ck kc kk kck ck k kk kt RO 0x0000 IO SPLIM RO SPLIM 0x0000 RO 0x07FF IO SPA RO SP 0x07FF KKK KK RARA RARA AA RA Set the value of SPAR and SPLIM as in Case b KKAKKAKAAKAAKAKAKAKAKAKAKAKAKAKAAKAKAAKAKAKAAKAAKAAKAAKAAKAAKAAKAAKAAKAAKAAKAAKAAAA RO 0x0000 IO SPLIM RO SPLIM 0x0000 RO 0x0010 IO SPA RO SP 0x0010 ARR RR AAA RARA RARA RAR A k Set the value of SPAR and SPLIM as in Case c kkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkkxkxkxkkxkxkkxkkxkxx k RO 0x0500 IO SPLIM RO SPLIM 0x0500 RO 0x07FF IO SPA RO SP 0x07FF BRR ARA A ke Set the value of SPAR and SPLIM as in Case d DR A A RO 0x07F0 IO SPLIM RO SPLIM 0x07F0 RO 0x07FF IO SPA RO SP 0x07FF 62 e Architecture eSL eSLS Series eSLZ000 User s Manual En Chapter 3 Chapter 3 Peripheral Control 3 1 Watchdog Timer WDT The eSL Series chips are equipped with internal Basic Watchdog Timer This timer is used to resume controller operation after being disturbed with noise system error or ot
118. ss is contained in the 16 LSBs of a 2 word instruction Rd or Rs specifies the destination or source register respectively Example R RAM8 RAM Space Banked OP RAM Direct Add 256 Figure 2 9a RAM 8 Bit Data Direct Addressing Example R RAM16 OP Rd Rs Direct Address RAM Space 65535 22 e Architecture Figure 2 9b RAM 16 Bit Data Direct Addressing eSL eSLS Series eSLZ000 User s Manual 2 3 7 Immediate Addressing Chapter 2 A 16 bit program address is contained in the 16 LSBs of a 2 word instruction Example CALL label and JMP label ROM Space OP Absolute Address Figure 2 10 Immediate Addressing 2 3 8 Relative Program Addressing 65535 Program execution continues at Address PC offset 1 The offset is contained in the instruction word Short conditional branch instructions can only get to locations 256 to 255 from the current address However Long Branch instructions can reach the entire program memory from every location ROM Space Program Counter OP Offset address 65535 Figure 2 11 Relative Program Addressing eSL eSLS Series eSLZ000 User s Manual Architecture e 23 Chapter 2 2 3 9 Data Indirect Addressing with Displacement Operand addr
119. stem clock Fsys The system clock frequency can be selected from frequency divider In FAST mode the power consumption is maximized eSL eSLS Series eSLZ000 User s Manual Architecture e 49 Chapter 2 B SLOW mode The SLOW mode reduces power consumption by using F32x operation clock frequency The CPU as well as the on chip peripheral modules keep on running under F32k Hz clock B GREEN mode The CPU stops running with some peripherals remaining active at RTC real time clock condition that is under F32x clock operation B SLEEP mode This is a very low power mode of operation in which the CPU and all peripherals stop running All internal registers and RAM retain the value before SLEEP mode is implemented This mode is occassionally also known as STOP mode ELAN eSL Series are awaken from both GREEN mode and SLEEP mode by a reset wake up external wake up or by an interrupt wake up with which the CPU and all peripherals as well as the oscillator start running ELAN eSL Series are also awaken from GREEN mode by an RTC wake up 2 9 4 Registers 2 9 4 1 CPU Mode Control Register CPUCON Bit Description Reset Value System operation mode control 000 FAST mode 001 SLOW mode 01X GREEN mode 1XX SLEEP mode 2 9 4 2 Active Clock Domains and Wake up Sources under Different System Mode Operations Oscillator Wake up Source System Clock Source External wake up pin PB 15 0 S Interru
120. t D E D Rs Rt US Rs U Rt S 2 D MUL US D Rs P Ri US EEE DER PIRt US BEE D Rs P Rt US Rs U PIRt S 3D 120 SCENE 120 D Rs Rt UU R U RLUSD Im DERRI Rogo mm DERRE RoRo 31 muy PRR Rora D Rs P Rt UU Rs U P Rt U gt D 1 2 1 D Rs P Rt UU Rs U P Rt U gt D Eme D Rs P Rt UU Rs 4 U P Rt U gt D 1 2 1 l DERSE TPR RSHHIUPIRE USD uz DIV S D D Rs S p us B DIV U D D Rs sl Ra wunne D D Rs Rt D Rs Rt gt D 1 1 D D Rs Rt D Rs Rt gt D ae DEE D D Rs Rt D Rs Rt gt D oM s D D Rs Rt D Rs Rt gt D in D D Rs P Rt D Rs P Rt gt D 1 2 1 D DReFRe osere Mo D D Rs P Rt DeRse PIRH gt D 121 DEDHRS ET PIR DerecjrRej gt D v2 EE D D R amp R Dro m bp DDRS RI orsRjSD m D D Rs Rt A SE mas PEORSRRE D D Rs P RI CERERE D D Rs P Rt E T D D Rs P Rt D Rs P Rt 2 D D D Rs P Rt D Rs P Rt gt D i Using RPT instruction to perform this operation only needs 1 cycle The division instruction 1 17 16 needs 17 cycles in integer mode and 16 cycles in fractional mode eSL eSLS Series eSLZ000 User s Manual Instruction Set Summary e 151 Chapter 6 6 2 3 Logic Operation Instructions AND OR XOR ROL SHL ROR
121. t flag eSL and eSLS chips will not do this automatically see Sections 2 10 3 4 and 2 10 3 5 for more details INTPO and INTPI are the Interrupt Priority registers which determine the priority of interrupt sources There are two priority levels for the all interrupts high low and natural order priority The natural order priority scheme has 0 as the highest priority and 20 as the lowest priority Priority is compared from High to Low see Sections 2 10 3 6 and 2 10 3 7 for more details eSL eSLS Series eSLZ000 User s Manual Architecture e 53 Chapter 2 2 10 3 2 Interrupt Enable Register O INTEO The INTEO register is used to enable or disable the external and internal interrupts B INTEO Attributes and Definitions INTEO EXINTIEO TIEO TIE1 Bit e 3 RW RW RW Description Enable Enable Enable 0 Disable Disable Disable Disable Reset Value Remarks 4 RW RW Enable Enable Disable Disable TIE3 TOIE3 EXINTIE1 6 RW RW RW Enable Enable Enable Disable Disable Disable RTCIEO PWMDIE PWMPIE SPIE DROMIE 12 14 RW RW RW RW RW RW RW Enable Enable Enable Enable Enable Enable Enable S lO O 0 0 0 0 O 0 0 0 0 0 0 0 Disable Disable Disab
122. t these locations 2 8 1 Block Diagram are not used Internal Pull up Resister Power On Reset SEM Circuit POR Brown Out Reset Circuit BOR Reset Software Reset Control CPUCON register eee 32K Oscillator Circuit Watch Dog Timer WDT Reset By POR a mel 10 Bit Internal Reset Figure 2 21 Reset System Block Diagram eSL eSLS Series eSLZ000 User s Manual Architecture e 45 Chapter 2 ps 2 8 2 Operation The following initialization takes place after a RESET occurs B The oscillator continues to run or will be started W The Watchdog timer is cleared B When power on reset or RESET pin is at low condition the SMC bits are set to 000 at FAST mode E The program counter PC is cleared to all 0 RESET Warm up TimeOut Internal Reset a External ResetDuring Operation RESET Warm up TimeOut Watch Dog Overflow Internal Reset b Watch Dog Overflow ResetDuring Operation Figure 2 22 Reset System Timing Diagram 46 e Architecture eSL eSLS Series eSLZ000 User s Manual Pz Chapter 2 2 8 3 Power On Reset POR The power on reset circuit holds the device at reset state until VDD is greater than the VPOR Power on reset voltage Otherwise if the voltage supply is lower than the power on reset voltage a reset will occur RESET Timer Warm up Overflow Time Out Int
123. terrupt flag is set 0 Clear oo RTCIF3 1 Interrupt flag is set 0 Clear 0 PWMDIF 1 Interrupt flag is set 0 Clear nu PWMPIF 1 Interrupt flag is set 0 Clear nu 1 Interrupt flag is set 0 Clear nu Except eSLS DROMIF 1 Interrupt flag is set 0 Clear oo SPIF SPI Transfer Complete Flag This status flag indicates that the received data has been placed in the RDBR and is ready to be read H W set S W cleared 0 Transfer is not completed 1 Transfer is completed and the Interrupt flag register is set 2 Do NOT use software to enable the interrupt in the eSLS ICs register Otherwise the whole system will reset when interrupt occurs 2 10 3 5 Interrupt Flag Register 1 INTF1 The INTFI register is used to identify and clear active interrupts You must enter the interrupt subroutine to clear the interrupt flag eSL and eSLS chips will not do this automatically B INTFI Attributes and Definitions Description 1 Interrupt flag is set 0 Clear Do NOT use software to enable the interrupt in the eSLS ICs register Otherwise the whole system will reset when interrupt occurs 1 Interrupt flag is set 1 Interrupt flag is set 0 Clear oo Except esLS 1 Interrupt flag is set 0 Except esLS eSL eSLS Series eSLZ000 User s Manual Architecture e 55 Chapter 2 Ve 2 10 3 6 Interrupt Priority Register 0 INTPO INTP register determines the priority of interrupt sources in two priority
124. that the SPLIM will restrict the SP from going under Address 0x0000 default value If the SPA value equals that of SPLIM interrupt will occur It alerts programmer that SPA operation is overused However for large SPA dynamic range as in this case such condition rarely occurs If for some reasons you have indeed overused the RAM memory error will result with the SPA value and the program control flow B Case b In this case the SPA dynamic operation range area of RAM memory is located at lower address and is separated from the area for user general usage This arrangement is fine for RAM memory allocated to user usage but for SPA dynamic operation range the area is not big enough Taken for granted that the area is still adequate for SPA dynamic operation range the area nonetheless will not be able to accommodate the BS and BC instructions which need RAM Address 0x0000 to 0x0007 to operate This is because its memory management is dynamic eSL eSLS Series eSLZ000 User s Manual Architecture e 61 Chapter 2 ps B Case c amp d The best arrangement for SPA and SPLIM is illustrated in Case c where you already know how much SPA dynamic operation range is needed by setting SPLIM not SP and use the remaining and most of the RAM memory for your general usage However if you provide inadequate space for SPA dynamic range as in Case d SPLIM interrupt will occur frequently Therefore Case c must be used carefully and i
125. troduction e 13 Chapter 1 1 6 5 4 Port D Attributes and Definitions eSL and eSLZ000 only Description General purpose output function pin with high drive current 1 Tg delay General purpose output function pin with high drive current 5 Tg delay General purpose output function pin with high drive current 2 Tg delay General purpose output function pin with high drive current 6 Tg delay General purpose output function pin with high drive current 3 Tg delay General purpose output function pin with high drive current 7 Tg delay General purpose output function pin with high drive current 4 Tg delay General purpose output function pin with high drive current 8 Tg delay i Tg 4 nano second for low noise design consideration 1 6 6 Data ROM Interface eSLZ000 only DROMA 23 0 DROMD 15 0 Description External Data ROM memory address bus External Data ROM memory data bus WEB External Data ROM write enable output External Data ROM read enable output External Data ROM chip select output 1 6 7 ICE Interface eSLZ000 only B ICE Interface Attributes and Definitions Description Test clock 14 e Introduction Test mode select eSL eSLS Series eSLZ000 User s Manual Chapter 1 B Boot Attributes and Definitions BTSCLK SYSMODI0 SYSMOD 1 ICEMOD eSL eSLS Series eSLZ000 User s Manual Description
126. ture e 29 Chapter 2 2 5 1 Logic and Mathematic Instructions The eSL Series has a full set of 6 bit 1 word and 16 bit 2 words logic and mathematic instructions j WD General 5 Purpose gt Rd Registers y Rs Rt SCH SCH Y 4 Y Y Y q Negate ALU OP Status Register Figure 2 14 The ALU unit B Logic and Mathematic Instruction Definitions Mnemonic Description Operand compare fe O 30 e Architecture eSL eSLS Series eSLZ000 User s Manual Mnemonic IF CC JMP Chapter 2 2 5 2 Conditional Branch Instruction Conditional jumps support program branching relative to the program counter The numeric range of short condition branch is 9 bit offset values 256 to 255 Long range condition branch can reach from 0 to 65 535 but it needs two words instruction The condition branch instructions that are supported by the eSL are shown in the following table When an specified condition is met a signed 9 bit is added to the value in the program counter or the program counter is replaced by 16 bit absolute address B Condition Branch Instruction Definitions Description Operation Comment Jump if carry C clear If C 0 then jump to PC n 1 IF CS JMP Jump if carry C set If C 1 then jump to PC n 1 p Jump if overflow V clear If V 0 then jump to PC n 1 Simple Jump if overflow V set If V 1 then jump to PC n
127. ture eSL eSLS Series eSLZ000 User s Manual En Chapter 2 2 12 Stack Pointer Limit SPLIM 2 12 1 General Description Generally the Stack Pointer Address SPA register is used as the last address pointer of RAM when the system is at the initial state of general application So it is very rare that the SPA register value is exceeded to less than or equal to Address 0x0000 of RAM In special cases such as in Cases c and d in the following block diagram you will not use the Stack Pointer SP to point to the last address of RAM or SPLIM but rather point the SP away from SPLIM to spare more RAM memory for data variable use Under this condition the Stack Pointer Limit SPLIM is used to limit the value of SP in order to optimize memory management eSL eSLS Series eSLZ000 User s Manual Architecture e 59 Chapter 2 2 12 2 Block Diagram RAM Space SPLIM g 22 0x0000 1 LLL SR SP 0x07FF Ox 1 FFF Case a General case initial state 1 SP dynamic range SP 0x0000 2 No Data usable range RAM Space 0x0000 2 pL Ox0500 EEE Case c Professionalcase initial state 1 SP dynamic range SP SPLIM 2 Data usable range SPLIM 1 0x0000 RAM Space SPLIM ELL LLL LLLLLLLM 00000 Seege SP ESS SSS SSE 00010 A i 2 Y 0x07FF Ox1FFF Case b SP near the start address initial state 1 SP dynamic range SP 0x0000 2 Data usable range 0x07FF
128. ut capture at rising edge of the TCCP pin 01 Input capture at falling edge of the TCCP pin 1X Input capture at rising and falling edges of the TCCP pin Selects the TCCR function 0 TPPR functions as an output compare register 1 TCCR functions as an input capture register n Fou 132 Feit 64 i FPLL 128 a Feu 024 Fou 4096 TEXI3 rising edge TEXI3 falling edge Timer 2 3 combine 82 e Peripheral Control eSL eSLS Series eSLZ000 User s Manual Pz Chapter 3 3 3 2 6 Examples Set Timer2 to compare mode toggle TIMO 01 TCCP2 PA8 to output waveform POWERON RO 0x0100 IO PORTA RO Set PORTA8 TCCP2 output RO 0x0040 CLEAR Tcount2 IO TCON2 RO RO 0x0001 One plus time 1 16384000 256 0x01 1 s 3lus IO TCCR2 R Set compare value RO 0x8010 IO TCON2 RO Timer2 Enabled compare mode TIMO 01 output toggles clock source Fpll 256 _Delay Main loop JMP Delay eSL eSLS Series eSLZ000 User s Manual Peripheral Control e 83 Chapter 3 En 3 4 Pulse Width Modulation PWM This module provides one channel 10 bit PWM waveforms generator It has a programmable period and a programmable duty cycle as well as a dedicated counter In particular this PWM module supports audio speaker power and motion control applications 3 4 1 Features e 10 bit glitch less Double Buffer PWM output e PWM resolution is adjusted by P
129. ut result N I The result of the operation is negative N 0 The result of the operation is not negative B Test T Flag T 1s used by Bit test operation instruction BTEST T 1 The tested bit is 1 T 0 The tested bit is O eSL eSLS Series eSLZ000 User s Manual Architecture e 27 Chapter 2 En E Fractional Integer F I Flag F T is used to indicate Fractional or Integer mode F I 1 Fractional mode F I 0 Integer mode BW Shift 6 Bit S6R Flag S6R is used to indicate Shift 6 bit or otherwise S6R 1 Right Shift 6 bit S6R 0 Left Shift 0 bit F I 0 Left Shift 1 bit F I 1 B Saturation Mode SME Flag SME is used to indicate Saturation mode status SME 1 Saturation mode enabled SME 0 Saturation mode disabled B Global Interrupt Enable GIE Flag The Global Interrupt Enable bit must be set to 1 for the interrupts to be enabled If reset all maskable interrupts are disabled The GIE bit is cleared by interrupts and restored by the RETI instruction GIE 1 Interrupts are enabled GIE 0 Interrupts are disabled 2 4 5 1 Division and Multiplication Modes S6R F I Division Multiplication Po o Integer eer Fractional Fractional ractiona Left Shift 1 bit Integer Right Shift 6 bit 2 4 5 2 ALU Saturation Mode 16bit SME Overflow V Carry C ALU Output i o o AuOWu i 1 pn 0411111111111111 1000000000000000 28 e Architecture eSL e
130. wer supply for D A Avss P OV Negative power supply eSLS Series only External reference voltage input pin for A D and MIC eSL and REF P N eSLZ000 only aii i RVIN P 5V Regulator voltage input RVOUT P 3V Regulator voltage output 3 0V 10 e Introduction eSL eSLS Series eSLZ000 User s Manual Chapter 1 These power pins must connect to the same VDD and VSS as IOVDD PB and IOVSS PB These power pins must connect to the same VDD and VSS as AVDD_DA and AVSS_DA 1 6 2 System Control Description RSTB is the low active global reset input Test mode select pin High active Internal pull down For chip internal test only Connected to VSS normally Xtal or RC oscillator connecting pin RC or X tal selection is by OSCS pin O X tal oscillator connecting pin RC or X tal selection O RC 1 X tal I PLL loop filter capacitor This pin has an internal pull up 150KQ resistor refer to Chapter 5 Application Circuit This pin must connect a 47nF capacitor to ground refer to Chapter 5 Application Circuit 1 6 3 DAC Output Name Type Description DACO O Current D A output pin 1 6 4 Two Stage Amplifier amp Touch Pad Positioning Supports eSL and eSLZ000 ICs only Post Amplifier output Microphone signal input AC coupling from microphone signal Automatic Level Control adjustment pin Touch Pad positioning for X axis about negative voltage level Touch Pad positioning for Y a
131. x0000 1 0 TM3 TCS3 2 0 0x3A 0x3D Reserve Ox3E WDTCON 0x0000 WDTREN WDTPSR 1 0 DOE RTCCON 0x0000 RTC WKUP 3 0 1 RTC1 1 RTCO 1 0 0x40 SPICON 0x0000 SPIHDEN MSTR SPR 2 0 0x41 TDBR 0x0000 TDBR 15 0 0x42 RDBR 0x0000 RDBR 15 0 0x43 SPISR 0x0000 0x44 0x4F Reserve 0x50 PWMD 0x000U PWMD 15 6 0x51 PWMP Ox7FCU PWMP 15 6 0x52 PWMCON 0x0000 PWMDEN PWMVOL 1 0 PWMCLR PWM RPT 2 0 PWM MOD CENTR PWMOEN 1 0 PWMPS 1 0 DROMD 0x0000 DROM DATA 15 0 DROMLA 0x0000 DROM LA 15 0 DROMHA 0x0000 DROM HA 7 0 0x56 DROMCON 0x0000 DROMEN DROM MODE 2 0 DROM DELAY COUNT 4 0 0x57 0x5F Reserve 0x60 DACD 0x000u DACD 15 4 0x61 DACCON 0x0007 DAC2SC DACMOD 1 0 DACVOL 2 0x62 0x63 Reserve 0x64 ADCON 0x0000 PDTWK PDTEN TPEN SDB 2 0 CHS 2 0 0x65 ADCD Oxuuuu AID Conversion Data 15 4 0x66 0x69 Reserve Ox6A MICCON 0x0000 0x6B 0x6F Reserve NOTE u under Initial Value column are unknown values 158 e Instruction Set Summary eSL eSLS Series eSLZ000 User s Manual Chapter 6 A 2 List of eSLS Special Function Registers
132. xis about negative voltage level Xp ADINO Touch Pad positioning for X axis about positive voltage level Analog Input channel 0 Yp ADIN1 Touch Pad positioning for Y axis about positive voltage level Analog Input channel 1 eSL eSLS Series eSLZ000 User s Manual Introduction e 11 Chapter 1 1 6 5 I O Port 1 6 5 1 Port A Attributes and Definitions Name Function Type Description GPIO YO General purpose input and output function PWMO O PWM output O GPIO UO General purpose input and output function PWM1 O PWM output 1 GPIO VO General purpose input and output function GPIO UO General purpose input and output function PA 4 GPIO YO General purpose input and output function TEXI2 I External timer 2 clock input PAIS GPIO VO General purpose input and output function TEXI3 I External timer 3 clock input GPIO YO General purpose input and output function GPIO VO General purpose input and output function GPIO VO General purpose input and output function TCCP2 YO Timer 2 capture input or compare output GPIO UO General purpose input and output function TCCP3 UO Timer 3 capture input or compare output GPIO VO General purpose input and output function EXINTO I External interrupt 0 input GPIO YO General purpose input and output function EXINT1 I External interrupt 1 input e PA 12 SPI function in Slave Mode used as chip select input and SS I can be used as UO pin in Master Mode

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