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GFEC Stratix II F1020 User's Manual for Development Board

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1. EUER 1 E i T e Te 2 00 UG EK2SF1020 CHT200 ABAID ABRAZA o GALAXY FAR EAST CORP Name of Product GFEC Stratix II F1508 F1020 Development Board Version of the User s Manual 2 00 UG_EK2SF1020 Date of Publication May 2005 All rights are reversed No reproduce is permitted 2004 Galaxy Far East Corp All rights of any parts of this product including accessories software etc _ belong to Galaxy Far East Corp shortened GFEC in the following It is prohibited to imitate copy transcribe or translate this publication arbitrarily without 9 pa 2 X the permission of GFEC Guarantee or standing expression in any way or any other hint 1 not contained in this manual any data loss profit damage or project termination caused by using this manual or other products mentioned in it GFEC will bear no responsibility to it In addition specification and information of products mentioned in this manual are only for reference the content of it 15 subjected to change without notice To any mistake made in this manual including in the parts of hardware and software GFEC do not assume any responsibility Names of products mentioned in this manual are only for identification Since these names may be registered trademarks or copyright of other company we
2. gt E EG e t Ha mm gt gt FEE EE E Fig 3 structural diagram of GFEC Stratix II development board Doi B82 10 ZS GALAXY FAR EAST CORP 2 3 Devices compatible with FPGA specifications of devices that are compatible with Stratix II Device Family are listed in the following table2 1 The development board supports the devices above 2560 Device ALMs Equivalent M512 RAM Total DSP 18 18 PLLs LEs Blocks Blocks Blocks Memory Blocks Multipliers a gt Bits EP2S15 6 240 15 600 104 78 0 419 328 12 48 6 nxn 2530 13 552 33 880 202 144 1 1 369 728 16 64 6 Tab I Stratix Device Family All packages supported by IC of Stratix II Device Family and available I Os are listed in table 2 2 The package which can be supported by the development board is Fine BGA 1020 Pin Device F484 484 F672 F780 F1020 F1508 EP2S15 341 365 EP2530 34 409 EP2560 34 409 2590 308 534 901 25130 534 1 109 25180 1 173 Tab 2 Stratix II Package Offerings amp Users I O Counts 2 4 Power System The development board can be supplied power with the adapter attached The adapter can also accept DC 6V input s
3. VOC V33 2 bx VCCPD7 2 GNDA PLL12 2 o VCCPD7 1 GNDA PLL12 1 t vis VCCPD6 2 GNDA PLL11 2 VCCPDE6 1 GNDA 11 1 e VCCPD5 2 GNDA PLL10 2 r VCCPD5 1 GNDA PLL10 1 VCCPD4 2 GNDA PLL9 2 v VCCPDA 1 GNDA PLL9 1 T VCCPD3 2 GNDA PLL8 2 1 GNDA 1 p 2 GNDA PLL7 2 ux 2 1 GNDA PLL7 1 v5 2 GNDA PLL6 2 VCCPD1 1 GNDA PLL6 1 2 7 AM30 En 3 CNDA PUSI pn VCCIO8 2 GNDA PLL4 2 VCCIOS 1 GNDA 4 1 2 GNDA PLL3 2 VCCIO7 3 GNDA PLL3 1 VOCIO7 2 VCCIO7 1 GNDA PLL2 2 2 ry oe Er 112 VCCIO6 3 GNDA PLL1 2 2 GNDA PLL1 1 mane 1 lo pi 4 7 VCCD PLL12 pe 5 2 VCCD PLL11 5 1 VCCD PLL10 VCCD PLL9 Hep EE 4 3 VCCD PLL7 4 2 VCCD PLL6 1 VCCD PLL5 VCCD PLL4 pop t E21 4 VCCD PLL3 VCCIO3 3 VCCD PLL2 2 VCCD PLL1 VCCIO3 1 VCCA PLL12 VCCA PLL11 VCCA PLL10 VCCA PLL9 VCCA PLL8 VCCIO2 2 2 1 VCCA PLL7 gt 2 VCCIO1 3 VCCA PLL5 ESTE VCCIO1 2 VCCA PLL4 VOCIO1 1 VCCA PLL3 VCCA PLL2 VCCA PLL1 VCC PLL12 out VCC PLL6 out NT 13 NT 14 NT 15 NT 16 NT 17 NT 18 NT 19 NT 20
4. C eda altera qdesigns EP2S60F1020C5ES 00292083 FFFFFFFF Br Change Fie Save File Lis 6 Choose the files to be burned POF GALAXY FAR EAST Select Programming File Look in tutorial B sk ab simulation filtref KEN fitret spp gt Type SOF File Date Modified 10 25 2004 5 28 PM Size 1 84 MB Files of type Programming Files sof Cancel gh gt 2 5 X 7 Confirm Checksum and Device and click Program configure L filtret cat Hardware Setup ByteBlaster LPT1 Mode eda altera qdesians P2S60F7020C5ES 00292083 Bt C eda altera qdesigns EP25850F1 2 0C5ES 00292083 FFFFFFFF n Auto Detect Delete lij Change Save File Add Device Hl P Lawn 8 Start burning FARPERAD GALAXY FAR EAST filtref cdf Hardware Setup ByteBlaster LPT1 Mode JTAG Progress C eda altera qdesigns EP2S60FI020CKES 00292083 FFFFFFFF X Delete Add File BB Change File fu gt 9 5 5 3 3 2 Active Serial Programming AS If Serial Configuration Device 5165 41 5645116 is burned in
5. 0 DQS9B IO PLL6 FBn OUT2n ARTS IO PLL6 OUTOp 107 PLL ENA itle lt Title gt 2 901020 7 IO DQOB1 IO DQ2B2 IO DQ3B2 IO DQ4B2 IO DQ4BO IO DQ6BO IO DQ7B1 IO DQ9B2 IO DQ9B1 IO PLL6 OUT1p IO PLL6 OUTOn IO DQ0B2 IO DQ1B1 IO DQ1B2 IO DQSn1B IO DQ1B3 IO DQ6B1 IO DQ8BO IO DQSn8B IO PLL6 OUT1n IO CLK7p DQS1B IO DQ1BO IO DQ5B1 IO DQSn5B DQ5B3 IO DQ8B1 IO DQS8B IO DQ8B3 IO CLK7n IO DQ5B2 IO DQS5B IO DQ5BO IO DQ8B2 IO VB7NO 90 IO VB7N2 90 VB7N2 1 IO VB7N2 2 IO VB7N1 1 IO VB7N1 2 IO VB7NO 1 IO VB7N2 3 IO VB7N2 4 IO VB7N1 3 IO VB7N1 4 IO VB7NO 2 IO VB7N2 5 IO VB7N1 5 IO VB7N1 6 IO VB7NO 3 IO VB7NO 4 IO VB7NO 5 IO VB7N2 6 IO VB7N1 7 IO VB7N1 8 IO VB7NO 6 IO VB7NO 7 IO VB7NO 8 C171 0 1uF 107 6 107 107 2 107 0 107 107 107 107 107 107 6 107 107 107 107 107 107 107 107 107 107 6 107 2 107 Q 107 10 107 107 107 107 A 107 107 107 0 107 107 107 107 4 107 9 107 107 107 107 107 4 107 107 107 107 107 107 107 5 AJ6 AJ7 AJ8 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AH5 AH6 7 AH8 AH9 11 AH13 AH14 AH15 AH16 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AF10 AF11 AF12 AF13 AF14 AE9 AE10 AE11 AE12 AE13 AE14 AD10 AD11 AD12 AD13 AD14 AB1 IO7 12 7 13 4 107 orm
6. 103 026 B3 026 103 025 B3 025 104 16 B4 16 93 897 Asr 85 p 625 103 A17 103 D17 8 40 YX 8 0 8 0 D 00406 03 B27 2 B27 103 25 25 103 0 4 GLK18n his 103 018 104 D16 B4 016 IO PLL11 FBn OUT2p IO PLL11 1 gl Ba E16 03 C27 B3 27 103 F24 B3 F24 GBE A OTOI O poster Die D19 n 37 103 027 B3 027 103 E24 B3 E24 A22 A x _ non 103 020 FEN 4 98416 103 E27 4 _ B3 E27 103 C24 4 _ B3 C24 ios DGSTOnT 551 103 A23 n lO DQ13TO IO DQ12T1 103 021 lOS B17 B3 B17 103 E28 B3 E28 103 B24 B3 B24 lO3 A24 103 A24 A24 10 DQ13T3 IO DQS12T 103 022 _ 17 6 B3 C17 103 028 6 028 103_A24 6 B3 A24 103 A25 103 A25 A IO DO14TO IO DO12TO 023 103 D17 B3 D17 103 A28 B3 A28 103 F23 B3 F23 103 A26 103 A26 26 10 pDQ14T1 IO DQS15T 025 _ 18 8 0 B3 B18 103 B28 8 0 B3 B28 103 023 8 0 B3 D23 A27 IOS 27 A IO DO16TO IO DO14T2 103 D26 103 C18 9 9 B3 C18 103 C28 9 9 B3 C28 103 C23 9 9 B3 C23 103 A28 A28 A28 10 DQ16T1 IO DO16T2 103 027 103 D18 0 8 B3 D18 103 A29 0 8 B3 A29 103 B23 0 8 B3 B23 A29 IOS A29 A29 0 001711 IO 001712 228 103 028 103 D28 lOS E18 B3 E18 103 B29 B3 B29 103 A23 B3 A23 103_Bi7 IO CLK14n lO PGMO 103 E17 5 103 029 B9 C29 oua OUTODB IO PLL11 OUTin 10
7. 3 3 Software Operation Since FPGA 1 fabricated on the basis of SRAM fab the development board offers two mode JTAG SOF and AS POF to plan FPGA mode is mainly used to plan FPGA and AS mode is mainly used to burn Serial EPROM The following explains the burning operation step by step If your purpose 15 only to burn FPGA or EPROM lab and not to compile it it s not necessary for you to install the wholeQuartus II It s enough to install Quartus II Programmer Only This programme is about 20 30MB it can save some space on the hardware and doesn t occupy system resource You can operate them in the same way This programme can be download from Altera website or look it up in the installation CD supplied by GFEC 3 3 1 JTAG Presently JTAG is mainly used to planAltera Stratix II FPGA Burning file SOF which is generated by Quartus II 1s necessary for the planning In this mode data will disappear when power is shut down The operation should be repeated after enable the power of the board 1 Execute Quartus II Tools gt Programmer Quartus filter tiltrer hitrer Compilation Report gt File Edit View Project Assignments Processing Tools Window Help 18 Do ld amp y Bags Adi Run EDA Simulation Tool T og ao 52 gt Run EDA Timing Analysis Tool Launch Software Debugger Ctrl Shift
8. mm He 4 a 55108 AH18 2 0 7 S 0 22 17 6 A18 Bis on 08 19 108_AM19 474 12 1K Ohm QS 32X861 J4B 00 00 00 B7 99 B7 AH6 9g 9g B7 4 98 B AH7 19 B7 T B7 AG8 Q B7 8 94 87 AE9 Q B7 AG9 Q B7 AH9 9 7 10 190 B7 186 7 AGIO __188 18 B7 186 BZ AFI 18 7 AG11 184 7 18 B7 18 87 ADIO 18 7 180 B7 7 AD11 8 87 12 87 AC12 7 2 7 AE12 7 7 AG12 7 7 AC13 87 AD13 169 7 AE13 168 7 16 7 AG13 166 B7 13 16 B7 164 7 16 7 AG15 16 lt ETT EET Ar EET ey nc a AE ETT 824 151 et 154 ES ACE 151 025 TOLG SOLC 5 26 B7 AKA AG 107 7 AL4 107 14 B7 AMA 107 4 7 AJ5 107 AJ5 B7 6 7 AK5 B7 5 107 15 B7 AM5 Q AD 7 5 B7 AJ6 9 107 AJ6 7 0 8 107 AK6 7 AL6 107 16 7 107 AM6 7 AJ7 107 AJ7 7 7 6 107 AK7 7 AL7 107 17 B7 AM7 Q 0 107 7 7 AJ8 107 AJ8 7 AK8 0 Q 7 AK8 7 AL8 107 18 B7 AM8 107 AM8 139 R137 1K Ohm 7 B7E QS 32X861 E v43 127 00 6 99 B7 AH5 48 98 B7 AH6 7 7 AG 96 7 AF8 7 7 AK9 9 7 7 19 A4 107 19
9. IO DIFFIO RX35p IO DIFFIO TX21n Bs 155 037 E IO DIFFIO RX35n IO DIFFIO TX24p 28 2 6251 IO DIFFIO RX40p IO DIFFIO TX24n ED pas 9 ENT IO DIFFIO RX40n IO DIFFIO TX27p Io Ead O DDA 2 730 CLK1p IO DIFFIO TX27n NOR 0 102 T29 CLK1n IO DIFFIO TX31p FN B2 1 102 R29 102 N24 ENTE 102 210 DIFFIO IO DIFFIO TX31n Iz B2 G31 VCC V43 VCC V43 102 P29 psg 2 102 M24 1 Sq IO DIFFIO TX29n DIFFIO TX35p 2882 LAS 6 DIFFIO RX27p IO DIFFIO TX35n L ag L ag IO DIFFIO RX27n IO DIFFIO TX41p 52 2 H30 102 P22 B2 P22 02 M29 pg RX26p EE 102 R23 O 10 RX26n IO DIFFIO TX25p 3 2 29 02 032 B2 032 102 P23 2 2 23 102 130 Lh DR P ES P Tp 102 R22 2 932 102 031 B2 031 102 P24 re 2 P24 102 29 9 E ER ee a 5 102 23 2 31 102 030 2 030 102 P25 2 25 oz kan RE n HEIN p D 102 22 2 J30 102 029 2 029 102 P26 2 26 102 29 DIRE S N N23 B2 J29 102 E32 B2 E32 102 P27 2 27 102 930 it Ue 1 PIN N22 B2 K32 102 E31 2 E31 102 P28 10 2 28 102 J29 Bd HE T p 1 2 M23 2 K31 102 E30 9 2 E30 102 29 9 9 2 29 jeg V 102 M22 2 30 102 E29 2 29 1
10. JESSEN MART me B Choose Open after finding files location B Choose OK CFCC 28058290 H SCRIP C maxplus2_96 Drivers win2000 B Choose Yes RT gt i Microsoft oo Windows fn Microsoft BUE RE Was EERE iA 5 FRAMES MALE HESS Microsoft YU RBA Windows Update https windowsupdate microsoft com FETE 900 HBH Altera Frogrammnr B Choose Yes HTA EEE x Microsoft fe FER Windows E EARRA gt KER Microsoft Allt E RENSE Ped Windows BEE ETF ABRE 10778983828 Microsoft FAE pu U Update microsoft com Me 7 FFO B Choose Next GOC EISBOSIRA GALAXY FAR EAST Windows TREE GER HE kan Akers EyePlunr gt o B Choose Finish Q TESTE ES E UE RETE Eget Altera Windows ERR STE BRETTET e EC WIEN d cn KE Bite pre EB B Restart computer 7 4 CONFIRM WHETHER THE INSTALLATION
11. M RAM Block High Speed kr Channels With Phase Alignment DPA 2 Phase Locked Channels With I RR Loop External Memory Interface Circuitry Stratix EP2560 Fig 1 Stratix II 2560 Floorplan New Logic Structure B New and innovative logic structure based on adaptive logic modules ALMs packs more logic into less area and enables higher performance B Dedicated arithmetic functionality to efficiently implement adder trees and other computationally intensive functions High Speed I O Signaling amp Interfaces B 1 Gbps source synchronous I O signaling performance in dedicated serialization deserialization SERDES circuitry B Dynamic phase alignment DPA circuitry accelerates maximum performance by dynamically resolving external board and internal device skew B Support for differential I O signaling levels including HyperTransport technology LVDS LVPECL and differential SSTL and HSTL External Memory Interfaces B Support for the latest external memory interfaces 1n dedicated circuitry including DDR2 SDRAM RLDRAM II and QDRII SRAM devices B Sufficient bandwidth and pins to support interfacing with multiple standard 64 bit or 72 bit 168 144 DIMMs Design Security B Brings programmable logic functionality and benefits to new applications requiring design security 9 ABAID 5 o GALAXY FAR EAST CORP
12. A 1 2 MESH sb oe 1 3 FAST USING THE DEVELOPMENT SA x 2 INFORMATION FOR HARDWARE INSTALLATION FER 2 1 OUTSIDE VIEW OF GFEC EK2SF1020 DEVELOPMENT BOARD E RER 2 2 STRUCTURAL DIAGRAM OF GFEC EK2SF1020 DEVELOPMENT BOARD SR Ed 2 3 DEVICES COMPATIBLE WITH FPGA FSR fi KE es 2 4 POWER SYSTEM FSR fi KE es 2 5 AVAILABLE OF DEVELOPMENT FER 2 9L IE FSR IIR es 752 PM FSR fi KE EVEN HER fil AE Fest d 2 5 4 PIAS MN FSR fi KE es 2 6 SPECIFICATION OF CONFIGURATION Seal IIR ER 2de EEE HER fil AE Fest d 2 8 58 2 RTR 33 2 10 DDR S0 DIMM Line us 2 11 SERA 2 12 020 0 2 10000000 geal 2 13 USAGE OF CLOCK 5 E fi KE 2 14 ELECTRIC SPECIFICATION AND CHARACTERISTICS OF FOLLOW THROUGH SWITCH ARR SEGA fil TE 2 15 SYSTEM STATUS INDICAT
13. IS 4 506 IS 460 6 2 05 0 1u IS 4 5 2 0 IS 4 5 ES 0 1u IS 4 S 2 0 1u IS 4 S J34 4 2 DDR V43 C186 100 uF C187 100 uF C174 10 uF C173 100 uF VCC V25 VCC En VDDQ VREF Comp GND FB MIC5162BMM C175 220 pF SI4420DY R57 3K Ohm TP16 VTT C182 C183 C176 C188 C189 0 1 uF 0 01 uF 100 uF 100 uF 100 uF itle Title Size Document Number Rev B Doc A Date Wednesday April 13 2005 Sheet 3 of 17 VCC VTT VCC VTT RN2 50 Ohm RN4 50 Ohm 8 DDR 006 04 C6 9 8 DDR CASn 103 H22 DDR DQ2 2904 Ec DDR 505 025 6 DDR DMO 6 DDR RASn 104 B5 G20 DDR DQSO DDR BAO 104 G21 DDR 005 DDR BA1 04 D6 J20 DDR 001 104 05 DDR A10 21 DDR 004 104 DDR AO 103 K20 VCC DDR Vref D DDR 000 DDR 1 Q 104 B4 119 RN6 50 Ohm RN8 50 Ohm V25 VCC V25 VCC V25 8 DDR 1 9 8 DDR DM4 VCC V25 2 DDR 6051 9904 8 DDR 55 03 Bel 104 07 103 019 6 DDR 0013 104 6 DDR 0037 C21 DDR 009 104 7 DDR 0033 E19 VSS1 vss L4 DDR DQ32 DDR 0036 DDR 0012 04 C9 DDR 0036 21 DDR 000 5 DQO 004 6 DDR 004 DDR 0033 129 130 DDR DQ37 7 DDR 008 DDR 6035 C190 DORDA 7 8 Dor 005 181 122 104 B7 103 B20 DDR Dar 99 0
14. 2 108 22 AM2 lt B10 733 Se arate 108 AM22 am 0 00118 0 01081 Aion 108 2 8 AD23 108 AD23 8 AJ23 108 AJ23 EET 108 AM23 DQ11B3 DQ10B3 Map 22 7 AC15 12 12 107_ 15 IO DQ13BO IO DQSn12B B8 AG22 14 2 108 AG22 AL23 18 DL 28 EEE 108 AM25 AMps 10 00138 105091481 Tans 108 25 B8 AF22 19 9 106 AF22 8 AM23 19 108 23 19 35M 108 AM26 AM2G 9091581 PQSN14B LAH2G AH26 AE22 20 108 AE22 AK24 20 108 AK24 X 20 Dd 108 AM27 AM27 10 00158 DQ14B2 AH28 108 28 B8 AD22 108 AD22 B8 AL24 108 AL24 14 211 A17 B17 22 4 107 AC14 108 AM28 AM28 10 001680 eid 108 AG17 8 AC22 108 22 B8 AM24 08 24 ABi4 lt 22 a 108 AM29 AMO 0 01681 is 108 AG18 i QOS ALI ET IO DEV CLR 106 AGIS AL18 AE ALIS AL18 OUTOp VB8NO 1 108 AG20 108 AL19 Ar19 0 a mr 108 AGz1 R151 1K Ohm R153 1K Ohm R149 1K Ohm ke ESTE EE 108 AG22 B7E 474 12 O 7 47e 12 121 A IO DAST1B IO DQ12B3 H 108 AG23 B7E 108 2 A 12 10001283 108 AG24 QS_32X861 QS 32X861 he O8 0 05138 90 2 4625 198 AGES 108 26 TA 108 AL27 Ajaz DQSn1
15. 128 bit advanced encryption standard AES design security using configuration bitstream encryption technology B Key securely stored in FPGA and does not require battery backup or consume logic resources TriMatrix M Memory B 9 Mbits of memory in three block sizes and M512 blocks B Includes parity bits for error checking B Performance up to 400 MHz B Mixed width data and mixed clock modes Digital Signal Processing DSP Blocks B More DSP block bandwidth with up to 4x more DSP bandwidth than Stratix devices 9 5 x B Dedicated multiplier pipeline and accumulate circuitry B New rounding and saturation support in Q1 15 format in each DSP block B Maximized performance of up to 420 MHz Clock Management Circuitry B Upto 12 on chip phase locked loops PLLs for device and board clock management B Dynamic PLL reconfiguration allowing on the fly PLL parameter changes B Redundant clock switchover for error recovery and multi clock systems On Chip Termination B On chip differential and series termination reducing board design complexity and cost Remote System Upgrades B Remote system upgrades for reliable and safe deployment of in system upgrades and bug fixes B Dedicated watchdog circuitry ensures proper functionality after update FRRPERAI GALAXY FAR EAST 1 1 Specifications of the Products When you get the GFEC EK2SF1020 development
16. K20 VCC V43 VCC V43 pe LE 103 H23 67 B3 E20 671 x BS GT 1 83621 ene 02 19 iG dis 59 59 59 59 BG vet B3 K21 K21 46 103 H24 H24 2 SPD SDA B3 L21 B3 L21 103 E19 4 B3 E19 103 G24 B3 G24 TO DATA4 IOS J23 B3_G22 B3_G22 103_D19 44 B3 D19 103 J23 4 44 B3 923 2 HK18 103 K18 103 K18 B3 H22 4 4 B3 H22 103 F20 4 B3 F20 103 H23 4 H23 IO VB3NO 3 103 K19 B3 J22 B3 J22 103 E20 4 B3 E20 103 G23 6 4 B3 G23 IO VB3N1 6 103 K20 B3 K22 5 B3 K22 103 020 B3 D20 103 122 B3 122 Ker B3 122 B3 122 103 C20 40 B3 C20 103 K22 8 40 _ B3 22 7 2 623 8 8 022 8 8 B3 G23 103 20 9 B3 B20 103 J22 9 9 B3 J22 IO VB3NO 4 103 118 B3 H23 Q Q B3 C22 Q 9 B3 H23 103 F21 Q B3 F21 103 H22 0 8 B3 H22 IO VB3NO 5 103 L19 B3 J23 80 80 J23 103 D21 B3 021 103 G22 B3 G22 IO VB3N1 8 103 120 B3 G24 8 8 3 24 103 C21 B3 C21 103 121 B3 121 CENT 103 121 B3 H24 3 24 103 B21 B3 21 103 21 B3 K 1 O OAR 103 122 B3 A23 9 B3 A23 A21 B3 21 103 921 B3 121 B3_B23 84 84 B3 B23 103 F22 B3 F22 IOS H21 21 B3 C23 8 gn _ C23 103 E22 Q B3 E22 103 G21 8 j B3 21 B3 023 86 _ 023 103 D22 9 022 103 120 120 B3 F23 3 8 B3 F23 103 C22 8 B3 C22 103 K20 B3 K20 B3 A24 88 88 B3 A24 103 B22 B3 B22 103 J20 B3 J20 103 B3 B24 20 20 B3 B24 103 A22 22 103 H20 B3 H20 B3 C24 90 o0 C24 103 G20 B3 52
17. MSEL1 MH C191 C192 C193 UN MSEL2 0 MSEL2 MSEL3 Me 0 1 uF 0 1 uF 0 1 uF R38 1 Ohm SEL3 uns TDO TDI TDI rv TOR R40 1K Ohm TM TMS CONF DONE R41 1K Ohm A130 2 no UG 0 5 5 DCLK nCE DALU DATAO nCEO R43 0 Ohm ASDI ASDO DATAO R45 0 Ohm DATA DATAO ASDO nCSO NSTATUS VCC V33 VCC V33 VCC V33 VOC V33 J11 R71 RN32 220 Ohm n 8 DCLK nSTATUS kh E R47 R48 DONE KA ER 220 Ohm 220 Ohm __6 nCONF ncSO DATA 73 0 310 9 ASDI CONF DONE 1 Ohm SW1 R70 0 Ohm R LED D10 G LED PS AS PG o 3 VCC V33 R72 0 Ohm PUSH BUTTOM NSTATUS J12 RN33 9 TDI NAG 1 JTAG J26 IDOS _ Tpos itle IDOM lt Title gt Jumper rem Number Date Wednesday April 13 2005 Sheet 15 of 17 VCC TP6 VCCIO1 VCC TP7 VCCIO2 VCC TP8 VCCIOS VCC 1 4 VCC TP10VCCIO5 TP11VCCIO6 TP12VCCIO7 8 101 102 103 104 105 106 107 108 J16 Jumper 914 417 Jumper 918 919 Jumper 421 Jumper J20 Jumper 422 Jumper 3 2 x J HO e on XH OO OS gt Mmm a a a a ad
18. Stratix 1l ao 2 5 1 JP1 amp JP5 PAX 123 ZS o GALAXY FAR EAST CORP 49 T27 T22 Tab 5 amp 5 ak strat Hol 51 Reserve GND 151 U27 153 U22 155 V29 156 V24 158 V23 W29 W27 162 W26 163 AA3 25 _ 164 W24 165 AA30 W23 166 67 AA29 W22 167 AB31 Y26 AB30 Y25 Y23 172 Y22 173 gt X gt I Em ER 75 AC29 26 175 76 AD32 AA25 176 EN AD3I 24 79 AD29 22 179 AE32 AB28 180 82 AE30 AB26 182 AF20 AB25 183 84 AF32 AB24 184 AF30 AC27 186 87 AF29 AC26 187 1 24 189 AG30 AD27 190 9 AG29 AD26 191 93 AH3I AD24 193 94 AH30 AE28 AJ32 AE26 196 0 Tab 6 amp 1 5 ID 2 5 2 JP2 amp JP6 bP _ 7 C9 E9 106 C8 108 F8 111 10 112 B10 F10 B11 118 121 125 126 128 G12 H12 K12 132 L12 J13 135 KL H14 BH ee X t CFCC Tab 7 JP2 amp JP6 1 _ 156 51 60 pis no 160 61 Jes ier 62 A19 1 19 162 63 19 G20 163 64 mo 65 D19 J20 165 F20 K20 166 120 20 69 20 21 70 B20 121 Fa D21 L21 172 C21 22 173 75 A21 J22 175 76 F22 K22 D
19. 7 8 7 9 4 107 7 7 AK10 107 AK10 7 AG9 7 AL10 107 110 7 AH9 7 AM10 Q 40 107 10 90 7 AE10 7 AK11 9 9 107 AK11 90 B7 AF10 B7 AL11 0 2 107 111 88 7 10 B7 AM11 107 11 Q B7 AJ10 B7 AJ12 107 AJ12 86 7 AE11 B7 AK12 107 AK12 8 7 AF11 7 112 107 112 84 7 11 7 AM12 107 12 8 B7 AH11 B7 AJ13 Q 0 107 AJ13 Q B7 AJ11 B7 AK13 9 9 107 AK13 Q 7 AD10 B7 AL13 0 2 7 AL13 80 B7 AB11 B7 AJ14 7 AJ14 7 11 B7 114 6 107 114 8 7 AD11 7 14 107 AM14 7 12 7 AC12 7 AD12 BY 12 472 R141 B7 AF12 Q BEI GND 2 B7E B7 AG12 B7 AB13 R143 32 56 2 7 1K Ohm 69 7 AD13 68 7 AE13 6 B7 AF13 66 7 AG13 B7E 6 B7 AH13 64 B7 AG14 6 7 AH14 VCC V43 7 15 938 lt B7E O B7 AB14 Ga VET gt R69 Fe Ne UN D27 iss ees SIE D26 S B7 AB16 B7 AC16 D25 451 107 AD10 V43 48 B7 AJ11 4 107 7_ 11 4 44 107 7_ 11 4 107 B7 AF11 6 4 107 B7 AE11 4 107 B7 AJ10 AQ 107 B7 AG10 Q Q 107 B7 AF10 0 2 107 7 AE10 107 B7 4 4 107 7 AG9 107 7_ 6 107 B7 AH8 107 B7 AG8 2 0 107 B7 AF8 9 9 107 B7 AH7 0 2 107 7 6 107 7_ 5 6 107 1K Ohm 4 12 C BE1 QS 32X861 U 7 48 B7 AG15 46 107 B7 14 4 107 B7 14 4 44 107 B7 AH13 107 B7 AG13 6 107 B7 AF13 107 B7 AE13
20. 1 RAST DOR CASn 4 DDR DDR Con 12195 n P122 ______ DDR 5 104 115 4 DDR A7 104 J14 DDR A8 x DDR A9 104 114 VSS35 Q 104 14 i 1 Title Size Document Number Rev B Doc A Date Wednesday April 13 2005 Sheet 4 of 17 5 B1 U28 B1 U27 B1 U23 B1 U22 B1 V29 B1 V28 B1 V24 Bi V23 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VCC V43 102 P32 102 P31 102 R31 02 R30 102 T32 102 T31 02 T30 102 T29 102 T28 102 T27 101 U32 031 030 029 V31 V30 W32 W31 R75 1 Ohm 47 VREF1 Me B1 030 6 8 9 29 60 W28 6 W27 6 W26 6 W25 W24 6 W23 66 W22 6 27 68 Y26 69 69 1_ 1 69 Y25 Q Y24 Y23 Y22 AA27 4 26 25 6 24 23 8 AA22 Q AB28 80 AB27 8 26 8 25 8 24 84 23 8 27 86 AC26 8 25 88 24 89 AD27 90 AD26 9 AD25 Q AD24 Q AE28 94 AE27 Q 26 96 AE25 Q 28 9g AF27 99 90 B1 AJ29 90 00 0 SOLC N OO s OO s O KO O KO O Co DD VCC V43 011 V43 931 gom 101 AE32 B1 AE32 1 AF27 2 R31 101 AE31 B1 AE31 101 AF28 2 R30 10
21. 101 VCC 102 VCC 103 VCC 104 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF C103 C104 C105 C106 C107 C108 C109 C110 C111 G112 G113 C114 C115 C116 C117 C118 0 1uF 0 1uF 0 1uF 0 1uF 105 VOC 106 107 108 Stratix II VCC PLL Out Place those Cap to per VCC PLL out as near as possible VCC 103 VCC 104 VCC 107 VCC 108 un sius m m 0 1uF 0 001uF 0 1uF 0 001uF 0 1uF 0 001uF 0 1uF 0 001uF itle Title Size Document Number Rev B Doc A Date Wednesday April 13 2005 Sheet 13 of 17 VCC V33 112 Yi R53 C158 C159 C160 lt 104 E16 220 Ohm 0 1 uF 0 001 uF 0 1 uF OE n GND 50Mhz Do not Stuff R52 for Ocilator operation Stuff R13 when using L E Clock input hol dg Jumper UART RXD VCC V33 103 620 Jumper DRILL1 DRILL3 DRILL5 DRILL DRILL DRILL DRILL2 DRILL4 DRILL DRILL PCB Please place those drills near the corner of board itle lt Title gt Size Document Number Rev B lt Doc gt A Date Wednesday April 13 2005 Sheet 14 of 17 nCSO DATAO ASDO DCLK VCC V33 EPCS64 Ver EEE PowerGood R154 1 25901020 VCC V33 Uil Configure J33 0 5 23 VCCSEL 2 TMEPDIODEn HAG TR ORM 9 TMEPDIODEp MSELO
22. 152 C26 9 TOLC 5 R121 B5E G6 G5 H6 H5 J9 J8 J7 J6 K9 K8 7 K6 L10 L9 L8 L7 L6 L5 11 M10 M9 M8 M7 M6 N11 N10 N9 N8 N7 N6 P11 P10 P9 P8 P6 P5 P4 B5 Ri1 B5 R10 B5 R7 B5 R6 B5 R5 B5 R4 B5 T11 B5 T10 B5 T6 B5 T5 v43 921 5 04 46 105 5 03 A 105 5 D2 Ad 105 B5 Di 105 B5 E4 4 105 5 A 105 B5 E2 An 105 B5 E1 5 105 B5 F4 105 5 F3 105 B5 F2 4 A 105 B5 Fi 105 B5 G4 105 B5 G3 105 B5 G2 0 105 B5 G1 0 105 B5 5 105 5 105 B5 H2 105 B5 Hi 105 1 Ohm A 12 O QS 32X861 VCC V43 B5 105 B5 Ja 105 B5 J2 105 B5 1 105 5 105 5 105 5 K2 i 105 B5 Ki 5 105 B5 L4 T 105 5 3 105 B5 L2 7 105 B5 LI 105 B5 M4 2 105 5 105 5 2 105 5 Mi 105 B5 N5 0 2 5 B5 105 5 3 105 B5 2 105 470 5415 OS 32X86 1 Ohm BSE 937 BSE D4 03 02 D1 E4 E3 F4 F3 F2 F1 G4 G3 G2 G1 H4 H3 H2 H1 R119 B5E J4 J3 J2 J1 K4 K3 2 K1 L4 L3 L2 L1 2 1 5 4 N3 N2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 V43 L5 L6 L7 L8 L9 L10 K6 K7 K8 K9 J6 J7 J8 J9 H5 H6 G5 G6 1K Ohm B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5
23. Tab 12 JP4 amp ID 2 6 Specification of Configuration EPROM 2 8 X Altera can be burned in many planning way The development board has been attached Configuration Device EPCS64 or EPCS 16 configured according to chosen capacity of FPGA before shipping And AS connection port is reserved on the board which can be used for Configuration Device EPCS 1651163 amp EPCS64SI64N by attached GFEC USB Blaster or Byte Blaster II Download Cable The detailed use method of ISP refers to 3 3 2 and these should be operated step by step P 20 000 Cs i 2 7 JTAG The development board provides one JTAG connector which is used in the early stage when RTL code has not finished and burning programme has to be changed frequently It can reduce the burning time and burning times when using configuration device ERBIOSIRAU GALAXY FAR EAST s gt II xneas GALAXY FAR EAST FRRPERAI 2 8 Test Pin The development board offers 16 test pins in total which are used to indicate the system status during validation GND 5 2 43 V 9 33 V X TP4 25V TP6 Bank 1 VCCIO TP7 Bank 2 VCCIO TP8 Bank 3 VCCIO TP9 Bank 4 VCCIO TP10 Bank 5 VCCIO Bank 6 VCCIO TP12 Bank 7 VCCIO TP13 Bank 8 VCCIO TP14 GND TP15 GND TP16 GND TP17 JL Nf _
24. VOC V43 V43 P4 P5 P6 P7 P8 P9 P10 6 7 N8 N9 N10 N11 M6 M7 M8 M9 M10 M11 Q 7d R117 1K Ohm B5E U41 QS 32X861 QS 32X861 N DO A DO 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 L5 L6 L7 L8 L9 L10 K6 K7 K8 K9 J6 J7 J8 J9 H5 H6 G5 G6 105 R4 105 R5 P4 P6 P7 P8 P10 P11 N6 N7 N8 N9 N10 N11 M6 M7 M8 M9 M10 M11 lt 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 Ti T2 R2 R3 P1 P2 N2 N3 1 2 L1 12 Ki K2 12 H1 H2 G1 G2 F1 F2 Ei E2 D1 D2 T3 T4 R4 R5 P4 P5 N4 N5 M3 M4 L3 L4 K4 J3 J4 H3 H4 G3 G4 F3 F4 E3 E4 D3 D4 C169 VREF5 EP25901020 U1E 3 D VREFB5NO VREFB5N1 VREFV5B2 RE 65 16 55 IO CLK10n 105 Re 0005 16 IO_DIFFIO_RX61n IO DIFFIO TX58p 105 P6 105 R7 IO DIFFIO RX62p IO DIFFIO TX55p 105 P7 N IO_DIFFIO_RX62n IO_DIFFIO_TX55n 105 NG IO DIFFIO RX59p IO DIFFIO TX52p 105 N7 Y IO DIFFIO RX59n IO DIFFIO TX52n M6 Y IO DIFFIO RX60p IO DIFFIO TX51p 105 7 IO DIFFIO RX60n IO DIFF
25. mS mar a eaer o m Son um men E on STE NE PPPS PSR RRR SPR PSPS SSSR SPP SPSS RRR pe mr rard EL _ EE m r 4 roa mer uia rv E pr EE L 1 a lt ra n mum zr n a Fa E 4 mos mer man on men a FE raa 2223 2 59 pe re od bord be 2 1 reaa mar xm xm Fr a FE r iam EI 2223 I a im Mund L3 r eam pa Ema 1 91250 0635 7 apr 5999 3075 4 45 4 4 Schematic 1 E LL S PowerGood Tg Ig 4 d L 5j 6 CON10C DC U4A V43 J13 p li O DC Jack 250 Ohm J27 100 Ohm DC_6V CON10C L1
26. 3 1 QuartusII Version Support QuartusII with version no lower than 4 0 supports Stratix II Device Family You will receive optical disk for upgrading from Altera itself when your software is within warranty period you can also apply for trail software from GFEC 9 8 x OS Service Packs or Patches Platform amp Hardware OS Windows XP None Windows 4 0 Service Pack 3 or greater System requirements Windows 2000 None 800 Mbytes disk space RedHat Linux 8 0 None 256 Mbytes RAM 1 RedHat Linux 7 3 None RedHat Enterprise Linux 3 None SUN Solaris 9 None System requirements 1 1 Gbytes disk space Solaris 8 2 256 Mbytes RAM 1 System requirements HP UX 11 0 2 925 Mbytes disk space 256 Mbytes RAM 1 Tab 15 contains details about Quartus II software version 4 2 operating system OS support BRR ZS S GALAXY FAR EAST CORP Stratix Device Availability POF Software Support Final Timing Support Models Preliminary Timing Models V4 2 SPI v5 0 V4 2 v5 0 gt ES x V4 1 SPI v5 0 V4 2 SPI v5 0 V4 2 v5 0 V4 2 SPI v5 0 Tab 16 Quartus II Support Stratix II Timing Model amp POF 3 2 Version Support from Cooperation Manufacturer Product Version Mentor Graphics Precision 2003c Synplicity Synplify 7 5 Tab 17 3 Support Stratix II device family
27. 8 23 05 8 27 8 AJ28 108 AJ28 B8 AH19 108 B8 AL27 2 B8 AL27 8 28 108 28 8 AG19 108 AG19 B8 27 9 E B8 27 B8 AL28 9 9 108 AL28 B8 AF19 9 108 AF19 8 AJ28 Q D 08 08 5 Q B8 AJ28 B8 28 0 8 108 AM28 8 AE19 108 AE19 8 28 3 B8 AH24 3 B8 28 B8 29 108 29 B8 AD19 108 AD19 B8 AL28 E 0G 8 AG25 06 E 8 AL28 8 AL29 108 AL29 8 AC19 108 AC19 B8 28 8 25 8 28 8 29 108 AM29 8 AB19 108 AB19 8 29 5 04 B8 AH26 04 E 8 29 8 29 8 29 R1471K Ohm 4 lt lt 8145 1K Ohm 479 BE EO itle CO CO B7E lt Title gt SOLC TOLC Size Document Number Rev B Doc A Date Wednesday April 13 2005 Sheet 12 of 17 IH Stratix II Decoupling VTT Regulators Stratix VCCINT Place those Cap to per VCCINT pin as near as possible VCC V12 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF C69 C70 C71 C72 C73 C74 C75 C76 77 78 79 80 C81 C82 C83 C84 C85 C86 al 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF Stratix VCCIO Place those to per VCCIO pin as near as possible
28. B Quartus 2000 03 or later 9 5 x 2 DRIVERS PATH B Maxplus2 lt Maxplus2 install path gt Drivers win2000 Default path c maxplus2 drivers win2000 B Quartus Quartus install path gt Drivers win2000 Default path c Quartus drivers win2000 3 PROGRAMME INSTALLATION B Enter Control Panel SED AXE gu REE See ETE HATE FERES TH OL ESUEBURSETRESECD B Select Internet H BAAS KAST EIGE IE E B Choose Next GALAXY FAR EAST FARPERAD PETER MGE F H B Choose Next m EET F R ESTE LIT X xi either EE E TERES HETE EET MENE RS Ri AZER I dite T PCI MERERI CD ROM 40X AKU FH gt a ai ee Naher LA AE NE EE nden MALTE EE MAA REE NE Windows NEL La B Choose Sound effect video and game controller GALAXY FAR EAST gt B Choose Installation from disk x i neu Semicendnctor Lu B Choose Browse
29. LL LL LL EL LL EE N 107 14 lt 107 14 lt 107 AD14 gt gt gt gt gt gt gt J UJ UJ UJ UJ UJ U 000 s 107 AB120157 5 7 AC1 7 12 107 AC13 4 107 14 Bre gt DP 15 107 15 STAIR or Asis 7 AC16 gt Size Document Number Rev B lt Doc gt A Date Wednesday April 13 2005 Sheet 11 of 17 172 VREF8 VCC V43 V43 V43 0 1uF ii EE EP2S901020 B8 AJ19 46 AJ19 BANK8 B8 AH28 108 28 B8 AJ20 108 AJ20 B8 AG18 AG18 B8 AH26 108 26 B8 AK20 108 20 8 AD18 AD18 222 8 25 108 25 B8 AL20 108 AL20 8 AC18 18 mmm B8 25 108 25 B8 21 108 AJ21 B8 AB18 AB18 D B8 AH24 108 24 B8 21 4 8_ 21 8_ 17 17 8 AG24 108 AG24 B8 21 10 108 21 8 AG17 17 9 9 B8 21 9 9 108 21 B8 AC17 9 17 AG23 7714 7 7 108 AG23 BE AKG2 1 PE ES So AMIS 10 DEV OE 108 AHTS 108 AM19 IO PLL12 FBn OUT2p 10 PLL12 OUT1n 108 18 B8 AF23 108 AF23 B8 AL22 4 7 ALOR 15 108 21 Eos 108 AHIS
30. NT 21 NT 22 NT 23 NT 24 NT 25 NT 26 NT 27 NT 28 NT 29 NT 30 NT 31 NT 32 NT 33 NT 34 NT 35 NT 36 NT 37 NT 38 VCC PLL11 out NT 12 VCC PLL5 out V V V V V V V V V VCC V VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC OO C SI 0 1 O 0 OO C 3 3 lt Q x 00 gt gt 2 q lt t tj itle U1J 2 901020 VCC AND p gt gt rp m gt O Do 00 D gt ee gt gt CO Sb lt Title gt VCCIO4 VCCIO8 Size Document Number VCCIO7 VCCIO3 B lt Doc gt Date Wednesday April 13 2005 Sheet VOC V12D VOC V12A 16 of 152 153 V33 0 1 uF 0 1 uF C14 VCC 6 C1 V D C24 r3 C2 GND UART_TXD TX10UT UART CTS TX2IN TX20UT UART RXD RX10UT UART RTS RX20UT RX2IN ICL3232 155 156 157 TP 0 1 uF 0 1 uF 0 1 uF RS 232 Activity LEDs TX 011 R49 220 Ohm RS232A TXD G LED RX D12 R50 220 Ohm RS232A_RXD G LED FEMALE RS232 CONNECTOR gt RS232A1 CTS Channel itle lt Title gt Size Document
31. The development board is pre set as PLL Enable If it is required to disable the embedded PLL for saving electricity or others the pll ena pin should be controlled by extrinsic loop The followings explain pins with special input 18 Doi Ree 10 ZS GALAXY FAR EAST CORP CLKOn Input Output B2 Toi JP1 45 Input B2 T30 JP1 46 CLKIn Input B2 125 1 47 CLK2p Input Output Bl m CLK2n Input Output Bl U31 JP1 53 CLK3p Input Bl U30 JP1 54 CLK3n Input Bl U29 A CLK4p Input Output B8 AMI JP4 46 j CLK4n Input Output B8 ALI7 JP4 47 x CLK5p Input Output B8 7 JP4 48 CLK5n Input Output 17 JP4 49 CLK6p Input Output B7 AM16 JP4 52 CLK6n Input Output B7 AL16 JP4 53 CLK7p Input Output B7 16 56 CLK7n Input Output B7 AGI6 JP4 57 CLKS8p Input Output B6 UI JP3 44 CLK8n Input Output B6 U2 JP3 45 CLK9p Input B6 U3 JP3 46 CLK9n Input B6 UA JP3 47 CLK10p Input Output 5 12592 Input Output 5 T2 JP3 53 Input B5 T3 JP3 54 Input B5 T4 IPS 55 CLK12p Input Output B4 16 JP2 44 CLK12n Input Output B4 B16 JP2 45 CLKI3p Input Output B4 16 JP2 48 Input Output B4 F16 JP2 49 CLK14p Input Output B3 A17 JP2 54 CLK14n Input Output B3 B17 JP2 55 CLKI5p Input Output B3 JP2 56 CLK15n Input Output B3 D17 57 FPLL7CLKp Input B2 D30 JP1 4 FPLL7CLKn Input B2 D29 JP1 5 FPLL8CLKp Input B1 AJ
32. V25 V33 25 V33 VCC V12D VCC V12A J29 ioa Ohm Vin Vout EDEN Vin Vout GND GND C164 C165 1 2 gt 0 10 uF EN 10 uF MIC5268BMM MIC5268BMM 4 Pu PG VCC V43 VCC V33 101 VCC 102 VCC 103 VCC 104 R58 R59 R60 C5 C8 C9 C10 C11 C12 0 Ohm 220 Ohm UN C13 14 15 16 17 18 19 20 10 uF 10 uF 10 uF 10 uF 10 uF 10 uF 10 uF 10 uF D1 D2 D3 G LED G LED UN VCC 105 VCC 106 VCC 107 VCC 08 VCC 12 DC lt C26 0 001uF R9 C29 C45 4 02K 100uF 100uF C35 C36 0 01uF 0 1uF R12 8 06K Ohm 07 C22 1N5817 10uF J32 0 001uF Si oootur UN C34 FONF Q1 D UGATE1 UGATE2 ON on SL 0 1uF rad V43 V33 V25 12 4420 1 PHASE2 VCC V33 C40 C41 47 30 R10 LGATE1 LGATE2 23 7 Ohm 0 01uF 0 1uF R11 7 5K Ohm VCC V25 Q5 25 333 R14 2 120K Ohm R15 17 4 Ohm 2 OCSET2 C42 C43 0 01uF O tuF R17 8 25K Ohm 5 PG 100K Onm UN itle Title SV Size Document Number B lt Doc gt Date Wednesday April 13 2005 Sheet 2 of 17 Fa PowerGood VCC VTT CN1 2 2 2 2 0 1u IS 4506 04115 430 0 IS 4506 0 1015 4506 450 CN11 0 1u IS 4 SO oe 0 1u IS 4 S DX 0 1u IS 4 S VCC VTT 2 2 2 9 0 1015 4606 0 1015 4305
33. 0 E D O LE um um um uzb GALAXY FAR EAST 2 9 Jumper Choosing Area According to customer s requirement voltage of every I O bank of the development board can be adjusted as 3 3V and 2 5 V gt 9 5 5 x 2 10 DDR So DIMM The development board offers one DDR So DIMM pin which is for designs needing DDR SDRAM The function is pre set as Disabled Customers have to process impedance matching resistance of 16P8R 50 Ohm by themselves when this function is needed FRRPERAI GALAXY FAR EAST CORP 2 11 The development board offers one RS 232 connector to be used when necessary RTS and CTS in the second group only be used for FPGA higher than EP2S90F 1020 0000 2 12 Re Configuration The board offers one Push Button Switch SW1 which provides re download from Serial Configuration Device to FPGA GALAXY FAR EAST 2 13 Usage of Clock Signal The development board offers two ways to lead in clock signal B Extension Connector B Oscillator Socket Half size Quartz oscillator is pre set as the input of clock signal and input clock signal to global clock 15 details as follow gt 5 X Tab 14 Global Clock in GFEC Stratix II Development Board Half Size Os
34. 0047 A24 RR DDR 0049 465 0049 166 DDR 0053 DDR 0019 104 F10 DDR 0043 103 F23 DDR DQ16 4 DDR 0020 ua VDD28 168 I DDR 0022 lO4 D10 DDR 0046 103 C24 DDR 0017 43 DDR 0021 DDR 0056 59 DQSE 170 DDR DM6 104 01 DDR DQ42 55103 024 DDR DG50 12 DDR 0054 DDR DM2 99 O4 F8 DDR DMS 99103 F22 DDR 0052 47 TE DDR DM2 5 DDR DQS2 5904 Fa 5 DDR DASS 99 03 823 DDR 6018 ______49 50 DDR DDR T 7 75 0883 126 DDR 0055 DDR 0056 77 0951 178 DDR 0060 RN18 50 Ohm RN20 50 Ohm DDR 53 VSS 54 DDR 0023 aa Ha 9 DDR DOS wing 9 DDR 0055 44103 pog DDR 0024 5 0019 56 DDR 0028 DDR DQ57 a 18 0061 DDR DQ27 0004 312 DDR DASI 9103 626 DDR 0057 ag 0057 184 DOR DM7 DDR 0030 95104 91 DQ54 99 03 02 DDR DQ25 59 60 1 DDR DQ29 L ie 0 186 T DDR DQ26 99 94 B11 DDR DQs0 99 O5 27 DDR 0953 62 DOR DM3 DDR Dass T 583 188 T DDR DM3 104911 4 DDR DM6 _ 99103 026 DDR 0958 190 _ DDR 0063 DDR DQs3 5504 01 DDR 5055 99103 028 0026 T 65 es DDR 0030 12 192 DDR 0029 DDR 0053 DDR 0027 7 log DDR 0031 SPD SDA _____193 o4 104 A11 C25 SPD SDA SD
35. 104 A7 B4 A7 104 11 121 B4 E11 ___ 121 84 8 104 B7 Q 0 7 104 11 8 122 B4 Fii 122 B8 104 C7 9 9 7 104 H11 9 129 B4H9 ___ 123 12 104 07 0 8 07 104 G11 0 B12 104 E7 B4 E7 104 G10 125 B4 Gii __ 125 C12 104 A8 104 H9 126 B4 H11 126 87 B4 012 104 88 B4 B8 127 B4 J11 497 B4 F12 128 __ _ ____28 ___ _813 120 4 G12 __ 120 B4 C13 R109 1K Ohm 130 Hi2 30 Di3 2 1 331 4 2 1311 E13 BEI 12 B4 132 B4 E li 4 3 G13 05 32861 4 14 1K Ohm 135 84 13 135 B4 B14 136 B4 K13 136 5 B4 014 137 84113 497 B4 14 138 4 G14 138 B4 Fi4 B3E 139 B4 Hi4 139 4 44 140 40 41 B4 Ki4 L4 et VOG 104 142 B4 li4 142 Er 43 B4 15 143 rae 144 B4 Ki5 144 R67 145 84115 ___145 TE st UN 46 B4 K16 146 Fan 148 42 5584 016 B3E 4 16 AK B3E 16 104 112 QS 32X861 R66 UN 104 K11 R Hesse 4 17 17 B4 116 K16 0 BA 15 9 BA K15 Ji5 4 114 K14 BA J14 4 4 4 4 0 4 B4 B4 B4 4 4 4 4 0 4 9 4 B4 6 4 ETE H14 G14 L13 K13 J13 H13 12 12 H12 G12 K11 J11 H11 G11 G10 H9 VCC DDR Vref 104 4 104 5 10
36. 104 K14 K16 K17 104 112 L14 L16 104 L15 L17 8 of 17 R123 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 B5 R1 B5 R1 B5 R7 B5 R6 B5 R5 B5 R4 B5 T11 B5 T10 B5 T6 B5 T5 VCC V43 B5 P2 105 2 B5 P1 105 P1 B5 R3 6 105 5 R2 105 R2 5 4 2 40 5 4 5 9 9 105 5 2 0 2 105 2 m 4 Ps 4 106 U6 A10 04 0 13 12 BI aye GREETS AG 99 106 pa 06_ BM A 18 sa 06 Ui ae a Yen Bir 9 2 B18 3 9106 W2 B6 Wi1 A19 106 W1 1K Ohm Ec BE QS 32X861 L J3B 00 00 00 G6 OO QO B5 D4 OQ OO B5 G5 98 98 5 D3 98 98 5 H6 2 7 B5 H5 T 96 Jo os B5 J8 94 OA B5 E3 04 B5 J7 4 BS gt B5 91 B5 K8 a0 90 5 K7 T Bs K6 T Bs 57 B5 T B5 L8 5 BS L7 7 A B5 L6 B5 L5 B gp B5 MH f 1 ES 80 5 9 o B5 M8 BB 7 5 M6 277785 Nil B5 N10 1 BB B5 8 B5 N7 B5 N6 gt B5 Pil T 10 68 58 B5 11 68 68 B5 P9 57 B5 8 7 P7 5 B5 P6 d B P5 5 25 P 2 B5 ETES gt 450 9 lt os 027 155 C er lt 15 L5 5 lt
37. DIFFIO TX15n IO DIFFIO TX17p IO DIFFIO TX17n IO DIFFIO TX19p IO DIFFIO TX19n IO DIFFIO TX1p IO DIFFIO TX1n IO DIFFIO TX2p IO DIFFIO TX2n IO DIFFIO TX4p IO DIFFIO TX4n IO DIFFIO TX5p IO DIFFIO TX5n IO DIFFIO TX6p IO DIFFIO TX6n IO DIFFIO TX11p IO DIFFIO TX11n IO DIFFIO TX14p IO DIFFIO TX14n IO DIFFIO TX20p IO DIFFIO TX20n IO DIFFIO TX3p IO DIFFIO TX3n IO DIFFIO TX7p IO DIFFIO TX7n IO DIFFIO TX10p IO DIFFIO TX10n IO DIFFIO TX18p 90 IO DIFFIO TX18n 90 2 901020 1 8 101 AF28 101 27 8 101 AE28 101 AE27 101 AD27 6 101 AD26 101_AC27 6 101 AC26 8 101 AB28 101 AB27 1 AA27 6 101 AA26 101 Y27 6 101 Y26 101 W27 N26 101 W26 4 101 V24 01 V24 Der 101 U28 101 027 5 101 AE26 01 U27 101 25 101 AD25 4 101 AD24 101 25 4 101 AC24 6 101 AB26 101 AB25 101 AA25 4 101 24 101 25 4 101 24 A 101 W25 N24 101 W24 101 023 S gt gt gt gt gt gt gt gt gt gt gt gt gt gt UJ UJ gt gt gt gt gt gt gt gt gt DD gt gt 00 101 023 22 101 U22 o U22 101 U22 4 101 AB24 101 23 101 AA23 01 AA22 101 23 101 22 A 101 W23 A 101 22 gt gt 00 DJ gt gt gt itle Title Size Document Number Rev B Doc A Date Wednesday April 13 2005 Sheet 5 of 17 B1E VCC V43 102 102 102 102 102 102 102 102 102 10
38. IS SUCCESSFUL B Return to the desktop choose My computer then click the right key of mouse and choose Content Choose Administrator under hardware m re emerge B Choose Sound effect video and game controller 50 F RPERAI GALAXY FAR EAST Ma gt DVDKD ROM HEHE E amp IDE 14 ESS Solel PCI AvdicDeive DM D Legacy Legacy up TE SER ee 1 If Altera Byteblaster appears it means that the installation has succeeded 4 2 Modify the Compatibility of Microsoft Window XP SP2 In Microsoft Window XP if the user installs Quartus II firstly and then installs Windows XP SP2 he has to re install Byteblaster driver and then download programme onto the hardware Do the re installation as follow Cd quartus drivers i386 Bblpt exe r removes the ByteBlaster driver Bblpt reinstalls the ByteBlaster driver Net start ALTERABYTEBLASTER gt 9 5 x 4 3 Dimensional Drawing RT Em RE E nar pm 5 5253 i T3 E os pese i mme A ul i UM
39. Number Rev B lt Doc gt A Date Wednesday April 13 2005 Sheet 17 of 17 ERBIODSIRAU GALAXY FAR EAST 4 5 Buffer Spec gt II xneas QUICKSWITCH PRODUCTS IDTQS32X861 HIGH SPEED CMOS 20 BUS SWITCH WITH FLOW THRU PINOUT FEATURES DESCRIPTION Enhanced channel FET with no inherent diode to Vcc The 0532 861 provides two sets of ten high speed CMOS TTL 50 bidirectional switches connect inputs to outputs compatible bus switches The low ON resistance ofthe QS 32X861 allows Zero propagation delay zero ground bounce inputs to be connected to outputs withoutadding propagation delay and Undershoot clamp diodes on all switch and control inputs withoutgenerating additional ground bounce noise The Bus Enable BEn Available in 48 pin QVSOP package signals turn the switches on The QS 32X861 bus switch is idealforswitching digital buses as well as APPLICATIONS forhotplug buffering and 5V to 3V conversion Hot swapping hot docking The 0532 961 is characterized for operation at 40 to 85 Voltage translation 5V to 3 3V Power conservation Capacitance reduction and isolation Bus isolation Clock gating FUNCTIONAL BLOCK DIAGRAM Bo BE2 The IDT logo registered trademark of Integrated Device Technology Inc INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2000 2000 Integrated Device Technology Inc DSC 5730 3
40. W25 Q B1 AA24 101 AD32 0 8 B1 AD32 101 W26 0 B1 AA23 101 AD31 B1 AD31 101 W27 B1 AA22 101 AD30 AD30 101 W28 B1 AB28 101 AD29 B1 AD29 101 W29 B1 AB27 B1 AB26 B1 AB25 R81 1K Ohm R83 1K Ohm BI AB24 BIE LAUS GND 12 B1 AB23 BE1 GND 2 GJ B1 AC27 gt AC26 QS 32X861 QS 32X861 B1 AC25 B1 AC24 B1 AD27 B1 AD26 B1 AD25 B1 AD24 B1 AE28 B1 AE27 B1 AE26 VCC V43 B1 AE25 J35 B1E BT AF28 B1 AF27 s DO DI Ps B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 AF27 AF28 AE25 AE26 AE27 AE28 AD24 AD25 AD26 AD27 AC24 AC25 AC26 AC27 AB23 AB24 AB25 AB26 AB27 AB28 AA22 AA23 AA24 AA25 AA26 AA27 22 Y23 Y24 Y25 Y26 Y27 W22 W23 W24 W25 W26 W27 W28 W29 01 01 01 1 01 01 01 01 01 01 01 1 1 01 01 01 01 01 01 01 01 1 01 01 1 1 1 01 01 01 01 1 01 01 01 01 101 01 01 01 01 101 01 101 01 01 01 101 01 01 01 01 2 AJ31 AH32 AH31 AG32 AG31 AF32 AF31 AE32 AE31 AD32 AD31 AC32 AC31 AB32 AB31 AA32 AA31 Y31 Y30 W32 W31 V31 V30 U32 U31 AJ30 AJ29 AH30 AH29 AG30 AG29 AF30 AF29 AE30 AE29 AD30 AD29 AC30 AC29 AB30 AB29 AA30 AA29 129 28 W29 W28 V29 V28 U30 U29 gt gt gt
41. gt gt gt gt be gt gt pp gt gt gt 2 gt gt gt DP PD DP hk gt VREF1 IO DIFFIO RX2p IO DIFFIO RX2n IO DIFFIO RX4p IO DIFFIO RX4n IO DIFFIO RX7p IO DIFFIO RX7n IO DIFFIO RX8p IO DIFFIO RX8n IO DIFFIO RX9p IO DIFFIO RX9n IO DIFFIO RX10p IO DIFFIO RX10n IO DIFFIO RX12p IO DIFFIO RX12n IO DIFFIO RX16p IO DIFFIO RX16n IO DIFFIO RX18p IO DIFFIO RX18n IO DIFFIO RX17p IO DIFFIO RX17n IO DIFFIO RX19p IO RX19n IO DIFFIO RX20p IO DIFFIO RX20n IO CLK2p IO CLK2n FPLL8CLKP FPLL8CLKn IO DIFFIO RX1p IO DIFFIO IO DIFFIO RX3p IO DIFFIO RX3n IO DIFFIO RX5p IO DIFFIO RX5n IO DIFFIO RX6p IO DIFFIO RX6n gt gt UJ VREFB1NO VREFB1N1 VREFB1N2 C46 Ec IO DIFFIO RX6p 90 IO DIFFIO RX6n 90 IO DIFFIO RX13p 90 IO DIFFIO RX13n IO DIFFIO RX14p 90 IO DIFFIO RX14n IO DIFFIO RX13p IO DIFFIO RX13n IO DIFFIO RX15p IO DIFFIO RX15n IO DIFFIO RX14p IO DIFFIO RX14n IO DIFFIO TX16p IO DIFFIO TX16n IO DIFFIO TX18p IO DIFFIO TX18n CLK3p CLK3n gt gt UJ UJ IO DIFFIO IO DIFFIO IO DIFFIO TX9p IO DIFFIO TX9n IO DIFFIO TX8p IO DIFFIO TX8n IO DIFFIO RX11p IO DIFFIO RX11n IO DIFFIO TX12p IO DIFFIO TX12n IO DIFFIO TX13p IO DIFFIO TX13n IO DIFFIO TX15p IO
42. make a declaration here as follow Stratix II is the name of Altera FPGA series Synprify and Synprify Pro are the names of Synplicity composite software Precision is the name of Mentor composite software Other trademarks and names not including in the above are all belonged to our company Since science and technology are developing at high speed please understand us if there is any description out of the season for some specifications in this manual We don t guarantee herein that there isn t any omission or mistake in the manual and it s also possible for us to update and republish it The content of it may be changed without any further notice If there is any change to accessories or hardware for the development board the manual will be updated accordingly You can browse detailed information about manual s update on the global information network of GFEC or contact GFEC directly 2 COC F RPERAE GALAXY FAR EAST Any tab or paster on development board should not be torn down or erased otherwise it may be disadvantaged to cognizance warrant period of product gt o P 5 X CHARACTERISTICS OVERVIEW OF STRATIX II F1020 J T gem n coc a 1 INTRODUCTION OF THE PRODUCT 5 Bu fi KE Se d 1 1 SPECIFICATIONS OF THE PRODUCTS fi
43. set with removable jumper Users should not change them by themselves B Power cable and download cable are expected as short as possible so as to reduce noise gt B If you have any question to the product be sure to consult our engineers before you use it so as to avoid damage by improper 9 5 5 operation CFEC FARPERAD GALAXY FAR EAST L5 Fast Using the Development Board 9 5 5 1 Power System Detail See 2 4 2 Extension Connector Detail See 2 5 3 AS Configuration Detail See 2 6 4 Configuration Detail See 2 7 5 Test Ping Detail See 2 8 6 B1 B8 Bank Voltage Detail See 2 9 7 DDRSDRAM Detail See 2 10 8 UART Detail See 2 11 9 Re Download Detail See 2 12 10 Oscillator Socket Detail See 2 13 11 FAN Connector Detail See 2 14 12 System Status Indicators Detail See 2 16 RABAID BRR ZS GALAXY FAR EAST CORP 2 Information for Hardware Installation 2 1 Outside View of GFEC EK2SF1020 Development Board The following 1s the outside view of GFEC Stratix II development board in Its actual size Ip xnens isa ie died _ grenen rd AT uu 1 1 1 1 2 outside view of GFEC Stratix development board 2 2 Structural D
44. the mode of Active Serial Programming AS once the burning is finished Altera Stratix II Device Family will plan automatically each time the board power enabled 1 Choose Active Serial Programming Mode If Hardware Setup is set as No Hardware repeat Step 2 Step 3 in 3 3 1 mode d filtre car 2 Hardware Setup ByteBlaster LPT1 pl Start gi Stop urs Delete 2 Choose files to be burned into Serial EPROM ESBOSIRA GALAXY FAR EAST CORP Select Programming Look in tutorial db IC sire akion pot I J POF File 4 5 Date Modified 10 25 2004 5 28 PM Size 2 00 MB s gt o P 5 X Filename Files of type POF Files pof 3 Confirm Device Checksum and Program Configure and check them filtref cdf Active Serial Programming El filtref pof lt gt 7 p L 0 SX A Bp Add File IP Add Device T Up Dawn 4 Choose Start to begin burning ABAID 5 o GALAXY FAR EAST CORP 4 Appendix 4 1 Guide for Installing Byteblaster MV II in Windows 2K XP During hardware setup if no hardware can be found the installation should be performed manually according to the following steps 1 Support version B Maxplus2 9 6 or later
45. 0 B3 E24 9 9 B3 E24 B3 F24 9 9 B3 F24 B3 A25 Q Q B3 A25 R101 1K Ohm 4 R103 1K Ohm 4 B25 194 94 B3 B25 B3E ria BE ad FERNER B3 C25 9 BS B2B 83 025 BEI lt 02 090 3 D25 96 96 3 D25 B3 25 19 a7 E25 B3 F25 98 og F25 B3 G25 99 99 B3 C29 99 99 B3 G25 00 00 itle VCC V43 lt Title gt J36 lt Size Document Number Rev Doc A Date Wednesday April 13 2005 Sheet 7 of 17 104 104 VCC V43 F11 E11 104 D11 4 104 C11 104 B11 6 104 A11 104 F10 Q 104 D10 9 104 C10 0 104 B10 104 A10 4 104 F8 104 E8 6 104 D8 104 C8 8 104 F9 9 104 E9 0 104 C9 104 B9 104 A9 R113 1 Ohm TROSK B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4_B15 B4_C1 B4 D1 B4_E15 B4_A16 _ B16 B4_C1 B4 D1 B4 B4 C4 5 5 05 E5 B6 C6 D6 E6 A7 B7 C7 D7 E7 B8 12 12 DIS D12 F12 B13 C13 D13 E13 F13 G13 14 14 014 14 F14 F15 5 5 6 6 6 LIB O LS IA LA N V43 VCC V43 AG 4 11 AG 4 B4 E11 104 12 4 B4 12 y B4 D11 104 812 4 P B4 812 103 L19 B4 C11 104 C12 B4 C12 103 K19 B4 B11 104 012 B4 012 103 J19 4 11 104 12 4 F12 m B4 F10 104 81
46. 02 N22 2 22 IDE MeS sd p COELO E n 102124 B2 K29 102 F32 B2 F32 102 N23 B2 N23 102 630 102 123 2 132 102 1 4 2 1 102 N24 4 B2 24 102 G29 2 i p 2 _1 38 lt 2 131 102 632 2 G32 102 N25 2 25 102 F30 ED 2 30 102 G31 B2 G31 102 N26 2 26 102 F29 9 2 2 129 102 G30 2 G30 102 N27 2 27 102 E30 B2 M32 102 629 8 2 G29 102 M22 7 2 22 102 E29 9 re B2 M31 102 32 Q B2 H32 102 M23 9 2 23 IG Ded pol 39n B2 M30 102 Hat B2 H31 102 M24 2 24 102 029 2 2 29 H30 2 30 102 M25 2 25 7CLKn 2 31 102 29 2 29 102 M26 2 26 2 30 102 M27 2 27 2 29 z 2 8 40 Bo pao _ R93 1K Ohm S R91 1K Ohm diues 4 41 gt BIE i2 1 12 ____ B2 P31 1 C BE1 42 R31 a gt rv 2 R30 QS 32X861 QS 32X861 LL 9982 R30 ED ag Fan 29 Be Te D 0 127 lt Title gt B1E BIE Size Document Number Rev B Doc A Date Wednesday April 13 2005 Sheet 6 of 17 R32 C167 VREF3 li 25901020 VOC DDR Vref vor va 8 VCC V43 VCC V43 ve 2 U1C 40 2 2 2 2 Pas A26 B3 A26 03 G25 B3 G25 regne 4 2284 015 103 826 4 4 B3 B26 103 F25 4 4 B3 F25 uj uj uj 2 43 Dyer 108 025 B3 C26 103 E25 B3 E25
47. 08 22 2 108 AB18 B8 AJ22 B8 AD20 B8 AJ22 108 AJ23 caste Pes AB19 108 19 8 22 8 20 8 22 Y 108 AJ25 AB20 108 20 B8 AL22 9 9 88 AF20 9 9 B8 AL22 VCC V43 30 VCC V43 9 108 AJ26 aoe ee ce AR 21 8 AM22 a 8 20 8 AM22 108 AJ27 E p 8 AJ23 8 20 B8 AJ23 108 AJ28 PQ16B2 B8 AK23 G 8 AB21 B8 AK23 ara DQ17B2 B8 AL23 B8 21 B8 AL23 B8 23 A 021 B8 23 46 8 AG21 46 08 AG21 8 24 B8 21 B8 AK24 B8 AJ25 A 108_ 25 B8 21 108 AF21 B8 AL24 B8 21 B8 AL24 B8 AK25 Y 108 AK25 B8 21 FY 108 21 8 AM24 8 21 B8 24 B8 AL25 108 AL25 B8 AD21 A 108 AD21 8 AJ25 8 AD22 B8 AJ25 B8 25 108 25 B8 21 108 21 B8 AK25 9 8 22 Q Q B8 AK25 B8 AJ26 108 AJ26 B8 21 A 108 21 B8 AL25 8 AE22 B8 AL25 B8 AK26 10 108 AK26 B8 20 10 108 20 25 B8 AF22 25 B8 AL26 108 AL26 8 20 108 20 B8 AJ26 G 88 AG22 B8 AJ26 B8 26 0 a 108 AM26 B8 AF20 a 108 AF20 B8 AK26 B8 AH22 B8 AK26 B8 AJ27 108 AJ27 B8 AE20 108 AE20 B8 AL26 A 8 AD23 B8 AL26 B8 27 4 4 108 27 B8 AD20 A 108 AD20 8 AM26 B8 AE23 B8 26 B8 AL27 108 AL27 B8 AC20 108 AC20 8 AJ27 8 AF23 8 AJ27 8 27 108 27 8 20 108 20 8 27 05
48. 1 AL B1 AE30 101 AE25 2 T32 101 AE29 B1 AE29 101 AE26 2 T31 101 AF32 6 B1 AF32 101 6 2 T30 1 AF31 1 1 101 AE28 B2 T29 101 AF30 Q 40 B1 AF30 101 AD24 B2 T28 101 AF29 9 9 Bi AF29 101 AD25 Q B2 T27 101 AG32 0 8 Bi AG32 101 AD26 D 1 AG31 B1 AG31 101 AD27 U32 101 AG30 Bi AG30 101 AC24 031 101 29 1 29 101 25 030 101 AH32 B1 AH32 101 AC26 129 101 AH31 AH31 101 AC27 V31 101 AH30 Q 0 B1 AH30 101 AB23 Q V30 101 AH29 O 9 B1 AH29 101 AB24 W32 101 AJ32 0 Q B1 AJ32 101 AB25 0 W31 101 AJ31 B1 AJ31 101 AB26 101 AJ30 B1 AJ30 101 AB27 101 AJ29 B1 AJ29 101 AB28 R77 1K Ohm R79 1K Ohm GND 1 474 GND 2 45 BIE 47 QS 32X861 QS 32X861 1_ U28 B1 U27 B1 U23 B1 U22 U12 U32 B1 V29 VOC V43 V43 B1 V28 PE 07 gr fo B V23 B1 W28 101 Y31 B1 Y31 101 AA22 B1 W27 101 Y30 B1 Y30 101 AA23 B1 W26 101 Y29 Bi Y29 101 24 B1 W25 101 Y28 1 28 1 25 Bi W24 1 AA32 6 2 101 AA26 B1 W23 101 AA31 1 1 101 27 Bi W22 101 Q AQ B1 AA30 101 Y22 8 B1 Y27 101 AA29 Q Q B1 AA29 lO1 Y23 Q B1 Y26 101 AB32 0 8 B1 AB32 101 Y24 0 B1 Y25 101 AB31 B1 AB31 101 Y25 B1 Y24 101 AB30 B1 AB30 101 Y26 B1 Y23 101 AB29 B1 AB29 1 Y27 B1 Y22 101 AC32 6 B1 AC32 101 W22 6 B1 AA27 101 AC31 B1 1 101 W23 B1 AA26 101 AC30 Q 0 B1 AC30 101 W24 Q B1 AA25 101 AC29 Q Q B1 AC29 101
49. 2 102 123 124 L25 L26 L27 L28 K24 K25 K26 K27 J26 J27 H27 H28 G27 G28 F29 F30 R87 1K Ohm D32 D31 D30 QS 32X861 5 5 Q N N Q 0 06 B2 H28 06 0 C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C D C 02 ae y N s DO 123 124 125 126 127 128 24 25 K26 K27 J26 427 27 28 G27 G28 F29 F30 lt rar re are er et tt nt OOMJMNINOAMDUITIRAVOLVLVNN 00 V43 V43 U33 2 J32 B2 32 166 102 31 2 31 102 930 7 82 230 1 V23 L4 50 VREF2 101 V24 B1 V24 102 429 B2 J29 43 _____ gt 101 V28 B1 V28 102 K32 6 B2 K32 142 gt 101 V29 1 V29 102 K31 2 K31 101 U22 B1 1 22 od ed 02 K30 8 0 2 K30 140 2 101 U23 B1 023 UiB 3 102 29 9 2 29 _____ gt B1 027 102 132 0 8 2 132 Ian SN PR 25901020 102 131 B2 131 a BANK 222 102 130 4 4 2 130 102 T22 B2 T22 102 129 2 129 102 23 2 123 102 M32 6 B2 M32 102 R22 B2 R22 102 M31 2 M31 102 R23 2 R23 102 M30 B2 M30 102 R24 5 2 R24 02 T32 0 0 02 T32 IO C
50. 2 40 107 B7 AD13 9 9 107 7 AC13 0 2 107 B7 AB13 107 B7 AG12 4 4 107 B7 AF12 107 B7 AE12 6 107 B7 AD12 107 B7 AC12 2 0 107 B7 AB12 9 9 107 B7 AD11 0 2 107 B7 AC11 107 B7 AB11 6 107 B7 AD10 107 1 Ohm 4 12 Ww BE1 U46 QS 32X861 R68 UN 7 11 AJ11 AH11 AG11 AF11 AE11 AJ10 AG10 AF10 AE10 AH9 AG9 AE9 AH8 AG8 AF8 AH7 AH6 AH5 AG15 AH14 AG14 AH13 AG13 AF13 AE13 AD13 AC13 13 12 12 12 AD12 AC12 12 AD11 AC11 AB11 AD10 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 U1G 49 VREFB7NO VREFB7N1 VREFB7N2 vig DQ0B3 O DQ2BO AM7 ay 00283 AMS AM9 AMIO mid IO DQ483 ami IO DQSB3 AN IO DQ7B2 10 00783 AM16 amig 10 09983 ar ALE ArH IO DQ0BO are DQS2B ALT 110 DOSn2B ALs DQS3B aa 10 ALIO 008 4 IO DQ6B2 IO DQS7B ine DQSn7B ALT ar 10 DOSn9B APTE IO DQ9BO ALTO 6 FBn OUT2p AK4 CLK6n aks 00508 005 0 AK7 DQ2B1 DQ4B1 Akin 00548 mei IO DQS6B 0 005 6 O DQ7BO
51. 22 C22 H23 179 B22 J23 180 82 A26 H24 182 83 B26 A23 84 C26 B23 85 106 E26 D23 186 87 27 E23 27 24 189 027 24 190 E24 92 ros 93 D28 A25 94 A28 B25 pers coo om II xm NO PAX 123 ZS o GALAXY FAR EAST CORP B29 F25 198 aos 3NI GNI 200 Tab 8 2 amp JP6 ID 2 5 3 amp 7 GND 2 X 1 ui Or ACT AB5 116 ABS AB8 119 AB9 AAT 123 8 DSAC2 27 127 Y6 30 AB3 Y8 130 Y9 133 w4 W7 137 WS 138 10 140 W11 AX 123 ARRAS GALAXY FAR EAST CORP 147 9 amp JP7 I d p X 56 n4 156 R10 160 R11 161 P5 163 164 167 N6 170 N7 9 173 N10 174 M7 177 8 178 10 180 181 L7 184 L L10 187 K6 188 194 091 08 001 az 4 gt GALAXY FAR EAST CORP D1 5 196 Gs 198 Tab 10 amp JP7 ID 2 5 4 amp h i 01 S gt 1 2 29_ Reserve 102 4 29 26 104 5 AM28 25 105 AL28 625 7 28 107 ADS 10
52. 3 10 B4 103 F19 Q B4 D10 104 C13 9 Q B4 C13 103 L18 0 C10 104 013 013 103 K18 B4 B10 104 E13 B4 E13 103 F18 4 B4 A10 104 F13 4 4 B4 F13 103 E17 104 Li7 B4 F8 104 G13 B4 G13 104 K17 B4 E8 104 A14 B4 14 104 116 6 B4 D8 104 B14 B4 14 104 K16 0 C8 104 014 Q D 4 014 104 115 Q 9 B4 F9 104 E14 9 9 B4 E14 104 K15 Q B4 E9 104 F14 D Q B4 F14 104 J15 0 C9 104 F15 4 15 104 114 B9 104 14 B4 A9 104 J14 R107 1K Ohm R105 1K Ohm 15 B3E ess Er QS 32X861 QS 32X861 J6A 102 V43 V43 103 BA S 103 M 104 8489 104 B4 5 105 4 9 105 B4 C4 48 48 106 B4E9 106 5 4 107 107 B4 B5 104 A4 46 B4 M 108 4 8 108 8 B4 C5 104 84 B4 B4 109 B4 08 ___ 100 4 05 104 C4 B4 C4 104 H14 140 4 8 110 0 104 5 B4 A5 104 G14 4141 BA F8 111 104 B5 6 B4 B5 104 L13 6 112 A10 104 C5 B4 C5 104 K13 113 B4 B10 113 84 C6 104 D5 Q AN B4 D5 104 J13 Q B4 D6 104 E5 9 B4 E5 104 H13 115 4 Di0 145 104 0 8 104 112 0 116 B4 F10 2 416 A7 104 B6 104 K12 117 BA A11 __ 117 B4 7 104 C6 B4 C6 104 J12 118 B4 118 Q 4 C7 104 D6 B4 D6 104 H12 119 B4 Cii __ 110 4 07 104 6 4 104 G12 6 120 011 __ 120 0 E7
53. 3 B20 0 IO PLL11 FBn OUT2n IO DQ10T1 103 E20 103 820503 821 55 DQ10T3 E20 R95 1K Ohm R97 1K Ohm rek R99 1K Ohm 108 BET SN B22 b lm o barro LE24 103 E24 BSE 12 s 4 ERE 12 ___ 23 lt lt 523 823 10 DQS13T IO DQSnt5T 25 2 Ese 6103 E25 103 B25 IO DQSn13T lO DQ15T3 E26 QS_32X861 QS_32X861 103 25 lt lt IO DQS14T IO DQ15T2 03 E27 um IO DQSn14T IO DQ17T3 103 E28 103 B27 lO3 B28 IO DQS16T lO PGM2 103 F18 SPD SCL 555537829 922 IO DQSN16T 734 103 F20 103 F19 359 KEN CH 103 B29 7o3 c17 c17 DQ17TO 103 F21 Pisa 53 4 52 2 et F22 4 103 C20 E la cher EE SS Ed 103 215503 C22 RA 103 F25 B3 F18 z 3 3 C22 11 57 88 017 87 Lir Xe o LG B3 K18 157 g 3 C23 165 54 IO DQI3T IO VB3NO 1 03 G20 B3 L18 B3 C18 B3 L18 103 24 lt 9103 C25 DQ13T2 VB3N2 1 1 E ac gt 103 02595103 C26 me VBSN2 2 Gog 103 023 B3 K19 161 IO DOICTI 1 4 03 624 B3 2 162 119 103 28 lt lt 93 28 IO DQS17T IO INIT DONE 83 1322 818 6 620 103 C29 bien 108 88 B3 H20 64 54 H20 LE 103 H21 J20 1g 65 J20 IO Vase H22 108 H22 103 B3 K20 66 _
54. 30 JP1 98 FPLL8CLKn Input Bl AJ29 VEIL FPLL9CLKp Input B6 AJ3 JP3 4 FPLL9CLKn Input B6 AJ4 JP3 5 19 G14 G27 G28 H3 PAX 3 BRR 23 GALAXY FAR EAST CORP Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve I O I O Reserve I O I O I O 20 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve I O I O Reserve I O I O I O JP3 106 JP3 107 JP4 193 JP3 104 JP4 105 JP4 157 JP1 199 JP1 198 JP4 121 JP4 106 JP2 71 JP2 198 JP3 198 JP3 199 JP2 138 JP1 105 JP1 104 JP3 82 Doi Ree 10 5 o GALAXY FAR EAST CORP I O I O JP3 83 H5 NC I O Reserve Reserve JP3 196 H6 NC I O Reserve Reserve JP3 197 H9 NC I O Reserve Reserve 2 123 m J29 NC I O I O I O JP1 23 J30 NC I O I O I O JP1 22 Reserve Reserve JP1 115 A L28 NC I O Reserve Reserve JP1 114 N10 NC I O I O JP3 174 x I O I O 163 175 p NC I O I O I O JP1 139 23 I O I O I O JP1 138 W10 NC I O I O JP3 140 WII NC I O I O I O JP3 141 W22 NC I O I O JP1 167 W23 NC I O I O JP1 166 Tab 4 Not Compatible Pins in All Family If there is any user I O unused we recommend to suspended joint them unused pin to ground should be set in Quartus II and the dedicate input should be pull high or pull low through a resistance
55. 4 104 A7 104 8 104 A9 104 A10 104 A11 104 A12 104 A14 104 A16 104 104 B5 104 B7 5 104_ 8 104_ 10 5 104 B11 104 B14 104 B15 104 B16 104 C4 04 lt lt 104 8 104 C9 104 C10 104 C12 104 C13 104 C15 104 C16 104 D5 104 D6 104 D7 104 D8 104 D10 104 104 D12 104 D13 104 D14 104 D15 104 D16 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 R56 0 Ohm A4 A5 A6 A7 A8 A9 A10 A11 A12 A14 A16 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C15 C16 D5 D6 07 08 010 011 012 013 014 015 016 C168 VREF4 EP2S901020 U1D Soto cen LL LL LL LLI LLI LLI EEE 11000 DQOT2 iO 20170 _002 2 25 4 10_DQ1T3 IO DQ2T1 00213 DQS4T1 24 4 DOSTI IO DQSn4T DQ3T3 IO DQ6TO IO DQ5TO IO DQ78TO IO DQ7T1 DQSn8T ace 10 IO PLL5 FB OUT2n DQ9T3 IO CLK13p IG IO DQS4T2 IO DQOTO DQS4T IO DQS4T3 29 DQS6T 10 DQSneT DGSST IO DQ78T1 5 0 _ DQS8T DQ5T1 IO DQ78T3 IO_DQ7T2 IO CLK13n DQSn7T IO_DQ6T1 IO DQ6T2 DQ
56. 4 7 ET ig ETER DDR 433 DDR DM4 6 DDR 003 104 A4 6 DDR CSOn 21 0 1 uF DDR DQSO 11 D d 12 DDR DMO DDR DQ34 135 196 DDR DQ38 d DDR 0950 006 127 138 RN10 50 Ohm RN12 50 Ohm a ds 16 DDR 5 39 440 DDR 0039 9 DDR DO 44104 9 DDR 0045 2 103 co por pos FT 37 18 por per DDR 6040 40 142 _ DDR 0044 DDR DQi7 DDR DO 99 03 03 008 f w 2 _ DDR Dar Ta Ha 5 DDR DQ20 99 04 16 5 DDR DO44 55103 021 32 1 22 DDR 0041 445 146 DDR DQ45 DDR DQ16 104 08 DDR 0040 023 DDR 009 24 DDR 0013 DDR 0055 147 148 DDR DM5 4 DDR 0015 55404 08 4 DDR 5039 103 023 DDR bast 25 099 26 _ DOR DM CE T 11 99 04 9 DDR DQ35 99103 022 28 DDR DQ42 P 51 952 152 DDR 0046 DDR DQ14 99 104 7 DDR DQ38 2995 20 T 0885 1 1 DDR 0014 DDR DQ43 153 2942 54 DOR 0047 5 5 E ay 32 _ 155 156 2 BU XK 104 PG A108 C20 E Pup LE 157 0025 RN14 50 Ohm RN16 50 Ohm E ae 7 TV lO4 C15 VSS27 lO4 C16 DDR 0928 DDR DOS2 47103 pps 6 ie I DDR 024 9104 014 DDR DQ48 2093 529 328 TREN ES 952 164 DDR pose DDR 0023 04 011 6 DDR
57. 5B VESND S 108 AF22 en 102005188 IO VBeNO KH 8128 DQSn16B IO nRS HA VREF8 VREF8 08 AL29 0 E AF19 108 19 49 149 1 149 49 MT skr IO VBBN2 1 arog 108 AE20 Cr er E 4 4 B8 AC17 2 a 8 18 S amp iO8 AK20 1 On A 108 AE22 22 AG AG 8 AG17 AG L46 Dr 108 21 0 E AE23 E 4 4 B8 AH17 4h 108 AK22 S E ADia 108 AD18 i 8 18 pg 108 22 AD19 108 AD19 sped 4 4 B8 AC18 4 Ma B7E B7E 108 AK24 0156 Anon 198 AD20 E 4 4 B8 AD18 4 TR 108 AK25 2 108 AD 1 4 B8 AG18 108 AK26 __ 091480 VB8NO 6 an 108 AD22 40 40 40 40 AK AD B8 AMT S B8 AC19 AJfA ME 108 AK28 28 2 108 AC17 8 AJ20 a 8 AD19 8 AJ20 108 AK29 E 108 18 8 20 B8 AE19 B8 AK20 ios 298 7 __ Lye 10 108 19 B8 AL20 G 8 AF19 B8 AL20 5108 AJIB Alte 2 rm Agen D 20 108 20 AJ21 B8 AG19 AJ21 EA 108 AC21 21 A 8 7 7 B8 21 108 AJ20 120 aR E 108 22 B8 21 B8 AB20 21 08 AJ21 a ME LE 108 AB17 B8 21 B8 AC20 B8 21 1
58. 8 AJ28 AM27 127 m lan AES3 __ 2 14 AL26 114 15 26 AH22 115 17 AM25 117 18 125 __ 22 118 AC22 21 AM24 621 121 22 AL24 AF21 122 24 AM23 124 25 AL23 21 125 26 23 AB21 126 28 AM22 AG20 128 29 AL22 AF20 129 31 AJ22 131 32 AM21 20 132 aslAL21 AB20 133 35 AJ21 AGI9 135 36 120 9 136 38 20 138 39 9 ACIO 139 4 19 AB10 140 41 AL19 141 42 AL18 __ 18 142 alakis PG 1 GALAXY FAR EAST ESBOSIRA 45 AH18 AHI7 145 AC17 147 17 148 Tab 11 JP4 amp 1 8 nxn 8 61 AHI5 4 161 62 14 AG15 1162 63 AL14 14 163 64 65 13 AHI3 165 AKI3 AGI3 166 AMI2 AEI3 168 AL12 AD13 1169 71 12 AB13 171 72 AMII 2 172 73 74 AKU AE12 75 AMIO AD12 175 76 2 1176 77 AK10 2 78 9 178 79 AL9 ACII 179 AK9 180 si 82 ALS 182 83 AKS AHII 183 85 11 185 ALT 11 186 ss AM6 AF10 189 AL6 10 190 AK6 9 AGS 091 DH ABAID 5 o GALAXY FAR EAST CORP 193 AHS oa fais 19 ALA AH6 19 AHS
59. 9TO IO DQ6T3 IO 5 OUTOp _0078 2 819 IO CLK12n VBAN2 90 DQSOT 4 0 90 DQSNOT IO VBANO 1 1 1 _ 1 2 IO VBANO 2 DQSn2T IO VBAN1 1 3 IO DQ3T2 IO VBAN1 2 DQ3TO VB4NO 3 DQS5T IO VBANO 4 DQSn5T IO VBAN1 3 DQS7T IO VBAN1 4 IO VBAN2 1 IO PLL5 OUTOn 4 0 5 op PLL5 IO VBAN1 5 527110 DQOT1 IO VBAN1 6 57 10 DOIT1 IO VBAN2 2 5 DQS2T VBAN2 3 510 19 DQS4TO IO VBAN2 4 DQ5T2 IO VBAN2 5 DQ5T3 VB4NO 6 IO DQ7TO IO VBAN1 7 514 DQAT2 IO VBAN1 8 IO VBAN2 6 IO PLL5 FB OUT2p IO VBAN2 7 IO UTIA VBAN2 8 h 104 6 104 104 E7 2 104 E8 9 104 104 104 E13 4 104 104 gt 104 E16 104 F8 gt 9 104 F9 104 104 F11 104 104 4 104 9 104 104 104 104 4 104 104 104 104 14 __104 14 104 K 104 K 104 104 K13 K 14 104 K14 104 104 104 104 104 4 104 LS ALO LN 104 115 6 104 104 Title Size Document Number B Doc Date Wednesday April 13 2005 Sheet ES 104_E5 104_E6 104_E7 E9 104_E8 104 E13 E15 104 E15 104 E16 104 F8 104 F9 104 F10 F12 104 F11 F13 104 13 104 F14 104 F15 104 F16 104 G10 104 G11 104 G12 Gi4 104_G13 H9 H11 H12 H13 H14 J11 J12 J13 104 J13 10414 lt 104 H14 415 K11 K12 104 K12 04 K15
60. A 5 DDR 0025 59104 010 5 DDR DO49 5 53 650 i En EET 196 J DDR 72 DDR DP4 x EN 198 RN22 50 Ohm RN24 50 Ohm DDR DP1 CBS 174 DDR DP5 99 00 9 DDR DP6 9 DDR 0062 44103 pog A 0 DDR DP2 104 G13 0 DDR 0058 103 027 DDR 00 8 77 78 DDR DM8 DM8 _ 9 4 pid DDR DM7 903 027 DDR DP2 I 7 DDR DP6 DDR 0058 DDR 0057 103 B27 H HE 10K Ohm DDR DP5 DDR 0061 DDR DP7 104 F14 103 A29 DDR DDR DQ57 8 86 104 F13 103 A28 DDR DP4 104 B14 DDR DQ60 B29 6 DDR DPO 6 DDR 0056 lon lO4 E13 A27 104 E15 104 EI roo DDR_SO DIMM rn 2 Me DDR 11 8 94 DDR 99104 19 CLKet 95 Pag CLKeO 6 epu DDR A13 9 DDR DDR 2 DDR Ai a too DOR ia DDR A9 I io 102 As 103 04 DDR DP7 DDR DQ63 47103 pog A7 105 DDR Ae DDR I Es 5 DDR 59 DDR AS w 08 1 1 DOR DDR A3 I 109 2 RN30 50 Ohm DDR Ai I 41 112 DOR AO 2 DDR 2 103 19 VDD20 is 0 DDR 103 J19 DDR A10 BA DDR BA1 a A4 att DDR BAO 117 Di18 D R DDR A5 2 1 DDR Wen
61. BOSIRAU GALAXY FAR EAST Version Change Record V0 50 Alpha Version V0 80 Beta Version V0 90 Pre Release 1 m V1 0 The first version manual V2 0 The Board Version C amp Bug fixed A 9 5 X
62. D 4 Compilation Hierarchy Compiler Tool 54 filet E Simulator Tool Ti Anal d iming Analyzer Tool Resource Optimization Advisor l Timing Optimization Advisor Flow Status Successful Mon Oct 25 17 28 45 2004 Quartus Version 4 1 Build 208 08 10 2004 SP 2 SJ Full Version amp Revision Name filtref e Chip Edkor Top level Entity Name filtref amp RTL viewer Family Stratix ax Technology Map Viewer Device 2560 1020 5 5 Timing Models Production SignalTap 11 Logic Analyzer Total ALUTs 32 48352 1X In System Memory Content Editor Total registers 58 Ja Programmer Total pins 22 718 3 Total memory bits 0 2544192 0 Megatiizard Plug In Manager DSP block 9 bit elements 0 288 0 2 Full Compilation oos Analysis amp 100 00 Fitter 00 02 Assembler 00 01 SOPC Builder Tcl Scripts Customize Options License Setup 2 Timing Analyzer 0000 7 amp Info Generated files fitref filtret Y sdo ir in Jeda shera adssignsd1 jud El 42 Info Quartus EDA Netlist Writer was successful 0 errors 0 warnings I Info Quartus Full Compilation was successful 0 errors 15 warnings lt m gt System Processing Message 0 of 278 Location Total PLLs T
63. FI B6 AAS 4 AAS B6 AG2 B6 AA2 B6 AA2 1 4 B6 AAT B6 AA BG BG BG BG 16 B6 AB3 30 9 86 AB3 B6 2 Q 9 6_ 2 B6 1 8 BG ABI BG B6 ACA B6 B6 AJ3 B6 AC3 26 5 B6 BG AJ B6 AC B6 AC B6 B6 ACi 2 4 B6 B6_AD4 B6_AD4 B6 AD3 B6 AD3 B6 AD B6 AD BG AD 86 AD pa B6 49 AE4 ES 18 AE AE Rizg 95 32086 BG 5 BG AE 1K Ohm B6 BG AFS 4 4 AF B6 AF BG AF2 B6 AFI BG AF BSE B6 AG2 B6 AG2 B6 AGi 19 9 AGI 9 09 B6 AD7 09 9 B6 AH4 BG B6 B6 B6 AH2 B6 5 B6 B6 B6 AJ3 04 B6 AF5 O4 4 6 AJ3 B6 AJ2 0 B6 AG4 0 B6 AJ2 B6 0 AG3 B6 SOLC TOLC ED EJ XS Y4 Y2 AA4 AA2 AA1 AB4 AB3 AB2 1 2 1 AD4 AD3 AD2 AD1 5 V43 GND 1 GND 2 R131 1K Ohm B5E DE BSE Q R127 1KOhm 472 BEI QS 32X861 VCC V43 6 B6 AA6 106 4 B6 AA7 4 106 AES AA8 4 106 AE2 B6 AA9 106 AE1 B6 AA10 6 106 B6 AA11 0 106 B6 Y6 8 9 106 2 6 Y7 9 8 106 B6 Y8 0 106 AG2 B6 Y9 4 06 AG1 B6 Y10 4 106 B6 Y11 106 4 6 106 B6 W5 0 106 W6 8 9 106 AJ4 B6 W7 9 8 106 W8 0 106 A
64. IDTQS32X861 HIGH SPEED CMOS 20 BIT BUS SWITCH WITH FLOW THROUGH PINOUT INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION N A N 13 po N N N md A N N DO QVSOP TOP VIEW ABSOLUTE MAXIMUM RATINGS Symbol Max Unt 120 Maximum Power Dissipation TA 85 Storage Temperature 65 to 150 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Vcc terminals 3 All terminals except Vcc CAPACITANCE 25 f 2 1 0M Hz OV Vout 20V Pins Quickswitch Channels Switch OFF NOTE 1 This parameter is measured at characterization but not tested PINDESCRIPTION Description Function Connect Come 7 Connect Z NOTE 1 HIGH Voltage Level L LOW Voltage Level Z High Impedance IDTQS32X861 HIGH SPEED CMOS 20 BIT BUS SWITCH WITH FLOW THROUGH PINOUT INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following C
65. IFFIO RX78n DIFFIO RX76p IO DIFFIO RX76n IO DIFFIO RX74p IO DIFFIO RX74n IO DIFFIO RX73p IO DIFFIO RX73n IO DIFFIO RX71p IO DIFFIO RX71n DIFFIO RX69p IO DIFFIO RX69n DIFFIO RX66p DIFFIO RX66n DIFFIO RX65p IO DIFFIO RX65n IO DIFFIO RX64p IO DIFFIO RX64n DIFFIO RX63p DIFFIO RX63n IO CLK8p IO CLK8n FPLL9CLKp FPLL9CLKn IO DIFFIO RX81p IO DIFFIO RX81n DIFFIO RX79p IO DIFFIO RX79n IO DIFFIO RX77p IO DIFFIO RX77n DIFFIO RX75p IO DIFFIO RX75n DIFFIO RX73p C170 0 1uF lt lt 5 90 IO DIFFIO RX73n 90 IO RX72p IO DIFFIO RX72n IO DIFFIO RX70p IO DIFFIO RX70n IO DIFFIO RX67n IO DIFFIO RX67p IO RX68p IO DIFFIO RX68n IO DIFFIO TX70p IO DIFFIO TX70n IO DIFFIO TX67p IO DIFFIO TX67n CLK9p CLK9n VREF6NO VREF6N1 VREF6N2 DIFFIO RX65p 90 DIFFIO RX65n 90 DIFFIO RX69p 90 DIFFIO RX69n 90 IO IO DIFFIO TX77p IO DIFFIO TX77n IO DIFFIO TX79p IO DIFFIO TX79n IO DIFFIO TX74p IO DIFFIO TX74n IO DIFFIO TX76p IO DIFFIO TX76n IO DIFFIO TX71p IO DIFFIO TX71n IO DIFFIO TX69p IO DIFFIO TX69n IO DIFFIO TX66p IO DIFFIO TX66n IO DIFFIO TX63p DIFFIO TX63n IO DIFFIO TX83p IO DIFFIO TX83n IO DIFFIO TX82p IO DIFFIO TX82n IO DIFFIO TX80p IO DIFFIO TX80n IO DIFFIO TX78p IO DIFFIO TX78n IO DIFFIO TX72p IO DIFFIO TX72n IO DIFFIO TX68p IO DIFFIO TX68n IO DIFFIO TX65p IO DIFFIO TX65n IO DIFFIO TX64
66. IO TX51n 105 L5 IO DIFFIO RX58p IO DIFFIO TX48p 105 L6 IO DIFFIO RX58n IO DIFFIO TX48n 105 gt IO DIFFIO RX54p IO DIFFIO TX47p 105 K7 IO DIFFIO RX54n IO DIFFIO TX47n lO5 Je IO DIFFIO RX52p IO DIFFIO TX42p 7 IO DIFFIO RX52n IO DIFFIO TX42n 105 H5 3 IO DIFFIO RX51p IO DIFFIO TX110p 90 105 H6 IO DIFFIO RX51n IO DIFFIO TX110n 90 105 G5 IO DIFFIO RX49p IO DIFFIO RX109p 90 105 G6 IO DIFFIO RX49n IO DIFFIO RX109n 90 105 T10 IO DIFFIO RX47p IO DIFFIO TX62n 105 T10 DIFFIO RX47n IO DIFFIO TX62p 105 T11 IO DIFFIO RX45p IO DIFFIO TX60n 105 R10 m IO_DIFFIO_RX45n IO_DIFFIO_TX60p 105 P8 5 11 IO DIFFIO RX43p IO DIFFIO TX54p 2210 DIFFIO RX43n IO DIFFIO TX54n 7 CLK11p IO DIFFIO TX53p 195 CLK11n IO DIFFIO TX53n 105 M8 IO DIFFIO TX59n IO DIFFIO TX50p 105 9 gt IO TX59p IO DIFFIO TX50n 195 L7 IO DIFFIO TX56n IO DIFFIO TX46p 105 L8 TX56p IO DIFFIO TX46n 195 K8 DIFFIO RX56p DIFFIO TX44p 105 K9 IO DIFFIO RX56n DIFFIO TX44n 195 J8 IO DIFFIO RX57p IO DIFFIO TX43p 105 J9 IO DIFFIO RX57n IO DIFFIO TX43n 105 P10 74 IO DIFFIO RX55p IO DIFFIO TX57n 195 Pit IO DIFFIO RX55n IO DIFFIO TX57p 105 N10 DIFFIO RX53p 10 DIFFIO TX100p 90 105 N11 IO DIFFIO RX53n IO DIFFIO TX100n 90 195 M10 74 IO DIFFIO RX50p DIFFIO TX49p lO5 M11 IO DIFFIO RX50n IO DIFFIO TX49n 105 L9 O DIFFIO RX108p 90 TX45p 105 L10 IO DIFFIO RX108n 90 IO DIFFIO R
67. J2 B6 W9 6 106 B6 W10 W11 J 47d ge QS 32X861 106 106 106 106 106 106 106 106 V4 V5 V6 V7 V9 V10 U10 Uti AG 106 4 106 44 106 4 106 4 106 4 106 4 106 106 106 106 106 106 106 106 106 106 106 106 6 106 106 CO s DO 5_ 5 105 T6 105 T10 5_ 11 105 R4 105 R5 105 105 R7 105 R10 105 R11 106 W1 106 W2 106 V2 106 106 Ui 106 U2 AA8 AA10 AA11 Y6 Y8 Y10 Y11 WA W5 W6 W7 W8 W9 W10 W11 106 03 106 04 amp 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 106 AJ2 AH1 AH2 AG1 AG2 AF1 AF2 AE1 AE2 AD1 AD2 AC1 AC2 1 2 1 AA2 Y2 YS W1 W2 V2 V3 U1 U2 AJ3 AH4 AG3 AG4 AF3 AF4 AE3 AE4 AD3 AD4 AC3 ACA AB4 AAA Y4 YS W4 W5 V4 V5 U3 U4 gt gt gt gt gt gt gt gt gt gt gt 2 gt gt gt D gt D DJ UJ DD s N N N s s gt gt gt gt gt gt gt gt be N gt gt 00 DJ VREF6 U1F 2 901020 BANK6 IO DIFFIO RX82p IO DIFFIO RX82n DIFFIO RX80p DIFFIO RX80n IO DIFFIO RX78p IO D
68. LKOp LENE LEES EN 2 T31 DEL IO CLKOn IO DIFFIO TX22n loa NET 2 T27 0 8 2 31 102 R26 2 R26 E 02 R31 E E 102 T28 102 R31 DIFFIO RX21p IO DIFFIO TX22p 2_ 28 102 N30 2 30 102 R27 2 R27 102 R30 pan 9 E 3 102 R27 102 R30 IO DIFFIO RX21n IO DIFFIO TX26p 102 N29 2 29 102 R28 2 R28 102 P31 102 826 102 N28 B2 N28 102 R29 B2 R29 pe pap lo EM de 102 P27 102 PS244 T62 N31 IO DIFFIO RX22p IO DIFFIO TX28p 75 102 P26 O2 N30 IO DIFFIO RX24p IO DIFFIO TX28n FSS 65 R85 1K Oh R89 1K Oh 102 M32 ree 306 102 N26 BIE 1 49 2 BE a Mal O DIFFIO_RX23p TX90n 092 102 M27 IO2 132 DIFFIO RX23n IO DIFFIO TX32p F 102 M26 102 131 IO DIFFIO RX25p IO DIFFIO TX32n H 2 52128 QS 32X861 QS 32X861 102 IO DIFFIO RX25n DIFFIO TX47p 90 55 3155727 IO DIFFIO RX29p DIFFIO TX47n 90 DIFFIO RX29n IO DIFFIO TX37p ES NUT IO DIFFIO RX31p IO TX37n 328 5997 Iz Ne IO DIFFIO RX31n IO DIFFIO TX39p DIFFIO RX32p IO DIFFIO TX39n HER T rear IO DIFFIO RX32n IG DIFFIO TX40p 258 a TOK oe TENET DIFFIO RX33p IO DIFFIO TX40n UART IO DIFFIO RX33n DIFFIO RX50n 90 UART RTS LB UN _ NET IO DIFFIO RX34 DIFFIO RX EE m UART CTS 02 FS ion IO ee 02
69. ORPORATE HEADQUARTERS for SALES for Tech Support 4 6024 Silver Creek Valley Road 800 345 7015 or 408 284 8200 logichelp idt com E ose 95138 fax 408 284 2775 www idt com ABAID 5 o GALAXY FAR EAST CORP 5 Reference TAB T STRATIX PANNE 17 2 STRATIX II PACKAGE OFFERINGS amp USERS I O COUNTS 17 ES 20 TAB 4 COMPATIBLE PINS IN ALL 0200000000000000000 21 Te MP 23 PEN NN 24 TE MP Nene 25 PEN 26 VED POP 27 28 TAPT hhv 29 Ter PET Nerve 30 TAB 13 UART IN GFEC STRATIX II DEVELOPMENT BOARD 34 TAB 14 GLOBAL CLOCK IN STRATIX DEVELOPMENT BOARD 35 TAB 15 CONTAINS DETAILS ABOUT QUARTUS II SOFTWARE VERSION 4 2 OPERATING SXSTBMTOS EEE 38 TAB 16 QUARTUS II SUPPORT STRATIX II TIMING MODEL amp 30 TAB 17 37 SUPPORT STRATIX II DEVICE FAMILY cette 39 FIG 1 STRATIX ILBP2S60 FLOORPLAN acissssessssidkndtebAkSenvssbersres dod 9 FIG 2 OUTSIDE VIEW OF GFEC STRATIX II DEVELOPMENT BOARD 15 FIG STRUCTURAL DIAGRAM OF GFEC STRATIX II DEVELOPMENT 16 9 8 x gt COC EIS
70. ORS FER fi KE 210 fi HE 3 INFORMATION ABOUT SOFTWARE HER RAE E 3 1 QUARTUSII VERSION SE o 3 2 VERSION SUPPORT FROM COOPERATION MANUFACTURER 888 4 Rita GALAXY FAR EAST 4 e 3 3 SOFTWARE OPERATION HER See E 39d JTAG EEE HER IRER 3 3 20 SERIAL PROGRAMMING HEER fi IE da APPENDIX SEES HS 4 1 GUIDE FOR INSTALLING BYTE BLASTER IN WINDOWS 2 fi 4 2 DODIFY THE COMPATIBILITY OF MICROSOFT WINDOW XP SP2 2 9 5 x 4 3 DIMENSIONAL DRAWING SER KES 4 4 5 2 0 00000 000000 KES 4 5 5 0000000 FER KES dX VERSION CHANGE RECORD T Bux Contact Galaxy Far East Corp Taipei Headquarters Address 14FI No 207 5 Sec 3 Beisin Rd Hsindien City Taipei County 231 TEL 886 2 8913 2200 FAX 886 2 8913 2277 Hsi
71. X48p IO DIFFIO RX48n IO DIFFIO RX46p IO DIFFIO RX46n IO DIFFIO RX44p IO DIFFIO RX44n FPLL10CLKp FPLL10CLKn IO DIFFIO TX45n itle Title Size Document Number Rev B Doc A Date Wednesday April 13 2005 Sheet 9 of 17 V43 8 vaa 024 B6 AG3 46 106 AG3 ___48 B6 AG4 4 106 AG4 B6 AF5 4 44 106 AF5 B6 Y5 AG 106 B6 AF6 4 106 AF6 B6 4 4 106 B6 5 4 106 AE5 4 44 106 B6 6 4 106 AE6 B6 Y2 4 106 B6 AD6 8 40 106 AD6 B6 4 6 106 B6 AD7 9 9 106 AD7 B6 AA3 4 106 B6 AD8 0 8 _ 8 B6 AA2 8 40 106 B6 AD9 106 AD9 B6 AA1 9 9 106 B6 AC6 4 4 106 6 B6 4 0 8 106 B6 AC7 106 AC7 ABS 106 B6 AC8 6 106 AC8 B6 AB2 4 4 106 B6 AC9 106 AC9 B6 AB1 106 B6 5 8 0 _ 5 B6 AC4 106 B6 AB6 9 9 _ B6 AC3 106 B6 0 8 106 AB7 B6 AC2 8 0 106 B6 8 106 AB8 B6 AC1 9 9 106 B6 9 106 AB9 B6 AD4 0 8 106 B6 10 106 10 B6 AD3 106 B6 AD2 6 106 B6 AD1 106 R133 1K 424 BSE R125 1K Ohm 12 1 QS 32X861 BsE C BE1 QS 32X861 VREF6 0 D 0 0 VREF6 5 T 4c EN 48 48 voc vag 025 B US ND gt 146 BEVI 148 Pago Bg E T EEE 0 44 EEE i Be Ul TD os Be vs 42 086 va 86 AE4 1 6 a0 40 B6 BY BOYS BG V BG BG B6 BG BG _ B6 Y2 BG AF2 9 B6 AM B6 AM BG A
72. apacitance at the specified frequency The A and B pins generate no significant AC or DC currents as they transition This parameter is guaranteed but not production tested lt W SWITCHING CHARACTERISTICS OVER OPERATINGRANGE Ta 40 to 85 C Vcc 5 0V 55 50pF 5000 unless otherwise noted Symbol Tm M Data Propagation Delay 23 0 25 S witch Turn on Delay VE off Delay 2 NOTES 1 Minimums are guaranteed but not production tested 2 This parameter is guaranteed but not production tested 3 The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance The time constant for the switch alone is of the order of 0 25ns for 50pF Since this time constant is much smaller than the rise and fall times of typical driving signals it adds very little propagation delay to the System Propagation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side IDTQS32X861 HIGH SPEED CMOS 20 BIT BUS SWITCH WITH FLOW THROUGH PINOUT INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDTQS XXXXX XX X Device Type Package Process Blank Industrial 40 C to 85 C Q1 48 Pin QVSOP Q1G QVSOP Green 32X861 High Speed CMOS 20 Bit Bus Switch with Flow Through Pinout P C
73. board package please check its content according to the following MStratixII Development Board MADAPTER pec power supply converter for AC 110V 220V to DC 6V 3A Power Cable I set red and white MUSB Download Cable 1 pec MCD ROM MSpecial Connector 4 pecs MHead Sink for Stratix 9 5 If you find any part absent or any damage to them please contact GFEC as soon as possible ABAID 3 BR ZS o GALAXY FAR EAST CORP 1 2 Precautions The development board 1s made up of lots of precise integrated circuits and their components Since these circuits easily subject to damage due to electrostatic influence please read the user s manual carefully and do the following preparation before installation gt _ B If you find any pin bendding or it s not easy to insert before inserting the development into the system designed by yourself you should not insert it by force Otherwise we can t offer warranty to the damaged 9 X N pin caused by doing so B You should not insert or pull out over frequently or with over force when the board were connected It is helpful to prolong service life of pins The board should be inserted or pulled out slowly in all direction so as to avoid pins being bent B Please confirm the voltage of power supply and wiring once again before you turn the power on B If the ISP function is needed you should c
74. cillator Socket 2 14 Electric Specification and Characteristics of I O Follow Through Switch In the development board all Stratix II FPGA I Os reach JP1 JP8 through Follow Through Switch Per buffer offers 20 channels Each buffer only offers max 0 5 Watt power although each channel can offer max 120mA Therefore the power is dispersed in different piece of buffer when more than one group of high current 1s needed Details about Follow Through Switch refer to the appendix 2 x AULA 2 15 System Status Indicators Five LEDs are offered on the development board System Power Good Done It means the configuration is successful if the green light becomes light or the configuration is failed if the red light becomes light 4 3V Power Good 3 3V Power Good 43 3 3V DONE PG CFEC GALAXY FAR EAST 2 16 Stacking If the FPGA Gate Count offered by the development board is not enough you can extend it by stacking up and down The only thing should be paid attention is that there should not be any confliction between pins definition so as to avoid damaging Follow Through Switch The development board offers TAG chain Through JTAG chain FPGA can be joint up in series with J26 gt 9 5 X T Single o Multi Device PAX I 5 o GALAXY FAR EAST CORP 3 Information About Software
75. iagram of GFEC EK2SF1020 Development Board The following is the structural diagram of GFEC Stratix II development board its actual size 15 OOC s s CO mi 01 5 WWW com tw 1 525 Peri CP me B 1 2V 5 SW rer Riom 2 113 PS AS Note Using DIMM Socket has to mount pull high resister first NO e 9 20 aunbijuoa ay _ ON ne nus k Tai 3 amma 9 D X gt m Taaa CANCER E zm unm gt e MT 019 18 016 n o S 9 00090 Lv GE 1 e _ L 5 B _ _ E gt 4 25 s E E s G zm 8 5 E m
76. nchu Brach Office Address 3 Fl No 526 Sec 1 Guangfu Rd Hsinchu City TEL 886 3 578 6766 FAX 886 3 577 4795 Kaohsiung Branch Office Address 10 8 Fl No 56 Minsheng 1 Rd Hsinshing District Kaohsiung City 800 TEL 886 7 223 1338 FAX 886 7 222 405 1 Tech Support Hotline TEL 0800819595 GFEC Website HTTP W W W GFEC COM TW AS D BR ZS GALAXY FAR EAST CORP www gfec com tw gt 9 8 X FARPERAD GALAXY FAR EAST Characteristics Overview of Stratix II F1020 Development Board 50 Faster Performance 2 25X Logic Capacity Increase 40 Lower Price per Density 4X DSP Bandwidth Increase 1 Gbps LVDS New Faster External Memory Interfaces gt Non Volatile Design Security 9 5 5 TriMatrix M Memory Digital Signal Processing Blocks External Memory Interfaces 840 Mbps Differential I O Pins Remote System Upgrades ARAID GALAXY FAR EAST CORP 1 Introduction of the product The development board is designed for IC development and verification therefore it is compatible with Altera Stratix II Device Family FPGA of EP2S180F1020 of the largest specification can provide embedded memory with a maximum capacity of 179 400 LEs 9 383 040 bits and maximum 753 available I Os for IC designers If the FPGA of maximum capacity still can t meet design gt requirement y
77. onditions Apply Unless Otherwise Specified Industrial 40 C to 85 C Vcc 5 0V 5 Parameter v C m fam f OF State Ouputcuren Hiz v vomevenswihesor onj af un Vcc Min Vin 2 4V lon 15mA 1 5 NOTES 1 Typical values are at Vcc 5 0V TA 25 C 2 Pass Voltage is guaranteed but not production tested TYPICAL ON RESISTANCE vs VIN AT Vcc 5V RON ohms 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 VIN Volts IDTQS32X861 HIGH SPEED CMOS 20 BIT BUS SWITCH WITH FLOW THROUGH PINOUT INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol Test Conditions QuiescentP ower Supply Current Vcc Max VIN or Vcc f 20 02 6 Power Supply Current per Control Vcc 2 34V f 0 25 ICCD Dynamic Power Supply Current per MHz Vcc and B pins open 0 25 mA MHz BEn Control Input Toggling at 50 Duty Cycle For conditions shown as Min Max use the appropriate values specified under DC Electrical Characteristics Typical values are at Vcc 5 0V 25 ambient TLL driven input Vin 3 4V control inputs only A and B pins do not contribute to Alcc This current applies to the control inputs only and represents the current required to switch internal c
78. onnect the development board and Byteblaster II USB Blaster or Byteblaster MV Download Cable before you turn the power on B You should avoid contacting metal wires and main body of IC package as possible as you can when you take the development board B If itis necessary for you to contact the IC board with your hand you should wear antistatic gloves to avoid the board subjecting to destroy or damage B When the development board is not installed or used it should be placed on an antistatic mat or kept in an antistatic pocket B Please confirm that all points are set correctly before turning the power on B Check supply voltage and wirings for several times before turning the power on B The board must not be thrown down or collided Any conducting material should not contact with any wiring or parts on the PCB board If you find the development board is damaged obviously you must not power up the board to test otherwise it will result in danger and IC destroy or damage B If you need to stack the development board to expand its capacity please confirm whether there is any conflict happened in I O settings 12 GALAXY FAR EAST so as to avoid damage the follow through switch B Operators should wear static prevent devices B On the related limitations and characteristics of Altera device used in this product please refer to Altera Data Manual B All adjustable points of this product are
79. otal DLLs 0 12 0 0 2 0 Open Programmer window Pun v X EISBOSIRAU GALAXY FAR EAST CORP 2 Setup hardware to be burned rtr endi E Hardware ByteBlaster LPT 1 Mode JTAG Progress e lt AN e Joe a alli Stoo C eda altera qdesigns EP2S60F1020C5ES 00292083 FFFFFFFF gli Auto Detect Delete Add File Change File 9 5 3 Choose the hardware used currently Bytebalster II Byteblaster MV or USB Blaster Hardware Setup Hardware Settings JTAG Settings Select programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware ByteBlaster LPT 1 lable hardware items b tela Add Hardware Remove Hardware 4 Choose JTAG mode GALAXY FAR EAST filtref cdf Hardware Setup ByteBlaster LPT1 Program n al ali Stop C eda altera qdesigns EP2S60F1020C5ES 00292083 FFFFFFFF Active Serial Programming renne Delete B r Change File ii Save Fite ae Bown gt B x 5 Add files in Add File d Hardware Setup ByteBlaster Mode T Progress Ok
80. ou can extend the available capacity by means of stacking FPGA performance reaches new heights with the Stratix II device family the 9 5 X industry s fastest and highest density FPGAs Built on a new and innovative logic structure Stratix II devices on average deliver 50 percent higher performance and offer more than twice the logic capacity of first generation Stratix FPGAs Stratix II devices extend the possibilities of FPGA design allowing designers to meet the high performance requirements of today s advanced systems and avoid developing with costly ASICs Based on the award winning Stratix device family architecture Stratix II devices are outfitted with a powerful set of system level features and incorporate many significant enhancements and new capabilities Stratix II FPGAs are manufactured on 300 mm wafers using TSMC s 90 nm low k dielectric process technology Stratix II devices mark the debut of an innovative and efficient logic structure that maximizes performance while consuming fewer resources and provides full backward compatibility with previous generation architectures This logic structure increases device densities to never before seen levels reaching up to 180K equivalent logic elements LEs and 9 Mbits of RAM all at a significantly lower cost than prior generation FPGAs Stratix II devices were designed in concert with the Quartus II software to deliver unmatched performance and ease of use The Quartu
81. p IO DIFFIO TX64n IO DIFFIO TX75p IO DIFFIO TX75n IO DIFFIO TX81p IO DIFFIO TX81n IO DIFFIO TX73p IO DIFFIO TX73n DIFFIO RX77p 90 IO DIFFIO RX77n 90 106 6 106 106 6 106 DE 106 106 6 106 106 106 106 106 106 106 106 106 106 6 106 V6 106 V7 106 05 106 U5 us 10606 667 106 06 06706 106 AD8 106 AD9 106 AC8 106 9 106 AB7 106 AB8 106 AA8 106 AA9 106 Y8 106 Y9 106 W8 106 W9 106 V9 0 6 V10 0 106 010 106 011 AA10 AA11 AB9 AB10 106 Y10 106 Y11 106 W10 106 W11 AF5 AF6 AE5 AD7 6 5 6 6 Y6 X7 W6 W7 gt gt gt gt gt gt gt gt gt gt gt 00 gt UJ UJ gt gt po gt gt gt gt gt gt 5 gt gt Oo gt lL gt gt gt gt gt itle lt Title gt Size Document Number Rev B lt Doc gt A Date Wednesday April 13 2005 Sheet 10 of 17 B8 AJ17 B8 AK17 B8 AL17 B8 AM17 8_ 18 B8 AJ18 B8 AK18 B8 AL18 B8 AL19 B8 AM19 R135 B7E VOC V43 B7 AH15 7 15 7 AJ15 7 AJ15 7 15 7 15 7 115 7 AL15 7 AG16 107 AG16 7 AH16 107 16 7 AJ16 Q 107 AJ16 7 AK16 9 7 AK16 7 AL16 0 107 116 7 AM16 107 16 Ma 0 17 2
82. s II software 1s the industry s most advanced development software for high density FPGAs and provides a comprehensive suite of synthesis optimization and verification tools in a single unified design environment Stratix II FPGAs are ideal for prototyping ASICs Providing the highest density and the highest performance Stratix II can emulate and validate an ASIC design with the high performance and density expected to model an ASIC accurately With support for migration to HardCopy II structured ASICs Stratix II FPGAs offer the industry s only seamless development path from FPGA prototype to high volume structured ASIC production Designing with HardCopy II devices allows users to reduce development costs and still get the flexibility and time to market advantages associated with FPGAs 8 gt GALAXY FAR EAST CORP Top level function Stratix II devices improve on the features that set new standards in FPGAs shown in Figure 1 New device capabilities such as the new logic structure and design security technology round out the industry s most advanced FPGA feature set 21 Channels With 4 External Memory u er Logic Interface Circuitry ules L High Speed M512 Black Channels With DPA Ph le 5 Digital Signal 9 E Processing Block 8 E DSP Block X r a a
83. upplied by the user if no proper 17 power source can supply to the adapter or the required power consumption 15 higher than the attached adapter in the using location The board contains power process circuit There are three ways to input power each of them are described in the following B We offer special adapter for our customers It can transform ACIIOV 240V into DC6V can be connected J13 directly providing necessary power to the board But it just can be used in the systems lower than 3A If there 1s any special requirement by the system the power for the outside should be supplied additionally B Connect the DC power adapter with the double cables attached after 2 8 E X check positive and negative poles The input voltage is DC6V B The board be used with other board together In this case the power is supplied from the other board but it must be lower than DC 6V i IE an Power Cable r Cable 2 5 Available I O of Development Board The development board sends all I Os available to FPGA from follow through switch to connector to ensure all I Os of FPGA not to be destroyed by extra high external voltage or current Detailed information of follow through switch sees the appendix When the board is used to validate circuit we recommend to use the user I O of EP2S60F 1020 mainly so as to avoid changing different size FPGA in F1020 at will

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