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MSP430 Peripheral Driver Library User's Guide

1. 1f ref generator busy WAIT while REFA isRefGenBusy MSP430 BASEADDRESS REF A Select internal ref 2 5V REFA setReferenceVoltage MSP430 BASEADDRESS REF A REFA VREFA2 5V Internal Reference ON REFA enableReferenceVoltage MSP430 BASEADDRESS REF A Delay 75us for Ref to settle delay cycles 75 Initialize the ADC12 Module Base address of ADC12 Module Use internal ADC12 bit as sample hold signal to start conversion USE MODOSC 5MHZ Digital Oscillator as clock source Use default clock divider pre divider of 1 Map to internal channel 0 ADC12B_init __MSP430_BASEADDRESS_ADC12_B_ ADC12B SAMPLEHOLDSOURCE SC DC12B CLOCKSOURCE ADC120SC DC12B CLOCKDIVIDER 1 DC12B CLOCKPREDIVIDER 1 DC12B MAPINTCHO pope Enable the ADC12B module ADC12B enable MSP430 BASEADDRESS ADC12 B Base address of ADC12B Module For memory buffers 0 7 sample hold for 64 clock cycles 2012 08 2814 58 17_0500 TI Information Selective Disclosure Internal Reference REFA For memory buffers 8 15 sample hold for 4 clock cycles default Disable Multiple Sampling ADC12B setupSamplingTimer MSP430 BASEADDRESS ADC12 B ADC12B CYCLEHOLD 64 CYCLES ADC12B CYCLEHOLD 4 CYCLES ADC12B MULTIPLESAMPLESDISABLE Configure Memory Buffer Base address of the ADC12B Module Configure memory buffer 0 Map input AO to memory buffer 0 Vref Vref INT Vref AVss ADC12B_memoryConfigure
2. unsigned int crcSeed OxBEEF unsigned int data 0x0123 0x4567 0x8910 0x1112 0x1314 unsigned int crcResult int i Stop WDT WDT hold MSP430 BASEADDRESS WDT A 2012 08 2814 58 17 0500 43 TI Information Selective Disclosure Cyclical Redundancy Check CRC Set P1 0 as an output GPIO setAsOutputPin MSP430 BASEADDRESS PORT1 R GPIO PORT P GPIO PINO Set the CRC seed CRC_set Seed __MSP430_BASEADDRESS_CRC__ crcSeed for i 0 i lt 5 i Add all of the values into the CRC signature CRC_setData __MSP430_BASEADDRESS_CRC__ data il Save the current CRC signature checksum to be compared for later crcResult CRC getResult MSP430 BASEADDRESS CRC 44 2012 08 2814 58 17 0500 TI Information Selective Disclosure 14 14 1 14 2 12 bit Digital to Analog Converter DAC 12 12 bit Digital to Analog Converter DAC12 Lil eMe HON PP Zo Poo ho b dod oo ao eko n oo d dk kk k Lo E od n o d 43 POTE PO ROT o od n a l A CAI da ELE 43 Prez DE sr ee 44 Introduction The 12 Bit Digital to Analog DAC12 API provides a set of functions for using the MSP430Ware DAC12 modules Functions are rpvided to initialize setup the DAC12 modules calibrate the output signal and manage the interrupts for the DAC12 modules The DAC12 module provides the ability to convert digital values into an analog signal for output to a pin The DAC12 can generate signals from 0 to
3. 6 2 22 m Single channel repeat single channel sequence autoscan and repeat sequence repeated autoscan conversion modes m Interrupt vector register for fast decoding of 38 ADC interrupts m 32 conversion result storage registers m Window comparator for low power monitoring of input signals of conversion result registers This driver is contained in driverlib 5xx 6xx ADC12B c with driverlib 5xx 6xx ADC12B h containing the API definitions for use by applications API Functions The ADC12B API is broken into three groups of functions those that deal with initialization and conversions those that handle interrupts and those that handle auxillary features of the ADC12B The ADC12B initialization and conversion functions are m ADC12B init m ADC12B memoryConfigure m ADC12B setWindowCompAdvanced m ADC12B setupSamplingTimer m ADC12B disableSamplingTimer m ADC12B startConversion m ADC12B disableConversions m ADC12B getResults m ADC12B isBusy The ADC12B interrupts are handled by m ADC12B enablelnterrupt m ADC12B disablelnterrupt m ADC12B clearlnterrupt m ADC12B getlnterruptStatus Auxilary features of the ADC12B are handled by m ADC12B setResolution m ADC12B setSampleHolaSignallnversion m ADC12B setDataReadBackFormat m ADC12B enableReferenceBurst m ADC12B disableReferenceBurst m ADC12B setAdcPowerMode m ADC12B getMemoryAddressForDMA m ADC12B enable m ADC12B disable 2012 08 2814 58 17_0500 TI I
4. 17 0500 45 TI Information Selective Disclosure 12 bit Digital to Analog Converter DAC 12 Calibration features of the DAC12 are handled by m DAC12 calibrateOutput m DAC12 getCalibrationData m DAC12 setCalibrationOffset The DAC12 interrupts are handled by m DAC12 enablelnterrupt DAC12 disablelnterrupt DAC12 getlnterruptStatus DAC12 clearlnterrupt 14 3 Programming Example The following example shows how to initialize and use the DAC12 API to output a 1 5V analog signal DAC12 init MSP430 BASEADDRESS DAC12 2 DAC12 SUBMODULE O0 Initialize DAC12 0 DAC12 OUTPUT 1 Choose P6 6 as output DAC12 VREF AVCC Use AVcc as Vref DAC12 VREFxl Multiply Vout by 1 DAC12 AMP MEDIN MEDOUT se medium settling speed current DAC12 TRIGGER ENCBYPASS Auto trigger as soon as data is set 3 Calibrate output buffer for DAC12 0 DAC12 calibrateOutput MSP430 BASEADDRESS DAC12 2 DAC12_SUBMODULE_0 DAC12_setData __MSP430_BASEADDRESS_DAC12_2__ DAC12 SUBMODULE 0 Set Ox7FF 1 5V Ox7FF into data buffer for DAC12 0 46 2012 08 2814 58 17 0500 TI Information Selective Disclosure Direct Memory Access DMA 15 Direct Memory Access DMA O 45 AP OS an 45 Presran nmyg Bande see 46 15 1 Introduction The Direct Memory Access DMA API provides a set of functions for using the MSP430Ware DMA modules Functions are provided to initialize and setup each DMA channel with the source a
5. 46 1 46 2 46 3 WatchDog Timer WDT WatchDog Timer WDT OU aerea ar oa abd d n la OR bib diede dede din a dk a oki Bek ac deus dod Mewes 145 MARCADOS A a o dh c V E Renee 145 Peca MCH Bande ann 145 Introduction The Watchdog Timer WDT API provides a set of functions for using the MSP430Ware WDT mod ules Functions are provided to initialize the Watchdog in either timer interval mode or watchdog mode with selectable clock sources and dividers to define the timer interval The WDT module can generate only 1 kind of interrupt in timer interval mode If in watchdog mode then the WDT module will assert a reset once the timer has finished This driver is contained in driverlib 5xx 6xx wdt c with driverlib 5xx 6xx wdt h containing the API definitions for use by applications API Functions The WDT API is one group that controls the WDT module m WDT_hold m WDT start m WDT_clearCounter m WDT watchdogTimerlnit m WDT intervalTimerlnit Programming Example The following example shows how to initialize and use the WDT API to interrupt about every 32 ms toggling the LED in the ISR Initialize WDT module in timer interval mode with SMCLK as source at an interval of 32 ms WDT intervalTimerInit MSP430 BASEADDRESS WDT A WDT CLOCKSOURCE SMCIK WDT CLOCKDIVIDER 32K Enable Watchdog Interupt SFR enableInterrupt MSP430 BASEADDRESS SFR WDTIE Set P1 0 to output direction GPIO setAsOutputPin MSP
6. GPIO PORT P2 GPIO PIN7 i High Level trigger ext clear enable TEC configureExternalClearInput __MSP430_BASEADDRESS_TEV1__ TEC EXTERNAL CLEAR SIGNALTYPE LEVEL SE TEC EXTERNAL CLEAR SIGNAL NOT HELD TEC EXTERNAL CLEAR POLARITY RISING EDGI y TEC_enableExternalClearInput __MSP430_BASEADDRESS_TEV1__ 120 2012 08 2814 58 17 0500 TI Information Selective Disclosure 39 39 1 Timer Timer INCAUTOS 119 MARCADOS A e e 120 Peca Bande aan 120 Introduction Timer is a 16 bit timer counter with multiple capture compare registers Timer can support multiple capture compares PWM outputs and interval timing Timer also has extensive interrupt capabil ities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers This peripheral API handles Timer A and Timer B handware peripheral Timer features include m Asynchronous 16 bit timer counter with four operating modes m Selectable and configurable clock source m Up to seven configurable capture compare registers m Configurable outputs with pulse width modulation PWM capability m Asynchronous input and output latching m Interrupt vector register for fast decoding of all Timer interrupts Timer can operate in 3 modes m Continuous Mode m Up Mode Down Mode Timer Interrupts may be generated on counter overflow conditions and during capture compare evenis The timer may also be used to generate P
7. TI Information Selective Disclosure EUSCI UART m eUART setDormant m eUART resetDormant m eUART selectDeglitchTime Sending and receiving data via the UART is handled by the m eUART transmitData m eUART receiveData m eUART transmitAddress m eUART transmitBreak Managing the UART interrupts and status are handled by the eUART enablelnterrupt eUART disablelnterrupt eUART getlnterruptStatus eUART clearlnterruptFlag m eUART queryStatusFlags DMA related m eUART getReceiveBufferAddressForDMA m eUART getTransmitBufferAddressForDMA 18 3 Programming Example The following example shows how to use the UART API to initialize the UART transmit characters and receive characters Configure UART if STATUS FAIL eUART init MSP430 BASEADDRESS EUSCI AO eU ART 32768 _CLOCKSOURCE_ACLK eUCS_getACLK __MSP430_BASEADDRESS_UCS__ 96 return eUART_enable 00 ART ART ART ART ART _NO_PARITY _LSB_FIRST ONE STOP BIT MODE LOW FREQUENCY BAUDRATE GENERATION MSP430 BASEADDRESS EUSCI A0 Enable USCI A0 RX interrupt eUART enableInterrupt MSP430 BASEADDRESS EUSCI A0 eUART RECEIVE INTERRUPT Enable interrupt enable interrupt while 1 TXData TXDatatl Increment TX data 58 2012 08 2814 58 17_0500 TI Information Selective Disclosure EUSCI UART Load data onto buffer eUART transm
8. The MSP430x5xx MSP430x6xx Family UserSs Guide SLAU208 1 recommends the settings shown in Table 1 when setting these bits The PMM_setVCore function follows these recommendations and ensures that the SVS levels match the core voltage levels that are used Advanced SVS Controls and Trade offs In addition to the default SVS settings that are provided with the PMM_setVCore function the SVS SVM modules can be optimized for wake up speed response time propagation delay and current consumption as needed The following controls can be optimized for the SVS SVM modules m Protection in low power modes LPM2 LPM3 and LPM4 m Wake up time from LPM2 LPM3 and LPM4 m Response time to react to an SVS event Selecting the LPM option wake up time and re sponse time that is best suited for the application is left to the user A few typical examples illustrate the trade offs Case A The most robust protection that stays on in LPMs and has the fastest response and wake up time consumes the most power Case B With SVS high side active only in AM no protection in LPMs slow wake up and slow response time has SVS pro tection with the least current consumption Case C An optimized case is described turn off the low side monitor and supervisor thereby saving power while keeping response time fast on the high side to help with timing critical applications The user can call the PMM_setVCore function which configures SVS SVM high side and low sid
9. __MSP430_BASEADDRESS_ADC12_B_ ADC12B MEMORY 0 ADC12B INPUT A0 ADC12B VREFAPOS INTBUF VREFANEG VSS ADC12B NOTENDOFSEOUENCE while 1 Enable Start sampling and conversion Base address of ADC12B Module Start the conversion into memory buffer 0 Use the single channel single conversion mode ADC12B_startConversion __MSP430_BASEADDRESS_ADC12_B__ ADC12B_MEMORY_0 ADC12B SINGLECHANNEL Poll for interrupt on memory buffer 0 while ADC12B getInterruptStatus MSP430 BASEADDRESS ADC12 B 0 ADC12IFG0 SET BREAKPOINT HERE no operation 2012 08 2814 58 17 0500 103 TI Information Selective Disclosure Internal Reference REFA 104 2012 08 2814 58 17_0500 TI Information Selective Disclosure 33 33 1 33 2 Real Time Clock RTC Real Time Clock RTC OU aerea oka toko eh dad o Ka OR bien diede dede dca a dok beo Bek a da rdi do Kao 103 AMIA A n o dh o eee E Re A 103 Peca MCH Bande anne 104 Introduction The Real Time Clock RTC API provides a set of functions for using the MSP430Ware RTC mod ules Functions are provided to calibrate the clock initialize the RTC modules in Calendar mode and setup conditions for and enable interrupts for the RTC modules If an RTC A module is used then Counter mode may also be intialized as well as prescale counters The RTC module provides the ability to keep track of the current time and date in calendar mode or can be setup as a 32 bit c
10. A E a a a 10 4 10 Bit Analog to Digital Converter ADC10B lt lt s ee eee nn 11 SEMI Go BRENT 11 ce FAP PUSS A ee Ga ae a Pe Ee de 11 43 Programming Example lt lt paed cd ok ooo RR ee AN 12 5 12 Bit Analog to Digital Converter ADC12 2200 rrr 15 el NOTAE uuu nee do on 9 S 9 RUE XA Uk A V AVG kee EG RO bee AA UR RR IG x e ub ee Ru Be 15 Wu AP PUES 22 oua mot m EL OR OE kon Esc ok Aw TRU RUE RS X eub RAE ec UR C o ew TR od x S ek a 15 53 Programming Example lt lt lt lt x lt 22 4 V 8 Sn oko Rh ok Aa PR ee Ee ERR RO ER ER RR A 16 6 12 Bit Analog to Digital Converter ADC12B 4 s ee eee hh 19 Gel a 13 32 4 0 0 bea doe ae Be ae o ae ee Wane wk Be Sees ates eked Ech dr Ark 19 ie P PLS lt gt 2 dee E rmm 20 63 Programming Example s z ccc 0 RRR RR ee R E KOR RE Ra RO RR 21 7 Advanced Encryption Standard AES oo 23 X IGOdHOllbl so Sa oem a EU E EUR QU Run A ee E GRO A AR oo k V RE s U d Jde o Ae E 23 fum FEU PUP ca bos oe E 49 era ee e OW ae CE Rc ba A ee a ee R 23 T Programming Example lt s u 20 se a anna na A a A 24 8 Comparator COMPB 2 ce ee aaa a ee A c9 a Be es a 25 B e s d 2 4 4 oce a Ee ee PECK AE ae eun oe ea Wok dee ck yb e tore 25 de ABI PUTS TM re ea Ee Eg BG we a Pe se we a BR eh dr he ce ded 25 63 Programming Example lt 56026 8 5 kom ok o R RKO A A Pe a ew ari 26 9 Gomparator COMPD uon nudo u ee
11. AR ee Re a 78 LDO PWR lt eck o eR a Re klub ee RR mU EA UR ee a e 79 d URAN RR CC c r 79 aii di ou RE RT an Aa ccn DELETE 79 Programming Example 3 1533 0000 oro nn RHE mon VO ROK a yx EURO ee eR E d 80 Memory Protection Unit MPU cosa oce lt lt ee eee ren 83 decr PDC 83 Fm o aoe a a man Aa a ia a ai a a Ea a a E a AR aa a E ea aa A A a a a a a aoa LA eA ao 83 Programming Example lt a lt sz s oro saaa mm nn OE Re en 84 32 Bit Hardware Multiplier MPY32 lt 2200000 85 BERS ARM deck on ake a Gen tee at bp TR e OS a e a ae ake ica De oie aei Sue GIA Me TER a ak Boke Mee A ye eee 85 Parr sos rsa veh an ee ects C a Glee B ae KG oe O ay Bris O O BYR uA Me dae OVL a Be ae he ee 85 Programming Example s 044 bo RH PR V R RE ROG a R VE RE RRA 86 Power Management Module PMM lt s ee ne 87 MAES EU RNOMY MMC 87 Podio ERNEUT TTTTS 88 Programming Example s 00 5 eames RA YG EO RH EE k EO e RR NR EROR Y XS X EV Oe k 9 E e RR OA A 90 Port Mapping Controller 2 zn erro RR KOK K oh Rm m f CK KOK O m m RR RR Rm n 91 MEROE SNO M ccc RR A NN 91 Hai uos gOS n nos heen Goad Sette Rua DTP 91 Programming Example zs esc or p Rn or RE Ee a OK cm A a a Se E A 91 RAM Gonttoller gt cpc ch o ERE RR no Rok RO mum RU E Rom Rem R room Ro m E m RE ORECRORORUEOS RO EOR ROR Eos cm m 93 dero CT 93 P xz RECTE A ae haare ira Ps A A A AA a lee 93 Programming
12. EE E dida 95 lai n Bande ss eh dd AA S z t 96 Introduction The Internal Reference REF API provides a set of functions for using the MSP430Ware REF modules Functions are provided to setup and enable use of the Reference voltage enable or disable the internal temperature sensor and view the status of the inner workings of the REF module The reference module REF is responsible for generation of all critical reference voltages that can be used by various analog peripherals in a given device These include but are not necessarily limited to the ADC10 A ADC12 A DAC12 A LCD B and COMP B modules dependent upon the particular device The heart of the reference system is the bandgap from which all other refer ences are derived by unity or non inverting gain stages The REFGEN sub system consists of the bandgap the bandgap bias and the non inverting buffer stage which generates the three primary voltage reference available in the system namely 1 5 V 2 0 V and 2 5 V In addition when enabled a buffered bandgap voltage is also available This driver is contained in driverlib 5xx 6xx ref c with driverlib 5xx 6xx ref h containing the API definitions for use by applications API Functions The DMA API is broken into three groups of functions those that deal with the reference voltage those that handle the internal temperature sensor and those that return the status of the REF module The reference voltage of the REF module is han
13. LDOPWR_unLockConfiguration __MSP430_BASEADDRESS_PU__ Configure PU 0 as output pins LDOPWR_enablePort_U_outputs __MSP430_BASEADDRESS_PU__ Set PU 1 high LDOPWR setPort U1 outputData MSP430 BASEADDRESS PU LDOPWR PORTU PIN HIGH Set PU 0 low LDOPWR setPort UO outputData MSP430 BASEADDRESS PU LDOPWR PORTU PIN LOW 3 Enable LDO overload indication interrupt LDOPWR enableInterrupt MSP430 BASEADDRESS PU LDOPWR LDO OVERLOAD INDICATION INTERRUPT Disbale access to config registers LDOPWR lockConfiguration MSP430 BASEADDRESS PU continuous loop while 1 Delay for i 50000 i gt 0 i Enable access to config registers LDOPWR unLockConfiguration MSP430 BASEADDRESS PU XOR PU 0 1 2012 08 2814 58 17 0500 TI Information Selective Disclosure LDO PWR LDOPWR_togglePort_Ul_outputData __MSP430_BASEADDRESS_PU__ LDOPWR togglePort UO outputData MSP430 BASEADDRESS PU Disbale access to config registers LDOPWR lockConfiguration MSP430 BASEADDRESS PU J f kk k k k kk k e HH A kk kk kk X AK kk X AK ke kk ok kk AX ko KA X A ko kk oko ko ko ko koe kk I kk ko ke kk k ke ke k This is the LDO PWR VECTOR interrupt vector service routine J Kk k k k k k k k k k k k k k k Ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k kk k kk k ck k k k kkk ckckckck ck ck ckck ck ck ck ck kkk k k interrupt void LDOInterruptHandler void i
14. ee ES ee ee REOR Ge klonil s 110 36 SFR SYS Modules 02 u a a x Rom mumgm Ee mus m X CR RR AA m n 111 IHN Ic EDT 111 30 2 ARI PURGHONS 5 e iue deen oe pa Rp eR m WO o9 Od mcm uw Yea bow mos wv Ra AR Rap eg GER Go moe Wed RE EUR TETTE 111 36 9 Programming Example z c s wa Hw eo khe om o ak Rok A Y 9 YOOX Rx Y 3k we ET A 112 37 Synchronous Peripheral Interface SP eee ee hrs 113 cr IR AN A Een aie EN aae EU aeae EA 113 37 2 AP FUNGIDNS sci doa eon i he a Doe Bee R RS Pow ee aS a a ee 113 37 3 Programming EXample uos os kom ee a RE eae aad O GS RUE ea eae OR Bare y Ge wy as 114 A ee ee ee ee 117 BIN OUI mE em Re asa A aaa Sm Reel nde dy Steed a ty Be Mee O ande 117 382 ellc MM IT 117 38 3 Programming Example saca eaae taa mor a a x p 3 TED nr EORR Es 118 DJ ODD RESI Exi Mas RUE RE ee oux mm ON ARUM eek boa EE E cese qo eine Redes e Ue mcer Saw igh aes Pe 119 lA O NN ee GPE ROVE Tas Se dues gt SA Ge alae UE Saka IC 119 39 2 A EUNRENGNS suu a a dB a pce oe RO LS ee ae a ae doe a ERU b PR BEL Ee 120 39 3 Programming Example lt e ios ses s cogo a GR YR nn a nr 120 c ep ee ee Be Bee ec ee 123 BPE MUNI A donde Soe ke nee tars ode vdov She ke ara beat nes ck E pu Rug Neg datu ch dy Be dete ne eta ars Shea 123 40 2 AR FUNCIONS ouo a ae m xong c p en doa 9b RE mex VR Yer E aed ee GO gor oe d ee ns 124 40 3 Programming Example ses oro 222 9 EO og hk RE E C 3S RO Y 3 Ox Y 08 een 124 AT
15. eot o ed no do a l o UAE a dos 61 Programming DNE see 62 Introduction FRAM memory is a non volatile memory that reads and writes like standard SRAM The MSP430 FRAM memory features include m Byte or word write access m Automatic and programmable wait state control with independent wait state settings for access and cycle times m Error Correction Code with bit error correction extended bit error detection and flag indicators m Cache for fast read m Power control for disabling FRAM on non usage This driver is contained in driverlib 5xx 6xx fram c With driverlib 5xx 6xx fram h containing the API definitions for use by applications API Functions FRAM enablelnterrupt enables selected FRAM interrupt sources FRAM getlnterruptStatus returns the status of the selected FRAM interrupt flags FRAM disablelnterrupt disables selected FRAM interrupt sources Depending on the kind of writes being performed to the FRAM this library provides APIs for FRAM writes FRAM write8 facilitates writing into the FRAM memory in byte format FRAM write16 facilitates writing into the FRAM memory in word format FRAM write32 facilitates writing into the FRAM memory in long format pass by reference FRAM memoryFill32 facilitates writing into the FRAM memory in long format pass by value FRAM status checks if the FRAM is currently busy pro gramming The FRAM API is broken into 3 groups of functions those that write into FRAM those that handle interrupt
16. how to initialize and use the SD24B API to start a single channel single conversion unsigned long results SD24B init MSP430 BASEADDRESS SD24 B SD24B CLOCKSOURCE SMCLK SD24B PRECLOCKDIVIDER 1 SD24B CLOCKDIVIDER 1 SD24B REF INTERNAL Select internal REF Select SMCLK as SD24 B clock source SD24B configureConverter MSP430 BASEADDRESS SD24 B SD24B CONVERTER 2 SD24B ALIGN RIGHT SD24B CONVERSION SELECT SD24SC SD24B SINGLE MODE delay cycles 0x3600 Delay for 1 5V REF startup while 1 SD24B startConverterConversion MSP430 BASEADDRESS SD24 B SD24B CONVERTER 2 Set Poll interrupt flag for channel 2 while SD24B getInterruptStatus MSP430 BASEADDRESS SD24 B SD24B CONVERTER 2 SD24 CONVERTER INTERRUPT 0 results SD24B getResults MSP430 BASEADDRESS SD24 B SD24B CONVERTER 2 Save CH2 results clears IFG no operation SET BREAKPOINT HERE 112 2012 08 2814 58 17 0500 TI Information Selective Disclosure 36 36 1 36 2 SFR SYS Modules SFR SYS Modules A e o abdo cadi o Rua OR bonded dede dca a dak oki bek asd da redo Mewes 111 IRA A nr dh ical E dicus UE dE I ped eater MU ob S irae 111 Peca MCH Bande i bos prp d T PFIIE v P ER D He DU RC DH MEER RON EET EP RH MEME 112 Introduction The Special Function Registers amp System Control SFR_SYS API provides a set of functions for using the MSP430Ware SFR and SYS modules Functions are provided to en
17. m el2C setMode m el2C enable m el2C enablelnterrupt if interrupts are being used This may be followed by the APIs for transmit or receive as required The user must first call the el2C slavelnit to initialize the slave module in I2C mode and set the slave address This is followed by a call to set the mode of operation transmit or receive The 12 module may now be enabled using el2C enable It is recommneded to enable the I2C module before enabling the interrupts Any transmission or reception of data may be initiated at this point after interrupts are enabled if any The transaction can then be initiated on the bus by calling the transmit or receive related APIs as listed below Slave Transmission API m el2C slaveDataPut Slave Reception API m el2C slaveDataGet 2012 08 2814 58 17 0500 TI Information Selective Disclosure EUSCI Inter Integrated Circuit I2C For the interrupt driven transaction the user must register an interrupt handler for the I2C devices and enable the I2C interrupt This driver is contained in driverlib 5xx 6xx ei2c c With driverlib 5xx 6xx ei2c h containing the API definitions for use by applications 16 2 API Functions The eUSCI I2C API is broken into three groups of functions those that deal with interrupts those that handle status and initialization and those that deal with sending and receiving data The I2C master and slave interrupts are handled by m el2C enablelnterrupt m el
18. or disables the POR signal gen eration when a low voltage event is registered by the high side SVS PMM_enableSVMHinterrupt PMM_disableSVMHinterrupt Enables or disables the interrupt generation when a low voltage event is registered by the high side SVM PMM clearPMMIFGS Clear all interrupt flags for the PMM PMM_SvsLEnabledinLPMFastWake Enables supervisor low side in LPM with twake up fast from LPM2 LPM3 and LPM4 PMM SvsLEnabledinLPMSlowWake Enables supervisor low side in LPM with twake up slow from LPM2 LPM3 and LPM4 PMM_SvsLDisabledInLPMFastWake Disables supervisor low side in LPM with twake up fast from LPM2 LPM3 and LPM4 PMM_SvsLDisabledInLPMSlowWake Disables supervisor low side in LPM with twake up slow from LPM2 LPM3 and LPM4 PMM SvsHEnabledinLPMNormPerf Enables supervisor high side in LPM with tpd 20 us 1 PMM SvsHEnabledInLPMFullPerf Enables supervisor high side in LPM with tpd 2 5 us 1 PMM_SvsHDisabledInLPMNormPerf Disables supervisor high side in LPM with tpd 20 us 1 PMM SvsHDisabledInLPMFullPerf Disables supervisor high side in LPM with tpd 2 5 us 1 PMM SvsLOptimizedInLPMFastWake Optimized to provide twake up fast from LPM2 LPM3 and LPM4 with least power PMM_SvsHOptimizedinLPMFullPerf Optimized to provide tpd 2 5 us 1 in LPM with least power PMM getlnterruptStatus Returns interrupt status of the PMM module PMM_setVCore Sets the appropriate VCORE level Calls the PMM_
19. pragma vector USCI A0 VECTOR interrupt void USCI A0 ISR void switch __even_in_range UCAOIV 4 Vector 2 RXIFG case 2 USCI_AO TX buffer ready while SPI_interruptStatus USCI_AO_BASE UCTXIFG receiveData SPI receiveData USCI A0 BASE Increment data transmitData Send next value SPI_transmitData USCI_AO_BASE transmitData Delay between transmissions for slave to process information __delay_cycles 40 break default break 2012 08 2814 58 17 0500 117 TI Information Selective Disclosure Synchronous Peripheral Interface SPI 118 2012 08 2814 58 17_0500 TI Information Selective Disclosure 38 38 1 38 2 TEC TEC MPO CHU SEDIT ear rs a beue bd UR ORE IDE bn e dd oa oko oki bk DE atre Mende 117 APIF ROIS A DRM Sega UM dU cba aale duae 117 Prez Exame anne 118 Introduction Timer Event Control TEC module is the interface between Timer modules and the external events This chapter describes the TEC Module TEC is a module that connects different Timer modules to each other and routes the external signals to the Timer modules TEC contains the control registers to configure the routing between the Timer modules and it also has the enable register bits and the interrupt enable and interrupt flags for external event inputs TEC features include m Enabling of internal and external clear signals m Routing of internal signals between Timer_D instances and
20. ssa seek ea oak aide aa ee Rode em Baad Boyt wheal Dae woh a A eee ey eae kk de 56 Flash Memory Gontroller s e ca ous n mh ERR RU a ee ee KK RU m um 59 l geo lt x ke tindaga AAA RE RA TT 59 uas o0 MEMENTO c TP 59 Programming Example sos or pom hor m Rr mon PE 3 OG ER Ks a a GO UR EO KR RON E POR S a i 60 FRAM ContlolleF lt s 4 ook JE ae sss Fa oa RO Ro dn 6x EROR Kom E moy E Bo ec Ko e N JR OR i Dr o Dt I COR om o e 61 INWOOUGHON fe ka ee A Le ER A AAA B ee a 61 PA Mz io LENS ITSSTDETCOCO OR Da ieda E We Buse car ab ats stodol z l Hs a waar Meas via aha sh ae ke die Be ads Be 61 Programming Example lt 45 e o or Pee RR EG ERE aa ETRE ROS O3 BOR AA 62 FRGPIO uoo Ro RR A AR Eo kn ee ee ee BG a e 63 In roduelio ocioso RE A RR A Po a S E CR UR A 63 ZUM O qct 64 Programming Example 64 20 0 kn RR REE ORR OE AAA 64 Power Management Module FRPMM 2 lt ee rn 67 INWOQUGHON s vun ee ek ee Ro Dk ee RE m OR eae OR ee a ae A 67 BA xmi A E d r Bec hy AS ie Mik kaw Gs ok oh atk BR Meats be fe Red Sh ne BO Be a ee 67 Programming Example s 0 sooo 4 a nn er ic A ra ne O 68 GPIO lulu Rx A ae 71 lllo D 71 Psi OEE ar A NAO TEX 72 Programming Example uuo sce som o m n pom m o8 8 8 9 da RE ECC ne 72 Inter Integrated Circuit 120 leere Rr htt 75 MAAE OG A NS NN 75 FIR FROHES A E A A hyd Aw lk Weis Be Blom ios Sy See 77 Programming Example lt es s 32048 ono nmm mm EER e YR
21. the associated CDPD x bit COMPD disableInputBuffer MSP430 BASEADDRESS COMPD COMPD INPUT2 Allow power to Comparator module COMPD_enable __MSP430_BASEADDRESS_COMPD__ __delay_cycles 400 delay for the reference to settle 30 2012 08 2814 58 17_0500 TI Information Selective Disclosure 10 10 1 10 2 Comparator COMPE Comparator COMPE IPT ON ok e dod noo i dok dod deo d pU dokn rd deans een 29 SNe USP PO ROT coron dd n o a a l ad GARE o oa een LE d 29 Prez MEK DE ss nee 30 Introduction The Comparator E COMPE API provides a set of functions for using the MSP430Ware COMPE modules Functions are provided to initialize the COMPE modules setup reference voltages for input and manage interrupts for the COMPE modules The COMPE module provides the ability to compare two analog signals and use the output in software and on an output pin The output represents whether the signal on the positive terminal is higher than the signal on the negative terminal The COMPE may be used to generate a hysteresis There are 16 different inputs that can be used as well as the ability to short 2 input together The COMPE module also has control over the REF module to generate a reference voltage as an input The COMPE module can generate multiple interrupts An interrupt may be asserted for the output with seperate interrupts on whether the output rises or falls This driver is contained in driverlib 5xx_6xx comp_
22. the lower byte of the PA port using byte operations the upper byte remains unchanged Similarly writing to the upper byte of the PA port using byte instructions leaves the lower byte unchanged When writing to a port that contains less than the maximum number of bits possible the unused bits are a don t care Ports PB PC PD PE and PF behave similarly Reading of the PA port using word operations causes all 16 bits to be transferred to the destination Reading the lower or upper byte of the PA port P1 or P2 and storing to memory using byte operations causes only the lower or upper byte to be transferred to the destination respectively Reading of the PA port and storing to a general purpose register using byte operations causes the byte transferred to be written to the least significant byte of the register The upper significant byte of the destination register is cleared automatically Ports PB PC PD PE and PF behave similarly When reading from ports that contain less than the maximum bits possible unused bits are read as zeros similarly for port PJ 2012 08 2814 58 170500 65 TI Information Selective Disclosure FRGPIO 21 2 21 3 66 The FRGPIO pin may be configured as an I O pin with FRGPIO_setAsOutputPin FRGPIO setAsInputPin FRGPIO_setAsInputPinWithPullDownresistor or FRG PIO_setAsInputPinWithPullUpresistor The FRGPIO pin may instead be con figured to operate in the Peripheral Module assigned funct
23. to el2C masterlnit That function will set the clock and data rates This is followed by a call to set the slave address with which the master intends to communicate with using el2C_setSlaveAddress Then the mode of operation transmit or receieve is chosen using el2C setMode The I2C module may now be enabled using el2C enable It is recommneded to enable the el2C module before enabling the interrupts Any transmission or reception of data may be initiated at this point after interrupts are enabled if any The transaction can then be initiated on the bus by calling the transmit or receive related APIs as listed below Master Single Byte Trasnmission 2012 08 2814 58 17 0500 49 TI Information Selective Disclosure EUSCI Inter Integrated Circuit I2C 16 1 2 50 m el2C masterSendSingleByte Master Mulitple Byte Transmission m el2C masterMultiByteSendStart m el2C masterMultiByteSendNext m el2C masterMultiByteSendStop Master Single Byte Reception m el2C masterReceiveStart m el2C masterSingleReceive Master Multiple Byte Reception m el2C masterMultiByteReceiveStart m el2C masterMultiByteReceiveNext m el2C masterMultiByteReceiveFinish m el2C masterMultiByteReceiveStop For the interrupt driven transaction the user must register an interrupt handler for the I2C devices and enable the I2C interrupt Slave Operations To drive the slave module the APIs need to be invoked in the following order m el2C slavelnit
24. unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifi cally designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory reguire
25. with driverlib 5xx 6xx spi h containing the API definitions for use by applications API Functions To use the module as a master the user must call SPI masterlnit to configure the SPI Master This is followed by enabling the SPI module using SPI enable The interrupts are then enabled if needed It is recommended to enable the SPI module before enabling the interrupts A data trans mit is then initiated using SPI transmitData and tehn when the receive flag is set the received data is read using SPI_receiveData and this indicates that an RX TX operation is complete To use the module as a slave initialization is done using SPI slavelnit and this is followed by enabling the module using SPI enable Following this the interrupts may be enabled as needed When the receive flag is set data is first transmitted using SPI transmitData and this is followed by a data reception by SPI receiveData The SPI API is broken into 3 groups of functions those that deal with status and initialization those that handle data and those that manage interrupts The status and initialization of the SPI module are managed by m SPI masterlnit m SPI slavelnit m SPI disable m SPI enable m SPI masterChangeClock m SPI isBusy Data handling is done by m SPI transmitData 2012 08 2814 58 17 0500 115 TI Information Selective Disclosure Synchronous Peripheral Interface SPI 37 3 116 m SPI_receiveData Interrupts from th
26. 0 MSP430ware_x_xx_xx_xx or the corresponding path where MSP430ware is installed 2012 08 2814 58 17 0500 9 TI Information Selective Disclosure How to create a new project that uses Driverlib 10 2012 08 2814 58 17_0500 TI Information Selective Disclosure 3 3 1 3 2 10 Bit Analog to Digital Converter ADC 10 10 Bit Analog to Digital Converter ADC10 Gist Mele seer eee erst Tere ee eee Dada eaa ete eee ee NRC re Len P TP eet eT eee Tee Sey bad re rer Te ree 9 PP UGOBE atid dae Ral GERD dee BER Oe DALA SSR CRA aaa Lae eRe EP Sed Od 9 Programming Banple u erh 10 Introduction The 10 Bit Analog to Digital ADC10 API provides a set of functions for using the MSP430Ware ADC10 modules Functions are provided to initializae the ADC10 modules setup signal sources and reference voltages and manage interrupts for the ADC10 modules The ADC10 module provides the ability to convert analog signals into a digital value in respect to given reference voltages The ADC10 can generate digital values from 0 to Vcc with an 8 or 10 bit resolution It operates in 2 different sampling modes and 4 different conversion modes The smapling modes are extended sampling and pulse sampling in extended sampling the sample hold signal must stay high for the duration of sampling while in pulse mode a sampling timer is setup to start on a rising edge of the sample hold signal and sample for a specified amount of clock cycles The 4 conversio
27. 2 Power Management Module FRPMM Power Management Module FRPMM MTR EDIT cca bp d nod a Fool dod drop oj os danke bd eee beta bip kto 67 SUPE HEROS C soto wann d ERN n E ATEA E re UE tao rau EE RAR eee Ld 67 Presran nmyg Bande CT dek dn A a t 68 Introduction The PMM manages all functions related to the power supply and its supervision for the device Its primary functions are first to generate a supply voltage for the core logic and second provide several mechanisms for the supervision of the voltage applied to the device DVCC The PMM uses an integrated low dropout voltage regulator LDO to produce a secondary core voltage VCORE from the primary one applied to the device DVCC In general VCORE supplies the CPU memories and the digital modules while DVCC supplies the I Os and analog modules The VCORE output is maintained using a dedicated voltage reference The input or primary side of the regulator is referred to as its high side The output or secondary side is referred to as its low side API Functions FRPMM_enableLowPowerReset FRPMM_disableLowPowerReset If enabled SVSH does not reset device but triggers a system NMI If disabled SVSH resets device Note not available on FR57xx devices FRPMM enableSVSH FRPMM_disableSVSH If disabled on FR58xx FR59xx High side SVS SVSH is disabled in LPM2 LPM3 LPM4 LPM3 5 and LPM4 5 SVSH is always enabled in active mode LPMO and LPM1 If disabled on FR57xx Hi
28. 2C bus serially transmit and or receive serial data to from the eUSCI B module through the 2 wire I2C in terface The Inter Integrated Circuit I2C API provides a set of functions for using the MSP430Ware I2C modules Functions are provided to initialize the I2C modules to send and receive data obtain status and to manage interrupts for the I2C modules The I2C module provide the ability to communicate to other IC devices over an I2C bus The I2C bus is specified to support devices that can both transmit and receive write and read data Also devices on the I2C bus can be designated as either a master or a slave The MSP430Ware 12C modules support both sending and receiving data as either a master or a slave and also support the simultaneous operation as both a master and a slave 12 module can generate interrupts The I2C module configured as a master will generate interrupts when a transmit or receive operation is completed or aborted due to an error The I2C module configured as a slave will generate interrupts when data has been sent or requested by a master Master Operations To drive the master module the APIs need to be invoked in the following order el2C masterlnit el2C setSlaveAddress el2C setMode el2C enable m el2C enablelnterrupt if interrupts are being used This may be followed by the APIs for transmit or receive as required The user must first initialize the I2C module and configure it as a master with a call
29. 2C disablelnterrupt m el2C clearlnterruptFlag m el2C getlnterruptStatus Status and initialization functions for the I2C modules are m el2C masterlnit m el2C enable el2C disable el2C_isBusBusy el2C_isBusy el2C slavelnit m el2C interruptStatus el2C setSlaveAddress el2C setMode m el2C masterlsSTOPSent m el2C selectMasterEnvironmentSelect Sending and receiving data from the I2C slave module is handled by m el2C slaveDataPut m el2C slaveDataGet Sending and receiving data from the I2C slave module is handled by m el2C_masterSendSingleByte m el2C masterSendStart el2C_masterMultiByteSendStart el2C_masterMultiByteSendNext el2C_masterMultiByteSendFinish m el2C masterMultiByteSendStop m el2C masterMultiByteReceiveNext 2012 08 2814 58 17 0500 51 TI Information Selective Disclosure EUSCI Inter Integrated Circuit I2C el2C_masterMultiByteReceiveFinish el2C_masterMultiByteReceiveStop el2C_masterReceiveStart el2C_masterSingleReceive el2C_getReceiveBufferAddressForDMA el2C_getTransmitBufferAddressForDMA DMA related m el2C getReceiveBufferAddressForDMA m el2C getTransmitBufferAddressForDMA 16 3 Programming Example The following example shows how to use the I2C API to send data as a master Initialize Master eI2C masterInit MSP430 BASEADDRESS EUSCI BO eI2C CLOCKSOURCE SMCIK UCS getSMCLK MSP430 BASEADDRESS UCS 1000000 eI2C SET DATA RATE 400KBPS 1 eI2C NO AUTO STOP Speci
30. 30_BASEADDRESS_PORT1_R__ FRGPIO_PORT_P1 FRGPIO_PINO i Enable P1 4 internal resistance as pull Up resistance FRGPIO_setAsInputPinWithPullUpresistor __MSP430_BASEADDRESS_PORT1_R__ FRGPIO_PORT_P1 FRGPIO_PIN4 i P1 4 interrupt enabled FRGPIO enableInterrupt MSP430 BASEADDRESS PORT1 R FRGPIO PORT P FRGPIO_PIN4 i P1 4 Hi Lo edge FRGPIO_interruptEdgeSelect __MSP430_BASEADDRESS_PORT1_R__ FRGPIO_PORT_P1 FRGPIO_PIN4 FRGPIO_HIGH_TO_LOW_TRANSITION i P1 4 IFG cleared FRGPIO clearInterruptFlag MSP430 BASEADDRESS PORT1 R FRGPIO PORT P FRGPIO_PIN4 i Enter LPM4 w interrupt __bis_SR _ register LPM4_bits GIE For debugger no operation J K k k k k k k k ck k ke kk k k k k k k k k k k k k k k k HH ck ck k k k k k k ck ck ck ck ck ck k k k k k k k This is the PORT1 VECTOR interrupt vector service routine J f kk k k k k k ROR ROR AK kk X AK XXX AX kk kk kk Kok kk IRR KA AX KX KA X A IR OR I OR I IR ke kk I ke k pragma vector PORT1 VECTOR __ interrupt void Port 1 void P1 0 toggle FRGPIO_toggleOutputOnPin __MSP430_BASEADDRESS_PORT1_R__ FRGPIO_PORT_P1 FRGPIO_PINO i P1 4 IFG cleared FRGPIO clearInterruptFlag MSP430 BASEADDRESS PORT1 R FRGPIO PORT P FRGPIO_PIN4 2012 08 2814 58 17 0500 67 TI Information Selective Disclosure FRGPIO 68 TI Information Selective Disclosure 2012 08 2814 58 17 0500 22 22 1 22
31. 430 BASEADDRESS PORT1 R GPIO PORT P GPIO PINO i 2012 08 28 4 58 17 0500 147 TI Information Selective Disclosure WatchDog Timer WDT Enter LPMO enable interrupts __bis_SR_register LPMO_bits GIE For debugger no operation 148 2012 08 2814 58 17 0500 TI Information Selective Disclosure 2012 08 28 4 58 17_0500 149 TI Information Selective Disclosure IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI com
32. 5 1 073 741 824 To overcome this limitation the sigma delta modulator implements a technique called noise shaping due to an implemented feedback loop and integra tors the quantization noise is pushed to higher frequencies and thus much lower oversampling rates are sufficient to achieve high resolutions This driver is contained in driverlib 5xx_6xx sd24_b c with driverlib 5xx_6xx sd24_b h containing the API definitions for use by applications API Functions The SD24B API is broken into three groups of functions those that deal with initialization and conversions those that handle interrupts and those that handle auxillary features of the SD24B The SD24B initialization and conversion functions are m SD24B init m SD24B configureConverter m SD24B configureConverterAdvanced m SD24B startGroupConversion m SD24B stopGroupConversion m SD24B stopConverterConversion m SD24B startConverterConversion m SD24B configureDMATrigger 2012 08 2814 58 17 0500 111 TI Information Selective Disclosure 24 Bit Sigma Delta Converter SD24B m SD24B getResulis m SD24B getHighWordResults The SD24B interrupts are handled by m SD24B enablelnterrupt m SD24B disablelnterrupt m SD24B clearinterrupt m SD24B getlnterruptStatus Auxilary features of the SD24B are handled by m SD24B setConverterDataFormat m SD24B setlnterruptDelay m SD24B setOversampling m SD24B setGain 35 3 Programming Example The following example shows
33. 5xx 6xx i2c c with driverlib 5xx 6xx i2c h containing the API definitions for use by applications API Functions The I2C API is broken into three groups of functions those that deal with interrupts those that handle status and initialization and those that deal with sending and receiving data The I2C master and slave interrupts are handled by m I2C enablelnterrupt 12C_disablelnterrupt UART clearlnterruptFlag I2C getinterruptStatus Status and initialization functions for the I2C modules are m 2C masterlnit m I2C enable m 2C disable m I2C isBusBusy m I2C isBusy 12C_slavelnit 12C_interruptStatus I2C setSlaveAddress 12C_setMode Sending and receiving data from the I2C slave module is handled by m I2C slaveDataPut m I2C slaveDataGet Sending and receiving data from the I2C slave module is handled by m I2C masterSendSingleByte m I2C masterMultiByte SendStart 2012 08 2814 58 17 0500 79 TI Information Selective Disclosure Inter Integrated Circuit I2C m I2C masterMultiByteSendNext m I2C masterMultiByteSendFinish m I2C masterMultiByteSendStop m I2C masterMultiByte ReceiveStart m I2C masterMultiByte ReceiveNext m I2C masterMultiByte ReceiveFinish m I2C masterMultiByte ReceiveStop m I2C masterSingleReceiveStart m I2C masterSingleReceive m l2C getReceiveBufferAddressForDMA m I2C getTransmitBufferAddressForDMA DMA related m l2C getReceiveBufferAddressForDMA m I2C getTransmitBufferAddressFor
34. 7 0500 23 23 1 GPIO GPIO IPPON rra rs oko dod aces o ed o dokn adiu kod k eee eater bp n k Yi PT HEROS C o E PEE nd nu xa path EIE dus cde LEE Te Presran nmyg Bande sc ee 72 Introduction The digital I O features include Independently programmable individual I Os Any combination of input or output m Individually configurable P1 and P2 interrupts Some devices may include additional port interrupts Independent input and output data registers Individually configurable pullup or pulldown resistors Devices within the family may have up to twelve digital I O ports implemented P1 to P11 and PJ Most ports contain eight I O lines however some ports may contain less see the device specific data sheet for ports available Each I O line is individually configurable for input or output direction and each can be individually read or written Each I O line is individually configurable for pullup or pulldown resistors as well as configurable drive strength full or reduced PJ contains only four I O lines Ports P1 and P2 always have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal All P1 I O lines source a single interrupt vector P1IV and all P2 I O lines source a different single interrupt vector P2IV On some devices additional ports with interrupt capability may be available see th
35. 7 3 54 eSPI_select4PinFunctionality m eSPI_changeClockPhasePolarity Data handling is done by m eSPI_transmitData m eSPI_receiveData Interrupts from the SPI module are managed using m eSPI_disablelnterrupt m eSPI_enablelnterrupt m eSPI_getinterruptStatus m eSP clearlnterruptFlag DMA related m eSPI_getReceiveBufferAddressForDMA m eSPI_getTransmitBufferAddressForDMA Programming Example The following example shows how to use the SPI API to configure the SPI module as a master device and how to do a simple send of data Initialize Master returnValue eSPI masterInit MSP430 BASEADDRESS EUSCI AO eSPI CLOCKSOURCE ACLK UCS getSMCLK MSP430 BASEADDRESS UCS 500000 eSPI MSB FIRST eSPI PHASE DATA CHANGED ONFIRST CAPTURED ON NEXT eSPI CLOCKPOLARITY INACTIVITY HIGH eSPI 3PIN i if STATUS_FAIL returnValue return Enable SPI module eSPI enable MSP430 BASEADDRESS EUSCI A0 Enable USCI A0 RX interrupt eSPI enableInterrupt MSP430 BASEADDRESS EUSCI A0 eSPI RECEIVE INTERRUPT Wait for slave to initialize delay cycles 100 TXData 0x1 Holds TX data USCI A0 TX buffer ready while eSPI getInterruptStatus MSP430 BASEADDRESS EUSCI A0 eSPI TRANSMIT INTERRUPT 2012 08 2814 58 17 0500 TI Information Selective Disclosure EUSCI Synchronous Peripheral Interface SPI Transmit Data to slave eSPI transmitData MSP430 BASEADDRESS EUSCI AO TXD
36. ADC10 setResolution 2012 08 2814 58 17 0500 11 TI Information Selective Disclosure 10 Bit Analog to Digital Converter ADC 10 ADC10_setSampleHoldSignallnversion ADC10_setDataReadBackFormat ADC10_enableReferenceBurst ADC10_disableReferenceBurst ADC10_setReferenceBufferSamplingRate ADC10_getMemoryAddressForDMA ADC10_enable ADC10 disable 3 3 Programming Example The following example shows how to initialize and use the ADC10 API to start a single channel single conversion Initialize ADC10 with ADC10 s built in oscillator ADC10 init __MSP430_BASEADDRESS_ADC10__ ADC10 SAMPLEHOLDSOURCE SC ADC10 CLOCKSOURCE ADC100SC ADC10 CLOCKDIVIDEBY 1 Switch ON ADC10 ADC10 enable MSP430 BASEADDRESS ADC10 Setup sampling timer to sample and hold for 16 clock cycles ADC10_setupSamplingTimer __MSP430_BASEADDRESS_ADC10__ ADC10_CYCLEHOLD_16_CYCLES FALSE Configure the Input to the Memory Buffer with the specified Reference Voltages ADC10_memoryConfigure __MSP430_BASEADDRESS_ADC10__ ADC10_INPUT_AO ADC10_VREF_AVCC Vref AVcc ADC10 VREF AVSS Vref AVss while 1 Start a single conversion no repeating or sequences ADC10_startConversion __MSP430_BASEADDRESS_ADC10__ ADC10_SINGLECHANNEL Wait for the Interrupt Flag to assert while ADC10 getInterruptStatus __MSP430_BASEADDRESS_ADC10__ ADC10IFGO Clear the Interrupt Flag and start another conversion ADC10 clearInterr
37. AES ready interrupt flag The AES256 accelerator module performs encryption and decryption of 128 bit data with 128 192 256 bit keys according to the advanced encryption standard AES FIPS PUB 197 in hardware The AES accelerator features are AES encryption 128 bit 168 cycles 192 bit 204 cycles 256 bit 234 cycles AES decryption 128 bit 168 cycles 192 bit 206 cycles 256 bit 234 cycles m On the fly key expansion for encryption and decryption m Offline key generation for decryption m Shadow register storing the initial key for all key lengths m Byte and word access to key input data and output data m AES ready interrupt flag This driver is contained in driverlib 5xx 6xx aes c with driverlib 5xx 6xx aes h containing the API definitions for use by applications API Functions The AES module APIs are m AES setCipherKey m AES256 setCipherKey m AES encryptData m AES decryptDataUsingEncryptionKey m AES generateFirstRoundKey m AES decryptData m AES reset m AES startEncryptData 2012 08 2814 58 17 0500 25 TI Information Selective Disclosure Advanced Encryption Standard AES 7 3 26 m AES startDecryptDataUsingEncryptionKey m AES startDecryptData m AES startGenerateFirstRoundKey m AES getDataOut The AES interrupt handler functions m AES enablelnterrupt m AES disablelnterrupt m AES clearlnterruptFlag Programming Example The follow
38. DMA 24 3 Programming Example The following example shows how to use the I2C API to send data as a master Initialize Master I2C masterInit USCI B0 BASE SMCLK CLK getSMClk I2C SET DATA RATE 400KBPS Specify slave address I2C setSlaveAddress USCI BO BASE SLAVE ADDRESS Set in transmit mode I2C_setMode USCI_BO_BASE I2C TRANSMIT MODE Enable I2C Module to start operations I2C enable USCI BO BASE while 1 Send single byte data I2C_masterSendSingleByte USCI_BO_BASE transmitData Delay until transmission completes while I2C_busBusy USCI_BO_BASE Increment transmit data counter transmitData 80 2012 08 2814 58 17 0500 TI Information Selective Disclosure 25 25 1 25 2 LDO PWR LDO PWR IPT ONT AAPP N AP dod aces o eo do o odd dk kod k Rexall bip do ba 79 ee i PO ROT odd dd o B l o od SAL editus cde o had 79 lai oic n Example ss ee 80 Introduction The features of the LDO PWR module include m Integrated 3 3 V LDO regulator with sufficient output to power the entire MSP430 microcon troller and system circuitry from 5 V external supply m Current limiting capability on 3 3 V LDO output with detection flag and interrupt generation LDO input voltage detection flag and interrupt generation The LDO PWR power system incorporates an integrated 3 3 V LDO regulator that allows the entire MSP430 microcontroller to be powered from nominal 5 V LDOI when it is ma
39. Example 4 sa cera saa a a xo m9 doa nn eh 93 internal Reference REF ua u a aan na a a A AAA A 95 OUEN uy i A ana ae OST Ge ANA ee Ml ae een ee ym sets DB Belo nah re EB a alge A ee see Eye Bs we ee 95 SEE o MERI C p edat em Kaveh uae Gass AT ia RARO A 95 Programming Example sos ommo EY PORE a RA BR E m a Gee RC EUR 96 Internal Reference REFA lt lt zn s ee ss a a E 99 MAPOU ENO C Gs ao ke blah he cia ect M d art abe a dk adored cae a Bs so Reddo ede Seal Ow sok sede ROR k d val Rob ou us tat ka Bee 99 FI ONO EON ten ko v n lee ak WE sana Bu Sta Rh alu ae ake ade St et Beis A ke Chime Aare He ke adrenal Bodom ads lea Re Ey ey Be BEE at Ge le 4 99 2012 08 28 4 58 17_0500 TI Information Selective Disclosure Table of Contents 32 3 Programming EXample 2 4 2 oa eR ee XO CE OG mc RUE Y em pA Eon 100 33 Real Time Clock RIG cc o aeaee Hua aan RR RU ee RA ne 103 O A RS AR RE 103 IE PUM A A E RA Be ok end 103 33 3 Programming Example lt core na ua kom hom tog 9o RE a 93 9 RR ee mn 104 34 Real Time Clock RICH oases i jn 107 c Mu lx MEET 107 34 2 ALEC ss mt Book meee Eee SOAR ca l JE Red Eh died UITIUM 107 34 3 Programming Example lt c s sa ao roo bpem ra i AR 1 x09 A ee ee RR CR 108 35 24 Bit Sigma Delta Converter SD24B hh hh ee 109 AMU a Er a tn A RR A OA Dee 109 35 2 API uncle gt c sacs sm oem ae A RO AR A TRUE we EL 109 35 9 Programming EXample uos usc wem a en
40. ExternalClockSource must be called if an external crystal XT1 or XT2 is used and the user intends to call UCS getMCLK UCS_getSMCLK or UCS getACLK APIs If not it is not necessary to invoke this API Failure to invoke UCS_clockSignallnit sets the clock signals to the default modes ACLK default mode UCS XT1CLK SELECT SMCLK default mode UCS DCOCLKDIV SELECT MCLK de fault mode UCS DCOCLKDIV SELECT Also fail safe mode behavior takes effect when a slected mode fails The status and configuration guery are done by m UCS faultFlagStatus m UCS clearFaultFlag m UCS getACLK m UCS getSMCLK m UCS getMCLK Programming Example The following example shows some UCS operations using the APIs Set DCO FLL reference REFO UCS clockSignalInit MSP430 BASEADDRESS UCS UCS FLLREF UCS REFOCLK SELECT UCS CLOCK DIVIDER 1 Set ACLK REFO UCS_clockSignallnit MSP430 BASEADDRESS UCS UCS_ACLK UCS_REFOCLK_SELECT UCS CLOCK DIVIDER 1 Set Ratio and Desired MCLK Frequency and initialize DCO UCS initFLLSettle MSP430 BASEADDRESS UCS UCS MCLK DESIRED FREOUENCY IN KHZ UCS MCLK FLLREF RATIO i Verify if the Clock settings are as expected clockValue UCS getSMCLK __MSP430_BASEADDRESS_UCS__ while 1 2012 08 2814 58 170500 145 TI Information Selective Disclosure Unified Clock System UCS 146 2012 08 2814 58 17_0500 TI Information Selective Disclosure 46
41. LFMOD CLK ACLK can be divided by 1 2 4 8 16 or 32 ACLK is software selectable by individual peripheral modules m MCLK Master clock MCLK is software selectable as LFXTCLK VLOCLK LFMODCLK DCOCLK MODCLK or HFXTCLK MCLK can be divided by 1 2 4 8 16 or 32 MCLK is used by the CPU and system m SMCLK Sub system master clock SMCLK is software selectable as LFXTCLK VLOCLK LFMODCLK DCOCLK MODCLK or HFXTCLK SMCLK is software selectable by individual peripheral modules m MODCLK Module clock MODCLK may also be used by various peripheral modules and is sourced by MODOSC m VLOCLK VLO clock VLOCLK may also be used directly by various peripheral modules and is sourced by VLO Fail Safe logic The crystal oscillator faults are set if the corresponding crystal oscillator is turned on and not operating properly Once set the fault bits remain set until reset in software regardless if the fault condition no longer exists If the user clears the fault bits and the fault condition still exists the fault bits are automatically set otherwise they remain cleared The OFIFG oscillator fault interrupt flag is set and latched at POR or when any oscillator fault is detected When OFIFG is set and OFIE is set the OFIFG requests a user NMI When the interrupt 2012 08 2814 58 17 0500 39 TI Information Selective Disclosure Clock System CSA 12 2 40 is granted the OFIE is not reset automatically as it is in pre
42. MCLK is software selectable as XT1CLK VLOCLK DCOCLK and when available XT2CLK MCLK can be divided by 1 2 4 8 16 or 32 MCLK is used by the CPU and system m SMCLK Subsystem master clock SMCLK is software selectable as XT1CLK VLOCLK DCOCLK and when available XT2CLK SMCLK is software selectable by individual peripheral modules MODCLK Module clock MODCLK is used by various peripheral modules and is sourced by MODOSC Fail Safe logic The crystal oscillator faults are set if the corresponding crystal oscillator is turned on and not operating properly Once set the fault bits remain set until reset in software regardless if the fault condition no longer exists If the user clears the fault bits and the fault condition still exists the fault bits are automatically set otherwise they remain cleared The OFIFG oscillator fault interrupt flag is set and latched at POR or when any oscillator fault is detected When OFIFG is set and OFIE is set the OFIFG requests a user NMI When the interrupt is granted the OFIE is not reset automatically as it is in previous MSP430 families It is no longer required to reset the OFIE NMI entry exit circuitry removes this requirement The OFIFG flag must 2012 08 2814 58 17 0500 35 TI Information Selective Disclosure Clock System CS 11 2 36 be cleared by software The source of the fault can be identified by checking the individual fault bits If XT1 in LF mode is sourcing an
43. Module For memory buffers 0 7 sample hold for 64 clock cycles For memory buffers 8 15 sample hold for 4 clock cycles default Disable Multiple Sampling ADC12_setupSamplingTimer __MSP430_BASEADDRESS_ADC12_PLUS__ ADC12_CYCLEHOLD_64_CYCLES ADC12_CYCLEHOLD_4_CYCLES ADC12 MULTIPLESAMPLESENABLE Configure Memory Buffer Base address of the ADC12 Module Configure memory buffer 0 Map input AO to memory buffer 0 Vref Vref INT Vref AVss ADC12_memoryConfigure __MSP430_BASEADDRESS_ADC12_PLUS__ ADC12 MEMORY 0 ADC12 INPUT A0 ADC12 VREFPOS INT ADC12 VREFNEG AVSS ADC12 NOTENDOFSEOUENCE while 1 Enable Start sampling and conversion 98 2012 08 2814 58 17_0500 TI Information Selective Disclosure Internal Reference REF Base address of ADC12 Module Start the conversion into memory buffer 0 Use the single channel single conversion mode x ADC12 startConversion MSP430 BASEADDRESS ADC12 PLUS ADC12 MEMORY 0 ADC12 SINGLECHANNEL Poll for interrupt on memory buffer 0 while ADC12 interruptStatus MSP430 BASEADDRESS ADC12 PLUS ADC12IFG0 no operation SET BREAKPOINT HERE 2012 08 2814 58 17 0500 99 TI Information Selective Disclosure Internal Reference REF 100 2012 08 2814 58 17_0500 TI Information Selective Disclosure 32 32 1 32 2 Internal Reference REFA Internal Reference REFA IRE TD SEIT lk pd no dob ad tol ked va oo d
44. R FRPMM trigBOR MSP430 BASEADDRESS PMM FR5xx if FRPMM_getInterruptStatus __MSP430_BASEADDRESS_PMM_FR5xx__ FRPMM_PMMBORIFG FRPMM_clearInterrupt __MSP430_BASEADDRESS_PMM_FR5xx__ FRPMM PMMBORIFG 2012 08 2814 58 17_0500 TI Information Selective Disclosure Was t Was t Was t Power Management Module FRPMM __delay_cycles 1000000 FRPMM lockLPM5 MSP430 BASEADDRESS PMM FR5xx Disable SVSH Base Address of Comparator D High side SVS SVSH is disabled in LPM4 5 SVSH is always enabled in active mode and LPM0 1 2 3 4 and LPM3 5 FRPMM_disableSVSH __MSP430_BASEADDRESS_PMM_FR5xx__ Disable SVSL Base Address of Comparator D Low side SVS SVSL is disabled in low power modes SVSL is always enabled in active mode and LPMO x FRPMM disableSVSL MSP430 BASEADDRESS PMM FR5xx Disable Regulator Base Address of Comparator D Regulator is turned off when going to LPM3 4 System enters LPM3 5 or LPM4 5 respectively x FRPMM_regOff __MSP430_BASEADDRESS_PMM_FR5xx__ __bis_SR_register LPM4_bits Enter LPM4 5 This automatically locks if not locked already all GPIO pir and will set the LPM5 flag and set in the PM5CTLO register upon wake __no_operation Don t sleep 2012 08 2814 58 17 0500 71 TI Information Selective Disclosure Power Management Module FRPMM 72 TI Information Selective Disclosure 2012 08 2814 58 1
45. R 1 2012 08 28 4 58 17 0500 41 TI Information Selective Disclosure Clock System CSA 42 TI Information Selective Disclosure 2012 08 2814 58 17 0500 13 13 1 13 2 13 3 Cyclical Redundancy Check CRC Cyclical Redundancy Check CRC MOU HON k o aa tol dod doleo ko od do kakaa k book earner d 41 N a U PO ROT C coton pais n o a a tee VAE eden en Ko MS 41 Prez MEK DNE CT dd A z t 41 Introduction The Cyclic Redundancy Check CRC API provides a set of functions for using the MSP430Ware CRC module Functions are provided to initialize the CRC and create a CRC signature to check the validity of data This is mostly useful in the communication of data or as a startup procedure to as a more complex and accurate check of data The CRC module offers no interrupts and is used only to generate CRC signatures to verify against pre made CRC signatures Checksums This driver is contained in driverlib 5xx 6xx crc c with driverlib 5xx 6xx crc h containing the API definitions for use by applications API Functions The CRC API is one group that controls the CRC module m CRC setSeed m CRC setData m CRC setSignatureByteReversed m CRC getSignature m CRC getResult m CRC getResultBitReversed Programming Example The following example shows how to initialize and use the CRC API to generate a CRC signature on an array of data that can be included in a UART message with the data to check for validity
46. S E A a A S 142 45 3 Programming Exemple lt sz sem soto mono o e pa ooa 9 Ro EE a Er mann 143 46 WatchDog Timer WBT x ER EO x OEE O X OK RE eS 145 FR POU MM MEMBER 145 AG ap dli MM 145 46 3 Programming Example eu 0 000 0 saa mori EE m m 1 a RO O ROY ox ROK ne ORO E 145 IMPORTANT NOTICE uuum x RR ERE RE R e mEdE SS RUE Xe gm mcecR EIE EO A xo UE deo v ROS eR DEC es 148 2012 08 2814 58 170500 5 TI Information Selective Disclosure Table of Contents 6 2012 08 2814 58 17_0500 TI Information Selective Disclosure Introduction 1 Introduction The Texas Instruments MSP430 Peripheral Driver Library is a set of drivers for accessing the peripherals found on the MSP430 family of microcontrollers While they are not drivers in the pure operating system sense that is they do not have a common interface and do not connect into a global device driver infrastructure they do provide a mechanism that makes it easy to use the device s peripherals The capabilities and organization of the drivers are governed by the following design goals They are written entirely in C except where absolutely not possible They demonstrate how to use the peripheral in its common mode of operation They are easy to understand They are reasonably efficient in terms of memory and processor usage They are as self contained as possible Where possible computations that can be performed at compile time are done there instead of
47. SEADDRESS_COMPE__ COMPE_INPUT2 COMPE_VREF COMPE_FILTEROUTPUT_OFF COMPE_NORMALOUTPUTPOLARITY 3 Set the reference voltage that is being supplied to the terminal Base Address of Comparator E Reference Voltage of 2 0 V Upper Limit of 2 0 32 32 2 0V Lower Limit of 2 0x 32 32 2 0V Static Accuracy COMPE setReferenceVoltage MSP430 BASEADDRESS COMPE COMPE VREFBASE2 OV 32 32 COMPE_ACCURACY_STATIC i Disable Input Buffer on P1 2 CD2 Base Address of Comparator E Input Buffer port Selecting the CEx input pin to the comparator multiplexer with the CEx bits automatically disables output driver and input buffer for that pin regardless of the state of the associated CEPD x bit COMPE disableInputBuffer MSP430 BASEADDRESS COMPE COMPE INPUT2 Allow power to Comparator module COMPE enable MSP430 BASEADDRESS COMPE 32 2012 08 2814 58 17 0500 TI Information Selective Disclosure Comparator COMPE delay cycles 400 delay for the reference to settle 2012 08 2814 58 17 0500 33 TI Information Selective Disclosure Comparator COMPE 34 TI Information Selective Disclosure 2012 08 2814 58 170500 Clock System CS 11 Clock System CS Gis l c eee ee ee Te eee ne rete eee eee eer P POV eee Ter eter dora dio rT Teer eT et er Tere re errs rere ER PCOS nen 34 Prez MEK DNE see 35 11 1 Introduction The clock system module supports low sys
48. SS ADC12B NOTENDOFSEQUENCE ADC12B WINDOW COMPARATOR DISABLE ADC12B DIFFERENTIAL MODE DISABLE while 1 Enable Start first sampling and conversion cycle Base address of ADC12 Module Start the conversion into memory buffer 0 Use the single channel single conversion mode x ADC12B startConversion MSP430 BASEADDRESS ADC12 B ADC12B MEMORY O0 ADC12B SINGLECHANNEL Poll for interrupt on memory buffer 0 2012 08 2814 58 17 0500 23 TI Information Selective Disclosure 12 Bit Analog to Digital Converter ADC 12B while ADC12B_getInterruptStatus __MSP430_BASEADDRESS_ADC12_B_ 0 ADC12B IFG0 __no_operation SET BREAKPOINT HERE 24 2012 08 2814 58 17_0500 TI Information Selective Disclosure 7 1 7 2 Advanced Encryption Standard AES Advanced Encryption Standard AES PPT HON EEE no ho usd odd z katoda kon odk du kouka lk tote k bp n do EUR d 23 BR EEE O ROT C coton pis n o a a l A ad MM o o cp EM LEE 23 Pregranimmno DE see 24 Introduction The AES accelerator module performs encryption and decryption of 128 bit data with 128 bit keys according to the advanced encryption standard AES FIPS PUB 197 in hardware The AES accelerator features are m Encryption and decryption according to AES FIPS PUB 197 with 128 bit key m On the fly key expansion for encryption and decryption m Off line key generation for decryption m Byte and word access to key input and output data m
49. TI Information Selective Disclosure 19 TEXAS INSTRUMENTS MSP430 Peripheral Driver Library USER S GUIDE Copyright 2012 Texas Instruments Incorporated Copyright Copyright 2012 Texas Instruments Incorporated All rights reserved MSP430 and 430ware are registered trademarks of Texas Instruments Other names and brands may be claimed as the property of others Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semicon ductor products and disclaimers thereto appears at the end of this document Texas Instruments I TEXAS ee S E INSTRUMENTS http www ti com msp430 Revision Information This is version 1 25 00 00 of this document last updated on 2012 08 28 4 58 17 0500 2 2012 08 2814 58 17_0500 TI Information Selective Disclosure Table of Contents Table of Contents poda sone is eS ae ae eee a A A Oe A daj da ea ee GR er eg 2 Revision Information lt csc 0 00 0a 0 cra as aa a ee ann 2 1 dune bei lt lt E 2 02 En ana Learn ra nr en 5 2 How to create a new project that uses Driverlib lt lt lt s lt eee 7 3 10 Bit Analog to Digital Converter ADC10 lt 4 s ee eee eee rrr 9 31 Io NER aby eg ek od LUTTE 9 32 AP POGUES knee 9 X09 ee ee wa d we A a a dU ocu V ee Ee ee ae 9 43 Programming Example errea aa ce ohm A a a
50. TVALUE COMPARE VALUE i Enter LPMO enable interrupts bis SR register LPMO bits GIE For debugger no operation J f kk kk k k kk k HH AK XXX AK kk Kok kk X AK kk IRR KA X KA kk X A ko RRA RR Kok kk ko ke kk ko ke kk k ke ke ke This is the Timer AO interrupt vector service routine TKK k k k k e HH HH KAZ X ORR IR KA X A IR IR IR I OR ke kk a KR pragma vector TIMER1 A0 VECTOR interrupt void TIMER1 A0 ISR void Toggle P1 0 GPIO_toggleOutputOnPin __MSP430_BASEADDRESS_PORTI_R__ GPIO_PORT_P1 GPIO_PINO i Add Offset to CCRO Timer_setCompareValue __MSP430_BASEADDRESS_T1A3__ TIMER_CAPTURECOMPARE_REGISTER_O COMPARE_VALUE 2012 08 2814 58 17 0500 123 TI Information Selective Disclosure Timer 124 2012 08 2814 58 17_0500 TI Information Selective Disclosure 40 40 1 TimerA TimerA OU SEDIT cres Raton dob obo bap dor a abuse bles d n ORE DRE bn bbe du oia dott bebe ne DE dated Aa itd 123 RO E OS sko A nra o auch oo dob a de ES DAE Sega ULM RU ce a ete ac 124 Peca MCH Bande anne 124 Introduction TimerA is a 16 bit timer counter with multiple capture compare registers TimerA can support mul tiple capture compares PWM outputs and interval timing TimerA also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers This peripheral API handles Timer A hardware periph
51. ToggleEdgeDirection Auxilary features of the COMPD are handled by 2012 08 2814 58 17 0500 29 TI Information Selective Disclosure Comparator COMPD m COMPD enableShortOflnputs COMPD disableShortOfInputs COMPD disablelnputBuffer COMPD enablelnputBuffer COMPD IOSwap COMPD setReferenceAccuracy 9 3 Programming Example The following example shows how to initialize and use the COMPD API to turn on an LED when the input to the positive terminal is highed than the input to the negative terminal Initialize the Comparator D module x Base Address of Comparator D Pin CD2 to Positive Terminal Reference Voltage to Negative Terminal Normal Power Mode Output Filter On with minimal delay Non Inverted Output Polarity COMPD_init __MSP430_BASEADDRESS_COMPD__ COMPD_INPUT2 COMPD_VREF COMPD_FILTEROUTPUT_OFF COMPD_NORMALOUTPUTPOLARITY i Set the reference voltage that is being supplied to the terminal x Base Address of Comparator D Reference Voltage of 2 0 V Upper Limit of 2 0 32 32 2 0V Lower Limit of 2 0 32 32 2 0V x COMPD setReferenceVoltage MSP430 BASEADDRESS COMPD COMPD VREFBASE2 OV 32 32 COMPD ACCURACY STATIC i Disable Input Buffer on P1 2 CD2 Base Address of Comparator D Input Buffer port Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output driver and input buffer for that pin regardless of the state of
52. UART clearlnterruptFlag m UART queryStatusFlags DMA related m UART getReceiveBufferAddressForDMA m UART getTransmitBufferAddressForDMA Programming Example The following example shows how to use the UART API to initialize the UART transmit characters and receive characters if STATUS FAIL UART init MSP430 BASEADDRESS USCI A0 UART CLOCKSOURCE SMCLK UCS getSMCLK MSP430 BASEADDRESS UCS BAUD RATE UART NO PARITY UART LSB FIRST UART ONE STOP BIT UART MODE UART OVERSAMPLING BAUDRATE GENERATION return Enable UART module for operation UART enable __MSP430_BASEADDRESS_USCI_AO__ Enable Receive Interrupt UART enableInterrupt MSP430 BASEADDRESS USCI AO UCRXIE 2012 08 2814 58 170500 TI Information Selective Disclosure UART Transmit data UART transmitData MSP430 BASEADDRESS USCI AO transmitData Enter LPM3 interrupts enabled bis SR register LPM3 bits GIE no operation J f kk kk k k Sk kk kk kk ke HH ko kk X AK kk IR ko kk KX kk X A kk kk IR I k k ko ke ke kk ke kk k ke ke k This is the USCI A0 interrupt vector service routine J f Kk kk kk ke kk koe kk kk kk ck ke ke kk I kk ck ck kc kck ck IR RARA ck kkk kkk kkk ck ck ck kkk kkk kk pragma vector USCI A0 VECTOR interrupt void USCI A0 ISR void switch __even_in_range UCAOIV 4 Vector 2 RXIFG case 2 Echo back RXed character confirm TX buffe
53. Vcc from an 8 or 12 bit value There can be one or two DAC12 modules in a device and if there are two they can be grouped together to create two analog signals in simultaneously There are 3 ways to latch data in to the DAC module and those are by software with the startConversion API function call as well as by the Timer A output of CCR1 or Timer B output of CCR2 The calibration API will unlock and start calibration then wait for the calibration to end before locking it back up all in one API There are also functions to read out the calibration data as well as be able to set it manually The DAC12 module can generate one interrupt for each DAC module It will generate the interrupt when the data has been latched into the DAC module to be output into an analog signal This driver is contained in driverlib 5xx_6xx dacl2 c with driverlib 5xx 6xx dac12 h containing the API definitions for use by applications API Functions The DAC12 API is broken into three groups of functions those that deal with initialization and conversions those that deal with calibration of the output and those that handle interrupts The DAC12 initialization and conversion functions are m DAC12 init m DAC12 setAmplifierSetting m DAC12 disable DAC12 enableGrouping DAC12 disableGrouping DAC12 enableConversions DAC12 setData DAC12 disableConversions DAC12 setResolution DAC12 setlnputDataFormat DAC12 getDataBufferMemoryAddressForDMA 2012 08 28 4 58
54. WM outputs PWM outputs can be generated by ini tializing the compare mode with Timer initCompare and the necessary parameters The PWM may be customized by selecting a desired timer mode continuous up upDown duty cycle out put mode timer period etc The library also provides a simpler way to generate PWM using Timer_generatePWM API However the level of customization and the kinds of PWM generated are limited in this API Depending on how complex the PWM is and what level of customization is required the user can use Timer_generatePWM or a combination of Timer_initCompare and timer start APIs The timer API provides a set of functions for dealing with the timer module Functions are pro vided to configure and control the timer along with functions to modify timer counter values and to manage interrupt handling for the timer Control is also provided over interrupt sources and events Interrupts can be generated to indicate that an event has been captured This driver is contained in driverlib 5xx_6xx timer c with driverlib 5xx 6xx timer h containing the API definitions for use by applications 2012 08 2814 58 17 0500 121 TI Information Selective Disclosure Timer 39 2 API Functions The timer API is broken into three groups of functions those that deal with timer configuration and control those that deal with timer contents and those that deal with interrupt handling Timer configuration and initialization is h
55. WeB rn A RRO ES dm scum ose gere ee m due de qr ren eRe Me o G 127 RPM eo lt is oar A cass Bee te mente ese ete ak putter rare te ata Slo eG aia a ZB CaP acer ae a Rasa ee wh ease A 127 41 2 dlc sca ge Soa Bae a ee A ee 128 41 3 Programming EXAM 22 se ju ee na RE RR y mk kom RR a namen 129 12 MIER cece Ga ee eos eee eR Se See eee Lee eee eee Oe eee Shek S oe 131 MEN ITU c MEE Rie Sete ws Besar can ha n AE uae YO do v l ods Soe She nim as Sa ges EEUU 131 422 ARI FUNCIONS sr e aore ae a ae Rex pa ae aw BG Be a eee E dE Renae CE qud RO ae we ARE ee 132 42 3 Programming Example uu a eraen aa kPa ppa a 9 9 O3 Yo Y ee a nn 134 43 Tag Length Value uuo 9 ak AR i 3 x XC Eee we A ee A WR LR as 135 BE MODO V N z a 5 Vu ihe os xs Wee Ronee ema Las Ine a E Gg ga ohh aan GPS OND els Tr 135 432 dal rci EM Goat kan ts e Bow tee 135 43 3 Programming Example 2s e wo a sn RE Re aD a ee AA 135 EI MAR A ou de oe A es ade Ro A ae Cee A Skee ee ee ee 137 t a uic s sade Re ean ena E SB deem cae toa Ss fet leva Sk Sugg lm ae Barer tl we ae yan De et ar ak ee 137 442 AR PURGHONS gt cuum dae ee ee UR we OES xov mw X aom Pow ee RA od Se up ow ee a ees 137 44 3 Programming Example lt cee oro on y oy og mo DE RS 9S a ROW Oe ROUX Y we ni 138 45 United Clock System UCS o 266 eee a gringe We BER ER 8 dB m Ce a Be Romx d Rx a 141 All INICIEN a a a A 141 432 ARI BBAGHORS vua uk cc mox kw a eee RO RUE E
56. _RESET_SET 383 i Initialize compare mode to generate PWM2 TimerB_initCompare __MSP430_BASEADDRESS_TOB7__ TIMERB_CAPTURECOMPARE_REGISTER_2 TIMERB_CAPTURECOMPARE_INTERRUPT_ENABLE TIMERB_OUTPUTMODE_RESET_SET 128 i 2012 08 2814 58 17_0500 131 TI Information Selective Disclosure timerB 132 2012 08 2814 58 17_0500 TI Information Selective Disclosure 42 42 1 timerD timerD AA o ne kk budto do dd BOB db kk bebe here dated Rd dea 131 Z OS snb A n o po ok oo dob a d S B dd ae o U dp a sa SS 132 Prozac EXSImplec s bos opak d n v generar el kl k bn pad o D MUERE do le eds k 134 Introduction Timer D is a 16 bit timer counter with multiple capture compare registers Timer D can support multiple capture compares interval timing and PWM outputs both in general and high resolution modes Timer D also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions from each of the capture compare registers This peripheral API handles Timer D handware peripheral timerD features include m Asynchronous 16 bit timer counter with four operating modes and four selectable lengths Selectable and configurable clock source Configurable capture compare registers m Controlling rising and falling PWM edges by combining two neighbor TDCCR registers in one compare channel output m Configurable outputs with PWM capability m High resolution mode with a fine clock frequen
57. _initCapture m TimerB_initCompare TimerB_clear m TimerB_stop m TimerB_initCompareLatchLoadEvent m TimerB_selectLatchingGroup m TimerB_selectCounterLength TimerB outputs are handled by m TimerB_getSynchronizedCaptureComparelnput m TimerB_getOutputForOutputModeOutBitValue m TimerB_setOutputForOutputModeOutBitValue m TimerB_generatePWM m limerB getCaptureCompareCount m limerB setCompareValue The interrupt handler for the TimerB interrupt is managed with m TimerB enablelnterrupt m TimerB disablelnterrupt 2012 08 2814 58 17 0500 TI Information Selective Disclosure timerB m TimerB_getlnterruptStatus m limerB enableCaptureComparelnterrupt m limerB disableCaptureComparelnterrupt m limerB getCaptureComparelnterruptStatus m limerB clearCaptureComparelnterruptFlag m TimerB clearTimerlnterruptFlag 41 3 Programming Example The following example shows some timerB operations using the APIs Start timerB TimerB_configureUpMode __MSP430_BASEADDRESS_TOB7__ TIMERB_CLOCKSOURCE_SMCLK TIMERB_CLOCKSOURCE_DIVIDER_1 511 TIMERB_TBIE_INTERRUPT_DISABLE TIMERB_CCIE_CCRO_INTERRUPT_DISABLE TIMERB_DO_CLEAR i TimerB_startCounter __MSP430_BASEADDRESS_TOB7__ TIMERB_UP_MODE i Initialize compare mode to generate PWM1 TimerB_initCompare __MSP430_BASEADDRESS_TOB7__ TIMERB_CAPTURECOMPARE_REGISTER_1 TIMERB_CAPTURECOMPARE_INTERRUPT_DISABLE TIMERB_OUTPUTMODE
58. able interrupts control the RST NMI pin control various SYS controls setup the BSL and control the JTAG Mailbox The SFR_SYS module can enable interrupts to be generated from other peripherals of the device This driver is contained in driverlib 5xx_6xx sfr_sys c with driverlib 5xx_6xx sfr_sys h containing the API definitions for use by applications API Functions The SFR_SYS API is broken into 5 groups the SFR interrupts the SFR RST NMI pin control the various SYS controls the BSL controls and the JTAG mailbox controls The SFR interrupts are handled by m SFR enablelnterrupt m SFR disablelnterrupt m SFR getlnterruptStatus m SFR_clearinterrupt The SFR RST NMI pin is controlled by m SFR setResetPinPullResistor m SFH setNMIEdge m SFR setResetNMIPinFunction The various SYS controls are handled by m SYS enableDedicatedJTAGPins m SYS getBSLEntryIndication m SYS enablePMMAccessProtect m SYS enableRAMBasedinterruptVectors m SYS disableRAMBasedlnterruptVectors The BSL controls are handled by 2012 08 2814 58 17 0500 113 TI Information Selective Disclosure SFR SYS Modules m SYS enableBSL Protect m SYS disableBSL Protect m SYS disableBSLMemory m SYS enableBSLMemory m SYS setRAMAssignedToBSL m SYS setBSL Size The JTAG Mailbox controls are handled by m SYS JTAGMailboxlnit m SYS getJTAGMailboxFlagStatus m SYS getJTAGInboxMessage16Bit m SYS getJTAGInboxMessage32Bit m SYS_setJTAGOutgoingM
59. andled by m Timer_startContinousMode m Timer_startUpMode m Timer_startUpDownMode m Timer_initCapture m Timer_initCompare m Timer_clear m Timer_stop Timer outputs are handled by m Timer_getSynchronizedCaptureComparelnput m Timer_getOutputForOutputModeOutBitValue m Timer_setOutputForOutputModeOutBitValue m Timer_generatePWM m Timer_getCaptureCompareCount m Timer_setCompareValue The interrupt handler for the Timer interrupt is managed with m Timer enablelnterrupt m Timer disablelnterrupt m limer getlnterruptStatus m Timer enableCaptureComparelnterrupt m Timer disableCaptureComparelnterrupt m Timer getCaptureComparelnterruptStatus m Timer clearCaptureComparelnterruptFlag m Timer clearTimerlnterruptFlag 39 3 Programming Example The following example shows some timer operations using the APIs Set P1 0 to output direction GPIO setAsOutputPin MSP430 BASEADDRESS PORT1 R GPIO PORT P GPIO PINO i 122 2012 08 2814 58 17_0500 TI Information Selective Disclosure Timer Start timer in continuous mode sourced by SMCLK Timer startContinousMode __MSP430_BASEADDRESS_T1A3__ TIMER CLOCKSOURCE SMCLK TIMER CLOCKSOURCE DIVIDER 1 TIMER TAIE INTERRUPT DISABLE TIMER DO CLEAR Initiaze compare mode Timer initCompare MSP430 BASEADDRESS T1A3 TIMER CAPTURECOMPARE REGISTER 0 TIMER CAPTURECOMPARE INTERRUPT ENABLE TIMER OUTPUTMODE OUTBI
60. are set and latched when the respective oscillator is enabled but not operating properly therefore they must be explicitly cleared in software The oscillator fault flags on previous MSP430 generations are not latched and are asserted only as long as the failing condition exists Therefore an important difference between the families is that the fail safe behavior in a 5xx based MSP430 remains active until both the OFIFG and the respective fault flag are cleared in software This fail safe behavior is implemented at the oscillator level at the system clock level and conse quently at the module level Some notable highlights of this behavior are described below For the full description of fail safe behavior and conditions see the MSP430x5xx MSP430x6xx Family UserSs Guide SLAU208 2012 08 2814 58 17 0500 143 TI Information Selective Disclosure Unified Clock System UCS 45 2 144 m Low frequency crystal oscillator 1 LFXT1 The low frequency 32768 Hz crystal oscillator is the default reference clock to the FLL An asserted XT1LFOFFG switches the FLL reference from the failing LFXT1 to the internal 32 kHz REFO This can influence the DCO accuracy because the FLL crystal ppm specification is typically tighter than the REFO accuracy over temperature and voltage of 396 m System Clocks ACLK SMCLK MCLK A fault on the oscillator that is sourcing a system clock switches the source from the failing oscillator to the DCO osc
61. ase Address of By default the up from an LPMx are previously 1 FRPMM_unlockL Get I x Ba mask FRPMM_PMM FRPMM_PMM FRPMM_PMM FRPMM_SVS FRPMM_SVS FRPMM_PMM return STATUS_SU GPIO pins Comparator D pins are unlocked unless waking 5 state in which case all GPIO ocked PM5 __MSP430_BASEADDRESS_PMM_FR5xx__ nterrupt Status from the PMMIFG register se Address of Comparator D BORIFG RSTIFG PORIFG LIFG HIFG LPM5IFG CCESS 0x01 or STATUS FAIL 0x00 if FRPMM getInterruptStatus MSP430 BASEADDRESS PMM FR5xx FRPMM PMMLPM5IFG Clear mask FRPMM_PMM FRPMM_PMM FRPMM_PMM FRPMM_SVS FRPMM_SVS FRPMM_PMM FRPMM_ALL F Interrupt Flag from the PMMIFG register Base Address of Comparator D BORIFG RSTIFG PORIFG LIFG HIFG LPM5IFG RPMM clearInterrupt MSP430 BASEADDRESS PMM FR5xx FRPMM_PMMLPM5IFG if FRPMM getInterruptStatus MSP430 BASEADDRESS PMM FR5xx FRPMM PMMRSTIFG F delay c Lock Base Address of Forces all GPIO states during a FRPMM loc Trigg Base Address of Forces the devic RPMM clearInterrupt MSP430 BASEADDRESS PMM FR5xx FRPMM PMMRSTIFG ycles 1000000 GPIO output states before triggering a BOR Comparator D to retain their output reset x kLPM5 __MSP430_BASEADDRESS_PMM_FR5xx__ er a software Brown Out Reset BOR Comparator D es to perform a BO
62. at run time They can be built with more than one tool chain Some consequences of these design goals are m The drivers are not necessarily as efficient as they could be from a code size and or execution speed point of view While the most efficient piece of code for operating a peripheral would be written in assembly and custom tailored to the specific requirements of the application further size optimizations of the drivers would make them more difficult to understand m The drivers do not support the full capabilities of the hardware Some of the peripherals provide complex capabilities which cannot be utilized by the drivers in this library though the existing code can be used as a reference upon which to add support for the additional capabilities m The APIs have a means of removing all error checking code Because the error checking is usually only useful during initial program development it can be removed to improve code size and speed For many applications the drivers can be used as is But in some cases the drivers will have to be enhanced or rewritten in order to meet the functionality memory or processing requirements of the application If so the existing driver can be used as a reference on how to operate the peripheral Each MSP430ware driverlib API takes in the base address of the corresponding peripheral as the first parameter This base address is obtained from the msp430 device specific header files or from the devi
63. ata bis SR register LPM0 bits GIE CPU off enable interrupts no operation Remain in LPMO pragma vector USCI A0 VECTOR interrupt void USCI A0 ISR void switch __even_in_range UCAOIV 4 Vector 2 case 2 break default break RXIFG USCI A0 TX buffer ready while eSPI getInterruptStatus MSP430 BASEADDRESS EUSCI A0 eSPI TRANSMIT INTERRUPT RXData eSPI receiveData MSP430 BASEADDRESS EUSCI AO Increment data TXData Send next value eSPI_transmitData __MSP430_BASEADDRESS_EUSCI_AO__ TXData i Delay between transmissions for slave to process information __delay_cycles 40 2012 08 2814 58 170500 55 TI Information Selective Disclosure EUSCI Synchronous Peripheral Interface SPI 56 TI Information Selective Disclosure 2012 08 2814 58 170500 18 18 1 18 2 EUSCI UART EUSCI UART nn kh n dod a k oo eo do o od Ede sh boku db n Rd d 25 SUPE HEROS C octo E DRE db S bb D ep bud ur ox MU ta pati EIE edu dus exequi tbe 55 Presran nmyg Bande ss ee 56 Introduction The MSP430Ware library for UART mode features include m Odd even or non parity m Independent transmit and receive shift registers m Separate transmit and receive buffer registers LSB first or MSB first data transmit and receive m Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge
64. ation 136 2012 08 2814 58 17 0500 TI Information Selective Disclosure 43 43 1 43 2 43 3 Tag Length Value Tag Length Value MESSI rias AAA AAA AAA AAA RAR 135 AP PUM MONS id nee 135 Pregrammng Example anne 135 Introduction The TLV structure is a table stored in flash memory that contains device specific information This table is read only and is write protected It contains important information for using and calibrating the device A list of the contents of the TLV is available in the device specific data sheet in the Device Descriptors section and an explanation on its functionality is available in the MSP430x5xx MSP430x6xx Family UserSs Guide This driver is contained in driverlib 5xx_6xx tlv c With driverlib 5xx_6xx tlv h containing the API definitions for use by applications API Functions The APIs that help in querying the information in the TLV structure are listed m TLV_getinfo This function retrieves the value of a tag and the length of the tag m TLV_getDeviceType This function retrieves the unique device ID from the TLV structure m TLV_getMemory The returned value is zero if the end of the memory list is reached m TLV_getPeripheral The returned value is zero if the specified tag value peripheral is not available in the device m TLV getlnterrupt The returned value is zero is the specified interrupt vector is not defined Programming Example The following example shows some tl
65. ation memory can have its access rights set independently m All MPU registers are protected from access by password This driver is contained in driverlib 5xx 6xx mpu c With driverlib 5xx 6xx mpu h containing the API definitions for use by applications API Functions The MPU API is broken into three group of functions those that handle initialization those that deal with memory segmentation and access rights definition and those that handle interrupts The MPU initialization function is m MPU start The MPU memory segmentation and access right definition functions are MPU createTwoSegments m MPU createThreeSegments The MPU interrupt handler functions m MPU enablePUCOnviolation MPU getlnterruptStatus m MPU clearlnterruptFlag m MPU clearAllInterruptFlags 2012 08 2814 58 17 0500 85 TI Information Selective Disclosure Memory Protection Unit MPU 26 3 Programming Example The following example shows some MPU operations using the APIs Define memory segment boundaries and set access right for each memory segment MPU_createThreeSegments __MSP430_BASEADDRESS_MPU__ 0x04 0x08 MPU_READ MPU_WRITE MPU_EXEC MPU_READ MPU READ MPU WRITE MPU EXEC Configures MPU to generate a PUC on access violation on the second segment MPU enablePUCOnViolation MSP430 BASEADDRESS MPU MPU SECOND SEG Enables the MPU module MPU start MSP430 BASEADDRESS MPU 86 2012 08 2814 58 17 0500 TI Informatio
66. block or burst block transfers once the block is completely transfered the interrupt is asserted 15 2 API Functions The DMA API is broken into three groups of functions those that deal with initialization and trans fers those that handle interrupts and those that affect all DMA channels The DMA initialization and transfer functions are DMA init DMA setSrcAddress DMA setDstAddress DMA enable Transfers DMA disable Transfers DMA startTransfer DMA setlransferSize The DMA interrupts are handled by DMA enablelnterrupt DMA disablelnterrupt DMA getlnterruptStatus DMA clearlnterrupt DMA NMlAbortStatus DMA clearNMIAbort Features of the DMA that affect all channels are handled by DMA disable TransferDuringReadModifyWrite DMA enableTransferDuringReadModifyWrite DMA enableRoundRobinPriority DMA disable RoundRobinPriority DMA enableNMIAbort DMA disableNMIAbort 2012 08 2814 58 17 0500 47 TI Information Selective Disclosure Direct Memory Access DMA 15 3 Programming Example 48 The following example shows how to initialize and use the DMA API to transfer words from one spot in RAM to another Initialize and Setup DMA Channel 0 Base Address of the DMA Module Configure DMA channel 0 Configure channel for repeated block transfers DMA interrupt flag will be set after every 16 transfers Use DMA_startTransfer function to trigger transfers Transfer Word to Word Trigger upon Rising Edge of Trigger Source Signal DMA_
67. ce datasheet The example code for the various peripherals show how base address is used When using CCS the eclipse shortcut Ctrl Space helps Type __MSP430 and Ctrl Space and the list of base addresses from the included device specific header files is listed The following tool chains are supported m AR Embedded Workbench m Texas Instruments Code Composer Studio 2012 08 2814 58 17 0500 7 TI Information Selective Disclosure Introduction 8 2012 08 2814 58 17_0500 TI Information Selective Disclosure How to create a new project that uses Driverlib 2 How to create a new project that uses Driverlib To create a driverlib project from scratch An emptyProject has been created for the con venience of the user so that he can create a project that uses driverlib This is avail able in C ti msp430 MSP430ware_x_xx_xx_xx examples driverlib 5xx_6xx 00_emptyProject IAR C ti msp430 MSP430ware_x_xx_xx_xx examples driverlib 5xx_6xx 00_emptyProject CCS or the correspond ing relative path where MSP430ware is installed The features of the emptyProject are m Includes driverlib library file by default m Includes a main c by default that has the following statements include inc hw memmap h void main void W Project is build by default for MSP430F5438A and has a large data model since driverlib is built by defualt for large data model W The project include path has the following added C ti msp43
68. ceVoltage m REFA enableReferenceVoltageOutput m REFA disableReferenceVoltageOutput REFA enableReferenceVoltage m REFA disableReferenceVoltage The internal temperature sensor is handled by m REFA disableTempSensor m REFA enableTempSensor The status of the REFA module is handled by m REFA getBandgapMode m REFA isBandgapActive m REFA isRefGenBusy 2012 08 28 4 58 17 0500 101 TI Information Selective Disclosure Internal Reference REFA 32 3 102 REFA_isRefGenActive REFA_getBufferedBandgapVoltageStatus REFA_getVariableReferenceVoltageStatus REFA_setReferenceVoltageOneTime Trigger REFA_setBufBandgapVoltageOneTimeTrigger Programming Example The following example shows how to initialize and use the REFA API with the ADC12 module to use the internal 2 5V reference and perform a single converson on channel AO The conversion results are stored in ADC12BMEMO Test by applying a voltage to channel AO then setting and running to a break point atthe __no_operation instruction To view the conversion results open an ADC12B register window in debugger and view the contents of ADC12BMEMO Set P1 0 as Ternary Module Function Output Base Address for Port 1 Select Port 1 Set Pin 0 to output Ternary Module Function A0 CO VREFA VeREFA x FRGPIO setAsPeripheralModuleFunctionOutputPin MSP430 BASEADDRESS PORTI R FRGPIO PORT P1 FRGPIO PINO FRGPIO TERNARY MODULE FUNCTION
69. channel single conversion Initialize ADC12 with ADC12 s built in oscillator ADC12 init __MSP430_BASEADDRESS_ADC12__ ADC12 SAMPLEHOLDSOURCE SC ADC12 CLOCKSOURCE ADC120SC ADC12 CLOCKDIVIDEBY 1 Switch ON ADC12 ADC12 enable MSP430 BASEADDRESS ADC12 Setup sampling timer to sample and hold for 16 clock cycles ADC12 setupSamplingTimer MSP430 BASEADDRESS ADC12 ADC12 CYCLEHOLD 64 CYCLES ADC12 CYCLEHOLD 4 CYCLES FALSE Configure the Input to the Memory Buffer with the specified Reference Voltages ADC12 memoryConfigure MSP430 BASEADDRESS ADC12 ADC12 MEMORY O0 ADC12 INPUT AO ADC12 VREF AVCC Vref ADC12 VREF AVSS Vref FALSE while 1 Start a single conversion no repeating or sequences ADC12_startConversion __MSP430_BASEADDRESS_ADC12__ ADC12 MEMORY O0 ADC12 SINGLECHANNEL Wait for the Interrupt Flag to assert while ADC12 getInterruptStatus MSP430 BASEADDRESS ADC12 ADC12IFG0 2012 08 2814 58 17 0500 TI Information Selective Disclosure 12 Bit Analog to Digital Converter ADC 12 Clear the Interrupt Flag and start another conversion ADC12_clearInterrupt __MSP430_BASEADDRESS_ADC12__ ADC12IFGO0 2012 08 2814 58 17 0500 19 TI Information Selective Disclosure 12 Bit Analog to Digital Converter ADC 12 20 TI Information Selective Disclosure 2012 08 2814 58 17 0500 6 6 1 12 Bit Analog to Digital Conve
70. cy up to 16 times the timer input clock frequency m Double buffered compare registers with synchronized loading m Interrupt vector register for fast decoding of all Timer_D interrupts Differences From Timer_B Timer_D is identical to Timer_B with the following exceptions Timer_D supports high resolution mode m Timer D supports the combination of two adjacent TDCCRx registers in one capture compare channel Timer_D supports the dual capture event mode Timer_D supports external fault input external clear input and signal See the TEC chapter for detailed information Timer_D can synchronize with a second timer instance when available See the TEC chapter for detailed information timerD can operate in 3 modes m Continuous Mode m Up Mode m Down Mode timerD Interrupts may be generated on counter overflow conditions and during capture compare events The timerD may also be used to generate PWM outputs PWM outputs can be generated by initializing the compare mode with TimerD_initCompare and the necessary parameters The 2012 08 2814 58 17 0500 133 TI Information Selective Disclosure timerD 42 2 134 PWM may be customized by selecting a desired timer mode continuous up upDown duty cy cle output mode timer period etc The library also provides a simpler way to generate PWM using TimerD generatePWM API However the level of customization and the kinds of PWM generated are limited in this API Depe
71. d etc The library also provides a simpler way to generate PWM using timerB generatePWM API However the level of customization and the kinds of PWM generated are limited in this API Depending on how complex the PWM is and what level of customization is required the user can use timerB_generatePWM or a combination of Timer initCompare and timer start APIs 2012 08 2814 58 17 0500 129 TI Information Selective Disclosure timerB 41 2 130 The timerB API provides a set of functions for dealing with the timerB module Functions are provided to configure and control the timer along with functions to modify timer counter values and to manage interrupt handling for the timer Control is also provided over interrupt sources and events Interrupts can be generated to indicate that an event has been captured This driver is contained in driverlib 5xx_6xx timerB c with driverlib 5xx_6xx timerB h containing the API definitions for use by applications API Functions The timerB API is broken into three groups of functions those that deal with timer configuration and control those that deal with timer contents and those that deal with interrupt handling TimerB configuration and initialization is handled by m TimerB_startCounter m TimerB_configureContinuousMode m TimerB_configureUpMode m TimerB_configureUpDownMode TimerB_startContinuousMode m TimerB_startUpMode m TimerB_startUpDownMode m TimerB
72. de available from the system Alternatively the power system can supply power only to other components within the system or it can be unused altogether This driver is contained in driverlib 5xx_6xx ldoPwr c with driverlib 5xx_6xx ldoPwr h containing the API definitions for use by applications API Functions The IdoPwr configuration is handled by m LDOPWR_unLockConfiguration m LDOPWR_lockConfiguration m LDOPWR enablePort U inputs m LDOPWR disablePort U inputs m LDOPWR enablePort U outputs m LDOPWR disablePort U outputs m LDOPWR_enable m LDOPWR disable m LDOPWR_enableOverloadAutoOff m LDOPWR disableOverloadAutoOff Handling the read write of output data is handled by m LDOPWR getPort U1 inputData m LDOPWR getPort UO inputData m LDOPWR getPort U1 outputData 2012 08 2814 58 17 0500 81 TI Information Selective Disclosure LDO PWR 25 3 82 LDOPWR getPort UO outputData LDOPWR getOverloadAutoOffStatus LDOPWR setPort UO outputData LDOPWR togglePort U1 outputData LDOPWR togglePort UO outputData m LDOPWR setPort U1 outputData The interrupt and status operations are handled by m LDOPWR enablelnterrupt LDOPWAR disablelnterrupt LDOPWR getlnterruptStatus LDOPWR_clearlnterruptStatus LDOPWR_isLDOInputValid LDOPWR_getOverloadAutoOffStatus Programming Example The following example shows how to use the LDO PWR API Enable access to config registers
73. detection for auto wake up from LPMx modes Status flags for error detection and suppression m Status flags for address detection m Independent interrupt capability for receive and transmit In UART mode the USCI transmits and receives characters at a bit rate asynchronous to another device Timing for each character is based on the selected baud rate of the USCI The transmit and receive functions use the same baud rate frequency This driver is contained in driverlib 5xx_6xx euart c with driverlib 5xx 6xx euart h containing the API definitions for use by applications API Functions The UART API provides the set of functions required to implement an interrupt driven UART driver The UART initialization with the various modes and features is done by the eUART_init At the end of this fucntion UART is initialized and stays disabled eUART_enable enables the UART and the module is now ready for transmit and receive It is recommended to iniailize the UART via eUART init enable the required interrupts and then enable UART via eUART enable The UART API is broken into three groups of functions those that deal with configuration and con trol of the UART modules those used to send and receive data and those that deal with interrupt handling and those dealing with DMA Configuration and control of the UART are handled by the m eUART init m eUART initAdvance m eUART enable m eUART disable 2012 08 2814 58 17 0500 57
74. dled by m REF setReference Voltage m REF enableReferenceVoltageOutput m REF disableReferenceVoltageOutput m REF enableReferenceVoltage m REF disableReferenceVoltage The internal temperature sensor is handled by m REF disableTempSensor m REF enableTempSensor The status of the REF module is handled by m REF getBandgapMode m REF isBandgapActive 2012 08 28 4 58 17 0500 97 TI Information Selective Disclosure Internal Reference REF m REF_isRefGenBusy m REF isRefGen 31 3 Programming Example The following example shows how to initialize and use the REF API with the ADC12 module to use as a positive reference to the analog signal input By default REFMSTR 1 gt REFCTL is used to configure the internal reference If ref generator busy WAIT while REF_refGenBusyStatus __MSP430_BASEADDRESS_REF__ Select internal ref 2 5V REF_setReferenceVoltage __MSP430_BASEADDRESS_REF__ REF_VREF2_5V Internal Reference ON REF_enableReferenceVoltage __MSP430_BASEADDRESS_REF__ __delay_cycles 75 Delay 75us for Ref to settle Initialize the ADC12 Module Base address of ADC12 Module Use internal ADC12 bit as sample hold signal to start conversion USE MODOSC 5MHZ Digital Oscillator as clock source Use default clock divider of 1 ADC12_init __MSP430_BASEADDRESS_ADC12_PLUS__ ADC12_SAMPLEHOLDSOURCE_SC ADC12_CLOCKSOURCE_ADC120SC ADC12 CLOCKDIVIDEBY 1 Base address of ADC12
75. e in the operation of the main and information memory sections Code and data can be located in either section The difference between the sections is the segment size There are four information memory segments A through D Each information memory segment contains 128 bytes and can be erased individually The bootstrap loader BSL memory consists of four segments A through D Each BSL memory segment contains 512 bytes and can be erased individually The main memory segment size is 512 byte See the device specific data sheet for the start and end addresses of each bank when available and for the complete memory map of a device This library provides the API for flash segment erase flash writes and flash operation status check This driver is contained in driverlib 5xx_6xx flash c with driverlib 5xx_6xx flash h containing the API definitions for use by applications 19 2 API Functions Flash_segmentErase helps erase a single segment of the flash memory A pointer to the flash segment being erased is passed on to this function Flash_eraseCheck helps check if a specific number of bytes in flash are currently erased A pointer to the starting location of the erase check and the number of bytes to be checked is passed into this function Depending on the kind of writes being performed to the flash this library provides APIs for flash writes Flash write8 facilitates writing into the flash memory in byte format Flash write16 facilitates writ
76. e SPI module are managed using m SPI disablelnterrupt m SPI enablelnterrupt m SPI getlnterruptStatus m SPI clearlnterruptFlag DMA related m SPI getReceiveBufferAddressForDMA m SPI_getTransmitBufferAddressForDMA Programming Example The following example shows how to use the SPI API to configure the SPI module as a master device and how to do a simple send of data Initialize Master returnValue SPI masterInit USCI A0 BASE SMCLK CLK getSMClk SPICLK MSB FIRST CLOCK POLARITY INACTIVITYHIGH if STATUS FAIL returnValue return Enable SPI module SPI enable USCI_AO_BASE Enable Receive interrupt SPI enableInterrupt USCI A0 BASE UCRXIE Configure port pins to reset slave Wait for slave to initialize delay cycles 100 Initialize data values transmitData 0x00 USCI A0 TX buffer ready while SPI interruptStatus USCI A0 BASE UCTXIFG Transmit Data to slave SPI transmitData USCI A0 BASE transmitData CPU off enable interrupts bis SR register LPMO bits GIE TORK RIOR HH HH HH HH HH HH KA KAZ X IRR KA X KA KA X A IR I HH k k k ke k k k k k a k This is the USCI_BO interrupt vector service routine TI Information Selective Disclosure 2012 08 2814 58 17 0500 Synchronous Peripheral Interface SPI TKK ROKR ke kk ke kk Kok kk Kok kk X AK XXX AK RRR kk ko ke IRR KA X KX KA X A IR k k K k I IR I k k K k kk a ke e
77. e a ee ee m RR RO je VEE eee a BYE eh wae 27 TEM SUIT ET ae Ka ee Be we ar ee eA ee R 27 92 salio RM ee a we ae a ee ke 27 9 3 Programming Example sa sr van ac nn ER AA 28 10 Gompatator GOMPE e sor a dore maci meak ee ee eR a ee ee ee OA ese 29 TON Sc i 3 55 4 0 a dw deh Ge he a are a Alva eke oe Ee obr Wea ew ae i c hen ce de A Bec 29 102 PAE POON D ee de de o ode A a de od Ee ware ee ee Re ce Bee ho 29 10 3 Programming Example lt o se wu ok a RR a REGE X UR R9 3 RR RU 30 11 Glock System GS unos ome ox oom a eee VE JE eee RR n ake ate 33 TEE ec a sion ke ee GAP ee Re eee we rod dy EA AR a A eR Gea Aj A wen 33 Tike FA PUNE a Pe ee a we Se we a a Vy i Ee a ae 34 11 3 Programming Example lt su eee Ee a RR Roo 9 REOR LR Rs 35 12 Glock System GSM io ci ee eee ae eh ee o Esa eas Rn sms eee Ee ee ers a 37 Tl DC DM ee Sra ae ew ee ee ee ee Pe eae eR ae ae nk A Be eon 37 122 AP POW v oca Gan dew bo uS mue dera em ee ae Xo he He Ge ke ee Ee a a oe ee ah 38 123 Programming Example sss s u ma 48 om RR eR RE RUE ee Rok ee a V a 39 13 Cyclical Redundancy Check CRC 22m 00 eee ee ee 41 Tech IMEEOHCION lt a are ee a Be Oho eee Me eee re eA E ru OR a KA a ae 41 Te AP FUNCIONE 2 a ao AE A a ae A hu 41 13 3 Programming Example 2 2 2 cu o ka go omm UR RR Oe RUSO E ERR EO 4 RR RR 41 14 12 bit Digital to Analog Converter DAC12 4 ee eee 43 SM scc NEMPE vr sna Bh zde ee Ee che ty he Re pln dod ea Be dai W
78. e c with driverlib 5xx_6xx comp_e h containing the API definitions for use by applications API Functions The COMPE API is broken into three groups of functions those that deal with initialization and output those that handle interrupts and those that handle auxillary features of the COMPE The COMPE initialization and output functions are m COMPE init m COMPE setReferenceVoltage m COMPE enable m COMPE disable m COMPE outputValue m COMPE setPowerMode The COMPE interrupts are handled by m COMPE enablelnterrupt m COMPE disablelnterrupt m COMPE clearlnterrupt m COMPE getlnterruptStatus m COMPE interruptSetEdgeDirection m COMPE interruptToggleEdgeDirection 2012 08 28 4 58 17 0500 31 TI Information Selective Disclosure Comparator COMPE Auxilary features of the COMPE are handled by m COMPE_enableShortOfInputs COMPE_disableShortOflnputs COMPE disablelnputBuffer COMPE enablelnputBuffer COMPE_lOSwap COMPE_setReferenceAccuracy COMPE_setPowerMode 10 3 Programming Example The following example shows how to initialize and use the COMPE API to turn on an LED when the input to the positive terminal is highed than the input to the negative terminal Initialize the Comparator E module Base Address of Comparator E Pin CD2 to Positive Terminal Reference Voltage to Negative Terminal Normal Power Mode Output Filter On with minimal delay Non Inverted Output Polarity COMPE_init __MSP430_BA
79. e device specific data sheet for details and contain their own respective interrupt vectors Individual ports can be accessed as byte wide ports or can be combined into word wide ports and accessed via word formats Port pairs P1 P2 P3 P4 P5 P6 P7 P8 etc are associated with the names PA PB PC PD etc respectively All port registers are handled in this manner with this naming convention except for the interrupt vector registers P1IV and P2IV that is PAIV does not exist When writing to port PA with word operations all 16 bits are written to the port When writing to the lower byte of the PA port using byte operations the upper byte remains unchanged Similarly writing to the upper byte of the PA port using byte instructions leaves the lower byte unchanged When writing to a port that contains less than the maximum number of bits possible the unused bits are a don t care Ports PB PC PD PE and PF behave similarly Reading of the PA port using word operations causes all 16 bits to be transferred to the destination Reading the lower or upper byte of the PA port P1 or P2 and storing to memory using byte operations causes only the lower or upper byte to be transferred to the destination respectively Reading of the PA port and storing to a general purpose register using byte operations causes the byte transferred to be written to the least significant byte of the register The upper significant byte of the destination register is clear
80. e with the recommended or de fault configurations or can call the APIs provided to control the parameters as the application demands Any writes to the SVSMLCTL and SVSMHCTL registers require a delay time for these registers to settle before the new settings take effect This delay time is dependent on whether the SVS and SVM modules are configured for normal or full performance See device specific data sheet for exact delay times API Functions PMM enableSvsL PMM disableSvsL Enables or disables the low side SVS circuitry PMM enableSvmL PMM disableSvmL Enables or disables the low side SVM circuitry PMM enableSvsH PMM disableSvsH Enables or disables the high side SVS circuitry 2012 08 2814 58 17 0500 TI Information Selective Disclosure Power Management Module PMM PMM_enableSVMH PMM_disableSVMH Enables or disables the high side SVM circuitry PMM_enableSvsLSvmL PMM_disableSvsLSvmL Enables or disables the low side SVS and SVM circuitry PMM_enableSvsHSvmH PMM_disableSvsHSvmH Enables or disables the high side SVS and SVM circuitry PMM_enableSvsLReset PMM_disableSvsLReset Enables or disables the POR signal gen eration when a low voltage event is registered by the low side SVS PMM_enableSvmLinterrupt PMM_disableSvmLInterrupt Enables or disables the interrupt generation when a low voltage event is registered by the low side SVM PMM_enableSvsHReset PMM_disableSvsHReset Enables
81. ective Disclosure 32 Bit Hardware Multiplier MPY32 MPY32 getResult32Bit MPY32 getResult64Bit MPY32 getSumExtension MPY32 getCarryBitValue 27 3 Programming Example 88 The following example shows how to initialize and use the MPY32 API to calculate a 16 bit by 16 bit unsigned multiplication operation WDT_hold __MSP430_BASEADDRESS_WDT_A__ Stop WDT Set a 16 bit Operand into the specific Operand 1 register to specify unsigned multiplication MPY32 setOperandOnel6Bit __MSP430_BASEADDRESS_MPY32__ MPY32 MULTIPLY UNSIGNED 0x1234 Set Operand 2 to begin the multiplication operation MPY32 setOperandTwol6Bit MSP430 BASEADDRESS MPY32 0x5678 bis SR register LPM4 bits Enter LPM4 no operation BREAKPOINT HERE to verify the correct result in the registers 2012 08 2814 58 17 0500 TI Information Selective Disclosure 28 28 1 Power Management Module PMM Power Management Module PMM WARE HON oca cic ba n od hloh O 87 PT HERES coton t Eis eb iba UE da 88 Presran nmyg Bande CT Me 90 Introduction The PMM manages the following internal circuitry m An integrated low dropout voltage regulator LDO that produces a secondary core voltage VCORE from the primary voltage that is applied to the device DVCC m Supply voltage supervisors SVS and supply voltage monitors SVM for the primary volt age DVCC and the secondary voltage VCORE The SVS and SVM incl
82. ed automatically Ports PB PC PD PE and PF behave similarly When reading from ports that contain less than the maximum bits possible unused bits are read as zeros similarly for port PJ The GPIO pin may be configured as an lO pin with GPIO_setAsOutputPin GPIO setAsInputPin GPIO setAsInputPinWithPullDownresistor or 2012 08 2814 58 17 0500 73 TI Information Selective Disclosure GPIO 23 2 23 3 74 GPIO_setAsInputPinWithPullUpresistor The GPIO pin may instead be con figured to operate in the Peripheral Module assigned function by config uring the GPIO using GPIO_setAsPeripheralModuleFunctionOutputPin or GPIO setAsPeripheralModuleFunctionlnputPin This driver is contained in driverlib 5xx 6xx gpio c With driverlib 5xx 6xx gpio h containing the API definitions for use by applications API Functions The GPIO API is broken into three groups of functions those that deal with configuring the GPIO pins those that deal with interrupts and those that access the pin value The GPIO pins are configured with m GPIO_setAsOutputPin m GPIO setAsInputPin m GPIO setAsInputPinWithPullDownresistor m GPIO setAsInputPinWithPullUpresistor m GPIO setDriveStrength m GPIO setAsPeripheralModuleFunctionOutputPin m GPIO setAsPeripheralModuleFunctionInputPin The GPIO interrupts are handled with m GPIO enablelnterrupt m GPIO disblelnterrupt m GPIO clearlnterruptFlag m GPIO getlnterruptSta
83. ee ode ke dur ra dyes cae eh Be aceon 43 pra FA POOR 2 4 2 Ge as de ba a a a ee a ee ae diode Be a A ga a S ee cache 43 14 3 Programming Example lt 2 s soo Ro komm RR RA SEX E RU Ro RR a RR RU 44 15 Direct Memory Access DMA u 20a 00 onm oy en 45 Teal MOGUCOM PCT eee A SC AR Se SA ae Da or eee es 45 Te API FUIS a ee ea a ea we ee k eee A Peta ee ae Ge eae ea eG 45 15 3 Programming Example s u eee 0 ER a AA 46 16 EUSCIInter Integrated Circuit I2C nn 47 16 1 ARENA 2 02 odo Pm 47 16 2 API Functions s osscar ko Re ER Re ae A KOB RR RU 49 16 3 Programming Example gt o se 0 0 4 5 4 Rmo Re RE ER RE a A 50 2012 08 2814 58 170500 3 TI Information Selective Disclosure Table of Contents 17 17 1 17 2 17 3 18 18 1 18 2 18 3 19 19 1 19 2 19 3 20 20 1 20 2 20 3 21 21 1 ele 21 3 22 221 22 2 22 3 23 23 1 23 2 23 3 24 24 1 24 2 24 3 25 25 1 25 2 25 3 26 26 1 26 2 26 3 27 27 1 21 2 27 3 28 28 1 28 2 28 3 29 29 1 29 2 29 3 30 30 1 30 2 30 3 31 31 1 31 2 31 3 32 32 1 32 2 EUSCI Synchronous Peripheral Interface SPI lt lt ooo nn 51 ges lt orcos sos pati AA ARA A AAA 51 COS RENS es ce GE a O A axe a peas ake Ge epee gach tm dera nde USE Acond a aA a an AERE t 51 Programming EXAME E RN 52 EUSCIUARE 20000 rs a a A A A E Seo Un 55 l gil s s ici RA A A ee ee 55 A E A Bol Be d l og es 55 Programing EXaMPIE
84. eral TimerA features include m Asynchronous 16 bit timer counter with four operating modes m Selectable and configurable clock source m Up to seven configurable capture compare registers Configurable outputs with pulse width modulation PWM capability m Asynchronous input and output latching m Interrupt vector register for fast decoding of all Timer interrupts TimerA can operate in 3 modes m Continuous Mode m Up Mode m Down Mode TimerA Interrupts may be generated on counter overflow conditions and during capture compare events The timerA may also be used to generate PWM outputs PWM outputs can be generated by initializing the compare mode with TimerA initCompare and the necessary parameters The PWM may be customized by selecting a desired timer mode continuous up upDown duty cy cle output mode timer period etc The library also provides a simpler way to generate PWM using TimerA generatePWM API However the level of customization and the kinds of PWM generated are limited in this API Depending on how complex the PWM is and what level of customization is required the user can use TimerA generatePWM or a combination of Timer initCompare and timer start APIs The timerA API provides a set of functions for dealing with the timerA module Functions are provided to configure and control the timer along with functions to modify timer counter values and to manage interrupt handling for the timer Control is also pr
85. essage 16Bit m SYS_setJTAGOutgoingMessage32Bit m SYS_clearJTAGMailboxFlagStatus 36 3 Programming Example 114 The following example shows how to initialize and use the SFR API do Clear XT2 XT1 DCO fault flags UCS_clearFaultFlag __MSP430_BASEADDRESS_UCS__ UCS_XT2OFFG UCS_XTIHFOFFG UCS XTILFOFFG UCS DCOFFG i Clear SFR Fault Flag SFR clearInterrupt __MSP430_BASEADDRESS_SFR__ OFIFG Test oscillator fault flag Jwhile SFR getInterruptStatus __MSP430_BASEADDRESS_SFR__ OFIFG 2012 08 2814 58 17 0500 TI Information Selective Disclosure 37 37 1 37 2 Synchronous Peripheral Interface SPI Synchronous Peripheral Interface SPI OU creo Rab koho ori aa Momence OR bob dad ddd oa adotta ado done ac da rd Ea dod 113 IAS A na Eabb ical E ov so boob a d ped eater MU o o date 113 Peca MACH Bande ann 114 Introduction The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode Devices communicate in master slave mode where the master device initiates the data frame This library provides the API for handling a 3 wire SPI communication The SPI module can be configured as either a master or a slave device The SPI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module s input clock This driver is contained in driverlib 5xx 6xx spi c
86. external clear signals m Support of external fault input signals m Interrupt vector generation of external fault and clear signals Generating feedback signals to the Timer capture compare channels to affect the timer outputs This driver is contained in driverlib 5xx 6xx tec c with driverlib 5xx 6xx tec h containing the API definitions for use by applications API Functions The tec configuration is handled by m TEC configureExternalClearlnput m TEC configureExternalFaultInput m TEC enableExternalFaultInput m TEC disableExternalFaultInput m TEC enableExternalClearlnput m TEC disableExternalClearlnput m TEC enableAuxiliaryClearSignal m TEC disableAuxiliaryClearSignal The interrupt and status operations are handled by m TEC enableExternalFaultInput m TEC disableExternalFaultInput m TEC clearlnterruptFlag m EC getlnterruptStatus 2012 08 2814 58 17 0500 119 TI Information Selective Disclosure TEC m TEC_enablelnterrupt m TEC disablelnterrupt m TEC getExternalFaultStatus m TEC clearExternalFaultStatus m TEC getExternalClearStatus m TEC clearExternalClearStatus 38 3 Programming Example The following example shows how to use the TEC API TimerD_startCounter __MSP430_BASEADDRESS_T1D3__ TIMERD_UP_MODE Configure TD1 TEC External Clear Need to physically connect P2 0 TD0 2 to P2 7 TECICLR GPIO setAsPeripheralModuleFunctionInputPin MSP430 BASEADDRESS PORT2 R
87. f LDOPWR_getInterruptStatus __MSP430_BASEADDRESS_PU__ LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT Enable access to config registers LDOPWR_unLockConfiguration __MSP430_BASEADDRESS_PU__ Software clear IFG LDOPWR_clearInterruptStatus __MSP430_BASEADDRESS_PU__ LDOPWR_LDO_OVERLOAD_INDICATION_INTERRUPT i Disable access to config registers LDOPWR lockConfiguration MSP430 BASEADDRESS PU Over load indication take necessary steps in application firmware while 1 2012 08 2814 58 17 0500 83 TI Information Selective Disclosure LDO PWR 84 TI Information Selective Disclosure 2012 08 2814 58 17 0500 26 26 1 26 2 Memory Protection Unit MPU Memory Protection Unit MPU Ulea Me vice nation Zoe UNE idol eai a dbd cod lod do c dt x ac o e p n dal 83 PT PO ROT coron pis ab iba a is do 83 Presran nmyg DNE CT eT 84 Introduction The MPU protects against accidental writes to designated read only memory segments or execu tion of code from a constant memory segment memory Clearing the MPUENA bit disables the MPU making the complete memory accessible for read write and execute operations After a BOR the complete memory is accessible without restrictions for read write and execute opera tions MPU features include m Main memory can be configured up to three segments of variable size m Access rights for each segment can be set independently m Inform
88. fy slave address el2C setSlaveAddress MSP430 BASEADDRESS EUSCI BO SLAVE ADDRESS i Set in transmit mode eI2C setMode __MSP430_BASEADDRESS_EUSCI_BO__ eI2C TRANSMIT MODE i Enable I2C Module to start operations eI2C_enable __MSP430_BASEADDRESS_EUSCI_BO__ while 1 Send single byte data el2C masterSendSingleByte MSP430 BASEADDRESS EUSCI BO transmitData i Delay until transmission completes while eI2C_isBusBusy __MSP430_BASEADDRESS_EUSCI_BO__ Delay between each transaction __delay_cycles 50 Increment transmit data counter transmitData 52 2012 08 2814 58 17 0500 TI Information Selective Disclosure 17 17 1 17 2 EUSCI Synchronous Peripheral Interface SPI EUSCI Synchronous Peripheral Interface SPI KINTENBHON 2 24 NOT EET TNT TT TET a O O R O OR V O PO NO O O O P ee 51 ArI EOC NO RE PR RO T OP VO O O O O T O O S ER O O Re 51 Programming Exame a ee 52 Introduction The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode Devices communicate in master slave mode where the master device initiates the data frame This library provides the API for handling a SPI communication using EUSCI The SPI module can be configured as either a master or a slave device The SPI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived fro
89. g to Digital Converter ADC12 MRT BON lk Bander Bo hloh dod pk k oko dod ko oo r k cA eee tee estas 15 SUPE HEROS C octava PE n o wa au rau AE o UE cad E PESE 15 Prez Bande sehe 16 Introduction The 12 Bit Analog to Digital ADC12 API provides a set of functions for using the MSP430Ware ADC12 modules Functions are provided to initializae the ADC12 modules setup signal sources and reference voltages for each memory buffer and manage interrupts for the ADC12 modules The ADC12 module provides the ability to convert analog signals into a digital value in respect to given reference voltages The ADC12 can generate digital values from 0 to Vcc with an 8 10 or 12 bit resolution with 16 different memory buffers to store conversion results It operates in 2 different sampling modes and 4 different conversion modes The sampling modes are extended sampling and pulse sampling in extended sampling the sample hold signal must stay high for the duration of sampling while in pulse mode a sampling timer is setup to start on a rising edge of the sample hold signal and sample for a specified amount of clock cycles The 4 conversion modes are single channel single conversion sequence of channels single conversion repeated single channel conversions and repeated sequence of channels conversions The ADC12 module can generate multiple interrupts An interrupt can be asserted for each memory buffer when a conversion is complete or when a conversion is abou
90. gh side SVS SVSH is disabled in LPM4 5 SVSH is always enabled in active mode and LPM0 1 2 3 4 and LPM3 5 If enabled SVSH is always enabled Note this API has different functionality depending on the part FRPMM_enableSVSL FRPMM_disableSVSL If disabled Low side SVS SVSL is disabled in low power modes SVSL is always enabled in active mode and LPMO If enabled SVSL is enabled in LPMO 1 2 SVSL is always enabled in AM and always disabled in LPM3 4 and LPM3 5 4 5 Note not available on FR58xx 59xx devices FRPMM_regOff FRPMM_regOn If off Regulator is turned off when going to LPM3 4 System enters LPM3 5 or LPM4 5 respectively If on Regulator remains on when going into LPM3 4 FRPMM_clearinterrupt Clear selected or all interrupt flags for the FRPMM FRPMM_getinterruptStatus Returns interrupt status of the selected flag in the FRPMM module FRPMM_lockLPM5 FRPMM_unlockLPM5 If unlocked LPMx 5 configuration is not locked and defaults to its reset condition if locked LPMx 5 configuration remains locked Pin state is held during LPMx 5 entry and exit This driver is contained in driverlib 5xx_6xx frpmm c with driverlib 5xx_6xx frpmm h containing the API definitions for use by applications 2012 08 2814 58 17 0500 69 TI Information Selective Disclosure Power Management Module FRPMM 22 3 Programming Example 70 The following example shows some pmm operations using the APIs Unlock the B
91. illator DCOCLKDIV This is true for all clock sources except the LFXT1 As previously described a fault on the LFXT1 switches the source to the REFO Since ACLK is the active clock in LPMS there is a notable difference in the LPM3 current consumption when the REFO is the clock source 3 pA active versus the LFXT1 300 nA active m Modules WDT A In watchdog mode when SMCLK or ACLK fails the clock source defaults to the VLOCLK This driver is contained in driverlib 5xx 6xx ucs c With driverlib 5xx 6xx ucs h containing the API definitions for use by applications API Functions The UCS API is broken into three groups of functions those that deal with clock configuration and control General UCS configuration and initialization is handled by m UCS clockSignallnit m UCS initFLL Settle m UCS enableClockRequest m UCS disableClockRequest m UCS_SMCLKOff m UCS_SMCLKOn External crystal specific configuration and initialization is handled by m UCS setExternalClockSource m UCS LFXTt1Start m UCS HFXT1Start m UCS bypassXT1 m UCS LFXT1StartWithTimeout m UCS_HFXT1StartWithTimeout m UCS bypassXT1WithTimeout m UCS XT10Off m UCS XT2Start m UCS XT20ff m UCS bypassXT2 m UCS XT2StartWithTimeout 2012 08 2814 58 17 0500 TI Information Selective Disclosure 45 3 Unified Clock System UCS m UCS bypassXT2WithTimeout m UCS clearAllOscFlagsWithTimeout UCS set
92. imerA clearCaptureComparelnterruptFlag m TimerA clearTimerlnterruptFlag 40 3 Programming Example The following example shows some timerA operations using the APIs 126 2012 08 2814 58 17 0500 TI Information Selective Disclosure TimerA Start TimerA TimerA configureUpDownMode __MSP430_BASEADDRESS_T1A3__ TIMERA_CLOCKSOURCE_SMCLK TIMERA_CLOCKSOURCE_DIVIDER_1 TIMER_PERIOD TIMERA_TAIE_INTERRUPT_DISABLE TIMERA_CCIE_CCRO_INTERRUPT_DISABLE TIMERA_DO_CLEAR i TimerA startCounter __MSP430_BASEADDRESS_T1A3__ TIMERA UPDOWN MODE Initialze compare registers to generate PWM1 TimerA_initCompare __MSP430_BASEADDRESS_T1A3__ TIMERA CAPTURECOMPARE REGISTER 1 TIMERA CAPTURECOMPARE INTERRUPT ENABLE TIMERA OUTPUTMODE TOGGLE SET DUTY CYCLE i Initialze compare registers to generate PWM2 TimerA_initCompare __MSP430_BASEADDRESS_T1A3__ TIMERA_CAPTURECOMPARE_REGISTER_2 TIMERA_CAPTURECOMPARE_INTERRUPT_DISABLE TIMERA_OUTPUTMODE_TOGGLE_SET DUTY_CYCLE2 i Enter LPMO __bis_SR_register LPMO_bits For debugger no operation 2012 08 2814 58 17 0500 127 TI Information Selective Disclosure TimerA 128 2012 08 2814 58 17_0500 TI Information Selective Disclosure 41 41 1 timerB timerB A dokon TTE 127 ARCAS A aun MU cR ic Ceca 128 Peca MCH Bande anne 129 Introduction timerB is a 16 bit timer counter with multiple capture compare registers timerB can support mul
93. imerD disableHighResFastWakeup m TimerD_enableHighResFastWakeup m limerD disableHighResClockEnhancedAccuracy m TimerD_enableHighResClockEnhancedAccuracy m limerD DisableHighResGeneratorForceON m TimerD EnableHighResGeneratorForceON m TimerD_selectHighResCoarseClockRange m TimerD_selectHighResClockRange m limerD configureHighResGeneratorlnFreeRunningMode m TimerD configureHighResGeneratorlnRegulatedMode 2012 08 2814 58 17 0500 135 TI Information Selective Disclosure timerD 42 3 Programming Example The following example shows some TimerD operations using the APIs Start TimerD TimerD configureUpDownMode __MSP430_BASEADDRESS_T1A3__ TimerD_CLOCKSOURCE_SMCLK TimerD_CLOCKSOURCE_DIVIDER_1 TIMER_PERIOD TimerD TAIE INTERRUPT DISABLE TimerD CCIE CCRO INTERRUPT DISABLE TimerD DO CLEAR i TimerD startCounter __MSP430_BASEADDRESS_T1A3__ TimerD UPDOWN MODE Initialze compare registers to generate PWM1 TimerD_initCompare __MSP430_BASEADDRESS_T1A3__ TimerD CAPTURECOMPARE REGISTER 1 TimerD CAPTURECOMPARE INTERRUPT ENABLE TimerD OUTPUTMODE TOGGLE SET DUTY CYCLE i Initialze compare registers to generate PWM2 TimerD initCompare MSP430 BASEADDRESS T1A3 TimerD CAPTURECOMPARE REGISTER 2 TimerD CAPTURECOMPARE INTERRUPT DISABLE TimerD OUTPUTMODE TOGGLE SET D UTY CYCLE2 Enter LPMO bis SR register LPMO bits For debugger no oper
94. ing into the flash memory in word format Flash write32 facilitates writing into the flash memory in long format pass by reference Flash memoryFill32 facilitates writing into the flash memory in long format pass by value Flash status checks if the flash is currently busy erasing or programming The Flash API is broken into 3 groups of functions those that deal with flash erase those that write into flash and those that give status of flash The flash erase operations are managed by m Flash segmentErase m Flash eraseCheck m Flash bankErase 2012 08 2814 58 17 0500 61 TI Information Selective Disclosure Flash Memory Controller 19 3 62 Flash writes are managed by The Flash_write8 Flash_write16 Flash_write32 Flash_memoryFill32 status is given by Flash_status Flash_eraseCheck Programming Example The do following example shows some flash operations using the APIs Flash segmentErase MSP430 BASEADDRESS FLASH unsigned char INFOD START i status Flash_eraseCheck __MSP430_BASEADDRESS_FLASH__ unsigned char x INFOD START 128 i Jwhile status STATUS FAIL Flash write Flash write32 MSP430 BASEADDRESS FLASH calibration data unsigned long x INFOD START 1 TI Information Selective Disclosure 2012 08 2814 58 17 0500 20 20 1 20 2 FRAM Controller FRAM Controller ICA vice csset nd do b dod ko eko ater dok E Nd aa aca M bata do by RU RA 61 SUPE ROT SC
95. ing example shows some AES operations using the APIs unsigned char Data 16 0x30 0x31 0x32 0x33 0x34 0x35 0x38 0x39 OxOC Ox0D unsigned char CipherKey 16 OxAA OxBB 0x02 0x03 0x04 0x05 0x08 0x09 OxOC Ox0D unsigned char DataAES 16 Encrypted data unsigned char DataunAES 16 Decrypted data Load a cipher key to module AES_setCipherKey __MSP430_BASEADDRESS_AES__ CipherKey Encrypt data with preloaded cipher key AES encryptData MSP430 BASEADDRESS AES Data DataAES Decrypt data with keys that were generated during encryption takes 214 MCLK This function will generate all round keys needed for decryption first and then the encryption process starts AES decryptDataUsingEncryptionKey MSP430 BASEADDRESS AES DataAES DataunAES 2012 08 2814 58 17 0500 TI Information Selective Disclosure 0x36 Ox0A OxOE 0x06 Ox0A OxOE 0x37 Ox0B 0x0F 0x07 Ox0B OxOF 8 1 8 2 Comparator COMPB Comparator COMPB Ll eMe HON EEE RUN ho t dod ane ruta ftot doe d dokn dint dds tac o E bp Dp RR ud 25 AEI ROT rer 25 lai ccn n po DNE sn nee 26 Introduction The Comparator B COMPB API provides a set of functions for using the MSP430Ware COMPB modules Functions are provided to initialize the COMPB modules setup reference voltages for input and manage interrupts for the COMPB modules The COMPB module provides the ability to compare two analog signals a
96. init __MSP430_BASEADDRESS_DMAX_3__ A CHANNEL 0 A TRANSFER REPEATED BLOCK RIGGERSOURCE 0 IZE SRCWORD DSTWORD RIGGER RISINGEDGE LJ o du tu SS Doo HUH Base Address of the DMA Module Configure DMA channel 0 Use 0x1C00 as source Increment source address after every transfer DMA_setSrcAddress __MSP430_BASEADDRESS_DMAX_3__ DMA CHANNEL 0 0x1C00 DMA DIRECTION INCREMENT Base Address of the DMA Module Configure DMA channel 0 Use 0x1C20 as destination Increment destination address after every transfer DMA_setDstAddress __MSP430_BASEADDRESS_DMAX_3__ DMA CHANNEL 0 0x1C20 DMA_DIRECTION_INCREMENT Enable transfers on DMA channel 0 DMA_enableTransfers __MSP430_BASEADDRESS_DMAX_3__ DMA CHANNEL 0 while 1 Start block tranfer on DMA channel 0 DMA_startTransfer __MSP430_BASEADDRESS_DMAX_3__ DMA CHANNEL 0 TI Information Selective Disclosure 2012 08 2814 58 170500 16 16 1 16 1 1 EUSCI Inter Integrated Circuit I2C EUSCI Inter Integrated Circuit I2C IPR rra bd wok dabit dod ao did dco d p dora dcin t do due afa eau Lo RE bp D Rd EU d 47 TTE O ROT S coton pais ah Se o UE Ras rM MM EIU QS D Edda 49 Predam Bande CT r m 50 Introduction In I2C mode the eUSCI B module provides an interface between the device and I2C compatible devices connected by the two wire 12C serial bus External components attached to the I
97. ion by configuring the FRGPIO using FRGPIO_setAsPeripheralModuleFunctionOutputPin or FRG PIO_setAsPeripheralModuleFunctionInputPin This driver is contained in driverlib 5xx_6xx frgpio c with driverlib 5xx_6xx frgpio h containing the API definitions for use by applications API Functions The FRGPIO API is broken into three groups of functions those that deal with configuring the FRGPIO pins those that deal with interrupts and those that access the pin value The FRGPIO pins are configured with m FRGPIO_setAsOutputPin m FRGPIO_setAsInputPin m FRGPIO_setAsInputPinWithPullDownresistor m FRGPIO_setAsInputPinWithPullUpresistor FRGPIO setAsPeripheralModuleFunctionOutputPin m FRGPIO setAsPeripheralModuleFunctionInputPin The FRGPIO interrupts are handled with m FRGPIO enablelnterrupt m FRGPIO disblelnterrupt FRGPIO clearlnterruptFlag FRGPIO getlnterruptStatus FRGPIO interruptEdgeSelect The FRGPIO pin state is accessed with FRGPIO setOutputHighOnPin FRGPIO setOutputLowOnPin FRGPIO toggleOutputOnPin m FRGPIO getlnputPin Value Programming Example The following example shows how to use the FRGPIO API A trigger is generated on a hi TO low transition on P1 4 pulled up input pin which will generate P1 ISR In the ISR we toggle P1 0 output pin 2012 08 28 4 58 17 0500 TI Information Selective Disclosure FRGPIO Set P1 0 to output direction FRGPIO_setAsOutputPin __MSP4
98. itData MSP430 BASEADDRESS EUSCI AO TXData while check 1 check 0 J f kk kk ROR HH HH HH IRR IR KA X A OR IR HH I IR ke kk k ke ke k This is the USCI_AO interrupt vector service routine J f kk kk ke kk ko ke HH kk Kok HH KA X IRR RR AXA HH RI IR I IO I I I ke ke k pragma vector USCI A0 VECTOR interrupt void USCI A0 ISR void switch __even_in_range UCAOIV USCI_UART_UCTXCPTIFG case USCI_UART_UCRXIFG RXData eUART_receiveData __MSP430_BASEADDRESS_EUSCI_AO__ f RXData TXData Check value F while 1 check 1 break 2012 08 2814 58 17_0500 TI Information Selective Disclosure 59 EUSCI UART 60 TI Information Selective Disclosure 2012 08 2814 58 170500 Flash Memory Controller 19 Flash Memory Controller gist Ns Me Ecol eee eek eee ee ene Tee tr tee Ter eer Te ree Ter Teer eT et eT Tree re eT rer eT Te 59 APLFINENONS en 59 Prosa Bande ss nee 60 19 1 Introduction The flash memory is byte word and long word addressable and programmable The flash memory module has an integrated controller that controls programming and erase operations The flash main memory is partitioned into 512 byte segments Single bits bytes or words can be written to flash memory but a segment is the smallest size of the flash memory that can be erased The flash memory is partitioned into main and information memory sections There is no differenc
99. itialize the I2C modules to send and receive data obtain status and to manage interrupts for the I2C modules The I2C module provide the ability to communicate to other IC devices over an I2C bus The I2C bus is specified to support devices that can both transmit and receive write and read data Also devices on the I2C bus can be designated as either a master or a slave The MSP430Ware I2C modules support both sending and receiving data as either a master or a slave and also support the simultaneous operation as both a master and a slave Finally the MSP430Ware I2C modules can operate at two speeds Standard 100 kb s and Fast 400 kb s 12 module can generate interrupts The I2C module configured as a master will generate interrupts when a transmit or receive operation is completed or aborted due to an error The I2C module configured as a slave will generate interrupts when data has been sent or requested by a master Master Operations To drive the master module the APIs need to be invoked in the following order m I2C masterlnit I2C setSlaveAddress I2C setMode I2C enable m I2C enablelnterrupt if interrupts are being used This may be followed by the APIs for transmit or receive as required The user must first initialize the I2C module and configure it as a master with a call to I2C masterlnit That function will set the clock and data rates This is followed by a call to set the slave address with which the master in
100. k System CSA JEDE rra rs dada kde kdo aden do E Nd aa cM te I bp Dp ERE 37 AAN ed no do ene l da 38 Presran nmyg Bande see 39 Introduction The clock system module supports low system cost and low power consumption Using three inter nal clock signals the user can select the best balance of performance and low power consumption The clock module can be configured to operate without any external components with one or two external crystals or with resonators under full software control The clock system module includes the following clock sources m LFXTCLK Low frequency oscillator that can be used either with low frequency 32768 Hz watch crystals standard crystals resonators or external clock sources in the 50 kHz or below range When in bypass mode LFXTCLK can be driven with an external square wave signal m VLOCLK Internal very low power low frequency oscillator with 10 kHz typical frequency m DCOCLK Internal digitally controlled oscillator DCO with selectable frequencies m MODCLK Internal low power oscillator with 5 MHz typical frequency LFMODCLK is MOD CLK divided by 128 m HFXTCLK High frequency oscillator that can be used with standard crystals or resonators in the 4 MHz to 24 MHz range When in bypass mode HFXTCLK can be driven with an external square wave signal Four system clock signals are available from the clock module m ACLK Auxiliary clock The ACLK is software selectable as LFXTCLK VLOCLK or
101. le conversion repeated single channel conversions and repeated sequence of channels conversions The ADC12B module can generate multiple interrupts An interrupt can be asserted for each mem ory buffer when a conversion is complete or when a conversion is about to overwrite the converted data in any of the memory buffers before it has been read out and or when a conversion is about to start before the last conversion is complete ADC12 B features include m 200 ksps maximum conversion rate at maximum resolution of 12 bits m Monotonic 12 bit converter with no missing codes m Sample and hold with programmable sampling periods controlled by software or timers m Conversion initiation by software or timers Software selectable on chip reference voltage generation 1 2 V 2 0 V or 2 5 V with option to make available externally m Software selectable internal or external reference m Up to 32 individually configurable external input channels single ended or differential input selection available m Internal conversion channels for internal temperature sensor and 2 3 x AVCC and four more internal channels available on select devices see device data sheet for availability as well as function m Independent channel selectable reference sources for both positive and negative references m Selectable conversion clock source 2012 08 2814 58 17 0500 21 TI Information Selective Disclosure 12 Bit Analog to Digital Converter ADC 12B
102. m the module s input clock This driver is contained in driverlib 5xx_6xx espi c with driverlib 5xx_6xx espi h containing the API definitions for use by applications API Functions To use the module as a master the user must call eSPI masterlnit to configure the SPI Mas ter This is followed by enabling the SPI module using eSPI enable The interrupts are then enabled if needed It is recommended to enable the SPI module before enabling the interrupts A data transmit is then initiated using eSPI_transmitData and then when the receive flag is set the received data is read using eSPI_receiveData and this indicates that an RX TX operation is complete To use the module as a slave initialization is done using eSPI_slavelnit and this is followed by enabling the module using eSPI_enable Following this the interrupts may be enabled as needed When the receive flag is set data is first transmitted using eSPI transmitData and this is followed by a data reception by eSPI_receiveData The SPI API is broken into 3 groups of functions those that deal with status and initialization those that handle data and those that manage interrupts The status and initialization of the SPI module are managed by m eSPI masterlnit m eSPI_slavelnit eSPI disable eSPI enable eSPI masterChangeClock eSPI isBusy 2012 08 2814 58 17 0500 53 TI Information Selective Disclosure EUSCI Synchronous Peripheral Interface SPI 1
103. mController_getSectorState Get RAM sector ON OFF status Programming Example The following example shows some RAM Controller operations using the APIs Start timer Timer startUpMode MSP430 BASEADDRESS TOB7 TIMER CLOCKSOURCE ACIK TIMER CLOCKSOURCE DIVIDER 1 25000 TIMER TAIE INTERRUPT DISABLE TIMER CAPTURECOMPARE INTERRUPT ENABLE TIMER DO CLEAR i RAM controller sector off ramController_setSectorOff __MSP430_BASEADDRESS_RC__ RAMCONTROL_SECTOR2 Y Enter LPMO enable interrupts __bis_SR _ register LPM3_bits GIE 2012 08 2814 58 17 0500 95 TI Information Selective Disclosure RAM Controller For debugger no operation J f kk kk k k kk k kk kk HH kk kk X A kk X AK kk ko kk X KA kk X A IR OR kk Kok kk ko ke kk Ke ke ke ke This is the Timer Lil J k kkk kkk k kk KK k k k k k pragma vector TIMER interrupt void TIM BO interrupt vector service routine BO_VECTOR ERBO_ISR void Ck ck ck ck ck ck ck ck KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKKKKKKKKKKKKKK returnValue ramController_getSectorState __MSP430_BASEADDRESS_RC__ RAMCONTROL_S RAMCONTROL_S ECTORO ECTOR1 RAMCONTROL_SECTOR2 RAMCONTROL_S ECTOR3 96 TI Information Selective Disclosure 2012 08 2814 58 170500 31 31 1 31 2 Internal Reference REF Internal Reference REF IRE TD HON lk band Pon nO 95 A pais abr ibat UE x Ra rM MEM CLE IU
104. me Clock RTCc Real Time Clock RTC A DP RF de WEE Et cce a o o uo ha Bl Bb bobo 107 APIBHDCHONS eiii AS 107 Programing Example ozon ds er NA RA AA AAA A 108 Introduction The Real Time Clock RTC_C API provides a set of functions for using the MSP430Ware RTC_C modules Functions are provided to calibrate the clock initialize the RTC_C modules in Calendar mode and setup conditions for and enable interrupts for the RTC_C modules The RTC C module provides the ability to keep track of the current time and date in calendar mode The RTC_C module generates multiple interrupts There are 2 interrupts that can be defined in calendar mode and 1 interrupt in counter mode for counter overflow as well as an interrupt for each prescaler This driver is contained in driverlib 5xx_6xx rtc_c c with driverlib 5xx_6xx rtc_c h containing the API definitions for use by applications API Functions The RTC C API is broken into 4 groups of functions clock settings calender mode counter mode and interrupt condition setup and enable functions The RTC_C clock settings are handled by m RTCC startClock m RTCC holdClock m RTCC setCalibrationFreguency m RTCC setCalibrationData m RTCC setTemperatureCompensation The RTC C Calender Mode is initialized and setup by m RTCC_calenderlnit m RTCC getCalenderTime m RTCC getPrescaleValue m RTCC setPrescaleValue The RTC C interrupts are handled by m RTCC setCalenderAlarm m RTCC setCalende
105. ments in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 reguirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio A Data Converters dataconverter ti com Automotive amu ticomibroadband DLP Products NA OD CUM Broadband www ti com digitalcontrol DSP dsp ti com Digital Control Clocks and Timers www ti com clocks Medical INMENSO UM Interface interface ti com Military Yewicti com military Logic logic ti com Optical Networking www ti com opticalnetwork Power Mgmt power ti com Security www ti com security Microcontrollers microcontroller ti com Telephony www ti com telephony RFID www ti rfid com Video amp Imaging www ti com video RF IF and ZigBee Solutions www ti com Iprf Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2012 Texas Instruments Incorporated 150 2012 08 2814 58 17 0500 TI Information Selective Disclosure
106. n Selective Disclosure 27 27 1 27 2 32 Bit Hardware Multiplier MPY32 32 Bit Hardware Multiplier MPY32 IPT rra is dod age aces Giada nade dane dk cde f abdo EE b n RE d 85 PE O ROT so od n o a a l ad MM o IE ln LUE 85 Prez MEK DE ss nee 86 Introduction The 32 Bit Hardware Multiplier MPY32 API provides a set of functions for using the MSP430Ware MPY32 modules Functions are provided to setup the MPY32 modules set the operand registers and obtain the results The MPY32 Modules does not generate any interrupts This driver is contained in driverlib 5xx 6xx mpy32 c with driverlib 5xx 6xx mpy32 h containing the API definitions for use by applications API Functions The MPY32 API is broken into three groups of functions those that control the settings those that set the operand registers and those that return the results sum extension and carry bit value The settings are handled by MPY32 setWriteDelay MPY32 setSaturationMode MPY32 resetSaturationMode MPY32 setFractionMode MPY32 resetFractionMode The operand registers are set by m MPY32_setOperandOne8Bit m MPY32 setOperandOne1 6Bit m MPY32 setOperandOne24Bit m MPY32 setOperandOne32Bit m MPY32 setOperandTwo8Bit m MPY32 setOperandTwo16Bit m MPY32 setOperandTwo24Bit m MPY32 setOperandTwo32Bit The results can be returned by m MPY32 getResult8Bit m MPY32 getResulti6Bit m MPY32 getResult24Bit 2012 08 2814 58 17 0500 87 TI Information Sel
107. n modes are single channel single conversion sequence of channels single conversion repeated single channel conversions and repeated sequence of channels conversions The ADC10 module can generate multiple interrupts An interrupt can be asserted when a conversion is complete when a conversion is about to overwrite the converted data in the memory buffer before it has been read out and or when a conversion is about to start before the last conversion is complete The ADC10 also has a window comparator feature which asserts interrupts when the input signal is above a high threshold below a low threshold or between the two at any given moment This driver is contained in driverlib 5xx 6xx adc10 c With driverlib 5xx 6xx adc10 h containing the API definitions for use by applications API Functions The ADC10 API is broken into three groups of functions those that deal with initialization and conversions those that handle interrupts and those that handle auxillary features of the ADC10 The ADC10 initialization and conversion functions are m ADC10 init m ADC10 memoryConfigure m ADC10 setupSamplingTimer m ADC10 disableSamplingTimer m ADC10 setWindowComp m ADC10 startConversion m ADC10 disableConversions m ADC10 getResults m ADC10 isBusy The ADC10 interrupts are handled by m ADC10 enablelnterrupt m ADC10 disablelnterrupt m ADC10 clearlnterrupt m ADC10 getlnterruptStatus Auxilary features of the ADC10 are handled by m
108. nd destination addresses manage the interrupts for each channel and set bits that affect all DMA channels The DMA module provides the ability to move data from one address in the device to another and that includes other peripheral addresses to RAM or vice versa all without the actual use of the CPU Please be advised that the DMA module does halt the CPU for 2 cycles while transfering but does not have to edit any registers or anything The DMA can transfer by bytes or words at a time and will automatically increment or decrement the source or destination address if desired There are also 6 different modes to transfer by including single transfer block transfer and burst block transfer as well as repeated versions of those three different kinds which allows transfers to be repeated without having re enable transfers The DMA settings that affect all DMA channels include prioritization from a fixed priority to dynamic round robin priority Another setting that can be changed is when transfers occur the CPU may be in a read modify write operation which can be disasterous to time sensitive material so this can be disabled And Non Maskable Interrupts can indeed be maskable to the DMA module if not enabled The DMA module can generate one interrupt per channel The interrupt is only asserted when the specified amount of transfers has been completed With single transfer this occurs when that many single transfers have occured while with
109. nd use the output in software and on an output pin The output represents whether the signal on the positive terminal is higher than the signal on the negative terminal The COMPB may be used to generate a hysteresis There are 16 different inputs that can be used as well as the ability to short 2 input together The COMPB module also has control over the REF module to generate a reference voltage as an input The COMPB module can generate multiple interrupts An interrupt may be asserted for the output with seperate interrupts on whether the output rises or falls This driver is contained in driverlib 5xx 6xx compb c with driverlib 5xx 6xx compb h containing the API definitions for use by applications API Functions The COMPB API is broken into three groups of functions those that deal with initialization and output those that handle interrupts and those that handle auxillary features of the COMPB The COMPB initialization and output functions are m COMPB init m COMPB setReferenceVoltage m COMPB enable m COMPB disable m COMPB outputValue The COMPB interrupts are handled by m COMPB enablelnterrupt COMPB disablelnterrupt m COMPB clearlnterrupt m COMPB getlnterruptStatus m COMPB interruptSetEdgeDirection m COMPB interruptToggleEdgeDirection Auxilary features of the COMPB are handled by 2012 08 2814 58 17 0500 27 TI Information Selective Disclosure Comparator COMPB COMPB enableShortOflnputs COMPB di
110. nding on how complex the PWM is and what level of customization is required the user can use TimerD_generatePWM or a combination of TimerD_initCompare and timer start APIs The TimerD API provides a set of functions for dealing with the TimerD module Functions are provided to configure and control the timer along with functions to modify timer counter values and to manage interrupt handling for the timer Control is also provided over interrupt sources and events Interrupts can be generated to indicate that an event has been captured This driver is contained in driverlib 5xx_6xx timerd c with driverlib 5xx_6xx timerd h containing the API definitions for use by applications API Functions The TimerD API is broken into three groups of functions those that deal with timer configuration and control those that deal with timer contents and those that deal with interrupt handling TimerD configuration and initialization is handled by TimerD_startCounter m TimerD_configureContinuousMode m TimerD_configureUpMode m TimerD_configureUpDownMode m TimerD_startContinuousMode m TimerD_startUpMode m TimerD startUpDownMode m TimerD_initCapture m limerD initCompare m TimerD clear m TimerD stop m limerD configureHighResGeneratorlnFreeRunningMode m TimerD_configureHighResGeneratorInRegulatedMode m TimerD_combineTDCCRToGeneratePWM m TimerB_selectLatchingGroup m TimerD_selectCounterLe
111. nformation Selective Disclosure 12 Bit Analog to Digital Converter ADC 12B 6 3 Programming Example The following example shows how to initialize and use the ADC12B API to start a single channel with single conversion using an external positive reference for the ADC12B Initialize the ADC12 Module Base address of ADC12 Module Use internal ADC12 bit as sample hold signal to start conversion USE MODOSC 5MHZ Digital Oscillator as clock source Use default clock divider pre divider of 1 Map to internal channel 0 ADC12B_init __MSP430_BASEADDRESS_ADC12_B__ ADC12B SAMPLEHOLDSOURCE SC ADC12B CLOCKSOURCE ADC120SC ADC12B CLOCKDIVIDER 1 A A DC12B CLOCKPREDIVIDER 1 DC12B MAPINTCHO Enable the ADC12B module ADC12B enable MSP430 BASEADDRESS ADC12 B Base address of ADC12 Module For memory buffers 0 7 sample hold for 16 clock cycles For memory buffers 8 15 sample hold for 4 clock cycles default Disable Multiple Sampling x ADC12B setupSamplingTimer MSP430 BASEADDRESS ADC12 B ADC12B CYCLEHOLD 16 CYCLES ADC12B CYCLEHOLD 4 CYCLES ADC12B MULTIPLESAMPLESDISABLE Configure Memory Buffer Base address of the ADC12 Module Configure memory buffer 0 Map input AO to memory buffer 0 Vref AVcc Vref EXT Positive Memory buffer 0 is not the end of a sequence x ADC12B memoryConfigure MSP430 BASEADDRESS ADC12 B ADC12B MEMORY 0 ADC12B INPUT A0 ADC12B VREFPOS EXTPOS VREFNEG V
112. ngth m TimerD initCompareLatchLoadEvent m TimerD disableHighResFastWakeup m TimerD enableHighResFastWakeup m limerD disableHighResClockEnhancedAccuracy m TimerD_enableHighResClockEnhancedAccuracy 2012 08 2814 58 17 0500 TI Information Selective Disclosure timerD TimerD_DisableHighResGeneratorForceON m TimerD_EnableHighResGeneratorForceON m TimerD_selectHighResCoarseClockRange m TimerD_selectHighResClockRange TimerD outputs are handled by m TimerD getSynchronizedCaptureComparelnput m TimerD_getOutputForOutputModeOutBitValue m TimerD_setOutputForOutputModeOutBitValue m TimerD_generatePWM m TimerD_getCaptureCompareCouni m TimerD_setCompareValue m TimerD getCaptureCompareLatchCount m TimerD getCaptureComparelnputSignal The interrupt handler for the TimerD interrupt is managed with m TimerD enableTimerlnterrupt m TimerD disableTimerlnterrupt m limerD getTimerlnterruptStatus m TimerD enableCaptureComparelnterrupt m TimerD disableCaptureComparelnterrupt m limerD getCaptureComparelnterruptStatus m limerD clearCaptureComparelnterruptFlag m TimerD clearTimerlnterruptFlag m TimerD enableHighReslnterrupt m TimerD disableTimerlnterrupt m limerD getHighReslnterruptStatus m TimerD_clearHighResinterruptStatus Timer D High Resolution handling APIs m limerD getHighReslnterruptStatus m TimerD_clearHighResinterruptStatus m T
113. ns are provided to initialize the COMPD modules setup reference voltages for input and manage interrupts for the COMPD modules The COMPD module provides the ability to compare two analog signals and use the output in software and on an output pin The output represents whether the signal on the positive terminal is higher than the signal on the negative terminal The COMPD may be used to generate a hysteresis There are 16 different inputs that can be used as well as the ability to short 2 input together The COMPD module also has control over the REF module to generate a reference voltage as an input The COMPD module can generate multiple interrupts An interrupt may be asserted for the output with seperate interrupts on whether the output rises or falls This driver is contained in driverlib 5xx_6xx compd c with driverlib 5xx_6xx compd h containing the API definitions for use by applications API Functions The COMPD API is broken into three groups of functions those that deal with initialization and output those that handle interrupts and those that handle auxillary features of the COMPD The COMPD initialization and output functions are m COMPD init m COMPD setReference Voltage m COMPD enable m COMPD disable m COMPD outputValue The COMPD interrupts are handled by m COMPD enablelnterrupt m COMPD disablelnterrupt m COMPD clearinterrupt m COMPD getlnterruptStatus m COMPD interruptSetEdgeDirection m COMPD interrupt
114. ockReguest m CSA getACLK m CSA getSMCLK m CSA getMCLK m CSA setDCOFreg The following external crystal and bypass specific configuration and initialization functions are avail able m CSA LFXTStart m CSA bypassLFXT m CSA bypassLFXTWithTimeout m CSA LFXTStartWithTimeout m CSA_LFXTOff m CSA HFXTStart m CSA bypassHFXT m CSA HFXTStartWithTimeout m CSA bypassHFXTWithTimeout m CSA HFXTOfi 2012 08 2814 58 170500 TI Information Selective Disclosure 12 3 Clock System CSA m CSA VLOoff The CSA interrupts are handled by m CSA enableClockRequest m CSA disableClockReguest m CSA faultFlagStatus m CSA clearFaultFlag m CSA clearAllOscFlagsWith Timeout CSA setExternalClockSource must be called if an external crystal LFXT or HFXT is used and the user intends to call CSA getMCLK CSA getSMCLK or CSA getACLK APIs and HFXTStart HFXTByPass HFXTStartWithTimeout HFXTByPassWithTimeout If not any of the previous API are going to be called it is not necessary to invoke this API Programming Example The following example shows the configuration of the CS module that sets SMCLK MCLK 8MHz Set DCO Frequency to 8MHz CSA_setDCOF req __MSP430_BASEADDRESS_CS_A__ CSA_DCORSEL_0 CSA_DCOFSEL_6 configure MCLK SMCLK to be source by DCOCLK CSA clockSignalInit MSP430 BASEADDRESS CS A CSA SMCLK CSA DCOCLK SELECT CSA CLOCK DIVIDER 1 CSA clockSignalInit MSP430 BASEADDRESS CS A CSA MCLK CSA DCOCLK SELECT CSA CLOCK DIVIDE
115. od odskok book od n bo 99 SUPE P ROT O n Etica a a o o RM RR Us EM o alas 99 Programming EK DIS eosasmepretba Pho P QR EIER EM OPERI DIM Rn op eR DP PC MERE 100 Introduction The Internal Reference REFA API provides a set of functions for using the MSP430Ware REFA modules Functions are provided to setup and enable use of the Reference voltage enable or disable the internal temperature sensor and view the status of the inner workings of the REFA module The reference module REF is responsible for generation of all critical reference voltages that can be used by various analog peripherals in a given device The heart of the reference system is the bandgap from which all other references are derived by unity or non inverting gain stages The REFGEN sub system consists of the bandgap the bandgap bias and the non inverting buffer stage which generates the three primary voltage reference available in the system namely 1 2 V 2 0 V and 2 5 V In addition when enabled a buffered bandgap voltage is available This driver is contained in driverlib 5xx 6xx refa c With driverlib 5xx 6xx refa h containing the API definitions for use by applications API Functions The DMA API is broken into three groups of functions those that deal with the refaerence voltage those that handle the internal temperature sensor and those that return the status of the REFA module The refaerence voltage of the REFA module is handled by m REFA setReferen
116. ounter RTC A Only The RTC module generates multiple interrupts There are 2 interrupts that can be defined in cal endar mode and 1 interrupt in counter mode for counter overflow as well as an interrupt for each prescaler This driver is contained in driverlib 5xx 6xx rtc c with driverlib 5xx_6xx rtc h containing the API definitions for use by applications API Functions The RTC API is broken into 4 groups of functions clock settings calender mode counter mode and interrupt condition setup and enable functions The RTC clock settings are handled by RTC startClock RTC holdClock RTC setCalibrationFreguency RTC setCalibrationData The RTC Calender Mode is initialized and setup by m RTC calenderlnit RTC getCalenderTime RTC getPrescaleValue RTC setPrescaleValue The RTC Counter Mode is initialized and setup by Available in RTC A Only m RTC counterlnit m RTC getCounterValue m RTC setCounterValue 2012 08 2814 58 17 0500 105 TI Information Selective Disclosure Real Time Clock RTC 33 3 106 RTC counterPrescalelnit RTC counterPrescaleHold RTC getPrescaleValue RTC setPrescaleValue The RTC interrupts are handled RTC setCalenderAlarm RTC setCalenderEvent RTC definePrescaleEvent RTC enablelnterrupt RTC disablelnterrupt RTC getlnterruptStatus RTC clearlnterrupt RTC counterPrescaleStart by The following API are available in RTC B Only m RTC convertBCDToBinary m RTC convertBina
117. out m CS XT10Off m CS XT2Start m CS bypassXT2 m CS XT2StartWithTimeout m CS bypassXT2WithTimeout m CS XT2Off The CS interrupts are handled by 2012 08 2814 58 17 0500 TI Information Selective Disclosure 11 3 Clock System CS m CS_enableClockRequest m CS disableClockReguest m CS faultFlagStatus m CS clearFaultFlag m CS clearAllOscFlagsWithTimeout CS setExternalClockSource must be called if an external crystal XT1 or XT2 is used and the user intends to call C8 getMCLK CS getSMCLK or CS getACLK APIs and XT1Start XT1ByPass XT1StartWithTimeout XT1ByPassWithTimeout If not any of the previous API are going to be called it is not necessary to invoke this API Programming Example The following example shows the configuration of the CS module that sets ACLK SMCLK MCLK DCOCLK Set DCO Frequency to 8MHz CS setDCOFreq MSP430 BASEADDRESS CS CS DCORSEL 0 CS DCOFSEL 3 configure MCLK SMCLK and ACLK to be source by DCOCLK CS clockSignalInit MSP430 BASEADDRESS CS CS ACLK CS DCOCLK SELECT CS CLOCK DIVIDER 1 CS clockSignallInit MSP430 BASEADDRESS CS CS SMCLK CS DCOCLK SELECT CS CLOCK DIVIDER 1 CS clockSignalInit MSP430 BASEADDRESS CS CS MCLK CS DCOCLK SELECT CS CLOCK DIVIDER 1 2012 08 28 4 58 17 0500 37 TI Information Selective Disclosure Clock System CS 38 TI Information Selective Disclosure 2012 08 2814 58 17 0500 12 12 1 Clock System CSA Cloc
118. ovided over interrupt sources and events Interrupts can be generated to indicate that an event has been captured This driver is contained in driverlib 5xx 6xx timera c with driverlib 5xx 6xx timera h containing the API definitions for use by applications 2012 08 2814 58 17 0500 125 TI Information Selective Disclosure TimerA 40 2 API Functions The timerA API is broken into three groups of functions those that deal with timer configuration and control those that deal with timer contents and those that deal with interrupt handling TimerA configuration and initialization is handled by m TimerA_startCounter m TimerA_configureContinuousMode m TimerA_configureUpMode m TimerA_configureUpDownMode m TimerA_startContinuousMode m TimerA_startUpMode m TimerA_startUpDownMode m TimerA_initCapture m TimerA_initCompare TimerA_clear m TimerA_stop TimerA outputs are handled by m TimerA_getSynchronizedCaptureComparelnput m TimerA_getOutputForOutputModeOutBitValue m TimerA_setOutputForOutputModeOutBitValue m TimerA_generatePWM m TimerA_getCaptureCompareCount m TimerA_setCompareValue The interrupt handler for the TimerA interrupt is managed with m TimerA enablelnterrupt m TimerA disablelnterrupt m TimerA getlnterruptStatus m limerA enableCaptureComparelnterrupt m limerA disableCaptureComparelnterrupt m limerA getCaptureComparelnterruptStatus m l
119. own resistors Devices within the family may have up to twelve digital I O ports implemented P1 to P11 and PJ Most ports contain eight I O lines however some ports may contain less see the device specific data sheet for ports available Each I O line is individually configurable for input or output direction and each can be individually read or written Each I O line is individually configurable for pullup or pulldown resistors PJ contains only four I O lines Ports P1 and P2 always have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal All P1 I O lines source a single interrupt vector P1IV and all P2 I O lines source a different single interrupt vector P2IV On some devices additional ports with interrupt capability may be available see the device specific data sheet for details and contain their own respective interrupt vectors Individual ports can be accessed as byte wide ports or can be combined into word wide ports and accessed via word formats Port pairs P1 P2 P3 P4 P5 P6 P7 P8 etc are associated with the names PA PB PC PD etc respectively All port registers are handled in this manner with this naming convention except for the interrupt vector registers P1IV and P2IV that is PAIV does not exist When writing to port PA with word operations all 16 bits are written to the port When writing to
120. ponents To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an
121. r is ready first USCI_AO TX buffer ready while UART_interruptStatus __MSP430_BASEADDRESS_USCI_AO__ UCTXIFG Receive echoed data receivedData UART receiveData __MSP430_BASEADDRESS_USCI_AO__ Transmit next data UART transmitData MSP430 BASEADDRESS USCI AO transmitData 3 break default break 2012 08 2814 58 170500 141 TI Information Selective Disclosure UART 142 2012 08 2814 58 17_0500 TI Information Selective Disclosure 45 45 1 Unified Clock System UCS Unified Clock System UCS A e O PEO EEE dne cdd kakao ade ant ing Ra aden hed aoo Dine a da roto Rd a 141 AMARO A Rr o dh bra medius Ead I ped eater MU E 142 Peca MCH Bande ios oo v p ER DPI DU RE DUM PEN ON ESTO EP RH MU dM 143 Introduction The UCS is based on five available clock sources VLO REFO XT1 XT2 and DCO providing signals to three system clocks MCLK SMCLK ACLK Different low power modes are achieved by turning off the MCLK SMCLK ACLK and integrated LDO m VLO Internal very low power low frequency oscillator 10 kHz 0 5 fC 4 V m REFO Reference oscillator 32 kHz 196 396 over full temp range m XT1 LFXT1 HFXT1 Ultra low power oscillator compatible with low frequency 32768 Hz watch crystals and with standard XT1 LFXT1 HFXT1 crystals resonators or external clock sources in the 4 MHz to 32 MHz range including digital inputs Most commonly used as 32 kHz watch crystal oscilla
122. rEvent m RTCC definePrescaleEvent m RTCC enablelnterrupt 2012 08 2814 58 17 0500 109 TI Information Selective Disclosure Real Time Clock RTCc m RTCC disablelnterrupt m RTCC getlnterruptStatus m RTCC_clearlnterrupt The RTC C data conversion is handled by m RTCC_convertBCDToBinary m RTCC_convertBinaryToBCD 34 3 Programming Example The following example shows how to initialize and use the RTC_C API to setup Calender Mode with the current time and various interrupts Initialize Calendar Mode of RTC C Base Address of the RTC_C_A Pass in current time intialized above Use BCD as Calendar Register Format x RTCC calendarInit MSP430 BASEADDRESS RTC C currentTime RTC C FORMAT BCD Setup Calendar Alarm for 5 00pm on the 5th day of the week Note Does not specify day of the week RTCC setCalendarAlarm MSP430 BASEADDRESS RTC C 0x00 Ox17 RTC C ALARMCONDITION OFF 0x05 Specify an interrupt to assert every minute RTCC setCalendarEvent MSP430 BASEADDRESS RTC C RTC C CALENDAREVENT MINUTECHANGE Enable interrupt for RTC C Ready Status which asserts when the RTC C Calendar registers are ready to read Also enable interrupts for the Calendar alarm and Calendar event RTCC enableInterrupt MSP430 BASEADDRESS RTC C RTC CRDYIE RTC CTEVIE RTC CAIE Start RTC C Clock RTCC startClock MSP430 BASEADDRESS RTC C Enter LPM3 mode with interrupts enabled bis SR regis
123. reached its next level 4 SvsL is increased SvsL is changed last because if SVSL were incremented prior to VCORE it would potentially cause a reset VCORE decrease 5 Decrement SvmL and SVSL levels 6 Decrement VCORE The PMM_setVCore function appropriately handles an increase or decrease of the core voltage NOTE The procedure recommended above provides a workaround for the erratum FLASH37 See the device specific erratasheet to determine if a device is affected by FLASH37 The workaround is also highlighted in the source code for the PMM library Recommended SVS and SVM Settings The SVS and SVM on both the high side and the low side are enabled in normal performance mode following a brown out reset condition The device is held in reset until the SVS and SVM verify that the external and core voltages meet the minimum requirements of the default core voltage which is level zero The SVS and SVM remain enabled unless disabled by the firmware The low side SVS and SVM are useful for verifying the startup conditions and for verifying any modification to the core voltage However in their default mode they prevent the CPU from executing code on wake up from low power modes 2 3 and 4 for a full 150 us not 5 us This is because in their default states the SVSL and SvmL are powered down in the low power mode of the PMM and need time for their comparators to wake and stabilize 2012 08 2814 58 17 0500 89 TI Information Selective Disclos
124. register for fast decoding of six ADC interrupts ADC10IFG0 ADC10TOVIFG ADC100VIFG ADC10LOIFG ADC10INIFG ADC10HIIFG This driver is contained in driverlib 5xx_6xx adcl0b c with driverlib 5xx_6xx adcl0b h containing the API definitions for use by applications API Functions The ADC10B API is broken into three groups of functions those that deal with initialization and conversions those that handle interrupts and those that handle auxillary features of the ADC10 The ADC10B initialization and conversion functions are m ADC10B init m ADC10B memoryConfigure 2012 08 2814 58 17 0500 13 TI Information Selective Disclosure 10 Bit Analog to Digital Converter ADC 10B ADC10B_setupSamplingTimer m ADC10B disableSampling Timer m ADC10B_setWindowComp m ADC10B startConversion m ADC10B disableConversions m ADC10B getResults m ADC10B isBusy The ADC10B interrupts are handled by m ADC10B enablelnterrupt m ADC10B disablelnterrupt m ADC10B clearlnterrupt m ADC10B getlnterruptStatus Auxilary features of the ADC10B are handled by m ADC10B setResolution m ADC10B_setSampleHoldSignallnversion m ADC10B setDataReadBackFormat m ADC10B enableReferenceBurst m ADC10B disableReferenceBurst m ADC10B setReferenceBufferSamplingRate m ADC10B getMemoryAddressForDMA m ADC10B enable m ADC10B disable 4 3 Programming Example The following example shows how to initialize and use the ADC10B API to start a single channel
125. roduction The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins The port mapping controller features are m Configuration protected by write access key m Default mapping provided for each port pin device dependent the device pinout in the device specific data sheet m Mapping can be reconfigured during runtime m Each output signal can be mapped to several output pins This driver is contained in driverlib 5xx 6xx pmap c With driverlib 5xx 6xx pmap h containing the API definitions for use by applications API Functions The MSP430ware API that configures Port Mapping is PMAP_configurePorts It needs the following data to configure port mapping portMapping pointer to init Data PxMAPy pointer start of first Port Mapper to initialize numberOfPorts number of Ports to initialize portMapReconfigure to enable disable reconfiguration Programming Example The following example shows some Port Mapping Controller operations using the APIs const unsigned char port_mapping Port P4 PM TBOCCROA PM TBOCCRIA PM TBOCCR2A PM TBOCCR3A PM TBOCCRAA PM TBOCCRS5A PM TBOCCR6A PM NONE y CONFIGURE PORTS pass the port_mapping array start P4MAP01 initialize a single port do not allow run time reconfiguration of port mapping PMAP_configurePorts __MSP430_BASEADDRESS_PORT_MAPPING__ 2012 08 2814 58 17 0500 93 TI Information Selective Disclo
126. rter ADC 12B 12 Bit Analog to Digital Converter ADC12B MUO SSI aas EE O RT VR POP RO RR KO O P O NOR EN OM Gs owas ae O RR O OR V O PO NO LEM MEE EIE 19 A ER ie uid ee n qd eau a bap 20 PIAR E 21 Introduction The 12 Bit Analog to Digital ADC12B API provides a set of functions for using the MSP430Ware ADC12B modules Functions are provided to initializae the ADC12B modules setup signal sources and reference voltages for each memory buffer and manage interrupts for the ADC12B modules The ADC12B module provides the ability to convert analog signals into a digital value in respect to given reference voltages The module implements a 12 bit SAR core sample select control and up to 32 independent conversion and control buffers The conversion and control buffer allows up to 32 independent analog to digital converter ADC samples to be converted and stored without any CPU intervention The ADC12B can also generate digital values from 0 to Vcc with an 8 10 or 12 bit resolution and it can operate in 2 different sampling modes and 4 different conversion modes The sampling modes are extended sampling and pulse sampling in extended sampling the sample hold signal must stay high for the duration of sampling while in pulse mode a sampling timer is setup to start on a rising edge of the sample hold signal and sample for a specified amount of clock cycles The 4 conversion modes are single channel single conversion sequence of chan nels sing
127. ryToBCD Programming Example The following example shows how to initialize and use the RTC API to setup Calender Mode with the current time and various interrupts Initialize Calendar Mode of RTC Base Address of the RTC_A Pass in current time intialized above Use BCD as Calendar Register Format RTC calendarInit __MSP430_BASEADDRESS_RTC__ currentTime RTC FORMAT BCD Setup Calendar Alarm for 5 00pm on the 5th day of the week Note Does not specify day of the week RTC setCalendarAlarm MS 0x00 0x17 RTC ALARMCONDITION OF 0x05 Specify an interrupt to RTC setCalendarEvent MS RTC CALENDAREVENT MIN P430 BASEADDRESS RTC assert every minute P430 BASEADDRESS RTC UTECHANGE Enable interrupt for RTC Ready Status which asserts when the RTC Calendar registers are ready to read Also enable interrupts RTC enableInterrupt MSP RTCRDYIE RTCTEVIE for the Calendar alarm and Calendar event 430 BASEADDRESS RTC RTCAIE 2012 08 2814 58 17 0500 TI Information Selective Disclosure Real Time Clock RTC Start RTC Clock RTC startClock MSP430 BASEADDRESS RTC Enter LPM3 mode with interrupts enabled __bis_SR_register LPM3_bits GIE no operation 2012 08 2814 58 17 0500 107 TI Information Selective Disclosure Real Time Clock RTC 108 2012 08 2814 58 17_0500 TI Information Selective Disclosure 34 34 1 34 2 Real Ti
128. s and those that give status of FRAM FRAM writes are managed by m FRAM write8 m FRAM write16 m FRAM write32 m FRAM memoryFill32 The FRAM interrupts are handled by 2012 08 2814 58 17 0500 63 TI Information Selective Disclosure FRAM Controller m FRAM enablelnterrupt m FRAM getlnterruptStatus m FRAM disablelnterrupt The status is given by m FRAM status 20 3 Programming Example The following example shows some FRAM operations using the APIs Writes the value of data 128 times to FRAM FRAM memoryFill32 MSP430 BASEADDRESS FRAM FR5XX data unsigned long x FRAM TEST START 128 64 TI Information Selective Disclosure 2012 08 2814 58 17 0500 21 21 1 FRGPIO FRGPIO MRT APA NN hh ko dod m aces oko eo da o osad E denne eee sate D ERR 63 SUPE RR ROT SC soto PES do B a pati ALA B B o dus c lata Lb 64 Prem Bande sc ee 64 Introduction The Digital O FRGPIO API provides a set of functions for using the MSP430Ware FRGPIO modules Functions are provided to setup and enable use of input output pins setting them up with or without interrupts and those that access the pin value The digital I O features include m Independently programmable individual I Os m Any combination of input or output Individually configurable P1 and P2 interrupts Some devices may include additional port interrupts m Independent input and output data registers m Individually configurable pullup or pulld
129. s use the same baud rate freguency This driver is contained in driverlib 5xx 6xx uart c with driverlib 5xx 6xx uart h containing the API definitions for use by applications API Functions The UART API provides the set of functions reguired to implement an interrupt driven UART driver The UART initialization with the various modes and features is done by the UART init At the end of this fucntion UART is initialized and stays disabled UART enable enables the UART and the module is now ready for transmit and receive It is recommended to iniailize the UART via UART init enable the required interrupts and then enable UART via UART enablef The UART API is broken into three groups of functions those that deal with configuration and con trol of the UART modules those used to send and receive data and those that deal with interrupt handling and those dealing with DMA Configuration and control of the UART are handled by the 2012 08 2814 58 17 0500 139 TI Information Selective Disclosure UART 44 3 140 m UART init m UART initAdvance m UART enable m UART disable m UART setDormant m UART resetDormant Sending and receiving data via the UART is handled by the m UART transmitData m UART receiveData m UART transmitAddress m UART transmitBreak Managing the UART interrupts and status are handled by the m UART enablelnterrupt m UART disablelnterrupt m UART getlnterruptStatus m
130. sableShortOfInputs COMPB disablelnputBuffer COMPB enablelnputBuffer COMPB lOSwap 8 3 Programming Example The following example shows how to initialize and use the COMPB API to turn on an LED when the input to the positive terminal is highed than the input to the negative terminal Initialize the Comparator B module x Base Address of Comparator B Pin CBO to Positive Terminal Reference Voltage to Negative Terminal Normal Power Mode Output Filter On with minimal delay Non Inverted Output Polarity x COMPB_init __MSP430_BASEADDRESS_COMPB COMPB_INPUTO COMPB_VREF COMPB_POWERMODE_NORMALMODE COMPB FILTEROUTPUT DLYLVLI COMPB NORMALOUTPUTPOLARITY i Set the reference voltage that is being supplied to the terminal Base Address of Comparator B Reference Voltage of 2 0 V Upper Limit of 2 0 32 32 2 0V Lower Limit of 2 0x 32 32 2 0V x COMPB setReferenceVoltage MSP430 BASEADDRESS COMPB COMPB VREFBASE2 DV 32 32 Allow power to Comparator module COMPB_enable __MSP430_BASEADDRESS_COMPB__ delay for the reference to settle delay cycles 75 28 2012 08 2814 58 17 0500 TI Information Selective Disclosure 9 1 9 2 Comparator COMPD Comparator COMPD Lil ee ee nn ee 27 AEI OE anoa n o ee a o ad MEM o k A Es 27 licct uno DNE ss ee 28 Introduction The Comparator D COMPD API provides a set of functions for using the MSP430Ware COMPD modules Functio
131. setVCoreUp or PMM_setVCoreDown function the required number of times depending on the current VCORE level because the levels must be stepped through individually A status indicator equal to STA TUS_SUCCESS or STATUS FAIL that indicates a valid or invalid VCORE transition respectively An invalid VCORE transition exists if DVCC is less than the minimum required voltage for the target VCORE voltage This driver is contained in driverlib 5xx_6xx pmm c with driverlib 5xx_6xx pmm h containing the API definitions for use by applications 2012 08 2814 58 17 0500 91 TI Information Selective Disclosure Power Management Module PMM 28 3 Programming Example The following example shows some pmm operations using the APIs Use the line below to bring the level back to 0 status PMM setVCore MSP430 BASEADDRESS PMM PMMCOREV 0 Set P1 0 to output direction GPIO setAsOutputPin MSP430 BASEADDRESS PORT1 R GPIO PORT P GPIO PINO i continuous loop while 1 Toggle P1 0 GPIO_toggleOutputOnPin __MSP430_BASEADDRESS_PORT1_R__ GPIO_PORT_P1 GPIO_PINO Delay __delay_cycles 20000 92 TI Information Selective Disclosure 2012 08 2814 58 17 0500 29 29 1 29 2 29 3 Port Mapping Controller Port Mapping Controller Ulea SEIT oca ciis b nod dok bn dod ao k ode edk o odd cda a ta Lo ik bp p k doch 91 PTT P ROT C coron Era n do a a l ad MEM o ots ea ee oa 91 Prodam DNE ss nee 91 Int
132. single conversion Initialize ADC10B with ADC10B s built in oscillator ADC10B init MSP430 BASEADDRESS ADC10 B ADC10B SAMPLEHOLDSOURCE SC ADC10B_CLOCKSOURCE_ADC100SC ADC10B CLOCKDIVIDEBY 1 Switch ON ADC10B ADC10B enable MSP430 BASEADDRESS ADC10 B Setup sampling timer to sample and hold for 16 clock cycles ADC10B setupSamplingTimer MSP430 BASEADDRESS ADC10 B ADC10B CYCLEHOLD 16 CYCLES FALSE Configure the Input to the Memory Buffer with the specified Reference Voltages ADC10B memoryConfigure MSP430 BASEADDRESS ADC10 B ADC10B INPUT A0 14 2012 08 2814 58 17 0500 TI Information Selective Disclosure while 2012 08 2814 58 170500 10 Bit Analog to Digital Converter ADC 10B ADC10B_VREFPOS_AVCC Vref AVcc ADC10B VREFNEG AVSS Vref AVss 1 Start a single conversion no repeating or sequences ADC10B startConversion MSP430 BASEADDRESS ADC10 B ADC10B_SINGLECHANNEL Wait for the Interrupt Flag to assert while ADC10B_getInterruptStatus __MSP430_BASEADDRESS_ADC10_B__ ADCI10IFGO Clear the Interrupt Flag and start another conversion ADC10B_clearInterrupt __MSP430_BASEADDRESS_ADC10_B__ ADC10IFGO 15 TI Information Selective Disclosure 10 Bit Analog to Digital Converter ADC 10B 16 TI Information Selective Disclosure 2012 08 2814 58 170500 5 5 1 5 2 12 Bit Analog to Digital Converter ADC12 12 Bit Analo
133. sure Port Mapping Controller const unsigned char port_mapping unsigned char amp PA4MAPO01 1 PMAP DISABLE RECONFIGURATION 2012 08 2814 58 170500 94 TI Information Selective Disclosure 30 30 1 30 2 30 3 RAM Controller RAM Controller Lies a cio pb dnobus dod aces o eo do o odd i denna senate n tl 93 BEE PO ROT Eee 93 Presran nmyg Bande sn ee 93 Introduction The RAMCTL provides access to the different power modes of the RAM The RAMCTL allows the ability to reduce the leakage current while the CPU is off The RAM can also be switched off In retention mode the RAM content is saved while the RAM content is lost in off mode The RAM is partitioned in sectors typically of 4KB sector size See the device specific data sheet for actual block allocation and size Each sector is controlled by the RAM controller RAM Sector Off control bit RCRSyOFF of the RAMCTL Control 0 register RCCTLO The RCCTLO register is protected with a key Only if the correct key is written during a word write the RCCTLO register content can be modified Byte write accesses or write accesses with a wrong key are ignored This driver is contained in driverlib 5xx_6xx ramcontroller c with driverlib 5xx 6xx ramcontroller h containing the API definitions for use by appli cations API Functions The MSP430ware API that configure the RAM controller are ramController_setSectorOff Set specified RAM sector off ra
134. t to overwrite the converted data in any of the memory buffers before it has been read out and or when a conversion is about to start before the last conversion is complete This driver is contained in driverlib 5xx_6xx adcl2 c with driverlib 5xx 6xx adc12 h containing the API definitions for use by applications API Functions The ADC12 API is broken into three groups of functions those that deal with initialization and conversions those that handle interrupts and those that handle auxillary features of the ADC12 The ADC 12 initialization and conversion functions are m ADC12 init m ADC12 memoryConfigure m ADC12 setupSamplingTimer m ADC12 disableSamplingTimer m ADC12 startConversion m ADC12 disableConversions m ADC12 readResults m ADC12 isBusy The ADC12 interrupts are handled by 2012 08 2814 58 17 0500 17 TI Information Selective Disclosure 12 Bit Analog to Digital Converter ADC 12 5 3 18 m ADC12 enablelnterrupt m ADC12 disablelnterrupt m ADC12 clearlnterrupt m ADC12 getlnterruptStatus Auxilary features of the ADC12 are handled by m ADC12 setResolution m ADC12_setSampleHoldSignallnversion m ADC12 setDataReadBackFormat m ADC12 enableReferenceBurst m ADC12 disableReferenceBurst m ADC12 setReferenceBufferSamplingRate m ADC12 getMemoryAddressForDMA m ADC12 enable m ADC12 disable Programming Example The following example shows how to initialize and use the ADC12 API to start a single
135. teReceiveFinishWithTimeout m I2C masterMultiByteSendStopWithTimeout Master Single Byte Receiption with Timeout I2C masterSingleReceiveStartWithTimeout For the interrupt driven transaction the user must register an interrupt handler for the I2C devices and enable the I2C interrupt Slave Operations To drive the slave module the APIs need to be invoked in the following order m 12C_slavelnit m I2C setMode m I2C enable m I2C enablelnterrupt if interrupts are being used This may be followed by the APIs for transmit or receive as required The user must first call the I2C slavelnit to initialize the slave module in I2C mode and set the slave address This is followed by a call to set the mode of operation transmit or receive The 12 module may now be enabled using I2C enable It is recommneded to enable the I2C module before enabling the interrupts Any transmission or reception of data may be initiated at this point after interrupts are enabled if any 2012 08 2814 58 17 0500 TI Information Selective Disclosure 24 2 Inter Integrated Circuit I2C The transaction can then be initiated on the bus by calling the transmit or receive related APIs as listed below Slave Transmission API m I2C slaveDataPut Slave Reception API m I2C slaveDataGet For the interrupt driven transaction the user must register an interrupt handler for the I2C devices and enable the I2C interrupt This driver is contained in driverlib
136. tem cost and low power consumption Using three inter nal clock signals the user can select the best balance of performance and low power consumption The clock module can be configured to operate without any external components with one or two external crystals or with resonators under full software control The clock system module includes up to five clock sources m XT1CLK Low frequency high frequency oscillator that can be used either with low frequency 32768 Hz watch crystals standard crystals resonators or external clock sources in the 4 MHz to 24 MHz range When optional XT2 is present the XT1 high frequency mode may or may not be available depending on the device configuration See the device specific data sheet for supported functions m VLOCLK Internal very low power low frequency oscillator with 10 kHz typical frequency m DCOCLK Internal digitally controlled oscillator DCO with three selectable fixed frequencies m XT2CLK Optional high frequency oscillator that can be used with standard crystals res onators or external clock sources in the 4 MHz to 24 MHz range See device specific data sheet for availability Four system clock signals are available from the clock module m ACLK Auxiliary clock The ACLK is software selectable as XT1CLK VLOCLK DCOCLK and when available XT2CLK ACLK can be divided by 1 2 4 8 16 or 32 ACLK is software selectable by individual peripheral modules m MCLK Master clock
137. tends to communicate with using I2C setSlaveAddress Then the mode of operation transmit or receieve is chosen using I2C setMode The I2C mod ule may now be enabled using I2C enable It is recommneded to enable the I2C module before enabling the interrupts Any transmission or reception of data may be initiated at this point after interrupts are enabled if any The transaction can then be initiated on the bus by calling the transmit or receive related APIs as listed below APIs that include a timeout can be used to avoid being stuck in an infinite loop if the device is stuck waiting for an IFG flag to be set Master Single Byte Transmission m 2C_masterSendSingleByte 2012 08 2814 58 17 0500 77 TI Information Selective Disclosure Inter Integrated Circuit I2C 24 1 2 78 Master Mulitple Byte Transmission m 2C_masterMultiByteSendStart m I2C masterMultiByteSendNext m I2C masterMultiByteSendFinish m I2C masterMultiByteSendStop Master Single Byte Reception m I2C masterSingleReceiveStart m I2C masterSingleReceive Master Multiple Byte Reception m I2C masterMultiByteReceiveStart m I2C masterMultiByte ReceiveNext m I2C masterMultiByte ReceiveFinish m I2C masterMultiByte ReceiveStop Master Single Byte Transmssion with Timeout m I2C masterSendSingleByteWithTimeout Master Multiple Byte Transmission with Timeout m I2C masterMultiByte SendStartWith Timeout m 12C_masterMultiByteSendNextWithTimeout m I2C masterMultiBy
138. ter LPM3 bits GIE no operation 110 2012 08 2814 58 17 0500 TI Information Selective Disclosure 35 35 1 35 2 24 Bit Sigma Delta Converter SD24B 24 Bit Sigma Delta Converter SD24B JESUS aerea ri da able dad la OR bib died adn aa dot ole od bre a da dio do dea 109 AIROSO AR 109 Presan nmyg Bande ann 110 Introduction The SD24_B module consists of up to eight independent sigma delta analog to digital converters The converters are based on second order oversampling sigma delta modulators and digital deci mation filters The decimation filters are comb type filters with selectable oversampling ratios of up to 1024 Additional filtering can be done in software A sigma delta analog to digital converter basically consists of two parts the analog part m called modulator and the digital part a decimation filter The modulator of the SD24 B provides a bit stream of zeros and ones to the digital decimation filter The digital filter averages the bitstream from the modulator over a given number of bits specified by the oversampling rate and provides samples at a reduced rate for further processing to the CPU As commonly known averaging can be used to increase the signal to noise performance of a con version With a conventional ADC each factor of 4 oversampling can improve the SNR by about 6 dB or 1 bit To achieve a 16 bit resolution out of a simple 1 bit ADC would require an impractical oversampling rate of 41
139. tiple capture compares PWM outputs and interval timing timerB also has extensive interrupt capabil ities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers This peripheral API handles Timer B harware peripheral TimerB features include m Asynchronous 16 bit timer counter with four operating modes m Selectable and configurable clock source m Up to seven configurable capture compare registers m Configurable outputs with pulse width modulation PWM capability m Asynchronous input and output latching m Interrupt vector register for fast decoding of all Timer B interrupts Differences From Timer A Timer B is identical to Timer A with the following exceptions m The length of Timer B is programmable to be 8 10 12 or 16 bits m Timer B TBxCCRn registers are double buffered and can be grouped m All Timer B outputs can be put into a high impedance state m he SCCI bit function is not implemented in Timer B TimerB can operate in 3 modes m Continuous Mode m Up Mode m Down Mode TimerB Interrupts may be generated on counter overflow conditions and during capture compare events The timerB may also be used to generate PWM outputs PWM outputs can be generated by ini tializing the compare mode with timerB initCompare and the necessary parameters The PWM may be customized by selecting a desired timer mode continuous up upDown duty cycle out put mode timer perio
140. tor m XT2 Optional high frequency oscillator that can be used with standard crystals resonators or external clock sources in the 4 MHz to 32 MHz range including digital inputs m DCO Internal digitally controlled oscillator DCO that can be stabilized by a frequency lock loop FLL that sets the DCO to a specified multiple of a reference frequency System Clocks and Functionality on the MSP430 MCLK Master Clock Services the CPU Com monly sourced by DCO Is avaiable in Active mode only SMCLK Subsystem Master Clock Services fast system peripherals Commonly sourced by DCO Is available in Active mode LPMO and LPM1 ACLK Auxiliary Clock Services slow system peripherals Commonly used for 32 kHz sig nal ls available in Active mode LPMO to LPM3 System clocks of the MSP430x5xx generation are automatically enabled regardless of the LPM mode of operation if they are required for the proper operation of the peripheral module that they source This additional flexibility of the UCS along with improved fail safe logic provides a robust clocking scheme for all applications Fail Safe logic The UCS fail safe logic plays an important part in providing a robust clocking scheme for MSP430x5xx and MSP430x6xx applications This feature hinges on the ability to detect an oscillator fault for the XT1 in both low and high frequency modes XT1LFOFFG and XT1HFOFFG respectively the high frequency XT2 XT2OFFG and the DCO DCOFFG These flags
141. tus m GPIO interruptEdgeSelect The GPIO pin state is accessed with m GPIO setOutputHighOnPin m GPIO setOutputLowOnPin m GPIO toggleOutputOnPin m GPIO getlnputPinValue Programming Example The following example shows how to use the GPIO API Set P1 0 to output direction GPIO setAsOutputPin MSP430 BASEADDRESS PORT1 R GPIO PORT P GPIO PINO i 2012 08 2814 58 17_0500 TI Information Selective Disclosure GPIO Set P1 4 to input direction GPIO_setAsInputPin __MSP430_BASEADDRESS_PORTI_R__ GPIO_PORT_P1 GPIO_PIN4 i while 1 Test P1 4 if GPIO INPUT PIN HIGH GPIO getInputPinValue __MSP430_BASEADDRESS_PORT1_R_ GPIO_PORT_P1 GPIO_PIN4 if P1 4 set set P1 0 GPIO setOutputHighOnPin MSP430 BASEADDRESS PORT1 R GPIO PORT P1 GPIO PINO i else else reset GPIO setOutputLowOnPin MSP430 BASEADDRESS PORTl1 R GPIO PORT P1 GPIO PINO i 2012 08 2814 58 17 0500 75 TI Information Selective Disclosure GPIO 76 TI Information Selective Disclosure 2012 08 2814 58 17 0500 24 24 1 24 1 1 Inter Integrated Circuit I2C Inter Integrated Circuit 12C Ll eMe APP Zo n o ikon dod ao odk ate aden dda aa h bool b n k a 75 A n o a Ra ad AE M o ta Edad OR v 77 Pregranimng DE see 78 Introduction The Inter Integrated Circuit I2C API provides a set of functions for using the MSP430Ware 12C modules Functions are provided to in
142. ude programmable threshold levels and power fail indicators Therefore the PMM plays a crucial role in defining the maximum performance valid voltage conditions and current consumption for an appli cation running on an MSP430x5xx or MSP430x6xx device The secondary voltage that is generated by the integrated LDO VCORE is programmable to one of four core voltage levels shown as 0 1 2 and 3 Each increase in VCORE allows the CPU to operate at a higher maximum frequency The values of these frequencies are specified in the device specific data sheet This feature allows the user the flexibility to trade power consumption in active and low power modes for different degrees of maximum performance and minimum supply voltage NOTE To align with the nomenclature in the MSP430x5xx MSP430x6xx Family UserSs Guide the primary voltage domain DVCC is referred to as the high side voltage SvsH SVMH and the secondary voltage domain VCORE is referred to as the low side voltage SvsL SvmL Moving between the different VCORE voltages requires a specific sequence of events and can be done only one level at a time for example to change from level 0 to level 3 the application code must step through level 1 and level 2 VCORE increase 1 SvmL monitor level is incremented 2 VCORE level is incremented 3 The SvmL Level Reached Interrupt Flag SVSMLVLRIFG in the PMMIFG register is polled When asserted SVSMLVLRIFG indicates that the VCORE voltage has
143. upt __MSP430_BASEADDRESS_ADC10__ ADC10IFGO 12 2012 08 2814 58 17_0500 TI Information Selective Disclosure 4 4 1 4 2 10 Bit Analog to Digital Converter ADC10B 10 Bit Analog to Digital Converter ADC10B A EN ONO O O RR O OR IF O PO NO ee 11 E AEE cs A dod A ee ee 11 Programming EAN DNE ases soccer k oo AA 12 Introduction The 10 Bit Analog to Digital ADC10B API provides a set of functions for using the MSP430Ware ADC10B modules Functions are provided to initializae the ADC10B modules setup signal sources and reference voltages and manage interrupts for the ADC10B modules The ADC10B module supports fast 10 bit analog to digital conversions The module implements a 10 bit SAR core together sample select control and a window comparator ADC10B features include m Greater than 200 ksps maximum conversion rate m Monotonic 10 bit converter with no missing codes m Sample and hold with programmable sampling periods controlled by software or timers m Conversion initiation by software or different timers m Software selectable on chip reference using the REF module or external reference m Twelve individually configurable external input channels m Conversion channel for temperature sensor of the REF module m Selectable conversion clock source m Single channel repeat single channel seguence and repeat seguence conversion modes m Window comparator for low power monitoring of input signals m Interrupt vector
144. ure Power Management Module PMM 28 2 90 before they can verify the voltage condition and release the CPU for execution Note that the high side SVS and SVM do not influence the wake time from low power modes If the wake up from low power modes needs to be shortened to 5 us the SVSL and SvmL should be disabled after the initialization of the core voltage at the beginning of the application Disabling SVSL and SvmL prevents them from gating the CPU on wake up from LPM2 LPM3 and LPM4 The application is still protected on the high side with SvsH and SVMH The PMM_setVCore function automatically enables and disables the SVS and SVM as necessary if a non zero core voltage level is required If the application does not require a change in the core voltage that is when the target MCLK is less than 8 MHz the PMM_disableSVSLSvmL and PMM_enableSvsHReset macros can be used to disable the low side SVS and SVM circuitry and enable only the high side SVS POR reset respectively Setting SVS SVM Threshold Levels The voltage thresholds for the SVS and SVM modules are programmable On the high side there are two bit fields that control these threshold levels U the SvsHRVL and SVSMHRRL The SvsHRVL field defines the voltage threshold at which the SvsH triggers a reset also known as the SvsH ON voltage level The SVSMHRRL field defines the voltage threshold at which the SvsH releases the device from a reset also known as SvsH OFF voltage level
145. v operations using the APIs struct s TLV Die Record pDIEREC unsigned char bDieRecord bytes TLV getInfo TLV TAG DIERECORD 0 F amp bDieRecord_bytes unsigned int amp pDIEREC 3 2012 08 2814 58 17 0500 137 TI Information Selective Disclosure Tag Length Value 138 2012 08 2814 58 17_0500 TI Information Selective Disclosure 44 44 1 44 2 UART UART MONO anne hdd zd ked ikea S ET 137 AP PUM MONS ju do el dek nee 137 Pregrammng Example ann 138 Introduction The MSP430Ware library for UART mode features include m Odd even or non parity m Independent transmit and receive shift registers m Separate transmit and receive buffer registers m LSB first or MSB first data transmit and receive m Built in idle line and address bit communication protocols for multiprocessor systems m Receiver start edge detection for auto wake up from LPMx modes m Status flags for error detection and suppression m Status flags for address detection m Independent interrupt capability for receive and transmit The modes of operations supported by the UART and the library include m UART mode m Idle line multiprocessor mode m Address bit multiprocessor mode m UART mode with automatic baud rate detection In UART mode the USCI transmits and receives characters at a bit rate asynchronous to another device Timing for each character is based on the selected baud rate of the USCI The transmit and receive function
146. vious MSP430 families It is no longer required to reset the OFIE NMI entry exit circuitry removes this requirement The OFIFG flag must be cleared by software The source of the fault can be identified by checking the individual fault bits If LFXT is sourcing any system clock ACLK MCLK or SMCLK and a fault is detected the system clock is automatically switched to LFMODCLK for its clock source The LFXT fault logic works in all power modes including LPM3 5 If HFXT is sourcing MCLK or SMCLK and a fault is detected the system clock is automatically switched to MODCLK for its clock source By default the HFXT fault logic works in all power modes except LPM3 5 or LPM4 5 because high frequency operation in these modes is not supported The fail safe logic does not change the respective SELA SELM and SELS bit settings The fail safe mechanism behaves the same in normal and bypass modes This driver is contained in driverlib 5xx_6xx cs_a c with driverlib 5xx_6xx cs_a h containing the API definitions for use by applications API Functions The CSA API is broken into four groups of functions an API that initializes the clock module those that deal with clock configuration and control and external crystal and bypass specific configuration and initialization and those that handle interrupts General CSA configuration and initialization are handled by the following API m CSA_clockSignallnit m CSA_enableClockRequest m CSA disableCl
147. y system clock ACLK MCLK or SMCLK and a fault is detected the system clock is automatically switched to the VLO for its clock source VLOCLK Similarly if XT1 in HF mode is sourcing any system clock and a fault is detected the system clock is automat ically switched to MODOSC for its clock source MODCLK When XT2 if available is sourcing any system clock and a fault is detected the system clock is automatically switched to MODOSC for its clock source MODCLK The fail safe logic does not change the respective SELA SELM and SELS bit settings The fail safe mechanism behaves the same in normal and bypass modes This driver is contained in driverlib 5xx 6xx cs c with driverlib 5xx 6xx cs h con taining the API definitions for use by applications API Functions The CS API is broken into four groups of functions an API that initializes the clock module those that deal with clock configuration and control and external crystal and bypass specific configuration and initialization and those that handle interrupts General CS configuration and initialization are handled by the following API m CS clockSignallnit m CS enableClockRequest m CS disableClockRequest m CS getACLK m CS getSMCLK m CS getMCLK m CS setDCOFreq The following external crystal and bypass specific configuration and initialization functions are avail able for FR57xx devices m CS_XT1Start m CS bypassXT1 m CS bypassXT1WithTimeout m CS XT1StartWithTime

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