User's Manual - High Energy Physics
Contents
1. Errors Error flags sent if an error condition have been detected 31130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6151413121110 0 1 1 O0 TDC ID Error flags Error flags see Table 2 and Table 3 Debugging data Additional information for system debugging Separator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 716151413 2110 0 1 1 4 TDC ID 0 0 0 0 Bunch ID Bunch ID Trigger time tag counter when separator was generated Buffer Occupancy 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2110 0 1 1 1 TDC ID 0 0 0 1 R L1 Occupancy L1 occupancy L1 buffer occupancy R Read out FIFO full 2 9 4 Event format Event format is shown in Fig 10 Each word is controlled in corresponding control bits and only exists when enabled corresponding control bits Header enable header Hard Error enable error enable errmrk Single Combined data enable pair enable leading enable2. Parity Instruction Name Description 0 0000 EXTEST Boundary scan for test of inter chip connections on module 1 0001 IDCODE Scan out of chip identification code 1 0010 SAMPLE Sample of all chip pins via boundary scan registers 0 0011 INTEST Using boundary scan registers to test chip itself 0100 0111 not used 1 1000 CONTROL Read Write of control data 0 1001 ASD control 0 1010 STATUS Read out of status register information 1 1011 CORETEST Read Write internal registers for debugging 0 1100 BIST Built In Self Test for Memories 1 1101 General purpose output port 0 1110 not used 0 1111 BYPASS Select BYPASS register 3 3 2 Boundary scan registers All signal pins of the TDC are passed through JTAG boundary scan registers All JTAG test modes related to the boundary scan registers are supported EXTEST INTEST SAMPLE m7 BRITA HOD AMT 3 Boundary Scan Registers BSR Pin name Input Output Comment 0 ASDMOD I 1 RESETB I inverted 2 ENCCONTP I LVDS input ENCCONTM 26 3 HITP 23 0 I LVDS input HITM 23 0 27 BUNCHRSTB I inverted 28 CLKOEN I 29 EVENTRSTB I inverted 30 CLKO 31 TRIGGER I 32 CLKP CLKM I LVDS input 33 DIOEN O 34 do 0 see Fig 13 35 di 0 I see Fig 13 56 do 11 O see Fig 13 57 di 11 I see
3. 25 3 1 13 pr E n ED E E E E E SA 26 3 1 14 5 1 14 T 26 3 1 15 CSRS EE 26 3 2 STATUS REGISTERS ENNEN EENEG 27 3 2 1 CSR EE 27 3 2 2 CSRIZ EE 27 3 2 3 TOEI 28 3 2 4 CS 819 28 3 2 5 EE 28 3 2 6 28 3 3 JTAG ERR geregelte 28 3 3 1 JTAG controller and instructions iscicccscciscsdecsdecedeccdsscdscadeceiecsieesdassdeccdescdscadacadoccdeesdsssdacededcdsesdscededsdsdses 29 3 3 2 Boundary Scan registers 2 32 e 30 3 3 3 TE 32 3 3 4 Lonirol Fee 32 3 3 5 Ha 32 3 3 6 Cofe Tegisiers o rU NEN I NN EN CN E NN 33 3 3 7 att entree 33 4 TIME ALIGNMENT BETWEEN HITS CLOCK AND TRIGGER MATCHING 35 4 1 EXAMPLE OF OFFSET SETTING e 37 5 APPENDIX INTERNAL DATA 39 6 APPENDIX BUFFER OVERFLOW CONTROLS MAY 7 2002 42 0 Notice 0 1 Document Change 0 2 Changes from AMT 2 1 Bugs in trigger matching circuit which occasionally cause hit miss and false hit were corrected 2 strobe_s
4. 0 71 68 67 66 65 60 initial value at reset JTAG bit No 3 2 1 CSR16 error flags 8 0 status of error monitoring see section 2 10 bit 8 0 1 2 3 4 5 6 7 11 buffer parity error trigger FIFO parity error trigger matching error state error readout FIFO parity error readout state error control parity error JT AG instruction parity error coarse error parity error in the coarse counter channel select error more than 1 channel are selected control parity parity of control data see section 2 10 rfifo full 0 rfifo empty 0 3 22 CSR17 write address 7 0 overflow read out FIFO full read out FIFO empty L1 buffer write address L1 buffer overflow bit 11 over recover L1 buffer overflow recover bit 11 nearly full L1 buffer nearly full bit empty L1 buffer empty bit 3 2 8 CSRI8 1 read address 7 0 L1 buffer read address running status of START signal tfifo full trigger FIFO full bit tfifo nearly full trigger FIFO nearly full bit trigger fifo empty trigger FIFO empty bit 3 2 4 CSRI9 11 start address L1 buffer start address tfiffo occupancy trigger FIFO occupancy number of word in trigger FIFO coarse counter Coarse counter bit 0 3 2 5 CSR20 coarse counter 12 1 Coarse counter bit 12 1 3 2 6 CSR21 rfifo_occupancy 5 0 Read out FIFO occupancy number of word in read out FIFO general_in 3 0 4
5. The JTAG control scan path is used to set CSRO 14 registers that should not be changed while the TDC is actively running See section 3 1 for register details 3 3 5 Status registers The JT AG status scan path is used to get access to the status of the TDC while it is running or after a run See section 3 1 15 for register details 3 3 6 Core registers The JT AG core register scan path is used to perform extended testing of TDC chip This scan path gives direct access to the interface between the channel buffers and first level buffer logic It is used in connection with the test mode bits CSRO 7 and is only intended for verification and production tests of the TDC chip If the test invert CSRO 6 21 and hit load 1 in the test mode contents of the hit data hit channel and hit select error are inverted in every cycle Table 7 Bit assignment of the core registers JTAG bit name R W comments 10 0 matching state 10 0 R monitoring of trigger matching state 37 11 trigger data 26 0 R monitoring of active trigger data 38 trigger ready monitoring of active trigger 74 39 II data 35 0 R monitoring of hit data to trigger matching 75 II empty monitoring of l1 empty flag 76 II data ready R monitoring of II data redy flag 168 77 hit data 91 0 R W monitoring generation of hit data 173 169 hit channel 4 0 R W monitoring generation of hit
6. 1 Led Jg Fig 9 Different strobe types 1 UU ULL Data read out of the TDC is contained in 32 bits data packets For the parallel read out mode one complete packet word can be read out in each clock cycle In the serial read out mode a packet is sent out bit by bit The first four bits of a packet are used to define the type of data packet The following 4 bits are used to identify the ID of the TDC chip programmable generating the data Only 7 out of the possible 16 packet types are defined for TDC data The remaining 9 packet types are available for data packets added by higher levels of the DAQ system TDC header Event header from TDC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 101 0 TDC ID Event ID Bunch ID TDC Programmed ID of TDC Event ID Event ID from event counter Bunch ID Bunch ID of trigger trigger time tag TDC trailer Event trailer from TDC 31 30 29 28 27 26 25 24 23 22121 20 19 18 17 16 15 14 13 12 11 10 9 8 7 1615 4131211410 11
7. 2 7 5 DLL TE 13 2 7 6 RERO RBRUM 14 2 8 READ OUT FIFO AND BUFFER FULL CONTROL cscscsccscecsscscecsccscecsecsceccscscecsecsceceecsceccecscesecsceceecscecescscecesesceces 15 2 9 READ OUT INTERFACE 15 2 9 1 E 15 2 9 2 E TR ET EE 16 2 9 3 Data fOr mec EE 17 2 9 4 18 2 10 ERROR MONITORING ed 18 2 10 1 Hard siete beiiiofote 19 2 10 2 Temporal E 19 3 CSR REGISTERS 4 JTAG ACCESS cc ccccccccccccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeeeeeees 20 3 1 CONTROL REGISTERS 22 3 1 1 EOE win ee a en 22 3 1 2 CSR ccr 23 3 1 3 TEE RAN RE 23 3 1 4 TE EE 23 3 1 5 CSRA 23 3 1 6 23 3 1 7 OSRG Mee 24 3 1 8 TE 24 3 1 9 CSRS o eric eee MEO CIO ET Mmm OARS I BONDED 24 3 1 10 v 24 3 1 11 CST110 5 1 ee E ana atone cirri 24 3 1 12
8. if enable_header and enable_trailer bits are set respectively The header contains an event id and a bunch id The event trailer contains the same event id plus a word count An example of setting is shown in 4 1 The trigger matching function may also be completely disabled enable_matching 0 whereby all data from the L1 buffer is passed directly to the read out FIFO In this mode the TDC have an effective FIFO buffering capability of 256 64 320 measurements Since the matching circuit which control the L1 buffer is disabled there is no overflow control to the L1 buffer Thus old data will be overwritten by new data if the overflow occur 2 7 Trigger amp Reset Interface The trigger interface takes care of receiving the trigger signal and generate the required trigger time tag to load into the trigger FIFO In addition it takes care of generating and distributing all signals required to keep the TDC running correctly during data taking The TDC needs to receive a global reset signal that initializes and clears all buffers in the chip before data taking A bunch count reset and event count reset is required to correctly identify the event ID and the bunch ID of accepted events These signals can either be generated separately or be coded on a single serial line at 40 MHz 2 7 1 Encoded trigger and resets Four basic signals are encoded using three clock periods Table 1 The simple coding scheme is restricted to only distribute on
9. pair 1 normal data 29 28 27 26 25 24 23 2221 20 19 18 17 161514131211109876543210 enable pair 1 over flow 29 28 27 26 25 24 23 2221 20 19 18 17 161514131211109876543210 enable pair 21 under flow 29 28 27 26 25 24 23 222120 19 18 17 161514131211109876543210 reject out enable pair reject first reject second reject first hit error select error coarse error Readout FIFO Event Header 27262524 2322212019 18171615 1413 1211 109876543210 parity 101 0 trigger_data 23 0 event id bunch id Lost Event Header 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109876543210 1 0 1 0 lost_trigger 11 0 lost event id trigger data 11 0 Event Trailer 27 26 25 24 23222120191817161514131211109876543210 parity 1 1 0 0 trigger_data 23 0 event id bunch id Lost Event Trailer 28 27 26 25 24 23 222120 19 18 17 16 15 14 13 12 11109876543210 parity 1100 lost trigger 11 0 lost event id Error 28 27 26 2524 23 Ds 14 error data 0 enable matching amp 11 buffer overflow error data 1 enable matching amp trigger lost error data 2 enable matching amp full rejected enable rofull reject amp readout fifo full amp enable reject nearly full enable trfull reject amp trigger fifo nearly full enable reject amp enable trfull reject error data 3 enable matching amp hit error error data 4 enable matching reject out Mask Flags 28 p
10. status bit The error bits are reset by a global reset or when error reset CSRO 10 bit is set or when error error word is marked The error bits are also reset by bunch count reset or event count reset if enable erst bcrevr is set All the available error flags are OR ed together with individual programmable mask bits to generate an ERROR signal When the ERROR signal becomes active the TDC can respond following ways Ignore No special action will be performed enable errmark 0 Mark events All events being generated after the error has been detected will be marked with a special error flag enable errmark 1 Table 2 Hard Errors comes after header word Error flag bit in enable error Description error flags and error word Coarse count error 0 A parity error in the coarse count has been detected in a channel buffer Channel select error 1 A synchronization error has been detected in the priority logic used to select the channel being written into the L1 buffer more than channel are selected L1 buffer error Parity error detected in L1 buffer Trigger FIFO error Parity error detected on trigger FIFO Matching state error Illegal state detected in trigger matching logic Read out FIFO error Parity error detected in read out FIFO Read out state error Illegal state detected in read out logic Control parity error Parity error detected in control registers INIA vJ AJIN J
11. the readout FIFO always stores header and trailer irrespective of enable header and enable trailer bits settings The event header and trailer are removed from the readout FIFO at readout time if above bits are not set When the readout FIFO becomes full there are two modes to handle data back propagate mode enable rofull reject 0 In this mode trigger matching will be blocked when the readout FIFO becomes full This will resume when a new space is available in the readout FIFO When this occurs the L1 buffer and the trigger FIFO will be forced to store more data and finally the measurement is stopped If this situation lasts longer than count roll over 2 period the data integrity can not be guaranteed data reject mode enable rofull reject 1 In this mode data in the L1 buffer will be rejected when the readout FIFO becomes full so this prevent to stop the measurement Instead only header error word with Readout FIFO overflow bit 11 flag and trailer are written to the readout FIFO This rejection occurs irrelevant to the data volume in L1 buffer and Trigger FIFO if enable_l1full_reject 0 and enable trfull 0 If enable_l1full_reject 1 the above rejection starts when the L1 buffer becomes nearly full at 191 words 2 255 64 If enable trfull reject 1 the above rejection starts when trigger FIFO becomes nearly full at 4 triggers References 1 AMT 0 manual http micdigital web cer
12. trailing Mask Flag enable mask Temporal Error enable errmrk ovr enable errmrk rejected Trailer enable trailer Debugging data enable sepa readout enable sepa bcrst emnable sepa evrst enable lloccup readout Header Fig 10 Event Format 2 10 Error monitoring There are two kinds of error hard errors and temporal errors Hard errors are enabled with enable error bits CSR12 8 0 and read through error flags CSR16 8 0 Temporal errors are such as buffer overflow and resumed automatically if data rate decreases These errors are embedded within data stream and available only through error word Since the hard error and temporal error are generated separately the error word only contains one kind of error flags 2 10 1 Hard Errors All functional blocks in the TDC are continuously monitored for error conditions Memories are continuously checked with parity on all data All internal state machines have been implemented with a one hot encoding scheme and is checked continuously for any illegal state The JT AG instruction register have a parity check to detect if any of the bits have been corrupted during down load The CSR control registers also have a parity check to detect if any of the bits have been corrupted by a Single Event Upset SEU The error status of the individual parts can be accessed via the CSR status registers Table 2 Any detected error condition in the TDC sets its corresponding error
13. wave do28 31 1 wave do28 31 0 wave Bdio24 27 3 ve asdchain asdl dac Fig 15 Simulated timing diagram of the ASD control signals SR wave trstb wave tck wave tms wave tdi wave tdo tap state ir update reg wave do28 31 3 wave do28 31 2 wave do28 31 1 wave do28 31 0 wave Bdio24 27 3 ve asdchain asdl dac Fig 16 Simulated timing diagram of the ASD control signal when the TDO register in the ASD is removed 4 Time alignment between hits clock and trigger matching The TDC contains many programmable setups which have effects on the performed time measurements and their trigger matching The main time reference of the TDC is the clock and the bunch reset which defines the TO time The time alignment can basically be divided into three different areas as shown in the figure below A Time relationship between the hits clock and the bunch count reset generating the basic timing measurements of the TDC B Time relationship between the performed time measurements and the trigger time tag C Time relationship between the time measurements and the automatic reject CO read out FIFO trigger maching D D D D Fig 12 Time alignment between hits trigger and automatic reject A Basic time measurement As previously stated the basic time reference of the TDC measurements is the rising edges of the clock The bunch count reset defines the TO reference time where the coarse time coun
14. 00 TDC ID Event ID Word Count Word count Number of words from TDC incl headers and trailers Mask flags Channel flags for channels having hits with in mask window 31130129 28 27 26125 24 23 22 21 20119118 17 16 15 14 13 112 11 110 9 7 6 5 4 3 2 1 0 0 0 1 0 TDC ID Mask flags Mask flags Channels flagged as having hits with in mask window Single measurement data Single edge time measurement 31130129128 27 26125 24 23 22 2120191817 16151413 1211109 8 171615 1413121110 0 0 1 1 TDC ID Channel T E Coarse Time Fine Time Channel TDC channel number Coarse Time Coarse time measurement in bins of 25ns Fine Time Fine time measurement from PLL in bins of 25ns 32 T Edge type 1 leading edge 0 trailing edge E Error An error has been detected in the hit measurement a coarse counter error a channel select error or a rejected hit error Combined measurement data Combined measurement of leading and trailing edge 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 918 7 6 5 4 3 2 1 0 0 1 0 0 TDC ID Channel Width Coarse Time Fine Time Width Width of pulse in programmed time resolution CSR9 width_select If the pulse width excees the width range the width will be FF Coarse Time Coarse time measurement of leading edge relative to trigger in bins of 25ns Fine Time Fine time measurement of leading edge in bins of 25ns 32
15. AMT 3 ATLAS Muon TDC version 3 User s Manual Yasuo KEK National High Energy Accelerator Research Organization 1 1 Oho Tsukuba Ibaraki 305 Japan yasuo arai kek jp http atlas kek jp tdc Tel 81 29 864 5366 Fax 81 29 864 2580 AMT 3 ES chip produced on Oct 2003 Rev 0 1 Jan 22 2003 SQ if II NS 2 22 E 2 OTTO TTT SO ds ESA Contents 0 NOTICE EE 4 0 1 DOCUMENT CHANGE 4 0 2 CHANGES FROM 2 Aan 4 0 3 KNOWN BUG S INSAM LE WE 4 12 INTRODUCTION coos Fee oe ea ENEE E ae ha cae ENEE NENNEN 5 2 CIRCUIT DESCRIPTION de e 6 2 1 FINE TIME MEASUREMENT EEN 7 2 2 COARSE COUNTER teuer een 8 2 3 CHANNEL BUFFER EE Ee 9 2 4 ENCODER ID NEEN ENEE ENNEN EEN NENNEN Ee 9 2 5 EU BUFFER legen attente 10 2 6 TRIGGER MATCHING ee EEN 11 2 7 TRIGGER amp RESET INTERFACE 5 52 0i eror desee senos uy esu sesvsesusesezesvzesuesuzesuzesvsesusesezesezesedesupesuseseresscu edusezesedosezesubs 12 2 7 1 Encoded trigger and LU EBERT M 12 2 7 2 Event count reset SEP PE EEE EEE EME CELE PEP ECE EEE EE EEE CELE EE PELE CECE EE EEE CELE EEE ECE EEE EE EEE CE hub 13 2 7 3 aM 13 2 7 4 Global reset cade dace duce t t te ie o i ee de ee 13
16. Fig 13 69 58 4 2 23 11 0 O 70 dio24_27 0 71 dio24_27 0 I 76 dio24_27 3 O 77 dio24_27 3 I 81 78 do28 31 3 0 82 GETDATA I 83 START I 84 DSPACE I 85 WR I 86 CS I 91 87 RA 0 4 I 92 CLKOUT 93 DREADY O 94 ERROR 95 SERIOUTP LVDS output SERIOUTM 96 STROBEP LVDS output STROBEM scan_out Boundary Scan Register scan_in enable output buffer dioen bsr_in BSR bsr out scan out scan in do 0 gt ber mm BGR ber out Diolol scan out scan in do 12 gt bsr_in BSR bsr out x 010 12 scan_out dilo J bsr_out BSR ber An scan out scan_in gn dol13 gt bsr_in BGR bsr_out gt pio 12 soenan scan_out do 1 gt ber An BSR bsr out DIO 1 scan out e scan in di 1 lt 4 bsr_out BSR ber An e scan_out e e x e scan_in do 11 gt ber An BSR bsr out pio 11 scan out senem do s1 bsr_in BSR ber out gt pIo z1 scan_out scan_in di 11 em bsr_out BSR ber An scan_out scan_in Fig 13 JTAG boundary scan circuit for the DIO port 3 3 3 code register A 32 bit chip identification code can be shifted out when selecting the ID shift chain 0 Start bit 1 11 1 manufacturer code 0000 0011 000 Toshiba 27 12 TDC part code 1000 1011 1000 0101 31 28 Version code 0011 Thus the total ID code in hex formats is 38B85031 3 3 4 Control registers
17. TAG error Parity error in JTAG instruction 2 10 2 Temporal Errors Temporal errors are embedded in data and available only through an error word Effective error bits are different depend on the setting of enable_match Table 3 Temporary Error comes after data enable_ Error flag bit in error Description Comments match word CSR10 9 0 L1 buffer overflow 9 L1 buffer becomes full and Enabled by enable_errmark_ovr hit data have been lost 1 L1 buffer overflow 9 L1 buffer becomes full and hit data have been lost 1 Trigger FIFO 10 Trigger fifo becomes full trigger lost overflow and events have been lost 1 Readout FIFO 11 Readout fifo becomes full enable rofull reject amp overflow and hit data have been lost readout fifo full amp enable reject amp nearly full enable trfull reject amp trigger fifo nearly full enable reject amp enable trfull reject 1 Hit error 12 A hit measurement have This error is set when the data been corrupted channel with hit error comes in trigger select error or coarse count matching circuit error 0 Channel buffer 13 Channel buffer becomes This error is set when the data oveflow full with rejected comes and enable_rejected 1 3 CSR Registers amp JTAG access There are two kinds of 12 bits registers CONTROL and STATUS registers The CONTROL registers are readable and writable registers which contr
18. arity 27 26 25 24 23222120191817161514131211109876543210 0 0 1 0 mask_flags 23 0 Single Measurement enable_relative 0 28 27262524 2322212019 16 15 14 13 1211109876543210 E Hit Error 11 data 31 11_data 30 T Edge Type 11 data 17 Single Measurement enable_relative 1 27262524 2322212019 16 15 1413 12111098765 43210 0 0 1 1 11_4 29 25 coarse_relative 11 0 11_data 4 0 Combined Measurement enable_relative 0 27 26 25 24 23 22 21 20 19 18 171615 1413 12 11 109876543210 010 0 1l data 29 17 11 data 10 0 Combined Measurement enable relativez1 27 262524 23 222120191817 1615 14 1312 11 1098765 43210 parity 0 1 0 0 11_data 29 17 corase_ 11_data 4 0 relative 5 0 Separator 2 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11109876543210 iy O 1 1 1 trigger data 11 0 Buffer Occupancy 28 27262524 23222120 191817161514131211109 8 76543210 R Readout FIFO full Trigger FIFO 23 22 21 20 19 18 17 16 15 14 13 12 11109876543210 N ON 6 Appendix B Buffer Overflow Controls May 7 2002 Buffer control mechanism of the AMT is somewhat complicated Although the detailed explanations are available in reference 4 and this manual brief summary is presented here for your understanding All description here assumes enable_match bit is set Fig 18 shows buffer structure of the AMT chip Overflow control is done for each buffer and described below In rea
19. bit general purpose inputs Input level of the DIO27 DIO24 can be read through this register if ASDMOD pin is set to high level general in 3 is shared with ASDIN signal 3 3 JTAG Port JT AG Joint Test Action Group IEEE 1149 1 standard boundary scan is supported to be capable of performing extensive testing of TDC modules while located in the system Testing the functionality of the chip itself is also supported by the JTAG INTEST and BIST capability In addition special JT AG registers have been included in the data path of the chip to be capable of performing effective testing of registers and embedded memory structures Furthermore it is also possible to access CSR registers from the JT AG port Parity error in JTAG instruction will set error flag 8 in CSR16 This error can be recognized by reading the register enable error word or detect through ERRORB signal The instruction is stored in instruction register and executed regardless of the presence of the instruction parity error JTAG TAP Test Access Port state diagram is shown in Fig 12 Test Logic Reset Run Test Fig 12 TAP controller state diagram Numbers in each states shown are state variable of the TAP controller 3 3 1 controller and instructions The JTAG instruction register is 4 bits long plus a parity bit 3 0 ins 3 0 JTAG instruction 4 parity 0 parity of JTAG instruction Table 6 JTAG Instructions
20. ch count reset The bunch count reset loads the programmed offsets into the coarse time counter the trigger time tag bunch id counter and the reject counter In addition a separator can be injected into the L1 buffer and the trigger FIFO if enable sepa bcrst is set From a bunch count reset is given to the TDC until this is seen in the hit measurements themselves a latency of the order of 2 clock cycles is introduced by internal pipelining of the coarse time counter The definition of time O in relation to the bunch count reset is described in more detail in section 4 2 7 4 Global reset The global reset generate master reset signal if enable mreset code is set see Fig 6 The master reset clears all buffers in the TDC and initializes all internal state machines to their initial state Before data taking an event count reset and a bunch count reset must also have been issued As shown in Fig 6 decoder circuit CSR JTAG contrioller and PLL circuit are not reset by the master reset 2 7 5 Trigger The basis for the trigger matching is a trigger time tag locating in time where hits belong to an event of interest The first level trigger decision must be given as a constant latency yes no trigger signal The trigger time tag is generated from a counter with a programmable offset When a trigger is signaled the value of the bunch counter trigger time tag is loaded into the trigger FIFO The effective trigger latency using this scheme e
21. channel 174 hit select error R W monitoring generation of hit select 175 hit load R W monitoring generation of hit load see Appendix A for internal format matching state 10 0 state waiting state write event header state write occupancy state active state write mask flags state write error state write event trailer state generating lost event header state generating lost event trailer state waiting for separator state write separator 3 3 7 ASD Control 00000000001 00000000010 00000000100 00000001000 00000010000 00000100000 00001000000 00010000000 00100000000 01000000000 10000000000 To control ASD chip developed by Harvard Univ ASD control signals are implemented in the AMT Simulated timing diagram is shown in Fig 15 and its simulation model is shown in Fig 14 Unfortunately both chip has TDO register so 2TDO registers are connected serially at the end of the scan chain Thus the scan chain looks 1 additional scan register If the TDO register in the ASD is removed the timing diagram will be Fig 16 ASDOUT tdi ASDLOAD tdo ASDIN ASDDOWN ASDCLK tms tck gt trstb Fig 14 AMT ASD control simulation model There are 2 registers at the end of scan chain Therefore there looks 1 additional scan register exist in the chain wave trstb wave wave tms wave tdi wave tdo tap_state ir update reg wave do28 31 3 wave do28 31 2
22. cles 88 924 usec 24 9501 ns in a beam revolution Thus the count roll over csr8 should be set 3563 deb in hex For the trigger latency of usec 120 clock bunch count offset should be set to 3564 120 3444 This is summarized in Table 8 Table 8 An example of register value setting Assumptions number of clock cycles per beam revolution CC 3564 cycles trigger latency TL 100 cycles 2 5 usec maximum drift time DT 32 cycles 800 ns register name contents typical value csrO 000 mask_window gt DT 32 020 csr2 search_window gt match_window 8 40 028 csr3 match window gt DT 32 020 csr4 reject_count_offset lt TL 8 mask_window 1 3423 D5F csr5 event count offset 0 000 csr6 bunch_count_offset 3463 D74 csr7 coarse_time_offset 0 000 csr8 count roll over 2 1 3563 DEB csr9 strobe 2 00 10 auto_reject match serial header a71 trailer leading 11 enable 11 csr12 enable sepa enable error 1FF csr13 enable channel 11 0 FFF 14 enable_channel 23 12 FFF 1 if enable mask 1 2 At present design count roll over must be greater than 800 window If the bunch count reset signal is applied in each cycle you can assume larger value for CC such as CC 4096 xxx window indicates window size so all these paramete
23. e command in each period of three clock periods A command is signaled with a start bit followed by two bits determining the command When using encoded trigger and resets an additional latency of three clock periods is introduced by the decoding compared to the use of the direct individual trigger and resets Selection between the encoded signals and the direct signals are schematically shown in Fig 6 Table 1 Encoded signal bit pattern Meaning bit 210 Trigger 100 Bunch count reset 110 Global reset 101 Event count reset 111 80MHz Clock 40MHz Clock 1k80M 1 40 JTAG controller reset CSR reset global_reset encoded signal ENCCONTP enable mreset code 2S enccont trigger esr11 3 ENCCONTM d bunch_count_reset z clock global_reset Sipe event_count_reset TRIGP gt gt trigger TRIGM o fae L master_reset BUNCHRSTP C gt bunch count reset BUNCHRSTM enable_mreset_evrst esr11 1 RE EVENTRSTP C gt event count reset EVENTRSTM o E enable_direct RESETP esrO 5 RESETM mi Fig 6 Simplified diagram of the clock reset and trigger signals 2 7 2 Event count reset An event count reset loads the programmed event_count_offset into the event ID counter In addition a separator can be injected into the L1 buffer and the trigger FIFO if enable_sepa_evrst is set 2 7 3 Bun
24. e enable enable enable enable enable enable enable lloccup match mask relative serial header trailer rejected pair trailing leading reject readou o 131 i 130 129 128 127 4126 i 1125 124 123 122 121 120 CSR11 enable enable_ enable_ enable_ inclk_b enable enable enable enable_ enable_ enable rofull llfull trfull_ errmark oost ermark errmark llovr mreset_ resetcb_ mreset setcount reject reject reject rejected _Ovr detect code sepa evrst berst 0 00 0 143 i 142 141 4140 139 138 137 136 135 134 133 132 CSR12 enable enable_ enable enable sep sepa sepa error 8 0 readout bcrst evrst 0 0 0 IFF 155 i 154 153 152 144 CSR13 enable_channel 11 0 FFF 167 156 CSR14 enable_channel 23 12 FFF 179 168 CSR15 general_out 1 1 0 0 initial value at reset JTAG bit No 3 1 1 CSRO pll_multi 1 0 The frequency ration between the external clock and the internal ring oscillator frequency is determined by these bits as shown below pll_multi 1 pll_multi 0 Input frequency Synthesized frequency clkout_mode 1 0 CLKOUT pin mode 0 Start_Sync Synchronized output of the START signal 1 40MHz clk PLL clock 2 output This is the system clock used in most of
25. ed at hit 2 3 Channel Buffer Each channel can store 4 TDC measurements before being written into the common 1 buffer The channel buffer is implemented as a FIFO controlled by an asynchronous channel controller The channel controller can be programmed to digitize individual leading and or trailing edges of the hit signal Alternatively the channel controller can produce paired measurements consisting of one leading edge and the corresponding trailing edge In paired measurement the edge data are always handled as pair so you can think the channel buffer is 2 words depth in this case If the channel buffer is full when a new hit arrives it will be ignored If the enable_rejected 1 and enable_match 0 the information of the rejected hit is transferred as soon as the channel buffer is available The data of the rejected has hit error flag and time when the buffer becomes available so the time is not relevant to hit time For the hits stored in the channel buffers to be written into the clock synchronous L1 buffer a synchronization of the status signals from the channel buffers is performed Double synchronizers are used to prevent any metastable state to propagate to the rest of the chip running synchronously at 40 MHz When paired measurements of a leading and a trailing edge is performed the two measurements are taken off the channel buffer as one combined measurement 2 4 Encoder When a hit has been detected on a channel the corre
26. ejection when read out FIFO full see section 2 8 3 1 13 CSR12 enable_error 8 0 ERROR signal is asserted if corresponding enable_error bit is set enable_sepa_evrst enable generate separator on event reset enable sepa bcrst enable generate separator on bunch count reset enable sepa readout enable read out of internal separators debugging 3 1 14 CSR13 14 enable channel 23 0 enable individual channel inputs 3 1 15 CSRI5 general out 11 0 12 bit general purpose outputs The value written to this register is available from the DIO23 DIO12 pins if ASDMOD pin is set to high level JT AG access to this register is independent from CSRO 14 JTAG path 3 2 Status registers Table 5 Bit assignment of the status registers all these registers are read only 11 10 9 8 7 6 5 4 3 2 1 0 5 16 rfifo_ 04 _ empty full arity flags 0 0 Q1 0 9 8 0 CSR17 ln H ln 1 II empty nearly ver over write address full cover flow 0 Im ol 0 0 23 22 21 20 19 12 CSRIS tfifo tfifo running m empty nearly ful read address full 0 0 35 434 33 32 31 24 CSR19 coarse tfifo_ counter start_address Im 0 0 0 47 46 44 43 36 CSR20 coarse_counter 12 1 0 59 48 CSR21 general_ 0 0 rfifo_ in 3 0 occupancy 5 0 DIO27 24 0 0
27. elect 2 was modified not to generate any strobe signal 3 bug fixed in error marking circuit 4 CSR interface through 12 bit parallel bus was modified to perform more stable operation 5 ID was changed to 38b85031 6 Modified not to interfere clock and reset signals by boundary scan 7 rejected_hit_error is masked in enable_reject 0 8 Modified to reset JTAG controller with reset signal 9 Add one wait to service_request to do fair arbitration 0 3 Known Bug s in AMT 3 1 Introduction The ATLAS Muon TDC AMT is a Time to Digital Converter TDC designed for the Monitored Drift Tubes MDT of the ATLAS muon detector It is processed in Toshiba 0 3 um CMOS Sea of Gate Technology TC220G Basic requirements on the AMT chip were summarized in ATLAS note MUON NO 179 May 1997 by J Christiansen and Y Arai Then AMT O 1 was designed in a 0 7 um full custom CMOS process based on the 32 channel TDC for the quick test of front end electronics and MDT chambers On the other hand it was decided to use a Toshiba s 0 3 um CMOS process for a final production To develop and test many critical elements in the 0 3 um process a TEG Test Element Group chip AMT TEG 2 was designed fabricated and tested successfully at KEK The AMT TEG was processed in a new 0 3 um process which will be used in final mass production The present AMT 1 design is based on the AMT 0 but many modifications are done since the technolog
28. ex When several hits are waiting in the channel buffers an arbitration between pending requests is performed New hits are only allowed to enter into the active request queue when all pending requests in the queue have been serviced Arbitration between channels in the active request queue is done with a simple hardwired priority channel 0 highest priority channel 23 lowest priority The fact that new requests only are accepted in the active request queue when the queue is empty enables all channels to get fair access to the L1 buffer 2 5 L1 Buffer The L1 buffer is 256 hits deep and is written into like a circular buffer Reading from the buffer is random access such that the trigger matching can search for data belonging to the received triggers If the L1 buffer runs full the latest written hit will be marked with a special full flag When the buffer recovers from being full the first arriving hit will be marked with a full recover flag These flags are used by the following trigger matching to identify events which may have lost hits because of the buffer being full 2 6 Trigger Matching Trigger matching is performed as a time match between a trigger time tag and the time measurements them selves The trigger time tag is taken from the trigger FIFO and the time measurements are taken from the L1 buffer Hits matching the trigger are passed to the read out FIFO Optionally the trigger time tag can be subtracted from the measuremen
29. f rejected hit If the channel buffer is full when a new hit arrives it will be ignored If this bit is set the information of the rejected hit is transferred as soon as the channel buffer is available even there 1s no hit see section 2 3 enable trailer in read out data enable header in read out data enable serial read out otherwise parallel read out enable read out of relative time to trigger time tag enable search and read out of mask flags enable trigger matching enable read out of 11 occupancy for each event use for debugging enable of automatic rejection of hits from the 1 1 buffer see section 2 6 enable all time counters to be reset on bunch count reset enable master reset on event reset enable channel buffer reset when a separator is inserted enable master reset from global reset of the encoded control enable L1 buffer overflow detection If this bit is not set write pointer of the L1 bufer will pass read pointer if the L1 buffer become full enable error marking events when L1 buffer overflows effective only in enable matching 0 enable error mark event if rejected hit seen effective only in enable matching 0 double the internal clock frequency Only for test enable error mark word if hard error exists enable event data rejection if trigger FIFO nearly full see section 2 8 enable event data rejection if L1 buffer nearly full see section 2 8 enable_rofull_reject enable event data r
30. hannels of inputs Table 1 summarizes the main features of the AMT 3 chip 2 1 Table 1 AMT 3 MAIN FEATURES System Clock Frequency is 40 MHz otherwise noted Least Time Count Time Resolution Dynamic range Integral Non Linearity Differential Non Linearity Difference between channels e Stability Input Clock Frequency PLL mode Internal System Clock No of Channels Level 1 Buffer Read out Buffer Trigger Buffer Double Hit Resolution Max recommended Hit rate Hit Input Level Supply Voltage Temperature range Process Package 0 78 ns bit rising edge 0 78 100ns bit falling edge RMS z 300 ps rising edge RMS 300 2905 falling edges 13 4 17 bit 102 4 usec Max 80 ps Max 80 ps Maximum one time bin lt 0 1 LSB 3 0 3 6 V 0 70 C 10 70 MHz x2 mode 1 x2 x4 or x8 Input Clock x PLL mode 2 24 Channels 256 words 64 words 8 words 10 ns 500 KHz per channel Low Voltage Differential Signaling LVDS Internal 100 Ohm termination 3 3 0 3 lt 200 mA 0 85 Deg Cent 0 3 um CMOS Sea of Gate Toshiba TC220G die size 6 mm x 6 mm 0 5 mm lead pitch 144 pin plastic QFP Fine Time Measurement The original idea of the TDC which use internal gate delay as a fine time element and stabilize the element with a feedback circuit was born in 1986 3 The chip was called TMC Time Memory Cell c
31. hip Initial TMC chip use a DLL Delay Locked Circuit technique and then PLL Phase Locked Loop technique has been used in recent chips In the PLL version we have been using a new kind of voltage controlled ring oscillator asymmetric ring oscillator Fig 2 To obtain 1 ns timing resolution 16 taps are extracted from the oscillator Fig 2 shows a simplified schematics and its timing diagram of the asymmetric ring oscillator Fig 2 only shows 8 stages but the actual chip implements 16 stages The asymmetric ring oscillator was creates equally spaced even number 16 of timing signals The PLL circuit comprises a phase frequency detector PFD a charge pump a loop filter LPF and a voltage controlled oscillator VCO asymmetric ring oscillator in this case An external capacitor Cvg is required in the loop filter The PLL has divide by 2 4 and 8 counter thus the frequency of the VCO can be either the same or the multiplied by 2 4 or 8 of the input frequency The propagation delay of the delay elements that determine the oscillation frequency of the VCO is controlled through a control voltage VGN When a hit occurs the state of the 16 taps and coarse counter are latched into a hit register a VGN b to B t1 D E F 13 H 5 Fig 2 a Asymmetric ring oscillator b extracted timing signal 2 2 Coarse Counter The dynamic range of the fine time measurement extracted from
32. ime offset and the bunch count offset The exact relation ship is latency coarse_time_offset bunch_count_offset modulus 2 A simple example is given to illustrate this A coarse_time_offset of 100 Hex decimal 256 and a bunch_count_offset of 000 Hex gives an effective trigger latency of 100 Hex decimal 256 Normally it is preferable to have a coarse time offset of zero and in this case the trigger count offset must be chosen to 000 Hex 100 Hex modulus 2 FOO Hex C Alignment between trigger time tag and reject count offset The workings of the reject counter is very similar to the trigger time tag counter The difference between the course time counter offset and the reject counter offset is used to detect when an event has become older than a specified reject limit The rejection limit expression is coarse time offset reject count offset modulus 2 The rejection limit should be set equal to the trigger latency plus a small safety margin In case the extraction of masking hit flags are required the reject limit should be set larger than the trigger latency masking window safety margin For a trigger latency of 100 Hex same as in example in the section above a reject limit of 108 Hex can be considered a good choice no mask detection This transforms into a reject count offset of EF8 Hex when a coarse time offset of zero is used 4 1 Example of Offset Setting In the LHC experiments there are 3564 clock cy
33. ing of hit measurements into the common L1 buffer A trigger matching function can select events related to a trigger The trigger information consisting of a trigger time tag and an event ID can be stored temporarily in an eight words deep trigger FIFO Measurements matched to the trigger are passed to a 64 words deep read out FIFO or A time window of programmable size is available for the trigger matching to accommodate the time spread of hits related to the same event Optionally channels with hits in a time window before the trigger can be flagged The trigger time tag can optionally be subtracted from the measurements so only time measurements relative to the trigger needs to be read out Accepted data can be read out in a direct parallel format be serialized at a programmable frequency Control amp Data I O JTAG signals JTAG TAP Controller i Control Registers pach A L Parallel to Serial Converter e 32 Status Registers Serial Strobe E L ReadoutLID Built In FIFO Self Test ew li 1 Trigger Al Even Couer rime Trigger Time Trigger 12b FIFO Trigger Matching Ek Channel Pulse Width Edge Time Read Pointer p eil e 78 Level 1 Buffer o o 256W Channel Controller Channel Buffer 4W Inputs 24ch Ka Clock J Fig 1 Block diagram of the AMT 3 2 Circuit Description Fig 1 shows a block diagram of the AMT 3 chip There are 24 c
34. l situations all these controls has strong relations Data Oui Readout Trigger FIFO 5 trigger machirng Trigger FIFO L1 Buttes Channel Butter Fig 18 Buffer controls A Channel buffer overflow The depth of the channel buffer is 4 If the channel buffer is full when a new hit arrives the new hit will be rejected discarded The occurrence of the rejection is reported by E flag of a data word if enable rejected bit is set Otherwise user can not detect the occurence of the rejection The information of the rejected hit is transferred as soon as the channel buffer is available Therfore the time of the data with E flag is the time when the buffer is available and not actual data Therefore the data should be discarded after error reporting In combined measurement enable pairz1 there is E flag in the data word but the rejected hit can appear in the data if enable rejected bit is set This may cause some confusion so in this mode enable rejected bit should not be set B L1 buffer overflow There are 256 words depth in the L1 buffer If enable detect bit is not set there is no pointer control so L1 write pointer may pass the L1 read pointer This bit should be set in normal use If the L1 buffer becomes full 2 253words L1 buffer overflow bit is set for next data and further data will be discarded When the data size becomes less than 251 words the situation will recover from o
35. logics 2 80 MHz clk PLL clock outpuut 3 Coarse Counter Carry Carry outout of the Coarse Counter This can be used to extend the time range disable_ringosc Stop the oscillation of the ring oscillator and disable charge pump circuit of the PLL enable_direct enable direct input pins 0 trigger reset signals are came from encoded input encontp enccontm trigger reset signals are came from direct input pins trigp trigm bunchrstp bunchrstm eventrstp eventrstm test invert automatic inversion of test pattern in test mode test mode enable test mode enable errrst bcrevr enable error reset when bunch count reset or event count reset is came disable encode disable fine time encoder and output 111 error reset clear error bits in CSR16 8 0 global reset Global reset of the TDC This reset does not clear the contents of the setup registers 3 1 2 CSRI mask window 11 0 mask window in number of clock cycles 3 1 3 CSR2 search window 11 0 search window in number of clock cycles 3 1 4 CSR3 match window 11 0 matching window in number of clock cycles 3 1 5 CSR4 reject count offset 11 0 rejection counter offset 3 1 6 CSR5 event count offset 11 0 event number offset 3 1 7 CSR6 bunch_count_offset 11 0 trigger time tag counter offset 3 1 8 CSR7 coarse_time_offset 11 0 coarse time counter offset 3 1 9 CSR8 count_roll_over 11 0 counter roll over value 3 1 10 CSR9
36. n ch micdigital amt htm 2 AMT chips web page http atlas kek jp tdc 3 Y Arai and T Ohsugi An Idea of Deadtimeless Readout System by Using Time Memory Cell Proceedings of the Summer Study on the Physics of the Superconductiong Supercollider Snowmass 1986 p 455 457 4 Y Arai and J Christiansen Requirements and Specifications of the TDC for the ATLAS Precision Muon Tracker ATLAS Internal note MUON NO 179 14 May 1997 Also available from http atlas kek jp tdc Documents TDCspec pdf
37. n when the hits have not been written into the L1 buffer in strict temporal order For normal applications it is sufficient to make the search window 8 larger than the match window The search window should be extended for applications with very high hit rates or in case paired measurements of wide pulses are performed a paired measurement is not written into the L1 buffer before both leading and trailing edge have been measured To prevent buffer overflow and to speed up the search time an automatic reject function can reject hits older than a specified limit when no triggers are waiting in the trigger FIFO and enable auto reject bit is set A separate reject counter runs with a programmable offset to detect hits to reject The trigger matching can optionally search a time window before the trigger for hits which may have masked hits in the match window if enable mask bit is set A channel having a hit within the specified mask window will set its mask flag The mask flags for all channels are in the end of the trigger matching process written into the read out FIFO if one or more mask flags have been set In case an error condition L1 buffer overflow Trigger FIFO overflow memory parity error etc has been detected during the trigger matching a special word with error flags is generated if enable_errmark and corresponding enable_error bits are set All data belonging to an event is written into the read out FIFO with a header and a trailer
38. of clock periods that the GETDATA signal is asserted is used to determine the word count for the event available in the global trailer 2 9 2 Serial read out The accepted TDC data can be transmitted serially over twisted pairs using LVDS signals by setting enable_serial 1 Data is transmitted in words of 32 bits with a start bit set to one and followed by a parity bit and 2 stop bit The parity is odd parity exclusive OR of the 32 data bits If number of 1 bits in the data is odd the parity bit will be 1 The serialization speed is programmable from 80 to 10 Mbits s Serial clock 36 bits word Fig 9 Serial frame format with start bit and parity bit In addition to the serialized data an LVDS pair can carry strobe information in a programmable format as shown in Fig 9 Leading Strobe Direct serializing clock to strobe data on rising edge DS Strobe DS strobe format as specified for transputer serial links DS strobe only changes value when no change of serial data is observed For each format there are two modes one is continuous strobe regardless of data existence another mode generate strobe signal only when data is available Serial data DS Strobe strobe_select 0 DS Strobe strobe_select 1 Leading Strobe strobe_select 2 Leading Strobe strobe_select 3 2 9 3 Data format Data Packet stop stari Data J LI LE LI EJ LI I
39. ol the chip functionality The STATUS registers are read only registers which shows chip statuses There are 15 Control registers CSRO 14 and 6 Status registers CSR16 21 These registers are accessible from 12 bit bus DIO 11 0 or through JTAG interface DIO 11 0 RA 4 0 WR CS TDO xcz TDI Built In Self Test circuit Device ID register Instruction register To ASD gt Control w gt NN NN TCK TAP Controller TRSTB Fig 11 Structure of JTAG CSR registers 3 1 Control registers Table 4 Bit assignment of the control registers BIT 11 10 9 8 7 6 5 4 3 2 1 0 CSRO global_r error disable_ enable_ test test enable disable clkout pl multi eset reset encode errst mode invert direct ringosc mode wew O O 0 11 010 0 8 7 6 5 4 0 1 0 i i B 3 2 CSRI mask window 0 23 12 CSR2 search window 0 3524 CSR3 match window 0 47 36 CSR4 reject_count_offset 0 59 48 CSR5 event count offset 0 71 60 CSR6 bunch_count_offset 0 83 72 CSR7 coarse_time_offset 0 95 84 CSR8 count_roll_over FFF 107 96 CSR9 strobe_select readout_speed width_select error_ tdc_id 0 0 test 0 0 119 118 117 116 115 113 112 111 10 _ 8j CSRIO enable enable enable enable enabl
40. quals the difference between the coarse_time_offset and the bunch_count_offset bunch count offset event count offset count roll over event count reset trigger bunch count reset 40MHz clock Load Event Count d 1034 FIFO Trigger Trigger lost time flag tag Trigger Matching Circuit Fig 7 Generation of trigger data If the trigger FIFO runs full the trigger time tags of following events will be lost The trigger interface keeps track of how many triggers have been lost so the event synchronization in the trigger matching and the DAQ system is never lost For each event with a lost trigger time tag the trigger matching will generate an event with correct event id and a special error flag signaling that the whole event has been lost 2 7 6 Separators The TDC is capable of running continuously even when bunch count resets and event count resets are issued Matching of triggers and hits across bunch count resets different machine cycles are handled automatically if the correct roll over value have been programmed Alternatively it is possible to insert special separators in the trigger FIFO and the L1 buffer when a bunch count reset an event count reset have been issued enable sepa bcrst or enable sepa evrst These will make sure that hits and triggers from different event count or bunch count periods machine cycles never are mixed In this mode it is not pos
41. r is positive value 0x001 means 1 clock tick window and OxFFF means 4095 clock tick window xxx_offset indicates relative time between each counters These offset is loaded into respective counters when bunch count reset is asserted All counters are roll over at value count roll over Thus larger value than count roll over has no meaning for the window size and the offsets 5 Appendix A Internal Data Format Channel Buffer Tu 424140 323130 40 323130 282726 181716 18 17 16 151413 3210 14 13 3210 re EN vernier parity parity gt Ste 888786 787776 87 86 78 77 76 747372 6046362 73 72 60463 62 6160 616059 444546 44 45 46 EM coarse2 coarsel vernier parity parity if enable pair 0 edge 0 trailing edge edge 1 leading edge if enable pair 1 edge 0 trailing edge found edge 1 trailing edge not found rejected data is rejected since the channel buffer is full Level 1 Buffer buffer overflow see below overflow stored overflow level 1 buffer overflow start buffer_size gt 253 buffer overflow set to 1 when overflow occured and kept 1 until overflow recover buffer size lt 251 make separator stored separator flag data 31 0 0 parity parity of data 34 0 enable pair 0 29 28 27 26 25 24 23 22 21 20 19 18 16 15 14 13 1211109876543210 enable
42. sible to match hits across bunch count periods This separator can be readout if enable sepa readout bit is set This mechanism is conceptually shown in Fig 8 Data Out Trigger read out FIFO Y trigger eee maching Trigger FIFO HA 1 Bunch Count Reset or Event Count Reset Pt buffer 2350 Hit Time Fig 8 Conceptual view of the separator insertion and matching 2 8 Read out FIFO and Buffer Full Control The read out FIFO is 64 words deep and its main function is to enable one event to be read out while another is being processed in the trigger matching If the read out FIFO runs full there are several options of how this will be handled Back propagate enable rofull 0 enable_l1full_reject 0 enable trfull reject 0 The trigger matching process will be blocked until new space is available in the read out FIFO When this occurs the 1 1 buffer and the trigger FIFO will be forced to buffer more data If this situation is maintained for extended periods the 1 1 buffer or the trigger FIFO will finally become full and the measurement is stopped Nearly full reject enable 11101 reject 1 and or enable trfull reject 1 In this mode the trigger matching will be blocked if either the L1 buffer is nearly full 256 64 191 words occupied or the trigger FIFO is nearly full contains 4 triggers If this occurs event data will be rejected to prevent the 1 1 buffer and
43. sponding channel buffer is selected the time measurement done with the ring oscillator is encoded into binary form vernier time the correct coarse count value is selected and the complete time measurement is written into the L1 buffer together with a channel identifier Although the ring oscillator and the coarse counter runs at 80 MHz the base LHC clock is 40 MHz and bunch number is counted at 40 MHz Most of logics in the AMT are designed to run at 40 MHz To shift from 80 MHz to 40MHz regime we would like to define different name to measured time We call the upper 12 bit of the coarse counter as a coarse time and the LSB of the coarse counter plus the vernier time as a fine time Thus the coarse time will be equivalent to the bunch count Coarse Counter 13 bit Ring Oscillator it 16 Vernier Time 4 bit Coarse Time Fine Time 12 bit 5 bit Fig 4 Definition of coarse time and fine time In case a paired measurement of leading and trailing edge has been performed the complete time measurement of the leading edge plus a 8 bit pulse width is written into the L1 buffer The 8 bit pulse width is extracted from the leading and trailing edge measurement taking into account the programmed roll over value The resolution of the width measurement is programmable In case the pulse width is larger than what can be represented with a 8 bit number the width will be forced to a value of FF H
44. t is loaded with its offset value The TDC also contains internal delay paths of the clock and its channel inputs which influences the actual time measurement obtained These effects can be considered as a time shift in relation to the ideal measurement The time shifts of individual channels may be slightly different but care has been taken to insure that the channel differences are below the bin size 1 ns of the TDC The time shift of the measurements also have some variation from chip to chip and variations with supply voltage and temperature These variations have also been kept below the bin size of the TDC by balancing the delay paths of the clock and the channels In Fig 17 a hit signal is defined such that the time measurement equals zero coarse_time_offset 0 The delay from the rising edge of the clock where the bunch reset signal was asserted to the rising edge of the hit signal is for a typical chip 55ns two clock periods plus 5ns external clock d L L L bunch_count i I _reset 88 a Hit Fig 17 Definition of reference time measurement B Alignment between coarse time count and trigger time tag To perform an exact trigger matching the basic time measurement must be aligned with the positive trigger signal taking into account the actual latency of the trigger decision The effective trigger latency in number of clock cycles equals the difference between the coarse t
45. tdc_id 3 0 TDC identifier This ID is attached to the output data error_test set all error flags to test error circuit Don t set this bit in normal operation width_select 2 0 Set pulse width resolution in pair measurement width select width output resolution max width full_width 7 0 0 78125 ns 200 ns 0 2 ful 4 5 6 at 40 MHz clock readout_speed 1 0 readout_speed speed 0 40Mbps 1 20 Mbps 2 10 Mbps 3 80 Mbps strobe_select 1 0 enable_serial strobe_select strobe mode gated DS strobe continuous DS strobe no strobe signal continuous leading edge clock Continuous parallel output oj IN i Handshaked parallel output 3 1 11 CSR10 enable_leading enable leading edge measurement enable_trailing enable trailing edge measurement enable_pair enable_rejected enable_trailer enable_header enable_serial enable_relative enable_mask enable_match enable_lloccup_readout enable_auto_reject 3 1 12 CSR11 enable setcount bcrst enable mreset evrst enable resetcb sepa enable mreset code enable llovr detect enable ovr enable errmark rejected inclk boost enable errmark enable trfull reject enable reject enable pair leading and trailing edge measurement If this bit is set enable leading and enable trailing bits are masked enable force generation o
46. the state of the VCO is expanded by storing the state of a clock synchronous counter The hit signal may though arrive asynchronously to the clocking and the coarse counter may be in the middle of changing its value when the hit arrives To circumvent this problem two count values 1 2 a clock cycle out of phase are stored when the hit arrives Fig 3 Based on the fine time measurement from the PLL one of the two count values will be selected such that a correct coarse count value is always obtained The coarse counter has 13 bits and is loaded with a programmable coarse time offset the LSB is always 0 at reset The coarse counter of the TDC will in ATLAS be clocked by the two times higher frequency than the bunch crossing signal thereby the upper 12 bit of the coarse counter becoming a bunch count ID of the measurement The bunch structure of LHC is not compatible with the natural binary roll over of the 12 coarse time counter The bunch counter can therefore be reset separately by the bunch count reset signal and the counter can be programmed to roll over to zero at a programmed value The programmed value of this roll over is also used in the trigger matching to match triggers and hits across LHC machine cycles coarse count offset bunch count reset Load Coarse counter paso ove om Clock c PLL select Coarse Gaunt Fig 3 Phase shifted coarse counters load
47. the trigger FIFO to overflow The event header and event trailer data will never be rejected as this would mean the loss of event synchronization in the DAQ system Any event which have lost data in this way will be marked with an error flag Reject enable rofull reject 1 As soon as the read out FIFO full event data not event headers and trailers will be rejected Any loss of data will be signaled with an error flag 2 9 Read out Interface All accepted data from the TDC can be read out via a parallel or serial read out interface in words of 32 bits The event data from a chip typically consists of a event header if enabled accepted time measurements mask flags if enabled error flags if any error detected for event being read out and finally a event trailer 1f enabled 2 9 1 Parallel read out Read out of parallel data from the TDC is enabled by setting enable sera and performed via clock synchronous bus Several TDC s may share one read out bus and each TDC will selected with CS chip select and DSPACE data space signals The read out of individual hits are controlled by DREADY data ready GETDATA get data handshake If the GETDATA signal is constantly held active independent of DREADY it is interpreted as the read out can be performed at the full speed of the TDC The effective read out speed can be slowed down by using the DREADY GETDATA handshake protocol to introduce wait cycles The number
48. ts enable relative 1 such that all time measurements read out are referenced to the time bunch crossing when the event of interest occurred reject coarse tima count affsat Bunch count offset search window mask window Fig 5 Trigger latency and trigger window related to hits on channels There are 3 time counters coarse time trigger time and reject time counters A match between the trigger and a hit is detected within a programmable time window Fig 5 if enable match is set The trigger is defined as the coarse time count bunch count ID when the event of interest occurred AII hits from this trigger time until the trigger time plus the matching window will be considered as matching the trigger The trigger matching being based on the coarse time means that the resolution of the trigger matching is one clock cycle 40MHz and that the trigger matching window is also specified in steps of clock cycles The maximum trigger latency which can be accommodated by this scheme equals half the maximum coarse time count 2 2 2048 clock cycles 51 us The trigger matching function is capable of working across roll over in all its internal time counters For a paired measurement the trigger matching is performed on the leading edge of the input pulse The search for hits matching a trigger is performed within an extended search window to guarantee that all matching hits are found eve
49. verflow to normal state The overflow event will have an error word with L1 buffer overflow bit 9 flag if the overflow occur in corresponding matching mask windows C Trigger FIFO overflow Trigger FIFO is 8 words depth If the trigger FIFO runs full the trigger time tags of following events will be lost The trigger interface keeps track of how many triggers have been lost so the event synchronization in the trigger matching and the DAQ system is never lost A full flag in the trigger FIFO together with the event number of the triggers are used to detect the loss of triggers If a positive trigger is signaled when the trigger FIFO is full the trigger interface stores the fact that one or several triggers have been lost As soon as the trigger FIFO is not any more full the event number of the latest lost trigger is written to the FIFO together with a trigger lost flag and bunch id of that time For each event with a lost trigger time tag the trigger matching will generate an event with correct event id and an error word with Trigger FIFO overflow bit 10 flag However the bunch id of the header indicates the time when the overflow was recovered D Trigger Matching and Readout FIFO overflow The trigger matching circuit continuously compares data with reject time counter and if the data is older than the reject time the data will be removed from the L1 buffer The readout FIFO is 64 words deep In addition to data and error words
50. y is different and many experience was obtained After the circuit test of AMT 1 AMT 2 chip was developed and produced on May 2001 AMT 2 chips were used in H8 test beam experiment and also tested at Univ of Michigan In these tests a serious bug was found in trigger matching circuit This bug and several other minor bugs are fixed in AMT 3 which was produced on Oct 2003 A time bin size 0 78 ns is obtained using the basic gate delay as the base for the time measurement This scheme prevents the use of very high speed clocks in the circuit and results in a low power device 20 mW channel The gate delay of CMOS devices normally have very large variations as function of process voltage and temperature In this TDC a phase locked loop PLL circuit is implemented to stabilize the gate delay Oscillation frequency of the internal ring oscillator is multiplied by two with the PLL thus generate 80 MHz clock This oscillator has 16 taps and time difference of two taps are exactly 1 16 of the clock period When a hit enters state of these 16 taps are latched and generate a fine time The fine time measurement is extended by a 13 bit coarse counter Although the PLL clock is 80 MHz most of the logic runs at 40MHz which is same as that of the LHC clock Each channel can buffer 4 measurements until they can be written into a common 256 words deep level 1 buffer The individual channel buffers works as small derandomizer buffers before the merg
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