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Extract of MSP430x1xx Family User's Guide (SLAU049E)

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1. r7 1 3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources The benefits of embedded emulation include Lj Unobtrusive development and debug with full speed execution breakpoints and single steps in an application are supported Development is in system subject to the same characteristics as the final application 1 Mixed signal integrity is preserved and not subject to cabling interference Introduction 1 3 Address Space 1 4 Address Space The MSP430 von Neumann architecture has one address space shared with special function registers SFRs peripherals RAM and Flash ROM memory as shown in Figure 1 2 See the device specific data sheets for specific memory maps Code access are always performed on even addresses Data can be accessed as bytes or words The addressable memory space is 64 KB with future expansion planned Figure 1 2 Memory OFFFFh OFFEOh OFFDFh 0200h 01FFh 0100h OFFh 010h OFh Oh 1 4 1 Flash ROM 1 4 22 RAM 1 4 Introduction Access Interrupt Vector Table Word Byte Flash ROM Word Byte Word Byte 16 Bit Peripheral Modules word 8 Bit Peripheral Modules Byte Special Function Registers Byte The start addre
2. gt LEXTICLK o Divider 1 2 4 8 OSCOFF XTS ACLK Auxillary Clock XIN E XT1 Off XOUT SELMx DIVMx CPUOFF ee 1 veik Divider 1 2 4 8 2 MCLK XT2IN Main System Clock XT2OUT xT2 Oscillator Y 4 MODx DCOR SCGO RSELx SELS DIVSx SCG1 off DC Generator Divider 1 2 4 8 P2 5 Rosc SMCLK Sub System Clock Note XT2 Oscillator The XT2 Oscillator is not present on MSP430x11xx MSP430x12xx devices The LFXT1CLK is used in place of XT2CLK Basic Clock Module 4 3 Basic Clock Module Registers 4 2 Basic Clock Module Registers The basic clock module registers are listed in Table 4 1 Table 4 1 Basic Clock Module Registers Register Short Form Register Type Address Initial State DCO control register DCOCTL Read write 056 060h with PUC Basic clock system control 1 BCSCTL1 Read write 057h 084h with PUC Basic clock system control 2 BCSCTL2 Read write 058h Reset with POR SFR interrupt enable register 1 IE1 Read write 000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 002h Reset with PUC 4 4 Basic Clock Module Basic Clock Module Registers DCOCTL DCO Control Register DCOx MODx Bits 7 5 Bits 4 0 DCO frequency select These bits select which of the eight discrete DCO frequencies of the RSELx setting is selected Modulator selection These bits d
3. 2 2 Principles for Low Power 2 3 Connection of Unused RISC 16 Bit CPU eee eae ee Sere dh CPU Introduction ss te teehee eke aa D aa 31 1 Status Register SR 3 1 2 Constant Generator Registers CG1 and CG2 Basic Clock Module cbe iere e 4 1 Basic Clock Module Introduction 4 2 Basic Clock Module Registers Flash Memory 5 1 Flash Memory Introduction 5 2 Flash Memory Segmentation 5 3 Flash Memory Registers Supply Voltage Supervisor 61 SVS Introduction 2 22 222222 62 SVS Registers 22222902224 Ae ae eee de Hardware Multiplier 7 1 Hardware Multiplier Introduction 7 2 Hardware Multiplier Registers Controller o ram NER ED ed teem ua sau oe 81 Introduction 82 DMA REQISTS S sion AA AA a vii Contents 9 10 11 12 13 14
4. 14 4 14 1 USART Introduction SPI Mode 14 1 USART Introduction SPI Mode In synchronous mode the USART connects the MSP430 to an external system via three or four pins SIMO SOMI UCLK and STE SPI mode is selected when the SYNC bit is set and the 2 bit is cleared SPI mode features include 7 or 8 bit data length 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer registers Selectable UCLK polarity and phase control Programmable UCLK frequency in master mode Ll Ll E E Li Lil Ll E Independent interrupt capability for receive and transmit Figure 14 1 shows the USART when configured for SPI mode 14 2 USART Peripheral Interface SP Mode USART Introduction SP Mode Figure 14 1 USART Block Diagram SPI Mode SWRST USPIEx URXEIE URXWIE SYNC 1 URXIFGx FE PE OE BRK Receive Control Receive Status Receiver Buffer UXRXBUF LISTEN MM SYNC RXERR RXWAKE Receiver Shift Register PENA 1 URXD SSEL1 SSELO SP CHAR UCLKS Baud Rate Generator 0 STE UCLKI ACLK e SMCLK 10 Prescaler Divider UxBRx UxBRx SMCLK Modulator UxMCTL UTXD SP CHAR PEV PENA Transmit Shift Register Transmit Buffer UxTXBUF Transmit Control SWRST USPIEx TXEPT STC i s Clock Phase and Polarity Refer to the device specific datasheet for SFH locations
5. TEXAS INSTRUMENTS MSP430x1xx Family User s Guide Extract 2005 Mixed Signal Products SLAU169 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work r
6. 15 16 17 18 19 viii Digital VO ties m 9 1 Digital l O Introduction 9 2 Digital I O Registers WUC I OT UIs eh rs se cas ses ets deh aid sesh tate 10 1 Watchdog Timer Introduction 10 2 Watchdog Timer Registers 111 Timer A Introduction 11 2 Timer A Registers Hee ends debe DERXY end dae aem ed coa 121 Timer B Introduction 12 1 1 Similarities and Differences From Timer A 122 Timer Registers USART Peripheral Interface UART Mode 131 USART Introduction UART Mode 13 2 USART Registers UART Mode USART Peripheral Interface SPI Mode 141 USART Introduction SPI Mode 14 2 USART Registers SPI Mode USART Peripheral Interface I2C Mode 15 1 12C Module 15 2 12C Module 2 1 20 16 1 Comparator A Introduction 16 2 Comparator A Registers 1
7. ADC12MCTL15 ADC12 17 3 ADC 12 Registers 17 2 ADC12 Registers The ADC12 registers are listed in Table 17 1 Table 17 1 ADC 12 Registers Register ADC12 control register 0 ADC 12 control register 1 ADC 12 interrupt flag register ADC12 interrupt enable register ADC 12 interrupt vector word ADC12 memory 0 ADC12 memory 1 ADC12 memory 2 ADC12 memory 3 ADC12 memory 4 ADC12 memory 5 ADC12 memory 6 ADC12 memory 7 ADC12 memory 8 ADC12 memory 9 ADC12 memory 10 ADC12 memory 11 ADC12 memory 12 ADC12 memory 13 ADC12 memory 14 ADC12 memory 15 ADC12 memory control 0 ADC12 memory control 1 ADC12 memory control 2 ADC12 memory control 3 ADC12 memory control 4 ADC12 memory control 5 ADC12 memory control 6 ADC12 memory control 7 ADC12 memory control 8 ADC12 memory control 9 ADC12 memory control 10 ADC12 memory control 11 ADC12 memory control 12 ADC12 memory control 13 ADC12 memory control 14 ADC12 memory control 15 17 4 ADC12 Short Form ADC12CTLO ADC12CTL1 ADC12IFG ADC12IE ADC12IV ADC12MEMO ADC12MEM1 ADC12MEM2 ADC12MEM3 ADC12MEM4 ADC12MEM5 ADC12MEM6 ADC12MEM7 ADC12MEM8 ADC12MEM9 ADC12MEM10 ADC12MEM11 ADC12MEM12 ADC12MEM13 ADC12MEM14 ADC12MEM15 ADC12MCTLO ADC12MCTL1 ADC12MCTL2 ADC12MCTL3 ADC12MCTL4 ADC12MCTL5 ADC12MCTL6 ADC12MCTL7 ADC12MCTL8 ADC12MCTL9 ADC12MCTL10 ADC12MCTL11 ADC12MCTL12 ADC12MCTL13 ADC12MCTL14 ADC12MCTL15 Register Type Address Read write 01A0h Read write 01A2
8. IE 171 ADC12 Introduction 172 ADC12 Registers ADC O cress do sea ace ee are a cee ida ba 181 ADC10 Introduction 18 2 ADC10 Registers DAG12 22 E a 191 DAC12 Introduction 19 2 DAC12 Registers Chapter 1 Introduction This chapter describes the architecture of the MSP430 Topic Page 14 Architecture soc cece 005 1 2 1 2 Flexible Clock SySteni 1 2 1 3 Embedded 22 2222222 222222222244 1 3 Address Space esc coo 11 4 Architecture 1 1 Architecture The MSP430 incorporates a 16 bit RISC CPU peripherals and a flexible clock system that interconnect using a von Neumann common memory address bus MAB and memory data bus MDB Partnering a modern CPU with modular memory mapped analog and digital peripherals the MSP430 offers solutions for demanding mixed signal applications Key features of the MSP430x1xx family include Ultralow power architecture extends battery life 0 1 uA RAM retention 0 8 uA real time clock mode 250 uA MIPS active 1 High performance analog ideal for precision measurement gm 12 bit or 10 bit ADC 200 temperature sensor Vner B 12 bit dual DAC B Comparator gated timers f
9. Bits 7 6 UTXIE1 Bit 5 URXIE1 Bit 4 Bits 3 2 UTXIEO Bit 1 URXIEO Bit 0 MSP430x12xx devices only These bits may be used by other modules See device specific datasheet USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific datasheet USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled USART Peripheral Interface UART Mode 13 11 USART Registers UART Mode IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 rw 0 UTXIFGot Bit 7 URXIFGOt Bit 6 Bits 5 0 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet T Does not apply to MSP430x12xx devices See IFG2 for the MSP430x12xx USARTO interrupt flag bits IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 rw 1 rw 0 rw 1 rw 0 Bits UTXIFG1 Bit 5
10. DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2005 Texas Instruments Incorporated Preface Read This First About This Manual This manual is an extract of the MSP430x1xx Family User s Guide SLAU049 Related Documentation From Texas Instruments For related documentation see the web site http Avww ti com msp430 FCC Warning This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other en vironments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference Notational Conventions Program examples are shown in a special typeface Glossary
11. 030h 031h 032h 033h 034h 035h 036h 037h Register Type Read only Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Initial State Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Digital I O 9 3 Chapter 10 Watchdog Timer The watchdog timer is a 16 bit timer that can be used as a watchdog or as an interval timer This chapter describes the watchdog timer The watchdog timer is implemented in all MSP430x1xx devices Topic 10 1 Watchdog Timer Introduction 10 2 10 2 Watchdog Timer Registers 10 4 Watchdog Timer Introduction 10 1 Watchdog Timer Introduction 10 2 The primary function of the watchdog timer WDT module is to perform a controlled system restart after a software problem occurs If the selected time interval expires a system reset is generated If the wat
12. 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 ADC12 17 7 ADC 12 Registers ADC12 Bits ADC12 clock source select SSELx 4 3 00 ADC120SC 01 10 11 SMCLK CONSEQx Bits Conversion sequence mode select 2 1 00 Single channel single conversion 01 Sequence of channels 10 Repeatsingle channel 11 Repeat sequence of channels ADC12 Bit 0 ADC12 busy This bit indicates an active sample or conversion operation BUSY O No operation is active 1 A sequence sample or conversion is active ADC12MEMx ADC12 Conversion Memory Registers 15 14 13 12 11 i A E ro ro ro ro m um z 7 6 5 4 3 2 i rw rw rw rw iW Conversion Bits The 12 bit conversion results are right justified Bit 11 is the MSB Bits 15 12 Results 15 0 are always 0 Writing to the conversion memory registers will corrupt the results 17 8 ADC12 ADC 12 Registers ADC12MCTLx ADC12 Conversion Memory Control Registers Modifiable only when ENC 0 EOS Bit 7 End of sequence Indicates the last conversion in a sequence 0 1 Not end of sequence End of sequence SREFx Bits Select reference 6 4 000 001 010 011 100 Vn AVss VR Vrer and Vn AVss Verer and Vn AVss Vener and Vn AVss Vn AVcc and Vg Vner Vengr 101 Vg and Vp Vnge J Verer 110 Vn Vener and Vn VREF J Vener 111 Vg Vener and Vg Vner Vener INC
13. B SBC B sETZ SUB B SUBC B SWPB SXT TST B T XOR B dst src dst se dst src dst src dst src dst src dst src ast dst src dst dst dst abe abe abe abe abe abe abe abe src dst dst dst src dst T Emulated Instruction 3 6 Description Add C to destination Add source to destination Add source and C to destination AND source and destination Clear bits in destination Set bits in destination Test bits in destination Branch to destination Call destination Clear destination Clear Clear N Clear Z Compare source and destination Add C decimally to destination Add source and C decimally to dst Decrement destination Double decrement destination Disable interrupts Enable interrupts Increment destination Double increment destination Invert destination Jump if C set Jump if higher or same Jump if equal Jump if Z set Jump if greater or equal Jump if less Jump Jump if N set Jump if C not set Jump if lower Jump if not equal Jump if Z not set Move source to destination No operation Pop item from stack to destination Push source onto stack Return from subroutine Return from interrupt Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not C from destination Set C Set N Set Z Subtract source from destination Subtract source and not C from dst Swap
14. EXETENXETEYECSEVES rw rw rw rw rw rw rw rw UxMCTLx Bits Modulation bits These bits select the modulation for BRCLK 7 0 13 8 USART Peripheral Interface UART Mode USART Registers Mode UxRXBUF USART Receive Buffer Register 7 6 5 4 3 2 1 0 ESERERESERESEAES r r r r r r r r UxRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UxRXBUF resets the receive error bits the RXWAKE bit and URXIFGx In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 CAEAENE TENE AE ARES rw rw rw rw rw rw rw rw UxTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to be 7 0 moved into the transmit shift register and transmitted on UTXDx Writing to the transmit data buffer clears UTXIFGx The MSB of UxTXBUF is not used for 7 bit data and is reset USART Peripheral Interface UART Mode 13 9 USART Registers UART Mode ME1 Module Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 UTXEot Bit 7 USARTO transmit enable This bit enables the transmitter for USARTO 0 Module not enabled 1 Module enabled URXEot Bit 6 USARTO receive enable This bit enables the receiver for USARTO 0 Module not enabled 1 Module enabled Bits These bits may be used by other modules See device specific datasheet 5 0 T Does not apply to MSP430x12xx devices See ME2 for
15. IFG1 Register Type Address Read write Read write Read write 0120h 0000h 0002h Initial State 06900h with PUC Reset with PUC Reset with PUCt Watchdog Timer Registers WDTCTL Watchdog Timer Register 15 14 13 12 11 10 9 8 Read as 069h WDTPW must be written as 05Ah 1 0 7 6 5 4 3 2 DTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL rw 0 rw 0 rw 0 rw 0 rO w rw 0 WDTPW WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx Bits 15 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bits rw 0 rw 0 Watchdog timer password Always read as 069h Must be written as O5Ah or a PUC will be generated Watchdog timer hold This bit stops the watchdog timer Setting WOTHOLD 1 when the WDT is not in use conserves power 0 Watchdog timer is not stopped 1 Watchdog timer is stopped Watchdog timer NMI edge select This bit selects the interrupt edge for the NMI interrupt when WDTNMI 1 Modifying this bit can trigger an NMI Modify this bit when WDTNMI 0 to avoid triggering an accidental NMI 0 NMI on rising edge 1 NMI on falling edge Watchdog timer NMI select This bit selects the function for the RST NMI pin 0 Reset function 1 NMI function Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode Watchdog timer counter clear Setting WOTCNTCL 1 clears the count value to 0000h WDTCNTCL is automatically reset 0 No action 1 WDTONT 0000h Watchdog t
16. MSC REF2_5V ADC120N ADC120VIE TOVIE ENC ADC12SC 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SHTOx Bits Sample and hold time These bits define the number of ADC12CLK cycles in 11 8 the sampling period for registers ADC12MEMO to ADC12MEM7 SHTx Bits ADC12CLK cycles 0000 4 0001 8 0010 16 0011 32 0100 64 0101 96 0110 128 0111 192 1000 256 1001 384 1010 512 1011 768 1100 1024 1101 1024 1110 1024 1111 1024 ADC12 17 5 ADC 12 Registers MSC REF2_5V REFON ADC120N Bit 7 Bit 6 Bit 5 Bit 4 ADC120VIE Bit ADC12 TOVIE ENC ADC12SC 17 6 Bit 2 Bit 1 Bit 0 ADC12 Multiple sample and conversion Valid only for sequence or repeated modes 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set 0 1 5V 1 2 5V Reference generator on 0 Reference off 1 Reference on ADC12 on 0 ADC 12 off 1 ADC12 on ADC12MEM x overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 conversion time overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Conversion time overflow interrupt di
17. TXWAKE UTXIFGx SYNC CKPH CKPL USART Peripheral Interface SPI Mode 14 3 USART Registers SPI Mode 14 2 USART Registers SPI Mode The USART registers shown in Table 14 1 and Table 14 2 are byte structured and should be accessed using byte instructions Table 14 1 USAHTO Control and Status Registers Register Short Form Register Type Address Initial State USART control register UOCTL Read write 070h 001h with PUC Transmit control register UOTCTL Read write 071 001h with PUC Receive control register UORCTL Read write 072h 000h with PUC Modulation control register UOMCTL Read write 073h Unchanged Baud rate control register 0 UOBRO Read write 074h Unchanged Baud rate control register 1 UOBR1 Read write 075h Unchanged Receive buffer register UORXBUF Read 076h Unchanged Transmit buffer register UOTXBUF Read write 077h Unchanged SFR module enable register 11 ME1 Read write 004h 000h with PUC SFR interrupt enable register 11 IE1 Read write 000h 000h with PUC SFR interrupt flag register 1t IFG1 Read write 002h 082h with PUC t Does not apply to MSP430x12xx devices Refer to the register definitions for registers and bit positions for these devices Table 14 2 USAHT1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive control register U1RCTL Read
18. addressing modes and instruction set Topic Page ad GP ntroducHgni 3 2 3 1 CPU Introduction 3 1 CPU Introduction 3 2 The CPU incorporates features specifically designed for modern programming techniques such as calculated branching table processing and the use of high level languages such as C The CPU can address the complete address range without paging The CPU features include d a d d RISC architecture with 27 instructions and 7 addressing modes Orthogonal architecture with every instruction usable with every addressing mode Full register access including program counter status registers and stack pointer Single cycle register operations Large 16 bit register file reduces fetches to memory 16 bit address bus allows direct access and branching throughout entire memory range 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides six most used immediate values and reduces code size Direct memory to memory transfers without intermediate register holding Word and byte addressing and instruction formats The block diagram of the CPU is shown in Figure 3 1 RISC 16 Bit CPU CPU Introduction Figure 3 1 CPU Block Diagram MDB Memory Data Bus Memory Address Bus MAB 15 0 lt gt RO PC Program Counter E gt Rus Stack Pointer o gt lt gt R2 SR CG1 Status P lt R3 CG2 Constant Generat
19. wee ome m mone rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 me men f me mes rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bit15 Unused TBCLGRP Bit TBCLx group 14 13 00 Each TBCLx latch loads independently 01 TBCL1 TBCL2 TBCCR1 CLLDx bits control the update TBCL3 TBCL4 TBCCR3 CLLDx bits control the update TBCL5 TBCL6 TBCCR5 CLLDx bits control the update TBCLO independent 10 TBCL1 TBCL2 TBCL3 TBCCR1 CLLDx bits control the update TBCL4 TBCL5 TBCL6 TBCCR4 CLLDx bits control the update TBCLO independent 11 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCCR1 CLLDx bits control the update CNTLx Bits Counter Length 12 11 00 16 bit TBR max OFFFFh 01 12 bit TBR max OFFFh 10 10 bit TBR max 03FFh 11 8 bit TBR max OFFh Unused Bit10 Unused TBSSELx Bits Timer_B clock source select 9 8 00 TBCLK 01 10 5 11 Inverted TBCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 01 2 10 4 11 8 Bits Mode control Setting MCx 00h when Timer_B is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TBCLO 10 Continuous mode the timer counts up to the value set by TBCNTLx 11 Up down mode the timer counts up to TBCLO and down to 0000h Timer_B 12 5 Timer_B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer B clear Setting this bit resets TBR t
20. 01 TBCLx loads when TBR counts to 0 10 loads when TBR counts 0 up or continuous mode TBCLx loads when TBR counts to TBCLO or to 0 up down mode 11 TBCLx loads when TBR counts to TBCLx Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TBCLO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set Timer B Timer_B Registers CCIE CCl OUT COV CCIFG 12 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer_B Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending Timer_B Registers TBIV Timer_B Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro ro r 0 r 0 r 0 ro TBIVx Bits Timer B interrupt vector value 15 0 Interrupt TBIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capt
21. 01 Timer A OUT1 10 Timer A OUTO 11 Timer A OUT2 ADC10DF Bit 9 ADC10 data format 0 Straight binary 1 2 s complement ISSH Bit 8 Invert signal sample and hold 0 The sample input signal is not inverted 1 The sample input signal is inverted ADC10 18 7 ADC10 Registers ADC10DIVx Bits ADC10 clock divider 7 5 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 ADC10 Bits ADC10 clock source select SSELx 4 3 00 ADC100SC 01 10 MCLK 11 SMCLK CONSEQx Bits Conversion sequence mode select 2 1 00 Single channel single conversion 01 Sequence of channels 10 Repeatsingle channel 11 Repeat sequence of channels ADC10 Bit 0 ADC10 busy This bit indicates an active sample or conversion operation BUSY O No operation is active 1 A sequence sample or conversion is active ADC10AE Analog Input Enable Control Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC10AEx Bits ADC10 analog enable 7 0 0 Analog input disabled 1 Analog input enabled 18 8 ADC10 ADC10 Registers ADC10MEM Conversion Memory Register Binary Format 1 9 5 14 13 2 11 10 0 0 ro ro ro ro 5 4 3 2 r r r r r 1 8 ri r r 7 6 1 0 Conversion Results r r r Conversion Bits The 10 bit conversion results are right justified straight binary format Bit 9 Results 15 0 is the MSB Bits 15 10 are always 0 ADC10MEM Conversion Memory Register 2 s Complement Format 1 1 14 13 2 11 10 9 8 r r
22. Bits 12C interrupt vector value 15 0 I2CIV Interrupt Interrupt Contents Interrupt Source Flag Priority 000h No interrupt pending 002h Arbitration lost ALIFG Highest 004h No acknowledgement NACKIFG 006h Own address OAIFG 008h Register access ready ARDYIFG 00Ah Receive data ready RXRDYIFG 00Ch Transmit data ready TXRDYIFG OOEh General call GCIFG 010h START condition received STTIFG Lowest USART Peripheral Interface 12C Mode 15 15 Chapter 16 Comparator Comparator_A is an analog voltage comparator This chapter describes Comparator A Comparator_A is implemented in MSP430x11x1 MSP430x12x MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 16 1 Comparator A Introduction 16 2 16 2 Comparator_A Registers err rex E RETE 16 4 16 1 Comparator_A Introduction 16 1 Comparator_A Introduction The comparator A module supports precision slope analog to digital conversions supply voltage supervision and monitoring of external analog signals Features of Comparator_A include Inverting and non inverting terminal input multiplexer Software selectable RC filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator ct L L L L Comparator and reference generator can be powered down Comparator_A block diagram is shown
23. E s i u s si aii 1 Timer_B 12 3 Timer_B Registers 12 2 Timer_B Registers The registers are listed in Table 12 1 Table 12 1 Timer_B Registers Register Short Form Register Type Address Initial State Timer_B control TBCTL Read write 0180h Reset with POR Timer_B counter TBR Read write 0190h Reset with POR Timer_B capture compare control 0 TBCCTLO Read write 0182h Reset with POR Timer_B capture compare 0 TBCCRO Read write 0192h Reset with POR Timer_B capture compare control 1 TBCCTL1 Read write 0184h Reset with POR Timer_B capture compare 1 TBCCR1 Read write 0194h Reset with POR Timer B capture compare control 2 TBCCTL2 Read write 0186h Reset with POR Timer capture compare 2 TBCCR2 Read write 0196h Reset with POR Timer B capture compare control TBCCTL3 Read write 0188h Reset with POR Timer_B capture compare 3 TBCCR3 Read write 0198h Reset with POR Timer_B capture compare control 4 TBCCTL4 Read write 018Ah Reset with POR Timer_B capture compare 4 TBCCR4 Read write 019Ah Reset with POR Timer_B capture compare control 5 TBCCTL5 Read write 018Ch Reset with POR Timer_B capture compare 5 TBCCR5 Read write 019Ch Reset with POR Timer_B capture compare control 6 TBCCTL6 Read write 018Eh Reset with POR Timer_B capture compare 6 TBCCR6 Read write 019Eh Reset with POR Timer_B Interrupt Vector TBIV Read only 011Eh Reset with POR 12 4 Timer_B Timer_B Registers Timer_B Control Register TBCTL 15 14 13 12 11 10 9 8
24. VcAREF is applied to the terminal 1 Vcaner is applied to the terminal Comparator reference These bits select the reference voltage VcAnEr 00 Internal reference off An external reference can be applied 01 0 25 Vcc 10 0 50 Vcc 11 Diode reference is selected Comparator on This bit turns on the comparator When the comparator is off it consumes no current The reference circuitry is enabled or disabled independently 0 Off 1 On Comparator_A interrupt edge select 0 Rising edge 1 Falling edge Comparator_A interrupt enable 0 Disabled 1 Enabled The Comparator_A interrupt flag 0 No interrupt pending 1 Interrupt pending Comparator_A 16 5 Comparator_A Registers CACTL2 Comparator_A Control Register 7 6 5 4 3 2 1 0 tt e im om caour rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Unused Bits Unused 7 4 P2CA1 Bit 3 Pin to CA1 This bit selects the CA1 pin function 0 The pin is not connected to CA1 1 The pin is connected to CA1 P2CAO Bit 2 Pin to CAO This bit selects the CAO pin function 0 The pin is not connected to CAO 1 The pin is connected to CAO CAF Bit 1 Comparator A output filter 0 Comparator_A output is not filtered 1 Comparator_A output is filtered CAOUT Bit 0 Comparator_A output This bit reflects the value of the comparator output Writing this bit has no effect CAPD Comparator_A Port Disable Register 7 6 5 4 3 2 1 0 0 rw 0 rw 0 rw 0 rw 0 rw 0 r
25. and do not affect the DAC12 core 15 12 DAC12 Data Bits DAC12 data 11 0 DAC12 Data Format DAC12 Data 12 bit binary The DAC12 data are right justified Bit 11 is the MSB 12 bit 2 s complement The DAC12 data are right justified Bit 11 is the MSB sign 8 bit binary The DAC 12 data are right justified Bit 7 is the MSB Bits 11 8 are don t care and do not effect the DAC12 core 8 bit 2 s complement The DAC 12 data are right justified Bit 7 is the MSB sign Bits 11 8 are don t care and do not effect the DAC12 core DAC12 19 7
26. appears such as DAC12_xDAT or DAC12_xCTL to describe register names When this occurs the x is used to indicate which DAC12 module is being discussed In cases where operation is identical the register is simply referred to as DAC12_xCTL The block diagram of the two DAC12 modules in the MSP430F15x 16x devices is shown in Figure 19 1 DAC12 Introduction Figure 19 1 DAC 12 Block Diagram VeREF p p To ADC12 module VREF 4 6 4 2 5V or 1 5V reference from ADC12 DAC12SREFx DAC12AMPx DAC12IR e e loo 3 i e 10 11 VR VR DAC12LSELx DAC12_0 DAC12 0OUT DAC12RES DAC12DF Latch Bypass DAC12 OLatch lt DAC12 ODAT DAC12GRP 6120 ENC DAC12_0DAT Updated DAC12SREFx DAC12AMPx DAC12IR t 00 3 x 10 11 AVss VR VR DAC12LSELx DAC12_1 DAC12_10UT DAC12RES DAC12DF gt DAC12 1Latch DAC12 1DAT DAC12GRP ENC DAC12 1DAT Updated 3 DAC12 19 DAC 12 Registers 19 2 DAC12 Registers The DAC12 registers are listed in Table 19 1 Table 19 1 DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12_0CTL Read write 01 0 Reset with POR DAC12_0 data DAC12_0DAT Read write 01C8h Reset with POR DAC12_1 control DAC12_1CTL Read write 01C2h Reset with POR DA
27. be erased The flash memory is partitioned into main and information memory sections There is no difference in the operation of the main and information memory sections Code or data can be located in either section The differences between the two sections are the segment size and the physical addresses The information memory has two 128 byte segments MSP430F 1101 devices have only one The main memory has two or more 512 byte segments See the device specific datasheet for the complete memory map of a device The segments are further dividing into blocks A block is 64 bytes starting at 0xx0Oh 0xx40h Oxx80h or OxxCOh and ending at Oxx3Fh Oxx7Fh OxxBFh or OxxFFh Figure 5 2 shows the flash segmentation using an example of 4 KB flash that has eight main segments and both information segments Figure 5 2 Flash Memory Segments 4 KB Example FFFFh F000h 10FFh 1000h Information Memory xxFFh Segment xxCOh xxBFh Segment1 xx80h xx7Fh Segment2 xx40h xx3Fh Segment3 xx00h Segment4 SegmentA SegmentB Flash Memory Controller 5 3 Flash Memory Registers 5 3 Flash Memory Registers The flash memory registers are listed in Table 5 1 Table 5 1 Flash Memory Registers Register Flash memory control register 1 Flash memory control register 2 Flash memory control register 3 Interrupt Enable 1 5 4 Flash Memory Controller Short Form FCTL1 FCTL2 FCTL3 IE1 Register Type Address Re
28. conditions and from each of the capture compare registers Timer_A features include Asynchronous 16 bit timer counter with four operating modes Selectable and configurable clock source Three configurable capture compare registers Configurable outputs with PWM capability Asynchronous input and output latching Interrupt vector register for fast decoding of all interrupts The block diagram of Timer_A is shown in Figure 11 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then an associated action will not take place Timer_A Introduction Figure 11 1 Timer_A Block Diagram Timer Block TASSELx ass i i TACLK 00 Divid 16 bit Timer i er Count I ACLK 01 1 2 4 8 gt la Mode EQUO Clear SMCLK 10 INCLK 11 SetTAIFG TACLR CCRO CCR1 CCR2 CCISx CMx COV SCS 2 00 Capture CCI2B 01 Mode GND 19 Timer Clock f gt Sync B VCG 11 TACCR2 B 2 EQU2 CAP Set TACCR2 CCIFG CCI OUT OUT2 Signal Timer_A 11 3 Timer_A Registers 11 2 Timer_A Registers registers are listed in Table 11 1 Table 11 1 Timer_A Registers Register Type Address Register Timer_A
29. is off 0001 1 9V 0010 2 1V 0011 2 2V 0100 2 3 0101 2 4 V 0110 2 5 V 0111 2 65 V 1000 2 8V 1001 2 9 V 1010 3 05 1011 3 2V 1100 3 35 V 1101 3 5V 1110 3 7V 1111 Compares external input voltage SVSIN to 1 2 V POR on This bit enables the SVSFG flag to cause a POR device reset 0 SVSFG does not cause a POR 1 SVSFG causes a POR SVS on This bit reflects the status of SVS operation This bit DOES NOT turn on the SVS The SVS is turned on by setting VLDx gt 0 0 SVS is Off 1 SVS is On SVS output This bit reflects the output value of the SVS comparator 0 SVS comparator output is high 1 SVS comparator output is low SVS flag This bit indicates a low voltage condition SVSFG remains set after a low voltage condition until reset by software or a brownout reset 0 No low voltage condition occurred 1 A low condition is present or has occurred Supply Voltage Supervisor Chapter 7 Hardware Multiplier This chapter describes the hardware multiplier The hardware multiplier is implemented in MSP430x14x and MSP430x16x devices Topic Page 7 1 Hardware Multiplier Introduction 7 2 7 2 Hardware Multiplier Registers 7 3 7 1 Hardware Multiplier Introduction 7 1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU This means its activities do not interfere with the CPU activiti
30. processing R3 01 00001h 1 R3 10 00002h 2 bit processing R3 11 OFFFFh 1 word processing The constant generator advantages are J No special instructions required No additional code word for the six constants No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers Constant Generator Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructions For example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst where the 0 is replaced by the assembler and R3 is used with As 00 INC dst is replaced by ADD 0 R3 dst RISC 16 Bit CPU 3 5 CPU Introduction Table 3 3 MSP430 Instruction Set Mnemonic ADC B f ADD B ADDC B AND BIC B BIS B BIT B CALL CLR B CLRN cLRzt CMP B DADC B DADD B DEC B f DECD B f DINT B t INCD B INV B f JC JHS JEQ JZ JGE JL JMP JN JNC JLO JNE JNZ MOV B B PUSH B RET RETI RLA B RLC B RRA B RRC
31. r r r r r 7 6 5 4 3 2 1 0 Il r ro ro ro ro ro ro r 5 Conversion Bits The 10 bit conversion results are left justified 25 complement format Bit 15 Results 15 0 is the MSB Bits 5 0 are always 0 ADC10 18 9 ADC10 Registers ADC10DTCO Data Transfer Control Register 0 7 ro Reserved ADC10TB ADC10CT ADC10B1 ADC10 FETCH 18 10 6 ro Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC10 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 ro ro Reserved Always read as 0 ADC10 two block mode 0 One block transfer mode 1 Two block transfer mode ADC10 continuous transfer 0 Data transfer stops when one block one block mode or two blocks two block mode have completed 1 Data is transferred continuously DTC operation is stopped only if ADC10CT cleared or ADC10SA is written to ADC10 block one This bit indicates for two block mode which block is filled with ADC10 conversion results ADC10B1 is valid only after ADC10IFG has been set the first time during DTC operation ADC10TB must also be set 0 Block 2 is filled 1 Block 1 is filled This bit should normally be reset ADC10 Registers ADC10DTC1 Data Transfer Control Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 DTC Bits DTC transfers These bits define the number of transfers in each block Transfers 7 0 0 DTC is disabled 01h OFFh Number of transfers per block ADC10SA Start Address Regi
32. write 07Ah 000h with PUC Modulation control register U1MCTL Read write 07Bh Unchanged Baud rate control register 0 U1BRO Read write 07Ch Unchanged Baud rate control register 1 U1BR1 Read write 07Dh Unchanged Receive buffer register U1RXBUF Read 07Eh Unchanged Transmit buffer register U1TXBUF Read write 07Fh Unchanged SFR module enable register 2 ME2 Read write 005h 000h with PUC SFR interrupt enable register 2 IE2 Read write 001h 000h with PUC SFR interrupt flag register 2 IFG2 Read write 003h 020h with PUC I OXOI I II I II IIIIIIII IOIII II INIWW I K MI I II IIII IIHI W II I I I I IIII IOVI WO I I II II I IIII 0 OE EEE EEE EEE lt A Note Modifying the SFR bits To avoid modifying control bits for other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B Or CLR B instructions JJ 14 4 USART Peripheral Interface SPI Mode USART Registers SPI Mode UxCTL USART Control Register Unused I2CT CHAR LISTEN SYNC SWRST Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 Unused 12C mode enable This bit selects 2 or SPI operation when SYNC 1 0 SPI mode 1 2 mode Character length 0 7 bit data 1 8 bit data Listen enable The LISTEN b
33. x IZCPSC 1 000h SCL low period 5 x I2CPSC 1 001h SCL low period 5 x I2CPSC 1 002h SCL low period 5 x I2CPSC 1 003h SCL low period 5 x I2CPSC 1 004h SCL low period 6 x I2CPSC 1 OFFh SCL low period 257 x IBCPSC 1 15 10 USART Peripheral Interface I2C Mode Module Registers 2 2 Own Address Register 7 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 I2COAx ro rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 N o gt x Bits 2 own address The I2COA register contains the local address of the 15 0 MSP430 controller The I2COA register is right justified Bit 6 is the MSB Bits 15 7 are always 0 2 I2C Own Address Register 10 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro rw 0 rw 0 7 6 5 4 3 2 1 0 2 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 N o gt x Bits 2 own address I2COA register contains the local address of the 15 0 MSP430 controller The I2COA register is right justified Bit 9 is the MSB Bits 15 10 are always 0 USART Peripheral Interface 12C Mode 15 11 Module Registers I2CSA 2 Slave Address Register 7 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 mmm ro rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CSAx Bits 2 slave address I2CSA regi
34. 10 bit SAR Divider 1 18 10 MCLK 1 SMCLK conver ADCIOCLK SHSx BUSY ISSH ENC za pas Sample Timer 4 8 16 64 ADC10DF ADC10SHTx MSC INCHx 0Bh ADC10MEM Data Transfer Controller ADC10SA ADC10CT ADC10TB ADC10B1 00 ADC10SC 01 TA1 Sync 10 TAO 11 TA2 RAM Flash Peripherials Halt CPU ADC10 18 3 ADC10 Registers 18 2 ADC10 Registers The ADC10 registers are listed in Table 18 1 Table 18 1 ADC10 Registers Register Short Form Register Type Address Initial State ADC10 Input enable register ADC10AE Read write 04Ah Reset with POR ADC10 control register 0 ADC10CTLO Read write 01BOh Reset with POR ADC10 control register 1 ADC10CTL1 Read write 01B2h Reset with POR ADC10 memory ADC10MEM Read 01B4h Unchanged ADC10 data transfer control register 0 ADC10DTCO Read write 048h Reset with POR ADC10 data transfer control register 1 ADC10DTC1 Read write 049h Reset with POR ADC10 data transfer start address ADC10SA Read write 01BCh 0200h with POR 18 4 ADC10 ADC10 Registers ADC10CTLO ADC10 Control Register 0 15 14 13 12 11 10 9 8 sv noces nerounsr rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw Modifiable only when ENC 0 SREFx Bits Select reference 15 13 000 Vg Vcc and Vn Vss 001 Vg Vngre and Vp Vss 010 Vn VeRE
35. A channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit triggers DMA channel 0 1111 External trigger DMAEO Same as DMA2TSELx Same as DMA2TSELx DMACTL1 DMA Control Register 1 15 ro 7 6 14 13 12 11 10 9 8 r0 r0 ro ro ro ro ro 5 4 3 2 1 0 DMA ROUND ONFETCH ROBIN rw 0 rw 0 rw 0 ro ro Reserved Bits 15 3 DMA Bit 2 ONFETCH ROUND Bit 1 ROBIN ENNMI Bit 0 8 6 ro ro ro Reserved Read only Always read as 0 DMA on fetch 0 The DMA transfer occurs immediately 1 The DMA transfer occurs on next instruction fetch after the trigger Round robin This bit enables the round robin DMA channel priorities 0 DMA channel priority is DMAO DMA1 DMA2 1 DMA channel priority changes with each transfer Enable NMI This bit enables the interruption of a DMA transfer by an NMI interrupt When an NMI interrupts a DMA transfer the current transfer is completed normally further transfers are stopped and DMAABORT is set 0 NMI interrupt does not interrupt DMA transfer 1 NMI interrupt interrupts a DMA transfer DMAxCTL DMA Channel x Control Register 15 Reserved rw 0 14 13 12 11 10 9 8 DMADTx DMADSTINCRx DMASRCINCRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 DMA DMA DMA rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved DMADTx DMA DSTINCRx DMA SRCINCRx DMA DSTBYTE Bit 15 Bits 14 12 Bits 11 10 Bits 9 8 Bit 7 Rese
36. ART STOP Multi master transmitter slave receiver mode Multi master receiver slave transmitter mode Combined master transmit receive and receive transmit mode Standard mode up to100 kbps and fast mode up to 400 kbps support Built in FIFO for buffered read and write Programmable clock generation 16 bit wide data access to maximize bus throughput Automatic data byte counting Designed for low power Slave receiver START detection for auto wake up from LPMx modes Extensive interrupt capability Ll LI Ll ud E Li Implemented on USARTO only The 2 block diagram is shown in Figure 15 1 15 2 USART Peripheral Interface I2C Mode Module Introduction Figure 15 1 USART Block Diagram 2 Mode IPCSSELx 2 SYNC 1 I2CBUSY __12 1 SMCLK uS 12CSCLLOW SMCLK ro lt gt RW MST I2CTRX LISTEN I2CRXOVR Receive Shift Register I2CSTP Transmit Shift Register I2CTXUDF I2CSTT 12 5 I2ZCWORD I2CSBD 2 I2CRM XA USART Peripheral Interface 12C Mode 15 3 Module Registers 15 2 12C Module Registers The 12C module registers are listed in Table 15 1 Table 15 1 12 Registers Register Short Form Register Type Address Initial State interrupt enable 2 Read write 050h Reset with PUC 12C interrupt flag I2CIFG Read write 051h Reset with PUC 12C data count I2CNDAT Read write 052h Reset with PUC USART control U
37. C12_1 data DAC12_1DAT Read write 01CAh Reset with POR 19 4 DAC12 DAC 12 Registers DAC12_xCTL DAC12 Control Register 15 Reserved rw 0 7 rw 0 14 13 12 11 10 9 8 DAC12 DAC12SREFx DAC12RES DAC12LSELx CALON DAC12IR rw 0 6 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 0 DAC12 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 m Modifiable only when DAC12ENC 0 Reserved DAC12 SREFx DAC12 RES DAC12 LSELx DAC12 CALON DAC12IR Bit 15 Bits 14 13 Bit 12 Bits 11 10 Bit 9 Bit 8 Reserved DAC12 select reference voltage 00 Vngr 01 VREF 10 11 VenEF DAC12 resolution select 0 12 bit resolution 1 8 bit resolution DAC12 load select Selects the load trigger for the DAC12 latch DAC12ENC must be set for the DAC to update except when DAC12LSELx 0 00 DAC12 latch loads when DAC12 xDAT written DAC12ENC is ignored 01 DAC12 latch loads when DAC12 xDAT written or when grouped when all DAC12 xDAT registers in the group have been written 10 Rising edge of Timer A OUT1 TA1 11 Rising edge of Timer B OUT2 TB2 DAC12 calibration on This bit initiates the DAC12 offset calibration sequence and is automatically reset when the calibration completes 0 Calibration is not active 1 Initiate calibration calibration in progress DAC12 input range This bit sets the reference input and voltage output range 0 DAC12 full scale output 3x re
38. F and Vn Vss 011 Vn VeREF and Vn Vss 100 Vg Vcc and Vg Vrer Verer 101 Vg and VREF J VeREF 110 Vp Vener and Vg VREFJ3 Vener 111 Vn Vener and Vn VREF J VenEF ADC10 Bits ADC10 sample and hold time SHTx 1211 00 4xADC10CLKs 01 8x ADC10CLKs 10 16x ADC10CLKs 11 64x ADC10CLKs ADC1OSR Bit10 ADC10 sampling rate This bit selects the reference buffer drive capability for the maximum sampling rate Setting ADC10SR reduces the current consumption of the reference buffer 0 Reference buffer supports up to 200 ksps 1 Reference buffer supports up to 50 ksps REFOUT Bit 9 Reference output 0 Reference output off 1 Reference output on REFBURST Bit 8 Reference burst REFOUT must also be set 0 Reference buffer on continuously 1 Reference buffer on only during sample and conversion ADC10 18 5 ADC10 Registers MSC REF2_5V REFON ADC100N ADC10IE ADC10IFG ENC ADC10SC 18 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC10 Multiple sample and conversion Valid only for sequence or repeated modes 0 The sampling requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set 0 1 5V 1 2 5
39. Glossary ACLK Auxiliary Clock ADC Analog to Digital Converter BOR Brown Out Reset BSL Bootstrap Loader CPU Central Processing Unit DAC Digital to Analog Converter DCO Digitally Controlled Oscillator dst Destination FLL Frequency Locked Loop GIE General Interrupt Enable INT N 2 Integer portion of N 2 Input Output ISR Interrupt Service Routine LSB Least Significant Bit LSD Least Significant Digit LPM Low Power Mode MAB Memory Address Bus MCLK Master Clock MDB Memory Data Bus MSB Most Significant Bit MSD Most Significant Digit NMI Non Maskable Interrupt PC Program Counter POR Power On Reset PUC Power Up Clear RAM Random Access Memory SCG System Clock Generator SFR Special Function Register SMCLK Sub System Master Clock SP Stack Pointer SR Status Register SIC Source TOS Top of Stack WDT Watchdog Timer See Basic Clock Module See System Hesets Interrupts and Operating Modes See www ti com msp430 for application reports See RISC 16 Bit CPU See Basic Clock Module See RISC 16 Bit CPU See FLL in MSP430x4xx Family User s Guide See System Hesets Interrupts and Operating Modes See Digital I O See System Resets Interrupts and Operating Modes See Basic Clock Module See System Resets Interrupts and Operating Modes See RISC 16 Bit CPU See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See Basi
40. Hx Bits Input channel select 3 0 0000 0 0001 A1 0010 A2 0011 0100 4 0101 A5 0110 A6 0111 A7 1000 VeREF 1001 VREF VenEF 1010 Temperature sensor 1011 AVgg 2 1100 AVgg 2 1101 AVcc AVgg 2 1110 AVcc AVgg 2 1111 AVss 2 ADC12 17 9 ADC 12 Registers ADC12IE ADC12 Interrupt Enable Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 de 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IEx Bits Interrupt enable These bits enable or disable the interrupt request for the 15 0 ADC12IF Gx bits 0 Interrupt disabled 1 Interrupt enabled ADC12IFG ADC12 Interrupt Flag Register 15 14 13 12 11 10 9 8 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG15 IFG14 IFG13 IFG12 IFG11 IFG10 IFG9 IFG8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG7 IFG6 IFG5 IFG4 IFG3 IFG2 IFG1 IFGO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFGx Bits ADC12MEMx Interrupt flag These bits are set when corresponding 15 0 ADC12MEMXx is loaded with a conversion result The ADC12IFGx bits are reset if the corresponding ADC12MEMX is accessed or may be reset with software 0 No interrupt pending 1 Interrupt pending 17 10 ADC12 ADC12IV ADC12 Interrupt Vector Register ro 7 ro ADC12IVx Bits 15 0 6 5 4 3 ADC12 int
41. K On DC Generator Off if DCO not used in active mode Peripheral Modules Are Active CPUOFF 1 SCG0 SCG1 1 CPU Off MCLK Off SMCLK Off DCO Off ACLK On WDTIFG 0 Puo RST NMI is Reset Pin WDT is Active RST NMI NMI Active Active Mode CPU Is Active CPUOFF 1 OSCOFF 1 SCGO 1 SCG1 1 LPM4 CPU Off MCLK Off DCO Off ACLK Off CPUOFF 1 DC Generator Off SCGO 1 0 SCG1 1 LPM3 CPU Off MCLK Off SMCLK Off DCO Off ACLK On LPM2 DC Generator Off SCG1 SCGO OSCOFF CPUOFF Mode CPU and Clocks Status 0 Active CPU is active all enabled clocks are active LPMO CPU MCLK are disabled SMCLK ACLK are active 0 1 0 1 LPM1 CPU MCLK DCO osc are disabled DC generator is disabled if the DCO is not used for MCLK or SMCLK in active mode SMCLK ACLK are active 1 0 0 1 LPM2 CPU MCLK SMCLK DCO osc are disabled DC generator remains enabled ACLK is active 1 1 0 1 LPM3 CPU MCLK SMCLK DCO osc are disabled DC generator disabled ACLK is active 1 1 1 1 LPM4 CPU and all clocks disabled System Resets Interrupts and Operating Modes 2 3 Principles for Low Power Applications 2 2 Principles for Low Power Applications Often the most important factor for reducing power consumption is using the MSP430 s clock system to maximize the time in LPM3 LPM3 power consumption is less than 2 uA typical with both a real time clock function a
42. Lx password Always read as 096h Must be written as OA5h or a PUC 15 8 will be generated FSSELx Bits Flash controller clock source select 7 6 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK FNx Bits Flash controller clock divider These six bits select the divider for the flash 5 0 controller clock The divisor value is FNx 1 For example when FNx 00h the divisor is 1 When FNx 03Fh the divisor is 64 5 6 Flash Memory Controller Flash Memory Registers FCTL3 Flash Memory Control Register FCTL3 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 ro ro rw 0 rw 1 r 1 rw 0 rw 0 r w 0 FWKEYx Reserved EMEX LOCK WAIT ACCVIFG KEYV BUSY Bits 15 8 Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FCTLx password Always read as 096h Must be written as OA5h or a PUC will be generated Reserved Always read as 0 Emergency exit 0 No emergency exit 1 Emergency exit Lock This bit unlocks the flash memory for writing or erasing The LOCK bit can be set anytime during a byte word write or erase operation and the operation will complete normally In the block write mode if the LOCK bit is set while BLKWRT WAIT 1 then BLKWRT and WAIT are reset and the mode ends normally 0 Unlocked 1 Locked Wait Indicates the flash memory is being written to 0 The flash memory is not ready for the next byte word write 1 The flash memory is ready for the next byte word wri
43. OCTL Read write 070h 001h with PUC 12C transfer control I2CTCTL Read write 071h Reset with PUC 12C data control I2CDCTL Read only 072h Reset with PUC 2 prescaler 2 5 Read write 073h Reset with PUC 2 SCL high I2CSCLH Read write 074h Reset with PUC 12C SCL low I2CSCLL Read write 075h Reset with PUC 12C data I2CDRW I2CDRB Read write 076h Reset with PUC 12C own address 2 Read write 0118h Reset with PUC 12C slave address 12CSA Read write 011Ah Reset with PUC 12C interrupt vector 12CIV Read only 011Ch Reset with PUC 15 4 USART Peripheral Interface I2C Mode Module Registers UOCTL USARTO Control Register I2C Mode 7 rw 0 RXDMAEN TXDMAEN 12C XA LISTEN SYNC MST I2CEN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 Receive DMA enable This bit enables the DMA controller to be used to transfer data from the 12C module after the 12C modules receives data When RXDMAEN 1 RXRDYIE is ignored 0 Disabled 1 Enabled Transmit DMA enable This bit enables the DMA controller to be used to provide data to the 12C module for transmission When TXDMAEN 1 TXRDYIE is ignored 0 Disabled 1 Enabled 2 mode enable This bit select 12C or SPI operation when SYNC 1 0 SPI mode 1 2 mode Extended Addressing 0 7 bit addressing 1 10 bit addressing Listen This bit selects loopback mode LISTEN is only valid when M
44. POR reset when the supply voltage or external voltage drops below a user selected threshold The SVS features include AVcc monitoring Selectable generation of POR Output of SVS comparator accessible by software Low voltage condition latched and accessible by software 14 selectable threshold levels gt 7680 E El External channel to monitor external voltage The SVS block diagram is shown in Figure 6 1 6 2 Supply Voltage Supervisor SVS Introduction Figure 6 1 SVS Block Diagram VCC Brownout Reset AVcc D SVSIN HDD gt SVS_POR p t zx NA Reset 50us e SVSOUT gt 1 25V Set SVSFG SVSCTL Bits Supply Voltage Supervisor 6 3 SVS Registers 6 2 SVS Registers The SVS registers are listed in Table 6 1 Table 6 1 SVS Registers Register SVS Control Register Short Form Register Type Address Initial State SVSCTL Read write 055h Reset with BOR SVSCTL SVS Control Register 7 rw ot 6 rw 0t 5 4 3 2 1 0 r rw ot rw 0t rw ot rw ot r t Reset by a brownout reset only not by a POR or PUC VLDx PORON SVSON SVSOP SVSFG 6 4 Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 Voltage level detect These bits turn on the SVS and select the nominal SVS threshold voltage level See the device specific datasheet for parameters 0000 SVS
45. Register Type Address Initial State USART control register UOCTL Read write 070h 001h with PUC Transmit control register UOTCTL Read write 071h 001h with PUC Receive control register UORCTL Read write 072h 000h with PUC Modulation control register UOMCTL Read write 073h Unchanged Baud rate control register 0 UOBRO Read write 074h Unchanged Baud rate control register 1 UOBR1 Read write 075h Unchanged Receive buffer register UORXBUF Read 076h Unchanged Transmit buffer register UOTXBUF Read write 077h Unchanged SFR module enable register 11 ME1 Read write 004h 000h with PUC SFR interrupt enable register 11 IE1 Read write 000h 000h with PUC SFR interrupt flag register 1 IFG1 Read write 002h 082h with PUC t Does not apply to 12xx devices Refer to the register definitions for registers and bit positions for these devices Table 13 2 USAHT1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive control register U1RCTL Read write 07Ah 000h with PUC Modulation control register U1MCTL Read write 07Bh Unchanged Baud rate control register 0 U1BRO Read write 07Ch Unchanged Baud rate control register 1 U1BR1 Read write 07Dh Unchanged Receive buffer register U1RXBUF Read 07Eh Unchanged Transmit buffer register U1TXBUF Read write 07Fh Unchanged SFR module enable register 2 ME2 Read write 005h 000h wi
46. SART1 transmit ready Multiplier ready No trigger No trigger DMA2IFG DMAEO DMAREQ TACCR2 CCIFG TBCCR2 CCIFG USARTO data received USARTO transmit ready DAC12_0IFG ADC12IFGx TACCRO_CCIFG TBCCRO_CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMAOIFG DMAEO DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USARTO data received USARTO transmit ready DAC12_0IFG ADC12IFGx TACCRO_CCIFG TBCCRO_CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMA1IFG DMAEO Aiuoud VINO cp DMADSTINCRx DMADTx DMADSTBYTE 3 ROUNDROBIN DMA Channel 0 DMAOSA DMAODA DMAOSZ DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx DMADSTBYTE DMA Channel 1 DMA1SA DMA1DA DMA1SZ DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx DMADSTBYTE DMA Channel 2 DMA2SA DMA2DA DMA2SZ DMASRSBYTE DMASRCINCRx DMAEN DMAONFETCH JTAG Active NMI Interrupt Request ENNMI Address Space oss Halt CPU 8 8 2 DMA Registers The DMA registers are listed in Table 8 1 Table 8 1 DMA Registers Register Short Form Register Type Address Initial State DMA control 0 DMACTLO Read write 0122h Reset with POR DMA control 1 DMACTL1 Read write 0124h Reset with POR DMA channel 0 control DMAOCTL Read write 01E0h Reset with POR DMA channel 0 source address DMAOSA Read write 01E2h Unchanged DMA channel 0 dest
47. SP430 is the master and is unused in slave mode 0 SCL is not being held low 1 SCL is being held low 12C single byte data This bit indicates if the receive register I2ZCDRW holds a word or a byte I2CSBD is valid only when I2CWORD 1 0 A complete word was received 1 Only the lower byte in I2CDR is valid 2 transmit underflow 0 No underflow occurred 1 Transmit underflow occurred 12C receive overrun 0 No receive overrun occurred 1 Receiver overrun occurred 2 bus busy bit A START condition sets I2CBB to 1 2 is reset by a STOP condition or when I2CEN 0 O 1 2 not busy 1 2 bus busy USART Peripheral Interface 12C Mode 15 7 Module Registers I2CDRW I2CDRB 2 Data Register 15 14 13 12 11 10 9 8 I2CDRW High Byte rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 I2CDRW Low Byte I2CDRB rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CDRW Bits 2 Data When I2CWORD 1 the register name is I2CDRW When I2CDRB 15 8 I2CWORD 0 the name is I2CDRB When I2CWORD 1 any attempt to modify the register with a byte instruction will fail and the register will not be updated I2CNDAT 2 Transfer Byte Count Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CNDATx Bits 2 number of bytes This register supports automatic data byte counting for 7 0 master mode In word mode I2CNDATx must be an even value 15 8 USART Peripheral Interface I2C Mode Mo
48. ST 1 and I2CTRX 1 master transmitter 0 Normal mode 1 SDA is internally fed back to the receiver loopback Synchronous mode enable 0 UART mode 1 SPlor I2C mode Master This bit selects master or slave mode The MST bit is automatically cleared when arbitration is lost or a STOP condition is generated 0 Slave mode 1 Master mode 2 enable The bit enables or disables the 12C module The initial condition for this bit is set and SWRST function for UART or SPI When the 2 and SYNC bits are first set after a PUC this bit becomes I2CEN function and is automatically cleared O IC operation is disabled 1 2 operation is enabled USART Peripheral Interface 12C Mode 15 5 Module Registers I2CTCTL 2 Transmit Control Register 7 rw 0 6 rw 0 5 4 3 2 1 0 I2CWORD 12CRM 12CSSELx I2CTRX 12CSTB I2CSTP 12CSTT rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 I2CWORD I2CRM I2CSSELx I2CTRX I2CSTB I2CSTP 12CSTT 15 6 Bit 7 Bit 6 Bits Bit 3 Bit 2 Bit 1 Bit 0 12C word mode Selects byte or word mode for the 12C data register 0 Byte mode 1 Word mode 2 repeat mode 0 I2CNDAT defines the number of bytes transmitted 1 Number of bytes transmitted is controlled by software I2CNDAT is unused 12C clock source select When MST 1 and arbitration is lost the external SCL signal is automatically used 00 No clock 2 module is inact
49. Timer overflow TAIFG 0Ch Reserved _ OEh Reserved Lowest Chapter 12 Timer_B is a 16 bit timer counter with multiple capture compare registers This chapter describes Timer_B Timer_B3 three capture compare registers is implemented in MSP430x13x and MSP430x15x devices Timer_B7 seven capture compare registers is implemented in MSP430x14x and MSP430x16x devices Topic Page 12 1 Miner B Introduction n 222222000502 12 2 12 2 Timer B Registers 12 4 Timer_B Introduction 12 1 Timer_B Introduction Timer_B is a 16 bit timer counter with three or seven capture compare registers Timer_B can support multiple capture compares PWM outputs and interval timing Timer_B also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer_B features include Asynchronous 16 bit timer counter with four operating modes and four selectable lengths Selectable and configurable clock source Three or seven configurable capture compare registers Configurable outputs with PWM capability Double buffered compare latches with synchronized loading Ll LI Li 0 Li Interrupt vector register for fast decoding of all Timer_B interrupts The block diagram of Timer_B is shown in Figure 12 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the pro
50. URXIFG1 Bit 4 Bits These bits may be used by other modules See device specific datasheet USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF empty 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag URXIFG1 is set when U1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet 13 12 USART Peripheral Interface UART Mode UTXIFGO Bit 1 URXIFGOt Bito MSP430x12xx devices only USART Registers UART Mode USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USART Peripheral Interface UART Mode 13 13 Chapter 14 USART Peripheral Interface SPI Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports two serial modes with one hardware module This chapter discusses the operation of the synchronous peripheral interface or SPI mode USARTO is implemented on the MSP430x12xx MSP430x13xx and MSP430x15x devices In addition to USARTO the MSP430x14x and MSP430x16x devices implement a second identical USART module USART1 Topic Page 14 1 USART Introduction SPI Mode 14 2 USART Registers SPI Mode
51. V Reference generator on 0 Reference off 1 Reference on ADC10 on 0 ADC10 off 1 ADC10 on ADC10 interrupt enable 0 Interrupt disabled 1 interrupt enabled ADC10 interrupt flag This bit is set if ADC10MEM is loaded with a conversion result It is automatically reset when the interrupt request is accepted or it may be reset by software When using the DTC this flag is set when a block of transfers is completed 0 No interrupt pending 1 Interrupt pending Enable conversion 0 ADC10 disabled 1 ADC10 enabled Start conversion Software controlled sample and conversion start ADC10SC and ENC may be set together with one instruction ADC10SC is reset automatically 0 No sample and conversion start 1 Start sample and conversion ADC10 Registers ADC10CTL1 ADC10 Control Register 1 15 14 13 12 11 10 9 8 O o rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Modifiable only when ENC 0 INCHx Bits Input channel select These bits select the channel for a single conversion or 15 12 the highest channel for a sequence of conversions 0000 AO 0001 A1 0010 2 0011 0100 4 0101 A5 0110 A6 0111 A7 1000 VeREF 1001 Vrer Verer 1010 Temperature sensor 1011 Vsg 2 1100 Vsg 2 1101 Vsg 2 1110 Vcc UVss 2 1111 Vcc Vss 2 SHSx Bits Sample and hold source select 11 10 00 ADC10SC bit
52. XBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USART Peripheral Interface SPI Mode 14 13 Chapter 15 USART Peripheral Interface Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports 12C communication in USARTO This chapter describes the 12C mode The 12C mode is implemented on the MSP430x15x and MSP430x16x devices Topic Page 15 1 2 Module Introduction 15 2 15 2 12C Module Registers 15 4 15 1 Module Introduction 15 1 2 Module Introduction The inter IC control 12C module provides an interface between the MSP430 and 2C compatible devices connected by way of the two wire 2 serial bus External components attached to the 2 bus serially transmit and or receive serial data to from the USART through the 2 wire I C interface The 12C module has the following features Compliance to the Philips Semiconductor 12C specification v2 1 Byte word format transfer 7 bit and 10 bit device addressing modes General call START REST
53. ace and are organized by byte SFRs must be accessed using byte instructions only See the device specific data sheets for applicable SFR bits 1 4 5 Memory Organization Bytes are located at even or odd addresses Words are only located at even addresses as shown in Figure 1 3 When using word instructions only even addresses may be used The low byte of a word is always an even address The high byte is at the next odd address For example if a data word is located at address xxx4h then the low byte of that data word is located at address xxx4h and the high byte of that word is located at address xxx5h Figure 1 3 Bits Bytes and Words a Byte Organized Memory xxxAh xxx9h xxx8h xxx7h xxx6h Word High Byte xxx5h Word Low Byte xxx4h Introduction 1 5 Chapter 2 System Resets Interrupts and Operating Modes This chapter describes the MSP430x1xx system resets interrupts and operating modes Topic Page 2 1 System Reset and Initialization 2 2 2 2 Principles for Low Power Applications 2 4 2 3 Connection of Unused Pins 2 1 System Reset and Initialization 2 1 System Reset and Initialization The system reset circuitry shown in Figure 2 1 sources both a power on reset POR and a power up clear PUC signal Different events trigger these reset signals and different initial conditions exist depend
54. ad write Read write Read write Read write 0128h 012Ah 012Ch 000h Initial State 09600h with PUC 09642h with PUC 09618h with PUC Reset with PUC Flash Memory Registers FCTL1 Flash Memory Control Register 15 14 13 12 11 10 9 8 FRKEY Read as 096h FWKEY Must be written as 0 5 7 6 5 4 3 2 1 0 rw 0 rw 0 ro ro ro rw 0 rw 0 ro WRT Reserved MERAS ERASE Reserved Bits 15 8 Bit 7 Bit 6 Bits 5 3 Bit 2 Bit 1 Bit 0 FCTLx password Always read as 096h Must be written as OA5h or a PUC will be generated Block write mode WRT must also be set for block write mode BLKWRT is automatically reset when EMEX is set 0 Block write mode is off 1 Block write mode is on Write This bit is used to select any write mode WRT is automatically reset when is set 0 Write mode is off 1 Write mode is on Reserved Always read as 0 Mass erase and erase These bits are used together to select the erase mode MERAS and ERASE are automatically reset when is set MERAS ERASE Erase Cycle 0 0 No erase 0 1 Erase individual segment only 1 0 Erase all main memory segments 1 1 Erase all main and information memory segments Reserved Always read as 0 Flash Memory Controller 5 5 Flash Memory Registers FCTL2 Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 FWKEYx Bits FCT
55. bit is set when a character is transferred into UxRXBUF before the previous character was read 0 No error 1 Overrun error occurred Break detect flag 0 No break condition 1 Break condition occurred Receive erroneous character interrupt enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received will set URXIFGx Receive wake up interrupt enable This bit enables URXIFGx to be set when an address character is received When URXEIE 0 an address character will not set URXIFGx if it is received with errors 0 All received characters set URXIFGx 1 Only received address characters set URXIFGx Receive wake up flag 0 Received character is data 1 Received character is an address Receive error flag This bit indicates a character was received with error s When RXERR 1 or more error flags FE PE OE BRK is also set RXERR is cleared when UxRXBUF is read 0 No receive errors detected 1 Receive error detected USART Peripheral Interface UART Mode 13 7 USART Registers Mode UxBRO USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 Be ee rw rw rw rw rw rw rw rw UxBR1 USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UxBRx The valid baud rate control range is 3 x UxBR OFFFFh where UxBR UxBR1 UxBR0 Unpredictable receive and transmit timing occurs if UxBR lt 3 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0
56. bytes Extend sign Test destination Exclusive OR source and destination RISC 16 Bit CPU dst C dst src dst dst src dst C dst src and dst dst and dst gt dst src or dst dst src and dst dst PC PC 2 gt stack dst gt PC 0 gt dst 02C 0 gt N 0 2 dst src dst C dst decimally src dst C gt dst decimally dst 1 dst dst 2 dst 0 gt GIE 1 gt GIE dst 1 gt dst dst 2 gt dst not dst dst PC 2x offset gt PC src dst ESP dst SP 2 gt SP SP 2 gt SP src gt SP SP gt PC SP 2 gt SP dst OFFFFh C gt dst 1 1 1 dst not src 1 gt dst dst not src C gt dst dst OFFFFh 1 src xor dst dst oo Chapter 4 Basic Clock Module The basic clock module provides the clocks for MSP430x1xx devices This chapter describes the operation of the basic clock module The basic clock module is implemented in all MSP430x1 xx devices Topic Page 41 Basic Clock Module Introduction 4 2 4 2 Basic Clock Module Registers 4 4 4 1 Basic Clock Module Introduction 4 1 Basic Clock Module Introduction 4 2 The basic clock module supports low system cost and ultralow power consumption Using three internal clock signals the user can select the best balance of performance and low power consumption The bas
57. c Clock Module See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See Watchdog Timer Register Bit Conventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit and the initial condition Register Bit Accessibility and Initial Condition Key Bit Accessibility Read write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 Cleared by hardware Set by hardware Condition after PUC Condition after POR vi Contents mE ET 7 1 A x ru eu ERO ep eae RR CERE RE 1 2 Flexible Clock System 13 Embedded 1 4 Address Space 147 Flas ROM cod ties Whe aa CR et Vane 1 42 BAM 352 er DUE beu beet nbd 1 4 3 Peripheral Modules 2 1 4 4 Special Function Registers SFRS 1 4 5 Memory System Resets Interrupts and Operating Modes 2 1 System Reset and
58. cess of counting for the action to take place If a particular value is directly written to the counter then an associated action does not take place 12 1 1 Similarities and Differences From Timer_A 12 2 Timer_B Timer_B is identical to Timer_A with the following exceptions _j The length of Timer B is programmable to be 8 10 12 or 16 bits Timer TBCCRx registers are double buffered and can be grouped Lj All Timer B outputs can be put into a high impedance state The SCCI bit function is not implemented in Timer B Figure 12 1 Timer_B Block Diagram Timer_B Introduction i Timer Clock Timer Block TBSSELx IDx MCx 15 0 e TBCLK 00 16 bit Timer Count gt TBR RC Pd EQUO 1 2 4 8 Mod t ASIK 1 kE Clear 8 10 12 16 oe SMCLK 10 CNTLx i o 11 j TBCLR 00 i TBCLGRPx 01 i Set TBIFG 10 Group 11 i Load Logic CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 ii de il a a 1 CCR6 i CCI6A 00 Capture ot Mode k 0 i 1 TBCCR6 1 timer ox ES s VCC 11 p CLLDx CCI T lee Compare Latch TBCL6 oad Logic Y x mao x EQU0 UP DOWN EQU6 CAP i Set TBCCR6 CCIFG OUT Output i EQU0 Unit6 OUTE6 Signal x Cp x a OUTMODx L
59. chdog function is not needed in an application the module can be configured as an interval timer and can generate interrupts at selected time intervals Features of the watchdog timer module include Four software selectable time intervals Watchdog mode Interval mode Access to WDT control register is password protected Control of RST NMI pin function Selectable clock source Ll L Ll Ll Ll LY Li Can be stopped to conserve power The WDT block diagram is shown in Figure 10 1 Note Watchdog Timer Powers Up Active After a PUC the WDT module is automatically configured in the watchdog mode with an initial 32 ms reset interval using the DCOCLK The user must setup or halt the WDT prior to the expiration of the initial reset interval ee Watchdog Timer Watchdog Timer Introduction Figure 10 1 Watchdog Timer Block Diagram WDTCTL MSB MDB Password Pulse Counter Compare Generator 16 bit PUC Write Enable Low Byte R W SMCLK WDTHOLD ACLK WDTNMIES WDTNMI WDTTMSEL Watchdog Timer 10 3 Watchdog Timer Registers 10 2 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10 1 Table 10 1 Watchdog Timer Registers Register Watchdog timer control register SFR interrupt enable register 1 SFR interrupt flag register 1 t WDTIFG is reset with POR 10 4 Watchdog Timer Short Form WDTCTL IE1
60. control Timer_A counter Short Form TACTL TAR Timer_A capture compare control 0 TACCTLO Timer_A capture compare 0 TACCRO Timer_A capture compare control 1 TACCTL1 Timer_A capture compare 1 TACCR1 Timer A capture compare control 2 TACCTL2 Timer A capture compare 2 TACCR2 Timer A interrupt vector 11 4 Timer A TAIV Read write Read write Read write Read write Read write Read write Read write Read write Read only 0160h 0170h 0162h 0172h 0164h 0174h 0166h 0176h 012Eh Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Timer_A Registers TACTL Timer_A Control Register 15 14 13 12 11 10 9 8 tt O rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 Cc es es mee rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bits Unused 15 10 TASSELx Bits Timer A clock source select 9 8 00 TACLK 01 ACLK 10 SMCLK 11 INCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 A 01 2 10 4 11 8 Bits Mode control Setting MCx 00h when Timer_A is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TACCRO 10 Continuous mode the timer counts up to OFFFFh 11 X Up down mode the timer counts up to TACCRO then down to 0000h Unused Bit 3 Unused TACLR Bit 2 Time
61. dule Registers I2CPSC 2 Clock Prescaler Register 7 6 5 4 3 2 1 0 2 5 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 I2CPSCx Bits 2 clock prescaler The 2 clock input I2CIN is divided by the 2 5 value 7 0 to produce the internal 12 clock frequency The division rate is 2 5 1 2 5 values gt 4 are not recommended The I2CSCLL and I2CSCLH registers should be used to set the SCL frequency 000h Divide by 1 001h Divide by 2 OFFh Divide by 256 USART Peripheral Interface 12C Mode 15 9 Module Registers I2CSCLH 2 Shift Clock High Register 7 6 5 4 3 2 1 0 I2CSCLHx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 I2CSCLHx Bits 2 shift clock high These bits define the high period of SCL when the 12C 7 0 controller is in master mode The SCL high period is I2CSCLH 2 x IBCPSC 1 000h SCL high period 5 x IBCPSC 1 001h SCL high period 5 x IBCPSC 1 002h SCL high period 5 x IBCPSC 1 003h SCL high period 5 x IBCPSC 1 004h SCL high period 6 x I2CPSC 1 OFFh SCL high period 257 x I2CPSC 1 I2CSCLL 2 Shift Clock Low Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 EN Modifiable only when I2CEN 0 I2CSCLLx Bits 2 shift clock low These bits define the low period of SCL when the 12C 7 0 controller is in master mode The SCL low period is I2CSCLL 2
62. e device specific datasheet USART Peripheral Interface SPI Mode 14 11 USART Registers SPI Mode UTXIEO Bit 1 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIEO Bit 0 USARTO receive interrupt enable This bit enables the URXIFGO interrupt for USARTO 0 Interrupt not enabled 1 Interrupt enabled MSP430x12xx devices only 14 12 USART Peripheral Interface SPI Mode USART Registers SPI Mode IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 rw 0 UTXIFGO Bit 7 URXIFGOt Bit6 Bits 5 0 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet t Does not apply to MSP430x12xx devices See IFG2 for the MSP430x12xx USARTO interrupt flag bits IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 rw 1 rw 0 rw 1 rw 0 Bits 7 6 UTXIFG1 Bit 5 URXIFG1 Bit 4 Bits 3 2 UTXIFGO Bit 1 URXIFGOt Bito MSP430x12xx devices only These bits may be used by other modules See device specific datasheet USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF is empty 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag URXIFG1 is set when U1R
63. e implements a 10 bit SAR core sample select control reference generator and data transfer controller DTC The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention The module can be configured with user software to support a variety of applications ADC10 features include Ll Ll Ll Li Lili Ll TE Li d a Greater than 200 ksps maximum conversion rate Monotonic10 bit converter with no missing codes Sample and hold with programmable sample periods Conversion initiation by software or Timer_A Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight external input channels Conversion channels for internal temperature sensor Vcc and external references Selectable conversion clock source Single channel repeated single channel sequence and repeated sequence conversion modes ADC core and reference voltage can be powered down separately Data transfer controller for automatic storage of conversion results The block diagram of ADC10 is shown in Figure 18 1 Figure 18 1 ADC10 Block Diagram ADC10 Introduction REFOUT REFBURST Ve REF ADC10SR REF2_5V REFON INCHx 0Ah V on ER 1 5Vor2 5V Voc Reference VREFL VeREF Ref_x SREF1 CONSEQx 11 10 01 00 PEF SREF2 Ey ADC100N ADC10SSELx ADC10DIVx 00 ivi 01 ACLK
64. efine how often the fpco 1 frequency is used within a period of 32 DCOCLK cycles During the remaining clock cycles 32 MOD the fbco frequency is used Not useable when DCOx 7 BCSCTL1 Basic Clock System Control Register 1 7 5 4 3 2 1 0 XT20FF XTS DIVAx XT5V RSELx rw 1 XT20FF XTS DIVAx XT5V RSELx rw 0 Bit 7 Bit 6 Bits 5 4 Bit 3 Bits 2 0 rw 0 rw 0 rw 0 rw 1 rw 0 rw 0 XT2 off This bit turns off the XT2 oscillator 0 XT2 is on 1 XT2 is off if it is not used for or SMCLK LFXT1 mode select 0 Low frequency mode 1 High frequency mode Divider for ACLK 00 A 01 2 10 4 11 8 Unused XT5V should always be reset Resistor Select The internal resistor is selected in eight different steps The value of the resistor defines the nominal frequency The lowest nominal frequency is selected by setting RSELx 0 Basic Clock Module 4 5 Basic Clock Module Registers BCSCTL2 Basic Clock System Control Register 2 SELMx DIVMx SELS DIVSx DCOR 4 6 BitS 5 4 Bit 3 BitS 2 1 Bit 0 Select MCLK These bits select the MCLK source 00 DCOCLK 01 DCOCLK 10 XT2CLK when XT2 oscillator present on chip LFXT1CLK when XT2 oscillator not present on chip 11 LFXT1CLK Divider for MCLK 00 A 01 2 10 4 11 8 Select SMCLK This bit selects the SMCLK source 0 DCOCLK 1 XT2CLK when XT2 oscillator present on chip LFXT1CLK when XT2 oscillator not presen
65. errupt vector value ADC12IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch OOEh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h Interrupt Source No interrupt pending ADC12MEMXx overflow Conversion time overflow ADC12MEMO interrupt flag ADC12MEM interrupt flag ADC12MEN2 interrupt flag ADC12MEMs3 interrupt flag ADC12MEM4 interrupt flag ADC12MEM5 interrupt flag ADC12MEM6 interrupt flag ADC12MEN7 interrupt flag ADC12MEMS8 interrupt flag ADC12MEMS 9 interrupt flag ADC12MEM 10 interrupt flag ADC12MEM 1 interrupt flag ADC12MEM12 interrupt flag ADC12MEM 13 interrupt flag ADC12MEM 14 interrupt flag ADC12MEM 15 interrupt flag 2 1 ADC12 Registers 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 0 ro Interrupt Interrupt Flag Priority ADC12IFGO ADC12IFG1 ADC12IFG2 ADC12IFG3 ADC12IFG4 ADC12IFG5 ADC12IFG6 ADC12IFG7 ADC12IFG8 ADC12IFG9 ADC12IFG10 ADC12IFG11 ADC12IFG12 ADC12IFG13 ADC12IFG14 ADC12IFG15 ADC12 Highest Lowest 17 11 Chapter 18 ADC10 The ADC10 module is a high performance 10 bit analog to digital converter This chapter describes the ADC10 The ADC10 is implemented in the MSP430x11x2 MSP430x12x2 devices Topic Page 18 1 ADGIO Introduction amanaya 18 2 19 20 ADCIO Registers coe EM Ee 18 4 18 1 ADC10 Introduction 18 1 ADC10 Introduction 18 2 ADC10 The ADC10 module supports fast 10 bit analog to digital conversions The modul
66. es The multiplier registers are peripheral registers that are loaded and read with CPU instructions The hardware multiplier supports Unsigned multiply Signed multiply Signed multiply accumulate d d Unsigned multiply accumulate d d 16x16 bits 16x8 bits 8x16 bits 8x8 bits The hardware multiplier block diagram is shown in Figure 7 1 Figure 7 1 Hardware Multiplier Block Diagram MPY 130h PE Z MPYS 132h MAC 134h MACS 136h Accessible Register MPY 0000 MACS MPYS MAC 32 bit Multiplexer RESHI 13Ch RESLO 13Ah 31 rw rw 0 SUMEXT13En 13Eh 7 2 Hardware Multiplier Hardware Multiplier Registers 7 2 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7 1 Table 7 1 Hardware Multiplier Registers Register Short Form Register Type Address Initial State Operand one multiply MPY Read write 0130h Unchanged Operand one signed multiply MPYS Read write 0132h Unchanged Operand one multiply accumulate MAC Read write 0134h Unchanged Operand one signed multiply accumulate MACS Read write 0136h Unchanged Operand two OP2 Read write 0138h Unchanged Result low word RESLO Read write 013Ah Undefined Result high word RESHI Read write 013Ch Undefined Sum Extension register SUMEXT Read 013Eh Undefined Hardware Multiplier 7 3 Chapter 8 DMA Controller The DMA controller module transfers data from one address to another wit
67. ference voltage 1 DAC12 full scale output 1x reference voltage DAC12 19 5 DAC 12 Registers DAC12 AMPx DAC12DF DAC12IE DAC12IFG DAC12 ENC DAC12 GRP 19 6 Bits 7 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC12 DAC12 amplifier setting These bits select settling time vs current consumption for the DAC12 input and output amplifiers DAC12AMPx Input Buffer 000 Off 001 Off 010 Low speed current 011 Low speed current 100 Low speed current 101 Medium speed current 110 Medium speed current 111 High speed current DAC12 data format 0 Straight binary 1 2 s compliment DAC12 interrupt enable 0 Disabled 1 Enabled DAC12 Interrupt flag 0 No interrupt pending 1 Interrupt pending Output Buffer DAC12 off output high Z DAC12 off output 0 V Low speed current Medium speed current High speed current Medium speed current High speed current High speed current DAC12 enable conversion This bit enables the DAC12 module when DAC12LSELx gt 0 when DAC12LSELx 0 DAC12bNC is ignored 0 DAC12 disabled 1 DAC12 enabled DAC12 group Groups DAC12 x with the next higher DAC12 x Not used for DAC12 1 MSP430x15x and MSP430x16x devices 0 Not grouped 1 Grouped DAC 12 Registers DAC12_xDAT DAC12 Data Register 15 14 13 12 11 10 9 8 r 0 r 0 r 0 r 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits Unused These bits are always 0
68. gister is not used for SPI mode and should be set 7 0 to 000h 14 8 USART Peripheral Interface SP Mode USART Registers SPI Mode UxRXBUF USART Receive Buffer Register 7 6 5 4 3 2 1 0 ESERERESERESEAES r r r r r r r r UxRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UxRXBUF resets the OE bit and URXIFGx flag In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 Rae see ESSERE rw rw rw rw rw rw rw rw UxTXBUFx Bits The transmit data buffer is user accessible and contains current data to be 7 0 transmitted When seven bit character length is used the data should be MSB justified before being moved into UXTXBUF Data is transmitted MSB first Writing to UXTXBUF clears UTXIFGx USART Peripheral Interface SPI Mode 14 9 USART Registers SPI Mode ME1 Module Enable Register 1 7 6 5 4 3 2 1 0 rw 0 Bit 7 This bit may be used by other modules See device specific datasheet USPIEOf Bit 6 USARTO SPI enable This bit enables the SPI mode for USARTO 0 Module not enabled 1 Module enabled Bits These bits may be used by other modules See device specific datasheet 5 0 T Does not apply to MSP430x12xx devices See ME2 for the MSP430x12xx USARTO module enable bit ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 Bits These bits may be used by other modu
69. h Read write 01A4h Read write 01A6h Read 01A8h Read write 0140h Read write 0142h Read write 0144h Read write 0146h Read write 0148h Read write 014Ah Read write 014Ch Read write 014Eh Read write 0150h Read write 0152h Read write 0154h Read write 0156h Read write 0158h Read write 015Ah Read write 015Ch Read write 015Eh Read write 080h Read write 081 Read write 082h Read write 083h Read write 084h Read write 085h Read write 086h Read write 087h Read write 088h Read write 089h Read write 08Ah Read write 08Bh Read write 08Ch Read write 08Dh Read write 08Eh Read write 08Fh Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR ADC 12 Registers ADC12CTLO ADC12 Control Register 0 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw Modifiable only when ENC 0 SHT1x Bits Sample and hold time These bits define the number of ADC12CLK cycles in 15 12 the sampling period for registers ADC12MEM8 to ADC12MEM 15 7 6 5 4 3 2 1 0 ADC12
70. hanged during block and burst block transfers DMAxSZ DMA Size Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSZx Bits DMA size The DMA size register defines the number of byte word data per 15 0 block transfer DMAxSZ register decrements with each word or byte transfer When DMAxSZ decrements to 0 it is immediately and automatically reloaded with its previously initialized value 000000 Transfer is disabled 00001h One byte or word is transferred 00002h Two bytes or words are transferred OFFFFh 65535 bytes or words are transferred Chapter 9 Digital 1 0 This chapter describes the operation of the digital I O ports Ports P1 P2 are implemented in MSP430x11xx devices Ports P1 P3 are implemented in MSP430x12xx devices Ports P1 P6 are implemented MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 9 1 Digital VO Introduction 9 2 9 2 Digital lO Registers 9 3 9 1 Digital VO Introduction 9 1 Digital I O Introduction 9 2 Digital I O MSP430 devices have up to 6 digital I O ports implemented P1 P6 Each port has eight I O pins Every I O pin is individually configurable for input or output direction and each I O line can be individually read or written to Ports P1 and P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be indiv
71. he TBCLK divider and the count direction The TBCLR bit is automatically reset and is always read as zero TBIE Bit 1 Timer B interrupt enable This bit enables the TBIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TBIFG Bit 0 Timer B interrupt flag 0 No interrupt pending 1 Interrupt pending TBR Timer B Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TBRx Bits Timer B register The TBR register is the count of Timer 15 0 12 6 Timer B Timer_B Registers TBCCTLx Capture Compare Control Register 15 14 rw 0 CMx Bit 15 14 CCISx Bit 13 12 SCS Bit 11 CLLDx Bit 10 9 CAP Bit 8 OUTMODx Bits 7 5 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 r 0 rw 0 5 4 3 2 1 0 rw 0 r rw 0 rw 0 rw 0 rw 0 rw 0 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TBCCRx input signal See the device specific datasheet for specific signal connections 00 01 CCIxB 10 GND 11 Voc Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Compare latch load These bits select the compare latch load event 00 TBCLx loads on write to TBCCRx
72. hout CPU intervention This chapter describes the operation of the DMA controller The DMA controller is implemented in MSP430x15x and MSP430x16x devices Topic Page 8 DMA introduction mnan aaa ms 8 2 8 2 DMA Registers 202 nn 2222222 NENNT NEUEN 8 4 8 1 8 1 DMA Introduction 8 2 The direct memory access DMA controller transfers data from one address to another without CPU intervention across the entire address range For example the DMA controller can move data from the ADC12 conversion memory to RAM Using the DMA controller can increase the throughput of peripheral modules It can also reduce system power consumption by allowing the CPU to remain in a low power mode without having to awaken to move data to or from a peripheral The DMA controller features include Three independent transfer channels Configurable DMA channel priorities Requires only two MCLK clock cycles Byte or word and mixed byte word transfer capability Block sizes up to 65535 bytes or words Configurable transfer trigger selections Selectable edge or level triggered transfer Four addressing modes L D D D D D D D L Single block or burst block transfer modes The DMA controller block diagram is shown in Figure 8 1 Figure 8 1 DMA Controller Block Diagram DMAOTSELx DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USARTO data received USARTO transmit ready DAC12_0IFG ADC12IFGx TACCRO_CCIFG TBCCRO_CCIFG USART1 data received U
73. ic clock module can be configured to operate without any external components with one external resistor with one or two external crystals or with resonators under full software control The basic clock module includes two or three clock sources LFXT1CLK Low frequency high frequency oscillator that can be used either with low frequency 32768 Hz watch crystals or standard crystals or resonators in the 450 kHz to 8 MHz range 1 XT2CLK Optional high frequency oscillator that can be used with standard crystals resonators or external clock sources in the 450 kHz to 8 MHz range Y DCOCLK Internal digitally controlled oscillator DCO with RC type characteristics Three clock signals are available from the basic clock module ACLK Auxiliary clock The ACLK is the buffered LFXT1CLK clock source divided by 1 2 4 or 8 ACLK is software selectable for individual peripheral modules MCLK Master clock MCLK is software selectable as LFXT1CLK XT2CLK if available or DCOCLK MCLK is divided by 1 2 4 or 8 MCLK is used by the CPU and system SMCLK Sub main clock SMCLK is software selectable as LFXT1CLK XT2CLK if available on chip or DCOCLK SMCLK is divided by 1 2 4 or 8 SMCLK is software selectable for individual peripheral modules The block diagram of the basic clock module is shown in Figure 4 1 Basic Clock Module Basic Clock Module Introduction Figure 4 1 Basic Clock Block Diagram DIVAx
74. idually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal All P1 I O lines source a single interrupt vector and all P2 I O lines source a different single interrupt vector The digital I O features include Independently programmable individual I Os Any combination of input or output c _j Individually configurable P1 and P2 interrupts d Independent input and output data registers 9 2 Digital I O Registers Table 9 1 Digital I O Registers Port 1 2 P4 P5 P6 Digital Registers Seven registers are used to configure P1 and P2 Four registers are used to configure ports P6 The digital I O registers are listed in Table 9 1 Register Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Input Output Direction Port Select Input Output Direction Port Select Input Output Direction Port Select Input Output Direction Port Select Short Form P1IN 1 P1DIR P1IFG P1IES P1IE P1SEL 2 2 P2DIR P2IFG P2IES P2IE P2SEL P3IN P3OUT P3DIR P3SEL P4IN P40UT P4DIR P4SEL P5IN P50UT P5DIR P5SEL P6IN P6OUT P6DIR P6SEL Address 020h 021 022h 023h 024h 025h 026h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh
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76. imer clock source select 0 SMCLK 1 ACLK Watchdog timer interval select These bits select the watchdog timer interval to set the WDTIFG flag and or generate a PUC 00 Watchdog clock source 32768 01 Watchdog clock source 8192 10 Watchdog clock source 512 11 Watchdog clock source 64 Watchdog Timer 10 5 Watchdog Timer Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 NMIIE WDTIE 10 6 Bits 7 5 Bit 4 Bits 3 1 Bit 0 These bits may be used by other modules See device specific datasheet NMI interrupt enable This bit enables the NMI interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific datasheet Watchdog timer interrupt enable This bit enables the WDTIFG interrupt for interval timer mode It is not necessary to set this bit for watchdog mode Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Watchdog Timer Watchdog Timer Registers IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 NMIIFG WDTIFG Bits 7 5 Bit 4 Bits 3 1 Bit 0 These b
77. in Figure 16 1 16 2 Comparator_A Comparator_A Introduction Figure 16 1 Comparator_A Block Diagram Voc OV 2 ES O CA0 O EO EE AR 1 CCHB 0 CAOUT CA1 O NA gt 1 lo eS en ee y P Set CAIFG P2CA1 Tau 2 0us CARSEL gt 0 5x Voc 0 25x Voc A Grs Comparator_A 16 3 Comparator_A Registers 16 2 Comparator_A Registers The Comparator_A registers are listed in Table 16 1 Table 16 1 Comparator A Registers Register Short Form Register Type Address Comparator_A control register 1 CACTL1 Read write 059h Comparator control register 2 CACTL2 Read write 05Ah Comparator port disable CAPD Read write 05Bh 16 4 Comparator A Initial State Reset with POR Reset with POR Reset with POR Comparator_A Registers CACTL1 Comparator_A Control Register 1 7 CAEX CARSEL CAREF CAON CAIES CAIE CAIFG rw 0 Bit 7 Bit 6 Bits Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Comparator A exchange This bit exchanges the comparator inputs and inverts the comparator output Comparator A reference select This bit selects which terminal the VcAnEr is applied to When CAEX 0 0 VcAREF is applied to the terminal 1 VcAREF is applied to the terminal When CAEX 1 0
78. ination address DMAODA Read write 01E4h Unchanged DMA channel 0 transfer size DMAOSZ Read write 01E6h Unchanged DMA channel 1 control DMA1CTL Read write 01E8h Reset with POR DMA channel 1 source address DMA1SA Read write 01EAh Unchanged DMA channel 1 destination address DMA1DA Read write 01ECh Unchanged DMA channel 1 transfer size DMA1SZ Read write 01EEh Unchanged DMA channel 2 control DMA2CTL Read write 01F0h Reset with POR DMA channel 2 source address DMA2SA Read write 01F2h Unchanged DMA channel 2 destination address DMA2DA Read write 01F4h Unchanged DMA channel 2 transfer size DMA2SZ Read write 01F6h Unchanged 8 4 DMACTLO DMA Control Register 0 15 14 13 12 11 10 9 8 rw 0 7 rw 0 6 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 0 DMA1TSELx DMAOTSELx rw 0 Reserved DMA2 TSELx DMA1 TSELx DMAO TSELx rw 0 Bits 15 12 Bits 11 8 Bits 7 4 Bits 3 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved DMA trigger select These bits select the DMA transfer trigger 0000 DMAREQ bit software trigger 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 URXIFGO UART SPI mode USARTO data received 12C mode 0100 UTXIFGO UART SPI mode USARTO transmit ready 2 mode 0101 DAC12 OCTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCRO CCIFG bit 1000 TBCCRO CCIFG bit 1001 URXIFG1 bit 1010 UTXIFG1 bit 1011 Multiplier ready 1100 No action 1101 No action 1110 DMAOIFG bit triggers DM
79. ing on which signal was generated Figure 2 1 Power On Reset and Power Up Clear Schematic Voc Brownout Reset 0v OV 50us OV mn 2 3 gt RST NMI WDTSSELT OES Resetwd1 EQut Resetwd2 KEYV from flash module POR 5 Latch POR R PUC MCLK T From watchdog timer peripheral module 3 Devices with BOR only Devices without BOR only Devices with SVS only A POR is a device reset A POR is only generated by the following three events J Powering up the device Alow signal on the RST NMI pin when configured in the reset mode An SVS low condition when PORON 1 A PUC is always generated when a POR is generated but a POR is not generated by a PUC The following events trigger a PUC A POR signal Watchdog timer expiration when in watchdog mode only d L Watchdog timer security key violation d A Flash memory security key violation 2 2 System Resets Interrupts and Operating Modes System Reset and Initialization Figure 2 2 MSP430x1xx Operating Modes For Basic Clock System RST NMI Reset Active WDT Time Expired Overflow WDTIFG 1 WDTIFG 1 WDT Active Security Key Violation CPUOFF 1 SCGO 0 SCG1 0 LPMO CPU Off MCLK Off SMCLK On ACLK On CPUOFF 1 SCGO 1 SCG1 0 LPM1 CPU Off MCLK Off SMCLK On ACL
80. it selects the loopback mode 0 Disabled 1 Enabled The transmit signal is internally fed back to the receiver Synchronous mode enable 0 UART mode 1 SPI mode Master mode 0 USART is slave 1 USART is master Software reset enable 0 Disabled USART reset released for operation 1 Enabled USART logic held in reset state t Applies to USARTO MSP430x15x and MSP430x16x devices only USART Peripheral Interface SPI Mode 14 5 USART Registers SPI Mode UxTCTL USART Transmit Control Register 7 rw 0 CKPH CKPL SSELx Unused Unused STC TXEPT 14 6 rw 0 Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 Clock phase select Controls the phase of UCLK 0 Normal UCLK clocking scheme 1 UCLK is delayed by one half cycle Clock polarity select 0 The inactive level is low data is output with the rising edge of UCLK input data is latched with the falling edge of UCLK 1 The inactive level is high data is output with the falling edge of UCLK input data is latched with the rising edge of UCLK Source select These bits select the BRCLK source clock 00 External UCLK valid for slave mode only 01 valid for master mode only 10 SMCLK valid for master mode only 11 SMCLK valid for master mode only Unused Unused Slave transmit control 0 4 pin SPI mode STE enabled 1 3 pin SPI mode STE disabled Transmitter empty flag The TXEPT f
81. its may be used by other modules See device specific datasheet NMI interrupt flag NMIIFG must be reset by software Because other bits in IFG1 may be used for other modules it is recommended to clear NMIIFG by using BIS BOrBIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet Watchdog timer interrupt flag In watchdog mode WDTIFG remains set until reset by software In interval mode WDTIFG is reset automatically by servicing the interrupt or can be reset by software Because other bits in IFG1 may be used for other modules it is recommended to clear WDTIFG by using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending Watchdog Timer 10 7 Chapter 11 Timer_A Timer_A is a 16 bit timer counter with three capture compare registers This chapter describes Timer_A Timer_A is implemented in all MSP430x1xx devices Topic Page Timers A Introduction 104 DES 11 2 11 2 Timer Registers 11 4 Timer_A Introduction 11 1 Timer_A Introduction 11 2 Timer_A Timer_A is a 16 bit timer counter with three capture compare registers Timer_A can support multiple capture compares PWM outputs and interval timing Timer_A also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow
82. ive 01 ACLK 10 SMCLK 11 SMCLK 2 transmit This bit selects the transmit or receive function for the 12C controller when MST 1 When MST 0 the R W bit of the address byte defines the data direction I2CTRX must be reset for proper slave mode operation 0 Receive mode Data is received on the SDA pin 1 Transmit mode Data transmitted on the SDA pin Start byte Setting the I2CSTB bit when MST 1 initiates a start byte when I2CSTT 1 After the start byte is initiated I2CSTB is automatically cleared 0 No action 1 Send START condition and start byte 01h but no STOP condition STOP bit This bit is used to generate STOP condition After the STOP condition the I2CSTP is automatically cleared 0 No action 1 Send STOP condition START bit This bit is used to generate a START condition After the start condition the I2CSTT is automatically cleared 0 No action 1 Send START condition USART Peripheral Interface I2C Mode Module Registers I2CDCTL 2 Data Control Register 7 Unused 2 05 2 SCLLOW 12CSBD I2CTXUDF I2ZCRXOVR 2 Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 ENS I2CBUSY NT 12CSBD I2CTXUDF I2CRXOVR 2 r 0 r 0 r 0 r 0 r 0 r 0 ro ro Unused Always read as 0 2 busy 0 2 module is idle 1 12 module is not idle 2 SCL low This bit indicates if a slave is holding the SCL line low while the M
83. lag is not used in slave mode 0 Transmission active and or data waiting in UXTXBUF 1 UxTXBUF and TX shift register are empty USART Peripheral Interface SPI Mode USART Registers SPI Mode UxRCTL USART Receive Control Register rw 0 FE Undefined OE Unused Unused Unused Unused Unused Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Framing error flag This bit indicates a bus conflict when MM 1 and STC 0 FE is unused in slave mode 0 No conflict detected 1 A negative edge occurred on STE indicating bus conflict Unused Overrun error flag This bit is set when a character is transferred into UxRXBUF before the previous character was read OE is automatically reset when UxRXBUF is read when SWRST 1 or can be reset by software 0 No error 1 Overrun error occurred Unused Unused Unused Unused Unused USART Peripheral Interface SPI Mode 14 7 USART Registers SPI Mode UxBRO USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 Be ee rw rw rw rw rw rw rw rw UxBR1 USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UxBRx The baud rate generator uses the content of UxBR1 UxBRO to set the baud rate Unpredictable SPI operation occurs if UxBR 2 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 iaia SEHE NES rw rw rw rw rw rw rw rw UxMCTLx Bits The modulation control re
84. les See device specific datasheet 7 5 USPIE1 Bit 4 USART1 SPI enable This bit enables the SPI mode for USART1 0 Module not enabled 1 Module enabled Bits These bits may be used by other modules See device specific datasheet 3 1 USPIEOt Bit 0 USARTO SPI enable This bit enables the SPI mode for USARTO 0 Module not enabled 1 Module enabled MSP430x12xx devices only 14 10 USART Peripheral Interface SP Mode USART Registers SPI Mode IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 UTXIEOT Bit 7 URXIEOT Bit 6 Bits 5 0 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific datasheet 1 Does not apply to MSP430x12xx devices See IE2 for the MSP430x12xx USARTO interrupt enable bits IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 Bits 7 6 UTXIE1 Bit 5 URXIE1 Bit 4 Bits 3 2 These bits may be used by other modules See device specific datasheet USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules Se
85. multiprocessor systems J Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression and address detection Independent interrupt capability for receive and transmit Figure 13 1 shows the USART when configured for UART mode USART Peripheral Interface UART Mode USART Introduction UART Mode Figure 13 1 USAHT Block Diagram UART Mode SWRST URXEx URXEIE URXWIE FE PE OE BRK Receive Control Receive Status Receiver Buffer UXRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSELO SP CHAR Baud Rate Generator Prescaler Divider UxBRx Modulator UXMCTL SP CHAR PEV PENA Transmit Shift Register Transmit Buffer UxTXBUF Transmit Control SWRST UTXEx TXEPT STC S Clock Phase and Polarity Refer to the device specific datasheet for SFR locations SYNC 0 LISTEN MM SYNC UCLKS Oo UCLKI ACLK SMCLK 10 SMCLK O l SIMO TXWAKE UTXIFGx SYNC CKPH CKPL USART Peripheral Interface UART Mode 13 3 USART Registers UART Mode 13 2 USART Registers UART Mode Table 13 1 lists the registers for all devices implementing a USART module Table 13 2 applies only to devices with a second USART module USART1 Table 13 1 USAHTO Control and Status Registers Register Short Form
86. nd all interrupts active A 32 kHz watch crystal is used for the ACLK and the CPU is clocked from the DCO normally off which has a 6 us wake up a d Use interrupts to wake the processor and control program flow Peripherals should be switched on only when needed Use low power integrated peripheral modules in place of software driven functions For example Timer A and Timer B can automatically generate PWM and capture external timing with no CPU resources Calculated branching and fast table look ups should be used in place of flag polling and long software calculations Avoid frequent subroutine and function calls due to overhead For longer software routines single cycle CPU registers should be used 2 3 Connection of Unused Pins The correct termination of all unused pins is listed in Table 2 1 Table 2 1 Connection of Unused Pins 2 4 Pin Potential Comment AVcc DVcc AVss DVss VREF Open Vener DVss Vner Vengr DVss XIN DVcc XOUT Open XT2IN DVss 13x 14x 15x and 16x devices XT20UT Open 13x 14x 15x and 16x devices Px 0 to Px 7 Open Switched to port function output direction RST NMI DVccor Vcc Pullup resistor 47 Test Vpp DVss P11x devices Test DVss Pulldown resistor 30K 11x1 devices Open 11x1A 11x2 12x 12x2 devices TDO Open TDI Open TMS Open TCK Open System Resets In terrupts and Operating Modes Chapter 3 RISC 16 Bit CPU This chapter describes the MSP430 CPU
87. or gt lt gt R4 General Purpose gt KC 5 General Purpose gt lt R6 General Purpose gt lt R7 General Purpose gt KC General Purpose 7 lt gt R9 General Purpose gt ZN 10 General Purpose gt L R11 General Purpose gt lt gt R12 General Purpose gt C R 3 General Purpose gt KC R14 General Purpose gt lt R15 _ General Purpose gt 16 16 Zero Z Carry C Overflow V Negative N RISC 16 Bit CPU 3 3 CPU Introduction 3 1 1 Status Register SR The status register SR R2 used as a source or destination register can be used in the register mode only addressed with word instructions The remain ing combinations of addressing modes are used to support the constant gen erator Figure 3 2 shows the SR bits Figure 3 2 Status Register Bits 15 9 8 7 0 OSC CPU Table 3 1 describes the status register bits Table 3 1 Description of Status Register Bits Bit Description V Overflow bit This bit is set when the result of an arithmetic operation overflows the signed variable range ADD B ADDC B Set when Positive Positive Negative Negative Negative Positive otherwise reset SUB B SUBC B CMP B Set when Positive Negative Negative Negative Positive Positive otherwise reset SCG1 System clock generator 1 This bit when set turns off the SMCLK SCGO System clock generator 0 This bit when se
88. or measuring resistive elements Supply voltage supervisor 16 bit RISC CPU enables new applications at a fraction of the code size Large register file eliminates working file bottleneck Compact core design reduces power consumption and cost B Optimized for modern high level programming Only 27 core instructions and seven addressing modes m Extensive vectored interrupt capability In system programmable Flash permits flexible code changes field upgrades and data logging 1 2 Flexible Clock System 1 2 Introduction The clock system is designed specifically for battery powered applications A low frequency auxiliary clock ACLK is driven directly from a common 32 kHz watch crystal The ACLK can be used for a background real time clock self wake up function An integrated high speed digitally controlled oscillator DCO can source the master clock MCLK used by the CPU and high speed peripherals By design the DCO is active and stable in less than 6 us MSP430 based solutions effectively use the high performance 16 bit RISC CPU in very short bursts Low frequency auxiliary clock Ultralow power stand by mode UY High speed master clock High performance signal processing Embedded Emulation Figure 1 1 MSP430 Architecture ACLK Flash ROM RAM SMCLK o MAB 16 Bit REC GPU 3 Bit 5 MDB 16 Bit us MDB 8 Bit y onv JTAG
89. otocol 1 Address bit multiprocessor protocol Software reset enable 0 Disabled USART reset released for operation 1 Enabled USART logic held in reset state USART Peripheral Interface UART Mode 13 5 USART Registers UART Mode UxTCTL USART Transmit Control Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 Unused Bit 7 Unused CKPL Bit 6 Clock polarity select 0 UCLKI UCLK 1 UCLKI inverted UCLK SSELx Bits Source select These bits select the BRCLK source clock 5 4 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK URXSE Bit 3 UART receive start edge The bit enables the UART receive start edge feature 0 Disabled 1 Enabled TXWAKE Bit 2 Transmitter wake 0 Next character transmitted is data 1 Next character transmitted is an address Unused Bit 1 Unused TXEPT Bit 0 Transmitter empty flag 0 UART is transmitting data and or data is waiting in UxTXBUF 1 Transmitter shift register and UxTXBUF are empty or SWRST 1 13 6 USART Peripheral Interface UART Mode USART Registers Mode UxRCTL USART Receive Control Register rw 0 FE PE OE BRK URXEIE URXWIE RXWAKE RXERR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Framing error flag 0 No error 1 Character received with low stop bit Parity error flag When PENA 0 PE is read as 0 0 No error 1 Character received with parity error Overrun error flag This
90. put signal is latched with the EQUx signal and can be read via this bit Unused Read only Always read as 0 Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TACCRO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set Timer_A 11 7 Timer_A Registers CCIE Bit 4 CCl Bit 3 OUT Bit 2 COV Bit 1 CCIFG Bit 0 Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending TAIV Timer_A Interrupt Vector Register ro 7 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 5 4 3 2 1 0 ro ro TAIVx Bits 15 0 11 8 Timer A ro ro r 0 r 0 r 0 ro Timer A Interrupt Vector value Interrupt TAIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TACCR1 CCIFG Highest 04h Capture compare 2 TACCR2 CCIFG 06h Reserved 08h Reserved OAh
91. r A clear Setting this bit resets TAR the TACLK divider and the count direction The TACLR bit is automatically reset and is always read as zero TAIE Bit 1 Timer A interrupt enable This bit enables the TAIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TAIFG Bit 0 Timer interrupt flag 0 No interrupt pending 1 Interrupt pending Timer A 11 5 Timer_A Registers TAR Timer_A Register 15 14 13 12 11 10 9 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TARx Bits Timer A register The TAR register is the count of Timer A 15 0 11 6 Timer A Timer_A Registers TACCTLx Capture Compare Control Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 r 0 rw 0 7 rw 0 CMx CCISx SCS SCCI Unused OUTMODx 6 Bit 15 14 Bit 13 12 Bit 11 Bit 10 Bit 9 Bit 8 Bits 7 5 5 4 3 2 1 0 rw 0 r rw 0 rw 0 rw 0 rw 0 rw 0 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TACCRx input signal See the device specific datasheet for specific signal connections 00 01 CCIxB 10 GND 11 Voc Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Synchronized capture compare input The selected CCI in
92. rd 1 Byte DMA Bit 6 DMA source byte This bit selects the source as a byte or word SRCBYTE 0 Word 1 Byte DMA Bit 5 DMA level This bit selects between edge sensitive and level sensitive LEVEL triggers 0 Edge sensitive rising edge 1 Level sensitive high level DMAEN Bit 4 DMA enable 0 Disabled 1 Enabled DMAIFG Bit 3 DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMAIE Bit 2 DMA interrupt enable 0 Disabled 1 Enabled DMA Bit 1 DMA Abort This bit indicates if a DMA transfer was interrupt by an NMI ABORT 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMAREQ Bit 0 DMA request Software controlled DMA start DMAREQ is reset automatically 0 No DMA start 1 Start DMA DMAxSA DMA Source Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSAx Bits DMA source address The source address register points to the DMA source 15 0 address for single transfers or the first source address for block transfers The source address register remains unchanged during block and burst block transfers 8 8 DMAxDA DMA Destination Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxDAx Bits DMA destination address The destination address register points to the 15 0 destination address for single transfers or the first address for block transfers The DMAxDA register remains unc
93. reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight individually configurable external input channels E LLL uo Conversion channels for internal temperature sensor AVcc and external references L Independent channel selectable reference sources for both positive and negative references LJ Selectable conversion clock source Single channel repeat single channel sequence and repeat sequence conversion modes ADC core and reference voltage can be powered down separately Interrupt vector register for fast decoding of 18 ADC interrupts 16 conversion result storage registers The block diagram of ADC12 is shown in Figure 17 1 Figure 17 1 ADC 12 Block Diagram ADC 12 Introduction REF2 5V REFON INCHx 0Ah 5 VeREF VREF on 1 5 V or 2 5 V AVcc VREF Vengr Reference AVcc SREF1 aves 2 01 Of m SREFO ADC120SC AO SREF2 N of ADC120N ADC12SSELx 2 ADC12DIVx e Sample 00 A5 and Divider 01 L ACLK A6 Hold 12 bit SAR 8 Mc A7 E H 11 SMCLK S Convert gt ADCI2CLK BUSY Bis X SHP SHTOx ISSH R 4 SHI 00 ADC12SC Sample Timer 01 FAA 14 1024 41 AVcc SAMPCON 1 x i SHT1x MSC INCHx 0Bh Ref_x gt CSTARTADDx CONSEQx ADC12MEMO ADC12MCTLO 16x 12 16x8 i Memory Memory Buffer Control at _ d ADC12MEM15
94. rved DMA Transfer mode 000 Single transfer 001 Block transfer 010 Burst block transfer 011 Burst block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst block transfer 111 Repeated burst block transfer DMA destination increment This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer When DMADSTBYTE 1 the destination address increments decrements by one When DMADSTBYTE 0 the destination address increments decrements by two The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented DMAxDA is not incremented or decremented 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA source increment This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer When DMASRCBYTE 1 the source address increments decrements by one When DMASRCBYTES0 the source address increments decrements by two The DMAxSA is copied into a temporary register and the temporary register is incremented or decremented DMAxSA is not incremented or decremented 00 Source address is unchanged 01 Source address is unchanged 10 Source address is decremented 11 Source address is incremented DMA destination byte This bit selects the destination as a byte or word 0 Wo
95. ry Segmentation 5 3 5 3 Flash Memory Registers 5 4 5 1 Flash Memory Introduction 5 1 Flash Memory Introduction The MSP430 flash memory is bit byte and word addressable and programmable The flash memory module has an integrated controller that controls programming and erase operations The controller has three registers a timing generator and a voltage generator to supply program and erase voltages MSP430 flash memory features include Internal programming voltage generation _j Bit byte or word programmable Ultralow power operation Segment erase and mass erase The block diagram of the flash memory and controller is shown in Figure 5 1 Note Minimum Vcc During Flash Write or Erase The minimum voltage during a flash write or erase operation is 2 7 V If Voc falls below 2 7 V during a write or erase the result of the write or erase will be unpredictable Figure 5 1 Flash Memory Module Block Diagram Address Latch Data Latch Enable Address Latch Timing Generator Enable Data Latch Programming Voltage Generator 5 2 Flash Memory Controller Flash Memory Segmentation 5 2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments Single bits bytes or words can be written to flash memory but the segment is the smallest size of flash memory that can
96. sabled 1 Conversion time overflow interrupt enabled Enable conversion 0 ADC12 disabled 1 ADC12 enabled Start conversion Software controlled sample and conversion start ADC12SC and ENC may be set together with one instruction ADC12SC is reset automatically 0 No sample and conversion start 1 Start sample and conversion ADC 12 Registers ADC12CTL1 ADC12 Control Register 1 15 14 13 12 11 10 9 8 rw 0 rw 0 7 6 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 rw 0 0 ADC12 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 m Modifiable only when ENC 0 CSTART Bits ADDx 15 12 SHSx Bits 11 10 SHP Bit 9 ISSH Bit 8 ADC12DIVx Bits 7 5 Conversion start address These bits select which ADC12 conversion memory register is used for a single conversion or for the first conversion in a sequence The value of CSTARTADDx is 0 to OFh corresponding to ADC12MEMO to ADC12MEM 15 Sample and hold source select 00 ADC12SC bit 01 Timer A OUT1 10 Timer B OUTO 11 Timer B OUT1 Sample and hold pulse mode select This bit selects the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly 0 SAMPCON signal is sourced from the sample input signal 1 SAMPCON signal is sourced from the sampling timer Invert signal sample and hold 0 The sample input signal is not inverted 1 The sample input signal is inverted ADC 12 clock divider 000
97. ss of Flash ROM depends on the amount of Flash ROM present and varies by device The end address for Flash ROM is OFFFFh Flash can be used for both code and data Word or byte tables can be stored and used in Flash ROM without the need to copy the tables to RAM before using them The interrupt vector table is mapped into the upper 16 words of Flash ROM address space with the highest priority interrupt vector at the highest Flash ROM word address OFFFEh RAM starts at 0200h The end address of RAM depends on the amount of RAM present and varies by device RAM can be used for both code and data Address Space 1 4 3 Peripheral Modules Peripheral modules are mapped into the address space The address space from 0100 to 01FFh is reserved for 16 bit peripheral modules These modules should be accessed with word instructions If byte instructions are used only even addresses are permissible and the high byte of the result is always 0 The address space from 010h to OFFh is reserved for 8 bit peripheral modules These modules should be accessed with byte instructions Read access of byte modules using word instructions results in unpredictable data in the high byte If word data is written to a byte module only the low byte is written into the peripheral register ignoring the high byte 1 4 4 Special Function Registers SFRs Some peripheral functions are configured in the SFRs The SFRs are located in the lower 16 bytes of the address sp
98. ster contains the slave address of the 15 0 external device to be addressed by the MSP430 It is only used in master mode I2CSA register is right justified Bit 6 is the MSB Bits 15 7 are always 0 I2CSA 2 Slave Address Register 10 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro rw 0 rw 0 7 6 5 4 3 2 1 0 12CSAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CSAx Bits 2 slave address The I2CSA register contains the slave address of the 15 0 external device to be addressed by the MSP430 It is only used in master mode The I2CSA register is right justified Bit 9 is the MSB Bits 15 10 are always 0 15 12 USART Peripheral Interface I2C Mode Module Registers I2CIE 2 Interrupt Enable Register 7 6 5 4 3 2 1 0 STTIE GCIE TXRDYIE RXRDYIE ARDYIE owe NACKIE ALIE rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 STTIE GCIE TXRDYIE RXRDYIE ARDYIE OAIE NACKIE ALIE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 START detect interrupt enable 0 Interrupt disabled 1 Interrupt enabled General call interrupt enable 0 Interrupt disabled 1 Interrupt enabled Transmit ready interrupt enable When TXDMAEN 1 TXRDYIE is ignored and TXRDYIFG will not generate an interrupt 0 Interrupt disabled 1 Interrupt enabled Receive ready interrupt enable When RXDMAEN 1 RXRDYIE is ignored and RXRDYIFG will not generate an interrupt 0 Interrupt disabled 1 Interrup
99. ster for Data Transfer ADC10SAx Bits ADC10 start address These bits are the start address for the DTC A write 15 1 to register ADC10SA is required to initiate DTC transfers Unused Bit 0 Unused Read only Always read as 0 ADC10 18 11 Chapter 19 DAC12 The DAC12 module is a 12 bit voltage output digital to analog converter This chapter describes the DAC12 Two DAC12 modules are implemented in the MSP430x15x and MSP430x16x devices Topic Page 19 1 DAG 2 Introduction 19 2 1g 290BACI2 Registers 19 4 DAC12 Introduction 19 1 DAC12 Introduction 19 2 DAC12 The DAC12 module is a 12 bit voltage output DAC The DAC12 can be configured in 8 or 12 bit mode and may be used in conjunction with the DMA controller When multiple DAC12 modules are present they may be grouped together for synchronous update operation Features of the DAC12 include 12 bit monotonic output 8 or 12 bit voltage output resolution Programmable settling time vs power consumption Internal or external reference selection Straight binary or 2 s compliment data format Self calibration option for offset correction Doo bo L L Synchronized update capability for multiple DAC12s Note Multiple DAC12 Modules Some devices may integrate more than one DAC12 module In the case where more than one DAC12 is present on a device the multiple DAC12 modules operate identically Throughout this chapter nomenclature
100. t turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK OSCOFF Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not use for MCLK or SMCLK CPUOFF CPU off This bit when set turns off the CPU GIE General interrupt enable This bit when set enables maskable interrupts When reset all maskable interrupts are disabled N Negative bit This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative Word operation N is set to the value of bit 15 of the result Byte operation N is set to the value of bit 7 of the result Z Zero bit This bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0 C Carry bit This bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred 3 4 RISC 16 Bit CPU CPU Introduction 3 1 2 Constant Generator Registers CG1 and CG2 Six commonly used constants are generated with the constant generator registers R2 and R3 without requiring an additional 16 bit word of program code The constants are selected with the source register addressing modes As as described in Table 3 2 Table 3 2 Values of Constant Generators CG1 CG2 Register As Constant Remarks R2 00 Register mode R2 01 0 Absolute address mode R2 10 00004h 4 bit processing R2 11 00008h 8 bit processing R3 00 00000h 0 word
101. t enabled Access ready interrupt enable 0 Interrupt disabled 1 Interrupt enabled Own address interrupt enable 0 Interrupt disabled 1 Interrupt enabled No acknowledge interrupt enable 0 Interrupt disabled 1 Interrupt enabled Arbitration lost interrupt enable 0 Interrupt disabled 1 Interrupt enabled USART Peripheral Interface 12C Mode 15 13 Module Registers I2CIFG 12C Interrupt Flag Register 7 6 5 4 3 2 1 0 core nmoweo mxnowro amwa onra nacia rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 STTIFG Bit 7 START detect interrupt flag 0 No interrupt pending 1 Interrupt pending GCIFG Bit 6 General call interrupt flag 0 No interrupt pending 1 Interrupt pending TXRDYIFG Bit 5 Transmit ready interrupt flag 0 No interrupt pending 1 Interrupt pending RXRDYIFG 4 Receive ready interrupt flag 0 No interrupt pending 1 Interrupt pending ARDYIFG Bit 3 Access ready interrupt flag 0 No interrupt pending 1 Interrupt pending OAIFG Bit 2 Own address interrupt flag 0 No interrupt pending 1 Interrupt pending NACKIFG Bit 1 No acknowledge interrupt flag 0 No interrupt pending 1 Interrupt pending ALIFG Bit 0 Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending 15 14 USART Peripheral Interface I2C Mode I2CIV 12C Interrupt Vector Register 15 ro Module Registers 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro r 0 r 0 r 0 r 0 ro I2CIVx
102. t on chip Divider for SMCLK 00 A 01 2 10 4 11 8 DCO resistor select 0 Internal resistor 1 External resistor Basic Clock Module Basic Clock Module Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 OFIE Bits 7 2 Bit 1 Bits 0 These bits may be used by other modules See device specific datasheet Oscillator fault interrupt enable This bit enables the OFIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled This bit may be used by other modules See device specific datasheet IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 OFIFG Bits Bit 1 Bits 0 These bits may be used by other modules See device specific datasheet Oscillator fault interrupt flag Because other bits in IFG1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B CLR B instructions 0 No interrupt pending 1 Interrupt pending This bit may be used by other modules See device specific datasheet Basic Clock Module 4 7 Chapter 5 Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller Topic Page 5 1 Flash Memory Introduction 5 2 5 2 Flash Memo
103. te Access violation interrupt flag 0 No interrupt pending 1 Interrupt pending Flash security key violation This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set KEYV must be reset with software 0 FCTLx password was written correctly 1 FCTLx password was written incorrectly Busy This bit indicates the status of the flash timing generator 0 Not Busy 1 Busy Flash Memory Controller 5 7 Flash Memory Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 4 0 ACCVIE Bit 5 Flash memory access violation interrupt enable This bit enables the ACCVIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled 5 8 Flash Memory Controller Chapter 6 Supply Voltage Supervisor This chapter describes the operation of the SVS The SVS is implemented in MSP430x15x and MSP430x16x devices Topic Page 61 SVS Introduction matan sans 6 2 62 SVS Registers nn nman nn 6 4 6 1 SVS Introduction 6 1 SVS Introduction The supply voltage supervisor SVS is used to monitor the AVcc supply voltage or an external voltage The SVS can be configured to set a flag or generate a
104. th PUC SFR interrupt enable register 2 IE2 Read write 001h 000h with PUC SFR interrupt flag register 2 IFG2 Read write 003h 020h with PUC r M 4 Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B Or CLR B instructions 13 4 USART Peripheral Interface UART Mode USART Registers Mode UxCTL USART Control Register PENA PEV SPB CHAR LISTEN SYNC SWRST Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 Parity enable 0 Parity disabled 1 Parity enabled Parity bit is generated UTXDx and expected URXDx In address bit multiprocessor mode the address bit is included in the parity calculation Parity select PEV is not used when parity is disabled 0 Odd parity 1 Even parity Stop bit select Number of stop bits transmitted The receiver always checks for one stop bit 0 One stop bit 1 Two stop bits Character length Selects 7 bit or 8 bit character length 0 7 bit data 1 8 bit data Listen enable The LISTEN bit selects loopback mode 0 Disabled 1 Enabled UTXDx is internally fed back to the receiver Synchronous mode enable 0 UART mode 1 SPI Mode Multiprocessor mode select 0 Idle line multiprocessor pr
105. the MSP430x12xx USARTO module enable bits ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 UTXE1 Bit 5 USART1 transmit enable This bit enables the transmitter for USART1 0 Module not enabled 1 Module enabled URXE1 Bit 4 USART1 receive enable This bit enables the receiver for USART1 0 Module not enabled 1 Module enabled Bits These bits may be used by other modules See device specific datasheet 3 2 UTXEOt Bit 1 USARTO transmit enable This bit enables the transmitter for USARTO 0 Module not enabled 1 Module enabled URXEOt Bit 0 USARTO receive enable This bit enables the receiver for USARTO 0 Module not enabled 1 Module enabled MSP430x12xx devices only 13 10 USART Peripheral Interface UART Mode USART Registers Mode IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 UTXIEot Bit 7 URXIEOT Bit 6 Bits 5 0 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific datasheet 1 Does not apply to MSP430x12xx devices See IE2 for the MSP430x12xx USARTO interrupt enable bits IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0
106. ure compare 1 TBCCR1 CCIFG Highest 04h Capture compare 2 TBCCR2 CCIFG 06h Capture compare 31 TBCCR3 CCIFG 08h Capture compare 4t TBCCR4 CCIFG OAh Capture compare 51 5 CCIFG OCh Capture compare 61 TBCCR6 CCIFG OEh Timer overflow TBIFG Lowest t 5 430 14 MSP430x16x devices only Timer B 12 9 Chapter 13 USART Peripheral Interface UART Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports two serial modes with one hardware module This chapter discusses the operation of the asynchronous UART mode USARTO is implemented on the MSP430x12xx MSP430x13xx and MSP430x15x devices In addition to USARTO the MSP430x14x and MSP430x16x devices implement a second identical USART module USART1 Topic Page 13 1 USART Introduction UART Mode 13 2 13 2 USART Registers UART Mode 13 4 USART Introduction UART Mode 13 1 USART Introduction UART Mode 13 2 In asynchronous mode the USART connects the MSP430 to an external System via two external pins URXD and UTXD UART mode is selected when the SYNC bit is cleared UART mode features include J 7 or 8 bit data with odd even or non parity Independent transmit and receive shift registers Separate transmit and receive buffer registers LSB first data transmit and receive Built in idle line address bit communication protocols for
107. w 0 rw 0 rw CAPDx Bits Comparator A port disable These bits individually disable the input buffer 7 0 for the pins of the port associated with Comparator A For example if CAO is on pin P2 3 the CAPDx bits can be used to individually enable or disable each P2 x pin buffer CAPDO disables P2 0 CAPD1 disables P2 1 etc 0 The input buffer is enabled 1 The input buffer is disabled 16 6 Comparator A Chapter 17 ADC12 The ADC12 module is a high performance 12 bit analog to digital converter This chapter describes the ADC12 The ADC12 is implemented in the MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 17 1 ADC12 Anona 17 2 17 4 17 1 ADC 12 Introduction 17 1 ADC12 Introduction 17 2 ADC12 The ADC12 module supports fast 12 bit analog to digital conversions The module implements a 12 bit SAR core sample select control reference generator and a 16 word conversion and control buffer conversion and control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention ADC12 features include Y Greater than 200 ksps maximum conversion rate Monotonic 12 bit converter with no missing codes Li Sample and hold with programmable sampling periods controlled by software or timers Conversion initiation by software Timer A or Timer B Software selectable on chip

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