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Xilinx UG364 Virtex-6 FPGA Configurable Logic Block User Guide

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1. I r DI1 ADDRC Registered Optional I gt I ADDRB l Registered Output Optional I I I DOA g ADDRA 4 i Registered l Output I Optional 1 ug364 10 080609 Figure 10 Distributed RAM RAM64X1Q Virtex 6 FPGA CLB User Guide www xilinx com 19 06364 v1 1 September 16 2009 CLB Overview XILINX RAM 64X3SDP DPRAM64 unused unused WADDRI6 1 WCLK WED Ort RADDR 6 1 2 0 2 DATA 3 O 3 ug364 11 080609 Figure 11 Distributed RAM RAM64X3SDP Implementation of distributed RAM configurations with depth greater than 64 requires the usage of wide function multiplexers F7AMUX F7BMUX and 20 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview RAM128X1S D A 6 0 WCLK WE Output Registered Output Optional ug364_12_080609 Figure 12 Distributed RAM RAM128X1S If two single port 128 x 1 bit modules are built the two RAM128X1S primitives can occupy a SLICEM as long as they share the same clock write enable and shared read and write port address inputs This configuration equates to 128 x 2 bit
2. The function generators in Virtex 6 FPGAs are implemented as six input look up tables LUTs There are six independent inputs A inputs A1 to and two independent outputs O5 and O6 for each of the four function generators in a slice A B C and D The function generators can implement any arbitrarily defined six input Boolean function Each function generator can also implement two arbitrarily defined five input Boolean functions as long as these two functions share common inputs Only the O6 output of the function generator is used when a six input function is implemented Both O5 and O6 are used for each of the five input function generators implemented In this case A6 is driven High by the software The propagation delay through a LUT is independent of the function implemented or whether one six input or two five input generators are implemented Signals from the function generators can exit the slice through A B C D output for O6 or AMUX BMUX CMUX DMUX output for O5 enter the XOR dedicated gate from an O6 output see Fast Lookahead Carry Logic enter the carry logic chain from an O5 output see Fast Lookahead Carry Logic enter the select line of the carry logic multiplexer from www xilinx com 11 06364 v1 1 September 16 2009 CLB Overview 12 XILINX O6 output see Fast Lookahead Carry Logic feed the D input of the storage element or go to FZAMUX F7BMUX from output In addition to the basic
3. 2 AQ Registered Output SEL 1 0 DATA 3 0 b Input 2 Optional ug364_22_040209 Figure 22 Two 8 1 Multiplexers in a Slice 16 1 Multiplexer Each slice has an FEMUX F8MUX combines the outputs of and F7BMUX to form a combinatorial function up to 27 inputs or a 16 1 MUX Only one 16 1 MUX can be implemented in a slice as shown in Figure 23 Virtex 6 FPGA CLB User Guide www xilinx com 31 06364 v1 1 September 16 2009 CLB Overview XILINX Input 6 1 GU IAN a A 71 LUT 06 I SEL D 1 0 DATA D 3 0 A 6 1 F7BMUX Input I LUT 06 oru SEL 1 0 DATA 3 0 6 1 6 A 6 1 Input F8MUX I BMUX 16 1 MUX SELF7 LUT Registered O6 Output SEL 1 0 3 0 1 8067 6 is o s Al6 1 F7AMUX Optional I LUT I I 06 SEL 1 0 DATA 3 0 467 amp SELF7 ON p BX SELF8 IK CLK 4 ug364 23 040209 Figure 23 16 1 Multiplexer in a Slice It is possible to create multiplexers wider than 16 1 across more than one SLICEM However there are no direct connections between slices to form these wide multiplexers Fast Lookahead Carry Logic In addition to function gener
4. 4 64 x 1S 1 64 x ID 2 64 x 100 4 64 x 3SDP O 4 128 x 15 2 128 x 1D 4 14 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview Table 4 Distributed RAM Configuration Cont d RAM Number of LUTs 256 x 1S 4 Notes 1 5 single port configuration D dual port configuration Q quad port configuration SDP simple dual port configuration 2 RAM32M is the associated primitive for this configuration 3 RAM64M is the associated primitive for this configuration For single port configurations distributed RAM has a common address port for synchronous writes and asynchronous reads For dual port configurations distributed RAM has one port for synchronous writes and asynchronous reads and another port for asynchronous reads In simple dual port configuration there is no data out read port from the write port For quad port configurations distributed RAM has one port for synchronous writes and asynchronous reads and three additional ports for asynchronous reads In single port mode read and write addresses share the same address bus In dual port mode one function generator is connected with the shared read and write port address The second function generator has the A inputs connected to a second read only port address and the WA inputs shared with the first read write port address Figure 6 through Figure 14 illustrate various example distribu
5. 46 XILINX RAM X1S RAM X1D RAM M D D DI A D 0 WE WE SPO WE DOD 0 WCLK WCLK WCLK 0 A 0 R W Port ADDRD 0 R W Port DPO DPRA 0 Read Port ADDRO 0 Read Port DOC 0 Read Port DOB 0 ADDRA 0 Read Port DOA 0 ug364_32_040209 Figure 32 Single Port Dual Port and Quad Port Distributed RAM Primitives Instantiating several distributed RAM primitives can be used to implement wide memory blocks Port Signals Each distributed RAM port operates independently of the other while reading the same set of memory cells Clock WCLK The clock is used for the synchronous write The data and the address input pins have setup times referenced to the WCLK pin Enable WE WED The enable pin affects the write functionality of the port An active write enable prevents any writing to memory cells An active write enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs Address A 0 DPRA 0 and ADDRA 4 0 ADDRD 0 The address inputs A 0 for single port and dual port DPRA 0 for dual port and ADDRA f0 ADDRD 0 for quad port select the memory cells for read or write The width of the port determines the required address inputs Some of the address inputs are not buses in VHDL or Verilog instantiations Table 10 summarizes the function of each address pins Data In D DID 4 0
6. Optional SHIFTOUT Q127 ug364_20_040209 Figure 20 128 bit Shift Register Configuration It is possible to create shift registers longer than 128 bits across more than one SLICEM However there are no direct connections between slices to form these shift registers Shift Register Data Flow Shift Operation The shift operation is a single clock edge operation with an active High clock enable feature When enable is High the input D is loaded into the first bit of the shift register Each bit is also shifted to the next highest bit position In a cascadable shift register configuration the last bit is shifted out on the M31 output The bit selected by the 5 bit address port A 4 0 appears on the Q output Dynamic Read Operation The Q output is determined by the 5 bit address Each time a new address is applied to the 5 input address pins the new bit position value is available on the Q output after the time 28 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview delay to access the LUT This operation is asynchronous and independent of the clock and clock enable signals Static Read Operation If the 5 bit address is fixed the O output always uses the same bit position This mode implements any shift register length from 1 to 32 bits in one LUT The shift register length is N 1 where N is the input address 0 31
7. Guide www xilinx com 37 06364 v1 1 September 16 2009 CLB Slice Timing Models XILINX Slice Distributed RAM Timing Model and Parameters Available in SLICEM only Figure 27 illustrates the details of distributed RAM implemented in a Virtex 6 FPGA slice Some elements of the slice are omitted for clarity Only the elements relevant to the timing paths described in this section are shown CX gt C input gt BI gt BX gt B input gt Al gt AX gt 6 A input ug364 27 080609 Figure 27 Simplified Virtex 6 FPGA SLICEM Distributed RAM 38 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX Distributed RAM Timing Parameters CLB Slice Timing Models Table 7 shows the timing parameters for the distributed RAM in SLICEM for a majority of the paths in Figure 27 Table 7 Distributed RAM Timing Parameters Parameter Function Description Sequential Delays for a Slice LUT Configured as RAM Distributed RAM to A B C D outputs Time after the CLK of a write operation that the data written to the distributed RAM is stable on the A B C D output of the slice Setup and Hold Times for a Slice LUT Configured as RAM Distributed RAM 2 Tps Tpg AI BI CI DI configured as Time before after the clock that data must be data input DI1 stable at the AI BI CI DI i
8. Reset Type Sync BFF Async BINIT1 Q gt BQ SR gt LUT B Output B SRHIGH SRLOW SR gt LUT O5 Output Reset Type BASS nFF B LATCH B INIT1 D CE SRLOW CK sh Br LUT A Output o OINITO AX SRHIGH SRLOW AX SR AFF LATCH OFF B LATCH BINIT1 D nINITO CE SRHIGH SRLOW CK ug364 05 040209 Figure 5 Two Versions of Configuration in a Slice 4 Registers Only and 4 Register Latch SRHIGH and SRLOW can be set individually for each storage element in a slice The choice of synchronous SYNC or asynchronous ASYNC set reset SRTYPE cannot be set individually for each storage element in a slice The initial state after configuration or global initial state is defined by separate INITO and INIT1 attributes By default setting the SRLOW attribute sets INITO and setting the SRHIGH attribute sets INIT1 Virtex 6 devices can set INITO and INIT1 independent of SRHIGH and SRLOW The configuration options for the set and reset functionality of a register or the four storage elements capable of functioning as a latch are as follows Virtex 6 FPGA CLB User Guide 06364 v1 1 September 16 2009 No set or reset Synchronous set Synchronous reset Asynchronous set preset Asynchronous reset clear www xilinx com
9. The Q output changes synchronously with each shift operation The previous bit is shifted to the next position and appears on the Q output Shift Register Summary e A shift operation requires one clock edge e Dynamic length read operations are asynchronous output e Static length read operations are synchronous Q output e The data input has a setup to clock timing specification Inacascadable configuration the Q31 output always contains the last bit value The Q31 output changes synchronously after each shift operation Multiplexers Function generators and associated multiplexers in Virtex 6 FPGAs can implement the following e 4 1 multiplexers using one LUT e 8 1 multiplexers using two LUTs e 16 1 multiplexers using four LUTs These wide input multiplexers are implemented in one level or logic or LUT using the dedicated F7BMUX F8MUX multiplexers These multiplexers allow LUT combinations of up to four LUTs in a slice Designing Large Multiplexers 4 1 Multiplexer Each LUT can be configured into a 4 1 MUX The 4 1 MUX can be implemented with a flip flop in the same slice Up to four 4 1 MUXes can be implemented in a slice as shown in Figure 21 Virtex 6 FPGA CLB User Guide www xilinx com 29 UG364 v1 1 September 16 2009 CLB Overview 30 SLICE LUT SEL D 1 0 DATA D 3 0 __ A 6 1 Input LUT O6 SEL 1 0 DATA 3 0 6 1
10. The data input D for single port and dual port and DID 0 for quad port provide the new data value to be written into the RAM Data Out O SPO DPO and DOA 4 0 DOD 4 0 The data out O single port or SPO dual port and DOA 0 DOD 0 quad port reflects the contents of the memory cells referenced by the address inputs Following an active write clock edge the data out O SPO or DOD 0 reflects the newly written data Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 www xilinx com XILINX CLB Primitives Inverting Clock Pins The clock pin CLK has an individual inversion option The clock signal can be active at the negative edge of the clock or the positive edge for the clock without requiring other logic resources The default is at the positive clock edge Global Set Reset GSR The global set reset GSR signal does not affect distributed RAM modules Shift Registers SRLs Primitive One primitive is available for the 32 bit shift register SRLC32E Figure 33 shows the 32 bit shift register primitive SRLCS32E ug364 33 040209 Figure 33 32 bit Shift Register Instantiating several 32 bit shift register with dedicated multiplexers F7 AMUX F7BMUX and allows a cascadable shift register chain of up to 128 bit in a slice Figure 18 through Figure 20 in the Shift Registers Available in SLICEM only section of this document illustrate the various impl
11. contents of the memory at the address on the ADDR inputs are changed The data written to this memory location is reflected on the A B C D outputs synchronously e At time before clock event 1 the write enable signal WE becomes valid high enabling the RAM for a Write operation e At time TAs before clock event 1 the address 2 becomes valid at the A B C D inputs of the RAM Attime Tps before clock event 1 the DATA becomes valid 1 at the DI input of the RAM and is reflected on the A B C D output at time after clock event 1 This is also applicable to the AMUX BMUX CMUX DMUX and COUT outputs at time and Twosco after clock event 1 Clock Event 2 Read Operation All Read operations are asynchronous in distributed RAM As long as WE is Low the address bus can be asserted at any time The contents of the RAM on the address bus are reflected on the A B C D outputs after a delay of length o propagation delay through a LUT The address F is asserted after clock event 2 and the contents of the RAM at address F are reflected at the output after a delay of length Trr o 40 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Slice Timing Models Slice SRL Timing Model and Parameters Available in SLICEM only Figure 29 illustrates shift register implementation in a Virtex 6 FPGA slice Some elements of the slice have been omitted for clarity On
12. single port distributed RAM Virtex 6 FPGA CLB User Guide www xilinx com 21 06364 v1 1 September 16 2009 CLB Overview XILINX A 6 0 WCLK WE 6 0 RAM128X1D SPO E Registered F7BMUX 3 Output Optional 4 DPO Registered F7AMUX Output Optional ug364_13_080609 Figure 13 Distributed RAM RAM128X1D 22 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX RAM256X1S SPRAM64 D ape A 7 0 44 5 6 1 WCLK wee 2 WE SN SPRAM64 A6 CX Figure 14 Distributed RAM RAM256X1S BX A6 AX F7AMUX CLB Overview Output Output Optional ug364 14 040209 Distributed RAM configurations greater than the provided examples require more than one SLICEM There are no direct connections between slices to form larger distributed RAM configurations within a CLB or between slices Distributed RAM Data Flow Synchronous Write Operation The synchronous write operation is a single clock edge operation with an active High write enable WE feature When W
13. the SR inputs of the slice sequential elements Set Reset Trew Minimum Pulse Width for the SR Set Reset Tro Propagation delay for an asynchronous Set Reset of the slice sequential elements From the SR inputs to the AO BO CO DO outputs Frog Toggle Frequency Maximum frequency that a CLB flip flop can be clocked 1 Notes 1 This parameter includes a LUT configured as two five input functions 2 Setup Time before clock edge and Tckxx Hold Time after clock edge Timing Characteristics Figure 26 illustrates the general timing characteristics of a Virtex 6 FPGA slice ous SA UM Z S Z CE AX BX CX DX DATA TsRCK SR 7 m um ERN c T AQ BQ CQ DQ L LAE 4 4 OUT ug364 26 040209 Figure 26 General Slice Timing Characteristics e Attime Togo before clock event 1 the clock enable signal becomes valid high at the CE input of the slice register At time before clock event 1 data from either CX or DX inputs become valid high at the D input of the slice register and is reflected on either the AQ BO CO or DQ pin at time Tcko after clock event 1 At time before clock event 3 the SR signal configured as synchronous reset becomes valid high resetting the slice register This is reflected on the AQ BO CQ or DQ pin at time Tcko after clock event 3 Virtex 6 FPGA CLB User
14. the slice TcrNc TemD A B C D input to Propagation delay from the A B C D inputs of AMUX BMUX CMUX DMUX the slice to AMUX BMUX CMUX DMUX output output of the slice using XOR sum Setup and Hold Times for a Slice LUT Configured as a Carry Chain Data inputs Time before the CLK that data from the CIN inputof the slice mustbe stable at the D input of the slice sequential elements configured as a flip flop Notes 1 Txxck Setup Time before clock edge and Tckxx Hold Time after clock edge Slice Carry Chain Timing Characteristics Figure 31 illustrates the timing characteristics of a slice carry chain implemented in a Virtex 6 FPGA slice 1 2 3 cK gt CINCK DATA EV lt SR 1 AQ BQ CQ DQ eso OUT ug364_31_040209 Figure 31 Slice Carry Chain Timing Characteristics 44 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Primitives e Attime TcrNck before clock event 1 data from CIN input becomes valid high at the D input of the slice register This is reflected on any of the AO BO CO DO pins at time after clock event 1 time before clock event 3 the SR signal configured as synchronous reset becomes valid high resetting the slice register This is reflected on any of the AQ BQ CQ DQ pin
15. to all storage elements in one slice When one flip flop in a slice has SR or CE enabled the other flip flops used in the slice will also have SR or CE enabled by the common signal Only the CLK signal has independent polarity Any inverter placed on the clock signal is automatically absorbed The CE and SR signals are active High All flip flop and latch primitives have CE and non CE versions The SR signal forces the storage element into the state specified by the attribute SRHIGH or SRLOW SRHIGH forces a logic High at the storage element output when SR is asserted while SRLOW forces a logic Low at the storage element output see Table 3 Table 3 Truth Table when using SRLOW and SRHIGH SR SRVAL Function 0 SRLOW default No Logic Change 1 SRLOW default 0 0 SRHIGH No Logic Change 1 SRHIGH 1 Figure 5 shows both the register only and the register latch configuration in a slice www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX LUT D O5 Output DFF LUT D Output INTI Q pQ DINITO B SRHIGH B SRLOW DX SR LUT C O5 Output CLB Overview DFF LATCH OFF B LATCH B INIT DQ D nINITO CE nSRHIGH SR CFF LUT C Output B OINITO Q gt CX SRHIGH SRLOW Cx SR LUT B O5 Output CFF LATCH OFF 6 B LATCH B INIT gt D SRLOW CK sh
16. 1 6 Input A 6 1 LUT 06 B 6 SEL B 1 0 DATA B 3 0 1 Input LUT O6 SEL A 1 0 DATA A 3 0 ELLA A 6 1 Input CLK CLK Figure 21 8 1 Multiplexer XILINX 4 1 MUX Output DQ Registered i Output gt 4 1 Output gt Registered Output gt 4 1 Output Registered A Output Optional A 4 1 MUX Output Registered gt p in gt AQ Output Optional ug364_21_040209 Four 4 1 Multiplexers in a Slice Each slice has an FZAMUX and an F7BMUX These two muxes combine the output of two LUTs to form a combinatorial function up to 13 inputs or an 8 1 MUX Up to two 8 1 MUXes be implemented in slice as shown in Figure 22 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview i LUT O6 D 6 1 SEL D 1 0 DATA D 3 0 6 Input 1 i o A 6 1 F7BMUX gt 8 1 LUT Output 1 CQ Registered Reg 96 Output SEL 1 0 3 0 6 1 6 6 b r Input 4 Optional SELF7 1 Cx CLK LUT O6 I B 6 1 SEL B 1 0 DATA B 3 0 gt 5 6 2 6 1 F7AMUX I oo gt 8 1 MUX Output
17. 13 CLB Overview XILINX Distributed RAM and Memory Available in SLICEM only Multiple LUTs in a SLICEM can be combined in various ways to store larger amount of data The function generators LUTs in SLICEMs can be implemented as a synchronous RAM resource called a distributed RAM element RAM elements are configurable within a SLICEM to implement the following Single Port 32 x 1 bit RAM e Dual Port 32 x 1 bit RAM e Quad Port 32 x 2 bit RAM e Simple Dual Port 32 x 6 bit RAM Single Port 64 x 1 bit RAM e Dual Port 64 x 1 bit RAM e Quad Port 64 x 1 bit RAM e Simple Dual Port 64 x 3 bit RAM Single Port 128 x 1 bit RAM e Dual Port 128 x 1 bit RAM Single Port 256 x 1 bit RAM Distributed RAM modules are synchronous write resources A synchronous read can be implemented with a storage element or a flip flop in the same slice By placing this flip flop the distributed RAM performance is improved by decreasing the delay into the clock to out value of the flip flop However an additional clock latency is added The distributed elements share the same clock input For a write operation the Write Enable WE input driven by either the CE or WE pin of a SLICEM must be set High Table 4 shows the number of LUTS four per slice occupied by each distributed RAM configuration Table 4 Distributed RAM Configuration RAM Number of LUTs 32 15 1 32 10 2 32 200 4 32 x 6SDP 2
18. 2009
19. 64 v1 1 September 16 2009 Preface About This Guide XILINX e Virtex 6 FPGA Transceivers User Guide This guide describes the GTH transceivers available in all Virtex 6 HXT FPGAs except the XC6VHX250T and the XC6VHX380T in the FF1154 package e Virtex 6 FPGA GTX Transceivers User Guide This guide describes the GTX transceivers available in all Virtex 6 FPGAs except the XC6VLX760 e Virtex 6 FPGA Embedded Tri Mode Ethernet MAC User Guide This guide describes the dedicated Tri Mode Ethernet Media Access Controller available in all Virtex 6 FPGAs except the XC6VLX760 e Virtex 6 FPGA DSP48E1 Slice User Guide This guide describes the architecture of the DSP48E1 slice in Virtex 6 FPGAs and provides configuration examples Virtex 6 FPGA System Monitor User Guide The System Monitor functionality available in all Virtex 6 devices is outlined in this guide e Virtex 6 FPGA PCB Design Guide This guide provides information on PCB design for Virtex 6 devices with a focus on strategies for making design decisions at the PCB and interface level Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support 6 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX Virtex 6 FPGA CLB CLB Overview The Configurable Logic
20. Blocks CLBs are the main logic resources for implementing sequential as well as combinatorial circuits Each CLB element is connected to a switch matrix for access to the general routing matrix shown in Figure 1 A CLB element contains a pair of slices These two slices do not have direct connections to each other and each slice is organized as a column Each slice in a column has an independent carry chain For each CLB slices in the bottom of the CLB are labeled as SLICE 0 and slices in the top of the CLB are labeled as SLICE 1 COUT COUT Switch Matrix CIN CIN ug364_01_040209 Figure 1 Arrangement of Slices within the CLB The Xilinx tools designate slices with the following definitions An X followed by a number identifies the position of each slice in a pair as well as the column position of the slice The X number counts slices starting from the bottom in sequence 0 1 the first CLB column 2 3 the second CLB column etc Y followed by a number identifies a row of slices The number remains the same within a CLB but counts up in sequence from one CLB row to the next CLB row starting from the bottom Figure 2 shows four CLBs located in the bottom left corner of the die Virtex 6 FPGA CLB User Guide www xilinx com 7 UG364 v1 1 September 16 2009 CLB Overview XILINX COUT COUT COUT COUT ug364_02_040209 Figure 2 Row and Column Relationship
21. DING ANY LOSS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2009 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 06 24 09 1 0 Initial Xilinx release 09 16 09 14 Add Virtex 6 HXT devices to Table 2 Updated discussions at Look Up Table LUT page 11 and Static Read Operation page 29 CLB labeling change in figures throughout document Figure 6 through Figure 13 Figure 15 Figure 17 Figure 27 through Figure 29 including clarifying the Tps functions descriptions and notes in Table 7 page 39 and Table 8 page 42 Virtex 6 FPGA CLB User Guide www xilinx com 00364 v1 1 September 16 2009 Table of Contents R vision History mu u wass aS G ukasa ee 2 Preface About This Guide Additional Documentation 4 e ka 5 Additional Support eese 6 Virtex 6 FPGA CLB CEB OVetvVIeW ie tee ee ek MT 7 Slice Descriptor s eerte ite eret ret dee a wasa leg eee es ote ete ied gt ua das 8 CLB Slice Timing 5 34 General Slice Timing Model and Para
22. E is High the input D is loaded into the memory location at address A Asynchronous Read Operation Virtex 6 FPGA CLB User Guide 06364 v1 1 September 16 2009 www xilinx com Registered 23 CLB Overview 24 XILINX The output is determined by the address A for single port mode output SPO output of dual port mode or address DPRA DPO output of dual port mode Each time a new address is applied to the address pins the data value in the memory location of that address is available on the output after the time delay to access the LUT This operation is asynchronous and independent of the clock signal Distributed RAM Summary Single port and dual port modes are available in SLICEMs e A write operation requires one clock edge Read operations are asynchronous Q output The data input has a setup to clock timing specification Read Only Memory ROM Each function generator in SLICEMs and SLICELs can implement a 64 x 1 bit ROM Three configurations are available ROM64x1 ROM128x1 and ROM256x1 ROM contents are loaded at each device configuration Table 5 shows the number of LUTs occupied by each ROM configuration Table 5 ROM Configuration ROM Number of LUTs 64x 1 1 128 1 2 256 1 4 Shift Registers Available SLICEM only A SLICEM function generator can also be configured as a 32 bit shift register without using the flip flops available in a slice Used in t
23. FF LAT DINIT1 D nINITO WEN MC31 P SRLO SR gt 0 1 SR gt D gt gt 4 I CK WEN gt ug364 03 040209 Figure 3 Diagram of SLICEM Virtex 6 FPGA CLB User Guide www xilinx com 9 06364 v1 1 September 16 2009 CLB Overview XILINX SRHI EM Reset Type SR Sync Async DX FF LAT 3 4 gt DMUX 06 1 gt A6 A1 LOD O FF LAT DQ D RINITO SRHI n SRLO 5 pied B INIT1 CE CK gn EX gt CMUX D gt A6 A1 LOC 96 FF LAT oINIT1 aH CQ NITO B SRHI 5 B SRLO SR 9 4 gt BMUX B6 1 gt A6 A1 LB FF LAT QHD BQ D nINITO OSRHI CK SRLO SR 2 4 AK t gt AMUX A6 1 gt A6 A1 ry D LA O6 n FF LAT EN QHD AQ n INITO SRHI B SRLO SR 0 1 gt D CE gt 5 d CIN ug364_04_040209 Figure 4 Diagram of SLICEL 10 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview CLB Slice Configurations Ta
24. LUTs slices contain three multiplexers F7AMUX and F8MUX These multiplexers are used to combine up to four function generators to provide any function of seven or eight inputs in a slice FZAMUX and F7BMUX are used to generate seven input functions from LUTs and or C and D while is used to combine all LUTS to generate eight input functions Functions with more than eight inputs can be implemented using multiple slices There are no direct connections between slices to form function generators greater than eight inputs within a CLB Storage Elements As in previous Virtex architectures there are four original storage elements in a slice that can be configured as either edge triggered D type flip flops or level sensitive latches The D input can be driven directly by a LUT output via AFFMUX BFFMUX CFFMUX or DFFMUX or by the BYPASS slice inputs bypassing the function generators via AX BX CX or DX input When configured as a latch the latch is transparent when the CLK is Low In Virtex 6 devices there are now four additional storage elements that can only be configured as edge triggered D type flip flops The D input can be driven by the O5 output of the LUT or the BYPASS slice inputs via AX BX CX or DX input When the original 4 storage elements are configured as latches these 4 additional storage elements can not be used The control signals clock CLK clock enable CE and set reset SR are common
25. RL for the Write operation that follows e At time before clock event 1 the data becomes valid 0 at the DI input of the SRL and is reflected on the A B C D output after a delay of length after clock event 1 Since the address 0 is specified at clock event 1 the data on the DI input is reflected at A B C D output because it is written to register 0 Clock Event 2 Shift In Attime Tps before clock event 2 the data becomes valid 1 at the DI input of the SRL and is reflected on the A B C D output after a delay of length after clock event 2 Since the address 0 is still specified at clock event 2 the data on the DI input is reflected at the D output because it is written to register 0 Clock Event 3 Shift In Addressable Asynchronous READ All Read operations are asynchronous to the CLK signal If the address is changed between clock events the contents of the register at that address are reflected at the addressable output A B C D outputs after a delay of length propagation delay through a LUT Tps before clock event 3 the data becomes valid 1 at the DI input of the SRL and is reflected on the A B C D output time after clock event 3 The address is changed from 0 to 2 The value stored in register 2 at this time is a 0 in this example this was the first data shifted in and it is reflected on the A B C D output after a delay of length Trr o Clock Event 32 MSB M
26. Virtex 6 FPGA Configurable Logic Block User Guide UG364 v1 1 September 16 2009 XILINX 2 XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLU
27. XILINX Table 6 shows the general slice timing parameters for a majority of the paths in Figure 25 Table 6 General Slice Timing Parameters Parameter Combinatorial Delays Function Description Tro A B C D inputs to A B C D Propagation delay from the A B C D inputs of outputs the slice through the look up tables LUTs to the A B C D outputs of the slice six input function 2 A B C D inputs to Propagation delay from the A B C D inputs of 7 AMUX CMUX outputs the slice through the LUTs and F7AMUX F7BMUxX to the AMUX CMUX outputs seven input function A B C D inputs to BMUX Propagation delay from the A B C D inputs of output the slice through LUTs FFAMUX F7BMUx and F8MUX to the BMUX output eight input function Sequential Delays Tcko Flip Flop Latch element FF Clock CLK to AQ BQ CQ DQ outputs Time after the clock that data is stable at the outputs of the slice sequential elements configured as a flip flop Flip Flop only element FF Clock CLK to Time after the clock that data is stable at the outputs outputs of the slice sequential elements TCKLO Latch Clock CLK to Time after the clock that data is stable at the outputs outputs of the slice sequential elements configured as a latch Setup and Hold Times for Slice Sequential Elemen
28. ators dedicated carry logic is provided to perform fast arithmetic addition and subtraction in a slice A Virtex 6 FPGA CLB has two separate carry chains as shown in Figure 1 The carry chains are cascadable to form wider add subtract logic as shown in Figure 2 The carry chain in the Virtex 6 device is running upward and has a height of four bits per slice For each bit there is a carry multiplexer MUXCY and a dedicated XOR gate for adding subtracting the operands with a selected carry bits The dedicated carry path and carry multiplexer MUXCY can also be used to cascade function generators for implementing wide logic functions Figure 24 illustrates the carry chain with associated logic elements in a slice 32 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 CLB Overview COUT To Next Slice Carry Chain Block CARRY4 gt DMUX DQ DMUX gt DQ Optional CMUX CQ O6 From LUTC gt CMUX gt CQ Optional gt BMUX BQ O6 From LUTB BMUX O5 From LUTB BX BQ Optional gt AMUX AQ O6 From LUTA gt MUXCYN ug364 09 040209 AMUX O5 From LUTA gt AQ Optional Can be used if unregistered registered outputs are free CIN From Previous Slice ug364_24_040209 Figure 24 Fast Carry Logic Path and Associated Elements The carry chains carry l
29. between CLBs and Slices Slice Description Every slice contains four logic function generators or look up tables eight storage elements wide function multiplexers and carry logic These elements are used by all slices to provide logic arithmetic and ROM functions In addition to this some slices support two additional functions storing data using distributed RAM and shifting data with 32 bit registers Slices that support these additional functions are called SLICEM others are called SLICEL SLICEM shown in Figure 3 represents a superset of elements and connections found in all slices SLICEL is shown in Figure 4 Each CLB can contain zero or one SLICEM Every other CLB column contains a SLICEMs In addition the two CLB columns to the left of the DSPA8E columns both contain a SLICEL and a SLICEM 8 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview B zB Reset Type Q CE CK sn FF LAT FF LAT OINITO SRHI WEN MC31 FF LAT INIT1 SRHI WEN MC31 B 5810 FF LAT B INIT1 B SRHI SRLO SR n
30. ble 1 summarizes the logic resources in one CLB Each CLB or slice can be implemented in one of the configurations listed Table 2 shows the available resources in all CLBs Table 1 Logic Resources in One CLB Slices LUTs Flip Flops Distributed Shift Registers 1 2 8 16 2 256 bits 128 bits Notes 1 SLICEM only SLICEL does not have distributed RAM or shift registers Table 2 6 FPGA Logic Resources Available CLBs peviee lies SEIGEES Dictributed RAM Kb aglater XC6VLX75T 11 640 7 460 4 180 46 560 1 045 522 5 93 120 XC6VLX130T 20 000 13 040 6 960 80 000 1 740 870 160 000 XC6VLX195T 31 200 19 040 12 160 124 800 3 140 1 570 249 600 XC6VLX240T 37 680 23 080 14 600 150 720 3 770 1 885 301 440 XC6VLX365T 56 880 40 360 16 520 227 520 4 130 2 065 455 040 XC6VLX550T 85 920 61 120 24 800 343 680 6 200 3 100 687 360 XC6VLX760 118 560 85 440 33 120 474 240 8 280 4 140 948 480 XC6VSX315T 49 200 28 840 20 360 196 800 5 090 2 545 393 600 XC6VSX475T 74 400 48 840 30 560 297 600 7 640 3 820 595 200 XC6VHX250T 39 360 27 200 12 160 157 440 3 040 1 520 314 880 XC6VHX255T 39 600 27 400 12 200 158 400 3 050 1 525 316 800 XC6VHX380T 59 760 41 520 18 240 239 040 4 570 2 285 478 080 XC6VHX565T 88 560 63 080 25 480 354 240 6 370 3 185 708 480 Virtex 6 FPGA CLB User Guide Look Up Table LUT
31. dress tied to 0000110 and a flip flop can be used as the last register In an SRLC32E primitive the shift register length is the address input 1 www xilinx com Virtex 6 FPGA CLB User Guide UG364 v1 1 September 16 2009 XILINX CLB Primitives OUT 72 bit SRL OUT 72 bit SRL 00140 ug364 35 040209 Figure 35 Example Static Length Shift Register Multiplexer Primitives Two primitives MUXF7 and are available for access to the dedicated F AMUX F7BMUX and F8MUX in each slice Combined with LUTS these multiplexer primitives are also used to build larger width multiplexers from 8 1 to 16 1 The Designing Large Multiplexers section provides more information on building larger multiplexers Port Signals Data In 10 11 The data input provides the data to be selected by the select signal 5 Control In S The select input signal determines the data input signal to be connected to the output O Logic 0 selects the 10 input while logic 1 selects the I1 input Data Out O The data output O provides the data value one bit selected by the control inputs Carry Chain Primitive The CARRYA primitive represents the fast carry logic for a slice in the Virtex 6 architecture This primitive works in conjunction with LUTs in order to build adders and multipliers This primitive is generally inferred by synthesis tools from standard RTL code The synthesis too
32. dual inversion option The clock signal can be active at the negative or positive edge of the clock without requiring other logic resources The default is positive clock edge Global Set Reset GSR The global set reset GSR signal does not affect the shift registers Other Shift Register Applications 48 Synchronous Shift Registers The shift register primitive does not use the register available in the same slice To implement a fully synchronous read and write shift register output pin Q must be connected to a flip flop Both the shift register and the flip flop share the same clock as shown in Figure 34 SRLC32G FF Synchronous Output Address CE Write Enable CLK ug364 34 040209 Figure 34 Synchronous Shift Register This configuration provides a better timing solution and simplifies the design Because the flip flop must be considered to be the last register in the shift register chain the static or dynamic address should point to the desired length minus one If needed the cascadable output can also be registered in a flip flop Static Length Shift Registers The cascadable 32 bit shift register implements any static length mode shift register without the dedicated multiplexers F7AMUX F7BMUX and Figure 35 illustrates a 72 bit shift register Only the last SRLC32E primitive needs to have its address inputs tied to 0b00111 Alternatively shift register length can be limited to 71 bits ad
33. e first bit of the next without using the LUT O6 output Longer shift registers can be built with dynamic access to any bit in the chain The shift register chaining and the FZAMUX F7BMUX and FEMUX multiplexers allow up to a 128 bit shift register with addressable access to be implemented in one SLICEM Figure 18 through Figure 20 illustrate various example shift register configurations that can occupy one SLICEM SHIFTIN D A 5 0 6 2 A5 AX CLK T WE L gt Output Q AQ Registered Optional MC31 SHIFTOUT Q63 ug364_18_040209 Figure 18 64 bit Shift Register Configuration 26 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview CX A5 SHIFTIN D DH 9 2 F7BMUX CLK BX A6 WE CE WE Output Q BQ Registered Optional AX A5 Not Used F7AMUX UG364 19 012509 Figure 19 96 bit Shift Register Configuration Virtex 6 FPGA CLB User Guide www xilinx com 27 06364 v1 1 September 16 2009 CLB Overview XILINX SHIFTIN D 5 A 6 0 6 2 CLK WE Output Q Registered F8MUX Output
34. ementation of cascadable shift registers greater than 32 bits Port Signals Clock CLK Either the rising edge or the falling edge of the clock is used for the synchronous shift operation The data and clock enable input pins have setup times referenced to the chosen edge of CLK Data In D The data input provides new data one bit to be shifted into the shift register Clock Enable CE The clock enable pin affects shift functionality An inactive clock enable pin does not shift data into the shift register and does not write new data Activating the clock enable allows the data in D to be written to the first location and all data to be shifted by one location When available new data appears on output pins Q and the cascadable output pin Q31 Address A 4 0 The address input selects the bit range 0 to 31 to be read The nth bit is available on the output pin Q Address inputs have no effect on the cascadable output pin 31 It is always the last bit of the shift register bit 31 Virtex 6 FPGA CLB User Guide www xilinx com 47 06364 v1 1 September 16 2009 CLB Primitives XILINX Data Out Q The data output Q provides the data value 1 bit selected by the address inputs Data Out Q31 optional The data output Q31 provides the last bit value of the 32 bit shift register New data becomes available after each shift in operation Inverting Clock Pins The clock pin CLK has an indivi
35. hese and other features of the CLB in detail Additional Documentation The following documents are also available for download at http www xilinx com support documentation virtex 6 htm Virtex 6 Family Overview The features and product selection of the Virtex 6 family are outlined in this overview Virtex 6 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex 6 family Virtex 6 FPGA Packaging and Pinout Specifications This specification includes the tables for device package combinations and maximum I Os pin definitions pinout tables pinout diagrams mechanical drawings and thermal specifications Virtex 6 FPGA Configuration Guide This all encompassing configuration guide includes chapters on configuration interfaces serial and bitstream encryption boundary scan and JTAG configuration reconfiguration techniques and readback through the SelectMAP and JTAG interfaces Virtex 6 FPGA Clocking Resources User Guide This guide describes the clocking resources available in all Virtex 6 devices including the MMCM and PLLs Virtex 6 FPGA Memory Resources User Guide The functionality of the block RAM and FIFO are described in this user guide Virtex 6 FPGA SelectIO Resources User Guide This guide describes the SelectIO resources available in all Virtex 6 devices Virtex 6 FPGA CLB User Guide www xilinx com 5 063
36. his way each LUT can delay serial data anywhere from one to 32 clock cycles The shiftin D DI1 LUT pin and shiftout Q31 MC31 LUT pin lines cascade LUTS to form larger shift registers The four LUTs in a SLICEM are thus cascaded to produce delays up to 128 clock cycles It is also possible to combine shift registers across more than one SLICEM Note that there are no direct connections between slices to form longer shift registers nor is the MC31 output at LUT B C D available The resulting programmable delays can be used to balance the timing of data pipelines Applications requiring delay or latency compensation use these shift registers to develop efficient designs Shift registers are also useful in synchronous FIFO and content addressable memory CAM designs The write operation is synchronous with a clock input CLK and an optional clock enable CE A dynamic read access is performed through the 5 bit address bus A 4 0 The LSB of the LUT is unused and the software automatically ties it to a logic High The configurable shift registers cannot be set or reset The read is asynchronous however a storage element or flip flop is available to implement a synchronous read In this case the clock to out of the flip flop determines the overall delay and improves performance However one additional cycle of clock latency is added Any of the 32 bits can be read out asynchronously at the O6 LUT outputs by varying the 5 bit address This capabi
37. igured as Time before the clock that the data must be stable data input DI at the AI BI CI DI input of the slice configured as an SRL Notes 1 This parameter includes a LUT configured as a two bit shift register 2 Setup Time before clock edge and Tckxx Hold Time after clock edge 3 Parameter includes AX BX CX DX configured as a data input 012 or two bits with a common shift Slice SRL Timing Characteristics Figure 30 illustrates the timing characteristics of a 16 bit shift register implemented in a Virtex 6 FPGA slice a LUT configured as an SRL CLK Write Enable WE Shift In Dl Address A B C D Data Out A B C D MSB MC31 DMUX ug364 30 040209 Figure 30 Slice SRL Timing Characteristics 42 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Slice Timing Models Clock Event 1 Shift In During a write Shift In operation the single bit content of the register at the address on the A B C D inputs is changed as data is shifted through the SRL The data written to this register is reflected on the A B C D outputs synchronously if the address is unchanged during the clock event If the A B C D inputs are changed during a clock event the value of the data at the addressable output A B C D outputs is invalid e Attime Tws before clock event 1 write enable signal WE becomes valid High enabling the S
38. in the same slice CLB Slice Timing Models Due to the large size and complexity of Virtex 6 FPGAs understanding the timing associated with the various paths and functional elements is a difficult and important task Although it is not necessary to understand the various timing parameters to implement most designs using Xilinx software a thorough timing model can assist advanced users in analyzing critical paths or planning speed sensitive designs Three timing model sections are described Functional element diagram basic architectural schematic illustrating pins and connections Timing parameters definitions of Virtex 6 FPGA Data Sheet timing parameters e Timing Diagram illustrates functional element timing parameters relative to each other Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer software TRCE and the section on switching characteristics in the Virtex 6 FPGA Data Sheet All pin names parameter names and paths are consistent with the post route timing and pre route static timing reports Most of the timing parameters found in the section on switching characteristics are described in this chapter All timing parameters reported in the Virtex 6 FPGA Data Sheet are associated with slices and CLBs The following sections correspond to specific switching characteristics sections in the Virtex 6 FPGA Data Sheet General Slice Timing Model and Parameters CLB Switching Characteris
39. l can identify the arithmetic and or logic functionality that best maps to this Virtex 6 FPGA CLB User Guide www xilinx com 49 06364 v1 1 September 16 2009 CLB Primitives 50 XILINX logic in terms of performance and area It also automatically uses and connects this function properly Figure 24 page 33 illustrates the 4 block diagram Port Signals Sum Outputs O 3 0 The sum outputs provide the final result of the addition subtraction Carry Outputs CO 3 0 The carry outputs provide the carry out for each bit A longer carry chain can be created if is connected to CI input of another CARRY4 primitive Data Inputs DI 3 0 The data inputs are used as generate signals to the carry lookahead logic The generate signals are sourced from LUT outputs Select Inputs S 3 0 The select inputs are used as propagate signals to the carry lookahead logic The propagate signals are sourced from LUT outputs Carry Initialize CYINIT The carry initialize input is used to select the first bit in a carry chain The value for this pin is either 0 for add 1 for subtract or AX input for the dynamic first carry bit Carry In The carry in input is used to cascade slices to form longer carry chain To create a longer carry chain the CO 3 output of another is simply connected to this pin www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16
40. lity is useful in creating smaller shift registers less than 32 bits For example when building a 13 bit shift register simply set the address to the 13 bit Figure 15 is a logic block diagram of a 32 bit shift register www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview SRLC32E SHIFTIN MC31 of Previous LUT Al SHIFTIN D SHIFTOUT 031 A 4 0 AGED A 6 2 CLK Output Q EE WE CE Q Registered Output Optional ug364 15 080609 Figure 15 32 bit Shift Register Configuration Figure 16 illustrates an example shift register configuration occupying one function generator 32 bit Shift Register SHIFTIN D WE gt SHIFTOUT Q31 CLK Address A 4 0 Q 10364 16 040209 Figure 16 Representation of a Shift Register Figure 17 shows two 16 bit shift registers The example shown can be implemented in a single LUT Virtex 6 FPGA CLB User Guide www xilinx com 25 06364 v1 1 September 16 2009 CLB Overview XILINX SHIFTIN1 Al n A 3 0 A 5 2 CLK CE SHIFTIN2 AX ug364 17 080609 Figure 17 Dual 16 bit Shift Register Configuration As mentioned earlier an additional output MC31 and a dedicated connection between shift registers allows connecting the last bit of one shift register to th
41. ly the elements relevant to the timing paths described in this section are shown DI D address CLK gt w gt CI C address gt D gt y B address A A address gt DMUX ug364_29_080609 Figure 29 Simplified Virtex 6 FPGA Slice SRL Virtex 6 FPGA CLB User Guide www xilinx com 41 06364 v1 1 September 16 2009 CLB Slice Timing Models XILINX Slice SRL Timing Parameters Table 8 shows the SLICEM SRL timing parameters for a majority of the paths in Figure 29 Table 8 Slice SRL Timing Parameters Parameter Function Description Sequential Delays for a Slice LUT Configured as an SRL to A B C D outputs Time after the CLK of a write operation that the data written to the SRL is stable on the A B C D outputs of the slice Trec CLK to AMUX DMUX output Time after the CLK of a write operation that the data written to the SRL is stable on the DMUX output of the slice M31 CLK to DMUX output via Time after the CLK of a write operation that the MC31 output data written to the SRL is stable on the DMUX output via MC31 output Setup and Hold Times for a Slice LUT Configured SRL 2 Tws TwH CE input WE Time before after the clock that the write enable signal must be stable at the WE input of the slice LUT configured as an SRL Tps Tpg AI BI CI DI conf
42. meters 34 Slice Distributed RAM Timing Model and Parameters Available in SLICEM only 38 Slice SRL Timing Model and Parameters Available in SLICEM only 41 Slice Carry Chain Timing Model and Parameters 44 CEB __ __ _ 45 Distributed RAM Primitives 45 Shift Registers SRLs 47 Other Shift Register Applications 48 Multiplexer Primitives 2 0s 0 049 Re Ie eR RR Y d 49 Carry Chain Primitive i aa eae rp ROC Ga rire rs 49 Virtex 6 FPGA CLB User Guide www xilinx com 06364 v1 1 August 21 2009 XILINX www xilinx com Virtex 6 FPGA CLB User Guide 006364 v1 1 August 21 2009 XILINX Preface About This Guide This guide serves as a technical reference describing Virtex 6 FPGA configurable logic blocks CLBs Usually the logic synthesis software assigns the CLB resources without system designer intervention It can be advantageous for the designer to understand certain CLB details including the varying capabilities of the look up tables LUTs the physical direction of the carry propagation the number and distribution of the available flip flops and the availability of the very efficient shift registers This guide describes t
43. nput of the slice A B C D address inputs Time before after the clock that address signals must be stable at the A B C D inputs of the slice LUT configured as RAM Tws Twu WE input Time before after the clock that the write enable signal must be stable at the WE input of the slice LUT configured as RAM Clock CLK Minimum Pulse Width High Minimum Pulse Width Low Twc Minimum clock period to meet address write cycle time Notes 1 This parameters includes a LUT configured as a two bit distributed RAM 2 Setup Time before clock edge and Hold Time after clock edge 3 Parameter includes AX BX CX DX configured as a data input DI2 Virtex 6 FPGA CLB User Guide 06364 v1 1 September 16 2009 www xilinx com 39 CLB Slice Timing Models XILINX Distributed RAM Timing Characteristics The timing characteristics of a 16 bit distributed RAM implemented in a Virtex 6 FPGA slice LUT configured as RAM are shown in Figure 28 1 2 3 4 5 6 7 gt TwPH TwPL cK H TAS NOK gt Fx 3s X04 ADDR AI BI CI DI DI WE DATA OUT AIBICID 1 DC O gt MEME Output WRITE READ WRITE WRITE WRITE READ ug364 28 080609 Figure 28 Slice Distributed RAM Timing Characteristics Clock Event 1 Write Operation During a Write operation the
44. ookahead logic along with the function generators There are ten independent inputs S inputs 50 to 53 DI inputs to DI4 CYINIT and CIN and eight independent outputs O outputs O0 to O8 and CO outputs CO0 to CO3 The S inputs are used for the propagate signals of the carry lookahead logic The propagate signals are sourced from the O6 output of a function generator The DI inputs are used for the generate signals of the carry lookahead logic The generate signals are sourced from either the O5 output of a function generator or the BYPASS input AX BX CX or DX of a slice The former input is used to create a multiplier while the latter is used to create an adder accumulator CYINIT is the CIN of the first bit in a carry chain The CYINIT value can be 0 for add 1 for subtract or AX input for the dynamic first carry bit The CIN input is used to cascade slices to form a longer carry chain The O outputs contain the sum of the addition subtraction The CO outputs compute the carry out for Virtex 6 FPGA CLB User Guide www xilinx com 33 06364 v1 1 September 16 2009 CLB Slice Timing Models XILINX each bit CO3 is connected to COUT output of a slice to form a longer carry chain by cascading multiple slices The propagation delay for an adder increases linearly with the number of bits in the operand as more carry chains are cascaded The carry chain can be implemented with a storage element or a flip flop
45. ost Significant Bit Changes At time after clock event 32 the first bit shifted into the SRL becomes valid logical 0 in this case on the DMUX output of the slice via the MC31 output of LUT A SRL This is also applicable to AMUX BMUX CMUX DMUX and COUT outputs at time and Twosco after clock event 1 Virtex 6 FPGA CLB User Guide www xilinx com 43 06364 v1 1 September 16 2009 CLB Slice Timing Models XILINX Slice Carry Chain Timing Model and Parameters Figure 24 page 33 illustrates a carry chain in a Virtex 6 FPGA slice Some elements of the slice have been omitted for clarity Only the elements relevant to the timing paths described in this section are shown Slice Carry Chain Timing Parameters Table 9 shows the slice carry chain timing parameters for a majority of the paths in Figure 24 page 33 Table 9 Slice Carry Chain Timing Parameters Parameter Function Description Sequential Delays for Slice LUT Configured as Carry Chain AX BX CX DX input to COUT Propagation delay from the AX BX CX DX output inputs of the slice to the COUT output of the slice input to COUT output Propagation delay from the CIN input of the slice to the COUT output of the slice A B C D input to COUT Propagation delay from the A B C D inputs of output the slice to the COUT output of
46. s at time after clock event 3 CLB Primitives More information on the CLB primitives are available in the software libraries guide Distributed RAM Primitives Seven primitives are available from 32 x 2 bits to 256 x 1 bit Three primitives are single port RAM two primitives are dual port RAM and two primitives are quad port RAM as shown in Table 10 Table 10 Single Port Dual Port and Quad Port Distributed RAM Primitive RAM Size Type Address Inputs RAM32X1S 32 bit Single port A 4 0 read write RAM32X1D 32 bit Dual port A 4 0 read write DPRA 4 0 read RAM32M 32 bit Quad port ADDRA 4 0 read ADDRBJ 4 0 read ADDRC 4 0 read ADDRDf 4 0 read write RAM64X1S 64 bit Single port 5 0 read write RAM64X1D 64 bit Dual port A 5 0 read write DPRA 5 0 read RAM64M 64 bit Quad port ADDRA 5 0 read ADDRB 5 0 read ADDRC 5 0 read ADDRDJ5 0 read write RAM128X1S 128 bit Single port A 6 0 read write RAM128X1D 128 bit Dual port A 6 0 read write DPRA 6 0 read 256 15 256 bit Single port A 7 0 read write The input and output data are 1 bit wide with the exception of the 32 bit RAM Figure 32 shows generic single port dual port and quad port distributed RAM primitives The A ADDR and DPRA signals are address buses Virtex 6 FPGA CLB User Guide www xilinx com 45 06364 v1 1 September 16 2009 CLB Primitives
47. ted RAM configurations occupying one SLICEM When using x2 configuration RAM32X2Q and WA6 are driven High by the software to keep O5 and O6 independent Virtex 6 FPGA CLB User Guide www xilinx com 15 06364 v1 1 September 16 2009 CLB Overview DID 1 DID 0 4 0 WCLK WED ADDRCI4 0 ADDRB 4 0 ADDRA 4 0 16 XILINX RAM 32X2Q 01 AX BX CX DX 06 1 5 5 CLK WE 5 1 al p www xilinx com DPRAM32 gt 2000 2001 DOC 0 WA 6 1 DOCT1 DPRAM32 2080 DPRAM32 DOA 0 DOA 1 ug364 06 080609 Figure 6 Distributed RAM RAM32X2Q Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview RAM 32X6SDP DPRAM32 unused unused WADDR 5 1 WADDRI6 1 WCLK WED DATA 1 DATA 2 5 1 6 1 2 Ort DATA 3 DATA 4 041 DATA 5 DATA 6 6 5 ug364_07_080609 Figure 7 Distributed RAM RAM32X6SDP Virtex 6 FPGA CLB User Guide www xilinx com 17 06364 v1 1 September 16 2009 CLB Overview XILINX RAM64X1S NINE 0 I 6 06 11 5 0 WCLK pa CLK 1 gt Output Regis
48. tered Output Optional ug364_08_080609 Figure 8 Distributed RAM RAM64X1S If four single port 64 x 1 bit modules are built the four RAM64XIS primitives can occupy a SLICEM as long as they share the same clock write enable and shared read and write port address inputs This configuration equates to 64 x 4 bit single port distributed RAM 9 RAM64X1D _____ D _ SPO D Registered l D 6 1 egistere A 5 0 01 1 5 A 6 1 Output WCLK Optional WE IT l I Registered DPRA S 0 B ud I Optional I I ug364_09_080609 Figure 9 Distributed RAM RAM64X1D If two dual port 64 x 1 bit modules are built the two RAM64X1D primitives can occupy a SLICEM as long as they share the same clock write enable and shared read and write port address inputs This configuration equates to 64 x 2 bit dual port distributed RAM 18 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Overview RAM64X1Q poer u ee q oo DID 20 ADDRD 016 1 Registered P e Output WE WE _ Optional I
49. tics Slice Distributed RAM Timing Model and Parameters Available in SLICEM only CLB Distributed RAM Switching Characteristics e Slice SRL Timing Model and Parameters Available in SLICEM only CLB SRL Switching Characteristics e Slice Carry Chain Timing Model and Parameters CLB Application Switching Characteristics General Slice Timing Model and Parameters A simplified Virtex 6 FPGA slice is shown in Figure 25 Some elements of the slice are omitted for clarity Only the elements relevant to the timing paths described in this section are shown 34 www xilinx com Virtex 6 FPGA CLB User Guide 00364 v1 1 September 16 2009 XILINX CLB Slice Timing Models LUT D 6 Inputs O6 C gt D O5 7 DMUX FF LAT DQ DX gt D a CE LUT us C F7BMUX Inputs gt 06 LO C O5 gt CMUX FF LAT CX gt 4 D CQ J B Q CLK FBMUX SR CK LUT x E 6 O6 gt Inputs 1 B O5 T gt BMUX FF LAT BX gt D Q H gt BQ CE CLK D SR CE LUT F7AMUX i A Inputs EFA AMUX AX gt FF LAT CE CK gt AQ SR CELO CLK gt SR gt 19364 25 040209 Figure 25 Simplified Virtex 6 FPGA Slice Virtex 6 FPGA CLB User Guide www xilinx com 35 06364 v1 1 September 16 2009 CLB Slice Timing Models Timing Parameters
50. ts 2 element Flip Flop Latch AX BX CX DX inputs Time before after the CLK that data from the element AX BX CX DxX inputs of the slice must be stable at the D input of the slice sequential elements configured as a flip flop Tpick Flip Flop only AX BX CX DX inputs Time before after the CLK that data from the element AX BX CX DxX inputs of the slice must be stable at the D input of the slice sequential elements Flip Flop Latch CE input Time before after the CLK that the CE input of element the slice must be stable at the CE input of the slice sequential elements configured as a flip flop Flip Flop only CE input Time before after the CLK that the CE input of element the slice must be stable at the CE input of the slice sequential elements Flip Flop Latch SR input Time before after the CLK that the SR Set Reset of the slice must be stable at the SR inputs of the slice sequential elements configured as a flip flop 36 www xilinx com Virtex 6 FPGA CLB User Guide UG364 v1 1 September 16 2009 XILINX CLB Slice Timing Models Table 6 General Slice Timing Parameters Cont d Parameter Function Description Flip Flop only SR input Time before after the CLK that the SR Set Reset element inputs of the slice must be stable at

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