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Hardware User Guide

1. 5 5 E eee eee Di D8 2222 22 2 LmovA swi 111 E L wv Y IRL yyy Us i HE dek 4 HPSP5551 ahhh hhh R 29991 k o se a 2 J1B a 4 56 INTO 2 4 e 8 RN11 TEET RN16 2 1 KA 12 sco LECET seo 560 a BI fost a1 1 i MAREM RB RE 6 51 6 DERRE c5 HARI me 75 O Mi 1 i ke 560 mo O4 EPIS tek G4 k4i h 4 hh4 ms RNG H 7 5 3h c am T5551 ciko elolsisialelsls slelalsisialels 99 855 3585 5 5S8REN deseesee 2229828 eggeeees EgeaRegs i k 2T 43 RESET MoRT 38 INP3 46 Fg o 24 47 23 4g XTLI vo 3g vo vo 21 so vo vo Ha vo o 51 yo U4 vo H2 53 XC3020A ar 347 VO vo 16 35 Vo vo 15 3g VO vo 14 37 vo VO 3 z5 vo vo Hz 39 DIN vo Hi g0 POUT vo Hy i CCLK PWRDN 1 RN7 4 7K 69099999 00000000 1 siglelelglelslel jeje z2O38853 oooooo cur JIA 455 R7 sigigigigigigig ggas ormon i 27K vec 1 da a e e Q s vi OiuF o tuF 7 t 7 DATA L A ca o 4 CLK DONE L s CEO p DIN R ROG 13 T swi aooe Wi CE wr i5 i SPE 3 14 q 17 2 1 MPE 2 15 1765 RST o ol t MCLK 7 310 J5 DOUT 81 o eri R 100K 5 u3 vout 3 oH 1 tya J12 2 c2 ci ca ca c7 ca ceo 5VREG Thur 1 otuF
2. J2B RT 312 RD O 4 TRIG O 6 TDI TeK ms cki cko FPP ppp SARR D9 525 15 1H 1 1 RN18 1 jg geseseco goegecsze g PNIS S z 590 6 swi 8 n N o 8 9 INP cou i e iX i T 13 Packt ok 3 E M uo pour H v 16 IDH O DIN jy TE Tokio vo HE hes 1 Tus vo vo 8 tA vo vo 19 llo 10 67 R4 R5 20 VO bs 1K 1K vo vo HE D U5 vo Pia 23 1S RNG 24 lO XC4003E 62 Lia 47K vec GND CCLK DONE DIN PROG INIT RST D17 5 GND u1 u2 78 5 Us 3 z 5 U4 18 52 1 35 z u5 2 11 33 42 54 1 12 21 31 43 52 HPSP5551 63 74 43 52 64 76 45 3 HPSP5551 Figure 3 6 XC4003E Schematic XC4003E FPGA and Socket U5 X4728 The XC4003E FPGA occupies socket U5 on the demonstration board Hardware User Guide 3 13 Hardware User Guide XC4003E Probe Points All pins of the XC4003E connect to the headers that surround the FPGA socket These pins provide convenient points for probing signals or making wirewrap connections to other circuitry including the prototype area Pin numbering increases from the
3. X4710 Bars Figure 3 1 FPGA Demonstration Board Displays General Components This section describes the common components that are found on the FPGA Demonstration Board The following figure shows the compo nent layout of the FPGA Demonstration Board Xilinx Development System FPGA Design Demonstration Board 2k OOOOC o 9goo OOOOOOO Oo oo OOOO0O0000I Xo 9o OOOO 90000000bO0500090090 00000000 00000 OcOoOoO OOOOOOOOOOOOOOO00000 OOOO 60000000000060000000 0009000 oooo OOOOOOOOOOOOOOOOO0O0OO0O000000000000000 00000000000000000000000000000000000 90000000000000000000000000000000000 JgesoonooaQdo OOOOOOOOOOOOOOO0O000000 O0 IOcCOooo0OoOoOO0O0O 00000000 200 2000000000009 OOcOOOOOOOO00 C 0000000 oo0oo0o0 ooo0oo00000000 oc OOcOO OOOOCOOOOOOO o OOcOO 00000000000 0000 00000000000 O000000C 0000 Qgo00000 20000000000000 oo0oo0o0 ooooooo0oo00000000000000 oooo o000000000000000000000 oooQ EA EAEI oo ooof o gooooooooooooooooooooOQo OOO0O 9 8oooo000000000000000000000000000000 OOOOOOOOOOOO0O0O0O0O0O0O0O0O0000000 oo0oo0o0000 ooo0oo0000000 ooo0oo000 OO AA A D 200 900ggoQo d OOOOOOOCOOOOCOOOOO00 O 90006000 0000090000 566000 9oooog oo g a a OO SS EN NS HO i ESI EN Wigs SIS 7 a 7 4 XC4003E PC84 a
4. pst Flying Lead Connector 1 IA S A U s m I NI ee cK Connections to DP Flying Lead Connector 2 Connections to Target System X8322 Figure 1 9 XChecker Cable and Flying Leads The following figure shows top and bottom views of the XChecker Cable 1 16 Xilinx Development System Cable Hardware Hardware User Guide XChecker Cable Top View Header 2 Header 1 Model DLC4 CAUTION Power 5V 100mA Typ Af A Serial DL 12345 T ELECTRONICCLKI LJ g Made in U S A DEVICE CLKO ERI RST Bottom View X7249 Figure 1 10 XChecker Cable Note The plastic cover of the XChecker Cable is beige while the cover for the Parallel Cable III is grey The flying lead wires are keyed to fit into the appropriate cable header Use Header 1 for FPGAs and Header 2 for CPLDs Hardware User Guide XChecker Baud Rates Communication between your host system and the XChecker Cable is dependent on host system capability The XChecker Cable supports several Baud rates and platforms as shown in the following table Table 1 4 Valid Baud Rates Platform 9600 19200 38400 115 2K IBM PC X X X X NEC PC X SUN X X X HP 700 X X X X X indicates applicable baud rate Configuring CPLDs With the XChecker Cable The JTAG Programmer should be used to prog
5. sssssse 4 1 Software and Download Cable Support sssse 4 1 Printed Circuit Board PCB sssssssseeeee 4 2 Prototyping Area asanes aar oie ce tec eee ee 4 2 Power Supply tirer tee bn e det ie epit tenute 4 2 Demonstration Board Schematics sss 4 3 Foundation Design Tutorial eeeeee 4 5 Example I Schematic Design Entry suus 4 5 Schematic With VHDL Macro Design sesss 4 6 Example 2 VHDL Design Entry esses 4 7 Xilinx Development System Chapter 1 Cable Hardware This chapter gives specific information about connecting and using the In System Programming ISP Download Cables These cables can be used to configure FPGAs and CPLDs The following sections are in this chapter e Cable Overview e Cable Baud Rates e MultiLINX Cable and Flying Leads e External Power for the MultiLINX Cable e Parallel Cable III e XChecker Cable e Download Cable Schematic Cable Overview There are three cables available for use with Xilinx Alliance and Foundation software The MultiLINX Cable supports USB and RS 232 serial port connections the Parallel Cable III supports parallel port and the XChecker Cable supports RS 232 serial ports Selecting a Cable Determine the most suitable cable to use depending upo
6. ssssssss 1 5 External Power for the MultiLINX Cable esses 1 7 Parallel Cable si iccicccs tissbnsdevaisavanais saa adgacisataabeegenaadbendve a A 1 8 Flying beads ais RIS Ai aes on b eq 1 9 Configuring CPLDs With the Parallel Cable lll 1 11 Configuring FPGAs With the Parallel Cable lll 1 13 XGhecker Cable 5 5 6 2 ferret rint tiir ede reve a Peto tee ces ced 1 15 Flying Leads d nda tea atero ds 1 15 XChecker Baud Rates ssseseee eene 1 18 Configuring CPLDs With the XChecker Cable 1 18 Configuring FPGAs With the XChecker Cable 1 19 Hardware User Guide 3 1i vii Hardware User Guide Chapter 2 Chapter 3 viii Pin Connection Considerations ssssssssss 1 20 Cable Connection Procedure sssssssenee 1 21 Setting Up The Cable sssssseeeeeenn 1 22 Download Cable Schematic sees 1 22 MutliLINX Cable Additional MultiLINX Documentation seeeeeeee 2 1 MultiLINX Platform Support 2 2 MultiLINX Flying Wires eese 2 2 MultiLINX B nd Rates seest a E E S 2 8 MultiLINX Power Requirements eene 2 8 External Power for the MultiLINX Cable essss 2 8 Device Configuration Modes ssssssseeeeenn
7. eeseeesess 3 17 Serial PROM Socket U2 sssssssseeeen 3 17 XC3020A Components ieioea tieer a etni aaa a aaa eaa 3 18 XC3020A FPGA and Socket U4 sssseessss 3 19 X63020A Probe POIs 6 dm teer Reit ned 3 19 XC3020A Configuration Switches SWh1 ssssse 3 19 INP Input Switch SW1 1 sse 3 19 MPE Multiple Program Enable SW1 2 sssss 3 20 SPE Single Program Enable SWh1 3 sss 3 20 MO M1 M2 Mode Pins SW1 4 5 6 nesese 3 20 MCLK Master Clock SW1 7 sse 3 21 DOUT Data Out SW1 8 ssssssssseeeen 3 21 XChecker Parallel Cable Ill Connector J1 3 21 Serial PROM Socket U1 ssssssssseee 3 23 Relaxation Oscillator Components R1 C5 R2 C6 3 23 Mode Switch Settings sssssssssssseeene 3 25 Demonstration Board Operation sss 3 30 Demonstration Designs eeeeee 3 30 Design Downloading Checklist ssssssss 3 31 Loading with a Configuration PROM esesesss 3 32 Starting Hardware Debugger sse 3 33 T totlals 5 3 pei ii oe E dina ire apre i M R 3 34 Hardware User Guide ix Hardware User Guide Chapter 4 CPLD Design Demonstration Board Demonstration Board Overview
8. RSI RDY BUSY Figure 1 1 MultiLINX Cable and Flying Lead Connectors The following figure shows the top and bottom view of the Multi LINX Cable 1 6 Xilinx Development System Cable Hardware Top View RT frs PWR RT TDO Je GND TRIG CCLK Ive TDI DONE IN TCK DIN TMS e PROG CLK1 IN Je e INIT CLK2 OUT e RST STATUS CSO GS fe DO TM CSi e o M t i CS2 e D2 u CLK2 IN e D3 CLK2 OUT D4 ce RS RDWR D6 RDY BUSY Le Bottom View CAUTION XILINX vs SENSITIVE ELECTRONIC c c SH M u t j CE Model DLC6 Power 2 5V 7 0 8A to 5V 73 0 4A Typ Serial UC 000074 He Dd Made in U S A UNIVERSAL SERIAL BUS X8927 Figure 1 2 MultiLINX Cable External Power for the MultiLINX Cable The MultiLINX Cable gets its power from the User s circuit board an extended power supply The cable power does not come from the USB port nor the RS 232 port The red PWR and black GND wires from Flying Wire Set 1 are connected to the VCC red wire and Ground black wire lines of the circuit board that is powering the Xilinx device The external power for the MultiLINX Cable is shown in the following figure Hardware User Guide 1 7 Hardware User Guide MultiLINX Connectors aa CLK2 OUT WS RS RDWR RDY BUSY 8 External DC Power Supply tiLINX Cable must be tied to
9. LUTRAMS amp block RAMS CAPTURE CAPCLK gt GCK y Logic dq Capture Contro o optional Veco Figure 2 16 SelectMAP Mode Virtex JTAG Mode In JTAG mode Synchronous Probing is not available 2 24 Xilinx Development System Chapter 3 FPGA Design Demonstration Board The FPGA Demonstration Board Part Number HW FPGABOARD is a stand alone board for experimenting and developing prototypes using the Xilinx FPGA architecture The FPGA Demonstration Board allows you to become familiar with some of the Xilinx FPGA device families and the Xilinx software development system This chapter contains the following sections e Demonstration Board Overview e General Components e XC4003E Components e XC3020A Components e Mode Switch Settings e Demonstration Board Operation Demonstration Board Overview The following sections detail the device and software support for the FPGA Demonstration Board as well as describing the board s general features Device Support The FPGA Demonstration Board supports the following Xilinx FPGA families e XC3000A XC3000L e XC3100A e XCA4000E Hardware User Guide 3 1i 3 1 Hardware User Guide e Spartan Product Families Note The Spartan series is a low cost FPGA family based on the XC4000 devices See the Xilinx web site or th
10. 1 Place and route the design Produce a routed design design name using a design entry tool and the appropriate place and route tool Generate a configuration bitstream for the design design name bit with the appropriate configuration options using the BitGen program Create a PROM file Generate a PROM file design name using the PROMGen program See the PROMGen documentation in the Development System Reference Guide to create a PROM file Note The XC1700 series of configuration serial PROMs must be programmed with the reset polarity set for active Low Place the PROM on the FPGA Demonstration Board After you have a PROM that has a configuration bitstream programmed into it place it into the FPGA Demonstration Board Xilinx Development System FPGA Design Demonstration Board 8 with power off Use the appropriate demonstration board socket for your device e U2 socket XC4003E devices U2 socket XC4003E and XC3020A devices in a daisy chain with the XC4003E at the head of the chain U1 socket XC3020A devices Set the mode switches When you use the serial PROMs the MO M1 and M2 switches must be off This setting causes the device to be in the active master serial mode Set the MPE SPE and RST switches to the desired positions Refer to theTable 3 15 and the Table 3 16 for switch settings required to configure a daisy chain Load the FPGA After you insert the PROM into the socket and set
11. o yo 3 R6 Tek CO x XC9536 S END 470 e moO oeri vo DON X PD wO l B Gck2 vo ESS R8470 Seque msQ 4 o sstccrrrfi Ne Eg 1M us 1 8 cano veco 2 7 RIG DISCH 6 3 OUT THRES 1 9 Ja 5 ESET CONT TLC555 Figure 4 1 XC9536 Device Schematic X8087 The following figure shows the pin layout and components of the ISP Demonstration Board Xilinx Development System CPLD Design Demonstration Board 1234567 891011 f ISP DEMO BOARD Zz OOOOOOOOGOOOOOOOOOOO 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 00000000000000000000000 off Zz o Fb X8163 Figure 4 2 CPLD ISP Demonstration Board All pins of the XC9536 device are connected to through hole pads on the PCB numbered 1 to 44 Header Rows of 0 025 inch square posts on 0 10 inch centers can be installed at these locations to provide connection points for applicati
12. Initialization sequencing pin during configu ration Indicates start of configu ration A logical zero on this pin during configuration indicates a data error 2 4 Xilinx Development System MutliLINX Cable Table 2 2 MultiLINX Pin Descriptions Signal Name RST Function Reset Pin used to reset internal FPGA logic Connection to this pin is optional during configura tion During configuration a Low pulse causes XC3000A devices to restart configuration After configuration this pin can drive Low to reset target FPGA internal latches and flip flops RST is the active high for XC4000 XC5200 devices RT Read Trigger Pin used to initiate a readback of target FPGA MultiLINX output Hardware Debugger provides Low to High transition on RT to initiate readback RD TDO Read Data MultiLINX input Hardware Debugger receives the readback data through the RD pin after readback is initiated Pin used to initiate a readback of target FPGA TDO is for JTAG TRIG System Trigger MultiLINX input High on this pin signals the MultiLINX electronics to initiate a readback and causes the RT pin to go High Hardware User Guide 2 5 Hardware User Guide 2 6 Table 2 2 MultiLINX Pin Descriptions Signal Name RD TDO TDI TCK TMS Function These pins are used for JTAG Programmer device configura tion The JTAG boundary scan pin
13. CPLD Design Demonstration board for design verification Before using this manual you should be familiar with the operations that are common to all Xilinx software tools how to bring up the system select a tool for use specify operations and manage design data These topics are covered in the 2 11 Quick Start Guide Other publications you can consult for related information are the Hardware Debugger Guide and the JTAG Programmer Guide Manual Contents This manual covers the following topics Hardware User Guide 3 1i Chapter 1 Cable Hardware provides specific information about using the MultiLINX Cable Parallel Cable III and XChecker cables to configure CPLDs and FPGAs Chapter 2 MutliLINX Cable provides detailed information about the MultiLINX Cable Flying Wires and Operation Modes Chapter 3 FPGA Design Demonstration Board describes the function and operation of the FPGA Demonstration Board Hardware User Guide e Chapter 4 CPLD Design Demonstration Board describes the function and operation of this board which is used for demon strating the In system Programming ISP capabilities of the XC9500 CPLD family e Glossary defines all the terms you should understand to use Xilinx Hardware Additional Resources For additional information go to http support xilinx com The following table lists some of the resources you can access from this Web site You can also directly access
14. Therefore the pins can be defined as outputs It is also possible to drive the pins from an external source by connecting the source signal to the FPGA probe point header See the following figure for details Hardware User Guide 3 19 Hardware User Guide XC3020A XC4003E X4691 Figure 3 8 Configuration Switch SW1 MPE Multiple Program Enable SW1 2 When MPE is on and SPE is off the configuration PROM U1 is reset by the RESET pushbutton SW4 Configuration must be set to the master serial mode After a Reset or powerup the first bitstream stored in the serial PROM is loaded into the XC3020A FPGA IF you press RESET the serial PROM address pointer is reset If you press PROG SW6 the XC3020A is loaded with the first bitstream again If you press PROG and do not press RESET the XC3020A is loaded with the next bitstream stored in the serial PROM The number of bitstreams that can be sequentially loaded is limited by the size of the serial PROM SPE Single Program Enable SW1 3 When SPE is on and MPE is off the configuration PROM U1 is reset by the XC3020A s INIT output which is driven Low whenever you press PROG SW6 The first bitstream stored in the serial PROM is loaded into the XC3020A FPGA Note MPE and SPE must not be on at the same time MPE and SPE are only used in conjunction with the serial PROMs The serial PROMs must be configured as OE RESET to allow MPE and SPE to function properly MO M
15. 5 734 866 5 734 868 5 737 234 5 737 235 Xilinx Development System Hardware User Guide 5 737 631 5 742 178 5 742 531 5 744 974 5 744 979 5 744 995 5 748 942 5 748 979 5 752 006 5 752 035 5 754 459 5 758 192 5 760 603 5 760 604 5 760 607 5 761 483 5 764 076 5 764 534 5 764 564 5 768 179 5 770 951 5 773 993 5 778 439 5 781 756 5 784 313 5 784 577 5 786 240 5 787 007 5 789 938 5 790 479 5 790 882 5 795 068 5 796 269 5 798 656 5 801 546 5 801 547 5 801 548 5 811 985 5 815 004 5 815 016 5 815 404 5 815 405 5 818 255 5 818 730 5 821 772 5 821 774 5 825 202 5 825 662 5 825 787 5 828 230 5 828 231 5 828 236 5 828 608 5 831 448 5 831 460 5 831 845 5 831 907 5 835 402 5 838 167 5 838 901 5 838 954 5 841 296 5 841 867 5 844 422 5 844 424 5 844 829 5 844 844 5 847 577 5 847 579 5 847 580 5 847 993 5 852 323 5 861 761 5 862 082 5 867 396 5 870 309 5 870 327 5 870 586 5 874 834 5 875 111 5 877 632 5 877 979 5 880 492 5 880 598 5 880 620 5 883 525 5 886 538 5 889 411 5 889 413 5 889 701 5 892 681 5 892 961 5 894 420 5 896 047 5 896 329 5 898 319 5 898 320 5 898 602 5 898 618 5 898 893 5 907 245 5 907 248 5 909 125 5 909 453 5 910 732 5 912 937 5 914 514 5 914 616 5 920 201 5 920 202 5 920 223 5 923 185 5 923 602 5 923 614 5 928 338 5 931 962 5 933 023 5 933 025 5 933 369 5 936 415 5 936 424 5 939 930 5 942 913 5 944 813 5 945 837 5 946 478
16. 5 949 690 5 949 712 5 949 983 5 949 987 5 952 839 5 952 846 5 955 888 5 956 748 5 958 026 5 959 821 5 959 881 5 959 885 5 961 576 5 962 881 5 963 048 5 963 050 5 969 539 5 969 543 5 970 142 5 970 372 5 971 595 5 973 506 5 978 260 5 986 958 5 990 704 5 991 523 5 991 788 5 991 880 5 991 908 5 995 419 5 995 744 5 995 988 5 999 014 5 999 025 6 002 282 and 6 002 991 Re 34 363 Re 34 444 and Re 34 808 Other U S and foreign patents pending Xilinx Inc does not represent that devices shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited Copyright 1991 2000 Xilinx Inc All Rights Reserved Xilinx Development System About This Manual This manual describes the function and operation of Xilinx hardware devices which include the following Cables for downloading designs MultiLINX Cable specific information FPGA Design Demonstration board for design verification
17. Additional MultiLINX Documentation e MultiLINX Platform Support e MultiLINX Flying Wires e Device Configuration Modes Additional MultiLINX Documentation You can access the following mentioned application note with descriptions of device specific design techniques and approaches from the support page at http support xilinx com support searchtd htm The Getting Started with the MultiLINX Guide application note is a quick reference to everything you need to know to use the MultiLINX Cable e Describes using a USB port Mixed Voltage environments connections for all the supported Modes e Describes how to setup a Prototype application for use with the MultiLINX Cable Hardware User Guide 3 1i 2 1 Hardware User Guide e Describes all the cables their capabilities and associated soft ware tools MultiLINX Platform Support The MultiLINX Cable supports the following platforms e Win 95 e Win 98 e WinNT 4 0 e Solaris 2 6 HP102 Table 2 1 MultiLINX Support PR USB RS 232 Win 95 X Win 98 X X Win NT 4 0 X Solaris 2 6 X HP 10 2 X X indicates applicable ports that can be used with the MultiLINX Cable on spec ified platforms MultiLINX Flying Wires The MultiLINX Cable is shipped with four sets of flying lead wires The following figure shows these four sets of MultiLINX flying lead connectors 2 2 Xilinx Development System MutliLINX Cable
18. Gate Array Company are service marks of Xilinx Inc All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx Inc devices and products are protected under one or more of the following U S Patents 4 642 487 4 695 740 4 706 216 4 713 557 4 746 822 4 750 155 4 758 985 4 820 937 4 821 233 4 835 418 4 855 619 4 855 669 4 902 910 4 940 909 4 967 107 5 012 135 5 023 606 5 028 821 5 047 710 5 068 603 5 140 193 5 148 390 5 155 432 5 166 858 5 224 056 5 243 238 5 245 277 5 267 187 5 291 079 5 295 090 5 302 866 5 319 252 5 319 254 5 321 704 5 329 174 5 329 181 5 331 220 5 331 226 5 332 929 5 337 255 5 343 406 5 349 248 5 349 249 5 349 250 5 349 691 5 357 153 5 360 747 5 361 229 5 362 999 5 365 125 5 367 207 5 386 154 5 394 104 5 399 924 5 399 925 5 410 189 5 410 194 5 414 377 5 422 833 5 426 378 5 426 379 5 430 687 5 432 719 5 448 181 5 448 493 5 450 021 5 450 02
19. Hardware User Guide Table 3 6 XChecker Parallel Cable Ill Connector J2 Pin Name Function Pin Name Function J2 5 N C J2 6 TRIG XChecker Cable input that allows an external event to trigger readback of the XC4003E or output a burst of clocks to the XC4003E Connects to tiepoint J10 1 J2 74 CCLK Provides the clock J2 8 N c gt during configura tion or readback Connects to XC4003E input pin 73 J2 9 DONE Indicates when J2 10 TDI Inputs boundary scan configuration is data to the XC4003E complete Connects to XC4003E Connects to pin 15 XC4003E output pin 53 2 11 DIN Provides configura J2 12 TCK Input boundary scan tion data during clock to the XC4003E configuration Connects to pin 16 Connects to XC4003E DIN input pin 71 J2 13 PROG Provides program J2 14 TMS Boundary scan mode pulse causing the input to the XC4003E FPGA to configure Connects to pin 17 Connects to XC4003E PROG input pin 55 3 16 Xilinx Development System FPGA Design Demonstration Board Table 3 6 XChecker Parallel Cable Ill Connector J2 allows XChecker Cable to provide a Resetinput same as pressing the Reset button Pin Name Function Pin Name Function J2 15 INIT Goes Low if CRC J2 16 CLK1 A system clock input to error occurs during XChecker Cable to be configuration controlled and output on Connects to CLKO XC4003E INIT pin Connects to tiepoint J
20. Hardware User Guide The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC3020A and XC4003E FPGAs in a daisy chain from the serial PROM multiple program Table 3 16 Configuring the XC3020A and XC4003E in a Daisy Chain from the Serial PROM Multiple Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE OFF SW2 2 MPE ON SW1 3 SPE OFF SW2 3 SPE OFF SW1 4 MO ON SW2 4 MO OFF SW1 5 M1 ON SW2 5 M1 OFF SW1 6 M2 ON SW2 6 M2 OFF SW1 7 MCLK ON SW2 7 RST X SW1 8 DOUT ON SW2 8 INIT ON X indicates don t care Demonstration Board Operation This section describes how to use the XChecker download cable with the FPGA Demonstration Board and Hardware Debugger software for device configuration Explicit cable connection information is included in the Cable Hardware chapter The information in this section applies to both the XC3020A and the XC4003E devices However for clarity references are only made to the XC4003E FPGA Note The Parallel Cable III can also be used for FPGA configuration For Parallel Cable III connection information refer to the External Power for the MultiLINX Cable section of the Cable Hardware chapter Demonstration Designs Demonstration designs are supplied with Xilinx Foundation and Alliance Series software You can view or edit the demonstration designs Before editing yo
21. LED XC3020A Pin LED XC4003E Pin D1 37 D9 61 D2 36 D10 62 D3 41 D11 65 D4 33 D12 66 D5 32 D13 57 D6 31 D14 58 D7 28 D15 59 D8 29 D16 60 3 10 Xilinx Development System FPGA Design Demonstration Board l O Line Connections There are 16 I O lines that connect the XC3020A and XC4003E FPGAs These are shown in the following table Table 3 5 I O Line Connections for XC3020A and XC4003E Devices I O Line XC3020A Pin XC4003E Pin 0 61 10 1 62 9 2 63 8 3 64 7 4 65 6 5 66 5 6 67 4 7 68 3 8 2 84 9 3 83 10 4 82 11 5 81 12 6 80 13 7 79 14 8 78 15 9 77 Optional Crystal Oscillator Y1 You can add a standard 4 pin crystal oscillator to the FPGA Demon stration Board The oscillator output drives the XC3020A XTL2 input at pin 43 and the XC4003E PGCK1 input at pin 13 Prototype Area The Prototype area is a 0 1 inch grid of holes where you can add additional circuitry to the demonstration board A 5 V bus compo Hardware User Guide 3 11 Hardware User Guide nent side and a ground bus solder side are available on the perim eter of this area There are also locations for filter capacitors XC4003E Components This section describes the components on the FPGA Demonstration Board which are used with the XC4003E device The following sche matic shows this device 3 12 Xilinx Development System FPGA Design Demonstration Board
22. design name exo using the PROMGen program This step is optional since the XChecker and Hardware Debugger software can use the design bit file as input 5 Connect the XChecker Cable to your host system 6 Connect the XChecker Cable to your target system The XChecker Cable draws its power from the target system through the VCC and GND wires Therefore power to the XChecker Cable and the target FPGA must be stable Do not connect the XChecker Cable pins to any signals before connecting VCC and ground to the FPGA Demonstration Board When you use the XChecker Cable to download only one of the two keyed connectors are needed Hardware User Guide 9 Connect XChecker to J1 for the XC3020A and J2 for the XC4003E on the FPGA Demonstration Board Set the mode switches When you use the XChecker Cable the M0 M1 and M2 switches must be on This setting causes the device to be in the serial slave mode Refer to the Table 3 14 for the switch settings necessary to configure a daisy chain Power up the target system 10 Start your software package For information on starting the Hardware Debugger software see the Starting Hardware Debugger section Loading with a Configuration PROM If you already have a design programmed in a PROM skip to step 5 You can also view or edit the demonstration designs supplied with the Xilinx software tools Note Make backups before making changes to any demonstration design files
23. inside row to the outside counterclockwise See the corners of each header for the starting number of that header XC4003E Configuration Switches SW2 The following sections describe each of the SW2 switches For more information on configuring the XC40003E device see the Mode Switch Settings section PWR Power SW2 1 This switch turns the unregulated power input on or off to the 5 V regulator U3 MPE Multiple Program Enable SW2 2 With MPE turned on and SPE turned off the configuration PROM U2 is reset by the RESET pushbutton SW4 Configuration mode must be set to master serial After a Reset or powerup the first bitstream stored in the serial PROM is loaded into the XC4003E Pressing RESET resets the serial PROM address pointer Pressing PROG SW6 loads the XC4003E with the first bitstream again If you press PROG without pressing RESET the XC4003E is loaded with the next bitstream that is stored in the serial PROM The size of the serial PROM limits the number of bitstreams that can be sequentially loaded SPE Single Program Enable SW2 3 With SPE turned on and MPE turned off the configuration PROM U2 is reset by the XC4003E s INIT output which is driven Low whenever you press PROG SW6 The first bitstream stored in the serial PROM is loaded into the XC4003E Note MPE and SPE must not be on at the same time one must be off when the other is on MPE and SPE are only used in conjunction with 3 14
24. jotuF orur jotuF o tuF s Od Qu o tuF 5 X9242 Figure 3 7 XC3020A Schematic 3 18 Xilinx Development System FPGA Design Demonstration Board XC3020A FPGA and Socket U4 The XC3020A FPGA occupies socket U4 on the demonstration board XC3020A Probe Points All pins of the XC3020A FPGA connect to the headers that surround the FPGA socket These pins provide convenient points for probing signals or making wirewrap connections to other circuitry such as the prototype area Pin numbering increases from the inside row to the outside counterclockwise See the corners of each header for the starting number of that header Refer to Table 3 5 for information The XC3020A I O pins 2 through 9 and 61 through 68 connect to XC4003E pins 3 through 10 and 77 through 84 respectively The XC3020A pins share the XC4003E probe points header XC3020A Configuration Switches SW1 The following sections describe each of the SW1 switches For more information on configuring the XC3020A device see the Mode Switch Settings section INP Input Switch SW1 1 INP is an extra switch which you can connect to provide an extra logic input to the XC3020A pin 46 and the XC4003E pin 69 The FPGA input pins are set to a logic 1 when the switch is on and a logic 0 when the switch is off The FPGA pins connected to this switch are intended for use as inputs However the pins have a 1 kilohm resistor that isolates them from the switch
25. 1 M2 Mode Pins SW1 4 5 6 To configure the XC3020A using the XChecker Parallel Cable III these switches must be on This places the FPGA in slave serial mode 3 20 Xilinx Development System FPGA Design Demonstration Board To configure from the onboard serial PROM these switches must be off This places the FPGA in master serial mode MCLK Master Clock SW1 7 When this switch is on it connects the XC4003E configuration clock pin 73 to the configuration clock on the XC3020A pin 60 This connection is used to configure FPGAs in a daisy chain with the XC4003E at the head DOUT Data Out SW1 8 When this switch is on it connects the XC4003E data out line pin 72 to the data in line of the XC3020A This connection configures FPGAs in a daisy chain with the XC4003E at the head Note MCLK and DOUT should only be used to configure the FPGAs in a daisy chain XChecker Parallel Cable Ill Connector J1 The following table describes the pins and functions of the XChecker Parallel Cable III J1 connector Table 3 7 XChecker Parallel Cable Ill Connector J1 Pin Name Function Pin Name Function J1 12 VCC Supplies 5 V tothe 1 2 RT Allows XChecker XChecker Cable Cable to trigger a read back of the XC3020A Connects to XC3020A pin 26 J1 3 GND Supplies ground J1 4 IRD Used by XChecker reference to Cable for readback XChecker Cable data Connects to XC3020A pin 25 Hardware User Guide
26. 10 41 2 J2 17 RST Connects to jumper J2 18 CLKO A system clock output J7 If connected controlled by XChecker Cable Used to single step or burst clocks to the XC4003E Connects to tiepoint J10 3 a Denotes pins supported by the Parallel Cable III b No pin connection The D P wire from the FPGA header on the Parallel Cable III is connected to J2 9 DONE pin Jumper J7 and Tiepoints J10 1 3 Jumper J7 allows the XChecker signal RST on J2 17 to drive the reset line on the demonstration board Tiepoint pins jumper the following XChecker signals into the circuit Tiepoint J10 1 connects to TRIG on J2 6 Tiepoint J10 2 connects to CLK1 on J2 16 and Tiepoint J10 3 connects to CLKO on J2 18 See the preceding table for more details on the cable and pin connections Serial PROM Socket U2 This serial PROM configures the XC4003E or the XC4003E and XC3020A connected in a daisy chain The configuration mode must be in the master serial mode to configure from the serial PROM Hardware User Guide Hardware User Guide XC3020A Components This section describes the components on the FPGA Demonstration Board which are for the XC3020A device The following figure is a schematic of the FPGA Demonstration Board utilizing this device
27. 2 5 453 706 5 455 525 5 466 117 5 469 003 5 475 253 5 477 414 5 481 206 5 483 478 5 486 707 5 486 776 5 488 316 5 489 858 5 489 866 5 491 353 5 495 196 5 498 979 5 498 989 5 499 192 5 500 608 5 500 609 5 502 000 5 502 440 5 504 439 5 506 518 5 506 523 5 506 878 5 513 124 5 517 135 5 521 835 5 521 837 5 523 963 5 523 971 5 524 097 5 526 322 5 528 169 5 528 176 5 530 378 5 530 384 5 546 018 5 550 839 5 550 843 5 552 722 5 553 001 5 559 751 5 561 367 5 561 629 5 561 631 5 563 527 5 563 528 5 563 529 5 563 827 5 565 792 5 566 123 5 570 051 5 574 634 5 574 655 5 578 946 5 581 198 5 581 199 5 581 738 5 583 450 5 583 452 5 592 105 5 594 367 5 598 424 5 600 263 5 600 264 5 600 271 5 600 597 5 608 342 5 610 536 5 610 790 5 610 829 5 612 633 5 617 021 5 617 041 5 617 327 5 617 573 5 623 387 5 627 480 5 629 637 5 629 886 5 631 577 5 631 583 5 635 851 5 636 368 5 640 106 5 642 058 5 646 545 5 646 547 5 646 564 5 646 903 5 648 732 5 648 913 5 650 672 5 650 946 5 652 904 5 654 631 5 656 950 5 657 290 5 659 484 5 661 660 5 661 685 5 670 896 5 670 897 5 672 966 5 673 198 5 675 262 5 675 270 5 675 589 5 677 638 5 682 107 5 689 133 5 689 516 5 691 907 5 691 912 5 694 047 5 694 056 5 724 276 5 694 399 5 696 454 5 701 091 5 701 441 5 703 759 5 705 932 5 705 938 5 708 597 5 712 579 5 715 197 5 717 340 5 719 506 5 719 507 5 724 276 5 726 484 5 726 584
28. 2 13 Verification of Configuration Data Only XC3000 Synchronous Probing This section details the connections needed for synchronous probing using the MultiLINX Cable Slave Serial Mode XC3000 The following figure shows in detail the Slave Serial Mode connec tions for synchronous probing using the XC3000 device Hardware User Guide 2 21 Hardware User Guide MultiLINX Connectors cso cs s s po csi cs2 CLK2 IN D3 CLK2 QUT 9 D4 WS ea RS RDWR D6 RDY BUSY I O TRIGG User M1 RDATA MONRTRIG Figure 2 14 Slave Serial Mode XC3000 Slave Serial Mode Spartan XC5200 XC4000 The following figure shows in detail the Slave Serial Mode connec tions for synchronous probing using Spartan XC5200 and XC4000 devices 2 22 Xilinx Development System MutliLINX Cable MultiLINX Connectors cso CS csi ws e RS RDWR RDY BUSY User I GESET F User I O User I 0 User 1 0 TRIGd X8929 Figure 2 15 Slave Serial Mode Spartan XC5200 XC4000 SelectMAP Mode Virtex The following figure shows in detail the Select MAP Mode connec tions for synchronous probing using Virtex devices Hardware User Guide 2 23 Hardware User Guide MultiLINX Connectors RDY BUSY BUSY DOU WRITE cs
29. 2M Currently USB is currently not USB USB is supported only supported on WorkSta on Win98 tions MultiLINX Cable 9600 19200 38400 9600 19200 and 38400 RS 232 and 57600 Parallel Cable 9600 Not supported on Workstations XChecker Cable 9600 19200 38400 9600 19200 and 38400 and 115200 MultiLINX Cable and Flying Leads The MultiLINX Cable is a device for configuring and verifying Xilinx FPGAs and CPLDs The MultiLINX Cable is shipped with four sets of flying lead wires A USB Cable and RS 232 Cable with adapter are also supplied For detailed information on the MultiLINX Flying Wires supported modes refer to the MutliLINX Cable chapter The following figure shows the MultiLINX Cable hardware and flying lead connection wires Hardware User Guide Hardware User Guide RT few unen i s GND TRIG XILINX E TMS e CLK1 IN INIT CLK2 OUT RST 4 C80 C e DO ee Mu t CLKZ IN D3 CLK2 OUT D4 Wee RS ROWA D6 RDY BUSY le MultiLINX Flying Lead Connector Set 1 a a GND CCLK DONE D P DIN PROG INIT RST 1 MultiLINX Flying Lead Connector Set 2 RT RD TDO TRIG TDI TCK TMS CLK1 IN CLK1 OUT MultiLINX Flying Lead Connector Set 3 7 EE DO m D1 MultiLINX Flying Lead Connector Set 4
30. 3 21 Hardware User Guide Table 3 7 XChecker Parallel Cable Ill Connector J1 Pin Name Function Pin Name Function J1 5 N C J1 6 TRIG XChecker Cable input that allows an external event to trigger read back of the XC3020A or outputting a burst of clocks to the XC3020A Connects to tiepoint J3 1 J1 7 CCLK Provides clock J1 8 N C5 during configura tion or readback Connects to XC3020A input pin 50 J1 93 D P Starts configuration J1 10 N C P and indicates completion Connects to XC3020A DONE PROGRAM pin 45 J1 11 DIN Provides configura J1 12 N C tion data during configuration Connects to XC3020A DIN input pin 58 J1 13 N C Ji 14 N CP 3 22 Xilinx Development System FPGA Design Demonstration Board Table 3 7 XChecker Parallel Cable Ill Connector J1 Pin Name Function Pin Name Function J1 15 N C b J1 16 CLKI System clock input to XChecker Cable to be controlled and output on CLKO Connects to tiepoint J3 2 J1 17 RST Connects to jumper J1 18 CLKO System clock output J5 If connected controlled by allows XChecker XChecker Cable used Cable to provide a to single step or burst Reset input same as clocks to the XC3020A pressing Reset Connects to tiepoint button J3 3 a Denotes pins supported by the Parallel Cable III b No pin connection Jumper J5 allows the XChecker Cable signal RST on J1 17 to drive the reset line o
31. E devices using the XChecker Parallel Cable III configure the XC4003E FPGA first If you configure the XC3020A first its configuration is lost when the XC4003E FPGA configures because the PROG signal connects directly to the XC4003E PROG input and through a diode to the XC3020A DONE PROG input The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC3020A FPGA from the serial PROM Table 3 10 Configuring the XC3020A from the Serial PROM Single Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE OFF SW2 2 MPE X SW1 3 SPE ON SW2 3 SPE X SW1 4 MO OFF SW2 4 MO X SW1 5 M1 OFF SW2 5 M1 X SW1 6 M2 OFF SW2 6 M2 X Xilinx Development System FPGA Design Demonstration Board Hardware User Guide Table 3 10 Configuring the XC3020A from the Serial PROM Single Program Switch Name Position Switch Name Position SW1 7 MCLK OFF SW2 7 RST X SW1 8 DOUT OFF SW2 8 INIT OFF X indicates don t care The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC4003E FPGA from the serial PROM Table 3 11 Configuring the XC4003E from the Serial PROM Single Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE X SW2 2 MPE OFF SW1 3 SPE X SW2 3 SPE ON SW1 4 MO X SW2 4 MO OFF SW1 5 M1 X SW2 5 M1 OF
32. F SW1 6 M2 X SW2 6 M2 OFF SW1 7 MCLK OFF SW2 7 RST X SW1 8 DOUT OFF SW2 8 INIT OFF X indicates don t care The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC3020A FPGA from the serial PROM multiple program Table 3 12 Configuring the XC3020A from the Serial PROM Multiple Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE ON SW2 2 MPE X SW1 3 SPE OFF SW2 3 SPE X SW1 4 MO OFF SW2 4 MO X SW1 5 M1 OFF SW2 5 M1 X Hardware User Guide Table 3 12 Configuring the XC3020A from the Serial PROM Multiple Program Switch Name Position Switch Name Position SW1 6 M2 OFF SW2 6 M2 X SW1 7 MCLK OFF SW2 7 RST X SW1 8 DOUT OFF SW2 8 INIT OFF X indicates don t care The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC4003E FPGA from the serial PROM multiple program Table 3 13 Configuring the XC4003E from the Serial PROM Multiple Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE X SW2 2 MPE ON SW1 3 SPE X SW2 3 SPE OFF SW1 4 MO X SW2 4 MO OFF SW1 5 M1 X SW2 5 M1 OFF SW1 6 M2 X SW2 6 M2 OFF SW1 7 MCLK OFF SW2 7 RST X SW1 8 DOUT OFF SW2 8 INIT OFF X indicates don t care The following table lists the names and
33. Hardware User Cable Hardware Guide MutliLINX Cable FPGA Design Demonstra tion Board CPLD Design Demonstra tion Board Glossary Hardware User Guide Alliance 3 1i Printed in U S A Hardware User Guide Hardware User Guide XILINX The Xilinx logo shown above is a registered trademark of Xilinx Inc ASYL FPGA Architect FPGA Foundry NeoCAD NeoCAD EPIC NeoCAD PRISM NeoROUTE Timing Wizard TRACE XACT XILINX XC2064 XC3090 XC4005 XC5210 and XC DS501 are registered trademarks of Xilinx The shadow X shown above is a trademark of Xilinx Inc All XC prefix product designations A K A Speed Alliance Series AllianceCORE BITA CLC Configurable Logic Cell CoolRunner CORE Generator CoreLINX Dual Block EZTag FastCLK FastCONNECT FastFLASH FastMap Fast Zero Power Foundation HardWire IRL LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroVia MultiLINX PLUSASM PowerGuide PowerMaze QPro RealPCl RealPCl 64 66 Selectl O SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch Smartspec SMARTSwitch Spartan TrueMap UIM VectorMaze VersaBlock VersaRing Virtex WebFitter WebLINX WebPACK XABEL XACTstep XACTstep Advanced XACTstep Foundry XACT Floorplanner XACT Performance XAM XAPP X BLOX X BLOX plus XChecker XDM XDS XEPLD Xilinx Foundation Series XPP XSI and ZERO are trademarks of Xilinx Inc The Programmable Logic Company and The Programmable
34. MultiLINX Flying Lead Connector Set 1 MultiLINX Flying Lead Connector Set 3 L3 DO MultiLINX Flying Lead Connector Set 4 CLK2 IN CSO CS CLK2 OUT WS RS RDWR RDY BUSY X8919 Figure 2 1 MultiLINX Flying Wires The MultiLINX Flying wires are described in the following table Table 2 2 MultiLINX Pin Descriptions Signal Name Function PWR Power Supplies VCC to cable Works at multiple voltages 5V 3 3V and 2 5V GND Ground Supplies ground refer ence to cable Hardware User Guide 2 3 Hardware User Guide Table 2 2 MultiLINX Pin Descriptions Signal Name Function CCLK Configuration Clock is the configuration clock pin and the default clock for readback opera tion DONE D P Done Program represents the D P pin for XC3000A L and XC3100A devices and DONE for XC4000 XC5200 and Spartan devices This pin indicates that the configuration process is complete for XC4000 XC5200 and Spartan devices This same pin initiates a reconfiguration and indicates that the configura tion process is complete on XC3000 FPGAs DIN Data In Provides configuration data to target system during configuration and is tristated at all other times PROG Program A Low indicates the device is clearing its configura tion memory Active Low signal to initiate the configuration process INIT Initialize
35. User I O TRIGGER PROG TDO Heck y 3 SX ice if applicable X8934 Figure 2 11 JTAG Mode XC9000 Virtex Spartan XC5200 XC4000 Verification of Configuration Data Only This section details the connections needed for verification of config uration data only using the MultiLINX Cable Verification of Configuration Data Only Spartan XC5200 XC4000 The following figure shows in detail the connections for verification of configuration data only with Spartan XC5200 and XC4000 devices Hardware User Guide 2 19 Hardware User Guide MultiLINX Connectors 43 cso cs s D0 csi e pi RT e TDO 3 GND TRIG i CCLK C c a DONE D P N P DIN MS PROG a D7 RDY BUSY X8933 Figure 2 12 Verification of Configuration Data Only Spartan XC5200 XC4000 Verification of Configuration Data Only XC3000 The following figure shows in detail the connections for verification of configuration data only with the XC3000 device 2 20 Xilinx Development System MutliLINX Cable MultiLINX Connectors cso cs po RT s Pw csi GND RIG Cs2 n CLK2 IN s D3 S CCLK CLK2 OUT pa E DONE D P WS DIN RS RDWR Db6 RDY BUSY I O TRIGG User M1 RDATA MO RTRIG X8932 Figure
36. Xilinx Development System FPGA Design Demonstration Board the serial PROMs The serial PROMs must be configured as OE Reset to allow MPE and SPE to function properly Mo M1 M2 Mode Pins SW2 4 5 6 These three switches must be on to configure the XC4003E using the XChecker Parallel Cable III When these switches are on the FPGA is in slave serial mode To configure the XC4003E from the onboard serial PROM these three switches must be off This places the FPGA in master serial mode RST Reset SW2 7 When this switch is on it connects the RESET pushbutton SW4 to INIT Initialize SW2 8 XC4003E pin 56 When this switch is on it connects the XC3020A INIT pin to the XC4003E INIT pin This connection is used to configure FPGAs ina daisy chain with the XC4003E at the head of the chain Note INIT should only be used to configure FPGAs in a daisy chain XChecker Parallel Cable Ill Connector J2 The following table provides a detailed description of the J2 XChecker Parallel Cable III connector Table 3 6 XChecker Parallel Cable Ill Connector J2 Pin Name Function Pin Name Function J2 1 VCC Supplies 5 V to the J2 2 RT Read Trigger allows cable XChecker Cable to trigger a readback of the XC4003E Connects to XC4003E pin 32 J2 3 GND Supplies ground J2 4 RD Used by XChecker Cable reference to the for readback data cable Connects to XC4003E pin 30 Hardware User Guide 3 15
37. ated Power Input J12 seeesss 3 6 5 V Regulator Option U3 ssssseeee 3 6 Xilinx Development System Contents RESET Pushbutton SW4 0 ccccececceeeeeeeeceeeeeeeaeeeeeeeeeenaeeeennees 3 7 SPARE Pushbutton SW5 cccccssseeeeeeeeeeeeeeeseeeeseeeeteeeeees 3 7 PROG Pushbutton SW6 cecccceeeeeeeeeeeeeeeeeeeeeeeesenaeeeeneees 3 7 Eight General Purpose Input Switches SW S 3 7 Seven Segment Displays U6 U7 U8 sss 3 9 LED Indicators D1 D8 D9 D16 seeseeeesse 3 10 I O Eine Gonnectioris idee dee ern ei 3 11 Optional Crystal Oscillator Y 1 3 11 Prototype Area tec tes tel egeo i rep iG recetas bug 3 11 XC4003E Components sssssssseee nennen 3 12 XC4003E FPGA and Socket U5 sess 3 13 XC4003E Probe Points ssssesssseeennn 3 14 XC4003E Configuration Switches SW2 3 14 PWR Power SW2 1 sse 3 14 MPE Multiple Program Enable SW2 2 ssss 3 14 SPE Single Program Enable SW2 3 sss 3 14 MO M1 M2 Mode Pins SW2 4 5 6 n se 3 15 RST Reset SW2 7 esses 3 15 INIT Initialize SW2 8 sss 3 15 XChecker Parallel Cable Ill Connector J2 3 15 Jumper J7 and Tiepoints J10 1 3
38. connec tions between the Parallel Cable III CPLD flying leads and a target system Hardware User Guide 1 11 Hardware User Guide TDI TDO g TMS T JTAG Flying Lead Connector Target System X83 Figure 1 6 Parallel Cable Ill Connections to CPLD Device The following table describes the pin functions and connections for configuring CPLDs with the Parallel Cable III Table 1 3 Parallel Cable Ill CPLD Pin Connections Name Function Connections VCC Power Supplies VCC 5 To target system VCC V 10 mA typically to the cable GND Ground Supplies ground To target system reference to the cable ground TCK Test Clock Drives the test Connect to system TCK logic for all devicesona__ pin JTAG chain TDO Test Data Output data Connect to system from the target system is TDO pin read at this pin 1 12 Xilinx Development System Cable Hardware Table 1 3 Parallel Cable Ill CPLD Pin Connections Name Function Connections TDI Test Data Input this Connect to system TDI signal is used to transmit pin serial test instructions and data TMS Test Mode Select this Connect to system TMS signal is decoded by the pin JTAG state machine to control test operations Note TRST is an optional pin in the JTAG IEEE 1149 1 specification and is not used by XC9500 CPLDs If any of your non Xilinx parts have a TRST pin the pin s
39. e 1998 Xilinx Databook for more information about Spartan Download Cable Support The FPGA Demonstration Board is shipped with two short ribbon cables which can be used to configure FPGAs You can also configure designs with the XChecker Cable slave serial mode the onboard XC1700PD8 PROM master serial mode or the Parallel Cable III a JTAG Cable For more information on connecting XChecker Cable or the Parallel Cable IIL see the Cable Hardware chapter Software Support Board 3 2 Two Xilinx software packages can be used with this demonstration board e XChecker is a command line text only program available for both PC and Workstation platforms The XChecker Software supports the XChecker Cable only e Hardware Debugger a GUI type program is the recommended software for use with this demonstration board For more infor mation on using Hardware Debugger with the demonstration board see the Demonstration Board Operation section Features The FPGA Demonstration Board is shipped with two devices the XC3020APC68 and XC4003EPC84 The board has the following features e One socket for an XC3000 PC68 device e One socket for an XC4000 PC84 device e One XC1700PD8 socket for each FPGA e An XChecker Parallel Cable III header for each FPGA e Daisy chain configuration with the XC4000 device at the head of the chain Xilinx Development System FPGA Design Demonstration Board e Total of three 8 pin DIP switches
40. e Xilinx configuration cables They include JTAG SelectMAP and Slave Serial Complex Programmable Logic Device CPLD is an erasable programmable logic device that can be programmed with a schematic or a behavioral design A daisy chain is a series of bitstream files concatenated in one file It can be used to program several FPGAs connected in a daisy chain board configuration Dowloading is the process of configuring or programming a device by sending bitstream data to the device FPGA Flying Lead Connector FPGA flying lead connectors connect your target FPGA to the FPGA demonstration board Hardware User Guide 3 11 Glossary 1 Hardware User Guide FPGA Lead Wires FPGA lead wires connnect to the Parallel Cable III GUI Based Program A graphical program used for accessing the implementation tools In System Programming ISP A programmable logic device that can be programmed after it has been connected to the system pc board JTAG Mode JTAG Mode is a MultiLINX configuration mode supported by the following MultiLINX devices Virtex Spartan XC9500 XC5200 and XC4000 MultiLINX Cable The MultiLINX cable is a device for configuring and verifying Xilinx FPGAs and CPLDs MultiLINX Flying Wires The MultiLINX flying wires consist of four sets that are included with the MultiLINX Cable Parallel Cable Ill Parallel Cable III is a cable assembly which contains a buffer to protect your PCs parallel port and a set o
41. ee 2 10 Downloading Configuration Data sseesessss 2 10 Slave Serial Mode XC3000 sss 2 10 Downloading Configuration Data or Verification of Data 2 12 SelectMAP Mode Virtex sssseeeeenme 2 12 Downloading Configuration Data sssessss 2 13 JTAG Mode XC9000 Virtex Spartan XC5200 XC4000 2 13 Downloading Verification of Configuration Data 2 14 Slave Serial Mode XC3000 sss 2 14 Slave Serial Mode Spartan XC5200 XC4000 2 15 SelectMAP Mode Virtex sse 2 16 SelectMAP Mode Virtex with Asynchronous Probing 2 17 JTAG Mode XC9000 Virtex Spartan XC5200 XC4000 2 18 Verification of Configuration Data Only sssssss 2 19 Verification of Configuration Data Only Spartan XC5200 XC4000 2 19 Synchronous Probing cce t tee rr hein edt 2 21 Slave Serial Mode XC3000 sss 2 21 FPGA Design Demonstration Board Demonstration Board Overview sse 3 1 Device Support esee 3 1 Download Cable Support eee 3 2 Software Support eee eee cece eee cere eeaeeeeeeeeeeeteaeeeeessaeeeaaes 3 2 Board Features iae eee e ues 3 2 General Components sesssssssssseseeeeeenenennn nnne 3 4 5 V Power Connector JQ ssssssssseeene 3 5 Unregul
42. es an interbook link which is a cross reference to another book Click the red underlined text to open the specified cross reference Xilinx Development System e Blue underlined text indicates an intrabook link which is a cross reference within a book Click the blue underlined text to open the specified cross reference Hardware User Guide v Hardware User Guide vi Xilinx Development System Contents About This Manual Manual Contents cuatreyucehuhdwatawenatan tr Ese beatae pelea uta da xara Toren de dn i Additional Resources seeesssssseseeeeeeeeeeenen nnne nnne ii Conventions Typographical teer tetti etti ep Ebo vitre erben iii Online Document sssssssee eene nnne enne iv Chapter 1 Cable Hardware Gable Overviews su tierelbecasecor tres eva risit A den tn 1 1 Selecting a Cable sssssssssssseeeeeneeenn 1 1 MultibINX Gable i rero eec ete tite 1 1 Parallel Cable tiere rei de te ii 1 2 XGhiecker Cable aa a rra eb Iesv et exta eire a sara eit sonia 1 2 Software Support sssssssssssseseeeeeeen enn 1 2 Gable Eimitations uote t tei ke D Reha 1 3 XChecker Hardware Drawbacks eese 1 3 MultiLINX Hardware Advantagges esses 1 3 Previous Cable Versions ccccccccceceessesseaeeeseeeeeeseeeeeseees 1 4 Gable Baud Rates de Advent iie dee re e teta 1 5 MultiLINX Cable and Flying Leads
43. es properly to your host and target system For information on connecting cables and powering up the demonstration board refer to the Cable Hardware chapter Hardware User Guide 3 1i 4 Hardware User Guide This demonstration board is supported by the JTAG Programmer Software For more information about using this software refer to the JTAG Programmer Guide Printed Circuit Board PCB The Printed Circuit Board is shipped with a 44 pin VOFP XC9536 device with two bypass capacitors 8 LEDs with current limiting resistors and a header for attaching the download cable The PCB will accept a DPDT switch or a permanent jumper at loca tion SW1 The switch is used to connect or disconnect an external DC voltage from the 5V regulator Prototyping Area A prototyping area is included on the PCB This area has 299 holes 13 columns x 23 rows for attaching additional circuitry The holes are 0 038 inch diameter on 0 10 inch centers Two pairs of these holes are connected to 5V and GND along the left side of the prototyping area Power Supply The Demonstration Board allows the attachment of an external regu lated 5V power supply via the pads at J2 Ifa 5V regulator is installed at location U2 with a 22uF or larger filter capacitor at C4 an external DC voltage of 7V to 12V can be applied at location J3 You can also install an outer case battery 5V regulator filter capac itor and on off switch on the demonstrati
44. est Mode Select this Connect to system TMS signal is decoded by the pin TAP controller to control test operations CLKI Not used Unconnected CLKO Not used Unconnected CCLK Not used Unconnected D P Not used Unconnected DIN Not used Unconnected PROG Not used Unconnected INIT Not used Unconnected RST Not used Unconnected RT Not used Unconnected TRIG Not used Unconnected Configuring FPGAs With the XChecker Cable This section details the connections needed to configure FPGAs with the XChecker Cable Note If you are using the Xilinx FPGA Design Demonstration Board see the Demonstration Board Operation section of the FPGA Design Demonstration Board chapter for specific configuration information Hardware User Guide 1 19 Hardware User Guide The following figures show which pins to connect depending on your chosen FPGA device For descriptions of each pin see Table 3 6and Table 3 7 of the FPGA Design Demonstration Board chapter Use Header 1 see Figure 1 9 to connect the XChecker Cable to the target system for configuring FPGAs When configuring XC4000 FPGAs the RST Reset wire is not used as shown in the following figure Done CK O O See eee wr 4000 FPGA in Slave Serial Mode el XChecker with Header 1 Target System Figure 1 11 XChecker Connections to XC4000 Device To configure XC3000 FPGAs t
45. f the circuit board that is powering the Xilinx device The minimum input voltage to the cable is 2 5 V 8 A The maximum input voltage is 5 V 4 A External Power for the MultiLINX Cable An optional method of powering the MultiLINX Cable is to use an external DC power supply not supplied as shown in the following 2 8 Xilinx Development System MutliLINX Cable Optional External Power for the MultiLINX Cable figure Typical current requirements are 300 mA at 2 5 V Note The voltage supplied to the MultiLINX Cable does not need to be the same voltage powering the Xilinx device The cable generates its own voltages from the power supplied to it MultiLINX Connectors D7 CLK1 IN INIT CLK1 OUT E RST 21 RDY BUSY External DC Power Supply ltiLINX Cable must be tied together 5 X8928 Figure 2 2 Optional External Power for the MultiLINX Cable When using an external power supply make sure that the ground of the supply the MultiLINX Cable and the circuit board are all tied together An advantage of the external DC power supply is that no power is taken away from the circuit board and the MultiLINX Cable Hardware User Guide 2 9 Hardware User Guide can remain powered up and does not get powered down when the circuit board power is off Device Configuration Modes The various MultiLINX device configuration modes supported for each device are shown in the following
46. f headers to connect to your target system Readback Readback is the process of reading the logic downloaded to an FPGA device Glossary 2 Xilinx Development System RS 232 Port The RS 232 Port is where the MultiLINX cable connects to on the host computer This is how the MultiLINX cable hardware communicates with the host SelectMAP Mode SelectMAP mode is a MultiLINX configuration mode supported by the MultiLINX device Virtex Slave Serial Mode Slave Serial Mode is a MultiLINX configuration mode supported by the following MultiLINX devices Virtex Spartan XCS5200 and XC3000 Universal Serial Buss USB Port The USB Port is where the MultiLINX cable connects to on the host computer XChecker Cable The XChecker hardware consists of a cable assembly with internal logic a test fixture and a set of headers to connect the cable to your target system Hardware User Guide Glossary 3 Hardware User Guide Glossary 4 Xilinx Development System
47. g FPGA pin LOW with a logic 0 The decimal point on U8 connects to the INIT pin of the XC4003E pin 41 and serves as a programming error indicator The decimal point should be on while the FPGA is in its internal clearing state then it should remain off during configuration If the decimal point comes back on a programming error has occurred The decimal points on U6 and U7 are tied to the Low During Config uration LDC pins of the XC3020A and XC4003E respectively The decimal points are on while the FPGAs wait to be configured The following table shows the I O pin definitions The following figure shows the seven segment display of the FPGA demonstration board Table 3 3 Seven Segment I O Connections Display Segment XC3020A XC4003E XC4003E U6 U7 U8 a 38 39 49 b 39 38 48 c 40 36 47 d 56 35 46 e 49 29 45 f 53 40 50 g 55 44 51 decimal point 30 37 41 Hardware User Guide X4709 Lj LJ Decimal point Figure 3 5 Seven Segment Display LED Indicators D1 D8 D9 D16 Eight LEDs are connected to the I O pins of each FPGA Pins D1 through D8 connect to the XC3020A and D9 through D16 connect to the XC4003E You can turn on an LED by driving its corresponding FPGA pin Low with a logic 0 The following table shows the pin connections for the LED indicators Table 3 4 LED Indicators for XC3020A and XC4003E
48. gether X8928 Figure 1 3 Optional External Power for the MultiLINX Cable When using an external power supply make sure that the ground of the supply the MultiLINX Cable and the circuit board are all tied together An advantage of the external DC power supply is that no power is taken away from the circuit board and the MultiLINX Cable can remain powered up and does not get powered down when the circuit board power is off Parallel Cable Ill The Parallel Cable III is a cable assembly which contains a buffer to protect your PC s parallel port and a set of headers to connect to your target system The cable can be used with a single CPLD or FPGA device or several devices connected in a daisy chain 1 8 Xilinx Development System Cable Hardware The transmission speed of the this cable is determined solely by the speed at which the host PC can transmit data through its parallel port interface Using the Parallel Cable III requires a PC equipped with an AT compatible parallel port interface and a DB25 standard printer connector Flying Leads This cable is shipped with two sets of flying leads one for FPGAs and one for CPLDs The CPLD leads are labelled JTAG and the FPGA leads are labelled FPGA Each flying lead has a 9 pin 6 signals 3 keys header connector on one end This connector fits onto one of the two cable headers These header connectors are keyed to assure proper orientation to the cable assemb
49. he PROG wire is not used This is shown in the following figure In both cases the FPGA must be in the Serial Slave Mode X8323 BEEN cox O DIN 3000 FPGA in Slave Serial Mode XChecker with Header 1 Target System X8324 Figure 1 12 XChecker Connections to XC3000 Device Pin Connection Considerations The following adjustments will make the process of connecting and downloading easier 1 20 Xilinx Development System Cable Hardware e Provide appropriate pins on your printed circuit board for your device type e Place pins on board so that flying leads can reach them The flying leads that are shipped with the cable are six inches long While pins may be a couple inches apart do not have any two pins more than six inches apart e Keep header pins on your board a minimum of 0 10 inches apart Cable Connection Procedure The following steps are required for download cable operation 1 Connect the cable to your host system Make sure to use the appropriate port and adapter if necessary 2 Connect the cable to your target system or demonstration board Always power up the host system before the target system The power for the drivers is derived from the target system 3 Connectthe cable s GND wire to the corresponding signal on the target board Next connect VCC to the 5 V on the target board 4 Connect the appropriate pins for device configuration 5 Power up the target
50. hould be connected to VCC Configuring FPGAs With the Parallel Cable IlI This section details the connections needed to configure FPGAs with the Parallel Cable III The following figures show which pins to connect depending on your chosen FPGA device For descriptions of each pin see Table 3 6and Table 3 7 of the FPGA Design Demonstration Board chapter Note If you are using the Xilinx FPGA Design Demonstration Board see the Mode Switch Settings section of the FPGA Design Demon stration Board chapter for specific configuration information Connect the flying wires to XC4000 FPGAs as shown in the following figure Hardware User Guide 1 13 Hardware User Guide mE FPGA oT vce a GND O AAN O Se O 5 PROG 00 FPGA in Slave Serial Mode Parallel Cable III with FPGA Flying Leads Target System X8326 Figure 1 7 Parallel Cable Ill Connections to XC4000 Device To configure XC3000 FPGAs the PROG wire is not used as shown in the following figure In both cases the FPGA must be in the Serial Slave Mode EE CC WM wa UU C o BEN a 0 DN eee c 000 FPGA in Slave Serial Mode Not Used Wag Parallel Cable III with FPGA Flying Leads Target System Figure 1 8 Parallel Cable Ill Connections to XC3000 Device X8327 Note If you are using the Xilinx FPGA Demonstration Board see the Mode Switch Settings section of the FPGA Design Demonstrati
51. ication of Data This section details the connections needed for downloading configu ration data or the verification of data with the MultiLINX Cable SelectMAP Mode Virtex The following figure shows in detail the Select MAP Mode connec tions for Virtex devices 2 12 Xilinx Development System MutliLINX Cable MultiLINX Connectors RT PwR RD TDO GND TRIG zo Bons D Pi N TEK N TMs PROG CLE1 IN EN CLKl OUT e ROW 21 l lt i 4 i cso cs s csi jas cs2 jas CLK2 IN s CLK2 OUT WS RS RDWR RDY BUSY 2 rnooosmado AAaaAAAAA nnn BUS Y DOUT E Veco Figure 2 5 SelectMAP Mode Virtex Downloading Configuration Data This section details the connections needed for downloading configu ration data with the MultiLINX Cable in JTAG Mode JTAG Mode XC9000 Virtex Spartan XC5200 XC4000 The following figure shows in detail the JTAG Mode connections for XC9000 Virtex Spartan XC5200 and XC4000 devices Hardware User Guide 2 13 Hardware User Guide MultiLINX Connectors cso CS CS1 v cs2 jag CLK2 IN 9 CLK2 OUT ws RS RDWR RDY BUSY only XC4000 and SPARTAN I applicable X8939 Figure 2 6 JTAG Mode XC9000 Virtex Spartan XC5200 XC4000 Downloading Verification of Configuration Da
52. ions for downloading verification of configuration data with Virtex devices 2 16 Xilinx Development System MutliLINX Cable MultiLINX Connec tors 4 cso cs s csi RDY BUSY s BUSY DOU RITE cs GCK x GCK y Figure 2 9 SelectMAP Mode Virtex SelectMAP Mode Virtex with Asynchronous Probing The following figure shows in detail the Select MAP Mode connec tions for Virtex with Asynchronous Probing Hardware User Guide 2 17 Hardware User Guide MultiLINX Connec tors cso cs s e RT 9 PWR csi cND secre mm a DONE D P pz N H E PROG L S RS RDWR RDY BUsY s carrure CAPCLK GCK y Xa935 Figure 2 10 SelectMAP Mode Virtex with Asynchronous Probing JTAG Mode XC9000 Virtex Spartan XC5200 XC4000 The following figure shows in detail the JTAG Mode connections for XC9000 Virtex Spartan XC5200 and XC4000 devices 2 18 Xilinx Development System MutliLINX Cable m MultiLINX Connec tors cso cs csi e e RT 9 PWR 1 RD TDO GND s2 Joe TRIG CLKZ IN CLK2 OUT D4 cerk DONE D P a DIN PROG TEIL RST _ 21 S D RS RDWR D s RDY BUSY e TMS TCK TDI I 5 INT
53. l commands that you enter in a syntactical statement However braces in Courier bold are not literal and square brackets in Courier bold are literal only in the case of bus specifications such as bus 7 0 rpt del net Courier bold also indicates commands that you select from a menu File Open e Italic font denotes the following items Variables in a syntax statement for which you must supply values edif2ngd design name References to other manuals Hardware User Guide 3 1i iii Hardware User Guide See the Development System Reference Guide for more informa tion Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets indicate an optional entry or parameter However in bus specifications such as bus 7 0 they are required edif2ngd option name design name Braces enclose a list of items from which you must choose one or more lowpwr on off pn A vertical bar separates items in a list of choices lowpwr on off A vertical ellipsis indicates repetitive material that has been omitted IOB 41 Name QOUT IOB 2 Name CLKIN A horizontal ellipsis indicates that an item can be repeated one or more times allow block block name loci loc2locn Online Document The following conventions are used for online documents iv Red underlined text indicat
54. lock can come from either the CLK2 IN pin or it can be inter nally generated by the Multi LINX Cable when CLK2 IN is unconnected WS Write Select The WS pin repre sents Write Select control for the Asynchronous Peripheral config uration mode on XC4000 and XC5200 FPGAs Hardware User Guide 2 7 Hardware User Guide Table 2 2 MultiLINX Pin Descriptions Signal Name Function RS RDWR Read Select The RS pin repre sents Read Select control for the Asynchronous Peripheral config uration mode on XC4000 and XC5200 FPGAs Read Write The RDWR pin is used as an active high READ and an active low WRITE control signal to the Virtex FPGA RDY BUSY Busy Pin Busy pin on the Virtex and RDY Busy pin on the XC3000 XC4000 and XC5200 FPGAs MultiLINX Baud Rates Communication between your host system and the MultiLINX Cable is dependent on host system capability The MultiLINX Cable supports several Baud rates With the USB interface the MultiLINX Cable can run at 12 M bits sec With the PC RS 232 interface the MultiLINX Cable can run from a 9600 baud rate to a 57 6 K baud rate MultiLINX Power Requirements The MultiLINX Cable gets its power from the User s circuit board The cable power does not come from the USB port nor the RS 232 port The red PWR and black GND wires from Flying Wire Set 1 are connected to the VCC red wire and Ground black wire lines o
55. ly On the other end of each flying lead are six individual wires with female connectors The female connectors fit onto standard 0 025 inch square male pins As an example the following figure shows the Parallel Cable IIT and its FPGA flying lead wires Hardware User Guide 1 9 Hardware User Guide a j la a a la la la la E a 5 DB25 Plug Connector Parallel Cable III FPGA Flying Lead Connector 8ETNNM 3 A g Connections to Target System X8325 NL AM EN NN PROG Figure 1 4 Parallel Cable Ill and FPGA Flying Leads The following figure shows top and bottom views of the Parallel Cable III including the FPGA and JTAG CPLD headers Xilinx Development System Cable Hardware Parallel Cable III Top View JTAG Header Parallel Cable III CAUTION ono M I DL odel DLC5 Af 2A hicks Power 5V 10mA Typ X J Serial JT 12345 1 Expo SENSITIVE p DIN x ELECTRONIC E Made in U S A DEVICE MS Bottom View X7252 Figure 1 5 Parallel Cable Ill Note The plastic cover of the Parallel Cable III is grey while the XChecker Cable is beige Configuring CPLDs With the Parallel Cable Ill When connecting the CPLD flying leads for configuration make sure to use the JTAG header The following figure shows the
56. n the demonstration board Tiepoint pins jumper the following XChecker Cable signals into your circuit Tiepoint J3 1 connects to TRIG on J1 6 Tiepoint J3 2 connects to CLK1 on J1 16 and Tiepoint J3 3 connects to CLKO on J1 18 See the preceding table for more information on cable connections Serial PROM Socket U1 This serial PROM configures the XC3020A You must use the master serial mode to configure from the serial PROM Relaxation Oscillator Components R1 C5 R2 C6 R1 C5 and R2 C6 are two RC networks that connect to the XC3020A at pins 12 and 14 These RC networks are for use in a relaxation oscil lator such as the circuit is shown in the following figure Hardware User Guide 3 23 Hardware User Guide nameQ nameQL al X6127 Figure 3 9 Relaxation Oscillator Schematic With the components provided R1 R2 100 kilohms and C5 C6 0 1uF the oscillator generates an output frequency of approximately 100 Hz The following figure shows the RC Network waveforms pov rm Ti VT v NR a E NT e ll CN X4715 Figure 3 10 RC Network Waveforms The formula for calculating the RC network is as follows T T1 T2 N RIC5 R2C6 where Xilinx Development System FPGA Design Demonstration Board N approximately 0 35 for TT threshold approximately 0 75 for CMOS threshold when the FPGA allows each capacitor to discharge during the oppo site timing phase Mode Swi
57. n the tasks you wish to perform MultiLINX Cable You can use the MultiLINX Cable to download and readback your Xilinx programmable logic device The MultiLINX cable hardware Hardware User Guide 3 1i 1 1 Hardware User Guide communicates with the host through the Universal Serial Bus USB port or an RS 232 interface The additional flying wires support the various configuration modes available on Xilinx configuration cables Parallel Cable The Parallel Cable III connects to the parallel printer port of a PC This cable can be used to download and readback configuration data via JTAG XChecker Cable The XChecker Cable connects to the serial port of both workstations and PCs This cable can be used for design verification and debug ging in addition to data download and readback Note Always set the configuration mode of the device being config ured to slave serial no matter which cable you use Table 1 1 Cable Support Name Function Platform MultiLINX Cable Download Readback PC Model DLC6 Workstation Parallel Cable III Download PC Model DLC5 Only XChecker Cable Download Readback PC Model DLC4 and Debug Workstation Software Support 1 2 Make sure that you use the appropriate configuration software for your device type e JTAG Programmer Software is used to configure FPGAs and CPLDs and supports both the XChecker and the Parallel Cable III This is a GUI based pr
58. o ez ee S o9 a 5 O 9epooo EF mn JIT t w i 5 z cr e cae e z 0o00 Dm B0O3EE a d SSAA 2 E P o o9 c Tolan apc e 3 9 fo Sa A 2s cm IEE AEN M irte st lt 5 d i WE Co ds ee pru aoe cor f Q IA AN o US tise gs 932 E e 9e E ree HREN roa a O 3 nn J tee Xe T 5 Q lt ba o x z 8 Figure 3 2 FPGA Demonstration Board 5 V Power Connector J9 A regulated 5 volts and ground connected to the FPGA Demonstra tion Board through connector J9 Pin 1 square pad is 5 V and pin 2 Hardware User Guide 3 5 Hardware User Guide is ground The power supply should provide at least 250 mA of current to drive the LED displays Unregulated Power Input J12 This input provides a way to power the FPGA Demonstration Board from an unregulated source such as a 9 V battery or an AC adapter Typically the input should be 7VDC 12VDC at 250 mA You must consider the power dissipation requirements of the U3 voltage regu lator if the voltage input is greater than 9 V The J12 unregulated power input provides two holes to connect the unregulated power source The hole with the square pad marked with a is the positive input The other hole marked with a is circuit ground The positive input is connected through the power on off switch SW2 1 to U3 1 which is the optional 5 V regulator U3 must be installed to use this input 5 V Regulat
59. ogram e Hardware Debugger Software supports the MultiLINX Parallel and XChecker download cables and is used for FPGA configura tion This is a GUI based program with a waveform viewer Xilinx Development System Cable Hardware Note All Hardware Debugger Software versions prior to 2 1i do not support the MultiLINX Cable The Hardware Debugger Soft ware only supports the MultiLINX Cable in the 2 1i release For specific information on using the download cables with the Hard ware Debugger Software see the Hardware Debugger Guide Consult the JTAG Programmer Guide for more information about using this software Cable Limitations Hardware User Guide The MultiLINX Cable is compatible in supporting Readback for all the FPGAs supported by the XChecker Cable In addition to the supporting legacy devices the MultiLINX Cable supports the devices that were not supported by the XChecker Cable Supported devices include those devices in the 4000E 4000XL and SPARTAN families whose bitfile size is more than 256K bits The MultiLINX Cable will also support readback for the new Virtex family Note Debug is not available with the MultiLINX Cable when using the Hardware Debugger Software in the 2 1i Xilinx release version XChecker Hardware Drawbacks Following are the limitations of the XChecker cable e Cannot support readback for devices whose bitfile size is more than 256K bits e Only supports RS 232 e Has less user control
60. on Board chapter for specific configuration information 1 14 Xilinx Development System Cable Hardware XChecker Cable The XChecker hardware consists of a cable assembly with internal logic a test fixture and a set of headers to connect the cable to your target system The cable can be used with a single FPGA or CPLD or several devices connected in a daisy chain Using the XChecker hardware requires either a standard DB 9 or DB 25 RS 232 serial port If you have a different serial port connection you need to provide a DB 9 DB 25 adapter Flying Leads The XChecker Cable is shipped with two sets of flying lead wires The flying lead connectors have a nine position header connector on one end The other end has eight individual wires with female connectors that fit onto standard 0 025 inch square male pins You need appropriate pins on the target system for connecting to the download cable The XChecker Baud Rates section details the necessary pins The following figure shows the XChecker Cable hardware and flying lead connection wires Hardware User Guide 1 15 Hardware User Guide Connection to Host Computer DB25 Adapter DB9 Socket Connector E f GND Qo 0Q 5v XChecker Cable Test Fixture nn lt XILINX Jails Enlarged to show plugs Header 2 Header 1 a Target System _ WIN SI ST MNN o0
61. on board These power supply components can be purchased from Digi Key as shown in the following table Table 4 1 Digi Key Parts List rar Digi Key Part Quantity Descriptions References Number 1 DPDT Switch SW1 EG1909 right angle 4 2 Xilinx Development System CPLD Design Demonstration Board Table 4 1 Digi Key Parts List pu Digi Key Part Quantity Descriptions References Number 1 5V 1A low U2 LM2940CT 5 0 dropout reg 1 22uf 16V C4 P2040 Tantalum cap e Digi Key Corporation is located at 701 Brooks Ave South Thief River Falls MN 56701 0677 Tel 800 344 4539 Fax 218 681 3380 http www digikey com e The PCB is designed to fit into a SERPAC plastic case Model H 65 AC This case can be purchased from SERPAC 619 Commer cial Ave Covina CA 91723 Tel 818 331 0517 Fax 818 331 8584 http www serpac com Demonstration Board Schematics A schematic of this demonstration board is shown in the following figure Hardware User Guide Hardware User Guide 4 4 SOMA liit I 9V BATTERY O u2 LM2940 L C4 y s 22uF Ri Di 2 470 R2 eg D2 A kl e D3 oooocogggeo We SUL G5 our N vo e ces U1 vo E 0 mS Seq g i wo ES E Ses e vec 69 vo GND 7 em amp GND 6
62. on circuitry Foundation Design Tutorial The Xilinx Foundation Software Series contains the CPLD Jcounter tutorial which includes the following five design entry methods e JCT SCH schematic only e JCT_ABL ABEL only e JCT_SABL schematic with ABEL macro e JCT VHD VHDL only e JCT_SVHD schematic with VHDL macro Example I Schematic Design Entry Example 1 shows the readme txt file that is located in the project directories of the Jcounter tutorial designs in the Xilinx Foundation Hardware User Guide 4 5 Hardware User Guide Series software Use these tutorial designs to learn the ISP design flow Schematic With VHDL Macro Design JCT_SVHD is a simple 8 bit Johnson counter DESIGN FLOW Schematic JCT_SVH1 SCH with XVHDL macro JCOUNTER VHD TARGET DEVICE XC9536 VQ44 any speed I O Pins CLK input free running clock Q0 Q7 counter outputs OPERATION The counter is triggered on rising edge of the clock CLK The following is the sequence of states on outputs Q Q7 Q0 00000000 00000001 00000011 00000111 00001111 00011111 00111111 01111111 1110 11110 111100 1111000 11110000 11100000 11000000 10000000 00000000 repeats SIMULATION WAVEFORMS 4 6 Xilinx Development System CPLD Design Demonstration Board JCT_FUNC functional simulation of design before implementation JCT_TIME timing simulation results af
63. only 2 sets of 8 flying wires each MultiLINX Hardware Advantages Following are the advantages of the MultiLINX cable e Fast download readback amp verify using the USB port e More configuration modes are supported e Supports both RS 232 ports and USB ports e Compatible with the currently supported devices for Readback amp Verify e Supports new devices that are not supported by XChecker due to RAM size limitation 1 3 Hardware User Guide 1 4 Works at multiple supply voltages 5 V 3 3 V and 2 5 V Supports JTAG configuration for all Xilinx devices Supports SelectMAP configuration mode for Virtex Previous Cable Versions This section details considerations for using previous download cables with the Hardware Debugger Software You can use Hardware Debugger software with all previous parallel and serial download cables However these previous cables can only be used to download a configuration bitstream they cannot be used for readback If you do use Hardware Debugger with a previous parallel or serial download cable version keep the following points in mind Previous versions of the download cable were made to download XC3000 and XC2000 designs not XC4000 designs The basic limi tation of the previous cables is that they do not have a PROG pin to initiate a re program in XC4000 devices They also do not have an INIT pin to check for Cyclical Redundancy Check CRC errors during configuration No
64. or Option U3 You can install a three terminal 5 V regulator such as the LM2940CT shown in the following figure This regulator powers the demonstra tion board from an unregulated power supply such as a 9 V battery Pin 1 square pad is Vin pin 2 is ground and pin 3 is 5 V out Note Insulate the metal heat sink tab of the regulator from traces and vias on the PCB C S LM2940CT Pint X4692 Figure 3 3 LM2940CT 5 V Regulator 3 6 Xilinx Development System FPGA Design Demonstration Board RESET Pushbutton SW4 Depending on how the Reset signal routing is configured the RESET pushbutton switch can apply an active Low Reset signal to the FPGAs and configuration PROMs Reset is normally pulled High through a 27 kilohm resistor SPARE Pushbutton SW5 The SPARE pushbutton applies an active Low signal to the XC3020A on pin 16 and to the XC4003E on pin 18 You can isolate these pins from the switch by using the trace cut options on the solder side of the board The trace cut options appear as point to point triangles the trace cut option for the XC3020A is under its socket and the trace cut option for the XC4003E is under R3 The SPARE signal is pulled High through a 27 kilohm resistor PROG Pushbutton SW6 The PROG pushbutton applies an active Low signal to the DONE PROGRAM input on the XC3020A FPGA socket at pin 45 and to the PROGRAM input on the XC4003E FPGA socket at pin 55 The PROG signal i
65. positions of the SW1 and SW2 switches for configuring the XC3020A and XC4003E FPGAs in a daisy chain from the XChecker Parallel Cable III Table 3 14 Configuring the XC3020A and XC4003E in a Daisy Chain from the XChecker Parallel Cable Ill Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE OFF SW2 2 MPE OFF SW1 3 SPE OFF SW2 3 SPE OFF Xilinx Development System FPGA Design Demonstration Board Table 3 14 Configuring the XC3020A and XC4003E in a Daisy Chain from the XChecker Parallel Cable Ill Switch Name Position Switch Name Position SW1 4 MO ON SW2 4 MO ON SW1 5 M1 ON SW2 5 M1 ON SW1 6 M2 ON SW2 6 M2 ON SW1 7 MCLK ON SW2 7 RST X SW1 8 DOUT ON SW2 8 INIT ON X indicates don t care The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC3020A and XC4003E FPGAs in a daisy chain from the serial PROM single program Table 3 15 Configuring the XC3020A and XC4003E in a Daisy Chain from the Serial PROM Single Program Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE OFF SW2 2 MPE OFF SW1 3 SPE OFF SW2 3 SPE ON SW1 4 MO ON SW2 4 MO OFF SW1 5 M1 ON SW2 5 M1 OFF SW1 6 M2 ON SW2 6 M2 OFF SW1 7 MCLK ON SW2 7 RST X SW1 8 DOUT ON SW2 8 INIT ON X indicates don t care Hardware User Guide 3 29
66. ram in JTAG mode When you configure a CPLD with the XChecker Cable connections between the cable assembly and the target system use only six of the sixteen leads For connection to JTAG boundary scan systems you need only ensure that the VCC GND TDI TCK TMS and RD TDO pins are connected Note TRST is an optional pin in the JTAG IEEE 1149 1 specification and is not used by XC9500 CPLDs If any of your non Xilinx parts have a TRST pin the pin should be connected to VCC Once installed properly the connectors provide power to the cable and allow download and readback of configuration data The following table describes the CPLD pin connections to the target circuit board Table 1 5 XChecker Cable Pin Connections for CPLDs Name Function Connections VCC Power Supplies VCC 5 To target system VCC V 100 mA typically to the cable GND Ground Supplies ground To target system reference to the cable ground 1 18 Xilinx Development System Cable Hardware Table 1 5 XChecker Cable Pin Connections for CPLDs Name Function Connections RD TDO Read Data Reads back Connect to system data from the target TDO pin system is read at this pin TDI Test Data In this signal is Connect to system TDI used to transmit serial test pin instructions and data TCK Test Clock this clock Connect to system TCK drives the test logic forall pin devices on boundary scan chain TMS T
67. s function for FPGA and CPLD JTAG operations CLKI IN Clock Input Transmits your system clock to the MultiLINX electronic Clock must be between 120 kHz and 10 MHz Connect this pin to target system clock to synchronize the read back trigger with target system clock CLK1 OUT Clock Output Drives target system clock Clock can come from either the CLKLI IN pin or it can be inter nally generated by the Multi LINX Cable when CLKT IN is unconnected D0 D7 Data Bus This pin is used for Virtex SelectMAP Mode An 8 bit data bus supporting the SelectMAP and Express configu ration modes CS0 CS Chip Select CS on the Virtex and CSO on the XC4000 and XC5200 FPGAs The CSO CS pin represents a chip select to the CS1 Chip Select The CS1 pin repre sents Chip Select to the XC4000 and XC5200 FPGAs during configuration Xilinx Development System MutliLINX Cable Table 2 2 MultiLINX Pin Descriptions Signal Name CS2 Function Chip Select The CS2 pin repre sents Chip Select to the XC3000 FPGA while using the Peripheral configuration mode CLK2 IN Clock Input Transmits your system clock to the MultiLINX electronics Clock must be between 120 kHz and 10 MHz Connect this pin to target system clock to synchronize the read back trigger with target system clock CLK2 OUT Clock Output Drives target system clock C
68. s normally pulled High through a 13 5 kilohm resistor Eight General Purpose Input Switches SW3 Eight switches connect to eight general purpose inputs on both the XC3020A and the XC4003E FPGAs These switches provide logic input to the FPGAs An FPGA input pin is set to a logic 1 when a switch is on and a logic 0 when a switch is off See the following figure for a diagram Hardware User Guide 3 7 Hardware User Guide XC3020A XC4003E 4 7K X4744 Figure 3 4 FPGA Demonstration Board General Purpose Switch The FPGA pins connected to this switch are intended for use as inputs However each FPGA pin has a 1 kilohm resistor that isolates it from the switch so it is possible to define the pins as outputs You can also drive the pins from an external source by connecting that signal to the FPGA probe point header The following table lists the FPGA pin connections Table 3 2 Input Switch Pin Connections Switch XC3020A XC4003E SW3 1 11 19 SW3 2 13 20 SW3 3 15 23 SW3 4 17 24 SW3 5 19 25 SW3 6 21 26 SW3 7 23 27 SW3 8 24 28 3 8 Xilinx Development System FPGA Design Demonstration Board Seven Segment Displays U6 U7 U8 Hardware User Guide Three seven segment displays are included with the leftmost display U6 connect to the XC3020A FPGA The rightmost two displays U7 and U8 connect to the XC4003E device Each LED segment is turned on by driving the correspondin
69. system A Caution Cable protection ensures that the host system port cannot be damaged through normal cable operation For increased safety please check that the power to the host computer is on before the target system is powered up 6 Start the appropriate Xilinx software package and configure your device The JTAG Programmer Software and Hardware Debugger Software will automatically identify the download cables when correctly connected If you need to set up the cable manually see the following section Note The download cables will not operate if the target system s power is turned off before or during software operations Make certain that this power connection is on and stable Your system s power should be on during ISP operations When powering down turn off the target demonstration board first and then the host machine Hardware User Guide 1 21 Hardware User Guide Setting Up The Cable If you are using the Hardware Debugger Software and a PC as a host system manually select your cable as follows Output gt Cable Setup Select your cable type then click OK If you are using the XChecker cable you may also select a BAUD rate See Table 1 4 If you are using the JTAG Programmer software select the cable manually as follows Output gt Cable Auto Connect Select your cable type then click OK Download Cable Schematic The following figure is an internal schematic of the Parallel Cable III You m
70. ta This section details the connections needed for downloading verifi cation of configuration data with the MultiLINX Cable in Slave Serial Mode Slave Serial Mode XC3000 The following figure shows in detail the Slave Serial Mode connec tions for the XC3000 device 2 14 Xilinx Development System MutliLINX Cable MultiLINX Connectors n U PWR cso cS s s bo RT csi 5 GND gle CS2 jas CLK2 IN D3 CLK2 OUT D4 RS RDWR D6 RDY BUSY hl only used for probing User I O TRIGG M1 RDATA MO RTRIG M2 X8938 Figure 2 7 Slave Serial Mode XC3000 Slave Serial Mode Spartan XC5200 XC4000 The following figure shows in detail the Slave Serial Mode connec tions for Spartan XC5200 and XC4000 devices Hardware User Guide 2 15 Hardware User Guide a3 MultiLINX Connectors cso cs ss po RT vs pun csi s pi RD TDO GND 2 TRIG ecLk m s DONE D Pe TCK DINC SN TMS PRoG INI T RST cs2 CLK2 IN D3 CLK2 QUT s s p4 ws e el RS RDWR D6 RDY BUSY hl only used for probinN B vec vcc 8937 Figure 2 8 Slave Serial Mode Spartan XC5200 XC4000 SelectMAP Mode Virtex The following figure shows in detail the Select MAP Mode connec t
71. table Table 2 3 MultiLINX Device Configuration Modes Configuration Device Mode Virtex Spartan XC9500 XC5200 xC4000 XC3000 SelectMAP X Slave Serial X X X X JTAG X X X X X Downloading Configuration Data This section details the connections needed to download configura tion data with the MultiLINX Cable Slave Serial Mode XC3000 The following figure shows in detail the Slave Serial Mode connec tions to a XC3000 device for Downloading Configuration Data Xilinx Development System MutliLINX Cable MultiLINX Connectors cso cs s 5 D0 CS1 n cs2 CLK2 IN CLK2 OUT no RS RDWR 2 RDY BUSY Figure 2 3 Slave Serial Mode XC3000 Slave Serial Mode Virtex Spartan XC5200 XC4000 The following figure shows in detail the Slave Serial Mode connec tions for Virtex Spartan XC5200 and XC4000 devices Hardware User Guide 2 11 Hardware User Guide Mult iLINX Connectors 43 cso cse no RT P P CS1 n D1 RD TDO P GND TRIG CS2 ja o CLK2 IN s L CLK2 OUT D4 Tp1 DONE m D BE P AS WS D5 TEK n n DIN ER D RS RDWR D6 Ts n7 cukl dn e INIT D RDY BUSY cLK1 our 2 IgsT N 21 X8941 Figure 2 4 Slave Serial Mode Virtex Spartan XC5200 XC4000 Downloading Configuration Data or Verif
72. tch Settings This section describes the SW1 and SW2 switch settings for config uring the XC3020A and XC4003E devices e From the XChecker Parallel Cable III e From the serial PROM single program e From the serial PROM multiple program e Ina daisy chain The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC3020A FPGA from the XChecker or Parallel Cable III Table 3 8 Configuring the XC3020A from the XChecker Parallel Cable Ill Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE OFF SW2 2 MPE X SW1 3 SPE OFF SW2 3 SPE X SW1 4 MO ON SW2 4 MO X SW1 5 M1 ON SW2 5 M1 X SW1 6 M2 ON SW2 6 M2 X SW1 7 MCLK OFF SW2 7 RST SW1 8 DOUT OFF SW2 8 INIT OFF X indicates don t care Hardware User Guide 3 25 Hardware User Guide The following table lists the names and positions of the SW1 and SW2 switches for configuring the XC4003E FPGA from the XChecker Parallel Cable III Table 3 9 Configuring the XC4003E from the XChecker Parallel Cable Ill Switch Name Position Switch Name Position SW1 1 INP X SW2 1 PWR X SW1 2 MPE X SW2 2 MPE OFF SW1 3 SPE X SW2 3 SPE OFF SW1 4 MO X SW2 4 MO ON SW1 5 M1 X SW2 5 M1 ON SW1 6 M2 X SW2 6 M2 ON SW1 7 MCLK OFF SW2 7 RST X SW1 8 DOUT OFF SW2 8 INIT OFF X indicates don t care When you configure both the XC3020A and XC4003
73. te To use a parallel download cable prior to the Parallel Cable III to download designs to the XC4000 family devices you must manually toggle the PROG pin to low PROG is active when it is low The Parallel Cable III has a wire for the PROG pin Previous download cables do not support readback or verifica tion For the PC the download cable is a parallel cable requiring connection to the parallel port The XChecker cable is serial There are only two situations when you might prefer using previous download cables instead of the XChecker Cable or MultiLINX Cable You have circuit boards with header connectors keyed to match the previous cable headers However you could use the XChecker Cable with its flying lead connectors Simply match the labeled flying leads to the equivalent signals on your system You have circuit boards where power consumption is a critical factor The XChecker Cable requires about 100 mA at 5 V and the MultiLINX Cable requires about 300mA at 5 V 500mA at 3 3 V Xilinx Development System Cable Hardware and 750mA at 2 5 V the Parallel Cable used with PCs draws less power from the target LCA board In such cases you may use the Hardware Debugger software to download the bitstream Cable Baud Rates The supported Baud Rates for the MultiLINX Parallel and XChecker Cables are shown in the following table Table 1 2 Cable Baud Rates Cable PC Workstation MultiLINX Cable 1M 1
74. ter implementation TUTORIAL This project is used as one of the example designs described in the CPLD Design Flow tutorial in the Foundation Series On Line Help System DEMO BOARD The JEDEC programming file produced by this project can be downloaded into the CPLD Demo Board HW CPLD DEMOBD Example 2 VHDL Design Entry Example 2 shows the same design done in VHDL while using Xilinx Foundation software library IEEE I use IE i E std logic 1164 all library metamor use metamor attributes all entity jcounter is port clk in STD LOGIC Dout buffer STD LOGIC VECTOR 7 downto 0 Hardware User Guide 4 7 Hardware User Guide Can use attributes to assign pin locations in Foundation VHDL attribute pinnum of Dout signal is p13 14 16 18 19 20 21 22 end jcounter architecture jcounter arch of jcounter is begin if CLK event and CLK 1 then CLK rising edge Dout 7 downto 1 lt Dout 6 downto 0 shift Dout 7 downto 1 lt Dout 6 downto 0 shift Dout 0 lt not Dout 7 Last bit inverted back into first bit end if end process end jcounter arch 4 8 Xilinx Development System Glossary Baud Rates Baud rates refer to your host system communication capabilities Configuration Modes CPLD Daisy Chain Download Configuration Modes are the modes available on th
75. the configura tion switches apply power to the FPGA Demonstration Board This step configures the FPGA when the DONE pin goes High it indicates that the design logic is active Start your configuration software For information on starting the Hardware Debugger software see the following section Starting Hardware Debugger Hardware User Guide The following section includes a checklist for opening the Hardware Debugger software For further information consult the Hardware Debugger Guide 1 2 Open your Alliance or Foundation software From within Xilinx Design Manager version M1 0 or later select Hardware Debugger from the tools menu You can also start the Hardware Debugger from the operating system prompt by entering the following command hwdebugr design name When you start the Hardware Debugger the port where the cable is plugged in is located and the baud rate is set to the maximum allowed by the platform Hardware User Guide 3 A message window indicates that the FPGA design is loading When loading is complete the Hardware Debugger indicates that the DONE pin went High At this point the loaded bit file func tions as designed Tutorials Tutorials are available from the Xilinx Web site and on the AppLINX CD The Web site location is http support xilinx com support techsup tutorials index htm Please contact your local Sales Repre sentative for a copy of the AppLINX CD Calculator
76. these resources using the provided URLs Resource Description URL Tutorials Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answers Current listing of solution records for the Xilinx software tools Database Search this database using the search function at http support xilinx com support searchtd htm Application Descriptions of device specific design techniques and approaches Notes http support xilinx com apps appsweb htm Data Book Pages from The Programmable Logic Data Book which contain device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http support xilinx com partinfo databook htm Xcell Journals Quarterly journals for Xilinx programmable logic users http support xilinx com xcell xcell htm Technical Tips Latest news design tips and patch information for the Xilinx design environment http support xilinx com support techsup journals index htm ii Xilinx Development System Conventions This manual uses the following conventions An example illustrates each convention Typographical The following conventions are used for all documents e Courier font indicates messages prompts and program files that the system displays speed grade 100 e Courier bold indicates litera
77. to set up the XC4000 and XC3000 FPGAs as shown in the following table Table 3 1 DIP Switch Configuration XC3000 SW1 XC4000 SW2 Switch INP 1 PWR MPE MPE multiple configurations 2 SPE SPE single configuration 3 MO MO 4 M1 M1 5 M2 M2 6 MCLK RST 7 DOUT INIT 8 Hardware User Guide 16 I O lines that connect the two FPGAs An external relaxation oscillator circuit available to the user for the XC3000 The XC4000 OSC4 library symbol which uses pin 19 of the XC4003E to drive the XC3000 TCLKIN on pin 11 of the XC3020A The XC4000 OSC4 uses pin 13 to drive the XC3000 alternate clock buffer BCLKIN on pin 43 Eight general purpose input switches to provide logic inputs to the FPGAs Program Reset and Spare Active Low push button switches which are common to both FPGAs An XC3000A display for the XC3000 device The display uses eight LED bars in one row and one 7 segment LED as shown in the following figure An XC4000A display for the XC4000 device The display uses eight LED bars in one row and two 7 segment LEDs as shown in the following figure Space for an optional 5 V regulator for battery operation Space for an optional crystal oscillator Headers for FPGA probe points 3 3 Hardware User Guide e A prototype area on the PC board U6 U7 U8 XC3000 XC4000 7 Segment Display 7V VV VV IV TV VV VIF
78. tutorial designs for Mentor and Cadence are available on the Xilinx CAE Interface CD ROM at the following locations e Mentor Tutorial on a Workstation CD DRIVE or server mentor tutorial calc 4ke calc bit e Cadence Tutorial on a Workstation CD DRIVE or server cadence tutorial calc_4ke xilinx run calc bit Xilinx Development System Chapter 4 CPLD Design Demonstration Board The CPLD Design Demonstration Board Part Number HW CPLD DEMOBD is a tool used for demonstrating the In System Program ming ISP capabilities of the XC9500 CPLD family Using this board you can easily program erase verify and functionally test any XC9500 device This chapter contains the following sections e Demonstration Board Overview e Demonstration Board Schematics e Foundation Design Tutorial Demonstration Board Overview The following section details the features and support for the CPLD Demonstration Board The demonstration board uses a surface mounted 555 timer with resistor and capacitor values set for 14 Hz operation This oscillator clocks a simple test design a Johnson counter implemented in the XC9536 this counter drives LEDs used to verify operation Software and Download Cable Support The CPLD Demonstration Board is shipped with two short ribbon style cables for device configuration The board also supports the Parallel Cable III and the XChecker serial cables Make sure to connect the cabl
79. u must compile the input files with your design implementation software Xilinx Development System FPGA Design Demonstration Board These example designs incorporate the ability of the XC4003E to build ROM out of function generators The ROM macros store a sequence of patterns that are displayed on the 7 segment displays and the LED bar graphs of the FPGA Demonstration board Please read the text files that accompany these designs Design sche matics are available by calling the Xilinx Technical Support Hotline You can also access schematics through the Xilinx web site located at http www xilinx com Design Downloading Checklist Hardware User Guide You must follow the recommended design flow to assure proper operation Make backups before making changes to any demonstra tion design files 1 Produce a routed design design name using a design entry tool and the appropriate place and route tool If you want a global Reset signal in your XC4000 designs you must include the Startup symbol in your design and select the location of the RESET pin Attach pin 56 to an inverter and the GSR pin on the Startup symbol GSR is active High so you must include an inverter between the pad and the Startup symbol 2 Generate a bitstream for the design design name bit with the appropriate configuration options using the BitGen program 3 Optionally create a PROM File 4 Generate a PROM file design name mcs design name tek or
80. ust use the recommended lengths for parallel cables Xilinx cables are typically six feet approximately two meters in length between the connector and active circuitry Keep the wires between the headers and target system as short as possible Xilinx Development System Cable Hardware JTAG Header 1N5817 1N5817 VCC SENSE s 1K OF L 14 14 5 1K 7 7 7 Y 100 100pF Uis zS AT 100 100pF 11 Ut 613 T 100 100pF U1 74HC125 U2 9 U2 74HC125 1004 DB25 MALE Serial JT 05000 and above FPGA Header CONNECTOR for EPP parallel ports X7557 Figure 1 13 Parallel Cable Ill Schematic Hardware User Guide 1 23 Hardware User Guide 1 24 Xilinx Development System Chapter 2 MutliLINX Cable The MultiLINX Cable is the next generation configuration and readback tool for FPGA s and CPLD s During the integration of Xilinx programmable logic into your design the MultiLINX Cable can be used to troubleshoot your configuration setup and diagnose configuration problems associated with Xilinx programmable logic The MultiLINX Cable uses either a serial or USB port on a host computer Maximum throughput is available by using the USB inter face This chapter contains the following sections e

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