March 21, 2006 Rev 060310 User's Manual The
Contents
1. 2 0 RS232 TX at RL 3kQ to DGND RS232 RX DGND RS232 TX at RL 3kQ to DGND RS232 RX DVCC TTL IN 3 0 0 7 x V DVCC ViL 0 3 x V DVCC 0 1 ei u pie other 0 7 x inputs DVCC 0 3 x DVCC All other DVCC 100 EM ie 2 Table 8 D C Operating pomeo Copyright 2004 2006 Pleora Technologies Inc Page 24 Rev 060310 Pleora Technologies 6 4 A C Operating Characteristics 6 4 1 Camera Interface Table 9 shows the A C sub clock delays of the Camera Link control signals in the PT1000 VB RXXCLK refers to IN CLKO RXXOUT 27 0 refers to all the inputs of the camera interface DATA 23 0 CL FVAL CL LVAL CL DVAL and CL SPARE Figure 6 is a timing diagram for the sub clock delays Parameter Symbol Min max Units notes ngmeveiwan i TED fe _ 160 m t o Me RXXCLK clock period By design By design n S Asynchronous E RXXOUT setup time Ies 2 RXXOUT hold time 2 CL CC pulse width 30 Table 9 A C Sub Clock Delays on the Camera Interface gt atop tcp gt RXXCLK wora BO HERE tps r tpu CL CC 4 1 M 1 1 m gt Figure 6 Timing Diagram of A C Sub Clock Delays on the Camera Interface Copyright 2004 2006 Pleora Technologies Inc2. 7 2 3 Chardeteristies e e 9 eT 08 91111122 9 3 1 Powerand IO 9 3 2 Camera COMMS CL 10 4 0 Sianal ANN TR 13 4 1 COOL ISOC ENTRE 13 4 1 1 GPIO Programming Signals 15 4 2 O MSE MEME UE 16 4 2 1 Comer DUIS 16 4 2 2 SEC EOS 16 4 2 3 Ia BUS TT 17 4 2 4 Serial Inte 18 4 3 Passing Signals between the Hirose and Samtec Connectors 18 5 0 Design Recommendations ccce eee e ee eere eene ee eere 19 5 1 Power Supply ConslIderallOfis coiere ipto ntt heo a o euo yani ud ek ae 19 5 2 In System JTAG sss 21 5 3 FPGA SEL e 22 5 4 Om eee 22 5 5 SC TP NS a peers pce ak 22 6 0 Operating 23 6 1 Absolute Maximum 23 6 2 Recommended Operating Conditions senes 23 6 3 Operating Character SHGs NE 24 GOA AC Operaimp Car AC STIS CS 25 6 4 1
3. 29 Table 14 A C Operating Characteristics of the USRT Interface 30 Copyright 2004 2006 Pleora Technologies Inc Page 4 Rev 060310 Pleora Technologies 1 0 Introduction 1 1 The Scope of this User s Manual This User s Manual describes how to access and use the features in Pleora s iPORT PT1000 VB In Camera IP Engine 1 2 Related Documents The PT1000 VB IP Engine is one member of Pleora s growing family of iPORT IP Engines For information about other available engine models visit www pleora com All the engines share one set of core features described in a document entitled User s Manual Shared Features of iPORT IP Engines iPORT PT1000 VB IP Engine is an element of the iPORT Connectivity Solution As such it is shipped with two PC applications the iPORT IP Device Driver and the iPORT Software Development Kit SDK available in C or Visual Basic These software applications have their own documentation The iPORT Connectivity Solution also includes the High Memory Manager which is described in the iPORT IP Device Drivers manual As an option the solution can also include 1PORT Hydra PC Communications Software described in the SDK C manual For PT1000 VB customers seeking to achieve EMI certification for their products Pleora has prepared a separate document entitled iPORT PT1000 VB In Camera IP Engi
4. Pleora Technologies 3 0 Connectors As shown in Figure 1 the iPORT PT1000 VB CL board has three connectors e One RJ45 Ethernet connector shown as J1 e One power and IO connector the 12 pin connector shown as J2 and e One camera connector the 80 pin connector shown as J3 The Ethernet connector is a standard RJ 45 plug The part number is XMultiple XRJV S 01 8 8 More information about this connector can be obtained from www xmultiple com The next sections of this document provide further details about the other two connectors J1 Ethernet TOP VIEW BOTTOM VIEW 1 19 Figure 1 Connector Locations 3 1 Power and IO Connector The power and IO connector shown as J2 in Figure 1 15 a Hirose 10 10 12 part Note that this connector 15 not provided with the engine only the mount for the connector 15 provided More information about the connector can be obtained at www hiroseusa com The mating part number 15 Hirose HRIOA 10P 12S Table 2 lists the 12 pins in the connector and describes the function of each Copyright 2004 2006 Pleora Technologies Inc Page 9 Rev 060310 Pleora Technologies Pin Signal Name R R e wm TT wm wrtema G3vaway TT Table 2 Power and lO Connector Pinout TTL OUT LVTTL LVTTL output 2 3 3 V output 3 2 Camera Connector The camera connector shown as J3 in Figure 1 is an 8
5. Updated connector location diagram Added footnotes for the camera connector pinout in regards to the UART and In System JTAG Updated the GPIO control block diagram 2 1 2 November 2005 Updated mechanical drawings Modified the tolerances Added some connector information and links Modified footnotes for the camera connector pinout table Added new sections on serial interfaces passing signals between connectors design recommendations and operating characteristics Modified the structure of the document 060206 February 2006 Modified text to reflect Software V2 2 0 Added Characteristics and Features table Reordered sections Updated formatting to comply with new Pleora template 060310 March 2006 Updated Table 14 Copyright 2004 2006 Pleora Technologies Inc Page 34 Rev 060310
6. Lb Technologies User s Manual The 1iPORT PT1000 VB In Camera IP Engine March 21 2006 Rev 060310 Pleora Technologies Inc 359 Terry Fox Drive Suite 230 Kanata Ontario Canada KAK 2 7 Tel 613 270 0625 www pleora com Pleora Technologies These products are not intended for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Pleora Technologies Inc Pleora customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Pleora for any damages resulting from such improper use or sale 2005 2006 Pleora Technologies Inc All information provided in this manual is believed to be accurate and reliable No responsibility 1s assumed by Pleora for its use Pleora reserves the right to make changes to this information without notice Redistribution of this manual in whole or in part by any means is prohibited without obtaining prior permission from Pleora Copyright 2004 2006 Pleora Technologies Inc Page 2 Rev 060310 Pleora Technologies Table of Contents LO OE 5 1 1 The Scope of this User s Manual assesses 5 1 2 SLE DOC iC IE Tm 5 2 0 Overview of the iPORT 1000 6 2 1 ETO NAS 6 22 MOISE a
7. IsPortAvailable e CyDevice ConfigPort e CyDevice GetPortConfig e CyDevice GetPortConfigFormat e CyDevice SendCommand CyDevice ReceiveAnswer e CyDevice ResetAnswerQueue e CyDevice GetAnswerQueueSize 6 4 4 1 UART Bulk Interface This UART is specified in the same manner as the Serial Port See Section 6 4 3 of this manual for more information The main difference 1s that the delay between packets 1s significantly smaller and more predictable 6 4 4 2 USRT Bulk Interface Table 14 details the A C operating characteristics of the USRT and Figure 12 shows the timing of the related RXD TXD and SCK signals ns Programmable to 16 667 8 333 4 167 2 083 and 1 041 MHz By design By design Parameter Symbol Min Typ Max SCK to TXD 5 5 delay RXD hold turx time 5 By design RXD setup tsrx time Table 14 A C Operating Characteristics of the USRT Interface Copyright 2004 2006 Pleora Technologies Inc Page 30 Rev 060310 Pleora Technologies SCK TXD START TXDO TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 STOP RXD START RXDO RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 STOP of ae e 1 scx yp SCK TXD TXD2 TXD3 1 TXD4 tsrx lt RXD RXD2 RXD3 RXD4 Figure 12 USRT Timing Diagrams Copyright 2004 2006 Pleora Technologies Inc Page 31 Rev 060
8. Page 25 Rev 060310 Pleora Technologies Table 10 shows the A C operating characteristics of the Camera Link control signals Figure 7 to Figure 9 are the related timing diagrams Parameter Symbol Min Max Units Notes FVAL valid to LVAL valid ftw fr CVA we LAL wales De e VAL wedge ote edie I e emm E s e _ wm nn i amune e e e 8 _ vemm ux 48 awawan e VAL wpe soe KO je _ 17117217 a i je i _ 15 11 eal wu e eu i Sl Cl COIE aawo ee nmo um KE AVAL wd WAL s e ue LmALmiAasmawda vam Aa e Feo ue 8 7 em p _ CRA bd owt 16 e r 1 je _ 15 e f _ Table 10 A C Operating Characteristics for Camera Link Signals Notes 1 The valid state of FVAL and LVAL 15 high when they are set as level high sensitive or rising edge sensitive Their valid state 1s low when they are set as level low sensitive or falling edge sensitive Copyright 2004 2006 Pleora Technologies Inc Page 26 Rev 060310 Pleora Technologies 2 If LVAL 1s va
9. amera 25 6 4 2 021221 2116 cies EE E E E 28 6 4 3 514 UART 28 6 4 4 Bulk Inierrace DS T ang WAR D esaleta Eo ne 30 6441 UART Bulk armen era ae Ee aM DIS dI VEDI Erde 30 644442 USRT Bulk Interface erret seen kk ose 30 7 0 Mechanical Dimensions e eee eee eee e eee ee eene eee ette ette eeoao 32 SU Additonal SUN Occ cacao 34 8 1 ag aero 34 Copyright 2004 2006 Pleora Technologies Inc Page 3 Rev 060310 Pleora Technologies List of Figures Figure E Connector o easier 9 Figure 2 PT1000 VB CL GPIO Control Block sss 14 Figure 3 Simplified Schematic of the PT1000 VB CL Power Supply Circuitry 19 Figure 4 In system JT AO Arc asane as 21 REPOS BILE DUO 22 Figure 6 Timing Diagram of A C Sub Clock Delays on the Camera Interface 25 Figure 7 Camera Interface Timing When FVAL and LVAL are Level Sensitive 21 Figure 8 Camera Interface Timing with FVAL and LVAL Edge Sensitive 27 Figure 9 Camera Interface Timing with FVAL Edge Sensitive and LVAL Level 28 Figure 10 GPIO Timing Dlagram sass 28 URL Timing DI OH aom s
10. Gen2 Q 10 Q 17 16 11 10 9 8 7 3 PG OUT 3 0 Q 17 16 11 10 9 8 7 3 Q 15 Q 17 16 11 10 9 8 7 3 Q 17 PG OUT 3 0 RSL OUT GPIO_CNT 31 0 lt time LI 7 0 mask v trigger igger tri 8 1 input Rescaler pax Mult 16 bit 8 1 input Delayer 5 1 reference TTL_OUTIO _ TTL_OUT 1 x TTL OUTI gt LUT Q 3 al CL_CC1 2 CL CC2 2 CL_CC3 CL CC4 GPIO FVAL a GPIO_LVAL 2 GPIO_TRIG ES 8 Pulser PG OUT O Pulse Gen1 PG_OUT 1 PG_OUT 2 Pulse_Gen3 PG_OUT 3 RSL_OUT DEL_OUT interrupt Interrupt FIFO 8 1 clear General Q 16 up Purpose Q 17 16 11 10 9 8 7 3 Q 17 16 11 10 9 8 7 3 gt down Counter GPIO IRQ TIME 31 0 MASK 7 0 GP CNT 31 0 GP CNT EQ GP CNT GT GP cNT 3 0 Timestamp Trigger TS CNT 31 0 Generator 8 1 clear Timestamp NA Counter gt TS TRIG 3 0 TS CNT 31 0 Interrupt and Frame Timestamp Source Selection GP CNT 31 0 TS CNT 31 0 Figure 2 iPORT PT1000 VB CL GPIO Control Block Copyright 2004 2006 Pleora Technologies Inc Rev 060310 GPIO CNT 31 0 Page 14 Pleora Technologies 4 1 1 GPIO Programming Signals Table 4 and Table 5 list the GPIO programming signals that are specific to the iPORT PT1000 VB CL The GPIO lab
11. To facilitate programming of the EPLD in the future pins 67 and 77 of the 80 pin Samtec connector are connected together If you want to use the in system JTAG as well then these pins should be coupled to the camera s TAP controller This will allow field updates of any camera firmware over the GigE link If pins 67 and 77 are not coupled using either of these methods it will not be possible to update the EPLD or the camera in the field via the GigE link PT1000 VB CL Altera FPGA Xilinx EPLD EP1C12F256C8 XC9572XL J3 pin 77 TDO gt 9 BP N C J3 pin78 Altera Xilinx TAP TAP Controller Controller TAP TDO gp TDI J3 pin67 In System 2 y DUT TAP BP TMS J3 pin79 Controller TDI BP TCK J3 pin80 1 In Sytem Altera and Xilinx JTAG share TMS and TCK 2 It is highly recommended to couple pin 67 to pin 77 via an external TAP controller or if the in system JTAG controller is not required via a zero Ohm resistor If this is not done certain upgrades cannot be performed in the field Figure 4 In System JTAG Architecture Copyright 2004 2006 Pleora Technologies Inc Page 21 Rev 060310 Pleora Technologies 5 3 FPGA_ SEL Considerations Figure 5 shows the FPGA SEL options The FPGA SEL pin J3 pin 68 is an input to the PT1000 VB CL that selects main FPGA SEL high or a back up FPGA SEL low firmware load Typically t
12. built hardware is used instead of an embedded processor This allows the engine to acquire packetize and drive camera data onto GigE links or LANs with ultra efficient clock cycle accuracy The PT1000 VB processes image data continuously at GigE s full 1 Gb s line rate while delivering low predictable latencies A unique IP transfer protocol guarantees the delivery of every packet ensuring best in class performance The high throughput of the board supports real time operation with most image sensors including performance oriented CCD sensors with fast frame rates At all throughput rates the PT1000 VB consumes less than 2 25 W of power making it an easy fit for small body cameras with strict power budgets The PT1000 VB also handles control signals from the PC and other system elements These signals are routed through a PLC programmable logic controller that allows users to precisely measure and control the operation of conveyors encoders cameras and other components either independently from or in conjunction with the host PC on the network As one element of Pleora s end to end 1 Connectivity Solution the iPORT PT1000 VB is shipped with two powerful PC applications The IP Device Driver streams data to PC memory using minimal CPU capacity Users can choose from two versions the iPORT High Performance IP Device Driver or the iPORT Universal IP Filter Driver The iPORT SDK gives users the building bloc
13. 0 pin Samtec AW 40 03 G D 230 075 A part The mating part number is the 80 pin Samtec CLE 140 01 G DV A Table 3 lists the 80 pins in the connector and describes the function of each AII signal levels are LVCMOS or LVTTL Type _ s rou mn onrar canere uoaaronn s orms caneuon _ s rou The RS232 interface is not currently implemented Copyright 2004 2006 Pleora Technologies Inc Page 10 Rev 060310 Pleora Technologies Pin Signal Name Description GND PWR Digital ground 18 GND PWR Digital ground 19 ORT B4 N DATA12 Camera Link Data Port B4 2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 N N N N N N N N N DATA13 Camera Link Data Port B5 DATA14 Camera Link Data Port B6 DATA15 Camera Link Data Port B7 DATA16 Camera Link Data Port CO DATA17 Camera Link Data Port DATA18 Camera Link Data Port C2 DATA19 Camera Link Data Port DATA20 Camera Link Data Port C4 DATA21 Camera Link Data Port C5 ORT_C6 N DATA22 Camera Link Data Port C6 7 N DATA23 Camera Link Data Port C7 VCC PWR Digital supply 3 3 VCC PWR Digital supply 3 3 ORT DO N CL SPARE Camera Link Spare ORT D1 N CL LVAL Camera Link Line Valid ORT D2 N CL FVAL Camera Link Frame Valid PORT D3 N CL DVAL Camera Link Data Valid PORT 4 OUT CL CC1 Camera Link Camera Control 1 connected to LUT output Q4 PORT D5 O CL_CC2 Camera L
14. 04 2006 Pleora Technologies Inc Page 28 Rev 060310 Don t Care Window Size N x M Pleora Technologies Baud Factor BF Baud Rate BR bps Notes LENNENU NNNL NN mme wm Table 12 UART Baud Rates B ALIE E LS Baud Rate BR 8170 8 170 2 083 333 Table 13 A C Operating Characteristics of the UART Interfaces tUART TXD RXD DO Di D2 D3 05 X D6 07 jParity STOP Figure 11 UART Timing Diagram Table 13 shows the A C operating characteristics of the UART interfaces and Figure 11 is the related timing diagram The UART only sends one byte at a time The time between bytes 1s not deterministic and depends on the PC host s available resources This will slow down the effective baud rate such that the time to send 1 KB of data 1s the same for 9 600 baud and 115 200 baud If a serial interface must move large amounts of data and or transfer time is issue it 1s recommended that the bulk interface described in Section 6 4 4 be used Copyright 2004 2006 Pleora Technologies Inc Page 29 Rev 060310 Pleora Technologies 6 4 4 Bulk Interface USRT and UART The bulk interface s can be configured as either USRT s or UART s These interfaces are intended for bulk data transfer Please refer to the Reference Manual 1 C SDK for details on how to configure and use these ports In particular review the following functions e CyDevice
15. 1 LVTTL Cam 1 LVTTL Cam Serial Ports UART 3 68 1 x RS232 GPIO Note 5 Two Wire Bus Interface 2 Optional Note 4 USRT 1 LVTTL Cam 1 LVTTL Cam Note 5 Min 4 5 V PT1000 VB Supply Voltage Typ 5V Max 16 V Power Consumption 2 2 W measured at 10 Max 2 4 W Min 0 C Operating Temperature Max 70 C Min 40 C Storage Temperature 125 Notes x xx Available since firmware version x xx In System JTAG NA Not applicable All features supported by iPORT S W 2 2 0 1 RGB supported as single tap 24 bits 2 Compatible with 12 4 NRE or other charges may apply Contact Pleora 5 Contact Pleora for availability DHCP Yes 4 06 1 Std Up to 4 Opt 1 2 or 3 4 Opt Note 4 Video Input LVTTL LVCMOS Yes SPARE used as FID Progressive Scan Yes Number of Data Channels Video Sources per Data Channel Interlaced Area Scan Yes Line Scan Yes Color RGB Bayer Monochrome Yes Grayscale PT1000 VB Data Output Formats Bayer RGB 8 10 12 14 16 24 Pixel Depth bits 32 Opt Min 1 MHz Pixel Clock Max 80 MHz 2 Std Note 1 Taps per Data Channel 4 d Min 4 Default 640 Max 16 380 Min 1 Image Height pixels Default 480 Max 16 383 Image Width pixels must be multiple of 4 Table 1 IPORT PT1000 VB CL Characteristics and Features Copyright 2004 2006 Pleora Technologies Inc Page 8 Rev 060310
16. 310 Pleora Technologies 7 0 Mechanical Dimensions Figure 13 to Figure 16 are mechanical drawings of the PT1000 VB board not to scale The measurements are in inches unless otherwise specified and have the following tolerances depending on the number of significant digits provided X 0 1 0 01 XXX 0 005 The board is 0 0625 inches thick The maximum secondary component height is 0 08 inches unless otherwise specified Please note that the stacker height of the Samtec camera connector referenced as HEADER 2x40 in Figure 16 15 0 230 inches high and its post height 15 0 075 inches for an overall pin height of 0 305 inches Refer to the Samtec web site www samtec com for further details Figure 13 lsometric View Copyright 2004 2006 Pleora Technologies Inc Page 32 Rev 060310 nmi Pleora Technologies 3 PEN Figure 14 Top and Side View I 130 634 305 Overall pin height stacker height 0 230 in Figure 15 Front View Figure 16 Bottom View Copyright 2004 2006 Pleora Technologies Inc Page 33 Rev 060310 Pleora Technologies 8 0 Additional Support Additional support can be obtained by contacting Applications Support at Pleora Technologies Inc at 613 270 0625 or via email at support pleora com 8 1 Revision History meon Date Description 2 1 1 June 2005 Removed custom model Added preliminary mechanical drawings
17. 6 4 4 of this manual In the future users will be able to configure the Bulk Interface 0 port as a USRT UART or two wire bus interface At present only the USRT interface is supported The RS232 interface 15 not currently implemented contact Pleora if required In the future this interface will be able to bridge with one of the other serial interfaces This will allow communication between the Hirose power and IO connector and the Samtec camera connector 4 3 Passing Signals between the Hirose and Samtec Connectors Upon request Pleora can customize the PT1000 VB CL to pass signals between the Hirose power and IO connector and Samtec camera connector Through hardware modifications one or both of the following configurations are offered J3 pin 64 AGND to J2 pin 3 TTL_IN 3 disconnected J3 pin 66 ANALOG VID to J2 pin 4 TTL OUTI2 disconnected Since these are direct short circuits between two pins any type of signal level can be passed between them As shown above this modification can sacrifice one or both of the TTL IN 3 and TTL OUT 2 signals Copyright 2004 2006 Pleora Technologies Inc Page 18 Rev 060310 Pleora Technologies 5 0 Design Recommendations This section presents some design recommendations and alternatives that should be considered in the initial stages of camera integration 5 1 Power Supply Considerations Power can be supplied to the PT1000 VB CL from three different sources Fig
18. Control Block programming language depend on the inputs configured in the GPIO Look Up Table dialog 4 2 2 Camera Controls The 1PORT PT1000 VB CL can send commands to the camera through the Camera Link Camera Control signals The Camera Link specification provides four camera control signals which can be used in a variety of ways The labels of the control outputs to the camera in the GPIO Control Block programming language are Q4 for Camera Link CL Q5 for Camera Link CC2 Q6 for Camera Link CC3 Q7 for Camera Link O 4 This is the same signal as IN CLKO from Pin 1 in Table 3 Refer to Table 9 in Section 6 4 1 for the frequency specifications Copyright 2004 2006 Pleora Technologies Inc Page 16 Rev 060310 Pleora Technologies 4 2 3 Pixel Bus Definition Table 6 lists all the configurations supported by the camera interface of the iPORT PT1000 VB CL CL Signal Pixel uu mre ROOT own v ae e f PA Roomer DATA pe e e 5 mre mem onan ar w w w fe Fort eoun PATA eo e 9 Fortes DATA m m e me 6600 eoumo owww w eo ne M4 foe _ mooums we me m _ Port ce ROUTE NC 9 we ne fe _ Table 6 Grabber Interface Pixel Bus Definition for the iPORT PT1000 VB CL The grabber input should be conf
19. ding unused supply outputs Copyright 2004 2006 Pleora Technologies Inc Page 22 Rev 060310 Pleora Technologies 6 0 Operating Characteristics 6 1 Absolute Maximum Ratings Ambient storage temperature sss 40 C to 125 C Ambient operating temperature sss eene 0 C to 70 C Voltage with respect to DGND WN 0 5 Vto25 V plug o T P 0 5 V to 4 6 V 25 V to 25 V 0 5 Vto7V AZUL 0 5 to 0 5 V 6 2 Recommended Operating Conditions Ambient operating temperature commerc1al 0 C to 70 C Supply voltages 3 0 V to 3 6 V VIN 4 5 V to 16 V 5 Stresses above those listed under Absolute Maximum Ratings may permanently damage the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this manual is not implied Exposure of the device to absolute maximum rating conditions for extended periods may affect reliability Copyright 2004 2006 Pleora Technologies Inc Page 23 Rev 060310 Pleora Technologies 6 3 D C Operating Characteristics Table 8 shows the D C operating characteristics of the 1 PT1000 VB CL o o qme o Y Y 208
20. els for inputs depend on the inputs configured in the GPIO Look Up Table dialog The GPIO labels for outputs are listed in the table Refer to User s Manual Shared Features of 1PORT IP Engines for details about other IO programming labels used by the engine Input Signal Description Table 4 iPORT PT1000 VB CL GPIO Input Signals fomo O o Y aros ommes TT aca Q7 Camera Link control 4 Table 5 iPORT PT1000 VB CL GPIO Output Signals Copyright 2004 2006 Pleora Technologies Inc Page 15 Rev 060310 Pleora Technologies 4 2 Camera Interface The iPORT PT1000 VB CL provides a 28 bit single ended LVTTL LVCMOS de serialized Camera Link compatible interface This approach which just removes the LVDS serializer simplifies integration with existing Camera Link cameras Please refer to the Camera Link specification for more details All Camera Link data and control signals are clocked by RXXCLK See Section 4 2 4 for information about the Camera Link serial communications port 4 2 1 Camera Inputs All Camera Link camera heads have four standard signals Camera Link Frame Valid CL FVAL Camera Link Line Valid CL LVAL Camera Link Data Valid CL DVAL and Camera Link Spare CL SPARE CL FVAL and CL LVAL can be activated by positive or negative signal edges or by high or low levels CL DVAL can be activated by high or low levels The labels for these signals in the GPIO
21. es da eee on DRE QI DEF uei me RIEN seems 29 Figure 12 USRT Timing Diagrams sss 3l Peoro ii 22 Figure 14 Top and Side View cccccsssssssesseesseseeeeeeseeeeseeeeeseeeeeeseseeeeeeseeeeeeeeeeeeeeeeeees 33 Pioute l5 BETON VIO Lorna RT eee ee 33 Figure 16 Bottom 33 List of Tables Table 1 iPORT PT1000 VB CL Characteristics and 8 Table 2 Power and Connector PINOUT oer s is 10 Tabie Camera 12 Table 4 iPORT PT1000 VB CL GPIO Input Signals eese 15 Table 5 iPORT PT1000 VB CL GPIO Output 5 15 Table 6 Grabber Interface Pixel Bus Definition for the iPORT PT1000 VB CL 17 11 18 aC eS T 18 Table D C Operating Characteristics 24 Table 9 A C Sub Clock Delays on the Camera Interface sss 25 Table 10 A C Operating Characteristics for Camera Link Signals 26 Table 11 A C Operating Characteristics of the GPIO 1 15 28 Te T Um 29 Table 13 A C Operating Characteristics of the UART Interfaces
22. his pin should not be driven An internal pull up resistor ensures that the main load is selected by default on power up In the unlikely event that the main load fails in the field and the engine cannot be updated remotely over the GigE link then the back up load can be selected It is therefore recommended that the FPGA SEL pin be connected to a jumper so that it can be easily shorted to ground if a new main load must be programmed into memory as shown in option a in Figure 5 It is also acceptable to just leave this pin unconnected as shown in option b In the default configuration it 1s critical to leave the pin in a high State PT1000 VB CL PT1000 VB CL DVCC DVCC Camera Board Camera Board Jumper open by default FPGA SEL FPGA_SEL E J3 pin 68 Xilinx EPLD No J3 pin 68 Xilinx EPLD XC9572XL Connect XC9572XL a Preferred Option b Secondary Option Figure 5 FPGA SEL Options 5 4 EMI Considerations In most cases it is recommended to provide a good ground connection between the mounting screws and the enclosure Please refer the PT1000 VB In Camera IP Engine Design Recommendations for FCC CE Certification document for more details 5 5 Unused Pins All unused inputs in the Samtec J3 and the Hirose J2 connectors can be left floating They will be held in a known state by weak internal pull ups or pull downs Any unused outputs should be left unconnected inclu
23. igured to match the camera head pixel bus using the CY GRABBER PARAM PIXEL DEPTH and CY GRABBER PARAM TAP QUANTITY parameters of the CyGrabber class in the SDK For the RGB configuration the grabber should be set to 1 tap and 24 bits The grabber output can reformat the data using the CY GRABBER PARAM NORMALIZED and CY GRABBER PARAM PACKED parameters of the CyGrabber class The structure Copyright 2004 2006 Pleora Technologies Inc Page 17 Rev 060310 m Pleora Technologies of the resulting buffer 1s described in the Derived Pixel Type Classes of the Imaging Library section of the Reference Manual PORT C Software Development Kit The SDK also provides functions to swap input ports and to optimize bandwidth usage by shifting the input data 4 2 4 Serial Interfaces The PT1000 VB CL has four serial interfaces that can send and receive data as shown in Table 7 Interface Type Level Port Name Receive Transmit Clock LVCMOS CL_SERTFG CL_SERTC UART Serial Port 0 LVTTL J3 pin51 J3 pin 52 LVCMOS UART_RX UART_TX UART Serial Port 1 LVTTL J3 pin 56 J3 pin 57 LVCMOS RXD TXD SCK USRT Bulk Interface 0 LVTTL J3 pin 53 J3 pin 54 J3 pin 55 RS232 RX RS232 TX UART RS232 TBA J2 pin 12 J2 pin 11 Table 7 Serial Interfaces Serial Port 0 and 1 are standard UARTs with selectable baud rates For more information about these and the USRT interface see Section 6 4 3 and
24. iming with FVAL and LVAL Edge Sensitive Copyright 2004 2006 Pleora Technologies Inc Page 27 Rev 060310 Pleora Technologies m tevarv p lFv2Dv bq tevari FVAL LVAL ecc E E E A Na SS DVAL Mes 1 0 Nt DATA 23 0 CAAA AAS ti vopv 28 1 0 eee Dog M aS t NT Figure 9 Camera Interface Timing with FVAL Edge Sensitive and LVAL Level Sensitive 6 4 2 GPIO Interface The GPIO signals TTL IN 3 0 and TTL OUTI 2 0 are all asynchronous and are specified below in Table 11 Figure 10 1s the related timing diagram Symbol Min Max Units Notes GPIO Signal Pulse Width tepiop 30 m Table 11 A C Operating Characteristics of the GPIO Signals TTLIN OUTIN 1 tcPIopP JM Figure 10 GPIO Timing Diagram 6 4 3 serial Port UART All three of the asynchronous serial ports interfaces CL SERTFG CL 5 UART RX UART TX and the RS232 interface are UARTS These interfaces only support 8 bit data transfer 1 start bit parity even odd or none and 1 2 stop bits As shown in Table 12 a number of preset baud rates can be used as well as a more flexible baud rate factor See the Reference Manual 1 C SDK for more details Copyright 20
25. ink Camera Control 2 connected to LUT output Q5 38 UT ORT_B5 ORT_B6 ORT_B7 ORT_CO ORT C1 ORT C2 ORT C3 ORT C4 ORT C5 If using these supplies please contact Pleora during the specification stage of your design Also these DVCC supplies are not recommended for analog circuitry Analog circuitry should be driven from a separate 3 3 V supply Copyright 2004 2006 Pleora Technologies Inc Page 11 Rev 060310 Pleora Technologies PORT_ SERIAL_ in SDK PORT_ SERIAL_ 0 in SDK Input Clock 1 for multi input device not used Input Clock 2 for multi input device not used Power On Reset Open Collector can be asserted low to reset the module FPGA load select load 0 or load 1 internal pull up Table 3 Camera Connector Pinout Signal Name ORT 1 U lt 4 2 U ORT F1 ORT F2 ORT F3 ORT F4 ORT F5 ORT F6 PORT F7 IN GND GND N CLK1 N CLK2 PWR ON 61 62 63 GND VCC ANALOG VID FPGA SEL lt z 4 5 1251250120 1 lt lt 5 2 gt No Connect TMS TCK The UART is implemented only in firmware Version 3 68 or higher If using this supply please contact Pleora during the specification stage of your design Also the DVCC supply is not recommended for analog circuitry Analog circuitry should be driven from a separate 3 3 V supply In system JTAG is not currently implemented but for future i
26. ks needed to quickly and easily enable third party or custom video applications For more information about the IPORT Connectivity Solution see the User s Manual Shared Features of 1PORT IP Engines Copyright 2004 2006 Pleora Technologies Inc Page 6 Rev 060310 Pleora Technologies 2 2 Models The first available model in Pleora s family of in camera IP engines is the 1 PT1000 VB CL This model is designed specifically for integration into cameras using the Camera Link protocol It 1s equipped with an FPGA load that accommodates the Camera Link interface and in keeping with the protocol encapsulates a serial communications channel over GigE This allows users to update camera configuration registers from a host PC Copyright 2004 2006 Pleora Technologies Inc Page 7 Rev 060310 Pleora Technologies 2 3 Characteristics and Features Table 1 lists key characteristics and features of the 1 PT1000 VB CL Hardware Available as OEM Onboard Memory Inputs Outputs 4xLVTTL Programmable Logic Control Pulse Generators timers 16 bit o 4 JA 3T 5 5 1 5 0 rm m o c m o c rm o 2 D o D nput Debouncing x oftware Controlled IO 0 01 1 151019 U 5 5 2 23 3 lt E 13 U 3 o 5 c c e 21518 121317 Ti 9 TI qm rr o
27. lid before FVAL becomes valid then the full line is dropped by the grabber 3 The configuration FVAL as level sensitive and LVAL as edge sensitive 15 invalid and is seen as FVAL and LVAL edge sensitive 4 Data valid is defined by FVAL valid note 1 LVAL valid note 1 and DVAL valid note 5 5 The valid state of DVAL signal is high when it is set as level high sensitive and low when set as level low sensitive DVAL 15 always valid in the grabber when parameter DataValidEnabled is off 6 If FVAL becomes invalid and LVAL is still valid the line 1s truncated 7 This is a worst case value Three clock cycles can be subtracted if the pixel type is 8 bit 1 tap or 1 clock cycle for all other pixel types except 10 12 bit 2 tap unpacked and RGB unpacked Up to seven clock cycles can be subtracted if the image size 1s a multiple of 32 bytes tvv 2 ti Li2py 9 FVAL gt trary 438 LVAL DVAL DATA XXEXXXXXK 23 0 5 li vzpv Ben Don t Care Window Size N x M Figure 7 Camera Interface Timing When FVAL and LVAL are Level Sensitive rvarv lFv2pv ion tevari FVAL e e ie LVAL see Ay gt DVAL DATA 55555552 x 23 0 Figure 8 Camera Interface T
28. n field updates pins TDI and TDO must be connected via a 0 ohm resistor or an in system TAP controller See Section 5 2 for more details Copyright 2004 2006 Pleora Technologies Inc Page 12 Rev 060310 Pleora Technologies 4 0 Signal Handling The 1PORT PT1000 VB CL handles signals in much the same way as other engine models There are a few minor differences which are described in this section 4 1 GPIO Control Block The Programmable Logic Controller PLC in the iPORT PT1000 VB CL routes signals through a sophisticated GPIO Control Block Figure 2 shows the GPIO Control Block signals for the iPORT PT1000 VB CL For further details on how the engines handle IO signals see the User s Manual Shared Features of iPORT IP Engines Copyright 2004 2006 Pleora Technologies Inc Page 13 Rev 060310 TTL IN O S D TTL IN 1 TTL IN 2 S D TTL IN 3 CL FVAL CL DVAL CL SPARE GPIO CTRL O GPIO GPIO GPIO Feedback Inputs CTRL 1 CTRL 2 _ Pleora Technologies CL_LVAL TTL OUT 2 LUT Q 3 CL_CC3 CL_CC4 O c 2 c C Cc T D Q PG OUTIO PG OUT 1 PG OUT 2 PG OUT 3 RSL OUT DEL OUT GP CNT EQ GP CNT GT TS TRIG O TS TRIG 1 TS TS TRIG 3 Synchronization Block 540 Synchronization and Debouncing Block Q 17 0 Q01 igger tri Pulse
29. ne Design Recommendations for FCC CE Certification In summary this User s Manual complements and should be used in conjunction with up to five other documents User s Manual Shared Features of iPORT IP Engines User s Manual iPORT IP Device Drivers e Reference Manual The iPORT C Software Development Kit Reference Manual The Visual Basic Software Development Kit and iPORT 1000 In Camera IP Engine Design Recommendations for FCC CE Certification Copyright 2004 2006 Pleora Technologies Inc Page 5 Rev 060310 Pleora Technologies 2 0 Overview of the iPORT PT1000 VB 2 1 Highlights Pleora s iPORT PT1000 VB In Camera IP Engine is a fast affordable and simple way to integrate high performance GigE connectivity into industrial cameras The board is ideal for GigE enabling cameras targeted at demanding vision applications in product inspection security surveillance traffic monitoring and post and parcel sorting The PT1000 VB 15 also ready to comply with the AIA s Automated Imaging Association GigE Vision standard The engine is optimized for in camera use with a small square footprint low power consumption and vertical mounts for power GPIO and GigE Straightforward interfaces to parallel data clocks line and frame signals allow most cameras including Camera Link models to support GigE with a simple change out to their back end electronics Purpose
30. pter Copyright 2004 2006 Pleora Technologies Inc Page 19 Rev 060310 Pleora Technologies The three supply configurations are as follows 1 Typical configuration External VIN supply Apply 5 15 V on VIN and ground RET on the Hirose J2 connector This supply is regulated and filtered VIN RET and DVCC DGND can be used internally over the Samtec connector Maximum current requirement at 4 5 V over the VIN RET pins 15 500 mA 2 Internal VIN Supply Apply 5 15 V on VIN and ground RET on the Samtec J3 connector This supply is regulated and not filtered DVCC DGND can be used internally over the Samtec connector VIN RET can be used externally over the Hirose connector Maximum current requirement at 4 5 V over the VIN RET pins is 500 mA 3 Internal DVCC Supply Apply 3 3 V to DVCC and ground GND on the Samtec J3 connector DVCC must be generated by a fully regulated supply This supply 15 not regulated or filtered on the PT1000 VB CL CAUTION VIN and RET or VIN and RET must be shorted together and connected to ground Otherwise the device may be damaged Make sure that at least 2 25 W of power 15 available to this supply The maximum current requirement at 3 3 V over the DVCC DGND pins 15 750 mA Copyright 2004 2006 Pleora Technologies Inc Page 20 Rev 060310 Pleora Technologies 5 2 In System JTAG Figure 4 is a block diagram of the in system JTAG architecture
31. ure 3 illustrates how the different power supplies are related There is one external filtered supply that 1s accessed via the Hirose power and IO connector shown as J2 The other two supply sources are not filtered and are provided over the internal Samtec camera connector shown J3 The only difference between the Hirose VIN RET and the Samtec VIN RET is a common mode choke EMI filter shown as L2 on the Hirose external versus the Samtec internal supplies Otherwise either one but not both of the connectors can supply VIN RET DGND 15 a digital ground and not suitable for analog ground supplies due to switching noise DGND must always be held at the same voltage level as RET or RET DVCC has approximately 500 mA of available current at 3 3 V 1 65 W VIN J3 pins 69 70 71 72 1 Voltage VIN DVCC C O e L M J2 pin 2 Je oa peared J3 pins 31 32 65 RET aa Ca DGND J2 pin 1 d WP 3 4 17 18 45 46 59 60 RET J3 pins 73 74 75 76 Figure 3 Simplified Schematic of the PT1000 VB CL Power Supply Circuitry CAUTION If there is a D C voltage difference between RET or RET and DGND it can damage the ferrite bead FB2 The bead is rated up to only 2 A and has a DC resistance of only 50 mOhms This damage can be caused by a simple misalignment of pins across the Samtec connector or when the Samtec connector is connected to a powered ada
Download Pdf Manuals
Related Search