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QCPU User's Manual (Multiple CPU System)

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2. Q65B 5 slots occupied ist 8 9 10 11 12 extension f 2 9 Y Ww U u o o uw fw ue ES o o 2 eg e 2 g es allgla le 25 a wyS jefe o 0 o0 z Q55B 5 slots occupied ona 13 14 15 16 17 extension i T o o t w u u ju u ey ui E es EP EE IR oo 9 ele e g ee o ojioj o o o o efsr oim a uj rcc Se 5 o0 Q65B 5 slots occupied 3rd 18 19 20 21 22 extension o Ed o o IL ujujuwju o 0 CN x olo NININITN IAN o o o o o oo e 2 j 2 2 S S S Orla 9 9 cK M MIN 1D o o t NININ ITNT NS o o Q65B 5 slots occupied an 23 25 26 27 extension Inhibited 2B0 to 2CF rere Error in mounting 1 Shows when the CPU module 2 is the PC CPU module If the CPU module 2 is the C Controller module a module can be mounted on the slot 1 Figure 2 6 System configuration example for using Basic model QCPU 2 8 ndOLOO Ndd000 nd90 Iepou orseg usn uogeunBijuoo ueis s V L z uongeunByuoo ueis S Lc Table2 3 Restrictions on system configuration available base units extension cables and power supply modules CPU number CPU1 CPU No 1 Basic model QCPU CPU2 CPU No 2 PC CPU module C Controller module Maximum number of exten
3. PLC No 1 Send PLC No 2 Receive PLC No 3fReceive PLC No 1 Receive PLC No 2 Send PLC No 3tReceive PLE No i Receive PLE No 2IReceive PLC No 3 Send Refresh device PLC No 1 lt Shared memory PLC No 2 Refresh device PLC No 2 Shared memory PLC No 2 Refresh devicePLC No 3 lt Shared memory PLC No 2 Set receive device from PLC No 2 Set send device to the other PLC Set receive device from PLC No 2 Auto refresh Auto refresh Auto refresh No point Start End No point Start End No point Start End 1 2 p20 B3F k 1 2 M32 M63 1 2 M32 M63 xe 2 32 w20 W3F lt 2 aghw20 WF 2 32 D32 D63 lt i 3 3 3 4 4 4 d Receive setting from CPU No 2 e Send setting of CPU No 2 f Receive setting from CPU No 2 1 Auto refresh setting of CPU No 1 2 Auto refresh setting of CPU No 2 3 Auto refresh setting of CPU No 3 Figure 4 32 Auto refresh setting related to sending and receiving CPU No 2 data Flow of sending data from CPU No 2 to other CPUs CPU No 2 writes device data set in Auto refresh CPU No 2 send data to the auto refresh area in CPU No 2 at END processing CPU No 2 sends data in auto refresh area of CPU No 2 to CPU No 1 and CPU No 3 in multiple CPU high speed transmission cycle CPU No 1 and No 3 read the received data from CPU No 2 to a device set in Auto refresh CPU No 2 receive area at END processing PLC No 1 PLC No 2 PLC No 3 Multiple CPU high sp
4. This manual confers no industrial property rights or any rights of any other kind nor does it confer any patent licenses Mit subishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual 2008 MITSUBISHI ELECTRIC CORPORATION Print date Manual number Revision May 2008 SH NA 080485ENG G Addition of Universal model QCPU and Process CPU models Model addition Q02PHCP Q06PHCPU QOS3UDECPU QO4UDEHCPU Q06UDEHCPU Q13UDEHCPU Q26UDEHCPU Partial correction A term MELSECNET G has been revised to CC Link IE controller network through this manual GENERIC TERMS AND ABBREVIATIONS Chapter 1 Section 1 1 2 1 1 2 1 2 2 1 3 22 2 3 2 4 3 1 3 8 4 2 4 3 1 4 3 3 5 1 5 2 6 1 Dec 2008 SH NA 080485ENG H Addition of Universal model QCPU and C Controller module Model addition QOOUCPU Q01UCPU Q10UDHCPU Q20UDHCPU Q10UDEHCPU Q20UDEHCPU Q61P D Partial correction ABOUT MANUALS GENERIC TERMS AND ABBREVIATIONS Chapter 1 Section 1 1 1 3 2 1 1 2 1 2 2 1 3 2 3 2 4 3 1 3 1 2 3 1 3 3 2 3 3 2 3 7 3 9 4 1 1 4 1 2 4 1 3 4 1 4 4 1 5 4 3 1 4 3 3 4 5 5 1 5 2 7 1 8 1 8 2 2 A 10 INTRODUCTION This manual is designed for users to understand the multiple CPU system including information of the
5. Q30B Generic term for the Q33B Q35B Q38B and Q312B main base units Q3LISB Generic term for the Q32SB Q33SB and Q35SB slim type main base units QS3LIRB Another name for the Q38RB redundant power main base unit QSLIDB Generic term for the Q38DB and Q312DB multiple CPU high speed main base units Q5LIB Generic term for the Q52B and Q55B extension base units Q6OB Generic term for the Q63B Q65B Q68B and Q612B extension base units Q6LIRB Another name for the Q68RB redundant power extension base unit QA1S60B Generic term for the QA1S65B and QA1S68B QA6LIB Generic term for the QA65B and QA68B extension base units A5LIB Generic term for the A52B A55B and A58B extension base units A6LIB Generic term for the A62B A65B and A68B extension base units QA6ADP A50B A60B Abbreviation for a large type extension base unit where the QA6ADP is mounted Power supply module Power supply module Generic term for the Q series power supply module slim type power supply mod ule and redundant power supply module Q series power supply module Generic term for the Q61P A1 Q61P A2 Q61P Q61P D Q62P Q63P Q64P and Q64PN power supply modules Slim type power supply module Abbreviation for the Q61SP slim type power supply module AnS series power supply module Generic term for the A1S61PN A1S62PN and A1863 power supply modules A series power supply module Generic term for the A61P A61PN
6. PLE Empty Emply 16points Input 16points Output x 16points 66 Input 1 points Assigning the 1 0 address is not necessary as the CPU does T automaticaly Leaving this setting blank will not cause an error to occur Base setting Base mode Auto C Detail 8 Slot Default t Default Base model name Power model name Extension cable I IsIsis alata Cero eer mee Import Multiple CPU Parameter Read PLC data Acknowledge XY assignment Multiple CPU settings Defaut Check End Cancel i To next page SJejeureJeg ueis s dD eidnini eui dN Bumes zg Ndd sseoouqd nid90 Jepoui eoueuuojeg uH id90 pow dseg eui 10 Huas JejeuleJed L z g 8 13 From previous page Intelligent function module detailed setting Rad Check settings of the control CPU HAW error time PLC 1 0 response operation lime mode x PLC No 1 v PLC No 1 v PLC No 1 v PLC No 2 v PLC No 2 v PLC No 2 v PLC No 3 v PLC No 3 v PLC No v PLC No 1 v PLC No 1 v PLC No v 91 1 10 1 2 Tz 1201 4 1 alalalalalalalalalalalalalalala alafalalalalala lala lala fa S l 3 3 ES E 14 1 5 Jsettings should be set as same when using multiple CPU Cancel Set parameters for non multiple CPU System Write set parameters in
7. E Slim type main base unit 32 point module is mounted on each slot Q35SB 5 slots occupied CPU 0 1 2 3 cel gea Slot number o o o n O eene l O number e e i O ett tjJo ni t z o anama Slim type power L supply module CPU module 3 CPU module 2 CPU module 1 Figure 2 22 System configuration example on using Q3LISB Table2 11 Restrictions on system configuration available base units extension cables and power supply modules CPU module 1 CPU No 1 CPU module 2 CPU No 2 CPU module 3 CPU No 3 CPU number Maximum number of Extension not allowed extension stages Maximum number of Q32SB 3 No of CPUs mountable I O Q33SB 4 No of CPUs modules Q35SB 6 No of CPUs Available main base Q32SB Q33SB Q35SB unit model Available power Q61SP supply module model When the QOOUCPU Q01UCPU QO2UCPU is used as the CPU module 1 only the C Controller module can be mounted Therefore the CPU modules 3 does not exist Precautions The slim type main base unit has no extension cable connector The extension base unit and GOT cannot be bus connected Since the current consumption of the CPU module exceeds the rated output current of the power supply ji module Q61SP mounting 4 CPU modules is not allowed No of CPUs indicates the number of CPU modules set in the No of PLCs of the G
8. Figure 4 20 Outline of auto refresh operation 4 19 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 3 Precautions a Local device setting Note4 6 Device ranges set for the use of the auto refresh cannot be set to local devices If set the refresh data will not be updated b Setting for using the same file name as the program in the file register Note4 7 Do not set devices for the use of the auto refresh in the file register for each program If set auto refresh will be performed on the file register that corresponds to the last scan execution type program executed c Assurance of data sent between CPUs The old data and the new data may be mixed in each CPU due to the timing of sending data from the host CPU and auto refresh in the other CPU The following shows the method to realize the data consistency of the user data in the communication by the auto refresh 1 Data consistency for 32 bit data Since the data transmission by the auto refresh mode can be set in units of 32 bits only data separation for 32 bits data will not occur AJOWSW pegeus dD Husn useJje1 one Aq uoneoiunuulo2 Z Lr Asowaw peeus dD Buisn se npoui Ndo ueewjeq suoneoiunuluo9 Ly Note4 6 Basic The Basic model QCPU does not have any local device 2 Note4 7 Basic Since the file register in the Basic model QCPU is fixed file register cannot be set for each program 4 20 2 Data consistency for data exc
9. T O No point d x sen 3072810000 B1307T E zen 3 1 2 3 USET 3072 610000 6113071 3 3 usEz 30721610000 13071 4 spuses sorz erocoo 613071 Pu Ns No Na Na eng touldbgsetas sane hen Ippon HutleCPUPaonete Chek Emo teen Figure 3 38 Example of setting host CPU number of multiple CPU system 3 40 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Point When making multiple CPU settings of all CPU modules in multiple CPU system same set No specification to Host CPU number If No specification is set at Host CPU number all CPU modules used in the multiple CPU system can share the same multiple CPU setting 2 Timing of checking host CPU number The host CPU number of the multiple CPU system is checked when the power supply of the programmable controller is turned ON or when the CPU module is reset If the CPU No set in the multiple CPU setting is not identical to the CPU No determined by the mounting position of the CPU modules CPU LAY ERROR error code 7036 will occur In this case the Universal model QCPU operates regarding the CPU No determined by the mounting position of the CPU modules as correct Point Setting Host CPU number in the Multiple CPU settings of PLC parameter permits checking the auto refresh direction on the following screens Multiple CPU setting screen Auto refresh
10. speed transmission i i l I 1 e ENDO END4 O Sequence program j CHEERS E 38 d aii E A po 0g iz 1 ol LO i NC od Vi Mog iol V Vo Multiple CPU 145 IRET 145 IRET 145 IRET vV 145 IRET 145 IRET i KI KH ei I Ki synchronous Multiple CPU 145 J IRET Read interrupt program high speed gt eading an imposition Reading an transmission peer signal signal when multiple CPU cycle synchronous interrupt program is not used Figure 1 6 Reading data using multiple CPU synchronous interrupt program Point The synchronous processing with the Motion CPU is available when the following CPU modules are used Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172DCPU Q173DCPU uleis s fido ejdnjnuu jo seunjee Z4 1 7 c Timing of data send receive between the CPU modules can be checked The sampling trace function of the Universal model QCPU enables to check the data send receive timing with the Motion controller Timing of data send receive can be checked between the Universal model QCPUs Using the sampling trace function facilitates to check the data send receive timing between CPU modules and reduces the debug time of the multiple CPU system Sampling trace result display by GX Developer Trace result Bit device Contact Coil Display units 1 po U3E0 G10000 0 M160 MO 4 Count 1024 Time sec Step
11. Auto refresh No it Start End 1 2 MB4 M35 gt 2 32 D64 D95 gt 3 4 5 B i Send setting of CPU No 3 1 Auto refresh setting of CPU No 1 2 Auto refresh setting of CPU No 2 Figure 4 29 Setting examples of auto refresh 3 Auto refresh setting of CPU No 3 4 29 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES b Data flow among CPU modules The following explains the data flow among CPU modules by the auto refresh set as a 1 Flow of sending data from CPU No 1 to other CPUs lt Parameter setting gt Figure 4 30 shows the settings related to sending and receiving CPU No 1 data a to c in Figure 4 30 in the setting example of auto refresh in Figure 4 30 PLC No T Send PLC No 2fReceive PLC No 3tReceive PLC No 1 Receivel PLC No 2 Send PLC No 3tReceive PLC No 1 Receive PLC No 2 Receive PLC No 3 Send Refresh device PLC No 1 gt Shared memory PLC No 1 Refresh device PLC No 2 Shared memory PLC No 1 Refresh device PLC No 3 lt Shared memory PLC No 1 Set send device to the other PLC Set receive device from PLC No 1 Set receive device from PLC No 1 Auto refresh Auto refresh Auto refresh l No _point Start End No point Start End No point Start End 1
12. No of CPUs 1 No of CPUs indicates the value set in the multiple CPU setting of the PLC parameter ba 2 Universal model QCPU except the QOOUCPU Q01UCPU Q02UCPU can be mounted 3 Universal model QCPU except the QOOUCPU Q01UCPU Q02UCPUJ and Motion CPU Q172UDCPU Q173UDCPU can be mounted 4 High Performance model QCPU and Process CPU can be mounted 5 The PC CPU module occupies 2 slots 6 The PC CPU module PPC CPU852 MS 512 can be mounted 3 14 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Mounting position of CPU module ainpow Jejouo2 9 e 9In pou dO p exPINDOW dO amp z MdOO lepoui 5 JesueNum einpoui A ddns 180g ieu 0111213 9Inpou ndo ex PINPOW dd 2 1d90 epow JesaeAiu ainpow A ddns je og zMdOO epow Jesueniu z 1d90 epow JesueAiu icu 0 1 2 3 jnpow A ddns amod 3 1 Mounting Position of CPU Module 3 1 3 When CPU No 1 is Universal model QCPU Z Ajduie 21d ainpow Ja JONUOD 2 e2INPOW dD z 1d90 epow JesjeAu einpoui A ddns 190g popu o 1 2 ainpow JE O UOD 9 Adw 21d SInpoui dd zMdOO epow eSJ AUN jnpow A ddns 48M0dg gt z NddO pow jesueniun e npoui A ddns 180g p Aydw9 91d e npouJ Jejoguo2 9 Adw 21d ze MdOD epow Jesaenu jnpow A ddns 190g cpu o 1 2 Adw 9Td e 8INPOW ndo e 9Inpoul Nd z 1dO0 Iepoui JesueA
13. Figure 2 7 System configuration when Q3LB is used VON NdI S fidO SS920J4g JO NdI JEPowW eoueuuojJed uBiH Buisn uoneunByuoo uejs S TLZ 2 10 2 11 4 Only one memory card can be mounted Select an appropriate memory card from the SRAM Flash and ATA in accordance with application and capacity When a commercial memory card is used the operation is not guaranteed 2 Use the Q series power supply module for the power supply module Keep the current consumption within the rated output current of the power supply module The Slim power supply module and Redundant power supply module are not available for the power supply module 3 Use of the Process CPU or the Universal model QCPU in combination with the AnS A series compatible power supply module the I O module and the special function module is not allowed L Refer to Section 7 1 4 The Q Series power supply module is not required for the Q5LIB extension base unit 5 The motion CPU and PC CPU module do not accept battery for QCPU and memory card 6 For further information on PC CPU module consult CONTEC Co Ltd Tel 81 6 6472 7130 7 Be sure to set the control CPU of the motion module to the Motion CPU 8 The PC CPU module and C Controller module cannot be mounted together 9 When mounting the Universal model QCPU and the PC CPU module at the same time use the PPC CPU852 MS 512 as the PC CPU module 10 The QOOUCPU Q01UCPU Q02UCPU cannot be
14. Oo 1 243 4 4 4 5 6 7 Slot number 2 5 o02 9o2 Input outut A D D A Input Output 8 88 85 la E SQ SQ N eo 2 EZ EZ EE Qoloooo Ww x x LL LL QIEDIESD NU 1O a2 o2 o8 uw gt 9 9 x lt gt 5 a Ent s 2 o o 9 2 z gt gt s 2 s El sis I rox gt x x x gt umber oi 16 16 16 16 16 16 slot points points points points points points points 1 1 1 1 Ul 2 2 Control CPU setting Figure 8 10 Configuration example of multiple CPU system 1 I O assignment and auto refresh settings Figure 8 11 shows a setting example of the I O assignment of each module and Figure 8 12 shows a setting example of the auto refresh area For the I O assignment settings refer to Section 3 3 For the auto refresh area settings refer to Section 4 1 4 Q parameter setting PLC name PLC system PLC fie PLC RAS Device Program Boot fle SFC 1 0 assignment 1 0 Assignment Model name Switch setting T points Detailed setting TBpoints T6points 16points TBpoints T6points Assigning the I D address is nol necessary as the CPU does it automatically Leaving thie setting blank will not cause an error to occur Base settingl Base mode Auto Detail Base model name Power model name Extension cable 8 Slot Default 12 Slot Default a lala falala lalla Ext Bases Ext Base
15. 1 The following number of points is set by the default Default value of CPU specific send range Number of CPUs CPU No 1 CPU No 2 CPU No 3 CPU No 4 Two CPUs 7k points 7k points Three CPUs 7k points 3k points 3k points Four CPUs 3k points 3k points 3k points 3k points 2 Sets the total of all CPUs to be the following points or lower When constituted with two CPUs 14k points When constituted with three CPUs 13k points When constituted with four CPUs 12k points AJowaw peeus Add Buisn se npoui Ndo ueewjeq suoneoiunuluo9 Ly ese uoissiuisueJi peeds ybiy Add ejdninui Bursn yseues one Aq uogeoiunuuoo pp 4 26 Point Selecting Advanced settings enables to change the number of points in Restricted system area used for dedicated instructions to 2 k points Changing the number of points in system area to 2 k enables to increase the number of dedicated instructions can be executed concurrently in a scan The following shows the setting screen and setting range of the case where Advanced settings is selected Item Multiple CPU settings No of PLC No of PLO 4 v Host CPU number PLC No 1 x Operating mode Error operation mode at the stop of PLC F Z All station stop by stop error of PLC2 J All station stop by stop error of PLC3 IV All station stop by stop error of PLCA Multiple CPU synchronous startup setting Target PLC Nol
16. 4 9 1 Communication using auto refresh a Operation of auto refresh Auto refresh allows communications using the auto refresh area of the CPU shared memory By making multiple CPU settings in PLC parameter data are automatically written read between all CPU modules of the multiple CPU system As device memory data of other CPUs are automatically read by the auto refresh function the host CPU can use those device data The following CPU modules in a multiple CPU system can perform auto refresh using auto refresh area in CPU shared memory Point Auto refresh is a factor for increasing the scan time in the multiple CPU system For calculation formulas for the auto refresh time refer to Section 5 2 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES Figure 4 5 shows an outline of operations when CPU No 1 performs auto refresh of 32 points for BO to B1F and when CPU No 2 performs auto refresh of 32 points for B20 to B3F CPU No 1 CPU No 2 Host CPU operation information area Host CPU operation information area Restricted system area Restricted system area Auto refresh area 3 Read by END Auto refresh area processing CPU No User setting area User setting area 1 Read by END 2 Read by END processing of CPU No 1 processing of CPU No 2 Device Device BO to B1F for CPU No 1 4 Read by END BO to B1F for CPU No 1 B20 to B3F for CPU No 2 processing of CPU No 1 B20 to B3F for CPU No 2 The processes
17. seeenn 3 9 Resetting the multiple CPU system 3 10 Operation for CPU module stop error 3 11 Host CPU number of multiple CPU system sssssssssseeeeeeeneeeee nennen A 12 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4 1 to 4 56 4 1 Communications between CPU modules using CPU shared memory ss 4 3 4 1 1 GPU shared memory eene PR HR UR RI EU OR RR RU Eher 4 3 4 1 2 Communication by auto refresh using CPU shared memory sss 4 8 4 1 3 Communication by auto refresh using multiple CPU high speed transmission area 4 23 4 1 4 Communication using CPU shared memory by program 4 36 4 1 5 Communications between CPU modules when the error occurs sssssss 4 46 4 2 Communications with instructions dedicated to Motion CPU ssssseeese 4 2 1 Control instruction from QCPU to Motion CPU 4 3 Communication with Dedicated Instructions ssssseeeeenee 4 3 1 Writing reading of device data from QCPU to Motion CPU 4 3 2 Starting interrupt program from QCPU to C Controller module PC CPU module 4 51 4 3 8 Writing reading of device data from QCPU to QCPU ssssssssessneneees 4 52 4 4 Multiple CPU Synchronous Interrupt ssssssssssssssseseeneeeenene nennen tenens 4 53 4 5 Multiple CPU Synchronized Boot up ssssssssseseeneeeenneen enne nnne nennen enses 4
18. 1 10 CHAPTER1 OUTLINE 1 3 Difference from Single CPU System Differences between the single CPU system and the multiple CPU system are described in this section Refer to the manuals below for the single CPU system gt QCPU Users Manual Hardware Design Maintenance and Inspection User s Manual Function Explanation Program Fundamentals for the CPU module used 1 When using the Basic model QCPU Table1 2 Difference from single CPU system Refer Item Single CPU system Multiple CPU system ence Maximum number of extension 4 stages stages Maximum number of mountable 4 49 24 25 No of CPUs I O modules Q30B Q30SB Q30DB Main base unit model QORB B Section System con Q50B Q60B 2 1 1 figuration Extension base unit model Q6ORB E Extension cable type QCO05B QC06B QC12B QC30B QC50B QC100B Overall distance of extension e Within 13 2 m cable QenriP Q60SP Power supply module model Q6ORP zi w Basic model QCPU Function version A or later Function version B Oo I O module Function version A or later F Available Function version B or later 3 module Function version A or later for QD62 T Intelligent function module Function version A or later 9 QD62D and QD62E No version 7i restriction for QI60 El GX Developer Version 7 or later Version 8 or later e 5 x pe GX Configu
19. Q Battery for QCPU Q6BAT Universal model Bree eater eee Q7BAT SET C QCPU Ge Q3LIRB type redundant power main base unit 2 Redundant power supply input output intelligent function module Extension cable Q5LB type extension base unit 3 Q6 ORB type redundant power extension base unit 2 uongeunByuoo uejs S Lc 1 Only one memory card can be mounted Select an appropriate memory card from the SRAM Flash and ATA in accordance with application and capacity When a commercial memory card is used the operation is not guaranteed 2 Use the redundant power supply module for the power supply module The redundant power supply modules Q63RP and Q64RP can be used on one redundant power supply base unit at the same time The Q series power supply module and the slim type power supply module are not available for the power supply module 3 The Q Series power supply module is not required for the Q5LIB extension base unit 4 When the Q8BAT is used for the Universal model QCPU use the connection cable whose connector part displays A For details of connector part of a connection cable refer to the following manual L gt QCPU User s Manual Hardware Design Maintenance and Inspection LON Nd S NddD 9pouu jesJeAluf Buisn uoneunByuoo uejs S crz Figure 2 19 System configuration when QORB is used
20. default synchronizes the boot up of all CPU modules 1 21 uleisAS fido ejBuis wo soususHig E4 Table1 5 Difference from single CPU system continued Item Single CPU system Multiple CPU system Reference NS Transmission from each CPU module Communication using QCPU f is up to 2k words in total of four ranges standard area by auto Not available Section 4 1 2 The total for all CPU modules is 8k refresh words m A memory size that can be used for all Communication using multi CPU modules is as shown below ple CPU high speed trans sk Not available Using two CPU modules 14k words Section 4 1 3 mission area by auto Using three CPU modules 13k words renee Using four CPU modules 12k words En RB Perform communication with the TO ied es ii jabi instruction FROM instruction and or Sedos Communica sharga memoryoy apro ot availaoie an instruction using the multiple CPU ection tion bet ram Dn eee j9 shared device U3En GD CPU mod les Communication is available with the fol Communication from Univer lowing z Section 4 2 sal model QCPU to Motion Not available Motion dedicated instruction 5 types Section 4 3 1 i 3 CPU Multiple CPU high speed transmission dedicated instruction 3 types Communication from the Perform communication with the multi Universal model QCPU to NS Not available ple CPU transmission dedicated Sect
21. Point If the operation of a CPU is halted by a stop error a MULTI CPU DOWN error code 7000 stop error will occur at the CPU on which the error was detected Depending on the timing of error detection a MULTI CPU DOWN error may be detected in a CPU of MULTI CPU DOWN status not the first CPU on which a stop error occurs For example if a stop error occurs in CPU No 2 and CPU No 3 is halted as a direct consequence of this CPU No 1 may be halted because of the stop error on CPU No 3 depending on the timing of error detection Fa 1 Stop with OPERATION ERROR 0 1 2 3 4__ Slot number e P c ooo0000 ooo0000 ooo0000 T E x 1 E Control CPU setting Es 2 Stop occurs with stop error detection of CPU No 2 MULTI CPU DOWN occurs drea neess 3 Stop may occur with stop error detection of CPU No 3 depending on the error detection timing MULTI CPU DOWN occurs Figure 3 36 Detection of stop error Because of this CPU No different from the one of initial error CPU may be stored in the error data s common information category To restore the system remove the error cause on the CPU that is stopped by an error other than MULTI CPU DOWN In Figure 3 37 the cause of the CPU No 2 error that did not cause the MULTI CPU DOWN error is to be removed PLC diagnostics PLC status PLC operation
22. Restricted system area Total module The system area is used for dedicated instructions Set the number of points for a system area to be assigned for each CPU Setting range 1k point to 2k point Displays the total of number of points of the host CPU send area and the Setting range 1 to 16k points restricted system area that are allocated to the each CPU module Setting unit 1k point a 2 3 4 27 Sets the total of all CPUs to be the following point or lower When constituted with two CPUs 14k points When constituted with three CPUs 13k points When constituted with four CPUs 12k points Sets the total of all CPUs to be 16 0k points or lower For dedicated instructions refer to the manual of the Motion CPU CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES b Auto refresh setting Auto refresh setting is a setting to use the auto refresh function The 32 ranges can be set for each CPU modules Auto refresh setting screen and the setting range are shown below Auto refresh settings PLC No T Send PLC No 2 Receive PLC No 3Receive PLC No 4 Receive Refresh device PLC No 1 gt Shared memory PLC No 1 Set send device to the other PLC Auto refresh E CPU specific send range U3E0 percepi Lu LIEN lt m2048 M2079 gt G13058 G13059 dior ios br 1000 pio gt mi3070 613071 O a ae Total points 62 Settable points
23. Version 1 25AB or later 4 GX Configurator TI Version 1 24AA or later Version 1 24AA or later Version 1 24AA or later Version 1 24AA or later 4 GX Configurator TC Version 1 23Z Version 1 23Z Version 1 23Z Version 1 23Z or later or later or later or later 4 Version 1 23Z Version 1 23Z Version 1 23Z Version 1 23Z GX Configurator FL M 2 3 4 or later or later or later or later Version 2 25B Version 2 29F Version 2 29F GX Configurator QP Not available or later or later or later GX Configurator PT Version 1 23Z Version 1 23Z Version 1 23Z Version 1 23Z or later or later or later or later 4 Version 1 21X Version 1 21X Version 1 21X Version 1 21X GX Configurator AS 9 3 4 or later or later or later or later GX Configurator MB Version 1 08J or later Version 1 08J or later Version 1 08J or later Version 1 08J or later GX Configurator DN Version 1 23Z or later Version 1 23Z or later Version 1 24AA or later Version 1 24AA or later 4 1 The software can be used by installing GX Developer Version 8 484 or later 2 The software can be used by installing GX Developer Version 8 62Q or later 3 The software can be used by installing GX Developer Version 8 68W or later 4 The software can be used by installing GX Developer Version 8 78G or later 5 The B
24. int ISettings should be set as same when using multiple CPU Execute it while waiting fe Acknowledge XY assignment Q parameter setting PLC name PLC system PLC fle PLC RAS Device Program Bootfile SFC O assignment uo Ss PLC Empty v Emply Output X X 16points 16points 16points ipu Input points ing hecessary as the CPU does it automatically Leaving this setting blank will not cause an error to occur Base setting Base model name Power model name Extension cable j Base mode Auto C Delail a alala 8 Slot Default 12 Slot Default ISeltings should be set as same when using multiple CPU Import Multiple CPU Parameter _ Read PLC data Acknowledge XY assignment Muliple CPU settings Defaut Check End Cancel i To next page Refresh settings option With change of settings 4 settings from setting 1 to setting can be made After setting select Setting completed and close the multiple CPU setting window Select I O assignment and display the I O assignment setting window I O assignment option Select the slot to PLC Empty that does not mount the CPU module for each type Select the type of each module from the pulldown menu Select Detailed setting on the I O assignment setting w
25. 9 Notes 4 For the Basic model QCPU the online module change setting is not available For the High Performance model QCPU modules cannot be replaced online To replace a module online when using the Process CPU set Enable online module change with another PLC 8 7 Ndd 80014 Nddo epow eoueuuojeg YBIH NddD pouw dseg euj 10 Bumes Jojeweseg L z8 sJejeureJeg ueis s dO Sidyinw eui dN Bumes zg 8 8 Multiple CPU settings No of PLC No of PLC 4 v Host Operating mode 7 Error operation E atthe coe of PLC F All station stop by stop error of PLCI I All station stop by stop error of PLC2 Iv Al station stop by stop error of PLC3 I All station stop by stop error of PLC4 From previous page Online module change Enable online module change with another PLC When the online module change is enabled with another PLC 4 MU status outside the group cannot be taken r170 sharing when using Multiple CPUs All CPUs can read all inputs T AI CPUs can read all outputs Communication area setting refresh setting CPU specific send range PLC side device Change screens Setting4 J Set starting devices for each PLC PLC Auto refresh area Caution Dev starting 0100 Point Start End Start End Not 0008 DOOF D100 D1071 No 2 0014 0027 D108 0127 No 3 0006 0008 D128 D133 No 4 0002 0003 D134 D135
26. V Use multiple CPU high speed transmission IV All station stop by stop error of PLCS Pigeon IV All station stop by stop error of PLC4 PLC User setting area Auta refresh poni VO Ne point Stat End por Seti MoE CHL sinere tarie ssi joe perpe ETUR o No2 3 use 3042 610000 613041 30 Seti i Not No3 3usE2 3oeo g10000 G13053 12 No 4 aju3E3 3072 610000 613071 Set auto refresh setting if itis needed No setting Already set usse Total T2K points Advanced settings Assignment confirmation The total number of points is up to 12K Settings should be set as same when Import Multiple CPU Parameter Check using multiple CPU ser To next page 8 24 Setting of carry over project Select the project that carries over multiple CPU setting and I O assignment Click Open When OK is selected the multiple CPU setting and the I O assignment setting data are read from the specified project and the data is overwritten Check the multiple CPU settings When changing a device in auto refresh setting select Auto refresh and input a device number to be changed Items with should have the same settings for each CPU module After checking the multiple CPU settings or completion of correction select END and close the multiple CPU setting window CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM From previous
27. to CPU No 1 send data to CPU No 2 receive area W3F 3 w40 to CPU No 3 receive area lt wsr CEA 1 Writing by END processing of CPU No 3 2 Sending data from CPU No 3 to CPU No 1 and CPU No 2 3 Reading by END processing of CPU No 1 4 Reading by END processing of CPU No 2 PLC No 2 Multiple CPU high speed transmission area PLC No 1 User free area Auto refresh area PLC No 2 User free area Auto refresh area PLC No 3 e PLC No 3 Multiple CPU high speed transmission area PLC No 1 User free area Auto refresh area PLC No 2 User free area Auto refresh area PLC No 3 User free area Auto refresh area Device to CPU No 1 receive area to CPU No 2 send data to CPU No 3 receive area to CPU No 1 receive area to CPU No 2 send data to CPU No 3 receive area F s Auto refresh area Device CPU No 1 receive area CPU No 2 receive area to CPU No 3 send data CPU No 1 receive area CPU No 2 receive area L to CPU No 3 send data Does not perform refresh Figure 4 37 Flow of send data in CPU No 3 to other CPUs when setting blank to No 2 field of PLC No 2 4 33 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4 Precautions a Local device setting Device ranges set for the use of the auto refresh cannot be set to local devices If set th
28. 2 32 2 33 Point The QOOUCPU Q01UCPU QO2UCPU is not available for the multiple CPU system When the multiple CPU system is configured using the Universal model QCPU except QOOUCPU Q01UCPU QO2UCPU or the Process CPU as the CPU No 1 only the following modules can be used as the CPUs No 2 to CPU No 4 High Performance model QCPU Process CPU Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU When duplicating power supply use the redundant power supply base unit and the redundant power supply module For the power supply module mounted on the redundant power supply base unit only the redundant power supply module can be used CHAPTER2 SYSTEM CONFIGURATION b Outline of system configuration 2 1 System configuration 2 1 3 System configuration using Universal model QCPU as CPU No 1 ojojojo ojo
29. nnunnu Word device Current value 16 bit x Decimal 1024 1023 1022 1021 U3E0 G10010 2450 2451 2452 2453 U3E0 G10000 20156 20157 20158 20159 D0 30568 30567 30566 30565 D200 0 0 0 0 w100 30619 30618 30617 30616 Count 1024 Time sec Program Create CSV file Figure 1 7 Sampling trace at the time of configuring multiple CPU system Point P The sampling trace of the other CPU module data can be executed specifying the following CPU modules Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172DCPU Q173DCPU 1 8 CHAPTER1 OUTLINE 3 System configuration based on load distribution a Distribution of processing By distributing the high load processing performed on a single QCPU over several CPU modules it is possible to reduce the overall system scan time Control in 1ms or less Control in several to several dozen ms Machine control high speed Data processing low speed CPU module for machine control CPU module for data processing 7 Machine control speed is further increased with All controls are executed with one QCPU load distribution according to the control cycle Figure 1 8 Distribution of processin
30. Available start devices are X Y M_ L B D WR ZR SM SD SB SW Word is used for points E very 2 points are counted as a set Settings should be set as same when using multiple CPU Check Cancel Figure 4 28 Auto refresh setting screen Table4 9 List of setting item for the refresh setting Item Setting description Setting range Specifies the number of points for data communication in word Setting range 2 to 14336 points Number of points unit Setting unit 2 points 2 Specifies the device which performs the data communication Device available for send range ifi vice whi unicati i X Y M L B D W R ZR SM SD SB SW auto refresh i i i 8 Specifies the device sent by the host CPU when the CPU Device available for receive range Start eat sn X Y M L B D W R ZR specific send range setting is the host CPU and specifies the Sets blank when auto refresh is not executed device received by the host CPU when the CPU specific send range setting is the other CPU The Start fields can be left blank for receive range 1 Setting which exceeds the number of points of the host CPU send area allocated to the each CPU module CPU specific send range cannot be set 2 Bit device can be specified in units of 32 points 2 words only 3 Device number is No 1 to No 32 which cannot be duplicated Ajowaw peeus dD Buisn se npoui Ndo ueewjeq suoneoiunuluo9 py es
31. CPUS with the instructions listed below FROM instruction Instructions that use inteligent function module device ULAGLI D Intelligent function module CPU 0 1 2 3 7 Slot number QD Es op naagana i 000000 J o AAAA WANANANANANANAS AAAA AAAA A ENAA EEREN o o TIeausteousis 2 Control CPU setting Buffer memory can be read Figure 3 27 Reading from intelligent function module 3 28 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM b Writing to buffer memory The following instructions cannot be used to write data to the buffer memory of intelligent function modules being controlled by other CPUs TO instruction Instructions that use inteligent function module device ULNGL T Intelligent function modules dedicated instructions An SP UNIT ERROR error code 2116 will be triggered if an attempt to write to the intelligent function module controlled by other CPU is carried out Intelligent function module n CPU 0 1 2 3 5 6 7_ Slot num
32. JSettings should be set as same when using multiple CPU Import Multiple CPU Parameter Read PLC data Acknowledge XY assignment Multiple CPU settings Default Check End Cancel Figure 8 11 I O assignment settings of each module 8 28 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM Change Eum Setting 1 Set starting devices for each PLC Send range for each PLC The auto refresh area Caution Dev stating DOJ Poit End Stt End Not 32 X 000 X OTF Doj D3l D32 D63 Change screens Setting 2 Set starting devices for each PLC Send range for each PLC PLC side device The auto refresh area Caution Stat Figure 8 12 Auto refresh area settings Ndd SseooJg pue f1d20 epoui soueWJOLeY YBIH NddD pow siseg au 40J sajdwexe urej60Jg pE useJjeJ ojne Buisn sejduiexe wes6oid uoneoiunuuo g 8 29 2 Example of bit amp word data transmission from CPU No 1 to No 2 Table8 1 Auto refresh devices used in each CPU module Auto refresh devices used in CPU No 1 Auto refresh devices used in CPU No 2 MO MO D0 D1 D0 D1 Program example Program by which bit and word data are sent ffom CPU No 1 to CPU No 2 CPU No 1 MO CPU No 1 transmission bit Transmission instruction DMOV K1234 DO CPU No 1 transmission word CPU No 2 sM400 MO e Normally ON CPU No 1 CPU No 2 transmission reception bit bit DMOV
33. M No 2 M No 3 Iv No 4 Online module changef Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs All CPUs can read all inputs T All CPUs can read all outputs Multiple CPU high speed transmission area setting Communication area setting refresh setting v Use multiple CPU high speed transmission CPU specific send range PLC User setting area int K 1 0 No No 1 3 U3E0 No 2 3 U3E1 int Stat End joint 3072 610000 G13071 ix No 3 3 U3E2 fi 3072 G10000 G13071 o ly 3072 610000 G13071 lu i iT No 4 3 U3E3 Set auto refresh setting if it is nee N ng Already set Total 16K points The total number of points The total points contain the capacity of the restricted system area 3072 610000 G13071 fi i ly vi Assignment confirmation is up to 16K Settings should be set as same when Import Multiple CPU Parameter Check ena Cancel using multiple CPU Figure 4 27 CPU specific send range setting screen Table4 8 List of parameter setting display item for CPU specific send range setting Setting description Setting display value CPU specific send range i 1 Sets the number of points of data that each CPU module sends Settingrange Oto HIC palnis Setting unit 1k point
34. Processing of auto refresh CPU No 1 CPU No 2 Device Device BO to B1F B20 to B3F Figure 4 9 Outline of auto refresh processing between CPU No 1 and No 2 4 12 AJOWSW pegeus Add Husn useJje1 one Aq uoneoiunuulo2 Z Lr AJowaw peeus dD Buisn se npoui Ndo ueewjeq suoneoiunuluo9 Ly 4 The area occupied for auto refresh in the CPU shared memory is a total of Setting 1 to 4 When send points are set the first and last addresses of the auto refresh area are automatically displayed as hexadecimal offset values For example the CPU that has send point setting in Setting 1 and 2 has the last address of the first address of the auto refresh area offset value of Setting 2 In Figure 4 10 up to the first address of the auto refresh area 11H are set for CPU No 1 and 2 and the first address of the auto refresh area 214 is set for CPU No 4 When a CPU has setting in Setting 1 only the last address in Setting 1 is the one of the CPU s auto refresh area Change screens Setting 1 Set starting devices for each PLC Transmission range of CPU No 1 Final address of CPU device Final address of CPU shared memory for each CPU Figure 4 10 Display of auto refresh area address 4 13 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 5 The same number of send points must be set for all CPUs in the multiple CPU system If different number of send points is set f
35. The applicable device of head device is B M Y D W RZR The unit of points of CPU specific send range is word Settings should be set as same when using multiple CPU Import Multiple CPU Parameter Check End Se ancel To next page CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM Setting of carry over project Select the project that carries over multiple CPU setting and I O assignment Click Open When Ok is selected the multiple CPU setting and the I O assignment setting data are read from the specified project and the data is overwritten Check the multiple CPU settings When the CPU device for refresh setting is changed input the device number after change Items with should have the same settings for each CPU module After checking the multiple CPU settings or completion of correction select END and close the multiple CPU setting window 8 11 Ndd sseoouqd nid90 Jepoui eoueuuojeg uPiH id90 pow oiseg eui 10 Hues JejeuleJed L z g sJejeureJeg ueis s dO eidnini eui dN Bumes zg From previous page Select PLC system and display the PLC system setting window Check the empty slot points on the PLC system setting window To next page 8 12 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM From previous page Q parameter setting Select I O assignment and display the I O JPLC file PLC RAS Device Program Boot file SFC upset assig
36. The restriction of each CPU module is explained in Table2 12 to Table2 16 a When Basic model QCPU Q00CPU Q01CPU is used Table2 12 Available CPU modules CPU module Model Restrictions Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T C Controller module QO6CCPU V Q06CCPU V B No version restriction Motion CPU 2 Refer to the CPU module manual PPC CPU686 MS 64 PC CPU module PPC CPU686 MS 128 Refer to the CPU module manual PPC CPU852 MS 512 1 The Basic model QCPU whose function version B or later is available 2 When using the Motion CPU install OS software For the OS types and versions refer to the manual of the Motion CPU SJEMIJOS e qe reAe pue eol ep ejqeunBijuoo ez 2 42 2 43 b When High Performance model QCPU is used as CPU No 1 Table2 13 Available CPU modules CPU module Model Restrictions High Performance model QCPU 2 QO02CPU Q02HCPU QO6HCPU Q12HCPU Q25HCPU Function version B Process CPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU No version restriction Universal model QCPU QO3UDCPU QO04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU QO3UDECPU QO4UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU No version restriction Motion CPU 1 Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T Refer to the CPU module manual C Controller module QO6CCPU V Q06CCPU V
37. 091 IAI 322 01 092 __ 8 34 01 09 N hae p 3 E x Mi 9 JSL op x 4Jsz o Ove amp JSE 91 Ove g a 0 S s IBTSWERTRETEI El 3 El gt cg z 8 SEL o1 0ZL 3 3 3 2 E 2 4 2 El ar o 001 E F F Eo 5 E 2 e 44903 2 2 3 com c e o D i Sy oo Ks 8 4a 09 co co co ES J ce 2 8 o m m m COT bE 5 e Si n2 lt EE 10V Y r2 r2 D po E n 8 amp a oc S gt ui D G gt G ke S Lb e ke EH oz mH C 25 S c o 2 16 Table2 5 Restrictions on system configuration available base units extension cables and power supply modules CPU number CPU module1 CPU No 1 CPU module 2 CPU No 2 CPU module 3 CPU No 3 CPU module 4 CPU No 4 Maximum number of 7 extension stages extension stages Maximum number of 65 No of CPUs mounted I O modules Available main base Q38RB unit model Type not requiring power supply module Q52B Q55B Available extension base unt motel Type requiring redundant power supply Q68RB module Available extension QCO05B QC06B QC12B QC30B QC50B QC100B cable model Available power Q63RP Q64RP supply module model Precautions Do not use an extension cable longer than 13 2m 43 31 ft When using an extension cable keep it away from the main circuit high voltage and large current line Set the number of extension stages so as not to be duplicated Although there is no restriction on the connection order of the Q5L T
38. 1 Information stored in the host CPU s operation information area Diagnostic error 2 1H Diagnostic error monisE An error No identified during diagnostics is stored in BIN SDO u The year and month that the error number was stored in the CPU 2H shared memory s 1 address is stored with two digits of the BCD SD1 code Time the The day and time that the error number was stored in the CPU j Time the diagnosis 2 3H diagnostic error shared memory s 14 address is stored with two digits of the BCD SD2 error occurred occurred code The minutes and seconds that the error number was stored in the 4n CPU shared memory s 1 address is stored with two digits of the SD3 BCD code Stores an identification code to determine what error information Error information Error information j P 5H TEMA NO has been stored in the common error information and individual SD4 identification code identification code error information 6H SD5 to Common error Common error The common information corresponding to the error number io information information identified during diagnostic is stored 104 SD15 11H an x F SD16 to Individual error Individual error The individual information corresponding to the error number t o information information identified during diagnostic is stored 1Bu SD26 1Cu Empty Cannot be used 1D4 Switch status CPU switch status Stores the CPU module switch status SD200 1En LED
39. C Controller module and PC CPU module CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 1 Communications between CPU modules In the multiple CPU system various communications between CPU modules are available depending on the communication source and destination CPU module types as shown Table4 1 For communication from the Motion CPU PC CPU module and C Controller module refer to the manuals of each module Table4 1 Communications between CPU modules Communicati Communication destination CPU Communication using CPU shared memory Communication using the instructions Communication between CPUs ENS dul Aut B ing dedicated module usin edicate CPU module o y dedicated to g j refresh program instructions Motion CPU Q172CPUN T Q173CPUN T Motion CPU O O O O Q172HCPU T Basic model Q173HCPU T QCPU cn PC CPU module O O x O C Controller module O O x O High Performance model QCPU Process o CPU Universal model QCPU T n High Q172CPUN T 173CPUN T Performance Motion CPU a i Oo Oo Oo Oo model QCPU Q T Process CPU Q173HCPU T PC CPU module O O x O C Controller module O O x Q Q172CPUN T Universal model Motion CPU Q173CPUN T o o o o otion QCPU Q172HCPU T QOOUCPU Q173HCPU T SDGPM PC CPU module o O x QO2UCPU C Controller module O O x O High Performance model QCPU Process O O x x CPU Universal model Uni model QC
40. Check End Cancel Figure 4 6 Auto refresh setting screen Select either setting the device of each CPU module from CPU No 1 consecutively or setting them with each CPU Set the device range of each CPU module Use the specified points continuously from the set device number a Setting switching and send range for each CPU Refresh range 1 Itis possible to set 4 ranges from Setting 1 to 4 for the refresh setting with the setting switching For example ON OFF data can be set to bit devices and other data can be set to word devices separately 2 In the send range for each CPU the points of the CPU shared memory are set in 2 point units 2 words 2 points in the word device specification and 32 points in the bit device specification Data for which the point is set to O in the send range for each CPU will not be refreshed When refresh is performed for 32 points BO to B1F on CPU No 1 and 32 points B20 to B3F on CPU No 2 the number of send points is 2 for CPU No 1 and 2 for CPU No 2 since 1 point of the CPU shared memory is equal to 16 points of bit devices CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 3 The number of send points is as follows For Basic model QCPU The numbers of send points are 320 words for the Basic model QCPU and 2048 words for the Motion CPU PC CPU module making a total of 4416 points 4416 words for all CPU modules Change screens Setting v hos Send range for each PLC PLC side dev
41. Figure 2 26 Configuration of peripheral devices 2 40 2 41 b For the Built in Ethernet port QCPU WiUniversal model QCPU G Memory card G Ethernet cable 4 if BPC GX Developer GX Configurator 3 LY gt FT S J Memory card 1 PC card adapter O USB cable uuanuuuuuauuuuu 4 2 3 4 lt A Do not format the ATA card by other than GX Developer 73 QCPU User s Manual Hardware Design Maintenance and Inspection For writing into memory card by GX Developer and information on USB cables refer to the operating manual of the GX Developer The available version varies depending on the system configuration gt Section 2 3 Use the following Ethernet cables 10BASE T connection Cables compliant with Ethernet standards category 3 or higher STP UTP cables 100BASE TX connection Cables compliant with Ethernet standards category 5 or higher STP UTP cables In an environment subject to electric noise use shielded twisted pair STP cables Figure 2 27 Configuration of peripheral devices CHAPTER2 SYSTEM CONFIGURATION 2 3 Configurable device and available software Information on devices and software packages used for the system configuration is described in this section 1 CPU modules available for multiple CPU system There are some restrictions on the CPU module model and function version as shown in the table below
42. OFFFH OFFFH Figure 8 16 Range of auto refresh area and user setting area 8 32 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM b Program example of continuous data writing reading using the user setting area from CPU No 2 to CPU No 1 Table8 3 Auto refresh devices used in each CPU module Auto refresh device used in CPU No 2 Auto refresh device used in CPU No 1 M63 M31 Program example Program by which data are continuously written read using the user setting area from the CPU module of CPU No 2 to the CPU module of CPU No 1 CPU No 2 SM400 BIN K4X20 Always ON BIN K4X30 S TO H3E1 H850 D200 K50 Write head data Write completed M31 RST CPU No 1 read completed CPU No 1 M63 FROM H3E1 H850 D100 CPU No 2 Read write flag head data Do F Write head data D4o j Write final data M100 Write completion i bit B N63 CPU No 2 write flag es CPU No 2 write flag K50 J M31 x CPU No 1 read completed Figure 8 17 Program example for continuously writing reading data using the user setting area from CPU No 2 to CPU No 1 8 33 fido SS3901d pue 1d20 pow eoueuuoLieg uBIH Nddo pou dseg eu 104 sejydurexe wesbolg peg useJjeJ ojne Buisn sejduiexe ueJ60ud uoneoiunuuo e g 8 3 2 Program examples for the Universal model QCPU This section explains program examples in the following system configuration given in Figure 8 18 and assi
43. Project drive SampleComment Drive Path C MELSEC GPPW Project name s ample Import Multiple CPU Parameter When multiple CPU parameters are used improperly all the following parameters are overwritten Q Assignment Setting 1 0 Assingment Standard setting PLC system setting Points occupied by empty slot Multiple CPU Settings Execute the multiple CPU parameter diversion Cancel Multiple CPU settings x No of PLE 1 Online module change NoofPic i T Enable online module change with another PLC When the online module change is enabled with another PLC X 1 0 status outside the group cannot be taken Jon z 1 0 sharing when using Multiple CPUs 4 T AI CPUs can read all inputs Operating mode Error operation mode at the stop of PLC ANDER van oa pul F y Communication area setting refresh setting IV All station stop by stop error of PLC2 Change screens Setting4 I Setstarting devices for each PLC Iv All station stop by stop error of PLC3 IV Allstalion stop by stop enor of PLC4 um Eese c send ange GI t Pomp Stet End Stat End Nol a 0000 097 D100 0107 No2 20 000 0013 D108 D127 No3 6l ooaj onos D128 D133 Nod 2 0000 0001 D134 D135 EE Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address
44. Q02UCPU QO3UDCPU Q04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU QO3UDECPU Q04UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU CHAPTERS PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 5 3 Reducing processing time 1 Multiple CPU system processing Access is made between a CPU module and an I O module or intelligent function module through a bus base unit pattern extension cable and this bus cannot be used by multiple CPU modules at the same time If more than one CPU module attempt to use it simultaneously the CPU module attempted access later is placed in Standby status until the processing of the first CPU module is completed In the multiple CPU system this waiting time time of Standby status will cause delay in input and output and increase in scan time 2 Maximum standby time In the multiple CPU system waiting time of the host CPU will reach the maximum when Using the maximum number of CPU modules Using extension base unit s An intelligent function module on an extension base unit has high volume of data Simultaneous accesses are made to a module on the extension base unit where the maximum number of CPU modules is mounted 3 Reducing processing time for multiple CPU system The following methods are available for reducing the processing time in the multiple CPU system Place modules of high access points e g CC Link IE controller network MELS
45. Writing PM Figure 4 48 Operation of writing device data from CPU No 1 to CPU No 2 For details of the multiple CPU high speed transmission dedicated instruction refer to the following manual L gt QCPU Programming Manual Common Instructions 4 52 NddD 01 NdOO Woy ejep eoiep jo Buipeej DunuM EEY suononJisu pejeoipeg ui uoneoiunuuo y 4 4 Multiple CPU Synchronous Interrupt The multiple CPU synchronous interrupt function executes interrupt programs multiple CPU synchronous interrupt programs at the timing of multiple CPU high speed transmission cycle The multiple CPU synchronous interrupt enables synchronization with multiple CPU high speed transmission cycle and communications among CPU modules Also since the multiple CPU high speed cycle is synchronized with the Motion CPU operation cycle using the multiple CPU high speed transmission function allows faster responses to requests from the Motion CPU and sequence pro gram execution synchronized with the operation cycle 1 Multiple CPU synchronous interrupt programs Multiple CPU synchronous interrupt programs are programs using interrupt pointer 145 A program from an interrupt pointer 145 to the IRET instruction corresponds to a multiple CPU synchronous interrupt program To execute multiple CPU synchronous interrupt programs set interrupt permitted status with the EI instruction 2 Execution timing Multiple CPU synchronous interrupt programs are exec
46. aa 29 30 31 32 33 34 35 36 extension 53 54 55 56 57 58 59 60 jJ extension im oo wjwunjwiujurjunjuwuj ulrjoo win uir ju uj l oo Woy Ise Cony Ee Le TT een ce Q r iojmioau i cd e o oloio oj s s o vo o o ol lvo r r 9 9 2 2 2 eS e 2 sere 2 2 2 2 2 ege ee EX Eco e co T elles oo e m e E o T S S o o x o co SiN o E e e s ix L S ololea 9 ol m nN EE o o 3 ied 7rd 38 40 41 42 43 44 extension 61 62 63 extension BET o o myulu ueyueyueypo ow Wy uw w wil cus o 0 r jojm nojur i cda I oj g9 sg SESSEL SE UO tO mim e i gi o o e e e e e e e 2 e e e e s ee Solo oo olla io o lo lo sizi 9 9 Tolo L OUSA YSlO e Si o o ser Ss srl oF see SSF Eae Be NIN 1 i 1 I Error in mounting When the QOOUCPU Q01UCPU and QO2UCPU are used as the CPU module 1 up to third CPU modules can be mounted Therefore the CPU module 4 does not exist When the QOOUCPU Q01UCPU and QO2UCPUCPU are used as the CPU module 1 CPU modules cannot be mounted on the 26th slot or later or 38th slot or later on the following conditions Therfore if a module is mounted on the following conditions an error SP UNIT LAY ERR error code 2124 occurs Maximum number of slots for the QOOUCPU QO01UCPU 25 slots Maximum number of slots for the QO2UCPU 37 slots When the QOOUCPU Q01UCPU Q02U
47. and display the PLC PLC name a RAS Device Program Boot fle SFC O assignment system setting window Label Comment Acknowledge XY assignment si Default End Cancel Q parameter setting Points occupied by empty slot Option Set the occupied points for one empty slot Default 16 points PLC name LC file PLC RAS Device Program Boot file SFC 1 0 assignment Timer limit setting pte 4 100 ms 1ms 1000ms Common pointer No P After 0 4095 High 10 00 ms 0 01ms 100ms speed Points occupied by empty slot 16 _z Points RUN PAUSE contacts Cmm stem interrupt settings RUN X X0 X1FFF fens PAUSE X XO X1 FFF Fixed scan interval Latch data backup operation valid contact 128 100 0 ms 0 5ms 1000ms rS zu El 129 40 0 ms 0 5ms 1000ms Remote reset 130 200 ms 05ms 1000ms Allow TT 131 10 0 ms 0 5ms 1000ms Dutput mode at STOP to RUN gt Previous state Interrupt program Fixed scan program setting Recalculate output is 1 scan later High speed execution r pa Intelligent function module setting bia an Reha m i 5 Interrupt pointer setting scan time proceeds Specify service process time ms 0 2ms 1000ms Module synchronization Specify service process E times 1 10 times execution counts Synchronize intelligent module s pulse up C Settings should be set as same when Execute it while wait
48. cee ee A 20 Mounting position 00 eee eee 3 1 Multiple CPU settings 6 1 N Network module 00 0c eee eee 2 52 No of CPU setting 00000 e ee 6 6 O Online module change 0005 2 48 Online module change setting 6 8 Operating mode at stop error 3 37 6 8 Operating mode setting 6 8 Operation for CPU module stop error 3 37 P Parameter setting 6 1 PC CPU module 0 00 A 20 Precautions Communication made by program 4 44 Communication using auto refresh 4 20 Precautions for system configuration 2 52 Processing time llle 5 1 Program example Continuous data transmission 8 31 8 37 Continuous data writing reading using the user setting area 8 33 8 39 Sending bit and word data 8 30 8 36 PX Developer nanunua nannan 2 49 Q Q series power supply module A 21 ekjupern E EE DE A 21 QSEIDB abre ipee eh ehe A 21 Q3SEIRB 2st ea E a A 21 QIEISB 2th a arena N ang DNUS ous A 21 O5EIB aas aaa a a Pete e EXE A 21 QOEIB nadra es eer a x Pes A 21 QOEIRB 52 Li ERI A bee Sagas A 21 QATSO6EIB ea ato a Hat eats ls bie AR eal ah s A 21 QAOADBZ woe kate ur UNES A 21 QA6ADP A5 LI AGLIB 4 A 21 QAGEIB isc ep ened Sei ets A 21 QnU D FDCPU sos dui Rem Res A 20 R Read instruction 2
49. estas Slot number B g H ei 1 amp te s Y e g io MM I O number falelolols Irz e N vt oO i HO s E Lp Slim type power supply L CPU module 2 module L CPU module 1 Figure 2 4 System configuration example for using Q3 SB Table2 2 Restrictions on system configuration available base units extension cables and power supply modules CPU number CPU1 CPU No 1 Basic model QCPU CPU2 CPU No 2 C Controller module Maximum number of extension stages Extension not allowed Maximum number of 32SB mountable I O Q33SB modules Q35SB Available main base unit model Q32SB Q33SB Q35SB Available power supply module model Q61SP Precautions The slim type main base unit has no extension cable connector The extension base unit and GOT cannot be bus connected 2 6 ndOLOO Ndd000 nd90 Iepoui oiseg usn uoneunBijuoo ueis sS V L z uongeunByuoo uejs S Lc 3 When using the Multiple CPU High speed main base unit Q30DB a System configuration Battery for QCPU Q6BAT Basic model Pc CPU C Controller QCPU module 3 4 5 module 5 Q30 DB type multiple CPU high speed main base unit 1 G Extension cable function module B type extension base unit 2 B type extension base unit 1 1 Asa power supply module use the Q series power supply
50. inir No of PLC Onir NoofPic 4 x x NoofPLC 4 gt m wi wl Host CPU number 10 Host CPU number 10 a vos a yo ra r Whether host CPU number Whether host CPU number is is consistent is checked consistent is checked ER OTT ead No 1 CPU No 2 No 3 CPU No determined by mounting position Point Checking the host CPU number of the multiple CPU system is available when the following CPU modules are used Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172DCPU Q173DCPU 1 Setting of checking the host CPU number When checking the host CPU number of the multiple CPU system set the CPU number of the CPU module where parameters will be written in Multiple CPU settings of the PLC parameter The host CPU number is selected from No specification PLC No 1 PLC No 2 PLC No 3 and PLC No 4 No specification is set by default If No specification is set at Host CPU number the host CPU number of the multiple CPU system is not checked Also setting the host CPU number is not required for all CPUs For example when the multiple CPU system is configured using three CPUs the host CPU number can be set to the CPUs No 1 and No 2 and no setting is made to the CPU No 3 Multiple CPU settings E Ned PLEO Setting host CPU number T7 AICPUs c Mulicle CFU Figh spe I Use mlitle CPU high speed
51. 00 000 4 37 Reducing processing time 5 10 Redundant power extension base unit A 20 Redundant power main base unit A 20 Refresh setting 20 0 05 4 11 6 8 Resetting the multiple CPU system 3 34 3 36 Restricted system area 4 3 4 7 S S PX CHGA S does et eR Aet Es 4 47 O P CHG Lue eed aca shoei ad EE EE 4 47 S P CHGV oid sese 1t tid 4 47 S P DDRD 2 200 0c aee 4 49 S P DDWRi aa ats nite te Sa ed mA TES 4 49 S PB SECSL uu sere ak ele veu pe ex 4 47 SIPI SVS fee etico ed euh t ad eden aa 4 47 S GINT nn IRE RUE beatae eee CER 4 51 Serial number 2 200000000 2 43 Slim type main base unit llus A 20 Slim type power supply module A 21 System configuration Configurable device and available software 0 22 00 e eee 2 42 Configuration of peripheral devices 2 38 Precautions for system configuration 2 52 System recovery procedure 3 39 U User setting area 0 4 3 4 7 W Write instruction s s s sasaa aaaea 4 37 Index 2 WARRANTY Please confirm the following product warranty details before using this product 1 Gratis Warranty Term and Gratis Warranty Range If any faults or defects hereinafter Failure found to be the responsibility of Mitsubishi occurs during use of the product within the gratis warranty term the product
52. 2 O Note4 10 cmm For the High Performance model QCPU or the Process CPU reading data from Restricted system area and Auto refresh area is not also allowed 9 Notes 11 An access executing flag SM390 is unavailable for the Universal model QCPU 4 44 weiBoid Aq Aiowaw pareys 142 Bursn uojesunwwoy 17 AJowaw peeus 142 Buisn se npoui Ndo usemjeg suoNediunwWWwOD Ly e Data writing to other CPU s shared memory Data cannot be written to the CPU shared memory of other CPU with a write instruction Writing data to the CPU shared memory of other CPU No with TO S TO instructions or those using the multiple CPU area device U3En GLJ may result in SP UNIT ERROR error code 2115 f Data writing to host CPU s shared memory 1 Basic model QCPU Data can be written to the host CPU s shared memory with a write instruction 2 High Performance model QCPU or Process CPU Data can be written to the host CPU s shared memory with the S TO instruction not with the instruction using the multiple CPU area device U3En GL Writing data to the host CPU s shared memory with the instruction using the multiple CPU area device U3En GL results in SP UNIT ERROR Error code 2114 3 Universal model QCPU Data can be written to the host CPU s shared memory with a write instruction g Data reading from CPU shared memory 1 Basic model QCPU Data can be read from the host CPU s shared memory with a read instruction 2
53. 2 60 BIF gt 1 2 Mo M3T lt 1 2 M0 M31 ef 2 32 wa WIF gt 2 32 wo WIF lt 2 32 00 D31 Le fi 3 3 3 4 4 4 a Send setting of CPU No 1 b Receive setting from CPU No 1 b Receive setting from CPU No 1 1 Auto refresh setting of CPU No 1 2 Auto refresh setting of CPU No 2 3 Auto refresh setting of CPU No 3 Figure 4 30 Auto refresh setting related to sending and receiving CPU No 1 data lt Flow of sending data from CPU No 1 to other CPUs gt CPU No 1 writes device data set in Auto refresh CPU No 1 send data to the auto refresh area in CPU No 1 at END processing CPU No 1 sends data in auto refresh area of CPU No 1 to CPU No 2 and CPU No 3 in multiple CPU high speed transmission cycle CPU No 2 and No 3 read the received data from CPU No 1 to a device set in Auto refresh CPU No 1 receive area at END processing PLC No 1 PLC No 2 PLC No 3 Multiple CPU high speed transmission area Multiple CPU high speed transmission area Multiple CPU high speed transmission area PLC No 1 PLC No 1 PLC No 1 User free area User free area User free area 2 2 Auto refresh area Auto refresh area Auto refresh area 7 PLC No 2 PLC No 2 PLC No 2 User free area User free area User free area Auto refresh area Auto refresh area Auto refresh area PLC No 3 PLC No 3 PLC No 3 User free area User free area User free area Auto refresh area Auto ref
54. 23 fol Fos Ke en fe o o jojojojojo og o o olo ojo eg o ojo o o o g o ojo jo ojo oO oO oO 4es o1 ozs amp 4c9 o1 029 8 4ez 0z7 4LS 00S z 419 01 009 8 31701007 44v o1 03v 2 449 01 036 2 449 039 z 4dr 0 007 8 4dS 01 099 5 409 01 099 5 5 Q ag 01 0vr 4a o1 ovS 8 J89 01 0v9 o 5 E 8 46t 01 08r 46S 01 08S 8 469 01 089 Li e 2 8 E 8 44v 01 097 348 01 098 349 01 099 ag D l 2 497 91 ory amp 9 499 01 0v9 2 8 J459 01 org o c 2 3 c o Fe o o s e o o o o g 46 0108 5 o o o 5 2 2 2 7 5 o o 42 2109 S D i o b o eo eo 2 2 E p ssa 3 E e La ba E g So Pi Ske 8 8 G E e Je 01 0Z 8 g G B p o fs P G LE 2 5 3 c g js 4L 0100 aso 9 E OFS 5 5 5 3 iS unnm im j 29 2 ERAI GRIC GIG e oo looo s 8 o E GEST S 2 lo kelelele 2 ojo Ejio ojolo 3 o o lo lolojo is WHEN HI 1296 i D 8 E J ae E amp sez 01 ozz a see o oze 8 4er 9 ozv S ci lol JH 22 2 41z o100z NI ALE 01 00 41v 007 o e Eu nin o 2 44L 0103 44z oaz 3 44 o1 03 E S Serm 9 4CL 01 001 4dz o1 022 8 Jae o1 02 D 3 ei e 491 o1 OVE amp 4az o1 0vz amp 4a o1 ove a os n 46L 0 084 amp 46z 01 082 amp 46 01 08 e 9 amp 1 z RRRRBE __ 4Z 091 al azz o 092 _ 8 34 01 09 N mD 3 x Me 9 JSL op x 4Jsz o Ove amp JSE 91 Ove g Oo e c 9 oS 3 3 El 8 Ww 2 5 a a
55. 55 CHAPTERS PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 5 1 to 5 10 5 1 Conceptof Scan TIme eu sue drei D we rtt e Eg c et 5 1 5 2 Factors for prolonged Scan Time nennen 5 3 5 3 Reducing processing Mereenie na a e a a aa E aaa a aa S A 5 10 CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6 1 to 6 9 641 Parameter list Aree rer eese E E A T TAT 6 1 1 Number of CPUs setling 1 ie eee e en de e e es 6 1 2 Operating mode setting nennen nnne nennen nennen nnns nenne 6 1 3 Online module change Setting ccccscceeseneeeeeteeeeeeeeeseeaeeeseaeeeeeeaeeeeeeeeeeeeeeteneeeteaees 6 1 4 I O settings outside of the group sssesssssssesseseeeenee enne nnne nennen 6 1 5 Communication area setting Refresh setting 6 1 6 Control GPU settings x ian neo n co hd e a dede ete doe nente da dU di vas 6 1 7 Multiple CPU synchronized boot up sssesseseeeeeneeenreneenneen renes 6 1 8 Multiple CPU high speed transmission area setting CHAPTER7 PRECAUTIONS FOR USING AnS A SERIES COMPATIBLE MODULES 7 1 to 7 4 7 1 Precautions for use of AnS A series compatible module ccccsccccesssseeeesesteeeeesssteeeeeeeee 7 1 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM 8 1 to 8 39 8 14 Flow chart for Starting Up the Multiple CPU System ccccccscccscccsecssccssccsseeseecssecsseeseesaee 8 1 8 2 Setting Up the Multiple CPU System Parameters 8 3 A 13 8 3 8 2 1 Paramet
56. A series compatible modules can be used for the multiple CPU configuration satisfied with the following all conditions A High Performance model QCPU is used for the CPU No 1 A High Performance model QCPU Motion CPU PC CPU module and C Controller module are used for the CPU No s 2 to 4 If a Process CPU or an Universal model QCPU is used for any one of the CPU No s 1 to 4 the multiple CPU con figuration using AnS A series compatible modules will not be provided Setting of control CPU Set the High Performance model QCPU to the control CPU when usiing AnS A series compatible modules Only one High Performance model QCPU from CPU No s 1 to 4 can be set to the control CPU For setting of the control CPU refer to Section 6 1 6 e npou ejqneduioo sees v suy Jo esn 10J suonneoasJgd pZ 1 2 Example When the control CPU is setup for CPU No 2 Set CPU No 2 to the control CPU for all slots where the AnS A series compatible modules are mounted If setting different CPU as the control CPU among any one of the AnS A series compatible module PARAMETER ERROR error code 3009 occurs and the multiple CPU system does not start Control CPU can be set for each slot y y v Y i CPU 0 1 2 3 4 5 6 10 11 Slot number Power cpu cpu cpu CPU
57. A5LIB A6LB in order from the nearest position of the main base unit Although there is no restriction on the connection order of the Q5 IB and the Q6UIRB check the availability of them by referring to QCPU User s Manual Hardware Design Maintenance and Inspection The extension base units QA1S6L TB QAGL TB and QAGADP ASLTB AGLTB can be extended when the High Performance model QCPU is set as the control CPU of the AnS A series When the Process CPU or the Universal model QCPU is used extension is not allowed The Q6L RB cannot be connected as an extension base unit Connect the OUT connector of an extension base unit and the IN connector of the adjacent extension base unit by an extension cable When 66 modules or more are mounted an error SP UNIT LAY ERR error code 2124 occurs The number of mountable modules includes one CPU module No of CPUs is the number of CPUs set by No of PLC of GX Developer When mounting the Universal model QCPU and the PC CPU module at the same time use the PPC CPU852 MS 512 as the PC CPU module The PC CPU module and C Controller module cannot be mounted together therefore mount either of them The PC CPU module occupies two slots Therefore when the PC CPU module is used the maximum number of I O modules is decreased by 1 from the value indicated in Table2 4 For details of the Motion CPU and PC CPU module refer to the manual of each CPU module When using the QA1S6L1B the QAGADP ASL
58. An area including the auto refresh area can be used as the user setting area when auto refresh is not performed QCPU standard area The area provided for the Universal model QCPU to communicate with other CPUs High Performance QCPU or Process CPU in a multiple CPU system This area includes Host CPU operation information area Restricted system area Auto refresh area and User setting area For each area refer to 1 to 4 Multiple CPU high speed transmission area note4 1 The area to perform communication with other CPU modules in the Multiple CPU system using the Universal model QCPU The Multiple CPU high speed transmission area has auto refresh area and user setting area a Auto refresh area The area used when the Multiple CPU system is automatically refreshed L Section 4 1 3 b User setting area The area for storing data to be sent to other CPU modules by the program Section 4 1 4 Address for CPU shared memory is 10000 or later q2 Note4 1 4 7 The QOOUCPU Q01UCPU QO2UCPU cannot perform the communication by the auto refresh using the multiple CPU high speed transmission area CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4 1 2 Communication by auto refresh using CPU shared memory The following describes communications with auto refresh using auto refresh area in CPU shared memory For the communication by the auto refresh using the multiple CPU high speed transmission area in th
59. CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Table3 4 Mounting position of CPU module When the QOOUCPU Q01UCPU Q02UCPU is mounted on the CPU No 1 cpu o 1 2 3 J Slotnumber Mounting position of CPU module 9x I NPOW ss ydo lt Od z 1d90 lepoui JesueAiu e npoui A ddns 190g Aduie 91d e f1dO YOO z f1dOO epow Jesjenu ainpow Aiddns je og 2 Q Oo 3 1 Mounting Position of CPU Module 3 1 3 When CPU No 1 is Universal model QCPU Aduie 91d Aduie 91d 2MdOO pow Jes1eAiu ajnpow Ajddns 49Moq ajnpow Jejouo2 9 z 1d90 epouw JesJaaluny e npoui ddns 190g ze dOD epow JesJaalun ainpow Ajddns samod zxMdOO pow jesueniun jnpow A ddns 4amod z f1d90 l pow JesueAiu jnpow A ddns 16wog N Aydw9 O1d 2 z 1d90 epow jesuaniuy CP ajnpow A ddns samod ainpow Jej ou02 9 e 1dO YOON T z f1dOO epoul O Jesjenu ainpow Aiddns JaMod ainpow Jejo4uo2 2 zx f1dOO epoui JesaeAu ainpow A ddns je og No of CPUs 4 No of CPUs indicates the value set in the multiple CPU setting of the PLC parameter 2 The QOOUCPU Q01UCPU QO2UCPU can be mounted 4 3 The Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T can be mounted 4 The PC CPU module occupies 2 slots 5 The Motion CPU Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T can be mounted together 6 T
60. CPU system Reference CPU slot CPU No 1 CPU module mounting posi Slot 0 CPU No 2 s CPU slot only no CPU No Section 3 1 2 tion and CPU No Slot 1 CPU No 3 Slot 2 CPU No 4 The number assigned to the right of the i CPU module placed in the rightmost Concept I O number assignment Slot 0 is 00n position in the multiple CPU setting is Section 3 3 1 004 5 The number of mountable mod nm The number of mountable modules per Restriction on number of ules per CPU module is QCPU and per system is restricted Section 2 4 mountable modules restricted depending on the j depending on the module type module type Setting the relations between the CPU Access from CPU module to module and other modules with the All modules can be controlled Section 3 4 other modules PLC parameter control CPU is required Accessible to the High Performance Manuals for Access from GOT Accessible z model QCPU of the specified CPU No GOT Access with instruction using Accessible Only control CPU is accessible Section 3 6 link direct Access range CC Link sys tem master Access to CC Link Accessible Only control CPU is accessible local module manuals Accessible through USB or RS 232 cable or via network Access from peripheral Accessible through USB or RS For access when the Motion CPU PC Gaolion9s i devices 232 cable or via network CPU module or C Controller module is connected refer to the manual of e
61. Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y D W R ZR The unit of points of CPU specific send range is word Settings should be set as same when ti PARE Import Multiple CPU Parameter Q parameter setting PLC name PLC system PLC fie PLC RAS Device Program Boot fie SFC I 0 assignment Timer limi setting Low 100 ms 1ms 1000ms speed High 100 ms 0 1ms 100ms speed Common pointer No P After 0 4095 Points occupied by empty slot 16 7 Points RUN PAUSE contacts RUN X X0 X1FFF r System interrupt settings Interrupt counter start No C 0 768 Fixed scan interval PAUSE X IXO XIFFF backup operation valid 128 100 0 ms 0 5ms 1000ms 129 400 ms 05ms 1000ms Remote reset Allow Output mode at STOP to RUN 130 20 0 ms 0 5ms 1000ms Hiph spoed interrupt setting 131 109 ms 0 5ms 1000ms Previous state C Recalculate output is 1 scan later Floating point arithmetic processing f Perform intemal arithmetic operations in precision Intelligent function module setting Interrupt pointer setting Module synchronization IV Synchronize inteligent modules pulse up 6 7700 0007 m MA T High speed execution APLC IV Use special relay special register iom SM SD1000
62. Controller module cannot be mounted together therefore mount either of them For details of the Motion CPU PC CPU module and C Controller module refer to the manuals of each CPU module ndOLOO Ndd000 nd90 Iepou oiseg Buisn uogeunBiuoo ueis s V L z 2 4 2 When using the slim type main base unit Q3OSB a System configuration G Battery for QCPU Q6BAT Basic mode C Controller QCPU module Slim type power supply input output intelligent function module 1 The slim type main base unit does not have an extension cable connector The extension base unit and GOT cannot be bus connected 2 Asa power supply module use the slim type power supply module Keep the current consumption within the rated output current of the power supply module The Q series power supply module and the redundant power supply module are not available for the power supply module Figure 2 3 System configuration when Q3 SB is used Point When the multiple CPU system is configured using the Basic model QCPU as the CPU No 1 only the C Controller module can be used as the CPU No 2 2 5 CHAPTER2 SYSTEM CONFIGURATION b Outline of system configuration W Slim type main base unit 32 point modules are mounted on each slot Q35SB 5 slots occupied CPU 0 1 2 3 M
63. E PLE Nea date PLE Not data PLE Wad dai The total number of points is upto 13K I Settings should be set as same when Import Multiple CPU Parameter Check End Cancel using multiple CPU Select Auto refresh setting Auto refresh settings screen Auto refresh settings K Sel ect PLC No 1 H Send e Direction of auto refresh is checked uJejs s NdI eldyinw jo jequinu Nd ISOH LVE Settings should bes mex Ea ced Figure 3 39 Direction of auto refresh using multiple CPU high speed transmission area 3 41 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES In the multiple CPU system the following methods are available to read write data between CPU modules e Communications with auto refresh Section 4 1 2 Section 4 1 3 Data reading writing between CPU modules e Communications with programs 3 Section 4 1 4 Writing reading of data among the C Controller module PC CPU module and QCPU in another CPU Reading the Motion CPU shared memory from the QCPU e Control direction with dedicated instructions s Section 1 2 Control direction from the QCPU to the Motion CPU e Communication with dedicated instructions 7 Section 1 3 Writing reading of device data from the QCPU to the QCPU and Motion CPU in another CPU Event issue from the QCPU to the Motion CPU
64. L o gt o n Input module Motion CPU Motion CPU Motion CPU Input module module Y BINPOW ndo Jo uonisog BununojN p e Addition Smet Move to the right Motion CPU Figure 3 11 Addition of Motion CPU when PC CPU module is mounted Ndo sseooug 10 NAOO Iepour eoueuuopied uDIH S L ON Ndo USUM ZVE 3 7 Table3 3 Mounting position of CPU module Slot number iceu 0 1 2 3 Mounting position of CPU module z 9 npouJ Add e npou4 A ddns jewog einpoui A ddns 190g ainpow Jejoguo2 2 ainpow A ddns samod ainpow Ajddns amod 4dw 9Td 4dw oTd ex NdIO ainpow Ajddns samod e npoui A ddns 180g einpou4 A ddns jeog ainpow Aiddns JamMod z JNpow Ndd Add YORON amp NdIO jnpow Ajddns 1 m0q jnpow 1 0 U09 9 jnpow 1 0 U09 9 e npoui K ddns 19 wod e npouJ Jejouuo2 2 e npoui A ddns 19 Mod ainpow A ddns samod ainpow Jejo unuoo 9 ejnpoui A ddns 19 og e npoui A ddns 190g oz 9 pouJ Md lt ainpow Ajddns JamMod e npouJ Jejoguo2 9 s Idd UORON e f1d90 ainpow jddns 4amod ainpow Ajddns je6wog No of CPUs 4 The number of CPUs shows the value set by the multiple CPU setting 4 2 The PC CPU module occupies two slots 3 The High Performance model QCPU and Process CPU can be mounted 4 The High Performance model QCPU
65. No 2 CPU shared memory CPU shared memory Multiple CPU high speed transmission 2 Data transmission to Multiple CPU high speed transmission area of CPU No 1 CPU No 2 area of CPU No 1 i User setting area User setting area Multiple CPU high speed transmission Multiple CPU high speed transmission area of CPU No 1 area of CPU No 2 User setting area User setting area I4 1 Writing with write instruction 3 Reading with read instruction Sequence program Sequence program Execution of write instruction Execution of read instruction Procedure for the CPU No 2 to read device data of the CPU No 1 1 Writes data in the user free area of the multiple CPU high speed transmission area of the CPU No 1 by the write instruction 2 Sends the data in the multiple CPU high speed transmission area of the CPU No 1 to that of the CPU No 2 3 Reads the data in the user setting area of the CPU No 1 to the specified device from the multiple CPU high speed transmission area of the host CPU by the read instruction Figure 4 41 Outline of communication by the program For the write read instruction refer to Section 4 1 4 1 Point Forthe Motion CPU the write read instructions cannot be used For the method to access from the Motion CPU to the multiple CPU high speed transmission area of the CPU shared memory refer to the manual for the Motion CPU The delay time of data transfer with programs using user setting area in mul
66. Not checked Multiple CPU high speed transmission Select whether to use the multiple CPU high speed transmission function or not Refer to Section 4 1 3 Default Selected to use the multiple CPU high speed transmission function 8 19 NddD pouw jesssaiuN eui 10 Bumes Jejeureded zz 8 SJejeureJeg ueis s dO eidnini eui dN Bumes zg Multiple CPU settings Operating mode Error operation mode at the stop of PLC F rf I All station stop by stop error of PLC2 IV All station stop by stop eror of PLC3 IV All station stop by stop error of PLCA Multiple CPU synchronous startup sett Es Target PLC No2 User Not v No2 Iv No3 M No4 Settings should be set as same when using muliple CPU PLENO Wend PLENe 3ecsie PLE Na dece PLE Ne Receive met Sel send device ta the ober PLC From previous page nline module change Enable online module change with another PLC When the online module change is enabled with another PLC HO status outside the group cannot be taken 1 0 sharing when using Multiple CPUs AIl CPUs can read all inputs AII CPUs can read all outputs Multiple CPU high speed transmission area setting Communication area setting refresh setting jV Use multiple CPU high speed transmission CPU specific send r User setting area Auto refresh point Start End point Setting 3072 G10000 813071 O Seti 3072 610000 613071 O Set nafFieceive 3072 G10000
67. One QCPU can concurrently issue up to 32 instructions of Instructions dedicated to Motion CPU and Instructions dedicated to communication between multiple CPUs except for S P GINT Note that multiple instructions are executed in order starting from the first instruction When 33 or more incomplete instructions are identified an OPERATION ERROR error code 4107 occurs Refer to the Motion CPU manual for details on the use of the insructions dedicated to Motion CPU f1dO uono 0 NdOO WO uononjjsur OUD Z v Nda uono N o1 peyeoipep suomnonJjsul uy suoneoiunuulo Zy 4 48 4 3 Communication with Dedicated Instructions 4 3 1 Writing reading of device data from QCPU to Motion CPU The QCPU can write read device data to from the Motion CPU with the multiple CPU transmission dedicated instruction and multiple CPU high speed transmission dedicated instruction Writing reading from the Motion CPU to other CPU modules including the Motion CPU is not allowed Example Using the S DDWR instruction The QCPU device data can be written to the Motion CPU devices QCPU Motion CPU S DDWR instruction x Reading device Writing device Device Device EN Figure 4 46 Operation of S DDWR instruction 1 Multiple CPU transmission dedicated instruction The QCPU can write read device data to from the Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T with the multiple CPU transmission dedicated instruction shown on T
68. Process CPU and Universal model QCPU except QQOUCPU Q01UCPU Q02UCPU can be mounted 5 The Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T can be mounted 6 When the PC CPU module is used in combination with the Universal model QCPU the PPC CPU852 MS 512 can be mounted 3 8 3 1 Mounting Position of CPU Module 3 1 2 When CPU No 1 is High Performance model QCPU or Process CPU CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Mounting position of CPU module p zx 9 npouJ jnpow jnpow faduue i N s fido uonow p Ni jajjouog 9 Ni jajjoquog 9 ay A Old 9 N 3d ainpow 3 s Nd UOHOW s f1dO YOO 19jonuo2 9 s Nd uonoiw 2 sf1dO UOHOW 9 jnpow exNddO p exNdOO p 19 onuo9 2 e fido S e NddO M 2 3 e g exNddO E i e f1d9O g e fId9O a Q 7 ainpow o e npoui jnpow jnpow A ddns 1aModq jnpow A ddns samod A ddns 190g A ddns 190g S ddns 1eog S o O p s 1dO YORON e f1ld90 e f1ld90 e fldoO CPU o 1 ajnpow A ddns 190g 9 z 9 POW fdO cpu 0 4 2 amp einpoui A ddns 160g icu o 1 2 ainpow Jej ou02 9 Ajddns 190g icu o 1 2 ainpow Jej ou02 9 ainpow Jej ou02 9 e npoui Ajddns 190g p fiduie 91d s NdID s NdOO e f1d9O e npoui Kjddns 190g cPU o 1 p s 1d90 s f1dOO s f1id9o0 exMddO cPU o 1 ajnpow A ddns 190g s fido UoN s f1dO YOO ex d
69. Q01UCPU Q02UCPU 34 Us 0 155 Us 120Us 304s 0 420 4s Q03UDCPU QOS3UDECPU 9us 0 162 4s 28 us 21 Us 0 410 4s Q04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU 8 us 0 132 Us 25 Us 20 Us 0 410 4s Q04UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU CHAPTERS PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM c When auto refresh of another CPU occurs during auto refresh processing of a CPU If auto refresh of another CPU occurs during auto refresh processing of a CPU the auto refresh time increases by the time obtained from each the following calculations 1 For Basic model QCPU Extension time 4 x No of reception word points x N6 x No of other CPUs us Use the values in Table5 7 for N6 Table5 7 Time prolonged when processing of other CPU is duplicated N6 Basic model QCPU f System including extension System with main base unit only base unit s QOOCPU Q01CPU 0 54 Us 1 30 Us 2 For High Performance model QCPU Process CPU Extension time No of transmission reception word points x N5 x No of other CPUs us Use the values in Table5 8 for N5 Table5 8 Time prolonged when processing of other CPU is duplicated High Performance model QCPU N5 Process CPU System with main base unit System including extension Univwesal model QCPU only base unit s Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU Q02PHCPU Q06PHCPU Q12PHCPU Q
70. Q26UDEHCPU the driver PPC DRV 02 whose version is 1 02 or later can be used When the PC CPU module is used in combination with the Q10OUDEHCPU Q20UDEHCPU the driver PPC DRV 02 whose version is 1 03 or later can be used 1 When using the Universal model QCPU together use the following Universal model QCPU First 5 digits of the serial number 09072 or later 2 When using a Motion CPU install operating system software on the CPU For models and versions of the operating system software refer to the Motion CPU manual 2 46 SJEMIJOS e qe reAe pue eol ep e jqeunBijuoo ez 2 Precautions when using Q Series I O modules and intelligent function modules a Compatible I O modules All I O modules QXL 1 QYL are compatible with the multiple CPU system They can be used by setting any of CPU No 1 to No 4 as a control CPU b Compatible intelligent function modules 1 The intelligent function modules compatible with the multiple CPU system are those of function version B or later They can be used by setting any of CPU No 1 to No 4 as a control CPU 2 Q Series high speed counter modules QD62 QD62D QD62E compatible with the multiple CPU system are those of function version A or later They can be used by setting any of CPU No 1 to No 4 as a control CPU 3 Q Series interrupt modules QI60 do not have a function version but are supported by the multiple CPU system CPUs No 1 to No 4 can be set up as co
71. QD62D and QD62E No version restric tion for QI60 GX Developer Version 7 10L or later GX Configurator AD Version 1 13P or later GX Configurator DA Version 1 13P or later 4 GX Configurator SC Version 1 13P or later Section 2 3 x Jg GX Configurator CT Version 1 13P or later 4 E i 4 foj Available GX Configurator TI Version 1 13P or later software GX Configurator TC Version 1 13P or later o GX Configurator FL Version 1 13P or later 7i GX Configurator QP Version 2 13P or later amp o GX Configurator PT Version 1 13P or later o z GX Configurator AS Version 1 13P or later F GX Configurator MB Version 1 00A or later a GX Configurator DN Version 1 13P or later 3 To the next page 1 17 Table1 4 Difference from single CPU system continued Item Single CPU system Multiple CPU system Reference CPU slot CPU No 1 CPU module mounting posi CPU slot only Slot 0 CPU No 2 Section 3 1 2 tion and CPU No no CPU No Slot 1 CPU No 3 Slot 2 CPU No 4 The number assigned to the right of the t CPU module placed in the rightmost Concept I O number assignment Slot 0 is 00H position in the multiple CPU setting is Section 3 3 1 004 5 The number of mountable mod The number of mountable modules per Restrictions on number of ules per CPU module is CPU module and per system is Sodium sd i mountable modules restricted depending on the restricted depending on the module
72. Stat Not 10 0000 pos D100 DiO9 noz 10 oooo ooo vo 59 Nas 10 ooo ooa D Dig pooof ooog oj veg Setting of CPU No 1 V Set starting devices for each PLC Change screens Setingl v Send range for each PLC PLC side device Hs Dev starting The auto refresh area Caution Pont Stat End Stet End No2 amp 10 ooo ooog 1 Nos 30 ooo ooog Cco Dg No4 1 0 X ooo oos Setting of CPU No 3 V Set starting devices for each PLC Change screens Setingl _v PLC side device Pont Stat End Stet End Noi 10 ooo 0009 D1i00 D109 LNo2 10 ooo X 009 LDo DS No3 10 oof 009 No4 to ooj QoS Setting of CPU No 2 Change screens Setting 1 Send range for each PLC The auto refresh area Caution V Set starting devices for each PLC Send range for each PLC The auto refresh area Caution Dev stating Poit Stat End Stat Noi 0 000 ooog Dioo Diog No2 30 000 0009 No3 30 X 8000 amp 003 Wo Nos 10f amp 000 A 000 Do DS Setting of CPU No 4 Figure 4 19 Setting of CPU device CPU No 1 Device CPU No 2 Device DO to D9 D10 to D19 D20 to D29 D100 to D109 CPU No 3 Device CPU No 4 Device
73. Target PLC Iv No 1 lv No 2 lv No 3 lv No 4 Figure 4 51 Multiple CPU synchronized boot up setting Set the same Multiple CPU synchronous boot up to all CPUs that constitute the Multiple CPU system When the all CPU modules that constitute the Multiple CPU system do not have the same setting the stop error 3015 will occur 4 55 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES Point The Multiple CPU synchronous startup setting cannot be made for the CPU modules except the Universal model QCPU except the QOOUCPU Q01UCPU QO02UCPU and Motion CPU Q172DCPU Q173DCPU When these modules have been used deselect the relevant CPUs at the Multiple CPU synchronous startup setting For example when using the High Performance model QCPU to CPU No 2 and No 4 deselect No 2 and No 4 Multiple CPU settings No of PLC Online module changef Enable online module change with another PLC Deselect these when using the CPU t Wise puc iuc d Host CPU number 0 status outside the group cannot be taken 10 ide the ke modules except the Universal model 5 VO shaing when using Muticle CPUs 1 QCPU except the QOOUCPU eT AI CPUs can read al inputs QO1UCPU QO2UCPU and Motion smsesemskamessano LT ACU eanit oea i i tiple igh speed transmission area setting Communication area setting refresh setting CPU Q172DCPU Q173DCPU IV Al station stop by stop error of PLC2 F Use multiple CPU high speed tran
74. The same devices can be set for settings 1 to 4 EEG Since 160 points of BO9 to B9F are used in setting 1 BAO or large value must be entered Setting 2 For link relay ELI uas settings like ially dupli i i Change screens Setting3 v Set starting devices for each PLC BO to B9F for setting 1 and Send range for each PLC PLC side device B90 to B10F for setting 3 are PLC The auto refresh area Caution B100 not allowed Point Stat End Stat End B100 BAF BI20 B13F 07 B140 BI7F 4 0 0025 gig0 B1BF Iw J Y The Start and the End addresses are automatically calculated with GX Developer Figure 4 12 Setting of devices at CPU Processing of auto refresh CPU No 1 CPU No 2 Device Device BO BO to to B1F B1F F B20 B20 Set with setting 1 to to B3F B3F A es A n B100 B100 to F to Bo Biz Setwih setting 3 to to B13F B13F Ww S EE A Figure 4 13 Outline of auto refresh processing between CPU No 1 and No 2 4 15 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES Devices of setting 1 to 4 can be set independently for each CPU For example devices of CPU No 1 can be set up as link relays and those of CPU No 2 can be set up as internal relays Refresh setting of CPU No 1 Change screens Setting2 v Set starting devices for each PLC Set starting devices f
75. area and User setting area For each area refer to 1 to 4 6 Multiple CPU high speed transmission area 2Notes 1_ The area to perform communication with other CPU modules in the Multiple CPU system using the Universal model QCPU The Multiple CPU high speed transmission area has auto refresh area and user setting area a Auto refresh area The area used when the Multiple CPU system is automatically refreshed lt gt Section 4 1 3 Kioureui pegeus Ndo pp 2 faouaui paseys ndo Buen sajnpowu nd UBeNaq suopeounumuo y b User setting area The area for storing data to be sent to other CPU modules by the program lt gt Section 4 1 4 Address for CPU shared memory is 10000 or later gt f notes The Q0UCPU QOTUCPU QU2UCPU cannot perform the communication by the auto retesh using the multiple ceu Section title The chapter of the current page can be easily identified by this indication on the The section number and title of the current page can be easily identified Icons Basic model QCPU High Performance model QCPU Universal model Process CPU QCPU Description eM cess Icons indicate that specifications described on the page contain some precau tions A 18 In addition this manual uses the following types of explanations Point In addition to description of the page notes or functions that requ
76. auto refresh area of the CPU No 1 send area at the END processing of the CPU No 1 Sends the data in the auto refresh area of the CPU No 1 send area to the CPU No 2 Reads the received data to the specified device at END processing of CPU No 2 3 CPU No 2 detects the send data setting completion 4 CPU No 2 performs the receive data processing 5 CPU No 2 turns on the receive data processing complete bit M32 Writes the above data 5 to the auto refresh area of the CPU No 2 send area at the END processing of the CPU No 2 Sends the data in the multiple CPU high speed transmission area of the CPU No 2 to the CPU No 1 Reads the received data to the specified device at END processing of CPU No 1 6 CPU No 1 detects that the receive data processing complete bit turns on and turns off the data setting complete bit Figure 4 38 Interlock program example 4 35 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4 1 4 Communication using CPU shared memory by program This section explains communications with programs using CPU shared memory in a multiple CPU system Use the following areas in a CPU shared memory for the communications with programs using CPU shared memory User setting area User setting area in multiple CPU high speed transmission area Host CPU operation information area Restricted system area Auto refresh area User setting area Available for the QCPU Use prohibited area Multiple C
77. be avoided by creating an interlock device at the start of data to be communicated An example for the program which interlocks CPU No 1 and CPU No 2 is shown in Figure 4 43 Transmission side program CPU No 1 Reception side program CPU No 2 MO M2 MO 4 H SET M2 H FROM H3E0 H900 DO K10H 5 FROM H3E1 H900 D10 K1 H Eus ME 8 Operation using from D1 to D9 M2 DO 0 D10 0 1 y y L M1 7 Set send data from D1 to D9 MW SET D10 0 M1 2 y SET D0 0 SET M1 SET M1 SP TO H3E1 H900 D10 Ki M2 3 M2 SP TO H3E0 H900 Do Kio M3 H RST Mi H M3 12 RST M1 DO 0 D10 0 M1 13 HL Pe ai m Lz f RST D10 0 Wt RST D0 0 M2 0 0 Lg g o 8 Te SET M1 SET M1 SP TO H3E1 H900 D10 K1 M3 11 E T H_ SP TO H3E0 H900 DO K1 M4 EF RST M1 RST M2 M0 Read command M4 M1 S TO in execution flag RST M1 M2 M3 S TO instruction completion device 1 2 3 4 5 CPU No 1 sets the send data from D1 to D9 6 CPU No 2 reads the receive data from D1 to D9 0 CPU No 1 turns on the send data setting complete flag D0 0 CPU No 1 writes the send data D1 to D9 to the user setting area in CPU No 1 CPU No 2 reads the send data from the user se
78. but any combinations of the QCPU Motion CPU and PC CPU module according to the system the development efficiency and ease of maintenance of the system can be enhanced b Module control Each CPU module in the multiple CPU system controls the I O module and intelligent function module on the base unit by each slot GX Developer groups the I O modules and intelligent function modules controlled by each CPU module in the multiple CPU system 2 Sequence control and motion control systems can be configured on the same base In a Multiple CPU System consisting of the QCPU and Motion CPU sequence control and motion control can be implemented together to achieve a high level motion system Contro Sequence control Operation switch Operation status display i j lt I badez Servo amplifier eo D lt o D 3 pa zh o g 62 SSCNET Servomotor Servomotor Figure 1 4 Motion system configuration uleis s fido adijjnw jo seunjeay Z4 1 5 Interaction with a motion controller for motion control is enhanced in the Universal model QCPU a Speeding up data transfer between multiple CPUs Maximum 14 k word data and a sequence program can be transferred between multiple CPUs with parallel processing It enables high speed data transfer independent of scan time whic
79. drop of the screw short circuit or malfunction Overtightening can damage the screw and or module resulting in drop short circuit or malfunction When using an extension cable connect it to the extension cable connector of the base unit securely Check the connection for looseness Poor contact may cause incorrect input or output When using a memory card fully insert it into the memory card slot Check that it is inserted completely Poor contact may cause malfunction Shut off the external power supply for the system in all phases before mounting or removing the module Failure to do so may result in damage to the product A module can be replaced online while power is on on any MELSECNET H remote I O station or in the system where a CPU module supporting the online module change function is used Note that there are restrictions on the modules that can be replaced online and each module has its predetermined replacement procedure For details refer to the relevant sections in the QCPU User s Manual Hardware Design Maintenance and Inspection and in the manual for the corresponding module Do not directly touch any conductive part of the module Doing so can cause malfunction or failure of the module When using a Motion CPU module and modules designed for motion control check that the combinations of these modules are correct before applying power The modules may be damaged if the combination is incorrect For detail
80. e S e E E ee ES E EE E e a ESEE o o qN s iojoj alolulojlmw sido c o o SJ S SIRA NIANIA o0 3 5 slots occupied Q68B 8 slots occupied 2nd 5rd 24 25 26 27 28 extension 45 46 47 48 49 50 51 52 extension oo o o w u jufu ju wje juje jejuejujua j foo og a Lrj o9 lei OIS M AJU NINI N M ouo 1 00 tO t0 tO 10 CO cO o o e 2 2 2 e ies e e e e e e e e les A E A re rete 9 9 Sonor otros eui e ma a oj j u o ec o o6 olojajolu oi cqwj joo AN a na oO 9 Wl MO MO wo H m o o o0 o o 3 Q68B 8 slots occupied 2 3d ard 29 30 31 32 33 34 35 36 extension 53 54 55 56 57 58 59 60 jJ extension o0 wjuj ujejejuejujuaj foo wWyuo juU uyeyulu w foo Q r iojmioilu i c i Q ir iojmiou i cda e o oloioj o s s o vo ololo dvo r rt i ee 2 2 2 8 2 2 2 eS 2 2 2 2 2 2 2 S 2 Sy e glisis 2l glalsig 5 2888 28888 m S Qi alesis ee o o oos oconr ME o0 3 Q65B 5 slots occupied zu 37 38 39 40 41 42 43 44 extension 61 62 63 extension o o 1 e ee w ur un ur r rj uwuwjuj joo
81. execution Points occupied by empty slot 16 Points L Floating point arithmetic processing APLE jg Perform intemal arithmetic operations in V Use special relay special register from SM SD 1000 double precision Inteligent function module setting Interrupt pointer setting Module synchronization using multiple CPU Acknowledge XY assignmg Multiple CPU settings T alcru rear Communication area setting refresh setting Fa K WA K Settings should be set as same when using muliple CPU Import Multiple CPU Parameter Check End Cancel Multiple CPU settings No of PLC mandatory item E a ee eS eae Set the number of CPU modules mounted reru on the main base unit with the multiple CPU 1 1 0 sharing when using Multiple CPUs system e Note8 3 All CPUs can read all inputs Operating mode 4 Error operation mode at the stop of PLC T AN CPUs can read all outputs VV Al station stop by st of PLC Communication area setting refresh setting IV All station stop by stop error of PLC2 V All station stop by stop error of PLC3 IV All station stop by stop error of PLCS sri spec sende Change screens Setting1 Setstarting devices for each PLC Caution Offset HEX from starting address of the auto refresh area Refer to
82. extension System with main base unit only base unit s QOOCPU 0 54 1 30 Q01CPU re ne 952 GEG p The CC Link IE controller network cannot use the Basic model QCPU or the Process CPU 5 7 CHAPTERS PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 2 For High Performance model QCPU Notes 3 Process CPU note5 4 Universal model QCPU Extension time No of transmission reception word points x N5 x No of other CPUs u s The number of transmission reception words is the total number of transfer data below LB LX LY SB Link refresh data 16 LW SW Data transferred to file register of memory card LB Ke peel LW SW LB Transfer between data links Note5 5 i LW x2 Use the values in Table5 10 for N5 Table5 10 Time increased by coincident refresh request from a network module of another High Performance model QCPU N5 Process CPU System with main base unit System including extension Univwesal model QCPU only base unit s QO02CPU QO02HCPU Q06HCPU Q12HCPU Q25HCPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU QOOUCPU Q01UCPU Q02UCPU 0 54 Lis 1 304 Q03UDCPU Q04UDHCPU Q06UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU Q03UDECPU QO04UDEHCPU Q06UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU Note5 3 The CC Link IE controller network can only use the High Performance model QCPU whose first 5 digits of serial No is 09012 or lat
83. into a user s device Failure that could have been avoided if functions or structures judged as necessary in the legal safety measures the user s device is subject to or as necessary by industry standards had been provided 4 Failure that could have been avoided if consumable parts battery backlight fuse etc designated in the instruction manual had been correctly serviced or replaced 5 Failure caused by external irresistible forces such as fires or abnormal voltages and Failure caused by force majeure such as earthquakes lightning wind and water damage 6 Failure caused by reasons unpredictable by scientific technology standards at time of shipment from Mitsubishi 7 Any other failure found not to be the responsibility of Mitsubishi or that admitted not to be so by the user 2 Onerous repair term after discontinuation of production 1 Mitsubishi shall accept onerous product repairs for seven 7 years after production of the product is discontinued Discontinuation of production shall be notified with Mitsubishi Technical Bulletins etc 2 Product supply including repair parts is not available after production is discontinued 3 Overseas service Overseas repairs shall be accepted by Mitsubishi s local overseas FA Center Note that the repair conditions at each FA Center may differ 4 Exclusion of loss in opportunity and secondary loss from warranty liability Regardless of the gratis warranty term Mitsubishi shall not be
84. memory card is used operation is not guaranteed 2 The slim type main base unit does not have an extension cable connector The extension base unit and GOT cannot be bus connected 3 Asa power supply module use the slim type power supply module Keep the current consumption within the rated output current of the power supply module The Q series power supply module and the redundant power supply module are not available for the power supply module 4 When the Q8BAT is used for the Universal model QCPU use the connection cable whose connector part displays A For details of connector part of a connection cable refer to the following manual uongeunByuoo ueljs S Lc L gt QCPU User s Manual Hardware Design Maintenance and Inspection 5 For memory cards that can be used with the C Controller module refer to the manual of the C Controller module Figure 2 11 System configuration when Q3L TISB is used Point When the multiple CPU system is configured using the High Performance model QCPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 and 3 High Performance model QCPU Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU C Controller module LON Nd S f1dO SS990Jg JO f1HOO 9pouiJ eoueuuoj9g ubiH Buisn uoneunByuoo uejs S TLZ 2 18 b Outline of system configuration WiSlim type main base unit 32 point module is mounted on each slot Q35SB 5 slots occupied
85. model QCPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 and 3 Motion CPU Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T PC CPU module C Controller module Note that the PC CPU module and C Controller module cannot be mounted together uongeunByuoo ueis S Lc ndOLOO Ndd000 nd90 pow oiseg usn uojesnByuoo ueis s V L z 2 2 2 3 b Outline of system configuration Mi Main base unit 32 point modules are mounted on each slot Q38B 8 slots occupied CPU 0 1 2 3 4 5 6 Tj uns Slot number p al g 82 m E 00 a fe aj pni 3 Blu u uj u tu Bl N t o lt E 2 e S EEES l O number m Sm Pou EC Ecc a H o6 0 r o o E ka v Q series power Empty space of 16 points supply module CPU module 3 1 CPU module 2 CPU module 1 E Extension base unit 32 point modules are mounted on each slot Q65B 5 slots occupied E i 8 9 10 11 12 extension 2 D ma uou um ur lee Ojuj 9 S o o g 2 g S g e e i DIPlo Cle o o Ai mia r i ie o o o0 z Q55B 5
86. module type type Setting the relations between the CPU Access from CPU module to module and other modules with the All modules can be controlled Section 3 4 other modules PLC parameter control CPU is required s Accessible to the Process CPU of the Manuals for Access from GOT Accessible E specified CPU No GOT Access with instruction using f Accessible Only control CPU is accessible Section 3 6 link direct Access range CC Link sys f l tem master Access to CC Link Accessible Only control CPU is accessible local module manuals Accessible through USB or RS 232 cable or via network Access from peripheral Accessible through USB or RS For access when the Motion CPU PC g i devices 232 cable or via network CPU module or C Controller module is connected refer to the manual of each CPU module Clock data used by intelli Clock func Clock data of the Process CPU Clock data of the Process CPU CPU j gent function module QD75 Section 3 8 2 tion is used No 1 is used etc The entire system is reset by resetting CPU module resetting oper The entire system is reset by the Process CPU CPU No 1 dolo ao i ation resetting the Process CPU Resetting CPU No 2 to 4 individually is not allowed For a stop error of the Process CPU of CPU No 1 the multiple CPU system Operation stops CPU modules No 2 to 4 are in MULTI CPU DOWN Error code Operation for CPU module The system stop
87. modules and intelligent function modules When a multiple CPU system includes a Process CPU online module change is allowed The modules controlled by the Process CPU can be changed online The modules controlled by the High Performance model QCPU Motion CPU PC CPU module and Universal model QCPU cannot be changed online Modules changeable online are shown in Table2 17 Table2 17 Modules replaceable online Module type Restriction Input module Output module No restriction I O composite module Analog digital converter module Digital analog converter module Intelligent function module Thermocouple input module Function version C or later Temperature control module Pulse input module b CPU modules To replace a module used with the Process CPU without stopping the system configure a multiple CPU system with the CPU modules given in Table2 18 Table2 18 CPU modules supporting online module change CPU Module Type Model Function Version Serial No High Performance model QO2CPU Q02HCPU QO6HCPU s First 5 digits of serial No 04012 QCPU Q12HCPU Q25HCPU Q02PHCPU Q06PHCPU Q12PHCPU Process CPU Q25PHCPU QO3UDCPU Q04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU No version restriction Universal model QCPU Q26UDHCPU QO03UDECPU QO4UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU Q172CPUN T Q173CPUN T Motion CPU Version A or la
88. mounted The Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU and the Motion CPU Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T cannot be mounted at the same time 11 When the Q8BAT is used for the Universal model QCPU use the connection cable whose connector part displays A For details of connector part of a connection cable refer to the following manual lt QCPU User s Manual Hardware Design Maintenance and Inspection 12 The QA6ADP ASLIB AGLBB is available However when using the QA1S6L B the QAGADP ABLTIB AGLIB cannot be connected Point When the multiple CPU system is configured using the High Performance model QCPU or the Process CPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 to No 4 High Performance model QCPU Process CPU Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T PC CPU module C Controller module Note that the multiple CPU system cannot be configured using the following combinations Combination of the Universal model QCPU except QOOUCPU Q01UCPU Q02UCPUJ and the Motion CPU Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T Combination of the Universal model QCPU except QOOUCPU Q01UCPU QO02UCPU and the PC CPU module PPC CPU686 MS 64 PPC CPU686 MS 128 Combination of the PC CPU module and the C Controller module CHAPTER2 SYSTEM CONFIGUR
89. occurs 6 7 CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6 1 2 Operating mode setting This is set to continue operation of other CPUs where a stopping error has not occurred when an error occurs at other than CPU No 1 The operating mode for the CPU No 1 cannot be changed all CPUs will suspend operations when a stop error is triggered for the CPU No 1 Section 3 10 6 1 3 Online module change setting This setting allows modules to be replaced online when the Process CPU is used lt 7 QCPU User s Manual Hardware Design Maintenance and Inspection 6 1 4 I O settings outside of the group This is set when the input and output X Y for I O modules and intelligent function modules being controlled by other CPUs is to be downloaded to the host CPU lt gt Section 3 4 2 6 1 5 Communication area setting Refresh setting This is set up to automatically refresh the device data on the multiple CPU system lt gt Section 4 1 2 ISl JejeujeJeg L 9 Bunjes pow Buneiedo z 9 92 E For the Basic model QCPU and the Universal model QCPU QOOUCPU Q01UCPU Q02UCPU the online modulechange cannot be set For the High Performance model QCPU and the Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU modules cannot be replaced online To replace modules online when using the Process CPU set Enable online module change with another PLC 6 8 6 1 6 Control CPU settings Sets up the control CPU
90. of the COM instruction refer to the following manual L gt QCPU Programming Manual Common Instructions d Settings required for auto refresh To perform auto refresh setting the number of points to be sent from each CPU module and a device for storing data device for executing auto refresh on Multiple CPU settings in PLC parameter is required 4 25 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 2 Multiple CPU high speed transmission area setting To perform auto refresh in CPU shared memory set the number of points to be sent from each CPU module Send range for each PLC and a device for storing data Auto refresh settings on Multiple CPU settings in PLC parameter a CPU specific send range setting CPU specific send range setting sets the number of points of multiple CPU high speed transmission area that is allocated to the each CPU module which constitutes the Multiple CPU system CPU specific send range setting screen and the setting range are shown below Multiple CPU settings No of PLC Online module change No of PLC Enable online module change with another PLC When the online module change is enabled with another PLC Host CPU number 1 0 status outside the group cannot be taken PLC No 1 xi Z0 sharing when using Multiple CPUs All CPUs can read all inputs Operating mode Error operation mode at the stop of PLC m i Multiple CPU high speed transmission area setting Communicat
91. other than CPU No 1 SD395 1 The USER LED on the front of the QCPU is illuminated when the annunciator F1 turns ON The number of the annunciator that has turned ON will be stored in the special register SD62 t K1 SD395 J SET F1 L Set the CPU No for comparison Figure 3 18 Program for checking host CPU No For checking method of the host CPU No s of the Motion CPU C Controller module and PC CPU module refer to the manuals of each CPU module jnpow NdI JO ON Ndd C 3 19 3 83 Concept of I O number assignment In the multiple CPU system I O numbers are used for interactive transmission between a CPU module and the I O modules and intelligent function modules or between CPU modules 3 3 1 I O number assignment of each module The multiple CPU system is different from the Single CPU system in the position slot of I O number OOH However the concept of the order of allocating I O numbers I O numbers for each slot and empty slots is the same for both types L gt User s Manual Function Explanation Program Fundamentals for the CPU module used 1 Position of I O number 00H a Slots occupied by CPU modules The number of slots set with the PLC parameters multiple CPU settings are occupied by the CPU modules on the multiple CPU system b Positions of I O modules and intelligent function modules I O modules and intelligent function modules are mounted from the right of the slots occupied
92. outside the group cannot be taken 1 0 sharing when using Multiple CPUs T AlI CPUs can read all inputs T AICPUs can read all outputs Multiple CPU high speed transmission area setting Communication area setting refresh setting JV Use multiple CPU high speed transmission CPU specific send rangel PLC Auto refresh point k i 3 U3E3 Set auto refresh setting if it is needed No setting Already set Total 12K points Advanced settings Assignment confirmation The total number of points is up to 12K Import Multiple CPU Parameter ont es Cancel Multiple CPU settings No of PLC No of PLC 4 gt Host CPU number Operating mode 7 Error operation mode at the stop of PLC 2 JV All station stop by stop error of PLC2 I All station stop by stop error of PLC3 JV All station stop by stop error of PLC4 Online module changel T Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs T AII CPUs can read all inputs I ANI CPUs can read all outputs Multiple CPU high speed transmission area setting Communication area setting refresh setting JV Use multiple CPU high speed transmission CPU specific send rangel PLE User setting area Auto refresh Multiple CPU synchronous startup
93. performed during CPU No 1 END process 1 Transfers BO to B1F transmission device data for CPU No 1 to the host CPU shared memory s auto refresh area 4 Transfers data in the CPU No 2 CPU shared memory s auto refresh area to B20 to B3F in the host CPU The processes performed during CPU No 2 END process 2 Transfers B20 to B3F transmission device data of CPU No 2 to the CPU shared memory s auto refresh area 3 Transfers data in CPU No 1 CPU shared memory s auto refresh area to BO to B1F in CPU No 2 Figure 4 5 Operation of auto refresh b Executing auto refresh Auto refresh is executed when the CPU module is in RUN STOP or PAUSE status Auto refresh cannot be performed when a stop error has been triggered in the CPU module If a stop error occurs on one module the other modules without any error will save the data prior to the stop error being triggered For example if a stop error occurs in CPU No 2 when B20 is ON the B20 in CPU No 1 will remain ON as shown in the operation outline in Figure 4 5 c Settings required for auto refresh When auto refresh is carried out it is necessary to set the points to be transmitted by each CPU and the device in which the data is to be stored the device that will perform auto refresh with the PLC parameter s multiple CPU settings Ajowaw pegeus dD Husn useJje1 one Aq uoneoiunuulo2 Zp y Asowaw peeus 1d2 Buisn se npoui Ndo ueewjeq suoneoiunuluo9 Ly 4 10 2 Refresh settings
94. processing 1 Data are written into the user setting area of CPU No 1 with a write instruction CPU No 2 processing 2 A read instruction is used to read data from the user setting area of CPU No 1 to the specified device Figure 4 40 Outline of communication by program For the write read instruction refer to Section 4 1 4 1 Point P For the Motion CPU the write read instructions are not usable For the accessing method from the Motion CPU and PC CPU module to the CPU shared memory refer to each CPU module manual weiBoid Aq Aiowaw pareys 142 Bursn uogeoiunuiuoo Ly AJowaw peeus 142 Buisn se npoui Ndo ueewjeq suoneoiunuluo9 py 4 38 2 Using user setting aera in multiple CPU high speed transmission area The data written to the multiple CPU high speed transmission area of the CPU shared memory of the host CPU by the write instruction is sent to the other CPU in a certain cycle The other CPU reads the receive data from the multiple CPU high speed transmission area of the CPU shared memory by the read instruction The other CPU can read the data of the multiple CPU high speed transmission area of the CPU shared memory at the execution of the instruction which is different from the auto refresh of the CPU shared memory The figure 4 10 shows the outline of operation where the data written to the CPU shared memory of the CPU No 1 using the write instruction is read by the CPU No 2 using the read instruction CPU No 1 CPU
95. shall be repaired at no cost via the sales representative or Mitsubishi Service Company However if repairs are required onsite at domestic or overseas location expenses to send an engineer will be solely at the customer s discretion Mitsubishi shall not be held responsible for any re commissioning maintenance or testing on site that involves replacement of the failed module Gratis Warranty Term The gratis warranty term of the product shall be for one year after the date of purchase or delivery to a designated place Note that after manufacture and shipment from Mitsubishi the maximum distribution period shall be six 6 months and the longest gratis warranty term after manufacturing shall be eighteen 18 months The gratis warranty term of repair parts shall not exceed the gratis warranty term before repairs Gratis Warranty Range 1 The range shall be limited to normal use within the usage state usage methods and usage environment etc which follow the conditions and precautions etc given in the instruction manual user s manual and caution labels on the product 2 Even within the gratis warranty term repairs shall be charged for in the following cases 1 Failure occurring from inappropriate storage or handling carelessness or negligence by the user Failure caused by the user s hardware or software design 2 Failure caused by unapproved modifications etc to the product by the user 3 When the Mitsubishi product is assembled
96. signals that could cause a serious accident Design Precautions In an output module when a load current exceeding the rated current or an overcurrent caused by a load short circuit flows for a long time it may cause smoke and fire To prevent this configure an external safety circuit such as a fuse Configure a circuit so that the programmable controller is turned on first and then the external power supply If the external power supply is turned on first an accident may occur due to an incorrect output or malfunction For the operating status of each station after a communication failure refer to relevant manuals for the network Incorrect output or malfunction due to a communication failure may result in an accident When changing data of the running programmable controller from a peripheral connected to the CPU module or from a personal computer connected to an intelligent function module configure an interlock circuit in the sequence program to ensure that the entire system will always operate safely For program modification and operating status change read relevant manuals carefully and ensure the safety before operation Especially in the case of a control from an external device to a remote programmable controller immediate action cannot be taken for a problem on the programmable controller due to a communication failure To prevent this configure an interlock circuit in the sequence program and determine corr
97. status Nol PLC operation STOP switch RUN No2 PLC operation STOP switch RUN No3 PLC operation STOP switch RUN Present Error MULTICPUDOWN 2001 2 Monitor run stop OPERATION ERROR MULTI CPU DOWN 2001 120 ioca Stop monitor Error Jump Help Error log Error log Clear log Error message Year Month Da MULTI CPU DOWN Error Jump Help Figure 3 37 Error display by PLC diagnosis 3 38 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3 System recovery procedure Observe the following procedures to restore the system 1 Confirm the error derected CPU No and error cause with the PLC diagnostics on GX Developer 2 Remove the error cause 3 Either reset the CPU No 1 or restart the power to the programmable controller power ON OFF ON 3 All CPUs on the entire multiple CPU system will be reset and the system will be restored when CPU No 1 is reset or the power to the CPU is reapplied Jo4Je dois jnpow Nd 104 uoNeJedO OL 3 39 3 11 Host CPU number of multiple CPU system Checking the host CPU number of the multiple CPU system is a function to check whether Host CPU number in Multiple CPU settings of the PLC parameter is identical to the number of the host CPU which is actually mounted The number of the host CPU which is actually mounted is determined by the mounting position of the CPU modules Setting the host CPU number 0 0
98. status CPU LED status Stores the CPU module s LED bit pattern SD201 CPU operation CPU operation 1Fu Stores the CPU module s operation status SD203 status status b Reading of host CPU operation information area 4 2 Other QCPU can use FROM instruction or multiple CPU area device U3En GL to read data from the host CPU operation information area of the host CPU However because there is a delay in data updating use the read data for monitoring purposes operation information area is read from the Motion CPU it will be read as 0 Program Fundamentals for the CPU module used For the Motion CPU 5x to 1Cx of the host CPU s operation information area is not used If 5H to 1Cx of the host CPU s For details refer to the section describing the corresponding special register in the User s Manual Function Explanation 4 6 AJOWSW peJeus Nd VV AJowaw peseys 1d2 Buisn se npoui Ndo ueewjeq suoNediunwWWwOoyD Ly 2 3 4 5 6 Restricted system area The area used by the system of the CPU module OS Auto refresh area The area used when the multiple CPU system is automatically refreshed Section 4 1 2 The points from the address next to the last address in the restricted system area are used for auto refresh User setting area The area for performing communication between CPU modules The points after the ones used for the auto refresh area are used
99. supply module module module module module module module module a z HEN 4 4 4 Control CPU setting PO Q312B Y y Y v y v v Y i 12 13 14 15 16 17 18 19__ lt Slot number Power ans ans Ans Ans Ans supply n i n Set the same CPU module module module module module module module module module module to the control CPU 2 2 2 2 2 2 2 2 Control CPU setting QA1S68B Y Y Y Y Y 20 21 22 23 24 25 26 27 Slot number Power ans ans Ans supply module module module module module module 2 2 2 2 2 Control CPU setting QA1S68B The control CPU setting shown in the illustration represents the following CPU module 1 to 4 CPU number AnS A module 1 to 4 Control CPU s CPU number Figure 7 1 Setting example of control CPU for the AnS A series compatible module CHAPTER7 PRECAUTIONS FOR USING AnS A SERIES COMPATIBLE MODULES 3 Ranges of access to controlled and non controlled modules Table7 1 indicates access range to the controlled and non controlled modules in the multiple CPU system Table7 1 Access range to controlled module and non controlled module Non controlled module I O setting outside of the Controlled group Access target module Disabled Enabled Not checked Checked Input X O x x Read x x Output Y 2 Write O x x Read O x x Buffer memory Write O x x O Accessible x Flnaccessible 4 Preca
100. system configuration functions and communication with external devices that are required when the MELSEC Q series programmable controller is used in the multiple CPU system This manual is composed of the following parts and explains 1 Chapter 1 and 2 Overview and system configuration of the multiple CPU system 2 Chapter 3 3 Chapter 4 5 Chapter 6 4 Chapter 5 6 Chapter 7 7 Chapter 8 Multiple CPU system concept Communications between CPU modules in the multiple CPU system Processing time in the multiple CPU system Parameters used in the multiple CPU system Precautions for use of the AnS series module in the multiple CPU system Startup of the multiple CPU system Before using the equipment please read this manual carefully to develop full familiarity with the functions and performance of the Q series programmable controller you have purchased so as to ensure correct use E Relevant CPU module CPU module Model Basic model QCPU QOOCPU Q01CPU High Performance model QCPU QO2CPU Q02HCPU QO6HCPU Q12HCPU Q25HCPU Process CPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU Universal model QCPU QOOUCPU Q01UCPU Q02UCPU QO3UDCPU Q04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU Q03UDECPU Q04UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU This manual does not include the specifications of the power supply module base unit extension cables
101. the QO3UDECPU QO4UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU and Q26UDEHCPU Generic term for Mitsubishi motion controllers Q172CPUN Q173CPUN Q172HCPU Q173HCPU Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T Q172DCPU and Q173DCPU PC CPU module C Controller module Generic term for MELSEC Q series compatible PC CPU module PPC CPU686 MS 64 PPC CPU686 MS 128 PPC CPU852 MS 512 manufactured by CONTEC Co Ltd Generic term for the QO6CCPU V QO6CCPU V B C Controller modules CPU module model QnU D H CPU Generic term for the QQOUCPU Q01UCPU QO2UCPU QO3UDCPU QO4UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU and Q26UDHCPU Base unit type Base unit Generic term for the main base unit extension base unit slim type main base unit redundant power main base unit redundant type extension base unit and multiple CPU high speed main base unit Main base unit Generic term for the Q3L 1B Q3LISB Q3LIRB and Q3LIDB Extension base unit Generic term for the Q5L B Qe6L IB Q6OIRB QG6LIWRB QA1S6 1B QAGLIB and QA6ADP A5LIB A6LIB Slim type main base unit Redundant power main base unit Another name for the Q3LISB Another name for the Q3LTRB Redundant power extension base unit A 20 Another name for the Q6LTRB Generic term abbreviation Description Multiple CPU high speed main base unit Another name for the Q3LTIDB Base unit model
102. the any CPU module cannot be mounted on the right side of the C Controller module 6 PLC Empty setting An empty slot can be reserved for future addition of a CPU module Select the number of CPU modules including empty slots at No of PLC and set the type of the slots to be emptied to PLC Empty from the right side slot of the mounted CPU module in order in the I O assignment screen of PLC parameter Example When 4 CPU modules have been set in the multiple CPU setting and 2 High Performance model QCPUs and one Motion CPU are to be mounted Mount the High Performance model QCPUs in the CPU slot and slot 0 and the Motion CPU in slot 1 and leave slot 2 PLC Empty Mounting allowed Mounting not allowed CPU o 1 2 lt Slot number CPU o 1 2 Slot number zm a 2 2 o i o o n Power supply module PLC empty Motion CPU PLC empty Motion CPU module Figure 3 10 PLC Empty setting Point P When using the High Performance model QCPU or Process CPU PLC Empty cannot be set between CPU modules To add a CPU module to the system where the PC CPU module is used move the PC CPU module to the right to make room for the CPU module to be added Set slot 2 to PLC Empty y Keep slot 3 empty popu o 1 2 3 4 Slotnumber CPU o 1 2 3 4 lt Slotnumber Power supply module High Performance model QCPU High Performance model QCPU ES a 2 2 o
103. the multiple CPU system power supply ON OFF ON for recovery Recovery is not allowed by resetting the error stopped CPU modules other than CPU No 1 Example For High Performance model QCPU or Process CPU Slot number Control CPU setting gt Resetting is not allowed in the multiple CPU system Doing so will result in MULTI CPU DOWN in all CPUs in the multiple CPU system The overall multiple CPU system can be reset Figure 3 34 Resetting of multiple CPU system Point P Q Itis not possible to reset the CPU modules of No 2 to No 4 individually in the multiple CPU system If an attempt to reset any of those CPU modules during operation of the multiple CPU system a MULTI CPU DOWN error code 7000 error will occur for the other CPUs and the entire multiple CPU system will be halted However depending on the timing in which any of CPU modules other than No 1 has been reset an error other than the MULTI CPU DOWN may halt the other CPUs A MULTI CPU DOWN error code 7000 error will occur regardless of the operation mode All stop by stop error of CPU n continue station set at the Multiple CPU settings screen within the PLC parameter dialog box when any of CPU modules of No 2 to No 4 is reset 37 Section 3 10 3 36 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM
104. to PLC network 3 33 Jedoje eq X9 Jo ebues sseooy ZE 3 8 Clock data used by CPU module and intelligent function module This section shows the clock data used by the CPU module and the intelligent function module 3 8 1 Clock data used by CPU module The following shows the clock data used by the CPU module 1 2 Setting of clock data When using the Universal model QCPU and Motion CPU Q172DCPU Q173DCPU as CPU No s 2 to 4 the clock data set to the CPU module of CPU No 1 is set to the CPU modules except CPU No 1 f Note3 5 When setting the clock data to the CPU modules other than the CPU module No 1 the clock data of the CPU module No 1 is automatically set to them Transmission of clock data The CPU module No 1 sends the clock data to other CPU modules at the following timing The clock data to be sent are year month day day of week time minute and second At power on of Multiple CPU system When turing Multiple CPU system from RESET STOP to RUN At 1 second interval after starting up Multiple CPU system Point Since the CPU module No 1 sets the clock data at 1 second interval error up to 1 second occurs to the clock data of CPU modules other than the CPU module No 1 There are three methods of setting clock data as shown below Setting with GX Developer Setting with programming Setting with time setting function SNTP client Available only for a Built in Ethernet port QCPU Howe
105. transmission area 8 For the TO DTO S TO instruction write instruction and the FROM DFRO instruction read instruction refer to the following manual 3 7 QCPU Programming Manual Common Instructions Note4 8 MOM Process For the High Performance model QCPU or the Process CPU write to the CPU shared memory with TO instruction is not allowed 4 37 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES b Outline of the communication by the program 1 Using user setting area The data written to the CPU shared memory of the host CPU with a write instruction can be read by another CPU using a read instruction Unlike the auto refresh of the CPU shared memory it is possible to read up to date data directly when this instruction is executed An outline of a process where data written in the CPU shared memory of CPU No 1 with an write instruction is read by CPU No 2 using an read instruction is shown in Figure 4 40 CPU No 1 CPU No 2 CPU shared memory CPU shared memory Host CPU operation Host CPU operation information area information area System area System area Auto refresh area Auto refresh area User free area Data written with write instruction User free area 2 Read with read instruction 1 Write with write instruction sequence program sequence program Execution of write instruction Execution of read instruction CPU No 1
106. when the QOOUCPU Q01UCPU Q02UCPU is used 4 extension stages Maximum number of mountable I O modules 65 No of CPUs when the QOOUCPU Q01UCPU is used 25 No of CPUs QO2UCPU is used 37 No of CPUs Available main base unit model Available extension base unit model Q38DB Q312DB Type not requiring power supply module Q52B Q55B Type requiring Q series power supply Q63B Q65B Q68B Q612B module Available extension cable model QCO05B QC06B QC12B QC30B QC50B QC100B Available power supply module model Q61P A1 Q61P A2 Q61P Q61P D Q62P Q63P Q64P Q64PN 1 When the QQOUCPU Q01UCPU and QO2UCPU are used as the CPU module 1 up to second CPU modules can be mounted Therefore the CPU modules 3 and 4 do not exist Precautions 2 27 Do not use an extension cable longer than 13 2 m 43 31 ft When using an extension cable keep it away from the main circuit high voltage and large current line Set the number of extension stages so as not to be duplicated Although there is no restriction on the connection order of the Q5L 1B and the Q6 B check the availability of them by referring to QCPU User s Manual Hardware Design Maintenance and Inspection when both the Q5LB and the Q6LB exist as the extension base unit The QA1S6L1B QA6LB QAGADP ABLTIB AGLIB or QeLTRB cannot be used as the extension base unit Connect the OUT connector of an extension base
107. which human life or property that could be greatly affected such as in aircraft medical applications incineration and fuel devices manned transportation equipment for recreation and amusement and safety devices shall also be excluded from the programmable controller range of applications However in certain cases some applications may be possible providing the user consults their local Mitsubishi representative outlining the special requirements of the project and providing that all parties concerned agree to the special circumstances solely at the users discretion SH NA 080485ENG H QCPU User s Manual Multiple CPU System MODEL QCPU U MA E pols 13JR75 SH NA 080485ENG H 0812 MEE s MITSUBISHI ELECTRIC CORPORATION HEAD OFFICE TOKYO BUILDING 2 7 3 MARUNOUCHI CHIYODA KU TOKYO 100 8310 nde NAGOYA WORKS 1 14 YADA MINAMI 5 CHOME HIGASHI KU NAGOYA JAPA When exported from Japan this manual does not require application to the Ministry of Economy Trade and Industry for service transaction permission Specifications subject to change without notice MITSUBISHI ELECTRIC HEADQUARTERS EUROPEAN REPRESENTATIVES EUROPEAN REPRESENTATIVES EURASIAN REPRESENTATIVES MITSUBISHI ELECTRIC EUROPE B V EUROPE GEVA AUSTRIA INTEHSIS sr MOLDOVA Kazpromautomatics
108. with PC CPU module 4 51 Communications with instructions dedicated to motion CPU 4 47 Consistency check between CPU Modules ee ee hae ee es 6 5 Control CPU settings 000 6 9 CPU shared memory 0020e ee eae 4 3 Auto refresh using CPU shared MEMO vee te ee ep e e 4 8 Communication using CPU shared memory by program 2000s 4 36 E Ethernet i e bd eS A 21 Extension base unit 000 A 20 F Factors for prolonged scan time 5 3 Flow chart Flow chart for starting up the multiple CPU system soei eret ee ee 8 1 Reusing preset multiple CPU settings and I O assignment 8 10 8 23 When creating a new multiple CPU SYSTOM eat uo Sie RAE e e e 8 5 8 17 Function version llle sess 2 42 Index 1 G GO T antt d eei d eee ERWW A 22 GX Configurator llllll elles 2 50 GX Developer 00000 e eae A 21 2 49 H Host CPU operation information area siue uv ec SEL 4 3 4 6 I I O number assignment nananana uaaa 3 20 I O settings outside of the group 3 23 6 8 Instructions dedicated to motion CPU 4 47 Intelligent function module device 4 37 L Link direct device lllsllsssessss 3 30 M Main base unit 2 22205 A 20 Maximum number of extension StageS cse ene fio eee ed 2 4 2 9 MELSECNET H esseeeeeeees A 21 Motion CPU 0
109. 01CPU QO02CPU 0 02ms QO02HCPU Q06HCPU Q12HCPU Q25HCPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU QOOUCPU Q01UCPU QO2UCPU QOSUDCPU Q04UDHCPU Q06UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU QO3UDECPU Q04UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU 0 05 to 0 13 x No of other CPUs ms 0 03ms 0 02ms SWI ueog Jo 1de2uo2 G 5 2 5 2 Factors for prolonged Scan Time The processing time in Multiple CPU Systems is prolonged in comparison with Single CPU Systems when the following functions are used When using the following add the values described later to the values calculated in Section 5 1 Auto refresh of CPU shared memory including multiple CPU high speed transmission function Refresh of CC Link IE controller network 9 Note5 1 and MELSECNET H CC Link automatic refresh 1 Auto refresh of CPU shared memory including multiple CPU high speed transmission function a Auto refresh of shared memory The amount of time required to perform the refresh function set up with the Multiple CPU settings multiple CPU high speed transmission area setting This value is the total amount of time required for writing into the host CPU s CPU shared memory and the time required for reading from other CPUs CPU shared memories These values are added when setting up the refresh settings multiple CPU high speed transmission area setting with the PLC parameter Mu
110. 072 610000 No 4 U3E3 510000 Set auto refresh setting if it is needed No setting Already set Total 12K points Advanced settings Assignment confirmation The total number of points is up to 12K Import Muliple CPU Parameter ot es Camel using multiple CPU Multiple CPU settings No of PLC No of PLC Host CPU number Operating mode f Error operation made at the stop of PLC d v All station stop by stop error of PLC2 IV Use maple CPU Tigh speed ransmesion V All station stop by stop error of v PAA F All station stop by stop error of PLC User setting area Multiple CPU synchronous startup setting Target PLC IV Noi IV No2 IV No3 IV No4 Settings should be set as same when using multiple CPU Online module change T Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs T All CPUs can read all inputs AlI CPUs can read all outputs Muliple CPU high speed transmission area setting Communication area setting refresh setting point K 7 0 No point Start End 3 U3E0 3072 610000 613071 3 3 U3E3 310000 8613071 Set auto refresh setting if it is needed No setting Already set Total 12K points Advanced
111. 1 A PARAMETER ERROR error code 3012 3015 will occur in the host CPU if they do not match When a stop error occurs at CPU No 1 STOP to RUN is not allowed as a MULTI CPU DOWN error code 7000 error will occur in the host CPU No consistency check between CPU modules 1 The Universal model QCOU checks consistency of multiple CPU parameters among the CPU modules A PARAMETER ERROR error code 3015 will occur in the host CPU if they do not match Point After multiple CPU system parameters unavailable with the Motion CPU are changed for the QCPU or PC CPU module in a multiple CPU system including a Motion CPU be sure to reset the QCPU for CPU No 1 or turn off and on the programmable controller system Otherwise the QCPU or PC CPU module checks consistency between CPU modules with multiple CPU system parameters of the Motion CPU causing a PARAMETER ERROR error code 3012 6 5 6 1 1 Number of CPUs setting 1 No of PLC CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM The number of CPU modules to be used on a multiple CPU system are set at the PLC parameter s Multiple CPU settings screen in the PLC parameter dialog box Multiple CPU settings fo of PLE s No of Puc Operating mode Error operation mode at the stop of PLC V All station stop by stop error of PLC2 All station stop by stop error of PLC3 All station stop by stop error of PLC4 JSettin
112. 1000ms Remote reset 130 206 ms D 5ms 1000ms T Allow Output mode at STOP to RUN Previous state Interrupt program Fixed scan program selling 3 C Recalculate output is 1 scan later T High speed execution 131 10 0 ms 0 5ms 1000ms r P int dit nee a SEC elis bun A c A 10 Interrupt pointer setting scan time proceeds C Specify service process time ms 0 2ms 1000ms Module synchronization V Synchronize inteligent modue spukeup Speci sevice process times 1 10 times Settings should be set as same when Execute it while waiting for constant scan setting using multiple CPU Ea DO Acknowledge XY assignment Defaut Check End Cance Q parameter setting Check the I O assignment settings and basic PLC name PLC system PLC file PLE RAS Device Program Boot fle SFC 1 0 assignment settings in the 1 0 assignment setting window 100 Assignment Select Detailed setting and display the detail setting window Detailed setting PLCIEmpty Input 16points 16points 16points 16points Assigning the I O address is not necessary as the CPU does it automatically Leaving this setting blank will not cause an error to occur Base mode C Auto C Detail 8 Slot Default 12 Slot Default Lk hirer gate Import Multiple CPU Parameter Read P
113. 2 o lt o o oa Basic model Motion CPU module module Added Motion CPU Figure 3 7 PLC Empty setting between CPU modules CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Table3 2 Mounting position of CPU module cpu o 1 2 Slotnumber Mounting position of CPU module dwe 91d Ndo Jepoui oiseg einpoul A ddns 190g ainpow 3 1 Mounting Position of CPU Module 3 1 1 When CPU No 1 is Basic model QCPU ZEN Jejoguo2 2 Ndo a S npoui ainpow jddns samod einpoui A ddns 190g ainpow Ajddns samod Nd UOHOW NddO jepow oiseg a npow A ddns 190g ainpow Jejouo2 2 a npow A ddns 190g e npoui A ddns 190g ainpow Jej oju02 9 Ndo O jepow oiseg einpoui A ddns 190g ainpow ae B Ndo pow oiseg jnpow A ddns 190g NddO O pow oiseg einpoui jddns 190g No of CPUs No of CPUs indicates the value set in the multiple CPU setting of the PLC parameter 2 The PC CPU module occupies 2 slots 1 3 When mounting a PC CPU module to slot 0 in the future do not mount any module to slot 1 4 When mounting a PC CPU module to slot 1 in the future do not mount any module to slot 2 3 5 3 1 2 When CPU No 1 is High Performance model QCPU or Process CPU The mounting position of each CPU module is shown in Table3 3 1 Mounting position of High Performance model QCPU or Process CPU Up to four modules of High Perfo
114. 2 SYSTEM CONFIGURATION 4 Precautions for using QCPU of function version A When the multiple CPU system has been configured using a QCPU of function version A an error occurs and the multiple CPU system is not started Errors shown in Table2 25 will occur and the multiple CPU system will not start up if function version A High Performance model QCPUs and High Performance model QCPU Process CPU are used on a multiple CPU system If any of the errors shown in Table2 25 are displayed after executing the CPU diagnosis function of GX Developer Version 6 or later replace the High Performance model QCPU of function version A with that of a function version B Table2 25 List of operations for each case CPU No 1 CPU Nos 2 to 4 Status of CPU No 1 Status of CPU Nos 2 to 4 High Performance model QCPU of function version A High Performance model QCPU of function version A UNIT VERIFY ERR error code 2000 SP UNIT LAY ERR error code 2125 High Performance model QCPU of function version A High Performance model QCPU Process CPU of function version B UNIT VERIFY ERR error code 2000 MULTI EXE ERROR error code 7010 High Performance model QCPU Process CPU of function version B High Performance model QCPU Process CPU of function version B High Performance model QCPU of function version A High Performance model QCPU Process CPU of function version B MULTI EXE ERROR error
115. 25PHCPU QO0UCPU Q01UCPU Q02UCPU 0 54s 1 3045 Q03UDCPU Q04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU Q03UDECPU Q04UDEHCPU Q06UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU 5 6 eu ueog peBuojoJd 104 suojoe4 Z S 2 Refresh of CC Link IE controller network Notes 2 and MELSECNET H a Refresh time of CC Link IE controller network and MELSECNET H The amount of time required for performing the refresh between the QCPU and the CC Link IE controller network or MELSECNET H network module For refresh time of CC Link IE controller network and MELSECNET H refer to the following manual L gt CC Link IE Controller Network System Reference Manual gt Q Corresponding MESLECNET H Network System Reference Manual b Calculation of refresh time In a multiple CPU system when refresh is requested from a network module of another CPU coincidentally the refresh time increases by the time obtained from each of the following calculations 1 For Basic model QCPU Extension time 4 x No of transmission reception word points x N6 x No of other CPUs u s The number of transmission reception words is the total number of transfer data below LB LX LY SB 16 Link refresh data LW SW Use the values in Table5 9 for N6 Table5 9 Time increased by coincident refresh request from a network module of another CPU N6 Basic model QCPU System including
116. 3 2 4 3 1 3 3 1 3 3 2 3 4 1 3 4 2 3 8 3 9 3 10 4 1 1 4 1 2 4 1 3 6 1 6 1 1 7 1 8 1 8 2 2 8 2 3 8 2 4 8 3 1 8 3 4 Appendix 1 1 Aug 2005 SH NA 080485ENG C Partial correction GENERIC TERMS AND ABBREVIATIONS Section 2 1 Apr 2007 SH NA 080485ENG D Universal model QCPU model addition Revision involving Universal model QCPU serial No 09012 Model addition QO2UCPU QO3UDCPU QO4UDHCPU Q06UDHCPU Q61P QA65B QA68B Partial correction SAFETY PRECAUTION ABOUT MANUALS GENERIC TERMS AND ABBREVIATIONS Section 1 1 1 2 1 3 2 1 1 2 1 2 2 1 3 2 2 2 3 2 4 3 1 1 3 1 2 3 1 3 Chapter 4 Section 4 1 4 1 1 4 1 2 4 1 3 4 1 4 4 1 5 4 3 2 5 1 5 2 6 1 6 1 3 6 1 4 6 1 7 6 1 8 7 1 8 1 8 2 1 8 2 2 Aug 2007 SH NA 080485ENG E Model addition QAGADP Partial correction GENERIC TERMS AND ABBREVIATIONS Section 1 1 1 2 1 3 2 1 1 2 1 2 2 1 3 2 2 2 3 3 1 3 1 2 3 1 3 3 3 1 3 8 4 1 4 1 2 4 2 1 4 3 1 8 2 2 Appendix 1 1 Mar 2008 SH NA 080485ENG F Universal model QCPU model addition Model addition Q13UDHCPU Q26UDHCPU Partial correction GENERIC TERMS AND ABBREVIATIONS Section 1 1 1 1 2 1 3 2 1 1 2 1 2 2 1 3 2 3 2 4 3 1 3 1 1 3 1 2 3 1 3 Chapter 4 Section 4 1 2 4 1 3 4 1 4 4 1 5 4 2 1 4 3 1 4 4 4 5 5 1 52 5 3 6 1 6 1 8 7 1 8 1 8 2 1 8 2 2 8 3 1 8 3 2 Addition Section 4 3 3 Japanese manual version SH 080475 H
117. 3 10 Operation for CPU module stop error The entire system will behaves differently depending whether a stop error occurs in CPU No 1 or any of CPU No 2 to No 4 in the multiple CPU system 1 When a stop error occurs at CPU No 1 A MULTI CPU DOWN error code 7000 error occurs at the other CPUs and the multiple CPU system will be halted when a stop error occurs at the CPU No 1 s Point on the next page for details 2 When a stop error occurs at CPU other than No 1 Whether the entire system is halted or not is determined by the multiple CPU setting s Operating Mode setting when a stop error occurs in a CPU other than CPU No 1 The default is set for all CPUs to be stopped with a stop error When you do not want to stop all CPUs at occurrence of a stop error in a specific CPU module remove the check mark that corresponds to the CPU No so that its error will not stop all CPUs Multiple CPU settings No of PLC Online module change No of PLC EE Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs Operation mode sere 7 AII CPUs can read all inputs MIAII station stop by stop error of PLC n nE Error operation mode at the stop of PLC AIICPUs can read all outputs Vv Communication area setting refresh setting All station stop by stop error of PLC n setting V
118. 4 data No 3 ransmission data ji Maximum No 2 i d ICPU No 4 reception D CPU No 4 2K words transmission data T gt ER S N mei data No 3 No 3 Setting 4 CPU No 4 Y F A 4 transmission data MO 4 No 4 X CPU No 1 EN E ES transmission data Se x x ilo DE cou No 2 reception br ES data No 4 m bas xYeru No 3 reception Sig data No 4 S A CPU No 4 reception A data No 4 Figure 4 16 Outline of auto refresh operations using 4 ranges nocas ED Since the number of CPU modules that can be mounted is up to 3 when using the Basic model QCPU QOOUCPU QO1UCPU Q02UCPU there is no CPU No 4 4 17 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES Point The followings are available when selecting the method of setting devices with each CPU optionally The order of the send range for each module can be changed since devices can be set individually The system scan time can be reduced since it is possible to set for not performing unnecessary refresh Example 1 When changing the order of send range for each CPU module The following shows the example performing auto refresh between High Performance model QCPU of CPU No 1 and Motion CPU of CPU No 2 By setting devices optionally it is possible to match the device of Performance model QCPU to the fixed device in Motion CPU Change screens Setting v IV Set starting devices for each PLC Ch
119. 50 Rubzowskaja nab 4 3 No 8 Fax 33 0 1 55 68 57 57 BA 71000 Sarajevo PL 32 083 Balice RU 105082 Moscow MITSUBISHI ELECTRIC EUROPE B V IRELAND Phone 387 0 33 921 164 Phone 48 0 12 630 47 00 Phone 7 495 545 3419 Irish Branch Fax 387 0 33 524 539 Fax 48 0 12 63047 01 Fax 7 495 545 3419 Westgate Business Park Ballymount AKHNATON BULGARIA Sirius Trading amp Services st ROMANIA NPP URALELEKTRA RUSSIA IRL Dublin 24 4 Andrej Ljapchev Blvd Pb 21 Aleea Lacul Morii Nr 3 Sverdlova 11A Phone 353 0 1 4198800 BG 1756 Sofia RO 060841 Bucuresti Sector 6 RU 620027 Ekaterinburg Fax 353 0 1 4198890 Phone 359 0 2 817 6004 Phone 40 0 21 430 40 06 Phone 7 343 353 2745 MITSUBISHI ELECTRIC EUROPE B V ITALY Fax 359 0 2 97 44061 Fax 40 0 21 430 40 02 Fax 7 343 353 2461 aa INEA CR d o o CROATIA Craft Con amp Engineering d o o SERBIA SOM R Losinjska 4 a Bulevar Svetog Cara Konstantina 80 86 Fendi un hiuc MI HR 10000 Zagreb SER 18106 Nis one Phone 385 0 1 36940 01 02 03 Phone 381 0 18 292 24 4 5 MIDDLE EAST REPRESENTATIVES Fax 39 039 60 53 312 Fax 385 0 1 36 940 03 Fax 381 0 18 292 24 4 5 TERRI ISRAEL ADLERA ELECTRIC EUROPE B V SPAIN AutoCont CS s r o CZECH REPUBLIC INEA SR d o o SERBIA 24 Shenkar St Kiryat Arie panish Branch Technologick 374 6 Izletnicka 10 ahi Carretera de Rubi 76 80 g 1L 49001 Petah Tiqva A C2 708 00 Ostrava Pustkovec SER 113000 Smeder
120. 71UC24 R4 CC Link master local module A1SJ61QBT11 A1SJ61BT11 AJ61QBT11 AJ61BT 11 Modem interface module A1SJ71CMO S3 ME NET interface module A1SJ71ME81 1 Only a multidrop link function is available Computer link and printer functions are not available c Modules that require instruction rewriting Dedicated instructions for the special function modules listed in Table7 4 cannot be used Rewriting them using the FROM TO instruction is required Table7 4 List of modules that require instruction rewriting Module Name Type High speed counter module MELSECNET MINI S3 A1SD61 A1SD62 A1SD62D S1 A1SD62E AD61 AD61S1 A1SJ71PT32 S3 A18J71T32 S3 Positioning module A1SD75P1 S3 P2 S3 P3 S3 AD75P1 S3 P2 S3 P3 S3 ID module A1SJ711D1 R4 A1SJ711D2 R4 d Modules which can use multidrop link function only The computer link multidrop link module A1SJ71UC24 R4 can use the multidrop link function only Computer link function and printer function are not available CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM This Chapter explains the standard start up procedures for the multiple CPU system 8 1 Flow chart for Starting Up the Multiple CPU System Parameters should be preset and sequence programs should be prepared in advance gt Section 8 2 Section 8 3 For parameter setting and program creation of the Motion CPU C Cont
121. 72HCPU T Q173HCPU T Q172DCPU Q173DCPU C Controller module PC CPU module manufactured by CONTEC CO LTD QO6CCPU V Q06CCPU V B PPC CPU686 MS 64 PPC CPU686 MS 128 PPC CPU852 MS 512 Choose the CPU modules suitable for the system size and application to configure the system Some combinations of CPU modules in Table 1 1 cannot be used Refer to Section 3 1 for combinations of configurable CPU modules 1 For further information on PC CPU module consult CONTEC Co Ltd Tel 81 6 6472 7130 For details of the Motion CPU C Controller module and PC CPU module refer to the manuals of each CPU module CHAPTER1 OUTLINE 3 Method for controlling I O module and intelligent function module It is necessary to set control CPU setup which CPU modules are to control which I O modules and intelligent function modules with a multiple CPU system 41 Slot number oooo00 000000 o ZLANANAVAN nj ssssssssssssszz AA AAA AAA I AAV AVA AN aN AVA E EJIEEEEEEEEEEEEEEEJ ES Ik v UCU m je ot e Control CPU setting 2 Control with CPU module 1 Control with CPU module 2 Figure 1 2 Setting of control CPU 2 Indicates the grouping configuration on the GX Developer 1 on the CPU module indicates CPU No 1 and 1 on
122. A62P A63P A68P A61PEU and A62PEU power supply modules Redundant power supply module Generic term for the Q63RP and Q64RP redundant power supply modules Network MELSECNET H Abbreviation for the MELSECNET H network system Ethernet Abbreviation for the Ethernet network system CC Link Abbreviation for the Control amp Communication Link Memory card Memory card Generic term for the SRAM card Flash card and ATA card Generic term for the Q2MEM 1MBS Q2MEM 2MBS Q3MEM 4MBS and SRAM card Q3MEM 8MBS SRAM cards Flash card Generic term for the Q2MEM 2MBF and Q2MEM 4MBF Flash cards Generic term for the Q2MEM 8MBA Q2MEM 16MBA and Q2MEM 32MBA ATA ATA card cards Others GX Developer Product name for SWLJD5C GPPW E GPP function software package compatible with the Q series PX Developer Product name for SWLJD5C FBDQ process control FBD software package QA6ADP Abbreviation for the QA6ADP QA conversion adapter module A 21 Generic term abbreviation Description Extension cable Generic term for the QCO5B QCO6B QC12B QC30B QC50B and QC100B extension cables Tracking cable Battery Generic term for the QC10TR and QC30TR tracking cables for the Redundant module Generic term for the Q6BAT Q7BAT and Q8BAT CPU module batteries Q2MEM BAT SRAM card battery and Q3MEM BAT SRAM card battery GOT Generic term for Mitsubishi Graphic Operation Ter
123. ATION b Outline of system configuration 32 point modules are mounted on each slot WE Main base unit Q312B 12 slots occupied S a E 3 E 5 2 11 O number Abb 0100L 10 330103 dd 9 09 dd 0 0V 36 0 08 AZ 0109 AS 010r Ae 0 02 Al 0100 oooooo CPU module 4 oooooo CPU module 3 oooooo I CPU module 2 oooooo CPU module 1 Q series power supply module 2 1 System configuration 2 1 2 System configuration using High Performance model QCPU or Process CPU as CPU No 1 32 point modules are mounted on each slot E Extension base unit 1st Q612B 12 slots occupied S c t c E ojojojojo fepoyeye olo SER
124. Accessible through USB RS Ethernet cables or via networks Access from peripheral 6 For access when the Motion CPU PC 232 or Ethernet cables or via Section 2 2 devices CPU module or C Controller module is networks connected refer to the manual of each CPU module Clock data used by CPU Clock data of the Universal model Not available 7 Section 3 8 1 modules No 2 to No 4 QCPU CPU No 1 is used Clock func ti Clock data used by intelli lon Clock data of the Universal Clock data of the Universal model i gent function module QD75 Section 3 8 2 eic model QCPU is used QCPU CPU No 1 is used The entire system is reset by resetting The entire system is reset by the Universal model QCPU CPU No CPU module resetting oper aion resetting the Universal model 1 Section 3 9 i QCPU Resetting CPU No 2 to 4 individually is not allowed For a stop error of the Universal model QCPU of CPU No 1 the multiple CPU system stops CPU modules No 2 to 4 are in MULTI CPU DOWN Error code Operation for CPU module A Operation Hnara The system stops 7000 status Section 3 10 For a stop error occurred in any of CPU No 2 to 4 the operation depends on the parameter setting of Operation mode It is possible to choose whether to syn chronize the boot up of CPU modules Multiple CPU system syn f z Not available in the Multiple CPU system or not The Section 4 5 chronized boot up
125. All station stop by stop error of PLC2 cvs ERNST Ub EE EE All station stop by stop error of PLC n V Al station stop by stop error of PLC3 THIS Not all station stop by stop error of PLC n setting S3seseebrsee ero of AS PLC Autorefeshares Caution Dev stating Point Start End Stat End Not No 2 I No3 No 4 I Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y D W R ZR The unit of points of CPU specific send range is word Settings should be set as same when Import Multiple CPU Parameter Check End using multiple CPU Figure 3 35 Operation setting for stop error a When All station stop by stop error of CPU n is set When a stop error occurs in the CPU module for which All station stop by stop error of CPU n has been set a MULTI CPU DOWN error code 7000 error occurs for the other CPU modules and the multiple CPU system will be halted C gt POINT on the next page for details b When Not all station stop by stop error of CPU n is set When a stop error occurs in the CPU module for which All station stop by stop error of CPU n has not been set a MULTI EXE ERROR error code 7010 error occurs in all other CPUs but operations will continue 3 37 Joe dois ejnpoui Add 104 uonejedO OL
126. B When the C Controller module is used in combination with the Universal model QCPU Q13UDHCPU Q26UDHCPU and Built in Ethernet port QCPU the C Controller module whose serial number first five digits is 10012 or later can be used PC CPU module 2 PPC CPU686 MS 64 PPC CPU686 MS 128 PPC CPU852 MS 512 Refer to the CPU module manual 1 When using the Motion CPU install OS software For the OS types and versions refer to the manual of the Motion CPU 2 When using the High Performance model QCPU together use the following High Performance model QCPU Function version B with the first 5 digits of the serial number 03051 or later CHAPTER2 SYSTEM CONFIGURATION c When Process CPU is used as CPU No 1 Table2 14 Available CPU modules CPU module Model Restrictions High Performance model QCPU QO02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU Function version B Process CPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU No version restriction Universal model QCPU QO3UDCPU Q04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU Q0SUDECPU QO4UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU No version restriction Motion CPU Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T Refer to the CPU module manual C Controller module QO6CCPU V Q06CCPU V B When the C Controller module is used in combination with the Un
127. B and the Q6RLIB check the availability of them by referring to QCPU User s Manual Hardware Design Maintenance and Inspection The QeL IB QA1S6L IB QA6LIB or QA6ADP ASLIB AGLIB cannot be connected as an extension base unit Connect the OUT connector of an extension base unit and the IN connector of the adjacent extension base unit by an extension cable When 66 modules or more are mounted an error SP UNIT LAY ERR error code 2124 occurs The number of mountable modules includes one CPU module No of CPUs is the number of CPUs set by No of PLC of GX Developer When the redundant base unit is used bus connection is not available for the GOT When the redundant power main base unit is used the Motion CPU and PC CPU module cannot be used When the redundant power main base unit is used the Motion CPU PC CPU module and C Controller module cannot be used 2 17 CHAPTER2 SYSTEM CONFIGURATION 3 When using the slim type main base unit Q3OSB a System configuration gt High Performance C Controller model QCPU module 4 5 Q Battery for QCPU Q6BAT Universal model 2 GO7BAT SET QCPU 4 Slim type power supply input output intelligent function module 1 One memory card is installed Select an appropriate memory card from the SRAM Flash and ATA cards according to the application and capacity When the
128. CPU Q02UCPU is used Table2 16 Available CPU modules CPU module Model Restrictions Universal model QCPU High Performance model QCPU QO3UDCPU Q04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU QO3UDECPU QO4UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU QO02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU No version restriction Function version B or later Process CPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU No version restriction Motion CPU Q172DCPU Q173DCPU Refer to the CPU module manual C Controller module QO6CCPU V Q06CCPU V B When the C Controller module is used in combination with the Universal model QCPU Q13UDHCPU Q26UDHCPU Built in Ethernet port QCPU the C Controller module whose serial number first five digits is 10012 or later can be used When the C Controller module is used in combination with the Universal model QCPU Q10UD E HCPU Q20UD E HCPU the C Controller module whose serial number first five digits is 10012 or later can be used PC CPU module PPC CPU852 MS 512 When the PC CPU module is used in combination with the Universal model QCPU QO3UDCPU Q04UDHCPU Q06UDHCPU the driver PPC DRV 02 whose version is 1 01 or later can be used When the PC CPU module is used in combination with the Universal model QCPU Q13UDHCPU Q26UDHCPU Q03UDECPU Q04UDEHCPU QO6UDEHCPU Q13UDEHCPU
129. CPU can be connected to GX Developer through a bus cable by installing GX Developer into the PC CPU module lt gt GX Developer operating manual 2 Forthe Basic model QCPU and Universal model QCPU it is the RUN STOP RESET switch 3 For the Basic model QCPU and Universal model QCPU it is the RUN STOP RESET switch 9 Notes 1 For the Basic modPel QCPU USB cables are not usable For the QO2CPU USB cables are not usable 8 1 8 2 From previous page Writing parameter and program tothe Motion CPU sd 57 Manual of the Motion CPU Writing parameter and program tothe C Controller module s Manual of the C Controller module Writing parameter and program to the PC CPU modue J L7 Manual of the PC CPU module SCR ETE e pis rs Set RUN STOP switch of all CPU modules to the RUN position RUN STOP switch setting for all CPUs Y PT rn Set RESET L CLR switch of the CPU module in CPU No Resetting CPU module of CPU No 1 1 to the RESET position to reset the entire system Refer to the following manual for RESET operation 557 QCPU User s Manual Hardware Design Maintenance and Inspection Check if all CPUs of the multiple CPU system are RUN status error by resetting the CPU module of CPU No 1 Confirmation of CPU module statues in all CPUs v Confirmation and correction of errors ZXZZLLLIE An error is checked with the system mon
130. CPU is used as the CPU module 1 up to four extensions can be connected Therefore five to seven extensions do not exist Figure 2 18 System configuration example for using Q3LIB 2 30 LON Ndd S NddD 9pouu jesJeAluf Buisn uoneunByuoo uejs sS ELZ uongeunByuoo uejs S pZ Table2 9 Restrictions on system configuration available base units extension cables and power supply modules CPU number CPU module1 CPU No 1 CPU module 2 CPU No 2 CPU module 3 CPU No 3 CPU module 4 CPU No 4 Maximum number of extension stages 7 extension stages when the QO2UCPU is used 4 extension stages Maximum number of mountable I O modules 65 No of CPUs when the QOOUCPU or Q01UCPU is used 25 No of CPUs when the QO2UCPU is used 37 No of CPUs Available main base unit model Available extension base unit model Q33B Q35B Q38B Q312B Type not requiring power supply module Q52B Q55B Type requiring Q series power supply Q63B Q65B Q68B Q612B module Available extension cable model QCO05B QC06B QC12B QC30B QC50B QC100B Available power supply module model Q61P A1 Q61P A2 Q61P Q61P D Q62P Q63P Q64P Q64PN 1 When the QOOUCPU Q01UCPU Q02UCPU is mounted on the CPU slot 1 up to three CPU modules can be mounted Therefore the CPU module 4 does not exist Precautions 2 31 Do not use an extension cable longer than 13 2m 43 31 ft When
131. DO pico 3j CPU No 1 CPU No 2 transmission reception word word Figure 8 13 Program example for sending bit and word data from CPU No 1 to CPU No 2 8 30 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM 3 Example of continuous data transmission from CPU No 1 to No 2 Table8 2 Auto refresh devices used in each module Auto refresh devices used in CPU No 1 Auto refresh devices used in CPU No 2 D10 to D18 M40 D10 to D18 For handshake in CPU Nos 1 and 2 refer to Section 4 1 2 Program example Program by which data are continuously stored from CPU No 1 to CPU No 2 M40 CPU No 2 reception completed Figure 8 14 Program example for storing data continuously from CPU No 1 to CPU No 2 CPU No 1 SM400 D10 0 BIN K4X20 D81 1 Always CPU No 1 Transmission ON transmission head data flag BIN K4X30 D88 Transmission final data BMOV D81 D11 K8 Transmission CPU No 1 head data transmission data o w w E Ov S SET Doo T Q3 CPU No 1 3 2 transmission 3 2 flag o BS 3 2 5g M40 i oo E a M I RST D10 0 d a CPU No 2 CPUNo 1 3 reception transmission a2 fl i amp completed ag m 3 ae a 2 99 CPU No 2 9 go SE vo C3 D10 0 g t BMOV D11 D121 K8 oo CPU No 1 CPUNo 1 CPU No 2 a gt transmission transmission reception o flag data data E 3 D 2 o o 3 o a 2 o O U c o 2 a D 3 o o o o 8 31 4 Writing r
132. E2 Settir U3E3 tit Setting Settin Not No2 No3 No 4 leceive ceive Set auto refresh setting if itis needed No setting Already set Total T2K points Assignment confirmation The total number of points is up to 12K Advanced settings Check Import Multiple CPU Parameter 8 20 To next page The number of points setting in Send range for each EJ PLC Set the number of points to be sent received among CPU modules Set them within the following number of points No of PLC Setting range Set 0 point for the following CPU modules High Performance model QCPU Process CPU C Controller module QO6CCPU V QO6CCPU V B PC CPU module Auto refresh setting Option Set devices and the number of points for data communication with auto refresh among CPU modules The number of points in the table below is occupied with one point in the auto refresh area X Y M L B SM SB 16 points D WRZRSD SW Set them by the number of CPUs Selection among CPU No 1 to CPU No 4 set on the Multiple CPU settings After the settings select the End button to close the Auto refresh settings window Communication area setting refresh setting Setting is required when performing communication with the following CPU modules High Performance model QCPU Process CPU C Controller module PC CPU module After setting select S
133. ECNET H or CC Link together on the main base unit Set one QCPU as the control CPU to control the modules of high access points e g CC Link IE controller network MELSECNET H or CC Link to prevent simultaneous access Reduce the number of refresh points of the CC Link IE controller network MELSECNET H and CC Link etc Reduce the number of auto refresh points between CPU modules Point P It is possible to reduce scan time by changing the following PLC parameter settings A Series CPU compatibility setting Note5 6 Floating point arithmetic processing Note5 7 L gt User s Manual Function Explanation Program Fundamentals for the CPU module used Bross ED TFor the Basic model QCPU and the Universal model QCPU A series CPU compatibility setting cannot be made 9 Notes 7 Gp ga For the Basic model QCPU the Process CPU or Universal model QCPU the floating point calculation processing cannot be changed 5 10 euin Buisseooud Buronpes E G CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM 6 1 Parameter list 1 2 Parameters that enable the use of multiple CPU system Comparing with a single CPU system a multiple CPU system has additional settings of Multiple CPU settings in PLC parameter and Control PLC setting in I O assignment setting The same PLC parameter must be set to all the CPU modules used in the multiple CPU system except some settings When using a PC CPU module
134. Fixed scan program setting Recalculate output is 1 scan later High speed execution System interrupt settings 131 10 0 ms 0 5ms 1000ms yey 2 F Use e Service processing setting Inteligent function module setting sae E Interrupt pointer setting scan time proceeds C Specify service process time ms 0 2ms 1000ms pm Specify service process tv IV Synchronize inteligent module s pulse up C PERIY SEITE Bt times 1 10 times Module synchronization JSettings should be set as same when Execute it while waiting for constant scan setting using multiple CPU Acknowledge XY assignment Defaut Check End Cancel To next page sJejeuueJed 1d2 ejdnjnuu jeseud Bulsney e z 9 SJejeureJeg ueis s fido eidnini eui dN Bumes zg 8 25 From previous page Q parameter setting Select I O assignment and display the I O PLCname PLC system PLC file PLE RAS Device Program Boot fie SFC O assignment L assignment setting window r Timer limit setting Low oo Common pointer No P After 0 4095 ndr ms 1ms 1000ms p High 10 00 0t 100ms S E speed oe ire oe Points occupied by empty slot 16 v Points RUN PAUSE contacts gt System interrupt settings RUN X IXO XTFFF Interrupt counter start No C PAUSE X X0 X1FFF Fixed scan interval Latch data backup operation valid contact 128 100 0 ms 0 5ms 1000ms Bes E E 129 40 0 me D 5ms
135. G13071 o tir i 3072 G10000 G13071 0j Set auto refresh setting if itis needed No setting Already set 12K points Advanced settings Assignment confirmation PLC poiniK VO No 3 No 3 3 U3E2 No 4 3 U3E3 Setting Receive Total The total number of points is up to 12K Import Multiple CPU Parameter ot es Cancel tesh tevicelPLENo 1 gt Shared memorPLC Nc 1 EUS Sat EU spect sere noe SEO Star End Setable points n Multiple CPU settings No of PLC No ofPic 4 v Host CPU number PLCNo 1 z Operating mode Error operation mode at the stop of PLC F Al station stop by stop error of PLC2 I7 All station stop by stop error of PLC3 All station stop by stop error of PLC4 Multiple CPU synchronous startup setting Target PLC IV No1 IV No2 IV No3 M No4 ISettings should be set as same when using multiple CPU Online module change T Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs T AII CPUs can read all inputs TT AlI CPUs can read all outputs Multiple CPU high speed transmission area setting Communication area setting refresh setlina JV Use multiple CPU high speed transmission CPU specific send range User setting are
136. High Performance model QCPU or Process CPU Data cannot be read from the host CPU s shared memory with a read instruction Doing so results in SP UNIT ERROR Error code 2114 3 Universal model QCPU Data can be read from the host CPU s shared memory with a read instruction h Access to CPU that is not actually installed Access to the CPU that is not actually installed with an instruction using the multiple CPU area device U3En GL is not allowed Doing so leads to SP UNIT ERROR Error code 2110 4 45 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4 1 5 Communications between CPU modules when the error occurs 1 Operation when the error occurs to the receive data When the CPU module receives the improper data at the data communication between the CPU modules due to noise or failure it cancels the receive data When the receive data is canceled the data which was received before this one remains without change When the normal data is received in the next time it will be updated to the receive data 2 Data transmission operation when the error occurs Table4 17 shows the auto refresh and the data communication between CPU modules when the host CPU detects the self diagnostics error Table4 13 Data communication between CPU modules when the self diagnostics error occurs Data communication Error definition Auto refresh 2 between CPU modules Slight error O O Factors other than below O O Errors on mul
137. J or later GX Configurator DN Version 1 23Z or later CPU slot CPU No 1 CPU module mounting posi CPU slot only Slot 0 CPU No 2 2 Section 3 1 3 tion and CPU No no CPU No Slot 1 CPU No 3 Slot 2 CPU No 44 The number assigned to the right of the R CPU module placed in the rightmost Concept I O number assignment Slot 0 is 004 FAM ME Section 3 3 1 position in the multiple CPU setting is 00n The number of mountable mod The number of mountable modules per Restrictions on number of ules per CPU module is CPU module and per system is Section 2 4 mountable modules restricted depending on the module type restricted depending on the module type 1 20 CHAPTER1 OUTLINE Table1 5 Difference from single CPU system continued Item Single CPU system Multiple CPU system Reference Setting the relations between the CPU Access from CPU module to module and other modules with the All modules can be controlled Section 3 4 other modules PLC parameter control CPU is required Accessible to the Universal model Manuals for Access from GOT Accessible E QCPU of the specified CPU No GOT Access with instruction using f f Accessible Only control CPU is accessible Section 3 6 link direct Access range CE Linkisys gt F F tem master Access to CC Link Accessible Only control CPU is accessible local module manuals Accessible through USB RS 232 or A l
138. L ainpow Jejognuoo 9 z NdOD epoul Jesjeniu ainpow Ajddns JamMod ainpow Ja O4JU0D 9 ainpow Jejouo2 9 T z NdOO epow O Jesaeniu ainpow A ddns je og ainpow Je ognuoo 9 ainpow Jejonuoo 25 ajnpow Jejonuoo 2 B z f 1dOO epoul O eSJ AUN jnpow Ajddns 18M0d No of CPUs a No of CPUs indicates the value set in the multiple CPU setting of the PLC parameter 2 Universal model QCPU except the QOOUCPU Q01UCPU Q02UCPU can be mounted be 3 Universal model QCPU except the QOOUCPU Q01UCPU Q02UCPUJ and Motion CPU Q172UDCPU Q173UDCPU can be mounted 4 High Performance model QCPU and Process CPU can be mounted 5 The PC CPU module occupies 2 slots 6 The PC CPU module PPC CPU852 MS 512 can be mounted 3 16 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Mounting position of CPU module ainpow JejoJuo2 2 e 9 npoui dD Aiduie 21d z 1dO0 Jepoui JesjeNum e npoui Kjddns 180g ainpow JejoJuo2 9 ainpow Jejouuo2 9 Ajduie 21d z f1dO0 epow JesjeNum einpoui A ddns 190g ieu o0 1 2 3 ov se INPOW Nd Od z MdOO epow Jesjenum einpoul A ddns 160g ze NdOO pow JesjeAum e npoui Kjddns samod Adw 21d Adw 21d Adw 21d zMdOO pow Jesuenu jnpow A ddns 190g N cpu o 1 2 Adw 21d Adwa 21d ainpow Jejognuoo 9 ze 1dO9O epow J
139. LC data Acknowledge XY assignment Multiple CPL settings Defaut Check End To next page 8 26 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM From previous page Intelligent function module detailed setting Check settings of the control CPU i HAW error Enortime time PLC 1 0 response Control PLC output i re mode operation rj mode Lo PLC PLCNo1 Li P c PLcNo2 L2 PLC PLC No 3 3 PLC PLC Emp La fara input 5 r ios wy RtNet im Le 5 5 Input z z 666 Output Clear s diate e zen men ee 10 9t 3 Output Lu 100 10 13 120 12 settings should be set as same when using multiple CPU i Set parameters for non multiple CPU system Write set parameters in the hard disk floppy disk Completed Figure 8 9 Parameter setting procedure for reusing multiple CPU system parameters sJejeuueJed 1d2 ejdnjnuu jeseud Bulsney e z 9 SJejeureJeg ueis s fido eidnini eui dN Bumes zg 8 27 8 3 Communication program examples using auto refresh 8 3 1 Program examples for the Basic model QCPU High Performance model QCPU and Process CPU This section explains program examples in the following system configuration given in Figure 8 10 and assignment of the data communications between CPU modules HPC GX Developer
140. Ltd KAZAKHSTAN German Branch Wiener StraBe 89 bld Traian 23 1 Mustafina Str 7 2 Gothaer Stra e 8 AT 2500 Baden MD 2060 Kishinev KAZ 470046 Karaganda D 40880 Ratingen Phone 43 0 2252 85 55 20 Phone 373 0 22 66 4242 Phone 4 7 7212 50 1150 Phone 49 0 2102 486 0 Fax 43 0 2252 488 60 Fax 373 0 22 66 4280 Fax 7 7212 501150 Fax 49 0 2102 486 1120 TEHNIKON BELARUS Koning amp Hartman b v NETHERLANDS CONSYS RUSSIA MITSUBISHI ELECTRIC EUROPEB V CZECH REPUBLIC Oktyabrskaya 16 5 Off 703 711 Haarlerbergweg 21 23 Promyshlennaya st 42 Czech Branch BY 220030 Minsk NL 1101 CH Amsterdam RU 198099 St Petersburg Radlick 714 113a Phone 375 0 17 21046 26 Phone 31 0 20 587 76 00 Phone 7 812 325 36 53 2 158 00 Praha 5 Fax 375 0 17 210 46 26 Fax 31 0 20 587 76 05 Fax 7 812 325 36 53 Phone 420 0 251 551 470 Koning amp Hartman b v BELGIUM Beijer Electronics AS NORWAY ELECTROTECHNICAL SYSTEMS RUSSIA Fax 420 0 251 551 471 Woluwelaan 31 Postboks 487 Derbenevskaya st 11A Office 69 MITSUBISHI ELECTRIC EUROPE B V FRANCE BE 1800 Vilvoorde N0 3002 Drammen RU 115114 Moscow French Branch Phone 32 0 2 257 02 40 Phone 47 0 32 24 30 00 Phone 7 495 744 55 54 25 Boulevard des Bouvets Fax 32 0 2 257 02 49 Fax 47 0 32 8485 77 Fax 7 495 744 55 54 ae SERE INEA BH d o o BOSNIA AND HERZEGOVINA MPL Technology Sp z o o POLAND ELEKTROSTILY RUSSIA one Aleja Lipa 56 Ul Krakowska
141. MS 512 can be mounted Mounting position of CPU module z NdOO epow Jesueniun all f1d90 Eepow JesueAiu ainpow Ajddns samod o s 91NPOW fdO e 9Inpouu dD NdOO z NdI Iepoui JesueAu einpoui A ddns 190g amp z NdOO IepouJ 5 JesyeAiu 3 e npoui K ddns 19 Mod d Adis 1d r NdOO 1dOO z NdOO Iepoui ESJU N ainpow jddns samod fiduie o 1d fiduie o 1d p 1HOO z NdOO pow 5 JesjeAiu ainpow Ajddns Jewog ainpow Jejouo2 9 Ajdwie 21d ajnpow Jejoujuo2 9 2 z NdOO pow 5 JesJeAu jnpow A ddns 190g z NdOO epow JesueAiu ainpow A ddns je og s SINPOW dD ainpow Jejouo2 9 NdIO z NdOO Iepoui JesueAu e npoui A ddns 190g s SINDOW ido amp z 1dOO epow O Jesjeniu ainpow Ajddns samod icPUu o 1 2 3 9x x 9 POW Md z f1dOO pow JesueNu einpoui A ddns 190g p s 9INDOW ndo Aiduie 9 1d p c JNpow Add amp z NdOO epow O JesueAu 3 einpoul Ajddns 19 og p Ajduie 21d ainpow Jejouuo2 2 e npouJ Jejouuo2 9 z NdOO epow JesjeAium e npoui Kjddns 190g ox ex NPOW fO zMdOO epow jesueniuy ainpow A ddns 19 0d amp o z NdOO Iepoui Jesjenu z NdOO epow JesaeAiu e npoui A ddns 190g a fiduie 9 1d e 9Jhpoui dO IdOO T z NdOO epow O jesuaniun ainpow Ajddns samod t
142. N 4 Auto refresh area x 2 a CPU No 3 send range a 2 CPU No 4 send range Figure 4 25 Memory configuration of multiple CPU high speed transmission area Table4 6 Description of multiple CPU high speed transmission area Size No Name Description Setting range Setting unit Area for data transmission between each CPU Multiple CPU high speed modules in the Multiple CPU system transmission area The area up to 14k word is divided by each CPU module that constitutes the Multiple CPU system 0 to 14k words 1k word Area to store the send data of the each CPU module Sends the data stored in the send area of the host CPU No n send area 2 CPU to the other CPUs Oto 14k words 1k word n n 1 to 4 Other CPU send area stores the data received from the other CPUs Area for data communication with other CPUs using the multiple CPU area device 3 User setting area 0 to 14k words 2 words Can be accessed by the user program using the multiple CPU area device Area for communicating device data with other CPUs 4 Auto refresh area Mi Oto 14k words 2 words by the communication using the auto refresh Point When the COM instruction is used in the sequence program the auto refresh can be executed automatically at the execution of the COM instruction However the scan time is prolonged due to the processing time for the auto refresh For details
143. N4 Table5 4 Auto refresh time High Performance model QCPU N1 N2 N3 N4 Process CPU QO2CPU 824s 0 524s 1064s 0 17 us QO2HCPU QO6HCPU Q12HCPU Q25HCPU 27 us 0 44 Us 27 Us 0 08 Us QO2PHCPU Q06PHCPU Q12PHCPU Q25PHCPU 5 4 aw ueog peBuojoJd 104 siojoe4 Z S 5 5 3 For Universal model QCPU Auto refresh time N1 No of transmission word points x N2 N3 No of other CPUs x N4 No of reception word points x N5 us The number of received words is the sum of the numbers of words transmitted by the other CPUs Example When No of CPU is set to 4 and the host CPU is CPU No 1 The number of received words is the sum of the numbers of words sent by CPUs No 2 to No 4 For the auto refresh using the multiple CPU high speed transmission area use values in Table5 5 for N1 to N5 Table5 5 Auto refresh time using multiple CPU high speed transmission area Univwesal model QCPU N1 N2 N3 N4 N5 QOOUCPU Q01UCPU Q02UCPU QO3UDCPU QO3UDECPU 64s 0 207 us 2Us 9Us 0 393 Us QO4UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU 6 0 183 2 9 0 327 Q04UDEHCPU Q06UDEHCPU Q10UDEHCPU ET eae is ES SELMS Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU For the auto refresh using the CPU shared memory use values in Table5 5 for N1 to N5 Table5 6 Auto refresh time using CPU shared memory Univwesal model QCPU N1 N2 N3 N4 N5 QOOUCPU
144. No 1 Set receive device from PLC No 1 Auto refresh No _ _point Start End 1 2M0 M31 4 2 32 W0 WIF E 3 4 b Receive setting from CPU No 1 PLE No 1 Receive PLC No 2 Send PLC No 3Receive Refresh device PLC No 2 Shared memory PLC No 2 Set send device to the other PLC Auto refresh No voint Start End 1 2 M32 M63 EN 2 32w20 WF 3 4 bes e Send setting of CPU No 2 PLC No 1 Receive PLC No 2 Send PLC No 3fReceive Refresh device PLC No 2 lt Shared memory PLC No 3 Set receive device from PLC No 3 h Receive setting from CPU No 3 PLC No 1 Receive PLC No 2 Receive PLC No 3 Send Refresh device PLC No 3 lt Shared memory PLC No 1 Set receive device from PLC No 1 Auto refresh No point 1 2 3 4 b Receive setting from CPU No 1 PLC No 1 Receive PLC No 2 Fleceive PLC No 3 Send Refresh device PLC No 3 Shared memory PLC No 2 Set receive device from PLC No 2 M32 M63 Go 32 D32 D63 ae Auto refresh No point Start End 2 1 2 3 4 f Receive setting from CPU No 2 PLC No 1 Receive PLC No 2 Receive PLC No 3 Send Refresh device PLC No 3 gt Shared memory PLC No 3 Set send device to the other PLC
145. No 1 send data to CPU No 1 receive area to CPU No 1 receive area O n W1F W1F D31 o w20 w20 D32 Oo 2 to CPU No 2 receive area to CPU No 2 send data to CPU No 2 receive area Uc W3F 3 W3F 4 D63 Cc o CPU No 3 i lt 1 y CPU No 3 i Eu CPU No 3 send data z5 o i rea We o 3 receive area ak lo 3 receive are d Ei E o a 1 Writing by END processing of CPU No 3 Ei i 2 Sending data from CPU No 3 to CPU No 1 and CPU No 2 a 3 3 Reading by END processing of CPU No 1 a 3 4 Reading by END processing of CPU No 2 2 Figure 4 35 Flow of sending data from CPU No 3 to other CPUs 3 B o 2 m c RV 4 32 Point If Start and End fields in Auto refresh are left blank auto refresh is not performed Start and End fields in Auto refresh in the Receive tab can be left blank The example for setting blank to the auto refresh setting of the CPU No 2 in Flow of sending data from CPU No 3 to other CPUs explained in the previous page 3 is shown below In the auto refresh setting of CPU No 2 in Figure 4 36 if the Start W40 and End W5F fields of the Auto refresh are left blank auto refresh is not performed to W40 to W5F in CPU No 2 Parameter setting PLC No 1 Send PLC No 2 Receive PLC No 3fReceive Refresh device PLC No 1 Shared memory PLC No 3 Set receive device from PLC No 3 Auto refresh No point Start End i 2 B40 BSF cs 32 w40 WSF lt g Receive setting
146. No1 v Le s5 input epen 3 Fiom v PLC No 1 v 10 jl Clear v v Y PLC No 1 v ti tor 10 Intelli Cla v S5tp v v PLC No 1 v EE E PLC No 1 mre o E A A A PLC No 1 v 14 13t PLC No 1 v Jsettings should be set as same when using multiple CPU Cancel Set parameters for non multiple CPU system Write set parameters in the hard disk floppy disk Completed Figure 8 8 Parameter setting procedure for new multiple CPU system creation 8 22 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM 8 2 3 Reusing preset multiple CPU parameters l Start up of GX Developer L Refer to the operating manual of GX Developer CHEER HC eX Open the PLC parameter setting window for PLC name PLC system PLC fle PLE RAS Device Program Bootfile SFC O assignment the parameter of GX Developer Select Multiple CPU settings and display the multiple CPU setting window Label Comment Acknowledge XY sssignmenl Ficligis CEU seing Multiple CPU settings Carry over of multiple CPU setting mS i Click Import Multiple CPU Parameter ie Multiple CPU high speed transmission area setting Communication area setting refresh setting E CPU specific send range PLC User selling area Auto refresh point Stat End point Setting No 2 No 3 Set auto r
147. O YOO e f1d90 e npoui A ddns 19 Mod icu o 1 2 cpu o 1 2 3 z JNpow ndd 9 d ainpow A ddns samod popu o 1 2 ainpow 1 01 U09 9 s f1dO YORON s f1dO YORON ex NdOO ainpow A ddns je og ainpow Jejonuoo O ainpow Jejo nuoo 9 gx dO YOO ee NddO einpoui Kjddns jeog cpu o 1 2 No of CPUs a The number of CPUs shows the value set by the multiple CPU setting ia Fz 2 The PC CPU module occupies two slots 3 The High Performance model QCPU and Process CPU can be mounted 4 The High Performance model QCPU Process CPU and Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU can be mounted 5 The Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T can be mounted the PPC 6 When the PC CPU module is used in combination with the Universal model QCPU 3 9 Mounting position of CPU module a Aydwie O1d ainpow Jejouo2 9 einpoui A ddns 190g p Aydw2 O1d Aydw9 901d yx dO YORON m z Nd CPU o 1 jnpow A ddns 190g a fiduie 5 1d ainpow Jejoguo2 9 einpoui A ddns 190g p Aduie 91d Aduie 91d p e NdIO jnpow A ddns 160g p Aduie 91d Ajdwe d1d Aduie 51d z f1d90 einpoui A ddns 190g ICPU o v Add YORON v dD YOO zf1d90 einpoui A ddns 190g ainpow Jejojuo2 9 ainpow J
148. Only 1 module GOT GOT A900 series Bus connection only 3 GOT1000 series Bus connection only controlled by QCPU Up to 5 modules Up to 5 modules 1 Modules of function version B or later can be used 2 Indicates the number of interrupt modules to which the interrupt pointer setting has not been made When the interrupt pointer setting has been made the number of modules are not restricted 3 For the available GOT model name refer to the following manuals 3 GOT A900 Series User s Manual GT Works2 Version2 GT Designer2 Version2 compatible Connection System Manual lt gt GOT1000 Series Connection User s Manual 2 52 uoneunBijuoo uiejs s 10 suonneoeJd rz b When using the High Performance model QCPU Process CPU Table2 22 Modules of restricted quantity Number of modules that Quantity restriction per Product Model can be mounted per QCPU system CC Link IE controller network QJ71GP21 SX Up to 2 Up to 2 module 4 e QJ71GP21S SX modules modules QJ71LP21 pee Up to 4 Up to 4 A QJ71LP21 25 Q series MELSECNET H Up to 4 modules Up to 4 modules QJ71LP21S 25 network module modules modules QJ71LP21G QJ71LP21GE QJ71NT11B e QJ71E71 Q series Ethernet interface module QJ71E71 B2 QJ71E71 B5 QJ71E71 100 Up to 4 modules Up to 4 modules Q series CC Link system master local module AnS series corresponding special f
149. P L programs SH 080076 13JF61 gt A 15 Manual name Description CPU module lt Manual number model code gt 1 2 3 4 QCPU Q Mode Programming Manual Structured Text Programming methods using structured lan O O O O guages SH 080366E 13JF68 QCPU Q Mode QnACPU Programming Man ual PID Control Instructions Dedicated instructions for PID control Olo O lt SH 080040 13JF59 gt QnPHCPU QnPRHCPU Programming Manual Process Control Instructions Dedicated instructions for process control O lt SH 080316E 13JF67 gt A 16 Other relevant manuals Manual name Description CC Link IE Controller Network Reference Manual lt SH 080668ENG 13JV16 gt Specifications procedures and settings before system operation parameter setting programming and troubleshooting of the CC Link IE controller network module Q Corresponding MELSECNET H Network System Reference Manual PLC to PLC network lt SH 080049 13JF92 gt Specifications procedures and settings before system operation parameter setting programming and troubleshooting of a MELSECNET H network system PLC to PLC network Q Corresponding MELSECNET H Network System Reference Manual Remote I O network lt SH 080124 13JF96 gt Specifications procedures and settings before system operation parameter setting programming and troubleshoot
150. PU The PC CPU module can be mounted on slot 0 or 1 The C Controller module can be mounted on slot 0 3 2 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 4 PLC Empty setting An empty slot can be reserved for future addition of a CPU module Select the number of CPU modules including empty slots at No of PLC and set the type of the slots to be emptied to PLC Empty in the I O assignment screen of PLC parameter a When adding the Motion CPU in the future Set slot 0 as PLC Empty CPU o 1 2_ lt Slot number CPU o 1 2 J 4 Slot number gt 5 a IS 2 35 2 o o L o o z z o6 o amp n Basic model PLC empty Basic model QCPU Motion CPU module Added Motion CPU Figure 3 2 PLC Empty setting for addition of Motion CPU b When adding the PC CPU module in the future 1 When mounting the Motion CPU Set slot 1 as PLC Empty icPul o 1 2 41 Slot number CPU Lo 112 4 Slot number gt om 2 2 o o o oa Basic model QCPU Power supply Motion CPU PLC empty module Basic model QCPU Motion CPU module Added PC CPU module Figure 3 3 PLC Empty setting for addition of PC CPU 2 When not mounting CPU Set slot 0 as PLC Empty cPU o 1 2 _ lt Slot number ICPU o 1 2 j Slot number BINPOW ndo Jo uonisog BununojN p e f1d90 l pow seg S L ON NdD U9SUM LVE gt a 2 2 o o gt o
151. PU No 1 detects the completion of the receive data processing and turns off the data setting completion bit 4 21 G0 MO F0 Data reception processing DO to D9 F1 SET M32 Figure 4 21 Interlock program example CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES Auto refresh between QCPUs Figure 4 22 shows program examples between the High Performance model QCPU when Auto refresh settings in Multiple CPU settings are made as Table4 5 Parameter setting Table4 5 Parameter setting example for interlock program CPU shared memory Device at CPU Setting No CPU No Number of i Start End Start End points CPU No 1 1024 0000 O3FF DO D1023 Setting 1 CPU No 2 1024 0000 O3FF D1024 D2047 In the parameter setting above use DO 0 as an interlock device of CPU No 1 data setting complete bit and D1024 0 as an interlock device of CPU No 2 receive data processing complete bit Transmission side program CPU No 1 Reception side program CPU No 2 Write Transmission side CPU No 1 Reception side CPU No 2 command 3 Mo Doo Di024 0 1 D0 0 D1024 0 4 Set send data from _ Read receive data DO to D1023 from DO to D1023 2 _ 5 _ SET DOO j 7 SET D1024 0 6 D0 0 D1024 0 DO 0 D1024 0 M B RST D1024 0 RST DOO RST MO H 1 CPU No 1 creates send data 2 CPU No 1 turns on the data se
152. PU No 2 auto refresh setting Data communication Device setting Device setting for data CPU specific send range for data range for each CPU DA er CPU Transfer communication Directio CPU Transfer communication No No Number n No No Number of Start End Start End of Start End Start End points points CPU Transfer 1 2 0 1 MO M31 CPU Transfer 1 2 0 1 MO M31 No 1 Transfer2 10 2 11 DO D9 No 1 Transfer2 10 2 11 D100 D109 CPU CPU Transfer 1 2 0 1 M32 M63 Transfer 1 2 0 1 M32 M63 No 2 No 2 Ajowaw peeus 182 Buisn se npoui Ndo ueewjeq suoneoiunuluo9 py In the above parameter settings use MO as an interlock device for CPU No 1 data setting completion bit and M32 as an interlock device for CPU No 2 receive data processing completion bit ese uoissiuisueJ peeds ybiy Add ejdninui Bursn usejje1 one Aq uogeoiunuuoo pp 4 34 Transmission side program CPU No 1 Receive side program CPU No 2 Write Transmission side CPU No 1 Reception side CPU No 2 command 3 M100 MO M32 1 MO M32 4 F4 Set send data HI yt Operation using from DO to D9 receive data DO to D9 2 5 SET Mo H r SET M32_H 6 MO M32 MO M32 u Tae RST Mo A M RST M32_H Le RT H 1 CPU No 1 stores the send data to DO to D9 2 CPU No 1 turns on the data setting completion bit MO Writes the above data to the
153. PU high speed tranmission User setting area Available for the Universal model QCPU only Auto refresh area Figure 4 39 Interlock program example Point P The user setting area of the multiple CPU high speed transmission area is available for the following CPU modules only Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172DCPU Q173DCPU 4 36 weiBoid Aq Aiowaw pareys 142 Bursn uogeoiunuiuoo pL AJowaw peeus 142 Buisn se npoui Ndo ueewjeq suoneoiunuiluo9 p 1 Communication made by program a Instructions used for writing to reading from the CPU shared memory The QCPU ina multiple CPU system enables to communicate each CPU module using user free areas in CPU shared memory and multiple CPU high speed transmission area with the write and read instructions The Table4 11 shows the write read instruction Table4 11 List of write and read instructions Description Instruction using the multiple CPU area device U3EmGLI Write instruction TO instruction Note4 8 e S TO instruction 2 Instruction using the multiple CPU area device U3EnGLI Read instruction e FROM instruction 2 1 When accessing multiple CPU high speed transmission area the processing speed is faster than when using any of the TO DTO FROM or DFRO instructions 2 Using the S TO instruction data cannot be written to user setting area in multiple CPU high speed
154. PU o 8 O niversal mode QCPU except T 172DCPU psi Motion CPU P O O O O Q01UCPU Q173DCPU Q02UCPU PC CPU module O O x O C Controller module O x Section 4 1 2 Reference Section 4 1 4 Section 4 2 Section 4 3 Section 4 1 3 1 Available instructions are restricted depending on the version of the Motion CPU For instructions that can be used refer to the manual of the Motion CPU O Available x Not available 4 2 4 1 Communications between CPU modules using CPU shared memory This chapter describes communication methods between CPU modules of the multiple CPU system using the CPU shared memory First the CPU shared memory is described 4 1 1 CPU shared memory The CPU shared memory is a memory provided for each CPU module and by which data are written or read between CPU modules of the multiple CPU system The CPU shared memory consists of four areas Host CPU operation information area Restricted system area Auto refresh area User setting area Multiple CPU high speed transmission area 4 3 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES The CPU shared memory configuration and the availability of the communication from the host CPU using the CPU shared memory by program are shown in Figure 4 1 to Figure 4 3 For Basic model QCPU Host CPU Other CPUs CPU shared memory Read Write Read OH 0 to to Host CPU operation infor
155. PU852 MS 512 When the Q8BAT is used for the Universal model QCPU use the connection cable whose connector part displays A For details of connector part of a connection cable refer to the following manual L gt QCPU User s Manual Hardware Design Maintenance and Inspection Figure 2 13 System configuration when Q3LDB is used 2 20 LON Nd S Nd SS990Jg JO f1HOO 9pouiJ eoueuuojSg uBiH Buisn uoneunByuoo uejs S TLZ uongeunByuoo uejs S pZ 2 21 Point When the multiple CPU system is configured using the High Performance model QCPU or the Process CPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 to No 4 High Performance model QCPU Process CPU Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU PC CPU module C Controller module Note that the multiple CPU system cannot be configured using the following combinations Combination of the Universal model QCPU and the PC CPU module PPC CPU686 MS 64 PPC CPU686 MS 128 Combination of the PC CPU module and the C Controller module CHAPTER2 SYSTEM CONFIGURATION b Outline of system configuration 32 point modules are mounted on each slot E Main base unit Q312DB 12 slots occupied S a E 3 E 5 o 11 O number ALL 0 00L 10 d4 0103 jd 9 09 Ad 0 0V 36 0108 AZ 9109 AS 9 0p AE 0 02 Al 0100 uunnna CPU mod
156. Performance model QCPU modules cannot be replaced online To replace a module online when using the Process CPU set Enable online module change with another PLC 8 4 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM 3 When creating a new multiple CPU system Start up of GX Developer lt gt The operating manual of GX Developer Open the PLC parameter setting window for parameters of GX Developer The operating manual of GX Developer Q parameter setting Select PLC system and display the PLC Device Program Boot fie SFC 1 0 assignment system setting window Acknowledge XY assignment Multiple CPU settings Default End Cancel Q parameter setting Points occupied by empty slot Option f JJPLc fie PLC RAS Device Program Boot fle SFC 1 0 assignment Set the occupied points for one empty slot Default 16 points Timer limit setting pod d 100 rms ims 1000ms Common pointer No P After 0 4095 High 10 0 ms 0 1ms 100ms c Uer pancene i sie EN RUN PAUSE contacts System interrupt settings RUN X 0 1 FFF E 7 J Interrupt counter start No C 0 768 PAUSE X XO X1FFF Fixed scan interval 128 100 0 ms 05ms 1000ms Zi 129 40 0 ms 05ms 1000ms Remote reset 130 20 0 ms 0 5ms 1000ms High speed F Allow TT interrupt setting 131 10 0 ms 0 5ms 1000ms Output mode at STOP to RUN Previous state Interrupt program Fixed scan progra
157. Precautions Do not use an extension cable longer than 13 2m 43 31 ft When using an extension cable keep it away from the main circuit high voltage and large current line Set the number of extension stages so as not to be duplicated Although there is no restriction on the connection order of the Q5L TB and the Q6LJB check the availability of them by referring to QCPU User s Manual Hardware Design Maintenance and Inspection when both the QSLIB and the Q6L 1B exist as the extension base unit The QA1S6L 1B QA6LIB QA6ADP A5LB A6LB or Q6RLIB cannot be connected as an extension base unit Connect the OUT connector of an extension base unit and the IN connector of the adjacent extension base unit by an extension cable When 66 modules or more are mounted an error SP UNIT LAY ERR error code 2124 occurs The number of mountable modules includes one CPU module No of CPUs is the number of CPUs set by No of PLC of GX Developer When mounting the Universal model QCPU and the PC CPU module at the same time use the PPC CPU852 MS 512 as the PC CPU module The PC CPU module and C Controller module cannot be mounted together therefore mount either of them The PC CPU module occupies two slots Therefore when the PC CPU module is used the maximum number of I O modules is decreased by 1 from the value indicated in the table For details of the PC CPU module and C Controller module refer to the manuals
158. RE 5 6 8 lo o ojo RA cle ee Le 2 2 peigiuu a 4 9 0z9 5 e 8 a SeSe E i peuqiuu a 99009 9 eleli o NGHE 3 m 364 0 082 si sagooas 2 E 5 UST gt is e gt e dasooog e P dag 01029 B as a 3 m 384 010v4 3 Jascovs 2 89 0v9 z INA 5 9 B amp d sooss g 46901089 9 3 e 3s 42901099 9 g N a O0 8 e dsoos 99 EN 449 01 039 6 o9 D o o Zid sssoors 2 gp d599099 g M lt v So el g E A e To S 3 olo olo o o a e a S co ae E o jojojojojo 8 o B m 7 7 2 amp a zoaosgz 8 3 8 beer js E c s o 1 Li ce al 424z ooz a asz o opz e Bee lt 8 B g Jez o ozz olofofofolo g ololo Elo ojo e LZ ooz g ser 1 0zr i aes ozs ej 444 OL0aL amp ALP 01007 2 digo 009 z 4al 09 3 44 03 S 44v 9 03v e 491 0Y 28 E olofofo g aae 9 098 z 40v 007 e 46L Ol 08L Sg emel lolele s age 0 ove 9 489v 9 ovr ALLO 094 amp dee oloze s 46 0 08 8j 46r 08r o o 12 e 4SL o OF 2 aleo ooe 2 8 44 0 09 s 44v 9 097 ses e JEL ozi 8 442 9 032 8 R ase o ore 8 b aSr 9 opp 2 amp daz 909z 2 2 E E E o amp saz 91 0WZ o o n t m e te m e i E G ce E g ce G M 2 s T L s I 2 s A O e OG BE mounting module Figure 2 8 System configuration example for using Q3OB 2 12 Table2 4 Restrictions on system configuration available base units e
159. S S S A Azz 01 092 amp 49z 91 orc S 8 amp 4ez 01 0zz x MS E e ALz 1002 g aevo ozy 3 aes ozs 9 444 03 g alv 00 l ALS 0 00S 4al 09 3 44 03 g 44v 03v 49L OVE 23 oEelejerejo 8 dae 009 z 4ar ol 004 S go ofolololo 2 J6L0108L 5 dae ol ove g dar ol ove z ALL 0109L 4J eoroce s 36 908 8 46t 08 bs o E 9 ASLO 0vL 2 digo oog 8 d4 0109 8 44v 09v De a JELOl0ZL 8 8 _44z 01032 8 R ase ove 8 ASO 0p g aaz 002 N 7 7 wo A 4az o rovc o co gt D ec 9 Oo m lo a e e e e Error in mounting Figure 2 14 System configuration example for using Q3LIDB 2 22 Table2 7 Restrictions on system configuration available base units extension cables and power supply modules CPU number CPU module1 CPU No 1 CPU module 2 CPU No 2 CPU module 3 CPU No 3 CPU module 4 CPU No 4 Maximum number of extension stages 7 extension stages Maximum number of mountable I O 65 No of CPUs modules Available main base Q38DB Q312DB unit model Type not requiring power supply module Q52B Q55B Available extension bass nitmodel xn LM Q series power supply Q63B Q65B Q68B Q6128 u Available extension QC05B QC06B QC12B QC30B QC50B QC100B cable model Available power Q61P A1 Q61P A2 Q61P Q61P D Q62P Q63P Q64P Q64PN supply module model
160. Section 3 4 other modules PLC parameter control CPU is required Manuals for Access from GOT Accessible GOT Access with instruction using 7 Accessible Only control CPU is accessible Section 3 6 link direct Access range CC Link sys f tem master Access to CC Link Accessible Only control CPU is accessible local module manuals Accessible through RS 232 cable or via E network Access from peripheral Accessible through RS 232 i For access when the Motion CPU or Section 2 2 devices cable or via network PC CPU module is connected refer to the relevant manual Clock data used by intelli Clock func Clock data of the Basic model Clock data of the Basic model QCPU gent function module QD75 Section 3 8 2 tion QCPU is used CPU No 1 is used etc z The entire system is reset by resetting The entire system is reset by CPU module resetting oper the Basic model QCPU CPU No 1 resetting the Basic model A Section 3 9 ation QCPU Resetting CPU No 2 and 3 individu i ally is not allowed For a stop error of the Basic model Operation QCPU of CPU No 1 the multiple CPU system stops CPU modules No 2 and Operation for CPU module 3 are in MULTI CPU DOWN Error The system stops Section 3 10 stop error code 7000 status For a stop error occurred in CPU No 2 or 3 the operation depends on the parameter setting of Operation mode 1 12 To the
161. TIB AGLIB cannot be connected CHAPTER2 SYSTEM CONFIGURATION 2 When using the redundant power main base unit Q30RB a System configuration Battery for QCPU Q6BAT High Performance model QCPU Process CPU Universal model Q7BAT SET r umer G9 O3LDIRB type redundant power main base unit 2 is 2 3 A Redundant power supply input output intelligent function module Extension cable Q5LB type extension base unit 3 Q6 ORB type redundant power extension base unit 2 Only one memory card can be mounted Select an appropriate memory card from the SRAM Flash and ATA in accordance with application and capacity When a commercial memory card is used the operation is not guaranteed Use the redundant power supply module for the power supply module The redundant power supply modules Q63RP and Q64RP can be used on one redundant power supply base unit at the same time The Q series power supply module and the slim type power supply module are not available for the power supply module The Q Series power supply module is not required for the Q5LIB extension base unit When the Q8BAT is used for the Universal model QCPU use the connection cable whose connector part displays A For details of connector part of a connection cable refer to the following manual L gt QCP
162. To perform auto refresh in CPU shared memory set the number of points to be sent from each CPU module Send range for each PLC and a device for storing data PLC side device on Multiple CPU settings in PLC Setting No switch Set the send range for each CPU module 4 11 parameter Multiple CPU settings No of PLC No of PLC fi Operating mode Error operation made at the stop of PLC F All station stop by stop error of PLC3 V All station stop by stop error of PLC4 Online module change Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs All CPUs can read all inputs All CPUs can read all outputs Communication area setting refresh setting z a Change scree Al Setting 1 E Set starting devices for each PLC CPU specific send range PLC sid PLC Auto refresh area Caution fev starting J Settings should be set as same when using multiple CPU device Pont Stat End j Stat En O O 50 0 Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y DW R ZR The unit of points of CPU specific send range is word Import Multiple CPU Parameter
163. Transmission side program CPU No 1 Reception side program CPU No 2 Write 3 command U3E0 U3E1 U3E0 U3E1 MO G10010 0 G10000 0 1 G10010 0 G10000 0 4 WE yt Set the send data to the H yt Operation using the user setting area receive side data U3E01G 10000 to G100009 2 U3E0 5 U3E1 SET G10010 0 SET G10000 0 6 E 7 U3E0 U3E1 U3E0 U3E1 G10010 0 G10000 0 U3E0 G10010 0 G10000 0 U3E1 m K RST 610010 0 H W RST G10000 0 Rar mo H 1 CPU No 1 writes the send data to the user setting area 2 CPU No 1 writes that the data setting complete bit turns on to the user setting area lt Data in multiple CPU high speed transmission area of CPU No 1 are sent to CPU No 2 gt 3 CPU No 2 detects the send data setting completion 4 CPU No 2 processes the receive data 5 CPU No 2 writes that the receive data processing completion turns on to the user setting area lt Data in multiple CPU high speed transmission area of CPU No 2 are sent to CPU No 1 gt 6 CPU No 1 detects that the receive data processing completion turns on and turns off the data setting complete bit lt Data in multiple CPU high speed transmission area of CPU No 1 are sent to CPU No 2 gt 7 CPU No 1 detects that the send data setting completion turns off and turns off the receive data processing completion Figure 4 44 Interlock program example With an instruction such as the BMOV instruction which writes 2 w
164. U 1 No of CPUs indicates the number of CPU modules set at No of PLC in the Multiple CPU settings screen of PLC parameter 2 When the PC CPU module is mounted the maximum number of mountable I O modules is the result of 65 No of CPUs 1 3 When the Motion CPU or PC CPU module is mounted on the multiple CPU system Q3LIRB Q6LIRB and Q6LIRP are not available 4 For some intelligent function modules different version may be used 5 When the PC CPU module is mounted the slot to the right of the PC CPU module is 10n 1 16 CHAPTER1 OUTLINE 3 When using the Process CPU Table1 4 Difference from single CPU system Item Single CPU system Multiple CPU system Reference Maximum number of exten 7 stages Sion stages Maximum number of mount able 64 65 No of CPUs I O modules System con Main base unit model Q30B Q3O0RB Q30DB 3 Section 2 1 2 figuration Extension base unit model Q50B Q60B Q6O0RB Extension cable type QCO05B QC06B QC12B QC30B QC50B QC100B Overall distance of extension a Within 13 2 m cable Power supply module 3 Q60P Q6ORP model Process CPU No restrictions on function version I O module Function version A or later Available Function version B or later module Function version A or later for QD62 Intelligent function module Function version A or later
165. U User s Manual Hardware Design Maintenance and Inspection Figure 2 9 System configuration when QORB is used 2 14 LON Nd S Nd SS990Jg JO f1HOO 9pouiJ eoueuuoj9g ubiH Buisn uoneunByuoo uejs S TZ uongeunByuoo uejs S pZ 2 15 Point When the multiple CPU system is configured using the High Performance model QCPU or the Process CPU as the CPU No 1 only the following modules can be used as the CPUs No 2 to CPU No 4 High Performance model QCPU Process CPU Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU When duplicating power supply use the redundant power supply base unit and the redundant power supply module For the power supply module mounted on the redundant power supply base unit only the redundant power supply module can be used CHAPTER2 SYSTEM CONFIGURATION b Outline of system configuration 2 1 System configuration 2 1 2 System configuration using High Performance model QCPU or Process CPU as CPU No 1
166. U settings screen of PLC parameter When the PC CPU module is mounted the maximum number of mountable I O modules is the result of 65 Number of CPUs 1 when using the QOOUCPU Q01UCPU 24 Number of CPUs 1 when using the QO2UCPU 37 Number of CPUs 1 When the Motion CPU or PC CPU module is mounted on the multiple CPU system Q3LIRB Q6LIRB and Q6ORP are not available When the QOOUCPU Q01UCPU QO2UCPU is used as the CPU module 1 up to three CPU modules can be mounted Therefore the CPU No 4 does not exist These versions can be used for the QO2UCPU QO3UDCPU QO04UDHCPU and QOGUDHCPU For software versions available for a Universal model QCPU other than the above refer to Section 2 3 Available for Built in Ethernet port QCPUs only When a Universal model QCPU except QOOUCPU Q01UCPU QO02UCPU or Motion CPU Q172DCPU or Q173DCPU is used as any of CPUs No 2 to No 4 clock data in CPU No 1 can be used When CPU No 1 is the QOOUCPU Q01UCPU QO2UCPU the communication by the auto refresh using the multiple CPU high speed transmission area is not available When CPU No 1 is the QO2UCPU the multiple CPU high speed transmission area cannot be set up 1 23 uleisAS fido ej amp uis wo eoueJeyid er CHAPTER2 SYSTEM CONFIGURATION This chapter explains the system configuration of Multiple CPU Systems and the precautions for Multiple CPU System configuration 2 1 System configuration 2 1 1 System configur
167. U3En GET c Control direction to the Motion CPU The QCPU can direct control to the Motion CPU with the following instruction Motion dedicated instruction d Writing reading device data from the QCPU to the Motion CPU The QCPU can write read device data to from the Motion CPU with the following instructions Multiple CPU transmission dedicated instruction Multiple CPU high speed transmission dedicated instruction e Event issue to the C Controller module or PC CPU module The QCPU can issue an event to the C Controller module or PC CPU module with the following instruction Multiple CPU transmission dedicated instruction 1 Refer to the manual of the Motion CPU for instructions dedicated to Motion 2 For the multiple CPU transmission dedicated instruction refer to the manuals of the Motion CPU C Controller module and PC CPU module 3 For the multiple CPU high speed transmission dedicated instruction refer to the following manuals Writing reading device data to from the QCPU QCPU Programming Manual Common Instructions Writing reading device data to from the Motion CPU Manual of the Motion CPU Point The Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU allows executing the motion CPU dedicated instruc tion several times in the same scan Since the motion CPU dedicated instruction can be executed consecutively to different axis numbers delay time of servo startup interval can be shortened
168. X from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y D W AZR The unit of points of CPU specific send range is word Settings should be set as same when Import Multiple CPU Parameter Check End using multiple CPU Cancel Figure 3 21 I O sharing when using Multiple CPUs input loading a When All CPUs can read all inputs has been set 1 Loads ON OFF data from the input and intelligent function modules being controlled by the other CPUs by performing input refresh before a sequence program operation starts In addition loading of ON OFF data from the input and intelligent function modules being controlled by the other CPUs is also available with direct access input DX DX20 C H H Loading is Loading is allowed with allowed with input refresh direct access input CPU 0 1 2 3 4 Slot number X20 oooo00 oooo000 Output Number of slot points 16 points 16 points 16 points 16 points EM KEEN 2 2 Control CPU setting t Loading is allowed from non controlled CPU Figure 3 22 When performing input loading in CPU No 1 3 24 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 2 Input X loading is performed for the modules shown in Table3 8 which are mounted to the main base
169. X Developer 2 37 CHAPTER2 SYSTEM CONFIGURATION 2 2 Configuration of peripheral devices This section describes the system configurations of peripheral devices that can be used with the Basic model QCPU High Performance model QCPU Process CPU and Universal model QCPU Point For connection between the Motion CPU PC CPU module or C Controller module and peripheral in the multiple CPU system refer to the manual of each CPU module 1 When using the Basic model QCPU H Basic model QCPU summon 1t O RS 232 cable unuuuuuunuuuuuu i The available version varies depending on the system configuration 5 Section 2 3 Figure 2 23 Configuration of peripheral devices Seoiep Jeeudued jo uoneunByuo0g zz 2 38 2 When using the High Performance model QCPU liHigh Performance model QCPU QG Memory card eres UO RS 232 cable O USB cable 2 3 uumuuuuuuuuuuu coc G Memory card 1 PC card adapter A gt 41 Do not format the ATA card by other than GX Developer 73 QCPU User s Manual Hardware Design Maintenance and Inspection 2 It is not used for the QO2CPU 3 For writing into memory card by GX Developer and information on USB cables refer to the operating manual of the GX Developer 4 The available version varies depending on the system configuration L37 Section 2 3 Figure 2 24 Confi
170. a Auto refresh point Stat End point Setting 3022 610000 613021 5O SettinalSend 3042 610000 613041 30 Set G1359 12 eisai _ Set auto refresh setting ifitismeeded No setting Already set 12K points Advanced settings Assignment confirmation PLC poinitK 170 No No1 3 uaen No2 3 U3E1 No3 3 use2 No 4 3 usea 3060 610000 3072 610000 Total The total number of paints is up to 12K oe Le Import Multiple CPU Parameter Cancel Multiple CPU settings No of PLC No ofPic 4 x Host CPU number PLC No 1 zl Operating mode Error operation mode at the stop of PLC F t JV All station stop by stop error of PLC2 1 All station stop by stop error of PLC3 I All station stop by stop error of PLC4 Multiple CPU synchronous startup setting Target PLC Iv Not IV No2 IV No3 IV No4 Settings should be set as same when using muliple CPU Online module change Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 statue outside the group cannot be taken 1 0 sharing when using Multiple CPUs T AIL CPUs can read all inputs T AI CPUs can read all outputs Multiple CPU high speed transmission area setting Communication area setting refresh setting JV Use multiple CPU high speed transmission PLC 170 No U3E0 U3E1 S U3
171. able4 15 Table4 15 List of multiple CPU transmission dedicated instructions CPU module Universal model QCPU D E CP Basic model ne Mie Instruction ENS QCPU High Q E Description Q00UCPU QO6UD E HCPU n d 01UCPU 10UD E HCPU meter econ riis aay Process CPU E Q20UD E HCPU Q26UD E HCPU S DDWR Writes host CPU device data into other CPU SP DDWR devices O O S DDRD Reads other CPU device data into the host SP DDRD CPU devices O O S GINT Requests start up of other CPU interrupt o O SP GINT programs 4 49 O Available X Not Available CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 2 Multiple CPU high speed transmission dedicated instruction The Universal model QCPU can write read device data to from the Q172DCPU and Q173DCPU with the multiple CPU high speed transmission dedicated instruction shown on Table4 16 Table4 16 List of multiple CPU high speed transmission dedicated instructions CPU module Universal model QCPU D E CP ese ma REM Instruction n QCPU High E Description QOOUCPU QO6UD E HCPU TES Blass 01UCPU 10UD E HCPU Ai i CT Eco Process CPU E Q20UD E HCPU Q26UD E HCPU D DDWR Writes host CPU device data into other CPU x DP DDWR devices O D DDRD Reads other CPU device data into the host DP DDRD CPU devices O D GINT Requests start up of other CPU interrupt 5 DP GINT programs O O Available X Not Available Point One QCPU
172. ach CPU module Clock data used by intelli Clock func f Clock data of the High Perfor Clock data of the High Performance c gent function module QD75 Section 3 8 2 tion gic mance model QCPU is used model QCPU CPU No 1 is used The entire system is reset by resetting The entire system is reset by i CPU module resetting oper the High Performance model QCPU f resetting the High Performance Section 3 9 ation CPU No 1 Resetting CPU No 2 to 4 model QCPU E individually is not allowed For a stop error of the High Perfor mance model QCPU of CPU No 1 the Operation multiple CPU system stops CPU mod ules No 2 to 4 are in MULTI CPU Operation for CPU module The system stops DOWN Error code 7000 status Section 3 10 stop error For a stop error occurred in any of CPU No 2 to 4 the operation depends on the parameter setting of Operation mode To the next page 1 15 uleisAS fido buig wo eoueueyid E4 Table1 3 Difference from single CPU system continued Single CPU system Multiple CPU system Reference Communication using CPU Up to 2k words in total of 4 settings per shared memory by auto Not available CPU The total for all CPU modules is Section 4 1 2 refresh 8k words With S TO FROM instructions and Communication using CPU Not available instruction using the multiple CPU area Section 4 1 4 shared memory by programs Co
173. afa MITSUBISHI ELECTRIC MELSEC Q series Programmable Controller User s Manual Multiple CPU System QCPU Oo NE MITSUBISHI ELECTRIC INDUSTRIAL AUTOMATION Versi rsion H QCPU User s Manual Multiple CPU System Mitsubishi Programmable Controller MELSEG Q MITSUBISHI Q00CPU Q01CPU Q02 H CPU QO6HCPU Q12HCPU Q25HCPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU Q00UCPU Q01UCPU Q02UCPU Q03UD E CPU QO4UD E HCPU QO6UD E HCPU Q10UD E HCPU Q13UD E HCPU Q20UD E HCPU Q26UD E HCPU SAFETY PRECAUTIONS Read these precautions before using this product Before using this product please read this manual and the relevant manuals carefully and pay full attention to safety to handle the product correctly In this manual the safety precautions are classified into two levels d DANGER and AN CAUTION A Indicates that incorrect handling may cause hazardous conditions CAUTION resulting in medium or slight personal injury or physical damage O DANGER Indicates that incorrect handling may cause hazardous conditions resulting in death or severe injury w e e e oe Under some circumstances failure to observe the precautions given under AN CAUTION may lead to serious consequences Make sure that the end users read this manual and then keep the manual in a safe place for future reference Design Precautions Configure safety circuits external to the programmable co
174. ange screens Setting v IV Set starting devices for each PLC Send range for each PLC PLC side device Send range for each PLC PLC side device PLC The auto refresh area Caution PLC The auto refresh area Caution Stat End Stat End Point j t zs Pointe pe om ES Ma M3839 Emu 05 0000 002F M3072 M3839 LNo2 66 oooof oat m2ooo M3055 Te SSS SS SSS SSS SS i SaaS SS ae SSS Ee Setting of CPU No 1 Setting of CPU No 2 Figure 4 17 Setting of CPU device CPU No 1 CPU No 2 Device Device MO c soc mns M2000 to Monitor device Monitor device M3055 Fixed A n M3072 Instruction device Instruction device Fixed Figure 4 18 Outline of auto refresh operation 4 18 Aiowaw pegeus dD Husn useJje1 opne Aq uoneoiunuulo2 Z Lr AJowaw peeus 1d2 Buisn se npoui Ndo ueewjeq suonediunwWwOoyD Ly Example 2 When setting not to perform unnecessary refresh The following shows the example performing auto refresh between each CPU from No 2 to No 4 and CPU No 1 only By leaving the device column of other CPUs of which auto refresh is not required in blank it is possible to set not to perform unnecessary refresh The device column of the host CPU cannot be left in blank Change screens Setting 1 V Set starting devices for each PLC Send range for each PLC The auto refresh area Caution Dev stating PLC side device Pont Stat End
175. ation using Basic model QCPU QOOCPU Q01CPU This following explains the system configuration using the Basic model QCPU 1 System using the main base unit Q3L1B a System configuration eq 2 3 4 5 6 m S gt Battery for QCPU Q6BAT Basic model Motion PC CPU C Controller QCPU CPU module 3 4 6 module 6 B type main base unit 1 G Extension cable Q series power supply input output intelligent function module motion module 5 Q50B type extension base unit 2 Q60B type extension base unit As a power supply module use the Q series power supply module Make the power consumption within the rated output current value of the power supply module The Slim type power supply module and Redundant power supply module cannot be used as a power supply module No Q series power supply module is required for the Q5LIB type extension base unit The QCPU battery Q6BAT cannot be installed to the Motion CPU and the PC CPU module For further information on PC CPU module consult CONTEC Co Ltd Tel 81 6 6472 7130 Be sure to set the control CPU of motion modules to the Motion CPU The PC CPU module and C Controller module cannot be mounted together Figure 2 1 System configuration when Basic model QCPU is used CHAPTER2 SYSTEM CONFIGURATION Point When the multiple CPU system is configured using the Basic
176. aution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y D W RZR The unit of points of CPU specific send range is word Import Multiple CPU Parameter Check End Cancel Doline madule changel T Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs 4 Operating mode Error operation mode at the stop of m IV All station stop by stop error of PLC2 v All station stop by stop error of PLC3 F All station stop by stop error of PLC4 Settings should be set as same when using multiple CPU Multiple CPU settings No of PLC No of PLC E Operating mode Error operation mode at the stop of PLC m IV All station stop by stop error of PLC2 IV All station stop by stop error of PLC3 I All station stop by stop error of PLC4 Settings should be set as same when using multiple CPU Al I AIL CPUs can read all inputs IT AI CPUs can read all outputs Communication area setting refresh setting Change screens Setingi I Set starting devices for each PLC CPU specific send range PLC side device PLC Auto refresh area Caution Dev starting Point Start End Start End No1 0
177. ber a E ES 5 5 8 B 3 pee amp les Cy n pn uni In n L3 ns a qn s Se cy Ind ass e BTE _ O LA m y L1 o o 1 EEBEBEN 2 2 Contro CPU setting f Write to buffer memory is disabled Write to buffer memory is disabled Figure 3 28 Writing to intelligent function module e npouJ p j01 u09 u0u uy ebuel sseooy Z YE Se npo N 19410 pue ejhpoyw ndo Jo buey sseoov pe 3 29 3 5 Access target under GOT connection When a GOT is connected the access range to QCPU varies depending on the connection method For details refer to the GOT manual 3 6 Access with instruction using link direct device Only control CPUs can execute instructions using link direct devices to access other modules Link direct devices are not usable for modules being controlled by other CPUs OPERATION ERROR error code 4102 occurs if an instruction using link direct devices is executed to a module controlled by other CPU Network module I Slot number 000000 Cleo Col TColz Control CPU setting Access allowed Access not allowed OPERATION ERROR Figure 3 29 Access with instruction using link direct device 3 30 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3 7 Access range of GX Developer 1 Access to QCPU It is possible
178. bia 0t03 iced is 0to3 Peer O to 1 0to3 4 QOSUDEEPU impossible is impossible Q04UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU 1 In a multiple CPU system configuration a PC CPU module and a C Controller module cannot be used at the same time 2 Universal model QCPUs except for the QOOUCPU Q01UCPU QO2UCPU can be used 3 1 BINPOW ndo Jo uonisog DununojN p e 3 1 1 When CPU No 1 is Basic model QCPU The mounting position of each CPU module is shown in Table3 2 1 Mounting position of Basic model QCPU Only one Basic model QCPU can be mounted on the CPU slot slot on the right hand side of the power supply module of the main base unit 2 Mounting position of Motion CPU Only one Motion CPU can be mounted to slot 0 on the right of the Basic model QCPU It cannot be mounted to other than slot 0 3 Mounting position of PC CPU module Either one of the PC CPU module can be mounted on the right edge of the CPU module No CPU module can be mounted on the right side of the PC CPU module icPU o 1 2 Slot number Power supply module E o o E o n ea Motion CPU 2 n o s C Figure 3 1 Position where the PC CPU module cannot be mounted when using the Motion CPU a When mounting the Motion CPU The PC CPU module can be mounted on slot 1 or 2 The C Controller module can be mounted on slot 1 b When not mounting the Motion C
179. bit device is specified in the CPU device Example If the total number of send points for all CPU modules is 10 then 160 points of BO to B9F are set when BO link relay is specified f 4 EB Process For Basic model QCPUs and High Performance model QCPUs Process CPUs of which the first 5 digits of serial No is 07031 or earlier auto refresh is available only by setting devices consecutively from the starting device of CPU No 1 In addition when using GX Developer of Version 8 22Y or earlier auto refresh is also available only by setting devices consecutively from the starting device of CPU No 1 4 14 Aiowaw paseys Add Husn useJje1 one Aq uoneoiunuulo2 Z Lr Asowaw peeus 142 Buisn se npoui Ndo ueewjeq suoNediunwWWwOoyD py 3 The CPU devices are set as follows It is possible to change the device for settings 1 to 4 The same devices can also be specified as long as the device range for settings 1 to 4 are not overlapped Setting 1 For link relay Change screens Setting v Set starting devices for each PLC B Send range for each PLC PLC side device PLC The auto refresh area Caution Dev stating B0 Settings with different Pont Stat End Stat End devices are available at ETIN setting 1 to setting 4 No2 l No 3 Setting 2 For link register Change screens Setting2 v Set starting devices for each PLC Send range for each PLC PLC side device The auto refresh area Caution Stat
180. by CPU modules c When not using the PC CPU module The I O number for an I O module or intelligent function module mounted to the next slot to those occupied by CPU modules is set as 00H and consecutive numbers are then allocated sequentially to the right Example Two CPU modules are mounted CPU 0 1 2 3 4 5 o mJ Slot number I O number 00x Figure 3 19 Position of I O number 00H 3 20 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM d When using the PC CPU module The PC CPU module occupies two slots The one on the right side among the two slots is handled as an empty slot 16 empty points are occupied by default Therefore the I O number of the next slot on the right side of the PC CPU module is 10H Set the empty slot to zero point on the I O assignment of PLC Parameter dialog box to assign 00H to the first I O number Example When No of CPUs is set to 3 CPU 9 Slot number v v rs No of CPU modules Empty slot 3 modules 00x to OFu occupied Figure 3 20 Position of I O number 00H Remark REESE 1 fthe number of CPU modules mounted on the main base unit is less than the number set at the Multiple CPU setting set the open slot s to PLC Empty For the PLC Empty se
181. can concurrently issue up to 32 instructions of Instructions dedicated to Motion CPU and Multiple CPU transmission dedicated instructions except for S P GINT Note that multiple instructions are executed in order starting from the first instruction When 33 or more incomplete instructions are identified an OPERATION ERROR error code 4107 occurs For details and availability of the multiple CPU transmission dedicated instruction refer to the manual of the Motion CPU The C Controller module has the function which writes reads device data to from the Motion CPU For details refer to the manual of the C Controller module 4 50 Nd UOHOW 01 NdOO Woy ejep 3919p jo Burpeej DunuM Ley suononJisu pejeoipeg uin uoneoiunuuo y 4 3 2 Starting interrupt program from QCPU to C Controller module PC CPU module Using the multiple CPU transmission dedicated instruction in Table4 17 an interrupt program can be started from the QCPU to the C Controller module PC CPU module The interrupt program from the PC CPU module to other CPU module cannot be started An interrupt program can be started from the C Controller module to the Motion CPU or the C Controller module in another CPU For details refer to the manual of the C Controller module Table4 17 CPU transmission dedicated instraction Instruction name Description S GINT SP GINT Requests start up of other CPU s interrupt programs Example When us
182. cations usage and settings and data communication method with external devices of the serial communication module Communication method using the MC protocol which reads writes data to from the CPU module via the serial communication module or Ethernet module GX Developer Version 8 Operating Manual lt SH 080373E 13JU41 gt Operating methods of GX Developer such as programming and printout A 17 Note icon The detailed explanation of Note A is provided under the corresponding Note A at the bottom of the page Note detailed explanation The detailed note corresponding to each icon is described MANUAL PAGE ORGANIZATION Reference Chapter The section in this manual or another relevant manual that can be referred to is shown with 37 right side CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 2 Restricted syste The area used by the sfstem of the CPU module OS 4 User settingva The area for performg communication between CPU modules The points after the one sed for the auto refresh area are used An area including the auto performed fresh area can be used as the user setting area when auto refresh is not 5 QCPU standard area The area provided for the Universal model GPU to communicate with other CPUs High Performance QCPU or Process CPU in a multiple CPU system This area includes Host CPU operation informatidN area Restricted system area Auto refresh
183. ce model QCPU at default CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM Operating mode option Select if all CPUs are stopped operated for occurrence of stop error Default With any error of CPUs 2 3 and 4 all CPUs stop checked For example when All station stop by stop error of PLC 2 is unchecked other CPUs continue operation for an error of CPU No 2 Operation of CPU No 1 cannot be changed Online module change 9 Note8 4 1 O sharing when using Multiple CPUs option Select if the online module change is set or if input output outside of group is set Default Online module change setting checked Online module change is inhibited for the following cases Online module change is not performed I O sharing when using Murtiple CPUs is performed I O sharing when using Multiple CPUs Set if the input output status beyond control of input output setting outside of group is loaded or not Default Not loaded Not checked Communication area setting refresh setting Option Set the devices used for data communications with auto refresh between CPU modules and the points of the auto refresh area Use the points of the auto refresh area from the Set startive device number The number of points in the table below is occupied with one point in the auto refresh area Point Set Online module change so that all CPU modules in the multiple CPU system can be the same setting
184. code 7010 No error SP UNIT LAY ERR error code 2125 No error 1 The following errors may occur except MULTI EXE ERROR when the programmable controller is turned on or the High Performance model QCPU for CPU No 1 is reset CONTROL BUS ERR error code 1413 1414 MULTI CPU DOWN error code 7000 7002 2 56 uoneunBijuoo uiejs s 10 suonneoeJd rz 5 6 7 Precautions for use of high speed interrupt function Note2 1 Some system configurations and functions are restricted when the High speed interrupt fixed scan interval setting has been mad with a parameter L gt Qn H QnPH QnPRH User s Manual Function Explanation Program Fundamentals Note that the above restrictions do not apply to the High Performance model QCPU of serial number 04011 or earlier since it ignores the High speed interrupt fixed scan interval setting Precautions for use of Motion CPU Q172DCPU Q173DCPU When the Q172 Q173DCPUs are used the main base unit can use the multiple CPU high speed main base unit for Multiple CPU system only However do not mount the motion modules to 0 to 2 of the multiple CPU high speed main base unit for Multiple CPU system s Manual for Motion CPU Precautions for GOT connection note2 2 Only the GOT A900 and GOT F900 series Basic OS compatible with Q mode and communication driver must be installed and GOT1000 series can be used The GOT800 series A77GOT and A64GOT cannot be u
185. configured using the Universal model QCPU except QOOUCPU Q01UCPU QO2UCPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 to No 4 Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU High Performance model QCPU Process CPU Motion CPU Q172DCPU Q173DCPU PC CPU module PPC CPU852 MS 512 C Controller module Note that the PC CPU module and C Controller module cannot be mounted together CHAPTER2 SYSTEM CONFIGURATION b Outline of system configuration q 2 3 MMain base unit 32 point modules are mounted on each slot Q312DB 12 slots occupied CPU 0 1 2 3 4 5 6 7 8 9 10 M eee Slot number z LL LL LL LL LL rs LL LL 0 O S fe OS Ie ele kele el e ea Se ss 1 0 number r o e e e eo eo e e eo e P o vm vlo o a jojuj o Q series power CPU module 4 1 supply module CPU module 3 1 CPU module 2 CPU module 1 WiExtension base unit 32 point modules are mounted on each slot Q612B 12 slots occupied Ta i 12 13 14 15 16 17 18 19 20 21 22 23 extension Wympuesuepue peso Popo a po yw EE ej m jr jo mlaoalr io un r io djele elel SEINNI NINIAN o o ra teh fe A E AE A E aS a feel ger E vey o o S E E S e
186. ctable 2 Notes 6 Process For the Basic model QCPU or the Process CPU using the AnS A series compatible I O modules and special function modules is not allowed 8 9 Ndd sseooJd nid90 epow eoueuuojeg YUBIH Nd dD pouw dseg euj 10 Bumes Jejeureled p Z8 SJejeureJeg ueis s dD eidnini eui dN Bumes zg 4 Reusing preset multiple CPU parameters i Start up of GX Developer 577 Refer to the operating manual of GX Developer parameter setting X Open the PLC parameter setting window for PLC system PLC file PLC RAS Device Program Boot file SFC VO assignment the parameter of GX Developer Select Multiple CPU settings and display the multiple CPU setting window Comment Acknowledge XY assignme Multiple CPU settings x Carry over of multiple CPU setting Click Import Multiple CPU Parameter Change screens Ez 0 Send range for each PLC PLC The auto refresh area Caution Pent Stat End Not No2 No3 Nod Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address Settings should be set as same when The applicable device of head device is B M Y D WR ZR using multiple CPU The unit of points that send range for each PLC is word Import Muliple CPU Parameter To next page 8 10 From previous page Open project c E
187. ction The QeL IB QA1S6L IB QA6LIB or QA6ADP ASLIB AGLIB cannot be connected as an extension base unit Connect the OUT connector of an extension base unit and the IN connector of the adjacent extension base unit by an extension cable When 66 modules or more are mounted an error SP UNIT LAY ERR error code 2124 occurs The number of mountable modules includes one CPU module No of CPUs is the number of CPUs set by No of PLC of GX Developer When the redundant power main base unit is used bus connection is not available for the GOT When the redundant power main base unit is used the Motion CPU and PC CPU module cannot be used 2 35 CHAPTER2 SYSTEM CONFIGURATION 4 When using the slim type main base unit Q30SB a System configuration E High Performance C Controller model QCPU module 5 Q Battery for QCPU Q6BAT G Universal model eT GO7BAT SET QCPU D 1 1 1 1 1 1 1 1 1 D 1 1 1 1 1 i Q8BAT connection cable Battery for QCPU Q8BAT Slim type power supply input output intelligent function module 1 One memory card is installed Select an appropriate memory card from the SRAM Flash and ATA cards according to the application and capacity When the memory card is used operation is not guaranteed 2 The slim type main base unit does not have an extension cable connector Th
188. d memory cards sys e Q Q Oo SH 080483ENG 13JR73 tem maintenance and inspection trouble shooting and error codes QnUCPU Users Manual Function Explanation Functions methods and devices for Program Fundamentals e programming lt SH 080807ENG 13JZ27 gt Qn H QnPH QnPRHCPU User s Manual Func Functions methods and devices for tion Explanation Program Fundamentals e 9 e programming lt SH 080808ENG 13JZ28 gt Information for configuring a multiple CPU system system configuration I O QCPU User s Manual Multiple CPU System numbers communication between CPU lt SH 080485ENG 13JR75 gt modules and communication with the input O O O O output modules and intelligent function mod ules QnUCPU User s Manual Communication via n Functions for the communication via built in Built in Ethernet Port O Ethernet port of the CPU module lt SH 080811ENG 13JZ29 gt gi Programming manual QCPU Programming Manual Common Instruc How to use sequence instructions basic tions naue 00 instructions and application instructions lt SH 080809ENG 13JW10 gt QCPU Q Mode QnACPU Programming System configuration performance specifications functions programming Manual SFC O O O O debugging and error codes for SFC lt SH 080041 13JF60 gt MELSAP3 programs QCPU Q Mode Programming Manual MELSAP L Programming methods specifications and o O O O functions for SFC MELSA
189. d receiving CPU No 3 data lt Flow of sending data from CPU No 3 to other CPUs gt CPU No 3 writes device data set in Auto refresh CPU No 3 send data to the auto refresh area in CPU No 3 at END processing CPU No 3 sends data in auto refresh area of CPU No 3 to CPU No 1 and CPU No 2 in multiple CPU high speed transmission cycle CPU No 1 and No 2 read the received data from CPU No 3 to a device set in Auto refresh CPU No 3 receive area at END processing PLC No 1 PLC No 2 PLC No 3 Multiple CPU high speed transmission area Multiple CPU high speed transmission area Multiple CPU high speed transmission area PLC No 1 PLC No 1 PLC No 1 User free area User free area User free area Auto refresh area Auto refresh area Auto refresh area Ao PLC No 2 PLC No 2 PLC No 2 zx User free area User free area User free area Oo 9 o3 Auto refresh area Auto refresh area Auto refresh area z 3 c a PLC No 3 PLC No 3 PLC No 3 E g User free area User free area User free area m S 2 2 o2 lt lt 3 Auto refresh area oa Auto refresh area A LI 1P MK Auto refresh area g g n F e Device Device Device So BO MO BO gt to CPU No 1 send data to CPU No 1 receive area to CPU No 1 receive area 0 c B1F M31 B1F o B20 M32 B20 3 to CPU No 2 receive area to CPU No 2 send data to CPU No 2 receive area 5 9 B3F 3 M63 4 B3F Sc B40 M64 B40 lo oO to CPU No 3 receive area lt to CPU No 3 receive area to CPU No 3 send data n B5F M95 B5F 3c c wo wo DO zx 2 to CPU
190. del QCPU is mounted on the multiple CPU system No of CPUs is the number of CPUs set by No of PLC of GX Developer The PC CPU module occupies two slots Therefore when the PC CPU module is used the maximum number of I O modules is decreased by 1 from the value indicated in Table2 3 The PC CPU module and C Controller module cannot be mounted together therefore mount either of them For details of the Motion CPU PC CPU module and C Controller module refer to the manuals of each CPU module 2 9 CHAPTER2 SYSTEM CONFIGURATION 2 1 2 System configuration using High Performance model QCPU or Process CPU as CPU No 1 This following explains the system configuration using the High Performance model QCPU and the Process CPU as the CPU No 1 1 When using the main base unit Q3L1B a System configuration S esta ace onm OUO E SUE NT M Q7BAT SET e MEE G Process CPU Universal model QCPU 9 10 y B type main base unit 2 utput lintelligent function module motion module 7 B type extension base unit 4 B type extension base unit 2 uongeunByuoo uejs S pZ QA1S6 OB type i extension base unit 3 amp AnS series power supply input output special function module v E QA6 OB type extension base unit 3 12 Q9 series power supply input output special function module
191. device from PLC No 1 Set receive device from PLC No 1 PLC No t Receive PLCNo 2 Send PLC No 1 Receive PLC No 2 Send Refresh device PLC No 2 gt Shared memory PLC No 2 Refresh device PLC No 2 Shared memory PLC No 2 Set send device to the other PLC Set send device to the other PLC Figure 8 23 Auto refresh setting same settings User free area will be from 3E0 G10000 for CPU No 1 and from 3E1 G10000 for CPU No 2 CPU shared memory Host CPU operation information area Restricted system area Auto refresh area Inapplicable CPU No 1 memory CPU No 2 memory 3E0 G10000 3E0 G10000 Multiple CPU high speed transmission area to User setting area CPU No 1 to User setting area CPU No 1 send area receive area 3E0 G17133 3E0 G17133 Auto refresh area Auto refresh area 3E1 G10000 3E1 G10000 User setting area CPU No 2 to User setting area CPU No 2 receive area send area 3E0 G17133 Auto refresh area Auto refresh area 3E1 G17133 8 38 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM 5 Program example of continuous data writing reading using the user setting area from CPU No 2 to CPU No 1 Table8 6 Auto refresh devices used in each CPU module Auto refresh device used in CPU No 2 Auto refresh device used in CPU No 1 M63 M31 Program example Program by which data are continuously written read using the user setting area from the CPU module of CPU No 2 t
192. e C Auto Detail 8 Slot Default Settings should be set as same when using multiple CPU Import Multiple CPU Parameter 12 Slot Default Read PLC data Acknowledge XY assignment Multiple CPU setlings Default Check End Cancel Figure 8 19 I O assignment settings of each module 8 34 CHAPTER8 STARTING UP THE MULTIPLE CPU SYSTEM Figure 8 20 Auto refresh area setting f1dOO pow jessaluA 24 10 sejduiexe urejDoJg z 8 UseJja1 one Buisn sejduiexe wesboid uoneoiunuiuo eg 8 35 2 Example of bit amp word data transmission from CPU No 1 to No 2 Table8 4 Auto refresh devices used in each CPU module Auto refresh devices used in CPU No 1 Auto refresh devices used in CPU No 2 MO MO D0 D1 D0 D1 Program example Program by which bit and word data are sent ffom CPU No 1 to CPU No 2 CPU No 1 MO CPU No 1 transmission bit Transmission instruction DMOV K1234 DO CPU No 1 transmission word CPU No 2 SM400 MG a e Normally ON CPU No 1 CPU No 2 i transmission reception bit bit DMOV DO pio 3j CPU No 4 CPUNo2 transmission reception word word Figure 8 21 Program example for sending bit and word data from CPU No 1 to CPU No 2 8 36 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM 3 Example of continuous data transmission from CPU No 1 to No 2 Table8 5 Auto refresh devices used in
193. e Maximum number of exten 7 stages when the QOOUCPU Q01UCPU Q02UCPU is used 4 stages sion stages 65 Number of CPUs Maximum number of mount 64 Use of QOOUCPU and Use of QOOUCPU and Q01UCPU 25 able Q01UCPU 24 Use of Number of CPUS I O modules Q02CPU 36 when the QO2UCPU is used 37 Num ber of CPUs System con figuration Main base unit model Q30B Q30SB Q3O0RB Q30DB Section 2 1 3 Extension base unit model Q5nrB Q60B Q6ORB Extension cable type QCO05B QC06B QC12B QC30B QC50B QC100B Overall distance of extension a Within 13 2 m cable Power supply module 3 QenriP Q60SP Q6ORP model Universal model QCPU No restrictions on function version I O module Function version A or later Available Function version B or later module Function version A or later for QD62 Intelligent function module Function version A or later QD62D and QD62E No version restric tion for QI60 GX Developer Version 8 48A or later GX Configurator AD Version 2 05F or later GX Configurator DA Version 2 06G or later GX Configurator SC Version 2 12N or later Section 2 2 GX Configurator CT Version 1 25B or later GX Configurator TI Version 1 24A or later Available i 5 GX Configurator TC Version 1 23Z or later software GX Configurator FL Version 1 23Z or later GX Configurator QP Version 2 25B or later GX Configurator PT Version 1 23Z or later GX Configurator AS Version 1 21X or later GX Configurator MB Version 1 08
194. e Universal model QCPU 9 Note4 3 refer to Section 4 1 3 Point In the following case uncheck Use multiple CPU high speed transmission function of Multiple CPU high speed transmission area setting in the Universal model QCPU The High Performance model QCPU or Process CPU is used as the CPU No 1 Use multiple CPU high speed transmission function of Multiple CPU high speed transmission area setting in the Universal model QCPU No 1 is unchecked The main base unit slim type main base unit or redundant power supply base unit is used Multiple CPLI high speed transmission area setting Communication area setting refresh setting CPU specific send range Auto refresh point k 1 O No point Stat End point Setting Set auto refresh setting if it is needed No setting Already set mul Ce Figure 4 4 Setting when not using the multiple CPU high speed communication 2 Note4 2 For the Universal model QCPU auto refresh area of the CPU shared memory means auto refresh area of the standard area When the Universal model QCPU is used read this section regarding CPU shared memory as QCPU standard area Note4 3 The QOOUCPU Q01UCPU QO2UCPU cannot perform the communication by the auto refresh using the multiple CPU high speed transmission area 4 8 Kowa pegeus Add Husn useJje1 opne Aq uoneoiunuulo2 Zp y Asowaw peeus 142 Buisn se npoui Ndo ueewjeq suoneoiunuluo9 Ly
195. e extension base unit and GOT cannot be bus connected 3 Asa power supply module use the slim type power supply module Keep the current consumption within the rated output current of the power supply module The Q series power supply module and the redundant power supply module are not available for the power supply module 4 When the Q8BAT is used for the Universal model QCPU use the connection cable whose connector part displays A For details of connector part of a connection cable refer to the following manual uongeunByuoo ueljs S Lc 7 QCPU User s Manual Hardware Design Maintenance and Inspection 5 For memory cards that can be used with the C Controller module refer to the manual of the C Controller module Figure 2 21 System configuration when Q3LISB is used Point When the multiple CPU system is configured using the QOOUCPU Q01UCPU Q02UCPU as the CPU No 1 only the following CPU module can be used as the CPU No 2 C Controller module When the multiple CPU system is configured using the Universal model QCPU except QOOUCPU Q01UCPU QO2UCPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 and 3 High Performance model QCPU Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU C Controller module LON Nd S NddD pow jesJeAluf Buisn uoneunByuoo uejs sS ELZ 2 36 b Outline of system configuration
196. e refresh data will not be updated b Setting for using the same file name as the program in the file register Do not set devices for the use of the auto refresh in the file register for each program If set auto refresh will be performed on the file register that corresponds to the last scan execution type program executed c Transmission delay time Data transmission delay time due to auto refresh is from 0 09 ms to 1 80 Sending side scan time Receiving side scan time x 2 ms d Assurance of data sent between CPUs Due to the timing of data send from the host CPU and auto refresh in any of other CPUs old data and new data may be mixed data separation in each CPU The following shows the methods for avoiding data separation at communications by auto refresh 1 32 bit data separation Transfer data with auto refresh method in units of 32 bits Since auto refresh is set in units of 32 bits 32 bit data does not separate 2 Data consistency for data exceeding 32 bits In auto refresh method data are read in descending order of the setting number in auto refresh setting parameter Transfer data separation can be avoided by using the transfer number lower than the transfer data as an interlock device Figure 4 38 shows a program example for interlocking between CPU No 1 and CPU No 2 lt Parameter setting gt Table4 10 Example for parameter setting for interlock program CPU No 1 auto refresh setting C
197. e uoissiuisueJi peeds ybiy Add ejdninu Bursn usejjei one Aq uogeoiunuuoo pp 4 28 3 Auto refresh setting and data flow The following explains the data flow among CPU modules when a multiple CPU system is configured among three CPU modules and auto refresh is set for two ranges a Setting examples of auto refresh to each CPU module Figure 4 29 shows the setting examples of auto refresh to explain the data flow by auto refresh PLC No 1 Send PLC No 2fReceive PLC No 3Receive Refresh device PLC No 1 gt Shared memory PLC No 1 Set send device to the other PLC Auto refresh No int Start End 2 BO BIF gt 1 2 32 w0 WIE ES 3 4 a Send setting of CPU No 1 PLE No 1 Send PLE No 2 Receive PLC No 3Receive Refresh device PLC No 1 lt Shared memory PLC No 2 Set receive device from PLC No 2 Auto refresh No ioint Start End 1 2 B20 5 32 w20 3 4 d Receive setting from CPU No 2 PLC No 1 Send PLC No 2 Receive PLE No 3 Receive Refresh device PLC No 1 Shared memory PLC No 3 Set receive device from PLC No 3 Auto refresh No point Start End 1 2 Bp40 BSF E 2 32 w40 WSF lt 3 4 5 6 g Receive setting from CPU No 3 PLC No 1 Receivel PLC No 2 Send PLC No 3fReceive Refresh device PLC No 2 Shared memory PLC
198. e3 4 MELSECNET H or Ethernet network can also be accessed Slot number oooooo ANA O o y AAAA AA o zzzzzzzzzzzzzzz op ANAVAA alt nN N Control CPU setting Access allowed Figure 3 32 Access to controlled module and non controlled module vos EPI The CC Link IE controller network can only be used with the High Performance model QCPU whose first serial number is 08102 or later 9 ER The CC Link IE controller network cannot be used with the Basic model QCPU and the Process CPU 3 32 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3 Access from GX Developer in other station From GX Developer connected to other station on the same network all QCPUs in the multiple CPU system can be accessed Station No 2 normal station a a a a a 5 S S Ei o a 5 o o o o fo o id T ene co B EH m e Dn s Q uH n npn Q p m e Dn pes 6 Hi n Inn E n ty e tay tt x v nif p m cll m p em up mp rpm zb i E BT I fo W Eat eg ey sd LL o o o o o o EH EBEBEB o o control CPU sett
199. each PLC PLC CPU specific send range PLC side device Auto refresh area Caution End Dev startir Start End No 1 Point Start uU No 2 of No 3 of No 4 ol Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y D W A ZR The unit of points of CPU specific send range is word I O sharing when using Multiple CPUs MAI CPUs can read all outputs All CPUs can read all outputs setting All CPUs can read all outputs Not all CPUs can read all outputs setting Import Multiple CPU Parameter Check End Cancel Figure 3 24 I O sharing when using Multiple CPUs output loading a When All CPUs can read all outputs has been set 1 Loads to the host CPU s output Y the ON OFF data that is output to the output module and intelligent function modules being controlled by the other CPUs by performing output refresh before a sequence program operation starts 3 26 ro Loading with output refresh is allowed Slot number CPU 0 1 2 3 4 B B B B B B B B B B Input Output Input Output LL LL LL qe N ceo wy gt x x v v o o o o E v ned eo e Q o T N ceo ev x gt x gt Number of slot point
200. each module Auto refresh devices used in CPU No 1 Auto refresh devices used in CPU No 2 D10 to D18 M40 D10 to D18 For handshake in CPU Nos 1 and 2 refer to Section 4 1 2 Program example Program by which data are continuously stored from CPU No 1 to CPU No 2 CPU No 1 SM400 D10 0 BIN K4X20 D81 1 Always CPU No 1 Transmission ON transmission head data flag BIN K4X30 D88 Transmission final data BMOV D81 D11 K8 Transmission CPU No 1 head data transmission data 0o w w B o ug SET Dio 0 F 33 CPU No 1 3 2 transmission i 3 2 i e flag o9 5 S 3 2 5z M40 j oo E Q n ASA D10 0 d a CPU No 2 CPUNo 1 3 3 reception transmission 22 completed flag c 3 23 0 z o 9 amp CPU No 2 3d ao oc o8 D10 0 Q S t BMOV D11 D121 K8 cg CPU No 1 CPU No 1 CPU No 2 i transmission transmission reception flag data data M40 CPU No 2 reception completed Figure 8 22 Program example for storing data continuously from CPU No 1 to CPU No 2 8 37 4 Writing reading using the user setting area of the CPU shared memory by a program a Memory addresses for auto refresh setting to user setting area In the auto refresh setting make same settings for CPU No 1 and CPU No 2 PLC No 1 Receive PLC No 2 Send PLC No Receive PLE No 2 Send Refresh device PLC No 2 Shared memory PLC No 1 Refresh device PLC No 2 lt Shared memory PLC No 1 Set receive
201. eading using the user setting area of the CPU shared memory by a program a Memory addresses for auto refresh setting to user setting area The same points must be set for CPU No 1 and CPU No 2 in the auto refresh setting Change meme Setting v Set starting devices for each PLC B Send range for each PLC PLC side device PEE The auto refresh area Caution Dev stating DOJ Peint Start End Stat End Not 3 X 000 OTF Doj D3l No2 1 32 X 0000 omF D32 D63 SS Stas eR Change screens Setting 2 Set starting devices for each PLC Send range for each PLC PLC side device PLC The auto refresh area Caution End Stat End Pont Stat Noi 2 0020 0021 MO mat No2 2 0020 goat M32 MB So EN EN EE SN NUN nost a EE Ea EE Figure 8 15 Auto refresh setting same settings The auto refresh area occupies the area from setting 1 and setting 2 to memory address of 0800H to 0821H Therefore the user setting area is in a range from 0822H to OFFFH Ls Section 4 1 1 CPU shared memory 0000H Host CPU operation to information area O1FFuH 0200H to Restricted system area O7FFH CPU No 1 memory CPU No 2 memory 0800H 0800H 0800H Auto refresh area I eui V A TEE E e d DO to D31 D32 to D63 to User setting area OFFF 081FH 081FH H 0820H 0820H MO to M31 M32 to M63 0821H 0821H 0822H 0822H 0850H 0850H 0881H 0881H
202. ective actions to be taken between the external device and CPU module in case of a communication failure N CAUTION Do not install the control lines or communication cables together with the main circuit lines or power cables Keep a distance of 100mm 3 94 inches or more between them Failure to do so may result in malfunction due to noise When a device such as a lamp heater or solenoid valve is controlled through an output module a large current approximately ten times greater than normal may flow when the output is turned from off to on Take measures such as replacing the module with one having a sufficient current rating Installation Precautions N CAUTION Use the programmable controller in an environment that meets the general specifications in the QCPU User s Manual Hardware Design Maintenance and Inspection Failure to do so may result in electric shock fire malfunction or damage to or deterioration of the product To mount the module while pressing the module mounting lever located in the lower part of the module fully insert the module fixing projection s into the hole s in the base unit and press the module until it snaps into place Incorrect mounting may cause malfunction failure or drop of the module When using the programmable controller in an environment of frequent vibrations fix the module with a screw Tighten the screw within the specified torque range Undertightening can cause
203. ecute the process as the scan time proceeds C Specify service process lime ms 0 2ms 1000ms Specify service process Spends sere i times 1 10 times C Execute it while waiting for constant scan selling Fa T AICP Multiple CPU high speed transmission area setting Communication area setting refresh setting I Use multiple CFU High speed transmission PLC Multiple CPU settings No of PLC 4 No ofPLC 4 x Host CPU number Error operation made at the stop of PLC VV All station stop by stop error of PLET I All station stop by stop error of PLC2 Allstation stop by stop error of PLC IV All station stop by stop error of PLC4 Multiple CPU synchronous startup setting Target PLC IV Not Iv No2 IV No3 IV No4 Settings should be set as same when using multiple CPU Online module change TT Enable onine module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs T7 AICPUs can read all inputs T AICPUs can read al outputs Multiple CPU high speed transmission area setting Communication ares setting refresh setting v Use multiple CPU high speed transmission CPU specific send rangel Ri User selling area point VO No point Stat point Nod 3fuseo 3072 610000 No 2 3 use1 3072 610000 No3 3fu
204. eed transmission area PLC No 1 User free area Auto refresh area Multiple CPU high speed transmission area Multiple CPU high speed transmission area PLC No 1 PLC No 1 User free area User free area Auto refresh area Auto refresh area PLC No 2 User free area User free area 2 Auto refresh area gt Auto refresh area User free area Auto refresh area PLC No 3 PLC No 3 Auto refresh area Auto refresh area Auto refresh area Device Device Device BO BO BE CPU No 1 send data CPU No 1 receive area to CPU No 1 receive area B20 4 BUE CPU No 2 receive area lt CPU No 2 send data Ae CPU No 2 receive area B40 B40 to CPU No 3 receive area CPU No 3 receive area to CPU No 3 send data B5F B5F wo Do WIE CPU No 1 send data CPU No 1 receive area to CPU No 1 receive area w20 4 Wee CPU No 2 receive area CPU No 2 send data E CPU No 2 receive area W40 D64 WEE CPU No 3 receive area CPU No 3 receive area Pos CPU No 3 send data 1 Writing by END processing of CPU No 2 2 Sending data from CPU No 2 to CPU No 1 and CPU No 3 3 Reading by END processing of CPU No 1 4 Reading by END processing of CPU No 3 Figure 4 33 Flow of sending data from CPU No 2 to other CPUs 4 31 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 3 Flow of sending data from CPU No 3 to other CPUs lt Para
205. eeding 32 bits In auto refresh method data are read in descending order of the setting number in auto refresh setting parameter Read data separation can be avoided by using the setting number lower than the setting data as an interlock device Auto refresh between QCPU and Motion CPU Figure 4 21 shows program examples for the Basic model QCPU and Motion CPU when Auto refresh settings in Multiple CPU settings are made as shown in Table4 4 Parameter setting Table4 4 Parameter setting example for interlock program CPU Shared Memory CPU Side Device Setting No CPU No Number of E Start End Start End points CPU No 1 2 00CO 00C1 MO M31 Setting 1 CPU No 2 2 0800 0801 M32 M63 CPU No 1 10 00C2 00CB DO D9 Setting 2 CPU No 2 0 Transmission program example Write command E 6 M32 Transmission program Ladder L 1 Transmission data processing DO to D9 2 SET MO RST MO RST XO 1 CPU No 1 creates send data 2 CPU No 1 turns on the data setting completion bit lt Auto refresh execution between multiple CPUs gt 3 CPU No 2 detects the completion of send data setting 4 CPU No 2 performs receive data processing Reception program example Reception program Motion SFC D 5 CPU No 2 turns on the completion of receive data processing lt Auto refresh execution between multiple CPUs gt 6 C
206. efresh setting if itis needed No setting Already set r L ssinment corfimatin Settings should be set as same when EEIE side CPU Import Multiple CPU Parameter Check JL era Cancel l To next page sJejeuueJed 1d2 ejdnjnuu jeseud Bulsney e z 9 SJejeureJeg ueis s fido eidnini eui dN Bumes zg 8 23 From previous page Open project Project drive J B SampleComment Drive Path C MELSEC GPPW Project name ample 7 Import Multiple CPU Parameter When multiple CPU parameters are used improperly all the following parameters are overwritten Q Assignment Setting 1 0 Assingment Standard setting PLC system setting Points occupied by empty slot Multiple CPLI Settings Execute the multiple CPU parameter diversion Cancel Multiple CPU settings No of PLC No ofPLC 4 Online module changef T Enable online module change with another PLC When the online module change is enabled with another PLC Host CPU number HO status outside the group cannot be taken PLC No 1 1 0 sharing when using Multiple CPUs P AICPUs can read all inputs Operating mode Enot oparaion mode ex ho sop PL T AIICPUs can read all outputs VV Ali station stop by stop error of PLET J All station stop by stop error of PLC2 Muliple CPU high speed transmission area setting Communication area setting refresh setting
207. eiBoid Aq Aiowaw pareys 142 Bursn uogeoiunuiuoo pL AJOWaW peeus 1d2 Buisn se npoui Ndo ueewjeq suoneoiunuluo9 p voco cm c For the High Performance model QCPU Process CPU Basic model QCPU Universal model QCPU QOOUCPU QO1UCPU Q02UCPU parameter setting can be ignored since the user setting area of the multiple CPU high speed transmission area is not available 4 40 3 Assurance of data sent between CPUs The old data and the new data may be mixed data separation in each CPU due to the timing of receiving data from the other CPU and reading in the host CPU The following shows the method to realize the data consistency of the user data for the data transmission in the multiple CPU high speed transmission function a Preventing 32 bit data separation Accessing to the user setting area of the multiple CPU high speed transmission area with placing the address of even number in front for example address 10002 can realize the data consistency for 32 bit data DMOV DO USEL11810002 Device memory CPU shared memory Va G10001 G10002 Even address G10003 e eed a 4 41 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES b Preventing separation for data exceeding 32 bits 1 Using user setting area Programs are read from the start of user setting area With the write instruction send data are written from the last address to the start address of the user setting area Therefore data separation can
208. ejouuo2 9 einpoui A ddns 190g p Ajdwe d1d Aduie 91d einpou Jejonuoo 9 e npoui A ddns 190g No of CPUs a The number of CPUs shows the value set by the multiple CPU setting 1 2 The High Performance model QCPU and Process CPU can be mounted 3 The High Performance model QCPU Process CPU and Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU can be mounted 4 The Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T can be mounted 3 10 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3 1 3 When CPU No 1 is Universal model QCPU The mounting position of each CPU module is shown is Table3 4 1 2 3 4 5 Mounting position of Universal model QCPU Only one QOOUCPU Q01UCPU Q02UCPU can be mounted on the CPU slot the right side slot of the power supply module As for other than QOOUCPU Q01UCPU QO2UCPU up to four modules can be mounted from the CPU slot the right side slot of the power supply module to slot 2 of the main base unit Mounting position of High Performance model QCPU and Process CPU The High Performance model QCPU or the Process CPU cannot be mounted when the QOOUCPU Q01UCPU QO2UCPU is used as the CPU No 1 When the QOOUCPU Q01UCPU QO2UCPU is used up to three modules the High Performance model QCPU s and or the Process CPU s can be mounted on slots 0 to 2 Mounting position of Motion CPU Only one Motion CPU can be mounted on slo
209. eo eo e Q eo e a l JE JE US E TR S sd co Ie armi uc z ame Q series power CPU module 4 1 supply module CPU module 3 CPU module 2 CPU module 1 E Extension base unit 32 point modules are mounted on each slot Q612B 12 slots occupied ist i 12 13 14 15 16 17 18 19 20 21 22 23 extension N W E e e a E E a e E o oO ej mnm jrjo mloar io ui r io SEES Ed aca sex ee CNN ENL SER EN O O 2 2 S S S S S 2 2 2 ese sj ee Doo falio olieioiiollio rege o o0 N sxiojojazojulejam sio c S9 w e aqj ae ae o0 S r A 3 Q55B 5 slots occupied FF Q68B 8 slots occupied E 24 25 26 27 28 extension 45 46 47 48 49 50 51 52 extension m am o0 o0 wpb yoyo ow wmyJul uw m el ul u uw foo ray fay me ey fool i6 iriojmioau i cd N N N oo Oxo 00 00 t0 tO 10 CO CO o o 9e e e se g js9 ees ses 2 2 2 les dtd 2 8 al slg E 1813121818138 PH S Q alaa 2 2 B S S S SIB Sisal e2 5 o0 3 Q68B 8 slots occupied 12 aq Q68B 8 slots occupied
210. er 2 Note5 4 The CC Link IE controller network cannot use the Process CPU Notes 5 Since the Universal model QCPU does not support transfer between data links adding the number of points for transfer between data links is unnecessary 5 8 eui ueog peBuojoJd 104 siojoe4 Z S 5 9 3 CC Link auto refresh a Auto refresh time on CC Link network The amount of time required for performing the refresh process between QCPU and CC Link master local modules Refer to the following manual for details on the auto refresh time for CC Link C gt QJ61BT11N CC Link System Master Local Module User s Manual b Calculation of auto refresh time The amount of time required for the auto refresh process will be prolonged only by the following amount of time when requests for refreshing are issued by other CC Link modules at the same time on a multiple CPU system Extension time No of transmission reception word points x N5 x No of other CPUs u s The number of transmission reception words is the transfer data below RX RY SB 16 SW Link refresh data Use the values in Table5 11 for N5 Table5 11 Time prolonged in simultaneous refresh request with the CC Link module of other CPU N5 QCPU System with main base unit System including extension only base unit s QOOCPU Q01CPU Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU 0 54 us 1 304s QOOUCPU Q01UCPU
211. er 01 0ZL 3 3 3 S o o o o iL E o5 2 Ellar 0001 A 9 A oe hs 9 e 330103 9 9 9 ma c 2 o o o Sv oo Ks o e 4a 09 co co co eg S His S h aeo m E D 3 Gr Eo T 2 J8 01OV rae ra ra E SE 2 no E co co co o sd X to 2 5 5 e o E ss Ww a ee Co E e E le _ m Q _ M roo z 2 E z 5 2 34 Table2 10 Restrictions on system configuration available base units extension cables and power supply modules CPU number CPU module1 CPU No 1 CPU module 2 CPU No 2 CPU module 3 CPU No 3 CPU module 4 CPU No 4 Maximum number of 7 extension stages extension stages Maximum number of 65 No of CPUs mounted I O modules Available main base unit model Type not requiring power supply module Q52B Q55B Available extension T iri dundant ype requiring redundant power supply Q68RB module Q38RB base unit model Available extension QCO05B QC06B QC12B QC30B QC50B QC100B cable model Available power Q63RP Q64RP supply module model Precautions Do not use an extension cable longer than 13 2m 43 31 ft When using an extension cable keep it away from the main circuit high voltage and large current line Set the number of extension stages so as not to be duplicated Although there is no restriction on the connection order of the Q5L TB and the Q6RLIB check the availability of them by referring to QCPU User s Manual Hardware Design Maintenance and Inspe
212. er setting for the Basic model QCPU High Paformance model QCPU Process GPUS molas ee ah ee ee statt 8 3 8 2 2 Parameter setting for the Universal model QCPU c ccccccsesesssssseseseseseseseseaeseeeeesesees 8 15 8 23 Reusing preset multiple CPU parameters 8 23 Communication program examples using auto refresh ssssssee 8 28 8 3 1 Program examples for the Basic model QCPU High Performance model QCPU and Process GPU oa co AE E Ded Se ce 8 28 8 3 2 Program examples for the Universal model QCPU ccccccsssesssssseseseseseseseseseseeeeesesees 8 34 INDEX A 14 Index 1 to Index 2 MANUALS To understand the main specifications functions and usage of the CPU module refer to the basic manuals Read other manuals as well when using a different type of CPU module and its functions Order each manual as needed referring to the following lists The numbers in the CPU module and the respective modules are as follows Number CPU module 1 Basic model QCPU 2 High Performance model QCPU 3 Process CPU 4 Universal model QCPU Basic manual Other CPU module manuals Manual name Deceannon CPU module lt Manual number model code gt kl diii 1 2 3 4 gi User s manual Specifications of the hardware CPU QCPU User s Manual Hardware Design Mainte modules power supply modules base units nance and Inspection extension cables an
213. ersion 1 13P or later GX Configurator SC Version 1 13P or later GX Configurator CT Version 1 13P or later GX Configurator TI Version 1 13P or later Be ce CBU GX Configurator TC Version 1 13P or later GX Configurator FL Version 1 13P or later GX Configurator QP Version 2 13P or later GX Configurator PT Version 1 13P or later GX Configurator AS Version 1 13P or later GX Configurator MB Version 1 00A or later GX Configurator DN Version 1 13P or later 2 50 2 When Universal model QCPU is used Table2 20 Applicable GX Configurator continued Version used in combination with Universal model QCPU Q03UDE Q04UDEH Q02U Q03UD Q00U Q01U Q13UDH QO6UDEH Product Q04UDH Q10UDH Q20UDH Q26UDHCPU Q13UDEH QO6UDHCPU in i Q10UDEH in use Q26UDEHCPU in use Q20UDEHCPU use GX Devel Version 8 48A Version 8 62Q Version 8 68W Version 8 78G es or later or later or later or later GX Configurator AD Version 2 05F or later Version 2 05F or later Version 2 05F or later Version 2 05F or later 4 GX Configurator DA Version 2 06G or later Version 2 06G or later Version 2 06G or later Version 2 06G or later 4 GX Configurator SC Version 2 12N or later Version 2 12N or later Version 2 17T or later Version 2 17T or later 4 GX Configurator CT Version 1 25AB or later Version 1 25AB or later Version 1 25AB or later
214. esjeAum ainpow Ajddns samod m icpu o 112 3 s s SI pouu fo Od s 9 npoui NdI Adw 21d z dO epow JesjeAum ainpow Ajddns amod ainpow Jejoguo2 2 z NdOD epow Jesjenum ainpow Ajddns 4amod No of CPUs a No of CPUs indicates the value set in the multiple CPU setting of the PLC parameter 2 Universal model QCPU except the Q02UCPU can be mounted ri 3 Universal model QCPU except the QO2UCPU and Motion CPU Q172UDCPU Q173UDCPU can be mounted 4 High Performance model QCPU and Process CPU can be mounted 5 The PC CPU module occupies 2 slots 6 The PC CPU module PPC CPU852 MS 512 can be mounted 3 1 Mounting Position of CPU Module 3 1 3 When CPU No 1 is Universal model QCPU 3 17 3 2 CPU No of CPU module a CPU No allocation CPU numbers are allocated for identifying the CPU modules mounted on the main base unit in the multiple CPU system CPU No 1 is allocated to the CPU slot and CPU No 2 No 3 and No 4 are allocated to the right of the CPU No 1 in this order 9 Note3 1 CPU slot CPU No 1 Slot 0 CPU No 2 Slot 1 CPU No 3 Slot 2 CPU No 4 Slot number o v c o N w ES ooo0000 ooo0000 ooo0000 ooo0000 1 EE 4 CPU number Figure 3 15 CPU No allocation The CPU No is used for the following applications Specifying the connect
215. etting completed and close the multiple CPU setting window CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM From previous page Q parameter setting Select I O assignment and display the I O PLC name PLC system PLC file PLCRAS Device Program Boot fle SFC 1 0 assignment assignment setting window Timer limit setting Ee 100 mms 1ms 1000ms Common pointer No P After 0 4095 High 10 00 ms 0 01ms 100ms i n speed Points occupied by empty slot 16 v Points RUN PAUSE contacts System interrupt settings RUN X XO X1 FFF PAUSE X XO X1FFF Fixed scan interval Latch data backup operation valid contact 1000 ms 05ms 1000ms Di Dee I 400 ms 0 5ms 1000ms Remote reset 200 ms 0 5ms 1000ms Al Goo a 700 ms D5ms 1000ms Output mode at STOP to RUN Previous state Interrupt program Fixed scan program setting C Recalculate output is 1 scan later High speed execution r ir if s Service processing settin Intelligent function module setting m ve idc LS io Interrupt pointer setting scan time proceeds C Specify service process time ms 0 2ms 1000ms Module synchronization Soni JV Synchronize intelligent module s pulse up Meno etal ag times 1 10 times Settings should be set as same when Execute it while waiting for constant scan setting using multiple CPU Acknowledge XY assignment 5 Deut Check End Cancel Q paramete
216. evo E 08190 Sant Cugat del Vall s Barcelona Phone 972 0 3 922 1824 Phone 902 131121 34 935653131 Phone 420 595 691 150 Phone 381 0 26 617 163 Fax 972 0 3 924 0761 Fax 420 595 691 199 Fax 381 0 26 617 163 SS B TECH A S CZECH REPUBLIC AutoCont Control slovakia i ELECTRONICS Ltd VOR MITSUBISHI ELECTRIC EUROPE B V UE rus aia 2 Ha umanut P 0 B 6272 UK Branch IL 42160 Netanya Travellers Lane C2 58001 Havl k v Brod SK 02601 Dolny Kubin Phone 972 0 9 863 39 80 ic es so ene DUET c SIT at Phone 44 0 1707 27 61 00 ak 006S arte Fax 44 0 1707 27 86 95 s TUNE A DENMARK n DUM S 0 SLOVAKIA ykkegarasvej 1 1 ajanskeno Missi dud CORPORATION JAPAN DK 4000 Roskilde SK 92101 Piestany AFRICAN REPRESENTATIVE Phone 45 0 46 75 76 66 Phone 421 0 33 7742 760 en M Chuo Ku Fax 45 0 46 75 56 26 Fax 421 0 33 7735 144 CBI Ltd SOUTH AFRICA MET e MI Beijer Electronics Eesti OU ESTONIA INEA d o o SLOVENIA Private Bag 2016 5 24 1600 Isando Fax 81 3 622 160 75 P rnu mnt 160i Stegne 11 Phone 27 0 11 928 2000 EE 11317 Tallinn SI 1000 Ljubljana MITSUBISHI ELECTR AUTOMATION Inc USA hone 4372 0 6 51 81 40 Phone 386 07 513 8100 Fax 27 0 11 392 2354 500 Corporate Woods Parkwa A 13 DELHI ee Fax 372 0 6 51 8149 Fax 386 0 1 513 8170 Phone 1 847 478 2100 Beijer Electronics OY FINLAND Beijer Electronics AB SWEDEN Fax 1 847 478 22 53 Jaakonkatu 2 Box 426 FIN 01620 Van
217. forced ON OFF status For the forced ON OFF of external I O refer to the following manual User s Manual Function Explanation Program Fundamentals for the CPU module used e npouJ pejjoujuoo uou ui ebuel sseooy Z YE Sse npo N Jeujo pue ejhpojw ndo Jo buey sseooy tpe b When Not all CPUs can read all Inputs has been set It is not possible to loads ON OFF data from input modules and intelligent function modules being controlled by other CPUs remains at OFF 3 25 2 Loading output Y The I O sharing when using Multiple CPUs setting in the PLC parameter s Multiple CPU settings determines whether output can be loaded from output modules and intelligent function modules being controlled by other CPUs Multiple CPU settings No of PLC No of PLC Ei E Operating mode Error operation mode at the stop of PLC m V All station stop by stop error of PLC2 v All station stop by stop error of PLC v All station stop by stop error of PLC4 JSettings should be set as same when using multiple CPU Online module changef Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 120 sharing when using Multiple CPUs All CPUs can read all inputs AI CPUs can read all outputs Communication area setting refresh setting Change screens Setting gt I Set starting devices for
218. from CPU No 3 e en 5 eo o PLC No 1 Receive PLC No 2 Send PLC No 3 Receive Refresh device PLC No 2 lt Shared memory PLC No 3 Set receive device from PLC No 3 Auto refresh point Start End 2 M64 M35 32 h Receive setting of CPU No 3 PLC No 1 Receive PLC No 2 Receive PLC No 3 Send Refresh device PLC No 3 gt Shared memory PLC No 3 Set send device to the other PLC Auto refresh point Sat End 2 M64 M95 32 D64 D95 i Send setting from CPU No 3 1 Auto refresh setting of CPU No 1 2 Auto refresh setting of CPU No 2 3 Auto refresh setting of CPU No 3 Figure 4 36 Auto refresh setting related to sending and receiving CPU No 3 data Leaving the second row of PLC No 2 blank lt Flow of sending data from CPU No 3 to other CPUs gt For flow of sending data from CPU No 3 refer to 3 Flow of sending data from CPU No 3 to other CPUs on the previous page PLC No 1 Multiple CPU high speed transmission area PLC No 1 User free area Auto refresh area PLC No 2 User free area Auto refresh area PLC No 3 fi serrera y Auto refresh area Device Bo to CPU No 1 send data B1F B20 to CPU No 2 receive area w a wo B40 to CPU No 3 receive area
219. g b Distribution of memory It is possible to increase the amount of memory used throughout the entire system by distributing the memory used over several CPU modules Used Empty memory Extendable for each CPU module memory 8 a g 8 E J 8 8 m E i B E H s E Used p I g memory Used memory One CPU module is added Extension of program memory Extension of device Ls J Figure 1 9 Distribution of memory 4 Enables system configuration through function distributing By distributing the functions control for production line A and control for production line B is performed on differ ent CPU modules allowing easy program development 1 9 uleis s fido ejdnjnuu jo seunjeej Z4 5 Communication between CPU modules in the multiple CPU system The following data transfer can be made between CPU modules in the multiple CPU system a Data transfer between CPU modules The following data transfer can be made between CPU modules in the multiple CPU system b Reading data in another CPU The QCPU can read data in another CPU with the following instruction when necessary The read instruction from another CPU shared memory Multiple CPU shared device
220. gnment of the data communications between CPU modules HEPC GX Developer 7 Slot number CPU 0 1 2 3 4 5 6 2 3 D Input output A D D A Input Output oO n zlo o w wo l l 8 NIS 3 93 t x t pelei k e 2 x gt alo 9 2 oc og 2 2 o o N e 2 2 o olo ajc o z S 3 a D x gt x gt Number of 16 16 16 16 16 16 slot points points points points points points points NEN ENBENBENEN Control CPU setting Figure 8 18 Configuration example of multiple CPU system 1 I O assignment and auto refresh settings I O assignment of each module and setting example of the auto refresh area are shown in Figure 8 19 For the I O assignment settings refer to Section 3 3 For the auto refresh area settings refer to Section 4 1 3 Q parameter setting PLC name PLC system PLC fie PLE RAS Device Program Boot fle SFC 1 0 Assignment 170 assignment Type Model name Points Start wa E00 3l 3E10 points Switch setting Detailed setting 16points TEpoints 16points 16points T6points Leaving this setting blank will not cause an error to occur Base setting Assigning the 1 0 address is not necessary as the CPU does it automatically Base model name Power model name Extens sion cable Base mod
221. gram For the restrictions on creating the program refer to the following manual lt gt User s Manual Function Explanation Program Fundamentals for the CPU module used 4 54 jdnueju snououugou S Nd eidniniN rz p 4 5 Multiple CPU Synchronized Boot up Multiple CPU synchronized boot up function synchronizes the start ups of CPU No 1 to CPU No 4 Since this function monitors the startup of each CPU module when another station is accessed by manual operation an interlock program which checks the CPU module startup is unnecessary With the multiple CPU synchronized boot up function the start up is synchronized with the CPU module of slow start up therefore the system start up may be slow Point Multiple CPU synchronized boot up function is to access each CPU module in a multiple CPU system without an inter lock This function is not for starting an operation simultaneously among CPU modules after start up The multiple CPU synchronized boot up is available when the following CPU modules are used e Universal model QCPU except QOOUCPU Q01UCPU QO02UCPU Motion CPU Q172DCPU Q173DCPU 1 Multiple CPU synchronized boot up setting To use the multiple CPU synchronized boot up function check from No 1 to No 4 of Target PLC on Multiple CPU settings in PLC parameter of GX Developer Synchronize Multiple CPU boot up is set to No 1 to No 4 at default Multiple CPU synchronous startup settina
222. gs should be set as same when using multiple CPU Online module change Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 120 sharing when using Multiple CPUs All CPUs can read all inputs AI CPUs can read all outputs Communication area setting refresh setting Change screens Setting v I Set starting devices for each PLC CPU specific send range Auto refresh area Caution Dev staring Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y D W A ZR The unit of points of CPU specific send range is word Import Multiple CPU Parameter Check en Cancel Figure 6 1 No of CPUs setting screen 6 6 Dunes SNdI Jo JequnN L9 IS JejeujeJeg L 9 2 Reserving empty slot When an empty slot is reserved for the purpose of mounting additional CPU modules in the future set PLC Empty on the I O assignment tab screen in the PLC parameter dialog box For example when setting 4 as No of CPUs in use of High Performace model QCPU and reserving one of them for future use set CPU Empty to slot 3 Q parameter setting PLC name PLC system PLC file PLC RAS Device Program Boot file SFC 1 0 assignment 1 0 Assignment Slot T Stary PLENo1
223. guration of peripheral devices 2 39 CHAPTER2 SYSTEM CONFIGURATION 3 When using the Process CPU Process CPU Memory card 1 RS 232 cable Q USB cable 2 EPC GX Developer GX Configurator PX Developer 3 numuumuumuuumuuu gt ZZ Memory card 1 PC card adapter G 1 Do not format the ATA card by other than GX Developer L gt QCPU User s Manual Hardware Design Maintenance and Inspection 2 For writing into memory card by GX Developer and information on USB cables refer to the operating manual of the GX Developer 3 The available version varies depending on the system configuration 7 s Section 2 3 Figure 2 25 Configuration of peripheral devices 4 When using the Universal model QCPU a For the QnU D H CPU WiUniversal model QCPU G Memory card RS 232 cable O USB cable t IPC GX Developer GX Configurator 3 Seoiep Jeeudued jo uoneunbyuo0g zz nuunuuuuuuuuuuuu gt ZZ Memory card 1 PC card adapter lt lt 1 Do not format the ATA card by other than GX Developer C gt QCPU User s Manual Hardware Design Maintenance and Inspection 2 For writing into memory card by GX Developer and information on USB cables refer to the operating manual of the GX Developer 3 The available version varies depending on the system configuration gt Section 2 3
224. h leads to takt time shortening of equipment CPU No 1 CPU No 2 SS So Se VEI ee E qoo eet es ae de VE Oe re ee cry Sequence program Multiple CPU high Multiple CPU high Sequence program X0 speed transmission Speed transmission X100 oH 9 Y20 i Data transfer E oH O lt f Data transfer f pe Naad f l l Data transfer z I FN ENDH J Parallel processing with a sequence program Figure 1 5 Multiple CPU data transfer Point P Speeding up data transfer between multiple CPUs is available when the following CPU modules are used e Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172DCPU Q173DCPU CHAPTER1 OUTLINE b Enabling synchronous processing with a motion control An interrupt program which is synchronized with the operation cycle of a motion controller multiple CPU syn chronous interrupt program can be executed Command l O from a motion controller can be synchronized with the operation cycle of the motion controller which enables high speed data transfer independent of scan time Motion Operation cycle controller p y of a motion controller Reading an ka s signal Motion SFC program i i Multiple CPU high speed transmission I SS Multiple CPU high l l speed transmission Universal 1 model QCPU Multiple CPU high
225. h the Process CPU select Enable online module change with another PLC 6 2 6 3 b For Universal model QCPU The Table6 2 shows the PLC parameter settings that are required when the Universal model QCPU is used Table6 2 Setting list for the multiple CPU and I O Assignment Necessity Necessity PLC parameter 7 of same Reference of setup _ 49 setting I O Assignment Type Oo Model name si aE Points aa O StartXY Fu oO Base setting QnUCPU User s Base model name oe Manual Function I O assignment Fower model name mu Explanation Program Extension cable Fundamentals slots O Switch settings ee Detailed settings Error time output mode lt H W error time PLC operation mode I O response time so Control PLC Oo O Section 6 1 6 QnUCPU User s Manual Function PLC system Points occupied by empty slot O Explanation Program Fundamentals CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM Necessity Necessity PLC parameter of same Reference of setup or setting No of PLC Q Q Section 6 1 1 Host CPU number Operation mode A O Section 6 1 2 Multiple CPU synchronized boot up A O Section 6 1 7 Online module change A Q Section 6 1 3 All CPUs can read all inputs A A Section 6 1 4 All CPUs can read all outputs A A Multiple CPU high speed transmission area sett
226. he PC CPU module PPC CPU852 MS 512 can be mounted 3 13 Table3 5 Mounting position of CPU module When except the QOOUCPU Q01UCPU Q02UCPU is mounted on the CPU No 1 CPU o 1 2 3 J Slotnumber Mounting position of CPU module Jejoguo2 2 z 1d90 epow JesueAiu popu o 1 2 jnpow jddns 4amod jnpow Jejouoo 9 z 1dOO epow Jesjenu ainpow A ddns je og ex 9INPOW ido id90 z 1d90 epou JesaeAu ainpow Ajddns 48M0d ff esame fido z 1d90 epow F Jesanluy ajnpow A ddns saMmod einpoui Jejouo2 2 2 2 NdOO Bpow JesueAiu einpou4 A ddns jeog z 1dOO epow Jesaenu icu o 1 2 e npoui A ddns 190g 2 z 1d90 pow Jesjenu ainpow Aiddns jeog z 1dOO epow Jesueniu z 1dOO epow Jesueniu einpoui Kjddns 19 Mog zx dOO Jepou JesyeAiu 3 e npoul A ddns 189 og ainpow Jejouo2 9 gt z 1d90 epow BS JesueNum e npoui A ddns 19 0d e 9 npoui dO Aduie 91d 2 z 1d90 Iepou JesueAiu e npoui A ddns 19 0d exPINDOW dO z 1dO0 epouw JesueAiu FEIERN NN jnpow A ddns jewog org 81NPOW fd9 Od z 1dOO epow Jesueniu e npoui A ddns 180g zx f1dOO epow Jesjenu ainpow A ddns je og s PINDOW Ndo ex PINPOW Nd z 1dOO epow JesueAiu ainpow A ddns 190g gt I z NddO pow Jesjenu einpoui A ddns 160g 2 z d90 Bpow Jesueniu einpoui Kjddns jewog
227. he manual for the intelligent function module 1 When Basic model QCPU Hogh Performance model QCPU and Process QCPU are used Table2 20 Applicable GX Configurator Applicable software version QCPU Product name Version GX Configurator AD Version 1 10L or later GX Configurator DA Version 1 10L or later GX Configurator SC Version 1 10L or later GX Configurator CT Version 1 10L or later GX Configurator TI Version 1 10L or later Basic model GX Configurator TC Version 1 10L or later QCPU GX Configurator FL Version 1 10L or later GX Configurator QP Version 2 10L or later GX Configurator PT Version 1 10L or later GX Configurator AS Version 1 13P or later GX Configurator MB Version 1 00A or later GX Configurator DN Version 1 10L or later GX Configurator AD SWOD5C QADU 20C or later GX Configurator DA SWOD5C QDAU 20C or later GX Configurator SC SWOD5C QSCU 20C or later MN GX Configurator CT SWOD5C QCTU 20C or later GX Configurator TI Version 1 00A or later S A ee GX Configurator TC SWOD5C QCTU 00A or later model QCPU GX Configurator FL SWODSC QFLU 004 or later 2 GX Configurator QP Version 2 00A or later 2 GX Configurator PT Version 1 00A or later 9 GX Configurator AS Version 1 13P or later GX Configurator MB Version 1 00A or later 2 GX Configurator DN Version 1 00A or later z GX Configurator AD Version 1 13P or later S GX Configurator DA V
228. he multiple CPU high speed transmission area by auto refresh cannot be made with the CPU modules except the Universal model QCPU except the QQQUCPU Q01UCPU Q02UCPU and Motion CPU Q172DCPU Q173DCPU mounted on the multiple CPU high speed main base unit When these modules have been mounted on the multiple CPU high speed main base unit set 0 to the relevant CPU by the point field in CPU specific send range of Multiple CPU high speed communication area setting Multiple CPU high speed transmission area setting Communication area setting refresh setting w Use multiple CPU high speed transmission CPU specific send range User setting area Auto refresh PLC Set 0 for the CPU modules except the Pc pointik 1 0 No point u3EO 3072 G10000 G13071 O SettingiSend QOOUCPU Q01UCPU Q02UCPU and U3E1 3072 G10000 G13071 0 Settnaffieceive Motion CPU Q172DCPU Q173DCPU Universal model QCPU except the No3 olux2 o j SecttingiReceivel No4 uses 3072 610000 613071 0 Setting Receive Set auto refresh setting if itis needed No setting Already set Total SK points Advanced settings Assignment confirmation The total number of points is up to 12K Figure 4 23 Setting 0 to point field for No 3 For Communication by auto refresh using CPU shared memory refer to Section 4 1 2 4 23 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 1 Communication using auto ref
229. i CPU 0 1 2 3 4 rans Slot number 1 O number 00 to 1F 20 to 3F Slim type power supply module CPU module 3 CPU module 2 CPU module 1 Figure 2 12 System configuration example for using Q3LISB Table2 6 Restrictions on system configuration available base units extension cables and power supply modules CPU number CPU module 1 CPU No 1 CPU module 2 CPU No 2 CPU module 3 CPU No 3 Maximum number of extension stages Extension not allowed Maximum number of Q32SB 3 No of CPUs mountable I O Q33SB 4 No of CPUs modules Q35SB 6 No of CPUs Available main base Q32SB Q33SB Q35SB unit model Available power Q61SP supply module model Precautions The slim type main base unit has no extension cable connector The extension base unit and GOT cannot be bus connected Since the current consumption of the CPU module exceeds the rated output current of the power supply module Q61SP mounting 4 CPU modules is not allowed When using the C Controller module mounting three CPU modules is not allowed No of CPUs indicates the number of CPU modules set in the No of PLCs of the GX Developer 2 19 CHAPTER2 SYSTEM CONFIGURATION 4 When using the Multiple CPU high speed main base unit Q30DB a System configuratio
230. ice When the CPU shared Theato refresh area Caution Dev stating BOJ memory is set to 2 4416 points for all CPU modules J Port Stat End St ea E ine be 4416 words Dif Gp wep amp mp se device is specified on Setting units of 2 points 2 words Ne2 2 ooo 0001 B20 BF the CPU device the number of the bit device points is 32 Basic model QCPU 320 points Motion CPU 2048 points PC CPU module 2048 points Since CPU No 3 has 0 point it is not refreshed Figure 4 7 Setting of send points For High Performance model QCPU or Process CPU or Universal model QCPU The number of send points is a maximum of 2 k points 2 k words for a total of four ranges for each CPU module making a total of 8 k points 8 k words for all CPUs Change TH Setting Set starting devices for each PLC Send range for each PLC PLC side device wc The auto refresh area Caution Dev stating BOJ LA RI Se ii Set End B Noi 2N Hun NENNEN NNI Nod X 2 000 on 820 3H UNA 8 310 410 4 31 Cosme Esca ENS SS Since CPU No 3 and 4 have 0 point it is not refreshed 2k points 2k words per module 8k points 8k words for all CPUs Setting units of 2 points 2 words When the CPU shared memory is set at 2 points and the bit device is specified on the CPU device the number of the bit device points is 32 points Figure 4 8 Setting of send points
231. ightening can damage the screw and or module resulting in drop short circuit or malfunction Startup and Maintenance Precautions N CAUTION Before performing online operations especially program modification forced output and operation status change for the running CPU module from the peripheral connected read relevant manuals carefully and ensure the safety Improper operation may damage machines or cause accidents Do not disassemble or modify the modules Doing so may cause failure malfunction injury or a fire Use any radio communication device such as a cellular phone or PHS Personal Handy phone System more than 25cm 9 85 inches away in all directions from the programmable controller Failure to do so may cause malfunction Shut off the external power supply for the system in all phases before mounting or removing the module Failure to do so may cause the module to fail or malfunction A module can be replaced online while power is on on any MELSECNET H remote l O station or in the system where a CPU module supporting the online module change function is used Note that there are restrictions on the modules that can be replaced online and each module has its predetermined replacement procedure For details refer to the relevant sections in the QCPU User s Manual Hardware Design Maintenance and Inspection and in the manual for the corresponding module After the first use of the product do not moun
232. in the multiple CPU system except some parts gt Section 6 1 Multiple CPU setting No of PLC I Operation mode Multiple CPU synchronous startup setting Online module change Multiple CPU high speed I O sharing when using Multiple CPUs transmission Multiple CPU high speed transmission area setting Send range each PLC Auto refresh setting Point Start Advanced setting System area Refresh setting Send range each PLC PLC side device l O assignment I O Assignment Detail settings amp Control PLC Basic setting slots PLC system Points occupied by empty slot Mandatory setting items Same setting items for each CPU module Figure 8 7 List of parameters required for multiple CPU system 8 16 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM 3 When creating a new multiple CPU system Start up of GX Developer lt gt The operating manual of GX Developer Open the PLC parameter setting window for parameters of GX Developer lt gt The operating manual of GX Developer Q parameter setting Eq Select PLC system
233. indow and display the detail setting window CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM From previous page Intelligent function module detailed setting Control PLC mandatory item em Select control PLC PLC No 1 to PLC No 4 Slot Type output vo response ae PLC for each slot Note8 5 le For the intelligent function module of function version A set Control PLC to PLC No 1 For the AnS A series compatible module set PLC No 1 v Control PLC to all same High Performance ait model QCPU Note8 6 PLC No 2 v X X M v PLC No 2 v x X X PLE PLC No 1 PLC PLC No 2 PLE PLC No 3 PLC PLC Empty 3 3 Empt 4 4 Input 5 5 Output B 6 Input 77 Output 3 8 8 Intelli 10 3 3 Input 11 10 10 Output 12 110 11 13 1212 14 130 13 15 14 14 settings should be set as same when using multiple CPU sis Set parameters for non multiple CPU system PLC No 2 v PLC No 3 v PLC No 3 v PLC No 1 v PLC No 1 v PLC No 1 v PLCNo 1 v Y I 4 4 4 Aidala lalallala 4 4 4 4 4 4 Write set parameters in the hard disk floppy disk Completed Figure 8 4 Parameter setting procedure for new multiple CPU system creation D Notes 5 Since the number of mountable CPU modules is three when using a Basic model QCPU PLC No 4 is not sele
234. ing ooooo00 000000 Station No 1 control station e e e id Oo 0 Oo o o 0 BIB TF ae ig BITE are e ail af Yay HH HE eps 8 i ay Hid E BINE aie mds e BIG RU ES EE L3 o o Oo o o o 2 EENEN 2 2 control CPU setting Station No 3 normal station o H E E a o o Ei fs 3 O i i i 3 Hi E x Li i d 6 Eu Cl o MELSECNET H PLC to PLC network METIO NETI boad boad COM EMT Transmission s peed T5 Eps boad MRETZUM MNETI CCUmk Etenet 24 medie modile modis mode le ratwork Other staionfTo esistence netuok G4 ile Bus Fir mode UCPU noisl ther statin Retytines gt NETHOM NETM Cli zn in Network No fT Staton No 2 ER EE PLC type Multile CPU seting Ja See 8 BENE Lo Tp aa ss cisci ER EO NEW CDU tend F toU Targa PLC REST Detail Figure 3 33 Access through MELSECNET H PLC
235. ing Multiple CPU high speed transmission Multiple CPU suncllois O O settings CPU specific send range O Auto refresh Section 6 1 8 Number of points A C9 Start A Advanced settings A Q Restricted system area A SUR Communication area setting Refresh setting Send range for each PLC A Q Section 6 1 5 PLC side device A 4 Necessity of setup column Items that must be set up for multiple CPU system operations not possible if not set up A Items that may be set up when required for multiple CPU system Items that are the same as single CPU system ISl JejeujeJeg L 9 2 Necessity of same setting column Items that must be the same settings for all CPU modules on the multiple CPU system A Items that must be the same settings for all QCPUs and PC CPU module on the multiple CPU system items that do not have settings for Motion CPUs Items that can be setup up individually for each CPU modules on the multiple CPU system 6 4 3 Multiple CPU parameters check At the time of the multiple CPU system power on reset or mode change from STOP to RUN of CPU No 1 or parameter change whether the multiple CPU parameters are the same settings for all CPUs or not is checked as shown in Table6 3 with items marked and A in the Necessity of same setting column in Table6 1 and 6 2 Consistency check between CPU modules a When all CPUs are the same The multiple CPU system will be
236. ing for constant scan setting using multiple CPU Acknowledge XY assignment Multiple CPU settings Default Check End Cancel NddOD pow jesieAiu 1 eui 10 Bumes JejeueJed ZZ SJejeureJeg ueis S dO eidnin eui dN Bumes zg To next page 8 17 8 18 Q parameter setting PLC name f PLC fie PLC Timer limit setting Low 100 me 1ms 1000ms High 10 00 ms 0 01ms 100ms i RUN PALISE contacts RUN X X0 X1FFF PAUSE X 40 XIFFF From previous page RAS Device Program Bootfile SFC O assignment Common pointer No P After 0 4095 Points occupied by empty slot 7 16 T Points r System interrupt settings Fired scan interval Latch data backup operation valid cont EN m act 100 0 ms 0 5ms 1000ms 40 0 ms 0 5ms 1000ms Remote reset Allow Output mode at STOP to RUN Previous state C Recalculate output 1 scan late rm internal arithi r Intelligent function module setting Interrupt pointer setting L Module synchronization IV Synchrorize inteligent module s pulse up Settings should be set as same when using multiple CPU RAI Fa d x SEXE SI SI Settings should be set as same when using multiple CPU 200 ms 05ms 1000ms 10 0 ms 05ms 1000ms Interrupt program Fixed scan program setting T High speed execution F FF Use special relay p Service processing setting qe Ex
237. ing of a MELSECNET H network system remote I O network Q Corresponding Ethernet Interface Module User s Manual Basic lt SH 080009 13JL88 gt Specifications procedures for data communication with external devices line connection open close fixed buffer communication random access buffer communication and troubleshooting of the Ethernet module Q Corresponding Ethernet Interface Module User s Manual Application lt SH 080010 13JL89 gt E mail function programmable controller CPU status monitoring function communication via MELSECNET H or MELSECNET 10 communication using the data link instructions and file transfer function FTP server of the Ethernet module CC Link System Master Local Module User s Manual lt SH 080394E 13JR64 gt System configuration performance specifications functions handling wiring and troubleshooting of the QJ61BT11N Q Corresponding Serial Communication Module User s Manual Basic lt SH 080006 13JL86 gt Overview system configuration specifications procedures before operation basic data communication method with external devices maintenance and inspection and troubleshooting for using the serial communication module Q Corresponding Serial Communication Module User s Manual Application lt SH 080007 13JL87 gt Q Corresponding MELSEC Communication Protocol Reference Manual lt SH 080008 13JF89 gt Special functions specifi
238. ing outside of the group Access target Disabled Not checked Enabled Checked Input X x O Read x Output Y E Write x x Buffer memory of intelligent Read O O function module Write x x Q Accessible x Inaccessible einpoui pej ou uoo ui eHuel sseooy pye Sse npo N JOUIO pue ejhpoyw nd9 Jo buey sseooy pe 3 23 1 Loading input X The I O sharing when using Multiple CPUs setting in the PLC parameter s Multiple CPU settings determines whether input can be loaded from input modules and intelligent function modules being controlled by other CPUs Multiple CPU settings No of PLC Online module change No of PLC f Enable online module change with another PLC When the online module change is enabled with another PLC n I O sharing when using Multiple CPUs zl i MIAIl CPUs can read all inputs Pega om xime Picea aoa ise All CPUs can read all inputs setting Vv Communication area setting refresh setting All CPUs can read all inputs IV All station stop by stop error of PLC2 i a Change screens Setting gt I Set starting devices for each PLC Not all CPUs can read all inputs setting Iv All station stop by stop error of PLC3 n CPU specific send range PLC side device IV All station stop by stop error of PLC4 PLE Aao meih mea CAR DAENS Paint Start End Start End No 1 U No 2 No 3 it No 4 0 Caution Offset HE
239. ing the S GINT instruction The interrupt program from the QCPU to the PC CPU module can be started QCPU PC CPU module Start request S GINT instruction z Figure 4 47 Operation of S GINT instruction For details and availability of the multiple CPU transmission dedicated instruction refer to the manuals of the C Controller module and PC CPU module 4 51 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4 3 3 Writing reading of device data from QCPU to QCPU The Universal model QCPU can write read device data to from another Universal model QCPU with the multiple CPU high speed transmission dedicated instruction shown on Table4 18 Table4 18 List of multiple CPU high speed transmission dedicated instructions CPU module Universal model QCPU Q03UD E CPU 4 IOR t Basle model QCPU Q04UD E HCPU UN escription High Performance Q00UCPU Q06UD E HCPU model QCPU Q01UCPU Q10UD E HCPU SI 2 Q02UCPU q4sup E HCPU Q20UD E HCPU Q26UD E HCPU D DDRD Reads other CPU device data into the host T s DP DDRD CPU devices E D DDWR Writes host CPU device data into other CPU DP DDWR devices O 1 CPU module whose first five digits of serial number is 10012 or later Figure 4 48 shows operation when CPU No 1 writes device data to CPU No 2 with the DP DDWR instruction E o CPU No 1 CPU No 2 User program HH oPDDWR USEI DO D100 D200 MO 4 4 m 4 S po DO amp N Y D100
240. ion 4 3 2 the PC CPU module C Con instruction 1 type troller module Communication from the Perform communication with the multi Universal model QCPU to Not available ple CPU high speed transmission dedi Section 4 3 3 the Universal model QCPU cated instruction 2 types In addition to factors for the single CPU Writing data during RUN or System refresh processing for CPU Factors for increasing scan UA Scan time fime communication processing modules in Multiple CPU system and Section 5 2 i time setting etc waiting time may increase the scan time 1 No of CPU modules Multiple CPU setting 2 Control CPU detailed I O assign ment setting 3 Out of group I O setting Multiple CPU setting 4 Operation mode for CPU error stop Multiple CPU setting Parameters added for multi 5 Multiple CPU synchronized boot up Parameter Not available Section 6 1 ple CPU system Multiple CPU settings 6 Multiple CPU high speed transmis sion area setting Multiple CPU set tings 9 7 Communication area setting refresh setting Some parameters must be set to the same for all CPU modules while others may be different for each CPU module AnS A series compatible Caution The AnS A series compatible modules cannot be used Section 7 1 module 1 22 2 3 4 5 6 I 8 9 CHAPTER1 OUTLINE No of CPUs indicates the number of CPU modules set at No of PLC in the Multiple CP
241. ion area setting refresh setting All CPUs can read all outputs IV All station stop by stop error of PLC2 v Use multiple CPU high speed transmission JV All station stop by stop error of PLC3 ifi V All station stop by stop error of PLC4 Multiple CPU synchronous startup setting Target PLC V No 1 V No 2 V No3 Set auto refresh setting if itis needed No setting Already set V No 4 3 Total 12K points Advanced settings Assignment confirmation The total number of points is up to 12K JSettings should be set as same when 3 using multiple CPU Import Multiple CPU Parameter Check end Cancel Figure 4 26 CPU specific send range setting screen Table4 7 List of parameter setting display item for CPU specific send renge setting Item Setting description Setting display value CPU specific send Setting range 0 to 14 0k points Sets the number of points of data that each CPU module sends range Setting unit 1 0k point Used when communicating with the other CPU using the program User setting area The value where the number of points set in the auto refresh is Display range 0 to 14335 points subtracted from the CPU specific send range setting is displayed Used when communicating with the other CPU using the auto refresh Auto refresh m Display range 0 to 14335 points Number of points that is set by the auto refresh setting is displayed
242. ion target by GX Developer PC Slot number o pe i ol I oooo000 000000 ooo000 000000 1 CPU number Communicate with CPU No 2 F Multple CPU setting 3333 8 ROS S NETZOH KETO TA NETHOM NETO CCLink fer Accessing host statin Taget PLE PLE NGZ Specify PLC No 2 CPU No 2 Figure 3 16 Transfer Setup with GX Developer p Note3 1 Basic For the Basic model QCPU QOOUCPU Q01UCPU Q02UCPU CPU modules can only be mounted up to CPU No 3 Therefore CPU No 4 is not available 3 18 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM Setting a control CPU in the I O assignment Intelligent function module detailed setting 1 0 response Control PLC time n H PLC No 1 PLCNo2 Control CPU PLCNo3 PLENo4 Control PLC B setting Cancel Figure 3 17 Control CPU setting b Checking host CPU number The QCPU stores the host number in the special register SD395 It is recommended to create a program for checking the host number on the QCPU This will enable easy verification when QCPUs are not mounted correctly and when programs are written into other CPUs with GX Developer In the program shown in Figure 3 18 the annunciator F1 turns to ON when QCPU to which a program is written is
243. ire special attention are described here The reference related to the page or useful information are described here e 0 0606 06006000000000000000000000000000000000000000000000000000000000 9 A 19 GENERIC TERMS AND ABBREVIATIONS indicates a part of the model or version Unless otherwise specified this manual uses the following generic terms and abbreviations Example Q33B Q35B Q38B Q312B Q3 IB Generic term abbreviation Description m Series Q series Abbreviation for Mitsubishi MELSEC Q series programmable controller Generic term for compact types of Mitsubishi MELSEC A Series Programmable AnS series Controller Asees Generic term for large types of Mitsubishi MELSEC A Series Programmable Controller CPU module type CPU module Generic term for the Basic model QCPU High Performance model QCPU Process CPU Redundant CPU Universal model QCPU Basic model QCPU Generic term for the QOOCPU and Q01CPU High Performance model QCPU Generic term for the Q02CPU Q02HCPU QO6HCPU Q12HCPU Q25HCPU Process CPU Generic term for the QO2PHCPU QO6PHCPU Q12PHCPU Q25PHCPU Universal model QCPU Generic term for the QQOUCPU Q01UCPU Q02UCPU QO3UDCPU QO4UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU Q03UDECPU Q04UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU and Q26UDEHCPU Built in Ethernet port QCPU Motion CPU Generic term for
244. it model Q50B Q60B QA1S60B QA60B QA6ADP A50B A60B Q60RB Extension cable type QCO05B QCO06B QC12B QC30B QC50B QC100B Overall distance of extension TA Within 13 2 m cable Power supply module 3 QenP QensP Q6ORP A1S6nP A60P model High Performance model Function version A or later Function version B QCPU n 1 O module Function version A or later Available module Function version B or later f Function version A or later for QD62 Intelligent function module Function version A or later QD62D and QD62E No function restriction for QI60 GX Developer Version 4 or later Version 6 or later GX Configurator AD SWOD5C QADU 00A or later SWO5D5C QADU 20C or later GX Configurator DA SWOD5C QDAU 00A or later 4 SWO5D5C QDAU 20C or later 4 GX Configurator SC SWODSC QSCU 00A or later SWO5D5C QSCU 20Corlate 4 Section 2 3 GX Configurator CT SWOD5C QCTU 00A or later SWO5D5C QCTU 20C or later Available GX Configurator TI Version 1 00A or later software GX Configurator TC SWOD5C QCTU 00A or later GX Configurator FL SWODSC QFLU 00A or later GX Configurator QP Version 2 00A or later GX Configurator PT Version 1 00A or later GX Configurator AS Version 1 13P or later GX Configurator MB Version 1 00A or later GX Configurator DN Version 1 00A or later 1 14 To the next page CHAPTER1 OUTLINE Table1 3 Difference from single CPU system continued Item Single CPU system Multiple
245. itch settings Detailed settings Error time output mode S H W error time PLC operation mode O response time DHT Control PLC O Oo Section 6 1 6 Qn H QnPH QnPRH User s Manual Function PLC system Points occupied by empty slot O Explanation Program Fundamentals S No of PLC Oo Oo Section 6 1 1 e Operation mode O Section 6 1 2 E 0 Online module change go Note6 1 A A Section 6 1 3 o Multiple CPU All CPUs can read all inputs A A 5 Section 6 1 4 settings All CPUs can read all outputs A A Communication area setting Refresh setting Send range for each PLC A O Section 6 1 5 PLC side devices A 1 Necessity of setup column Items that must be set up for multiple CPU system operations not possible if not set up A Items that may be set up when required for multiple CPU system Items that are the same as single CPU system 2 Necessity of same setting column Items that must be the same settings for all CPU modules on the multiple CPU system A Items that must be the same settings for all QCPUs and PC CPU module on the multiple CPU system items that do not have settings for Motion CPUs Items that can be setup up individually for each CPU modules on the multiple CPU system f v GB For the Basic model QCPU the online module change cannot be set For the High Performance model QCPU modules cannot be changed online To change a module online wit
246. itor of GX Developer for correction Debug of each CPU module ss Jv Multiple CPU system is debugged for each CPU module Actual operation Completed 1 For the Basic model QCPU and Universal model QCPU it is the RUN RESET STOP switch For the Motion CPU and the PC CPU module refer to the manual of each CPU module 2 Forthe Basic model QCPU and Universal model QCPU it is the RUN RESET STOP switch Figure 8 1 Procedure to start multiple CPU system CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM 8 2 Setting Up the Multiple CPU System Parameters This section explains the procedures for setting multiple CPU parameter with GX Developer Refer to the GX Developer s operation manual for details on setting up all other parameters 8 2 1 Parameter setting for the Basic model QCPU High Paformance model QCPU Process CPU 1 System configuration The following explains setting procedures of the multiple CPU parameter with a system example of Figure 8 2 HEPC GX Developer Empty slot for addition l of future CPU module cedo 1 2 s 4 5 e z7 Slotnumber model QCPU o 3 o E m a 2 2 o o o n High Performance Process CPU Input module Output module Input module Output module N N EBEB 2 Control CPU Figure 8 2 Configuration example of mul
247. iversal model QCPU Q13UDHCPU Q26UDHCPU and Built in Ethernet port QCPU the C Controller module whose serial number first five digits is 10012 or later can be used PC CPU module PPC CPU686 MS 64 PPC CPU686 MS 128 PPC CPU852 MS 512 Refer to the CPU module manual 1 When using the Motion CPU install OS software For the OS types and versions refer to the manual of the Motion CPU 2 44 SJEMIJOS e qe reAe pue eol ep e qeunBijuoo ez 2 45 d When Universal model QCPU is used as CPU No 1 1 When the QOOUCPU Q01UCPU Q02UCPU is used Table2 15 Available CPU modules CPU module Model Restrictions Universal model QCPU Motion CPU QOOUCPU Q01UCPU Q02UCPU Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T No version restriction Refer to the CPU module manual C Controller module PC CPU module QO6CCPU V Q06CCPU V B PPC CPU852 MS 512 The C Controller module whose serial number first five digits is 10102 or later can be used Refer to the CPU module manual 1 When using the Universal model QCPU together use the following Universal model QCPU First 5 digits of the serial number 09072 or later 2 When using a Motion CPU install operating system software on the CPU For models and versions of the operating system software refer to the Motion CPU manual CHAPTER2 SYSTEM CONFIGURATION 2 When except the QOOUCPU Q01U
248. j No 2 0j a No3 No 4 0j Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y D W RZA The unit of points of CPU specific send range is word Import Multiple CPU Parameter Check End Cancel Online module change T Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs T Al CPUs can read all inputs All CPUs can read all outputs Communication area setting refresh setting Change screens Setting v I Setstatting devices for each PLC CPU specific send range PLC side device PLC Auto reftesh area Caution Dev starting Paint Stat End Start End Not No 2 No 3 No4 0j Caution Offset HEX from starting address of the auto refresh area Refer to the user s manual of the each PLC about the starting address The applicable device of head device is B M Y D W RZR The unit of points of CPU specific send range is word Import Multiple CPU Parameter Check End Cancel l To next page 1 Indicates the case of the Process CPU Enable online module change with another PLC is set disabled not checked for the High Performan
249. l QCPU Host CPU Other CPU CPU shared memory Read OH GO to to Host CPU operation O information area 1FFH G511 2001 G512 to to QCPU Restricted system area O 7FFH G2047 standard area 8005 62048 Auto refresh area x to to User setting area O FFFH G4095 1000H G4096 to to Use prohibited area x 270FH G9999 2710H G10000 to to Multiple CPU high speed O Max transmission area 5FOFH G24335 Communication allowed X Communication not allowed 1 The QOOUCPU Q01UCPU Q02UCPU does not have the use prohibited area and the multiple CPU high speed transmission area Figure 4 3 Configuration of CPU shared memory CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 1 Host CPU operation information area a Information stored in the host CPU operation information area The following information is stored in the host CPU operation infomation area in the multiple CPU system These will all remain as 0 and will not change in the case of single CPU system Table4 2 List of host CPU operation information areas CPU Correspo shared nding Name Detail Description memory special address register The area to confirm if information is stored in the host CPU s operation information area 1H to 1Fu or not 0 Information Information 0 Information not stored in the host CPU s operation i availability availability flag information area
250. liable for compensation of damages caused by any cause found not to be the responsibility of Mitsubishi loss in opportunity lost profits incurred to the user by Failures of Mitsubishi products special damages and secondary damages whether foreseeable or not compensation for accidents and compensation for damages to products other than Mitsubishi products replacement by the user maintenance of on site equipment start up test run and other tasks 5 Changes in product specifications The specifications given in the catalogs manuals or technical documents are subject to change without prior notice 6 Product application 1 In using the Mitsubishi MELSEC programmable controller the usage conditions shall be that the application will not lead to a major accident even if any problem or fault should occur in the programmable controller device and that backup and fail safe functions are systematically provided outside of the device for any problem or fault 2 The Mitsubishi programmable controller has been designed and manufactured for applications in general industries etc Thus applications in which the public could be affected such as in nuclear power plants and other power plants operated by respective power companies and applications in which a special quality assurance system is required such as for Railway companies or Public service purposes shall be excluded from the programmable controller applications In addition applications in
251. loading the output data from the output module the I O composite module and the intelligent func tion modules the PLC parameter s multiple CPU setup is necessary However it is not possible to access non controlled modules in the following ways Outputting data to output modules I O composite module and intelligent function modules Writing data into the intelligent function module s buffer memory CPU 0 1 2 3 4 5 6 7 4 Slot number a a E 8 5 3 B d EN al I FEES E ene mI i 8 Fi ups OY nAi Hy n Onin ub c nb n m i mm il zs z iE OY a WID One a 1 o o IJ fe o 1 1 1 1 2 2 2 lt t Control CPU setting Readable with CPU module 2 Readable with CPU module 1 Figure 1 3 Access to non controlled module c Range of access to other station s CPU module To access to a CPU module on other station from GX Developer access can be made through a network mod ule controlled by any CPU module in the multiple CPU system When other station has multiple CPUs specifying the CPU No allows access to the desired CPU User s manual for each network module 1 4 CHAPTER1 OUTLINE 1 2 Features of multiple CPU system 1 Multi control system a Configuration optimum for system Since each system uses not only one QCPU
252. lowed Table4 14 List of instructions dedicated to Motion CPU CPU module Universal model QCPU 03UD E CPU eel eae ie E Instruction eee QCPU High E Description Q00UCPU Q06UD E HCPU ke d ete Q01UCPU Q10UD E HCPU dais Q02UCPU MR a Process CPU E Q20UD E HCPU Q26UD E HCPU S SFCS O O SP SFCS Requests startup of the motion SFC program D SFCS T O DP SFCS S SVsT a 8 SP SvsT Requests the start of the servo program D SVST T x O DP SVST S CHGV e a SP cHGV Changes the speed of the axes during D CHGV positioning and JOG operations DP CHGV n O S CHGT SP cHGT Changes the torque control value during O O operation and suspension when in the real D CHGT mode v O DP CHGT S CHGA SP CHGA Changes the current values of the halted O O aj axes the synchronized encoder and the cam D CHGA axes T O DP CHGA 4 4 47 The following version restrictions apply to the Motion CPU Q172CPU Q173CPU Q172CPUN T Q173CPUN T Q17H2CPU T Q173HCPU T Version N or later Version M or later No version restriction No version restriction O Available X Not Available CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES Example When using the S SFCS instruction It is possible to start up the Motion CPU s motion SFC from the QCPU QCPU Motion CPU S SFCS instruction Figure 4 45 Operation of S SFCS instruction Point
253. ltiple CPU settings f notes E p For details of the CPU modules applicable to CC Link IE controller network refer to Section 2 4 5 3 CHAPTERS PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM b Calculation of auto refresh time The automatic refresh time of the CPU shared memory is calculated in the following equation 1 For Basic model QCPU Auto refresh time N1 No of transmission word points x N2 N3 No of other CPUs x N4 No of reception word points x N5 us The number of received words is the sum of the numbers of words transmitted by the other CPUs Example When No of CPU is set to 3 and the host CPU is CPU No 1 The number of received words is the sum of the numbers of words sent by CPUs No 2 to No 3 For N1 to N5 use the values in Table5 3 Table5 3 Auto refresh time Basic model QCPU N1 N2 N3 N4 N5 QOOCPU 63 Us 1 13 Us 63 Us 1614s 0 88 4s Q01CPU 57 Us 1 03 Us 57 us 1464s 0 80 4s 2 For High Performance model QCPU Process CPU Auto refresh time N1 No of reception word points x N2 x No of other CPUs N3 No of transmission word points x N4 us The number of received words is the sum of the numbers of words transmitted by the other CPUs Example When No of CPU is set to 4 and the host CPU is CPU No 1 The number of received words is the sum of the numbers of words sent by CPUs No 2 to No 4 Use the values in Table5 4 for N1 to
254. m Fundamentals for the CPU module used b When Not all CPUs can read all outputs has been set It is not possible to load ON OFF data output to output modules and intelligent function modules by other CPUs into the host CPU s output Y remains at OFF e npouJ pejjojuoo uou UM ebuel sseooy Z YE Sse npo N JOUIO pue ejhpojN ndo Jo eBues sseooy pe 3 27 3 Output to output modules and intelligent function modules It is not possible to output ON OFF data to non controlled modules Devices will be turned ON or OFF inside the QCPU when the output from output modules or intelligent function modules controlled by other CPUs is turned ON OFF by as to the output modules or intelligent function modules quence program but this will not be actually output X0 X0 vio va0 H x ON OFF not allowed ON OFF allowed CPU 0 1 2 3 4 Slot number 000000 ooo000 s XO to XF Y10 to Y1F X20 to X2F Y30 to Y3F VINE I I Ex Input Output Input Output Number of slot points 16 points 16 points 16 points 16 points EN EHEN Control CPU setting Figure 3 26 When performing output from CPU No 1 to module 4 Accessing the intelligent function module buffer memory a Reading from buffer memory It is possible to read data from the buffer memory of intelligent function modules being controlled by other
255. m setting C Recalculate output is 1 scan later I High speed execution Floating point arithmetic processing APLC ju Perform intemal arithmetic operations in Use special relay special register from SM SD1000 double precision Intelligent function module setting Interrupt pointer setting Module synchronization JV Synchronize intelligent module s pulse up Settings should be set as same when using multiple CPU Acknowledge XY assignment Multiple CPU settings Default SJejeureJeg ueis s dD Sidyinw eui dN Bumes zg To next page Ndd sseooJd nid20 epow eoueuuojeg YBIH Nd dD pou dseg euj 10 Bumes JejeureJed p Z8 8 5 From previous page Q parameter setting 53 Select Multiple CPU settings and LC fle PLCRAS Device Program Boot fle SFC O assignment display the multiple CPU setting window Timer imit seing Low 100 Common pointer No P Alter 0 4095 E ms 1ms 1000ms High oo xd ms D 1ms 100ms RUN PAUSE contacts ERN pup ss pO Interrupt counter start No C 0 768 PAUSE X WO RTFFF Fixed scan interval 7 128 1000 ms 0 5ms 1000ms UTE 129 400 ms 05ms 1000ms Remote reset 130 200 ms 0 5ms 1000ms m Allo interrupt setting L i 131 00 ms 0 5ms 1000ms Output mode at STOP to RUN Previous state Interrupt program Fixed scan program setting C Recalculate output is 1 scan later T High speed
256. mation area O i O 5FH 95 60H 8 to to Restricted system area x x o BFH 191 1 1 ous 192 Auto refresh area x x x x to to User setting area O O x O 1FFH 511 0 1 O Communication allowed X Communication not allowed 1 Restricted system area is used for communicating with instructions dedicated to Motion CPU Refer to the programming manual of Motion CPU for applications and usage methods of restricted system area used with instructions dedicated to Motion CPU Figure 4 1 Configuration of CPU shared memory For High Performance model QCPU or Process CPU Host CPU Other CPUs CPU shared memory Write Read Write Read 0H OP e u me T Poe to to Host CPU operation X x x O information area FFH 51447 0 A 200H 512 to to Restricted system area x x x Oo Q 7FFH 2047 ss 2 poH 2048 Auto refresh area x x x x 5 a to to 5 User setting area O x x O z FFFH 4095 AJ 25j lt O Communication allowed X Communication not allowed 1 Restricted system area is used for communicating with instructions dedicated to Motion CPU Refer to the programming manual of Motion CPU for applications and usage methods of restricted system area used with instructions dedicated to Motion CPU Figure 4 2 Configuration of CPU shared memory Asowaw peeus 1d2 Buisn se npoui Ndo usemjeq suoNediunwWWwOoyD p 4 4 4 5 For Universal mode
257. memory cards and batteries Refer to the following manual lt QCPU User s Manual Hardware Design Maintenance and Inspection This manual does not describe the functions of the CPU module For the functions refer to the following Manuals for the CPU module used Function Explanation Program Fundamentals CONTENTS SAFETY PRECAUTIONS REVISIONSS ES ee cree ware E Pan ee ee CCE RE TREE ENT INTRODUCTION MAIN WARS ae carr saree cree eee Se aes Oe REC USO EL EC TCs a Ur cg Re ae MANUAISPAGEIORGANIZATIONISS SS A 18 GENEIRIGSRIEIMSIANPIABBRSEVIAIIGNSRE A 20 CHAPTER1 OUTLINE 1 1 to 1 23 1 4 Whatis multiple CPU system nci eter dee tae tee zr e t ed tbt e de 1 1 1 2 Features of multiple CPU system ssssssssssseseeeneeeeeeneneeenen nennen nennen 1 5 1 3 Difference from Single CPU System ssssssssssseseeeeeeneenneeere nennen 1 11 CHAPTER2 SYSTEM CONFIGURATION 2 1 to 2 57 2 1 Systent config ration aree o pe ete E Ee De ade 2 1 2 1 1 System configuration using Basic model QCPU QOOCPU Q01CPU sss 2 1 2 1 2 System configuration using High Performance model QCPU or Process CPU as CPU NOT owe 2 10 2 1 3 System configuration using Universal model QCPU as CPU No 1 sssssssssss 2 24 2 2 Configuration of peripheral devices 2 3 Configurable device and available software sse 2 42 2 4 P
258. meter setting gt Figure 4 34 shows the settings related to sending and receiving CPU No 3 data g to i in Figure 4 34 in the setting example of auto refresh in Figure 4 34 r 7 r zi r PLC No 1 Send PLC No 2 Receive PLC No 3 Receive PLC No 1 Receive PLC No 2 Send PLC No 3 Receive PLC No 1 Receive PLC No 2 Receive PLC No 3 Send Refresh device PLC No 1 lt Shared memory PLC No 3 Refresh device PLC No 2 lt Shared memorylPLC No 3 Refresh device PLC No 3 gt Shared memory PLC No 3 Set receive device from PLC No 3 Set receive device from PLC No 3 Set send device to the other PLC Auto refresh Auto refresh Auto refresh No point Start End No point Start End No point Start 1 2 840 BSF E 1 2 M64 M95 c mi 2 M6 amp 4 2 32 w40 Wor lt 2 32w40 WSF c Im 32 D54 3 3 3 4 n H3 5 5 ms B 6 Le g Receive setting from CPU No 3 h Receive setting of CPU No 3 i Send setting from CPU No 3 1 Auto refresh setting of CPU No 1 2 Auto refresh setting of CPU No 2 3 Auto refresh setting of CPU No 3 Figure 4 34 Auto refresh setting related to sending an
259. minal GOT A series GOT F series and GOT1000 series A 22 CHAPTER1 OUTLINE CHAPTER1 OUTLINE 1 1 What is multiple CPU system 1 Configuration of multiple CPU system A multiple CPU system is a system in which more than one CPU module are mounted on several a main base unit in order to control the I O modules and intelligent function modules Motion CPU PC CPU module QCPU 000000 000000 Figure 1 1 Configuration of multiple CPU 1 1 Eweaysks NdI dyNU srjeuM LL 1 2 2 Available CPU modules in multiple CPU system Table1 1 shows the available CPU modules in multiple CPU system Refer to Section 2 3 for the compatible version of each module Table1 1 Applicable CPU modules CPU module Model Basic model QCPU QOOCPU Q01CPU High Performance model QCPU Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU Process CPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU cv do Universal model QCPU QOOUCPU Q01UCPU Q02UCPU Q03UDCPU Q04UDHCPU QO6UDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU QO3UDECPU Q04UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU Motion CPU Q172CPUN Q173CPUN Q172HCPU Q173HCPU Q172CPUN T Q173CPUN T Q1
260. mmunica device U3Enm GL tion between SR Instructions dedicated to the Motion CPU mod Communication from High CPU 5 types Instructions dedicated to Section 4 2 Performance model QCPU Not available M i ules the communication between multiple Section 4 3 1 to Motion CPU CPUs 3 types Communication from the High Performance model Instruction dedicated to the communi Not available f Section 4 3 2 QCPU to the PC CPU mod cation between multiple CPUs 1 type ule C Controller module In addition to factors for the single CPU Writing data during RUN or system refresh processing for CPU Factors for increasing scan uro Scan time fime communication processing modules in Multiple CPU system and Section 5 2 i time setting etc waiting time may increase the scan time 1 No of CPU modules Multiple CPU setting 2 Control CPU detailed I O assign ment setting 3 Out of group I O setting Multiple p CPU setting Parameters added for multi Parameter Not available 4 Operation mode for CPU error stop Section 6 1 ple CPU system Multiple CPU setting 5 Communication area setting refresh setting Multiple CPU setting Some parameters must be set to the same for all CPU modules while others may be different for each CPU module Use is allowed when the High Perfor AnS A series compatible i Caution Use is allowed mance model QCPU is set to the con Section 7 1 module trol CP
261. module Make the power consumption within the rated output current value of the power supply module The Slim type power supply module and Redundant power supply module cannot be used as a power supply module 2 No Q series power supply module is required for the Q5LTIB type extension base unit 8 The QCPU battery Q6BAT cannot be installed to the PC CPU module 4 For further information on PC CPU module consult CONTEC Co Ltd Tel 81 6 6472 7130 b The PC CPU module and C Controller module cannot be mounted together Figure 2 5 System configuration when Basic model QCPU is used Point When the multiple CPU system is configured using the Basic model QCPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 PC CPU module C Controller module Note that the PC CPU module and C Controller module cannot be mounted together 2 7 CHAPTER2 SYSTEM CONFIGURATION b Outline of system configuration WMain base unit 32 point modules are mounted on each slot Q38DB 8 slots occupied CPU 0 1 2 3 4 5 6 M ncs Slot number LL Hn LL LL LL i Nitel amp 828J 8gJ 8 2 2 Onumber eo o eo o e eo D JIo lIa Q series power supply module Empty space of 16 points CPU module 2 1 CPU module 1 WeExtension base unit 32 point modules are mounted on each slot
262. n G Battery for QCPU Q6BAT Q High Performance PC CPU module C Controller model QCPU 4 5 6 7 module 4 6 itia E Q7BAT SET Bc i U Universal model QCPU Battery holder G9 Q3LIDB type multiple CPU high speed main Battery for QCPU Q7BAT base unit 2 bes Be 2 3 A 5 6 sT 8 Q series power supply input output intelligent function module B type extension base unit 3 B type extension base unit 2 Only one memory card can be mounted Select an appropriate memory card from the SRAM Flash and ATA in accordance with application and capacity When a commercial memory card is used the operation is not guaranteed Use the Q series power supply module for the power supply module Keep the current consumption within the rated output current of the power supply module The Slim power supply module and Redundant power supply module are not available for the power supply module The Q Series power supply module is not required for the Q5L 1B extension base unit The PC CPU module do not accept battery for QCPU and memory card For further information on PC CPU module consult CONTEC Co Ltd Tel 81 6 6472 7130 The PC CPU module and C Controller module cannot be mounted together When the PC CPU module and the Universal model QCPU are mounted together use the PC CPU module PPC C
263. n Basic model Power supply module Basic model module Added PC CPU module Figure 3 4 PLC Empty setting for addition of PC CPU 3 3 3 4 c When adding the C Controller module in the future 1 When mounting the Motion CPU Set slot 1 as PLC Empty CPU o 1 2 j Slot number ICPU o 1 2 jJ 4 Slot number a 2 2 o lt D o Basic model QCPU Power supply Motion CPU PLC empty module module Basic model QCPU Motion CPU C Controller Added C Controller module Figure 3 5 PLC Empty setting for addition of C Controller module 2 When not mounting Motion CPU Set slot 0 as PLC Empty CPU o 1 2_ lt Slot number CPU o 1 2 lt e Slot number 2 2 2 o M 7 z o oO Basic model QCPU Power supply module Basic model C Controller module Added C Controller module Figure 3 6 PLC Empty setting for addition of C Controller module Point When using the Basic model QCPU PLC Empty can be set between CPU modules Therefore even when the Motion CPU will be added to the system where the Basic model QCPU PC CPU module and C Controller module are used the CPU No s of the PC CPU module and C Controller module are not changed and changing the program is unnecessary CPU o 1 2_ lt Slot number cPu o 1 2 j 4 Slot number a a 2 o a o o n Basic model roll 2
264. n matter such as dust or wire chips from entering the module Such foreign matter can cause a fire failure or malfunction Wiring Precautions A protective film is attached to the top of the module to prevent foreign matter such as wire chips from entering the module during wiring Do not remove the film during wiring Remove it for heat dissipation before system operation Mitsubishi programmable controllers must be installed in control panels Connect the main power supply to the power supply module in the control panel through a relay terminal block Wiring and replacement of a power supply module must be performed by maintenance personnel who is familiar with protection against electric shock For wiring methods refer to the QCPU User s Manual Hardware Design Maintenance and Inspection Startup and Maintenance Precautions Do not touch any terminal while power is on Doing so will cause electric shock Correctly connect the battery connector Do not charge disassemble heat short circuit solder or throw the battery into the fire Doing so will cause the battery to produce heat explode or ignite resulting in injury and fire Shut off the external power supply for the system in all phases before cleaning the module or retightening the terminal screws or module fixing screws Failure to do so may result in electric shock Undertightening the terminal screws can cause short circuit or malfunction Overt
265. next page CHAPTER1 OUTLINE Table1 2 Difference from single CPU system continued Item Single CPU system Multiple CPU system Reference Basic model QCPU 320 points a Motion CPU 2048 points Communication using CPU C Controller module 2048 points R shared memory by auto Not available Section 4 1 2 PC CPU module 2048 points refresh Total points of all CPU modules 4416 points Communica With TO S TO and or FROM instruc Communication using CPU tion between Not available tions and instruction using the multiple Section 4 1 4 shared memory by programs CPU mod CPU area device U3En Gr ules Instructions dedicated to the Motion Communication from Basic Not available CPU 5 types Instructions dedicated to Section 4 2 vai model QCPU to Motion CPU the communication between multiple Section 4 3 1 CPUs 3 types Communication from Basic in Communication dedicated instruction model QCPU to PC CPU Not available Section 4 3 2 between multiple CPUs 1 type module In addition to factors for the single CPU Writing data during RUN or System refresh processing for CPU Factors for increasing scan e Scan time me communication processing modules in Multiple CPU system and Section 5 2 i time setting etc waiting time may increase the scan time 1 No of CPU modules Multiple CPU setting 2 Control CPU detailed I O assign ment setting 3 Out of group I O se
266. nment setting window 100 ms Ims 1000ms Common pointer No P After 0 4095 1000 ms 0 01ms 100ms Points occupied by empty slot 16 T Points RUN PAUSE contacts RUN X X0 X1 FFF PAUSE X KO X1FFF Fixed scan interval Latch data backup operation valid contact 1000 qs 05ms 1000ms pere 55 ms 0 5ms 1000ms 400 Remote reset 20 0 ms 0 5ms 1000ms LEES 100 ms 05ms T000ms Output mode at STOP to RUN G Previous state Interrupt program Fixed scan program setting C Recalculate output is 1 scan later High speed agecution System interrupt settings r r z Service processing setting lli unct iodul ti Intsligert function modde seting e Execute the process as the Interrupt pointer setting scan time proceeds C Specify service process lime ms 0 2ms 1000ms Module synchronization Specify service process tines 1 10 times v Synchronize intelligent module s pulse up execution counts Settings should be set as same when Execute it while waiting for constant scan setting using multiple CPU Acknowledge XY assignment Multiple CPU setings Defaut Check End Came Q parameter setting Check the I O assignment settings and basic settings in the I O assignment setting window 1 0 Assignment Select Detailed setting and display the detail setting window Detailed setting PLC name PLC system PLC file PLC RAS Device Program Boot fle SFC
267. ntrol CPUs 4 Intelligent function modules of function version A can be used in the multiple CPU system by setting CPU No 1 as a control CPU However only control CPU can be accessed from serial communication modules and other external modules MELSECNET H serial communication modules and other external modules cannot access non control CPUs The SP UNIT VER ERR error code 2150 occurs if any of CPU No 2 to No 4 has been set as a control CPU and the multiple CPU system will not start up c Ranges of access to controlled and non controlled modules In a multiple CPU system non controlled modules can be accessed by setting Out of group I O setting at the Multiple CPU settings dialog box in PLC Parameter Refer to Section 3 4 for the details about accessibility to the controlled and non controlled modules in the multiple CPU system Point When all of the following conditions 1 to 4 are met use a MELSECNET H module whose first five digits of serial No is 10042 or later A multiple CPU system containing a Built in Ethernet port QCPU is configured Tothe Ethernet port of the Built in Ethernet port QCPU GX Developer or GOT is connected From GX Developer or GOT access is made to another station through a MELSECNET H module controlled by another CPU Q The access target on another station is an A QnA series CPU module 2 47 CHAPTER2 SYSTEM CONFIGURATION 3 Module replaceable online a I O
268. ntroller to ensure that the entire system operates safely even when a fault occurs in the external power supply or the programmable controller Failure to do so may result in an accident due to an incorrect output or malfunction 1 Configure external safety circuits such as an emergency stop circuit protection circuit and protective interlock circuit for forward reverse operation or upper lower limit positioning 2 The programmable controller stops its operation upon detection of the following status and the output status of the system will be as shown below Overcurrent or overvoltage protection of All output t d off All output t d off the power supply module is activated E E aca Sepe eue see The CPU module detects an error such as All outputs are held or a watchdog timer error by the turned off according to the All outputs are turned off self diagnostic function parameter setting All outputs may turn on when an error occurs in the part such as I O control part where the CPU module cannot detect any error To ensure safety operation in such a case provide a safety mechanism or a fail safe circuit external to the programmable controller For a fail safe circuit example refer to Chapter 10 LOADING AND INSTALLATION in the QCPU User s Manual Hardware Design Maintenance and Inspection 3 Outputs may remain on or off due to a failure of an output module relay or transistor Configure an external circuit for monitoring output
269. o 2 Procedure for the CPU No 2 to read device data of the CPU No 1 1 Transfers data in BO to B1F to auto refresh area of the host CPU at END processing of a CPU No 1 2 Sends data in multiple CPU high speed transmission area of CPU No 1 to CPU No 2 3 Transfers the received data to BO to B1F at END processing of CPU No 2 Procedure for the CPU No 1 to read device data of the CPU No 2 4 Transfers data in B20 to B3F to auto refresh area of the host CPU at END processing of CPU No 2 5 Sends data in multiple CPU high speed transmission area of CPU No 2 to CPU No 1 6 Transfers the received data to B20 to B3F at END processing of CPU No 1 Figure 4 24 Outline of auto refresh operation b Execution of auto refresh Auto refresh is executed when the CPU module is in RUN STOP or PAUSE status For auto refresh processing at error refer to Section 4 1 5 AJowaw peeus dD Buisn se npoui Ndo ueewjeq suoneoiunuluo Ly ese uoissiuisueJi peeds ybiy Add ejdninui Bursn yseues one Aq uogeoiunuuoo pp 4 24 c Memory configuration of multiple CPU high speed transmission area The following explains the memory configuration of the multiple CPU high speed transmission area of the CPU shared memory that is used in the multiple CPU high speed transmission function For the CPU shared memory refer to Section 4 1 1 2 CPU No 1 send range 3 User setting area 1 Multiple CPU high speed transmission area LL 2 CPU No 2 send range EO
270. o the CPU module of CPU No 1 CPU No 2 SM400 M63 X Jt BIN K4X20 D200 Always CPU No 2 Write ON write flag head data BIN K4X30 D249 H Write final data U3EX BMOV D200 610000 K50 H Write a head data w w T a3 HE o 5 63 g SET M oz y g 8 CPU No 2 35 write flag oc E d eo 83 g M31 c3 RST M63 2 a t CPU No 1 read CPU No 2 g completed write flag 95 3 2 o Q Q o TE CPU No 1 p OS vF c M63 U3E BMOV 10000 D100 K50 n CPU No 2 Read wite fag head data M31 X CPU No 1 read completed Figure 8 24 Program example for continuously writing reading data using the user setting area from CPU No 2 to CPU No 1 8 39 A ADEIB 2 eu ET d SR ae ae ae A 21 AOsEIB utro esa heres aC deo pe EUN A 21 Access range of GX Developer 3 31 Access with instruction using link direct deviGe s oca SR Ret DE vete 3 30 A to refresh 4 a elt 4 9 Auto refresh area 000 0020 4 3 4 7 Auto refresh setting 4 11 6 8 B Base u nil 2 nnELEsIERILIeS wah hae A 20 C GCG LInIe 22 eR S opel A 21 Communication between multiple CPUs with dedicated instructions 4 49 Communication using CPU shared memory by program 33 4 4 ots ee a ies 4 36 Communication with instructions dedicated to communicationbetween multiple CPUS 202000000 00 4 49 Communication with motion CPU 4 47 4 49 Communication
271. of each CPU module 2 23 CHAPTER2 SYSTEM CONFIGURATION 2 1 3 System configuration using Universal model QCPU as CPU No 1 The following explains the system configuration using the Universal model QCPU as the CPU No 1 1 When using the Multiple CPU High speed main base unit Q30DB a System configuration Battery for QCPU Q6BAT Universal model Motion PC CPU C Controller EXON RENE Q7BAT SET 8 QCPU CPU 4 module 4 6 module 4 6 R Process CPU High Performance model QCPU Battery holder Battery for QCPU Q7BAT G9 Q3LIDB type multiple CPU high speed main base unit 2 Q series power supply input output intelligent function module motion module B type extension base unit 3 B type extension base unit 2 uongeunByuoo ueljs S pZ Figure 2 15 System configuration when Q3LIDB is used LON Nd S NddD 9pouau jesJeAluf Buisn uoneunByuoo uejs S c 2 24 2 25 4 12 3 4 5 6 T 8 9 Point When the multiple CPU system is configured using QOOUCPU Q01UCPU QO2UCPU as the CPU No 1 only the Only one memory card can be mounted Select an appropriate memory card from the SRAM Flash and ATA in accordance with application and capacity When a commercial memory card is used the operation is not guaranteed Use the Q series power supply module for the power s
272. or each PLC Send range for each PLC he auto refresh area Caution Dev stating BOJ AA Pont Stat End Stat End Nof 2 N 000 001 80 BiAA Ng2 2 oof X ot 820 B3F N 3 a 000 0003 840 BF NX 2 4 ooo 000 Bsoj BSF No v Setting 1 Change screens CPU devices of CPU No 1 and No 2 are set with the same device The same number of points is set for all CPUs Refresh setting of CPU No 2 CPU devices of CPU No 1 and No 2 are set with different devices wi pic headforetesh ares Couion Dev stating MOA w AC Pont N Set End Stn Eno Df z X ox oof wj si Ez 2 ooo oof Ma2 we Lg 4 00x wo we mrar No 2 7 ooo ooo ize MisS Figure 4 14 Devices set individually for each CPU e e n mn a A jw Processing of auto refresh CPU No 1 CPU No 2 Device Device BO MO to to B1F M31 B20 M32 to lt to B3F M63 uw o pe MAIL od Figure 4 15 Outline of auto refresh processing between CPU No 1 and No 2 4 16 AJOWSW peJeus 1d2 Bursn useJjja1 ojne Aq uoneoiunuuuo2 z Ly Aiowaw peJeus Nda Husn sajnpow Nd usemjeq suoneoiunuuo9 p y 4 When the auto refresh operations are divided into four ranges Setting 1 Link relay B Setting 2 Link register W Setting 3 Data
273. ora CPU PARAMETER ERROR occurs in the consistency check between CPUs gt Section 6 1 3 For details of consistency check between CPUs refer to Section 6 1 b CPU devices The following devices can be used for auto refresh purposes other devices cannot be set up with the GX Developer Table4 3 Devices used for auto refresh Settable devices Caution Data register D Link register W None File register R ZR Link relay B Internal relay M Specify 0 or multiples of 16 for the first number Output Y 1 For setting the CPU side devices the following 2 methods are available 9 Note4 4 Method of setting devices from the startive device of CPU No 1 consecutively Method of setting devices for each CPU module optionally Setting v Set starting devices for each PLC Changa screens oe Set starting devices for each PLC Send range for each PLC Method of setting devices from the The auto refresh area Caution Dev stating startive device of CPU No 1 consecutively Set starting devices for each PLC Method of setting devices for each CPU module optionally Figure 4 11 Selection of setting method for the CPU side devices 2 The CPU side devices use the device range of points set for each CPU module from the set startive device Set a device number so that the necessary amount of send point devices can be secured Sixteen times the number of send points will be set if a
274. ord or more data to the user setting area data are written from the last address to the start address When writing the send data and interlock signal together with one instruction creating an interlock signal at the start of data will avoid data separation CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES 4 Precautions a First O numbers of CPU modules The following values are set for the CPU module s first I O number in the write read instructions Table4 12 First I O numbers of CPU modules CPU No CPU No 1 CPU No 2 CPU No 3 CPU No 4 1 Value set in the first I O number 3E0H 3E1H 3E2H 3E3H 1 Since the number of mountable CPU modules is three when using a Basic model QCPU QOOUCPU Q01UCPU QO2UCPU PLC No 4 is not selectable b Writing to CPU shared memory Do not write data to the following areas in the CPU shared memory Note4 10 7 Section 4 1 1 Restricted system area Auto refresh area c Access to module in reset status No error will occur even if the CPU accessed with a write instruction is in reset status However access execution flag SM390 9 Note4 11 will remain OFF after the instruction execution has been completed d Simultaneous access to CPU module Establish an interlock to prevent simultaneous access during interactive data communication with write read instructions Old data and new data may be mixed together if simultaneous access is carried out Section 4 1
275. page Q parameter setting Select PLC system and display the PLC PLC name PLE system PLC file PLC RAS Device Program Boottie SFC 1 0 assignment system setting window 1 0 Assignment Switch setting PLC Emply Input 16points Output points Input 16points Output 16points Assigning the 1 0 address is not necessary as the CPU does it automatically Leaving this setting blank will not cause an error to occur Base model name Power model name Extension cable Auto C Detail 8 Slot Default 12 Slot Default Teo eeepc came when Import Multiple CPU Parameter _ Read PLC data Acknowledge XY assignment Multiple CPU settings Defaut Check End Cancel Q parameter setting Check the empty slot points on the PLC PLEname PLC system PLC file PLE RAS Device Program Boot fle SFC O assignment system setting window Timer limit setting Low 100 ms ime 1000ns Common pointer No P After 0 4095 High 10 00 ms 0 01ms 100ms z speed Points occupied by empty slot 9 16 RUN PAUSE contacts RUN X X0 X1FFF PAUSE X X0 x1FFF Fixed scan interval Latch data backup operation valid contact 128 100 0 ms 0 5ms 1000ms B enm Eee X 129 400 ms 0 5ms 1000ms Remote reset 130 20 0 ms 0 5ms 1000ms T Allow Output mode at STOP to RUN Previous state Interrupt program
276. r of the CC Link master local modules QOOUCPU Q01UCPU Q02UCPU up to 4 Except QOOUCPU Q01UCPU Q02UCPU up to 8 There is no restriction on the number of mountable modules when setting parameters with the CC Link dedicated instructions 53 7 CC Link Master Local Module User s Manual 2 For the model name of the applicable GOT refer to the following manual GOT1000 Series Connection System Manual 3 The number of interrupt modules where the interrupt pointer setting is not made is shown If set there is no restriction on the number of mountable modules 4 The number of mountable modules per QCPU QOOUCPU Q01UCPU or QO2UCPU are limited as shown below e QO2UCPU up to two QOOUCPU or Q01UCPU up to one 5 When the following CPU module is used in a multiple CPU system configuration Number of mountable modules per system and Number of mountable modules per CPU for CC Link IE controller network modules are up to two respectively High Performance model QCPU Process CPU 6 The number of mountable modules per QCPU QOOUCPU Q01UCPU or QO2UCPU and per system are limited as shown below e QO2UCPU up to two QOOUCPU or Q01UCPU up to one 7 Applicable to the function version B or later 2 54 uoneunBijuoo uiejs s 10 suonneoeJd rz 2 Modules that have restrictions on use of a Built in Ethernet port QCPU Table2 24 lists the module that have restrictions on use of a Built in Ethernet po
277. r setting x I O assignment option PLC name PLC system PLC fie PLC RAS Device Program Boot fle SFC O assignment Select the slot to PLC Empty that does not mount the CPU module for each type Select the type of each module from the PcNe2 v pulldown menu Shy Select Detailed setting on the I O assignment ions setting window and display the detail setting Teroris window Output x 16points Assigning the I O address is not necessary as the CPU does it automatically Leaving this setting blank will not cause an error to occur 1 0 Assignment Base mode Auto C Detail Base model name Power model name Extension cable 8 Slot Default 12 Slot Default Ce aoada ame Me Import Multiple CPU Parameter Read PLC data Acknowledge XY assignment Multiple CPU settings Default Check End Cancel To next page NddD pow jessaaiuN eui 104 Hues JayoweseY z z 9 SJejeureJeg ueis S dO dyw eui dN Bumes zg 8 21 From previous page Intelligent function module detailed setting Control PLC mandatory item Select Control PLC for each slot Selectable numbers depend on the CPU module punc faen PS QOO0UCPU Q01UCPU Q02UCPU PLC No1 PLC No 1 to PLC No 3 PLC Nol Except the QOOUCPU Q01UCPU Q02UCPU ea PLCNS TR PLC No 1 to PLC No 4 PLC
278. rator AD Version 1 10L or later F GX Configurator DA Version 1 10L or later a 3 GX Configurator SC Version 1 10L or later Section 2 3 GX Configurator CT Version 1 10L or later Available GX Configurator TI Version 1 10L or later software GX Configurator TC Version 1 10L or later package GX Configurator FL Version 1 10L or later GX Configurator QP Version 2 10L or later GX Configurator PT Version 1 10L or later GX Configurator AS Version 1 13P or later GX Configurator MB Version 1 00A or later GX Configurator DN Version 1 10L or later To the next page 1 11 Table1 2 Difference from single CPU system continued Item Single CPU system Multiple CPU system Reference r CPU slot CPU No 1 CPU module mounting posi CPU slot only no CPU No Slot 0 CPU No 2 Section 3 1 1 tion and CPU No Slot 1 CPU No 3 The number assigned to the right of the CPU module placed in the rightmost I O number assignment Slot 0 is 00H ee on Section 3 3 1 Concept position in the multiple CPU setting is 004 4 The number of mountable mod Sp The number of mountable modules per Restrictions on number of ules per CPU module is QCPU and per system is restricted Section 2 4 mountable modules restricted depending on the R depending on the module type module type Setting the relations between the CPU Access from CPU module to module and other modules with the All modules can be controlled
279. recautions for system configuration sse nnne 2 52 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3 1 to 3 41 3 1 Mounting Position of CPU Module sse nnne nennen 3 1 3 1 14 When CPU No 1 is Basic model QCPU cececscseseeseseseseeeeeeseeeseseeeeneesesaeeeeeenseseeneneaeaes 3 2 3 1 2 When CPU No 1 is High Performance model QCPU or Process CPU sss 3 6 3 1 3 When CPU No 1 is Universal model QCPU sse 3 11 3 2 OPU Nos of CPU Mod l suisa e re tere tete nde emt c ideo 3 18 3 3 Concept of I O number assignment sse 3 20 3 3 1 I O number assignment of each module sssssssssnnenennetenne 3 20 3 3 2 WO number of each CPU module sesenta 3 22 3 4 Access Range of CPU Module and Other Modules ceccccccsceeceeeeeseeseeseeseeeeeeseeeseeatens 3 23 3 4 1 Access range with controlled module 3 4 2 Access range with non controlled module sss 3 23 3 5 Access target under GOT connection ssssssssssssssseeeeneeeeneenneeeeneneenenee 3 6 Access with instruction using link direct device 3 7 Access range of GX Developer sssssssssssseseeeneennen retener ens 3 8 Clock data used by CPU module and intelligent function module 3 8 1 Clock data used by CPU module ssssssseseeeeereneeneen nemen 3 8 2 Clock data used by intelligent function module
280. register D Setting 4 Internal relay M the outline is as shown in Figure 4 16 CPU No 1 Device CPU shared memory Setting 1 CPU shared memory of Read by END processing BO CPU No 1 Write at END processing CPU No 1 other PLCs of CPU No 1 qo Tansmission data transmission data No 1 No 1 CPU No 2 CPU No 1 SEEN CPU No 1 FORRNI data transmission data CPU Wo 7 ICPU No 3 reception No 2 i transmission data data No 1 CPU No 1 jaximum No 2 c o ICPU No 4 reception e Maximum 2K words CPU No 2 transmission data transmission data data No 1 No 3 2K words No 3 g ae Y Setting 2 No 2 CPU No 1 t dat aeons ranstNo4 an fees pM transmission data No 2 No 4 CPU No 3 NES i CPU No 2 reception 2 CPU No 3 User setting area transmission data data No 2 i 9 a R No 1 CPU No 3 reception DA o CPU No 3 data No 2 Qu transmission data d 2 Fi Maximum No 2 ICPU No 4 reception Sf ad 2K words CPU No 3 data No 2 2 transmission data i 4 Sq No 3 PSS oa Maximum 9 Setting 3 2 CPU No 3 ge 8K words S transmission data DO CPU No 1 Pd m No 4 transmission data S b No 3 j CPU No 4 9 Note4 5 CPU No 2 reception P4 CPU No 4 data No 3 transmission data F No 1 BUNT No 3 reception if i CPU No
281. resh a Overview of auto refresh The auto refresh is a communication method using the auto refresh area of the multiple CPU high speed transmission area in the CPU shared memory The data written to the auto refresh area of the multiple CPU high speed transmission area is sent to that of the other CPUs in a certain cycle multiple CPU high speed transmission cycle Setting the PLC parameter Multiple CPU settings allows to automatically read write data among all CPUs in the Multiple CPU system Since device data of other CPUs can be automatically read by the auto refresh function the host CPU can also use them as those of host CPU Figure 4 24 shows an outline of operations when CPU No 1 performs auto refresh of 32 points for BO to B1F and when CPU No 2 performs auto refresh of 32 points for B20 to B3F CPU No 1 CPU No 2 CPU shared memory CPU shared memory Multiple CPU high speed transmission Multiple CPU high speed transmission area of CPU No 1 2 Sends to CPU No 2 area of CPU No 1 Auto refresh area Auto refresh area Multiple CPU high speed transmission 5 Multiple CPU high speed transmission area of CPU No 2 Sends to CPU No 1 area of CPU No 2 Auto refresh area Auto refresh area H 1 Writing by END processing 3 Writing by END processing 5 Reading by END processing 4 Reading by END processing Device Device BO to B1F for CPU No 1 BO to B1F for CPU No 1 B20 to B3F for CPU No 2 B20 to B3F for CPU N
282. resh area Auto refresh area Device a Device 3 Device 4 T e CPU No 1 send data Mi CPU No 1 receive area ae CPU No 1 receive area JY B20 M32 B20 to CPU No 2 receive area to CPU No 2 send data to CPU No 2 receive area B3F M63 B3F B40 M64 B40 to CPU No 3 receive area to CPU No 3 receive area to CPU No 3 send data BSF M95 BSF wo wo 3 DO p 4 to CPU No 1 send data to CPU No 1 receive area to CPU No 1 receive area W1F W1F D31 W20 W20 D32 to CPU No 2 receive area to CPU No 2 send data to CPU No 2 receive area W3F W3F D63 W40 W40 D64 to CPU No 3 receive area to CPU No 3 receive area to CPU No 3 send data W5F W5F D95 1 Writing by END processing of CPU No 1 2 Sending data from CPU No 1 to CPU No 2 and CPU No 3 3 Reading by END processing of CPU No 2 4 Reading by END processing of CPU No 3 Figure 4 31 Flow of sending data from CPU No 1 to other CPUs 4 30 ese uoissiuisueJi peeds ufu Add ejdninui Bursn yseues one Aq uogeoiunuuoo pp Ajowaw peeus dD Buisn se npoui Ndo ueewjeq suoneoiunuluoS p 2 Flow of sending data from CPU No 2 to other CPUs lt Parameter setting gt Figure 4 32 shows the settings related to sending and receiving CPU No 2 data d to f in Figure 4 32 in the setting example of auto refresh in Figure 4 32
283. reuse the multiple CPU system parameters in the PC CPU setting utility 5 3 PC CPU module manual The PLC parameter settings for use in multiple CPU system The necessity of setting PLC parameter and necessity of same setting that are required for using multiple CPU System are listed in Table6 1 and 6 2 When parameters such as multiple CPU settings have been changed make the same settings for all CPUs in the multiple CPU system then reset CPU No 1 or reapply power to the multiple CPU system power ON to OFF to ON It is possible to reuse the multiple CPU parameters set up for another project with GX Developer Refer to Section 8 2 1 4 and Section 8 2 2 4 for reuse of the multiple CPU parameters a For Basic model QCPU High Performance model QCPU and Process CPU The Table6 1 shows the PLC parameter settings that are required when the Basic model QCPU the High Performance QCPU and the Process CPU are used CHAPTER6 PARAMETER ADDED FOR MULTIPLE CPU SYSTEM Table6 1 Setting list for the multiple CPU and I O Assignment Necessity Necessity PLC parameter 4 of same Reference of setup 49 setting I O Assignment Type o Model name m ces Points pes O StartXY BE o Base setting Qn H QnPH QnPRH Base model name User s Manual Function I O assignment Power mogel name Explanation Program Extension cable T Fundamentals slots im O Sw
284. rmance model QCPUs or Process CPUs can be mounted from the CPU slot the slot on the right side of power supply module to slot 2 There must be no empty slot between CPU modules 2 Mounting position of Universal model QCPU Up to three Universal model QCPU can be mounted on slots 0 to 2 of the main base unit 3 Mounting position of Motion CPU Next to the right side of the High Performance model QCPU Process CPU or Universal model QCPU up to three Motion CPUs can be mounted on slots 0 to 2 The High Performance model QCPU Process CPU or Universal model QCPU cannot be mounted on the right side of the Motion CPU Mounting allowed Mounting not allowed CPU o 1 2 J Slot number ICPU o 1 2 J Slot number m i 2 2 o o z o n Power supply Motion CPU Motion CPU module Motion CPU Motion CPU Figure 3 8 Mounting position of Motion CPU 4 Mounting position of PC CPU module Only one PC CPU module can be mounted on the right side of the other CPU modules No CPU module can be mounted on the right side of the PC CPU module CPU o 1 2 J 4 Slot number o Q P lt 2 83 9 E Motion CPU Figure 3 9 Position where the PC CPU module cannot be mounted when using the Motion CPU 3 6 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 5 Mounting position of the C Controller module Up to three C Controller modules can be mounted on slots 0 to 2 of the main base unit Note that
285. roller module and PC CPU module refer to the manuals of each CPU module Definition of functions with multiple CPU system LLLI Control and function executed in each CPU module are defined Application and assignment of device When auto refresh of the CPU shared memory is performed the number of refresh points is continuously obtained gt Section 4 1 2 LLL Select the module to achieve the function with the multiple CPU system Selection of module for use tet t ng Mount the selected module on the main base unit and the extension base unit Mounting of module Start up of GX Developer peere Available GX Developer varies for each QCPU I Section 2 3 lt The operation manual of GX Developer for operation tet nn Power ON the programmable controller power with the RUN STOP switch 2 STOP and the RESET L CLR switch OFF for the CPU module of CPU No 1 Power ON programmable controller Connection of PC to the CPU module ofCPUNo 1 230 Connect the PC that started GX Developer to the CPU module of CPU No 1 with the RS 232 cable USB cable f9 Note8 1 ett ntn Write parameter and sequence program in the CPU module of CPU No 1 For QCPU other than CPU No 1 select the applicable CPU by specifying the connection Write of parameter and program To next page uejs S Add eidniniN eui dN Bues 10 ueuo vo 4 4 8 1 When the PC CPU module is used the Q
286. rt QCPU Table2 24 Modules that have restrictions on use of a Built in Ethernet port QCPU Product name Model Five digits of available serial No MELSECNET H module QJ71LP21 25 QJ71LP21S 25 QJ71LP21G QJ71BR11 Some modules have restrictions depending on the use conditions Serial communication module QJ71C24N QJ71C24N R2 QJ71C24N R4 10042 or later Modem interface module QJ71CMON Web server module QJ71WS96 10012 or later MES interface module QJ71MES96 1 If the MELSECNET module meets the following all conditions use the MELSECNET H module whose serial number first five digits is 10042 or later 1 A multiple CPU system containing a Built in Ethernet port QCPU is configured 2 To an Ethernet port of a Built in Ethernet port QCPU GX Developer or GOT is connected 3 From GX Developer or GOT access is made to another station through a MELSECNET H module controlled by another CPU 4 The access target on another station is an A QnA series CPU module 3 Combination of power supply module base unit and QCPU Combination of power supply module base unit and QCPU has some restrictions 2 55 For details refer to the following KL QCPU User s Manual Hardware Design Maintenance and Inspection Example The redundant power supply module can be mounted only on the redundant power main base unit or the redundant power extension base unit CHAPTER
287. s 16 points 16 points 16 points 16 points 1 2 2 Loading is allowed from non controlled CPU Control CPU setting Figure 3 25 When performing output loading in CPU No 1 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 2 Output Y loading is performed for the modules shown in Table3 9 which are mounted to the main base unit or extension base unit s Table3 9 Modules that can load outputs I O allocation type Mounted module Output module None I O composite module Intelligent function module Input module Output i Output module I O mix I O composite module Intelli Intelligent function module 3 Output data cannot be loaded from empty slots and remote stations on MELSECNET H or CC Link networks being controlled by the other CPU Use auto refresh of CPU shared memory and send the ON OFF output data for remote stations from control CPU to non controlled CPU to use the ON OFF output data for remote stations on MELSECNET H or CC Link in non controlled CPU Point By enabling ALL CPUs can real all outpus setting input data controlled by other CPUs can be loaded into the host CPU In this case if the forced ON OFF of external I O is activated for the output data loaded from other CPUs to the host CPU the data will be set into the specified forced ON OFF status For the forced ON OFF of external I O refer to the following manual User s Manual Function Explanation Progra
288. s 7000 status Section 3 10 stop error For a stop error occurred in any of CPU No 2 to 4 the operation depends on the parameter setting of Operation mode 1 18 To the next page CHAPTER1 OUTLINE Table1 4 Difference from single CPU system continued Item Single CPU system Multiple CPU system Reference Communication using CPU Up to 2k words in total of 4 settings per shared memory by auto Not available CPU The total for all CPU modules is Section 4 1 2 refresh 8k words With TO FROM instructions and Communication using CPU F Suo b Not available instruction using the multiple CPU area Section 4 1 4 ica shared memor rograms communica DOSE device U3En GX tion between CPU mod Instructions dedicated to the Motion Communication from Pro CPU 5 types Instructions dedicated to Section 4 2 ules Not available o cess CPU to Motion CPU the communication between multiple Section 4 3 1 CPUs 3 types Communication from the NE Communication dedicated instruction Process CPU to the PC CPU Not available Section 4 3 2 between multiple CPUs 1 type module C Controller module In addition to factors for the single CPU Writing data during RUN or System refresh processing for CPU Factors for increasing scan n Scan time tima communication processing modules in Multiple CPU system and Section 5 2 i time setting etc waiting time may increase
289. s Control PLCs for the I O modules and intelligent function modules mounted on the base unit in the multiple CPU system All default settings are set to CPU No 1 Intelligent function module detailed setting time PLC operation PLC No 1 PLC No 2 PLC Nol v3 PLC No 1 v PLC No 1 v PLC No 1 v PLC No 1 v PLC No 1 v PLC No 1 v PLC No 1 v aid idiaiaiaiaiaie ala lalalalalalalata settings should be set as same when using multiple CPU Figure 6 3 Control CPU setting screen 6 1 7 Multiple CPU synchronized boot up This is set for synchronizing the boot up time for each CPU module C27 Section 4 5 6 1 8 Multiple CPU high speed transmission area setting This is set when the auto refresh is performed using the multiple CPU high speed transmission area in the multiple CPU system Ls Section 4 1 3 Point The multiple CPU synchronized boot up and the multiple CPU high speed transmission area setting are available when the following CPU modules are used e Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172DCPU Q173DCPU 6 9 CHAPTER7 PRECAUTIONS FOR USING AnS A SERIES COMPATIBLE MODULES CHAPTER7 PRECAUTIONS FOR USING ANS A SERIES COMPATIBLE MODULES 7 1 Precautions for use of AnS A series compatible module 1 Multiple CPU configuration available for AnS A series compatible 2 modules AnS
290. s refer to the user s manual for the Motion CPU module Wiring Precautions Shut off the external power supply for the system in all phases before wiring Failure to do so may result in electric shock or damage to the product After wiring attach the included terminal cover to the module before turning it on for operation Failure to do so may result in electric shock N DANGER Ground the FG and LG terminals to the protective ground conductor dedicated to the programmable controller Failure to do so may result in electric shock or malfunction Use applicable solderless terminals and tighten them within the specified torque range If any spade solderless terminal is used it may be disconnected when the terminal screw comes loose resulting in failure Check the rated voltage and terminal layout before wiring to the module and connect the cables correctly Connecting a power supply with a different voltage rating or incorrect wiring may cause a fire or failure Connectors for external connection must be crimped or pressed with the tool specified by the manufacturer or must be correctly soldered Incomplete connections could result in short circuit fire or malfunction Tighten the terminal screw within the specified torque range Undertightening can cause short circuit fire or malfunction Overtightening can damage the screw and or module resulting in drop short circuit or malfunction Prevent foreig
291. s used 2 28 LON Nd S NddD pow jesJeAluf Buisn uoneunByuoo uejs S crz uongeunByuoo waJs S Lc 2 29 Point When the multiple CPU system is configured using QOOUCPU Q01UCPU QO02UCPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 and No 3 Motion CPU Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T PC CPU module PPC CPU852 MS 512 C Controller module Note that the PC CPU module and C Controller module cannot be mounted together When the multiple CPU system is configured using the Universal model QCPU except QOOUCPU Q01UCPU QO2UCPU as the CPU No 1 only the following CPU modules can be used as the CPUs No 2 to No 4 High Performance model QCPU Process CPU Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU PC CPU module PPC CPU852 MS 512 C Controller module Note that the PC CPU module and C Controller module cannot be mounted together CHAPTER2 SYSTEM CONFIGURATION b Outline of system configuration 4 2 3 MMain base unit 32 point modules are mounted on each slot Q312B 12 slots occupied CPU 0 1 2 4 5 6 8 10 Tt Slot number E ns n ee oy oe fe ne S ce Ger fe tS ee ee fe Ge ll se S S SS SS e2 2 2 O number 1 r e e eo
292. se2__ 3072 610000 No 4 3 uses 3072 610000 Set auto refresh setting if itis needed No setting Already set Total 12K points Advanced settings Assignment confirmation The total number of points is up to 12K Import Multiple CPU Parameter En Cancel To next page Select Multiple CPU settings and display the multiple CPU setting window The number of mountable CPU modules depends on the CPU model QOOUCPU Q01UCPU Q02UCPU PLC No 1 to PLC No 3 Except the QOOUCPU Q01UCPU Q02UCPU PLC No 1 to PLC No 4 No of PLC mandatory item Set the number of CPU modules mounted on the main base unit with the multiple CPU System Host CPU number Setting is required when checking the host CPU number of the multiple CPU system Refer to Section 3 11 Default No specification Multiple CPU settings No of PLC No of PLE Host Operating mode Error operation made at the stop of PLC F Iv All station stop by stop error of PLC2 I All station stop by stop error of PLC3 I All station stop by stop error of PLC4 Target PLC IV Noi IV No2 IV No3 IV No4 Settings should be set as same when using multiple CPU Muligie CPU synchronous startup seing From previous page nline module changel T Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status
293. sed 9 ED GE For the Basic model QCPU the Process CPU and the Universal model QCPU the high speed interrupt function is not available 42 Note2 2 2 57 For the Universal model QCPU GOT A900 and GOT F900 series are not available Only 1000 series is available CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3 1 Mounting Position of CPU Module For the configuration of the multiple CPU system the combination of CPU modules shown in Table3 1 is available Table3 1 Combination of CPU modules Number of CPU that can be mounted on CPU module No 2 or later Maximum High Motion CPU PC CPU module 1 number of Performance PPC mounted CPU module No 1 Model QCPU qi72cPUN T CPU686 MS c modules Reference Process CPU Q173CPUN T Q172DCPU 64 Ee Controller including Universal Q172HCPU T Q173DCPU PPC CPU852 MS moque ERU model Q173HCPU T CPU686 MS aig module QCPU 2 128 No 1 indicates indicates Basic model QCPU combination is 0 to 1 combination 0to 1 0 to 1 3 Section 3 1 1 impossible is impossible indicates T 0 to 3 0to3 combination 0 to 1 0 t0 3 4 Section 3 1 2 is impossible QOOUCPU indicates indicates indicates Q01UCPU combination is 0 to 1 combination combination O to 1 0 to 1 3 Q02UCPU impossible is impossible is impossible QO3UDCPU QO4UDHCPU QO6UDHCPU Q10UDHCPU Universal Q13UDHCPU model Q20UDHCPU MN m Section 3 1 3 EON bs du
294. sed with the following CPU module High Performance model QCPU First five digits of serial number must be 09012 or later Process CPU First five digits of serial number must be 10042 or later Point For restrictions on mounting the A series module on the QA6L B QA6ADP A5LIB A6LIB refer to the following manual lt gt QA65B QA68B Extension Base Unit User s Manual lt gt QA6ADP QA Conversion Adapter Module 2 53 CHAPTER2 SYSTEM CONFIGURATION c When using the Universal model QCPU Table2 23 Modules of restricted quantity Product CC Link IE controller network module 9 Model QJ71GP21 SX QJ71GP21S SX Q series MELSECNET H network module QJ71LP21 e QJ71BR11 QJ71LP21 25 e QJ71LP218S 25 e QJ71LP21G e QJ71LP21GE e QJ71NT11B Number of modules that can be mounted per system Up to 4 modules Quantity restriction per QCPU Up to 4 modules 4 Q series Ethernet interface module QJ71E71 QJ71E71 B2 QJ71E71 B5 QJ71E71 100 Up to 4 modules 6 Up to 4 modules Q series CC Link system master local module QJ61BT11N No restriction 17 No restriction 1 7 Interruption module QI60 Up to 4 modules Only 1 module 3 GOT GOT1000 series Bus connection only E Up to 5 modules Up to 5 modules 1 One CPU module with CC Link network parameter setting in GX Developer can control the following numbe
295. setlings Assignment confirmation The total number of points is up to 12K Import Multiple CPU Parameter ont es Cancel To next page CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM Operating mode option Select if all CPUs are stopped operated for occurrence of stop error Default With any error of CPUs 2 3 and 4 all CPUs stop checked For example when All station stop by stop error of PLC 2 is unchecked other CPUs continue operation for an error of CPU No 2 Operation of CPU No 1 cannot be changed Multiple CPU synchronized boot up setting Select whether to simultaneously start the CPU modules in a multiple CPU system Default All CPUs are synchronously started checked Deselect all items in Multiple CPU synchronous startup setting for the following CPU modules High Performance model QCPU Process CPU Controller module QO6CCPU V Q06CCPU V B PC CPU module Online module change I O sharing when using Multiple CPUS option Select whether to perform Online module change l O sharing when using Multiple CPUs Default Online module change is disabled not checked Select Enable online module change with another PLC in the following case Enable online module change with another PLC has been selected to the Process CPU Setif the input output status beyond control of input output setting outside of group is loaded or not Default Not loaded
296. setting Target PLC point 1 0 No point Start point Setting No 1 3 H3E0 3072610000 ting S No 2 3 USET 3072 610000 Dj SetinafReceive No 3 3 U3E2 3072 610000 lr T No 4 3 U3E3 3072 610000 o Set auto refresh setting if it is needed No setting Already set Total 12K points Advanced settings Assignment confirmation Settings should be set as same when The total number of points is up to 12K Import Multiple CPU Parameter ot es Cancel using multiple CPU Multiple CPU settings No of PLC No of PLC 4 v Host CPU number a Operating mode 7 Error operation mode at the stop of ME Ee F JV All station stop by stop error of PLC2 TA All station stop by stop error of PLC3 JV All station stop by stop error of PLC4 Multiple CPU synchronous startup setting Target PLC Not Iv No 2 v No3 IV Nod Settings should be set as same when Online module change Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs All CPUs can read all inputs Multiple CPU high speed transmission area setting Communication area setting refresh setting JV Use multiple CPU high speed transmission CPU specific send rangel PLC User setting area point k point Start 3 3
297. settings screen Multiple CPU high speed communication area assignment confirmation screen Multiple CPU high speed communication area Multiple CPU settings screen assignment confirmation screen Multiple CPU settings E3 Multiple CPU high speed communication area assignment confirmation 3 Noot PLC Online module change PIC NGT PLE o2 PLC Wea PLE o4 NoofPic 5 shared nemow shared nemo shared memo Eun Host EPUI Select UseNEr0000 TPE Net dac __ PLENot aaa PLENatdotal IPLE Not dete z 1 0 sharing when 3k poi Uma IT AICHUs can tead olus Assignment EE petating mode utor IT ARCPUs can read all outputs x PICNGT Error operation mode at the stop of PLC e E Riise CONfirmation Fey e NN M NN M V Al station stop by stop enor of PLC2 V Use multiple CPU high speed t Enc eea Nazi evar Allstaton stop by stop enor of PLC3 STU sdb LanslFe PR aes F PLC ser seing area Aulo ree Poa pem K VONo pont Stat End pom Setting Maipi CPU synchronous siatup setin Tier sfulge0 T a072a1o000 a127i Ol Sandsendl em Jede No2 aju3E1 3072 610000 613071 O _SetingRecewe a d eE F Not No 3 3juse2 3072 610000 613071 Of SetingfFieceivel F No2 No4 dra idis Set auto refresh setting iiti needed No seting 7 Aleady set Total SK pointe I Advanced settings Assignment confirmation fj Eos
298. sion stages 4 extension units Maximum number of mountable I O 25 No of CPUs modules Available main base Q38DB Q312DB unit model Model not requiring power supply module Q52B Q55B Available extension Model requiri i i de Q series powersupPly 0635 Q65B Q68B Q6128 u base unit model Available extension QC05B QC06B QC12B QC30B QC50B QC100B cable model Available power Q61P A1 Q61P A2 Q61P Q61P D Q62P Q63P Q64P Q64PN supply module model Precautions Do not use an extension cable longer than 13 2m 43 31 ft When using an extension cable keep it away from the main circuit high voltage and large current line Set the number of extension stages so as not to be duplicated The QA1S6LIB QAeL IB QA6ADP ASLTB AGLIB or Q6RLIB cannot be connected as an extension base unit Although there is no restriction on the connection order of the Q5LB and the Q6L IB check the availability of them by referring to QCPU User s Manual Hardware Design Maintenance and Inspection when both the QS5LIB and the Q6L B exist as the extension base unit Connect the OUT connector of an extension base unit and the IN connector of the adjacent extension base unit by an extension cable When 26 modules or more are mounted an error SP UNIT LAY ERR error code 2124 occurs The number of mountable modules includes one CPU module The redundant base unit cannot be used when the Basic mo
299. slot is limited up to slot 1 3E20H 3 22 CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3 4 Access Range of CPU Module and Other Modules 3 4 1 Access range with controlled module In the multiple CPU system a CPU can refresh I O data of its controlled modules and write or read data of the buffer memory of intelligent function modules in the same way as a single CPU system L s User s Manual Function Explanation Program Fundamentals for the CPU module used 3 4 2 Access range with non controlled module CPU modules can obtain input X ON OFF data of non controlled modules and output Y ON OFF data of CPUs of other No by the PLC parameter setting Therefore ON OFF data of input modules I O composite module or intelligent function modules controlled by other CPUS can be used as interlocks for the host CPU and the output status to external equipment being controlled by other CPUs can be confirmed Also the contents of the intelligent function module s buffer memory can be read by non control CPUs regardless of the PLC parameter setting However it is not possible for non control CPUs to output ON OFF data to non controlled output modules composite l O module or intelligent function modules and to write data to the buffer memory of intelligent function modules Table3 7 indicates accessibility to the non controlled modules in the multiple CPU system Table3 7 Access range to non controlled module 1 0 sett
300. slots occupied pur 13 14 15 16 17 extension ima p o0 T w u u juu oola oj u a 28 S olojilojo o o o0 i aTeuor oum ialj rcc c l 5 o0 i Q65B 5 slots occupied m i 18 19 20 21 22 extension al in o0 FRARI j NININ INI SN je fe fer fey fe xe o0 2 2 2 ey een em o o0 amp s I oj n t INS TF ININININ o0 z Q65B 5 slots occupied an 23 24 25 26 27 extension Sol TT 3 a4 Tere i aZiloididis ee Nj L 2 2 21 ma 2 21222 D 1 a B S 118 i ss 1 I 1 o0 1 2 b4 a 4 4 Error in mounting 1 Shows when the CPU module 3 is the PC CPU module If the CPU module 3 is the C Controller module a module can be mounted on the slot 2 Figure 2 2 System configuration example for using Basic model QCPU CHAPTER2 SYSTEM CONFIGURATION Table2 1 Restrictions on system configuration available base units extension cables and power supply modules CPU1 CPU No 1 Basic model QCPU CPU2 CPU No 2 Motion CPU CPU3 CPU No 3 PC CPU module C Controller module CPU number Maximum number of extension stages 4 extension units Maximum number of mountable I O 25 No of CPUs modules Available main base Q33B Q35B Q38B Q312B unit model Model not requiring power supply module Q52B Q55B Available extension bese unit imedel MEO Q series power supply Q63B Q65B Q68B Q612B u Available e
301. smission V All station stop by stop error of PLC3 CPU specific send ranae IZ All station stop by stop error of PLC PLC User setting area Ponk VO No point Stan Nad USED Target PLC em M Not No 3 U3E2 Nod UsE3 3072610000 612071 Multiple CPU synchronous startup setting Set auto refresh setting if it is needed No setting Already set Total 12K points Advanced settings The total number of points is up to 12K Settings should be set as same when using multiple CPU Import Mutiple CPU Parameter Check End Cea Figure 4 52 Multiple CPU synchronous startup setting when deselecting No 2 and No 4 When this function is not used each CPU boot up without synchronization it is recommended to use SM220 to SM223 Preparation completed flag of CPUs No 1 to No 4 of the special relay and create the sequence program to check the boot up of the each CPU module a Special relay to check the boot up of CPU No 2 SM2 1 U3E1 o c vo coo po Access to CPU No 2 Figure 4 53 Program to check the boot up of CPU No 2 4 56 dn joog p zjuosyou S ndo AdyNN S Y CHAPTERS PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 5 1 Concept of Scan Time 1 I O refresh time I O refresh time is calculated with the equation explained in the following manual The concept of scan time in the multiple CPU system is the same as that in the single CPU sy
302. started up b When all CPUs are not the same The operations described in Table6 3 will be performed In this event check the multiple CPU parameters and set all CPUs with the same settings To start the multiple CPU system reset CPU No 1 or turn off and on the multiple CPU system power ON OFF ON For the action after CPU No 1 reset refer to Section 3 9 Table6 3 List of consistency check between CPUs Item CPU No 1 CPU No 1 to 4 When the multiple CPU system is powered on When CPU No 1 is reset When the RUN STOP switch has been changed from STOP to RUN When parameters are written with the GX Developer When CPU in the RUN mode exist No consistency check between CPU modules for the multiple CPU parameters will be run A comparison check will be run on the multiple CPU parameters of CPU No 1 A PARAMETER ERROR error code 3012 3015 will occur in the host CPU if they do not match A comparison check will be run on the multiple CPU parameters of RUN state CPU of the lowest No A PARAMETER ERROR error code 3012 3015 will occur in the host CPU if they do not match When CPUs in the RUN mode do not exist A comparison check will be run on the multiple CPU parameters of stopped CPU No 2 A PARAMETER ERROR error code 3012 3015 will occur in the host CPU if they do not match A comparison check will be run on the multiple CPU parameters of CPU No
303. stem This chapter describes how to calculate the processing time when the multiple CPU system is configured s User s Manual Function Explanation Program Fundamentals for the CPU module used The I O refresh time is prolonged by the following values when it is overlapped with bus access from to other CPUs No of input points No of output points Extension time Use the value in Table5 1 for N3 16 Table5 1 Extension of I O refresh time x N3 x No of other CPUS us QCPU QOOCPU Q01CPU QO02CPU QO02HCPU Q06HCPU Q12HCPU Q25HCPU Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU QOOUCPU Q01UCPU QO2UCPU QO3UDCPU Q04UDHCPU Q0GUDHCPU Q10UDHCPU Q13UDHCPU Q20UDHCPU Q26UDHCPU Q03UDECPU Q04UDEHCPU QO6UDEHCPU Q10UDEHCPU Q13UDEHCPU Q20UDEHCPU Q26UDEHCPU Systems with only a main base unit 8 7 us N3 Systems that include additional base units 214s 2 Total value of instruction execution time Refer to the following manual for details on the processing time of instructions dedicated to the multiple CPU System and various processing times of instructions used in the multiple CPU system QCPU Programming Manual Common Instructions CHAPTERS PROCESSING TIME OF QCPU IN MULTIPLE CPU SYSTEM 3 Common processing The values in Table5 2 show the common processing time Table5 2 END processing time QCPU Common processing time QOOCPU Q
304. t 0 when the QOOUCPU Q01UCPU QO2UCPU is used When other than the QOOUCPU Q01UCPU QO2UCPU is used up to three Motion CPUs can be mounted on slots 0 to 2 of the main base module Mounting position of PC CPU module Only one PC CPU module can be mounted on the right side of the other CPU modules No CPU module can be mounted on the right side of the PC CPU module CPU o 1 2_ lt Slot number gt a 2 2 o i o z o a module Motion CPU Figure 3 12 Location where the PC CPU module cannot be mounted Mounting position of the C Controller module When using the QOOUCPU Q01UCPU Q02UCPU only one C Controller module can be mounted on the right side of the CPU modules When using except the QOOUCPU Q01UCPU QO2UCPU up to three C Controller modules can be mounted on the right side of the following CPU modules High Performance model QCPU Process CPU Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU C Controller module Motion CPU Q172DCPU Q173DCPU 3 11 f1d90 IJepoui jesI AUN SI L ON NdD YAUM ELE e npoi ndo Jo uonisod BuyuNoW p e 6 PLC Empty setting 3 12 An empty slot can be reserved for future addition of a CPU module Select the number of CPU modules including empty slots at No of PLC and set the type of the slots to be emptied to PLC Empty in the I O assignment screen of PLC parameter Point When using the Universal model QCPU PLC Empty can be set bet
305. t remove the module to from the base unit and the terminal block to from the module more than 50 times IEC 61131 2 compliant respectively Exceeding the limit of 50 times may cause malfunction Do not drop or apply shock to the battery to be installed in the module Doing so may damage the battery causing the battery fluid to leak inside the battery If the battery is dropped or any shock is applied to it dispose of it without using Before handling the module touch a grounded metal object to discharge the static electricity from the human body Failure to do so may cause the module to fail or malfunction Disposal Precautions N CAUTION When disposing of this product treat it as industrial waste When disposing of batteries separate them from other wastes according to the local regulations For details of the Battery Directive in EU countries refer to the QCPU User s Manual Hardware Design Maintenance and Inspection Transportation Precautions N CAUTION When transporting lithium batteries follow the transportation regulations For details of the regulated models refer to the QCPU User s Manual Hardware Design Maintenance and Inspection REVISIONS The manual number is given on the bottom left of the back cover Print date Jun 2004 SH NA 080485ENG A First edition May 2005 SH NA 080485ENG B Partial correction GENERIC TERMS AND ABBREVIATIONS Chapter 1 Section 1 1 2 1 2
306. taa SE 20124 Malm Phone 358 0 207 463 500 Phone 46 0 40 35 86 00 Fax 358 0 207 463 501 Fax 46 0 40 35 86 02 UTECO A B EE GREECE EconotecAG SWITZERLAND 5 Mavrogenous Str Hinterdorfstr 12 GR 18542 Piraeus CH 8309 N rensdorf Phone 30 211 1206 900 Phone 41 0 44 838 48 11 Fax 30 211 1206 999 Fax 41 0 44 838 48 12 MELTRADE Ltd HUNGARY GTS TURKEY Fert utca 14 Dar laceze Cad No 43 KAT 2 HU 1107 Budapest TR 34384 Okmeydanr Istanbul Phone 36 0 1 431 9726 Phone 90 0 212 320 1640 Fax 36 0 1 431 9727 Fax 90 0 212 320 1649 Beijer Electronics SIA LATVIA CSC Automation Ltd UKRAINE Vestienas iela 2 15 M Raskova St Fl 10 Office 1010 LV 1035 Riga UA 02002 Kiev Phone 371 0 784 2280 Phone 380 0 44 494 33 55 Fax 371 0 784 2281 Fax 380 0 44 494 33 66 Beijer Electronics UAB LITHUANIA MITSUBISHI ELECTRIC Savanoriu Pr 187 LT 02300 Vilnius Phone 370 0 5 232 3101 Fax 370 0 5 232 2980 Mitsubishi Electric Europe B V FA European Business Group Gothaer Stra e 8 D 40880 Ratingen Germany FACTORY AUTOMATION Tel 49 0 2102 4860 Fax 49 0 2102 4861 120 info mitsubishi automation com www mitsubishi automation com
307. ter Q172HCPU T Q173HCPU T C Controller module QO6CCPU V Q06CCPU V B PPC CPU686 MS 64 Refer to the manual of each CPU module PC CPU module PPC CPU686 MS 128 PPC CPU852 MS 512 2 48 SJeMIJOS e qe reAe pue 3149p e jqeunBijuoo ez 4 Applicable software a GX Developer and PX Developer Versions of the GX Developer and the PX Developer applicable in the multiple CPU system are shown in Table2 19 Table2 19 Applicable GX Developer and PX Developer Applicable software version QCPU GX Developer PX Developer Basic model QCPU 2 Version 8 00A or later Not available High Performance model QCPU Version 6 00A or later Process CPU Version 7 10L or later 1 Version 1 00A or later QO2UCPU QO3UDCPU Version 8 48A or later Q04UDHCPU f QO6UDHCPU Not available Q13UDHCPU Version 8 62Q or later Q26UDHCPU QO3UDECPU Universal model QCPU Q04UDEHCPU QO6UDEHCPU Version 8 68W or later Not available Q13UDEHCPU Q26UDEHCPU QOOUCPU QO0O1UCPU Version 8 78G or later Not available Q10UD E HCPU Q20UD E HCPU 1 When using PX Developer use GX Developer of version 7 12N or later 2 49 CHAPTER2 SYSTEM CONFIGURATION b Applicable GX Configurator Versions of GX Configurator applicable in the multiple CPU system are shown in Table2 20 Available GX Configurator versions vary depending on the intelligent function module used For available GX Configurator versions refer to t
308. the I O module and intelligent function module indicates that their Control CPU is the CPU No 1 The CPU module that controls the I O modules and intelligent function modules is called as a Control CPU The I O modules and intelligent function modules controlled by the control CPU are called controlled modules Other modules not controlled by the control CPU are called as non controlled modules 1 3 Eweaysks NdI eidninu srjeuM LL 4 Multiple CPU system setting For control in the multiple CPU system it is necessary to set up the Number of mounted CPU modules and the Control CPU with PLC parameter for all CPU modules mounted on the main base unit User s Manual Function Explanation Program Fundamentals for the CPU module used 5 Access range of multiple CPU system In the multiple CPU system the access ranges are different between the controlled module and the non con trolled module a Controlled module The multiple CPU system s control CPU can refresh the I O data of controlled modules and read write the buffer memory data of intelligent function modules in the same way as in a single CPU system b Non controlled module It is possible to access non controlled modules in the following ways Refreshing the input for I O modules I O composite module and intelligent function modules the PLC parameter s multiple CPU setup is necessary Reading the intelligent function module s buffer memory Down
309. the SRAM Flash and ATA in accordance with application and capacity When a commercial memory card is used the operation is not guaranteed Use the Q series power supply module for the power supply module Keep the current consumption within the rated output current of the power supply module The Slim power supply module and Redundant power supply module are not available for the power supply module The Q Series power supply module is not required for the Q5LIB extension base unit The motion CPU and PC CPU module do not accept battery for QCPU and memory card For memory cards that can be used with the C Controller module refer to the manual of the C Controller module Usable Motion CPUs are only the Q172CPUN T Q173CPUN T Q172HCPU T and Q173HCPU T when the QOOUCPU Q01UCPU Q02UCPU is used When using the Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU the Motion CPU cannot be mounted For further information on PC CPU module consult CONTEC Co Ltd Tel 81 6 6472 7130 The PC CPU module and C Controller module cannot be mounted together When the Q8BAT is used for the Universal model QCPU use the connection cable whose connector part displays A For details of connector part of a connection cable refer to the following manual QCPU User s Manual Hardware Design Maintenance and Inspection Be sure to set the control CPU of the motion module to the Motion CPU Figure 2 17 System configuration when Q3LIB i
310. the hard disk floppy disk Completed Figure 8 5 Parameter setting procedure for reusing multiple CPU system parameters 8 14 CHAPTERS STARTING UP THE MULTIPLE CPU SYSTEM 8 2 2 Parameter setting for the Universal model QCPU 1 System configuration Figure 8 2 shows an example procedures for setting up the multiple CPU parameters HEPC GX Developer Empty slot for addition of future CPU module cpu 0 1 2 3 4 5 6 7 lt Slotnumber o 2 3 um de e Ely 3 3 9 93 2 9 8 8 9 2 92 23 8 at E JE Z l35 S9 s3 S1 S Qa o o Rel o e alg s Ee oO E6909 E t sils2s2so d E s E s sS s 25 2525 Qg E S 2 sg 5eo l5e5oa S5 Jol s oJ s2E EB 2 ENBEB 2 2 2 Controi cpu setting 8 9 10 11 12 13 14 15 Stot number o 3 E 3 fo E ol E ioi 5 2 amp l8 8 9 JHAR 3ls a l ela sg amp amp loO E Control CPU setting Figure 8 6 Configuration example of multiple CPU system Nd pow JesjeAiu eui JO Buas sojowesey ZZS SJejeujeJeg ulejs S do eidniniN 24 dq Bunjes zg 8 15 2 Parameters required for multiple CPU system When the multiple CPU system is used the following parameter settings are required Parameters of Same setting items for each CPU module should be set with the same settings in all CPU modules used
311. the scan time 1 No of CPU modules Multiple CPU setting 2 Control CPU detailed I O assign ment setting 3 Out of group I O setting Multiple CPU setting Parameters added for multi Parameter Not available 4 Operation mode for CPU error stop Section 6 1 ple CPU system Multiple CPU setting 5 Communication area setting auto refresh setting Multiple CPU setting Some parameters must be set to the same for all CPU modules while others may be different for each CPU module AnS A series compatible Caution The AnS A series compatible modules cannot be used Section 7 1 module 1 No of CPUs indicates the number of CPU modules set at No of PLC in the Multiple CPU settings screen of PLC parameter 2 When the PC CPU module is mounted the maximum number of mountable I O modules is the result of 65 No of CPUs 1 3 When the Motion CPU or PC CPU module is mounted on the multiple CPU system Q3LIRB QeLIRB and Q6LTRP are not available 4 For some intelligent function modules different version may be used 5 When the PC CPU module is mounted the slot to the right of the PC CPU module is 10n 1 19 uleis S fido ejfBuis wo eoueJeyd E4 4 When using the Universal model QCPU Table1 5 Difference from single CPU system Item Single CPU system Multiple CPU system Referenc
312. the user s manual of the each PLC about the starting address The applicable device of head device is B M Y DW R ZR The unit of points of CPU specific send range is word Settings should be set as same when i kei Import Multiple CPU Parameter Check Les Cancel To next page Notes 3 Since the number of CPU modules that can be mounted is up to 3 when using the basic model QCPU do not set to 4 8 6 Multiple CPU settings No of PLC No of PLC DN Operating mode Error operation mode at the stop of PLC m IV All station stop by stop error of PLC2 IV All station stop by stop error of PLC3 v All station stop by stop error of PLO4 Settings should be set as same when using multiple CPU Multiple CPU settings No of PLC No of PLC f From previous page Online module change T Enable online module change with another PLC When the online module change is enabled with another PLC 1 0 status outside the group cannot be taken 1 0 sharing when using Multiple CPUs 4 T AICPUs can read all inputs T Al CPUs can read all outputs Communication area setting refresh setting Change screens Setting I Set starting devices for each PLC CPU specific send range PLC side device PLC Auto reftesh area Caution Dev starting Pont Stat End Start End Not 0j No 2 0j a No 3 No 4 0j C
313. tiple CPU high speed transmission function parameter x including the consistency check error Moderate error 4 Severe error x x3 O Transfer x Does not transfer 1 Shows the data transfer between the internal user device and the multiple CPU high speed transmission area of the host CPU 2 Shows the data communication between the multiple CPU high speed transmission area of the host CPU and the multiple CPU high speed transmission area of the other CPU 3 When the error occurs during the normal operation transmission of the normal data before the error occurs is continued 4 Continues sending receiving data between the auto refresh area 0 and CPU module if consistency check error occurs due to PLC parameter change during normal operation Point The communication between CPU modules when the error occurs can be executed if the following CPU modules are used e Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172DCPU Q173DCPU 4 46 SJn290 10119 BU U YM se npouil Nd UuseMmIeg suogeoiunuuo 5 Gg Lr AJowaw peeus 1d2 Buisn se npoui Ndo ueewjeq suoNediunWWwOD Lo 4 2 Communications with instructions dedicated to Motion CPU 4 2 1 Control instruction from QCPU to Motion CPU Control instructions can be issued from the QCPU to Motion CPU with the instructions dedicated to Motion CPU as listed in Table4 14 Control instructions from a Motion CPU to other Motion CPU is not al
314. tiple CPU high speed transmission area is from 0 09 ms to 1 80 ms 4 39 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES c Memory configuration of multiple CPU high speed transmission area 1 Addresses of user setting area The addresses of user setting area depend on the CPU module For user setting area addresses refer to Section 4 1 1 2 Addresses of multiple CPU high speed transmission area The following explains the memory configuration of the multiple CPU high speed transmission area that is used in the multiple CPU high speed transmission function For the CPU shared memory refer to Section 4 1 1 U3E0 G 10000 1 t CPU No 1 send range User setting area Multiple CPU high p lA speed transmission area U3E1 G10000 1 A eie to CPU No 2 send range Dna Auto refresh area U3E2 G10000 1 to CPU No 3 send range U3E3 G10000 1 x CPU No 4 send range to 1 Indicates addresses when user setting area for each CPU is specified using multiple CPU devices Figure 4 42 Memory configuration of multiple CPU high speed transmission area For the each area of the multiple CPU high speed transmission area refer to Section 4 1 3 2 Parameter setting note4 9 When performing the auto refresh of the multiple CPU high speed transmission area the number of points to be sent by each CPU module is set in the PLC parameter Multiple CPU settings For the setting description of the parameter refer to Section 4 1 3 w
315. tiple CPU system setting 8 9 10 11 12 13 14 15 Slot number S 2 o 8 S 3 E E 5 o a z 83 3 S 2 eBIg E 5 o g D o a zla 8 8 E a S S 4 0 0 2 Control CPU O setting P 7 lt Q D 3 T e S 3 c oO a Ndd sseooJd nid90 epow eoueuuojeg YBIH Nd dD pouw dseg euj 10 Bumes JejeureJed L z8 8 3 2 Parameters required for multiple CPU system When the multiple CPU system is used the following parameter settings are required Parameters of Same setting items for each CPU module should be set with the same settings in all CPU modules used in the multiple CPU system except some parts gt Section 6 1 Multiple CPU setting No of PLC Operation mode Note8 2 Q Online module change s I O sharing when using Multiple cpus Refresh settings Change screens Send range each PLC PLC side device l O assignment E I O Assignment Detail settings Control PLC Basic setting slots PLC system Points occupied by empty slot Mandatory setting items Same setting items for each CPU module Figure 8 3 List of parameters required for multiple CPU system f 2 EDB For the Basic model QCPU the online module change setting is not available For the High
316. to write parameters and programs and perform monitoring and tests on QCPUs connected to GX Developer To access QCPUs of other CPU No via a QCPU connected to GX Developer specify the target CPU No in the mulple CPU setting of the GX Developer Slot number ooo0000 Jo zXveXuexueXueXueXueXuel D gt o sz o 2_ Control CPU setting Access allowed with CPU module 1 Figure 3 30 Access to QCPU when target CPU is not specified Slot number o pe c ol I naagaad nannnu ooo000 000000 CPU number Communicate with CPU No 2 Jedoje eq X9 Jo ebues sseooy ZE CA NEZ NETI DCirk Ethem CH NETAOH NETIN CCLnk _ Ethene Aecseengi hod salon Specify PLC No 2 CPU No 2 Figure 3 31 Access to QCPU when target CPU is specified 3 31 2 Access to controlled module and non controlled module GX Developer can access the modules regardless of whether they are controlled or non controlled by the QCPU connected to the GX Developr By connecting GX Developer to a single QCPU it is possible to perform monitoring and tests on all modules being controlled by the multiple CPU system s QCPU The QCPU on another station in the same CC Link IE controller network Note3 3 Not
317. tting Multiple CPU setting Parameters added for multi Parameter Not available 4 Operation mode for CPU error stop Section 6 1 ple CPU system f Multiple CPU setting 5 Communication area setting refresh setting Multiple CPU setting Some parameters must be set to the same for all CPU modules while others may be different for each CPU module AnS A series compatible Caution The AnS A series compatible modules cannot be used Section 7 1 module 1 No of CPUs indicates the number of CPU modules set at No of PLC in the Multiple CPU settings screen of PLC parameter 2 When the PC CPU module is mounted the maximum number of mountable I O modules is the result of 25 No of CPUs 1 3 For some intelligent function modules different version may be used 4 When the PC CPU module is mounted the slot to the right of the PC CPU module is 10n 1 13 uleis S nido ejBuis wo eoueJeyd E4 2 When using the High Performance model QCPU Table1 3 Difference from single CPU system Item Single CPU system Multiple CPU system Reference Maximum number of exten 7 stages sion stages Maximum number of mount able 64 65 No of CPUs I O modules System con Main base unit model Q30B Q30SB Q30RB Q30DB i T figuration Extension base un
318. tting refer to Section 3 1 2 Thel O numbers for the multiple CPU system can be confirmed with the system monitor 3 The I O number 00 can be placed in any slots with I O assignment setting of PLC parameter L gt User s Manual Function Explanation Program Fundamentals for the CPU module used yu wu isse 1equinu Q Jo 3de2u02 g e e npouJ uoee jo 1ueuiuBisse jJequinu O L 3 21 3 3 2 I O number of each CPU module In the multiple CPU system I O numbers are assigned to each CPU module to specify mounted CPU modules The I O number for each CPU module is fixed to the corresponding slot and cannot be changed in the I O assignment of the PLC parameter Table3 6 shows the I O number allocated to each CPU module when the multiple CPU system is composed Table3 6 I O number for each CPU module CPU module gt ri CPU slot Slot 0 Slot 1 Slot 2 9 Note3 2 mounting position First I O number 3E00H 3E10H 3E20H 3E30H The CPU modules I O numbers are used in the following cases When making communications between CPU modules When specifying a target CPU module for communication with MC protocol 2 1 Refer to CHAPTER 4 for communication between CPU modules 2 Refer to Q Corresponding MELSEC Communication Protocol Reference Manual for access to QCPU with MC protocol q Note3 2 Basic When the Basic model QCPU or Universal model QCPU QOOUCPU Q01UCPU Q02UCPU is used available
319. tting area in CPU No 1 CPU No 2 detects that the send data setting complete flag D0 0 turns on 7 8 9 1 CPU No 2 turns on the receive data processing complete flag D10 0 CPU No 2 writes the receive data processing complete flag to the user setting area in CPU No 2 CPU No 1 detects that the receive data processing complete flag D10 0 turns on CPU No 1 turns off the send data setting complete flag DO O 11 CPU No 1 writes the send data setting complete flag to the user setting area in CPU No 1 1 14 CPU No 2 writes the receive data processing complete flag to the user setting area in CPU No 2 CPU No 2 turns off the receive data processing complete flag D10 0 weiBoid Aq Aiowaw pareys 142 Bursn uogeoiunuiuoo p L p AJowaw peeus 142 Buisn se npoui Ndo ueewjeq suoneoiunuluo9 py 12 CPU No 2 detects that the send data setting complete flag DO 0 turns off 3 Figure 4 43 Interlock program example 4 42 4 43 2 Using multiple CPU high speed transmission area In the direct access mode the data is transferred in order starting from the one which was written to the user setting area first Using the device which is written after the data transfer regardless of kinds of device or addresses can realize the data consistency of the transferred data Example for program executing interlock in CPUs No 1 and No 2 is shown in Figure 4 44
320. tting completion bit Auto refresh execution between multiple CPUs 3 CPU No 2 detects the completion of send data setting 4 CPU No 2 performs receive data processing 5 CPU No 2 turns on the completion of receive data processing Auto refresh execution between multiple CPUs 6 CPU No 1 detects the completion of the receive data processing and turns off the data setting completion bit Auto refresh execution between multiple CPUs 7 CPU No 2 detects that the data setting complete bit turns off and turns off the receive data processing completion Figure 4 22 Interlock program example AJOWSW pegeus Add Husn useJje1 one Aq uoneoiunuulo2 Zp y AJowaw peeus 142 Buisn se npoui Ndo ueewjeq suoneoiunuluo p 4 22 4 1 3 Communication by auto refresh using multiple CPU high speed transmission area The following describes the communication by the auto refresh using the multiple CPU high speed transmission area in the Universal model QCPU The communication by the auto refresh using the multiple CPU high speed transmission area can be performed only when the following conditions are all met The multiple CPU high speed main base unit Q38DB or Q312DB is used The Universal model QCPU except the QQOUCPU Q01UCPU Q02UCPU is used as the CPU No 1 At least two modules are used among the Universal model QCPU except the QOOUCPU Q01UCPU QO2UCPU and the Motion CPU Q172DCPU Q173DCPU Communication using t
321. u ainpow Ajddns samod e npouJ Jejoguo2 2 z 1dOO epow Jesjenu z 1dO0 lepoui JesJeAtu einpoui A ddns 190g ainpow Ja JONUOD 9 e npouJ Jejouo2 9 exPINDOW dd z NdI epow JesjeAu einpoui A ddns 190g 3 icu o 1 2 e 9 npouu NdI Aiduie 5 1d e 9Jnpouu f1dO z NdOO Iepoui Jesjenu ajnpow A ddns 190g 2INPOw Adwe d1d can be mounted and Motion CPU Q172UDCPU Q173UDCPU can be 3 15 ex 9INDOW dO ex 9 NPOW NdI SInpoui ndo d90 fido n NdIO Aduie 21d al f1d90 Bpow 5 JesueAiu e npoui Ajddns 190g e 9 pou dO cx SINDOW ndo T zMdOO epow 5 JesueAiu ainpow A ddns JamMod popu o 1 2 z 1dO9O0 epow Jes1eAu z 1dOO0 epow JesueAu ainpow Ajddns amod z 1dO0 epow JesueAiu z 1d90 lepou JesueAiu ainpouw A ddns JaM0d z MdOD epow JesJaAlun 2 nd90 Iepou JesueAlu e npoui Ajddns 190g CPU o 1 2 Ajduie 21d z 1d90 JepouJ jesueniun ajnpow Ajddns 190g No of CPUs a No of CPUs indicates the value set in the multiple CPU setting of the PLC parameter 1 2 Universal model QCPU except the QOOUCPU Q01UCPU QO2UCPU 3 Universal model QCPU except the QOOUCPU Q01UCPU Q02UCPU mounted 4 High Performance model QCPU and Process CPU can be mounted 5 The PC CPU module occupies 2 slots 6 The PC CPU module PPC CPU852
322. uilt in Ethernet port QCPU can use the software only by USB connection 2 51 CHAPTER2 SYSTEM CONFIGURATION 2 4 Precautions for system configuration Restrictions on the system configuration using the Q series CPU module are provided in this section 1 Modules of restricted quantity The number of mountable modules and supported functions are restricted depending on the module type For the number of modules that can be mounted for each Motion CPU or PC CPU module refer to each CPU module manual a When using the Basic model QCPU Table2 21 Modules of restricted quantity Number of modules that Quantity restriction per Product Model can be mounted per QCPU system CC Link IE controller network QJ71GP21 SX Up to 4 Only 1 module module QJ71GP21S SX modules Up to 4 ITIL modules in POJIBRT total Only one One module e QU71LP21 25 Only 1 module Q series MELSECNET H Up to 4 module can be only on the QJ71LP21S 25 network module md modules controlled by PLC to PLC QCPU network QJ71LP21GE QJ71NT11B QJ71E71 Q series Ethernet interface module QJ71E71 B2 QJ71E71 B5 QJ71E71 100 Only 1 module Controllable with QCPU only Only 1 module Up to 10 modules Q series CC Link system e QJ61BT11 T 2 moau b U 2 modules master local module QJ61BT11N Up tos modules vamos Pioa mogues controlled by QCPU Up to 3 modules 2 Interrupt module QI60 Only 1 module can be
323. ule 4 uununn CPU module 3 ununnn Dm CPU module 2 oo0000 Til CPU module 1 Q series power supply module 32 point modules are mounted on each slot E Extension base unit 2 1 System configuration 2 1 2 System configuration using High Performance model QCPU or Process CPU as CPU No 1 1st Q612B 12 slots occupied TIRARA AE HEEEEERE ood ogo x o o o o ojo E fon Ton Ke Ke Ke o amp Je9olozo 8g J 201024 A v 8 ojojojojojo z d4i901009 l 4Ji401007 55 ARBRAR 8 449 039 8 449 039 z 5 9 4qs 099 5 409 9 099 1 pewgiul Ree a ee te pee NT das ol ovs 499 0v9 i peuqiuu __ s 46s0108S 8 46901089 8 364 01 087 o o o 449 01095 3 429 0 099 2 8 ALL 01 097 89 s9 ops 8 8 499 079 8 3 ASLO OZ z E 2 2 E ojojojojo 3 3 3 2 olto o o o eo eo wo a ab B R 46z 01 08z
324. unction module e QJ61BT11 QJ61BT11N e ATSJ71PT32 S3 A1SJ71T32 S3 No restriction No restriction Auto refresh setting not allowed No restriction 1 No restriction Auto refresh setting not allowed ATSD51S ATSD21 S1 A1SJ71J92 S3 When using GET PUT service Up to 6 modules Up to 6 modules Interruption module A1SI61 2 Only 1 module QI60 Up to 4 modules 4 Up to 3 modules when the A1SI61 is in use Only 1 module 4 GOT GOT A900 series Bus connection only 3 GOT1000 series Bus connection only 3 Up to 5 modules Up to 5 modules 1 One CPU module with CC Link network parameter setting in GX Developer can control the following number of the CC Link master local modules The CPU module whose first five digits of serial number is 08031 or lower up to 4 The CPU module whose first five digits of serial number is 08032 or later up to 8 2 This module can be used when a High Performance model QCPU is set to a controlled module When the Process CPU is used in conbimation however it cannot be used gt Section 7 1 3 For the available GOT model name refer to the following manuals When the Universal model QCPU is used GOT A900 Series cannot be used L3 GOT A900 Series User s Manual GT Works2 Version2 GT Designer2 Version2 compatible Connection System Manual 7 GOT1000 Series Connection User s Manual 4 Can be u
325. unit or extension base unit s Table3 8 Modules that can load inputs I O allocation type Mounted module Input module High speed input module None 7 I O composite module Intelligent function module Input module Input High speed input module High speed input 2 I O mix Output module l O composite module Intelli Intelligent function module 1 When input X loading is performed for QX48Y57 of I O composite module input X is loaded as all points OFF in Xn8 to XnF assigned to output part Xn Loads ON OFF of input X Xn7 Yn8 Xn8 Loads input X as all points OFF YnE XnE OOF sas cbr REPRE cece 4 QX48Y57 QCPU Figure 3 23 Loading of input X from QX48Y57 SN 2 When input X loading is performed for output module input X is loaded as all points OFF 3 Input data cannot be loaded from empty slots and remote stations on MELSECNET H or CC Link networks being controlled by the other CPU Use auto refresh of CPU shared memory to use the ON OFF input data for remote stations on MELSECNET H or CC Link in non controlled CPU Point By enabling ALL CPUS can real all outpus setting input data controlled by other CPUs can be loaded into the host CPU In this case if the forced ON OFF of external I O is activated for the input data loaded from other CPUs to the host CPU the data will be set into the specified
326. unit and the IN connector of the adjacent extension base unit by an extension cable When 66 modules or more are mounted 26 modules or more for the QOOUCPU or Q01UCPU 38 modules or more for the QO2UCPU an error SP UNIT LAY ERR error code 2124 occurs The number of mountable modules includes one CPU module No of CPUs is the number of CPUs set by No of PLC of GX Developer The PC CPU module and C Controller module cannot be mounted together therefore mount either of them The PC CPU module occupies two slots Therefore when the PC CPU module is used the maximum number of I O modules is decreased by 1 from the value indicated in the table For details of the Motion CPU C Controller module and PC CPU module refer to the manuals of each CPU module CHAPTER2 SYSTEM CONFIGURATION 2 When using the main base unit Q3L1B a System configuration Battery for QCPU Q6BAT High Performance Motion PC CPU C Controller model QCPU CPU 4 5 module 4 6 7 module 4 7 Q7BAT SET p DIU Foe SG Process CPU Universal model QCPU B type main base unit 2 is 2 a3 A 5 6 T 8 9 Q series power supply i lintelligent function module motion module 9 B type extension base unit 3 B type extension base unit 2 Only one memory card can be mounted Select an appropriate memory card from
327. upply module Keep the current consumption within the rated output current of the power supply module The Slim power supply module and Redundant power supply module are not available for the power supply module The Q Series power supply module is not required for the Q5LIB extension base unit The motion CPU and PC CPU module do not accept battery for QCPU and memory card For memory cards that can be used with the C Controller module refer to the manual of the C Controller module For the Motion CPU module only the Q172DCPU and Q173DCPU can be mounted The Motion CPU module can be mounted when using the Universal model QCPU except QOOUCPU Q01UCPU QO2UCPU Any Motion CPU cannot be mounted with the QOOUCPU Q01UCPU QO2UCPU The PC CPU module and C Controller module cannot be mounted together Be sure to set the control CPU of the motion module to the Motion CPU When the Q8BAT is used for the Universal model QCPU use the connection cable whose connector part displays A For details of connector part of a connection cable refer to the following manual lt QCPU User s Manual Hardware Design Maintenance and Inspection For further information on PC CPU module consult CONTEC Co Ltd Tel 81 6 6472 7130 following CPU modules can be used as the CPUs No 2 PC CPU module PPC CPU852 MS 512 C Controller module Note that the PC CPU module and C Controller module cannot be mounted together When the multiple CPU system is
328. using an extension cable keep it away from the main circuit high voltage and large current line Set the number of extension stages so as not to be duplicated Although there is no restriction on the connection order of the Q5L TB and the Q6LTRB check the availability of them by referring to QCPU User s Manual Hardware Design Maintenance and Inspection The QA1S6LIB QA6LB QA6ADP ASLIB AGLIB or Q6LIRB cannot be connected as an extension base unit Connect the OUT connector of an extension base unit and the IN connector of the adjacent extension base unit by an extension cable When 66 modules or more 26 modules or more for the QOOUCPU or Q01UCPU 38 modules or more for the QO2UCPU are mounted an error SP UNIT LAY ERR error code 2124 occurs The number of mountable modules includes one CPU module No of CPUs is the number of CPUs set by No of PLC of GX Developer The PC CPU module and C Controller module cannot be mounted together therefore mount either of them The PC CPU module occupies two slots Therefore when the PC CPU module is used the maximum number of I O modules is decreased by 1 from the value indicated in the Table2 9 For details of the Motion CPU C Controller module and PC CPU module refer to the manuals of each CPU module CHAPTER2 SYSTEM CONFIGURATION 3 When using the redundant power main base unit Q30RB a System configuration High Performance model QCPU G Process CPU
329. uted at the timing of multiple CPU high speed transmis sion cycle Multiple CPU high speed transmission cycle 0 88ms Multiple CPU high speed transmission t H t Interrupt request v ENDO ENDV 0 END 0 Sequence program H H H cms th th dh th A ee synenronous 145 IRET 145 IRET 145 IRET 145 IRET 145 IRET interrupt program H I l Figure 4 49 Execution timing of multiple CPU synchronous interrupt program Point The multiple CPU synchronous interrupt is available when the following CPU modules are used e Universal model QCPU except QOOUCPU Q01UCPU Q02UCPU Motion CPU Q172DCPU Q173DCPU 4 53 CHAPTER4 COMMUNICATIONS BETWEEN CPU MODULES When a multiple CPU synchronous interrupt factor occurs during the execution of another interrupt program the running program is aborted to execute the multiple CPU synchronous interrupt program Interrupt request from 145 Interrupt request from In END 0 Sequence program 4 r In IRET Interrrupt program S a Multiple CPU synchronous 145 IRET l interrupt program Figure 4 50 Processing of multiple CPU synchronous interrupt program during interrupt program execution 3 Operation when the interrupt factor occurs For operation when the interrupt factor occurs refer to the following manual L3 User s Manual Function Explanation Program Fundamentals for the CPU module used 4 Restrictions on creating the pro
330. utions for use of AnS A series compatible modules a Accessible device range When using the following AnS A series compatible modules accessible device range is restricted as shown on Table7 2 A1SD51S AD51 S3 AD51H S3 type intelligent communication module Table7 2 List of accessible device ranges Device Accessible device range Input X Output Y X YO to 7FF Internal relay M Latch relay L MILO to 8191 Link relay B BO to FFF Timer T TO to 2047 Counter C CO to 1023 Data register D DO to 6143 Link register W WO to FFF Annunciator F FO to 2047 ainpow sjqnedwoo sees y Suy Jo esn 10J suonneoasJd pZ 7 3 7 4 b Unavailable modules The modules shown in Table7 3 cannot be used Table7 3 List of unavailable modules Module Name Type MELSECNET 10 network module A1SJ71LP21 A1SJ71BR11 A1SJ71QLP21 A1SJ71QLP21S A1SJ71QLP21GE A1SJ71QBR11 AJ71LP21 AJ71LP21G AJ71BR11 AJ71LR21 AJ71QLP21 AJ71QLP21S AJ71QLP21G AJ71QBR11 AJ71QLR21 MELSECNET Il B data link module A1SJ71AP21 A1SJ71AR21 A1SJ71AT21B AJ71AP21 AJ71AP21 S3 AJ71AR21 AJ71AT21B Ethernet interface module A1SJ71QE71 B2 S3 B5 S3 A1SJ71E71 B2 S3 B5 S3 AJ71QE71N B5T AJ71E71 B2 B5T Serial communication module or computer link module A1S8J71QC24 N A1SJ71UC24 R2 PRF AJ71QC24N N AJ71QC24N R2 R4 A1SJ71UC24 AJ71UC24 Computer link or multidrop link module A1SJ
331. uwju Sele cum o o r jojm naju i cz OINO oD SM om wo ooo mii Gi Oi o o e e elg eg s 9 2 2 2 2 8 2 8 2 8 2 8 8 lgl elZ EH l sla Oo wo je 2 aap S 1 li Error in mounting When the QOOUCPU Q01UCPU and Q02UCPU are used as the CPU module 1 up to second CPU modules can be mounted Therefore the CPU modules 3 and 4 do not exist When the QOOUCPU Q01UCPU and QO2UCPUCPU are used as the CPU module 1 CPU modules cannot be mounted on the 26th slot or later or 38th or later on the following conditions Therfore if a module is mounted on the following conditions an error SP UNIT LAY ERR error code 2124 occurs Maximum number of slots for the QOOUCPU QO01UCPU 25 slots Maximum number of slots for the QO2UCPU 37 slots When the QOOUCPU Q01UCPU Q02UCPU is used as the CPU module 1 up to four extensions can be connected Therefore five to seven extensions do not exist Figure 2 16 System configuration example for using Q30DB 2 26 LON Nd S NddD 9pouu jesJeAluf Buisn uoneunByuoo uejs sS ELZ uongeunByuoo wa Js S Lc Table2 8 Restrictions on system configuration available base units extension cables and power supply modules CPU number CPU module1 CPU No 1 CPU module 2 CPU No 2 CPU module 3 CPU No 3 CPU module 4 CPU No 4 Maximum number of extension stages 7 extension stages
332. v 3E00 Switch setting a PLCNo2 v EN PLC PLCNo3 v 3E2 Detailed setting PLC PLCEmpty v 3E30 3t 3 4 4 KIKI 5 B8 Assigning the 1 0 address is not necessary as the CPU does it automatically Leaving this setting blank will not cause an error to occur Base setting Base made Base model name Power model name Estension cable WA C Detail B Slot Default 12 Slot Default Aer cebu ee Ne Import Muliple CPU Parameter _ Read PLC deta Acknowledge XY assignment Multiple CPU settings Defaut Check End Cancel Figure 6 2 Empty slot setting screen Point In the mounted CPU module of CPU No 1 errors occur caused by the following error factors 1 or 2 1 When the number of mounted CPU modules exceeds the number set with the No of CPU settings a When CPU No 1 is Basic model QCPU Universal model QCPU CPU LAY ERROR error code 7030 occurs b When CPU No 1 is High Performance model QCPU or Process CPU PARAMETER ERROR error code 3010 occurs 2 When CPU modules of which numbers are set in the No of CPU setting are not mounted in the CPU module mounting slots a When CPU No 1 is Basic model QCPU Universal model QCPU CPU LAY ERROR error code 7031 occurs b When CPU No 1 is High Performance model QCPU or Process CPU PARAMETER ERROR error code 3010
333. ver clock data can be configured for the CPU No 1 in any of Universal model QCPUS since the clock data configured for the CPUs other than the CPU No 1 will be changed to clock data for the CPU No 1 woo ED 3 34 When using the High Performance model QCPU and the Process CPU as CPU No s 2 to 4 the clock data of CPU No 1 cannot be set to other CPUs When using the Basic model QCPU only the Motion CPU Q172CPUN T Q173CPUN T Q172HCPU T Q173HCPU T and the PC CPU module can be used as CPU No s 2 and 3 The clock data of the Basic model QCPU cannot be set to other CPUs Set clock data of each CPU CHAPTER3 CONCEPT FOR MULTIPLE CPU SYSTEM 3 8 2 Clock data used by intelligent function module Some intelligent function modules store an error code and time clock data read from QCPU into the buffer memory when an error occurs The CPU No 1 time data will be stored as the time for the error regardless of whether the module concerned is a control CPU or a non control CPU e npouJ uonounj jueBij o1ur q pesn ejep X90 D Z gE e npouJ uonouny 1ueBi jejur pue ejnpow 3H2 Aq pesn gep yoo D gE 3 35 3 9 Resetting the multiple CPU system The entire multiple CPU system can be reset by resetting CPU No 1 The CPU modules of No 2 to No 4 I O modules and intelligent function modules will be reset when CPU No 1 is reset If a stop error occurs in any of the CPUs on the multiple CPU system either reset CPU No 1 or restart
334. ween CPU modules Therefore even when the CPU module will be added to the system CPU No of a CPU module to be added is not changed and changing the program is unnecessary CPU o 1 2 j Slot number CPU o 1 2_ lt Slot number a 2 o o o nm model QCPU Universal model QCPU m a 2 o o o A module Universal Motion CPU Universal model QCPU Universal model QCPU Universal model QCPU Motion CPU Added Universal model QCPU Figure 3 13 PLC Empty setting between CPU modules Note that when using either of the following CPU modules PLC Empty cannot be set to the left side of the CPU module High Performance model QCPU Process CPU To add the High Performance model QCPU to the system including the PC CPU module C Controller module the PC CPU module C Controller module must be moved to the right edge Set slot 2 to PLC empty y Keep slot 3 empty icpUu o 1 2 3 4 Slt icPU o 1 2 3 4 lt Slot number number Power supply High Performance model QCPU High Performance model QCPU High Performance model QCPU module model QCPU gt oe 2 2 o o z o n Universal Empty Input module Universal model QCPU Input module A n Addition et Move these modules to the right o a c ED oA tO eg E E TE Figure 3 14 Addition of the High Performance model QCPU when the PC CPU module is mounted
335. xtension QC05B QC06B QC12B QC30B QC50B QC100B cable model Available power Q61P A1 Q61P A2 Q61P Q61P D Q62P Q63P Q64P Q64PN supply module model Precautions Do not use an extension cable longer than 13 2m 43 31 ft When using an extension cable keep it away from the main circuit high voltage and large current line Set the number of extension stages so as not to be duplicated The QA1S6LIB QA6LIB QA6ADP A5LIB A6LB or Q6RLIB cannot be connected as an extension base unit Although there is no restriction on the connection order of the Q5LB and the Q6L IB check the availability of them by referring to QCPU User s Manual Hardware Design Maintenance and Inspection when both the Q5LB and the Q6LB exist as the extension base unit Connect the OUT connector of an extension base unit and the IN connector of the adjacent extension base unit by an extension cable When 26 modules or more are mounted an error SP UNIT LAY ERR error code 2124 occurs The number of mountable modules includes one CPU module The redundant base unit cannot be used when the Basic model QCPU is mounted on the multiple CPU system No of CPUs is the number of CPUs set by No of PLC of GX Developer The PC CPU module occupies two slots Therefore when the PC CPU module is used the maximum uongeunByuoo ueljs S Lc number of I O modules is decreased by 1 from the value indicated in Table2 1 The PC CPU module and C
336. xtension cables and power supply modules CPU number CPU module1 CPU No 1 CPU module 2 CPU No 2 CPU module 3 CPU No 3 CPU module 4 CPU No 4 Maximum number of extension stages 7 extension stages Maximum number of mountable I O modules 65 No of CPUs Available main base unit model Available extension base unit model Q33B Q35B Q38B Q312B Type not requiring power supply module Q52B Q55B QAGADP ASLIB Type requiring Q series power supply Q63B Q65B Q68B Q612B module Type requiring AnS series power supply QA1S65B QA1S68B module Type requiring A series power suppl iid 9 P PES QA65B QA68B QA6ADP A6L1B module Available extension QCO05B QC06B QC12B QC30B QC50B QC100B cable model Q series power supply module Q61P A1 Q61P A2 Q61P Q61P D Q62P Q63P Q64P Q64PN Available power AnS series power supply module A1S61PN A1S62PN A1S63P supply module model A series power supply module A61P A61PN A62P A63P A61PEU A62PEU Precautions 2 13 q Do not use an extension cable longer than 13 2m 43 31 ft When using an extension cable keep it away from the main circuit high voltage and large current line Set the number of extension stages so as not to be duplicated When the Q5L1B Q60B QA1S6L 1B QA6LIB and QAGADP A5B AGLTB are used together as the extension base unit mount the Q5LIB QeL 1B QA1S6L 1B QAeGLIB and QA6ADP

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