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Integer Arithmetic IP Cores User Guide

1. N 1 y t 2 YB A t i i 0 N represents the number of cycles of data that has entered into the accumulator y t represents the output at time f A t represents the input at time f and B i are the coefficients The t and i in the equation correspond to a particular instant in time so to compute the output sample y t at time t a group of input samples at N different points in time or A n A n 1 A n 2 A n N 1 is required The group of N input samples are multiplied by N coefficients and summed together to form the final result y The systolic register architecture is available only for sum of 2 and sum of 4 modes The following figure shows the systolic delay register implementation of 2 multipliers ALTMULT ADD Multiply Adder Altera Corporation LJ Send Feedback UG 01063 9 8 Systolic Delay Register 2014 12 19 Figure 9 8 Systolic Delay Register Implementation of 2 Multipliers chainin a0 MultO Systolic registers bO Mult al lt result The sum of two multipliers is expressed in the following equation y t al t x b1 t a0 t 1 x bO t 1 The following figure shows the systolic delay register implementation of 4 multipliers Altera Corporation ALTM
2. 7 3 Paratineteto u aee temen a ies P are e t qe eese ae edo te deuil eset idee ivive sre E IER 7 4 Destan Example 5 x8 NUBE quu ceo ente ec net alcun as Fa et lad GUAE E E a OR LUN RM 7 5 Understanding the Simulation Resills iiuun qt Wd DR DUI tM bI NIME d TUE 7 6 ALTMULT ACCUM Multiply Accumulate eere eere eene 8 1 hu aS 8 2 Resource Utilization and Perfo miance oua ise svi S RO QA UE R USRTRN NNI UR ANNA EISE MR AEN RUN TE 8 2 Altera Corporation TOC 4 Integer Arithmetic IP Cores User Guide Verilog HDL Prototype P X aS 8 4 VHDL Component Declan ah its oui pasear ote otro ala Leg lu oi ds bebe UNE ARENA 8 4 VHDL LIBRARY USE Declaration ce ttis eter eT Here eer ruin 8 4 ALTIMULT ACCUM Ports 3 aate pic ate ren a ne n eed b Ce D RE Rc cR e Uni e d ns 8 4 ATLTMULT ACCU M Paratnetetsnitoeo tasto reno Fiant Cet ee reet eee ert te e este etn risen 8 6 Design Example Shift Accummulatot auae api Rr das rto aoa be dba Rr a Rat eda 8 19 Understanding the Simulation Results aiio iore Hem n PR D DI A RRNGI MEE pRIE 8 19 ALIMULI ADD Multiply Adder eoe pntir eo tetsnketeap exu o DEOR ira epu ERR EE Ren ERHIE 9 1 uu 9 3 yrs e 9 4 Systolic Delay Registers 9 7 Pie Tie tS EN M
3. INPUT R EGISTER Gil String Specifies the clock port for the datac operand of the second multiplier Values are UNREGISTERED CLOCKO CLOCK1 and cLock2 If omitted the default value is CLOCKO The value must be set similar to the value of INPUT_REGISTER_AO or Set as UNREGISTERED INPUT_R EGISTER C2 String No Specifies the clock port for the atac operand of the third multiplier Values are UNREGISTERED CLOCKO CLOCK1 and crocxk2 If omitted the default value is cLockO0 The value must be set similar to the value of INPUT REGISTER A0 or set as UNREGISTERED INPUT RE GALS IR CS String Specifies the clock port for the datac operand of the fourth and corresponding multiplier Values are UNREGISTERED CLOCKO CLOCK1 and cLock2 If omitted the default value is CLOCKO The value must be set similar to the value of INPUT REGISTER AO Or set as UNREGISTERED MUTIPLI ERI DIRE CTION String No Specifies whether the second multiplier adds or subtracts its value from the sum Values are app and sus If the addnsub1 port is used this parameter is ignored If omitted the default value is ADD Altera Corporation ALTMULT ACCUM Multiply A
4. 2 2 VHDL Component Declarallobu ascen bo deben bites anasita thra ihr ci op ARE iE t E api 2 3 VHDL LIBRARY USE Declaration iet eti e eiai eto AN aeg eie X Renee a ne E ia 2 3 joe 2 3 Parameters ssescatescatecisdis 2 5 LPM DIVIDE Divider iiis ccsatsneoavth convent thun eR par ob RM BER VM Eus e SN TRE VeRE 3 1 Beat t Sciceeesoo RURRERRERIRRERRURR IE REESE ERAS NI IE 3 1 Resource Utilization and Pes For ditt iste doc i che atest lipucdpoa di hana dris nta ordi tua c cedi 3 1 Veril g HDL Prototype AUC ONTe 3 2 VHDL Component Declaralidli uiuat hene ek iirinn EREA R AENEAN EEKE RE E 3 2 VHDL LIBRARY USE Declaration eintreten e ERR RE Reef HERI te dees iai 3 3 d 3 3 DAVAO LOLS ss 9 3 3 LPM MULT Multiplie jcicscwasicrmmaniincnsaecnienciinus aan y eV ERE MN E 4 1 nii 4 1 Resource Utilization and Perfotbntatiee uie aeri iore ptrt tol ure teked a eoi INR ER IHE QA REPE NRREN EI VAN ERU E 4 1 Verilog HDL PEOLODVDO acuenesuae inniit ARR ARENAEN cR et EDU AR d 4 2 VHDL Component Declaratioti zu eid nu IR pi DOE Od a M UNSER a 4 3 VEHDE LIBRARY USE DeclaratiOT aed iter eerte i Ei nen d Ere ene roce seis es 4 3 LPM LM 4 3 LPM MULT Par areters z hoe rete eve reos ied PR E FO QVE ee ERE Ean 4 4 Altera Corporation Integer
5. ACCUM SLOAD ACLR String No Specifies the asynchronous clear source for the first register on the accum s1oad or sload accuminput Values are NONE ACLRO and ACLR1 If omitted the default value is NONE SCANOUTA REGISTER String No Specifies the clock source for the scanouta data bus registers Values are UNREGISTERED CLOCKO CLOCK1 and cLock2 If omitted the default value is UNREGISTERED SCANOUTA ACLR String No Specifies the asynchronous clear source for the scanouta data bus registers Values are NONE ACLRO ACLR1 and ACLR2 If omitted the default value is None WIDTH C Integer No Width of the datac port WIDTH COEF Integer No Specifies the width of the constant value stored ALTERA MULT ADD Multiply Adder J send Feedback Altera Corporation 6 16 ALTERA_MULT_ADD Parameters UG 01063 2014 12 19 TINPUTOREGISTERSE 0 3 String Specifies the clock port for the datac operand of the multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOCK2 If omitted the default value is UNREGISTERED INPUT REGISTER C 1 3 R must have similar values with INPUT EGISTER C 0 INPUT ACLR C O0 3 String No Specifies the asynchronous clear for the datac operand of the multiplier Valu
6. 9 10 Double AccumulatOT ssiri op atas cel an Rob TOT ESTE bt va RITES C o Te POOP AA Rua ed 9 10 Resource Utilization and Pertforimance sacus esee crasiendeceka bitur aber APR EA YEARS UBRO HR GHI OR HL 9 11 Verilog HDL Prototype uenotenecaoie nte pria iatan ai Da nitens aui o pU HR UK I aa 9 11 VHDL C mp nent Dec ata OR ono escrito DUPRmoRUL Pt TU goes Ed HOptrdc enti otav ul e Ru par mU RR 9 11 VHDL LIBRARY USE Declaration rer scancacenshndsssenecensnsesdunnacendesevessusaunansevcuaaesds 9 12 ALTMUELT ADD Ports tette eii be i Ge Ee e ERE E dede eee e d rU a aen 9 12 ALTMULT ADD Para t ts 4 cscs nece rtr ooa aout Ero elo ones edis iaaa ed aed eda eae 9 14 Design Example Implementing a Simple Finite Impulse Response FIR Filter 9 34 Understanding the Simulation Resulls uie ttti petes bite obti u du ia tUa M nih 9 35 ALTMULT COMPLEX Complex Multiplier eere 10 1 Compl x Multiplication P EC M M 10 2 Canonical Representation P 10 2 Conventional RepresentatiofL cu eno euen p eerie iustis aarteista eaS Er IAA KE prp eoo TAEAE e 10 3 hun l 10 3 Resource Utilization and Dettormdie uino tibi dvo Fen a RP OH radi en po cadi 10 4 Verilog HDL Prototype can eio aquetbun eu pam itn MdB dum NN S NN M NEM 10 4 VHDL Component DeclaratiOlh uocant sbMpda pesa deeplseevn std Q
7. SHIFT_RIGHT_REGISTER String No Specifies the clock source for the first register on the snift right input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO SEDIBISECGEDEEAC TE String No Specifies the asynchronous clear source for the first register on the shift right input Values are NONE ACLRO ACLR1 ACLR2 and ACLR3 If omitted and sHIFT_ RIGHT REGISTER is used the default value is ACLR3 SHIFT RIGHT PIPELINE REGISTER SHIFT RIGHT PIPELINE ACLR String No Specifies the clock source for the second register on the shift right input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO String No Specifies the asynchronous clear source for the second register on the shift right input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and SHIFT_ RIGHT PIPELINE REGISTER is used the default value is AcLR3 SHIFT RIGHT OUTPUT R EGIST ER String No Specifies the clock source for the third register on the shift_ right input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cCLOCK3 If omitted the default value is cLOCKO SA TETARTCHTEOUTEUTEACIR String No _ Specifies the asynchronous clear source for the th
8. DSP BLOCK BALANCING String No Specifies whether to use DSP block balancing Values are UNUSED Auto DSP blocks Logic Elements Off Simple Jg leuig WMiuuhe aol sews Simple Multipliers and Mieka TS e Multipliers EXTRA_ACCUMULATOR_LATENCY String Adds the number of clock cycles of latency specified by the OUTPUT_REG parameter to the accumulator portion of the DSP block EXTRA_MULTIPLIER_LAT ENCY Integer No Specifies the number of clock cycles of latency for the multiplier portion of the DSP block If the MULTIPLIER_REG parameter is specified then the specified clock port is used to add the latency If the MULTIPLIER_REG parameter is set to UNREGISTERED then the c1ock0 port is used to add the latency INPUT_ACLR_A String No Specifies the asynchronous clear port for the dataa port Values are ACLRO ACLR1 ACLR2 and AcLR3 If omitted the default value is ACLR3 Altera Corporation ALTMULT ACCUM Multiply Accumulate C Send Feedback UG 01063 2014 12 19 ALTMULT_ACCUM Parameters 8 9 TNBUTEACLREB String Specifies the asynchronous clear port for the aatab port Values are ACLRO ACLR1 ACLR2 and AcLR3 If omitted the default value is ACLR3 INPUT_REG_A String Specifies the clock port for the dataa port Values are UNREGISTERED CLOCKO CLOCK1 CLOC
9. INPUT ACLR C1 String No Specifies the asynchronous clear for the datac operand of the second multiplier Values are ACLRO and ACLR1 If omitted and corresponding INPUT_ REGISTER C is used the default value is acLRO The value for INPUT ACLR C1 must be set similar to the value of INPUT_ACLR_AO INPUT ACLR C2 String No Specifies the asynchronous clear for the datac operand of the third multiplier Values are ACLRO and AcLR1 If omitted and corresponding INPUT REGISTER C is used the default value is acLRO The value for INPUT ACLR C2 must be set similar to the value of INPUT ACLR AO INPUT ACLR C3 String No Specifies the asynchronous clear for the datac operand of the fourth and corresponding multiplier Values are ACLRO and ACLR1 If omitted and corresponding INPUT_REGISTER_C is used the default value is ACLRO The value for INPUT_ ACLR_C3 must be set similar to the value of INPUT_ACLR_ AO ALTMULT_ACCUM Multiply Accumulate J send Feedback Altera Corporation 8 14 ALTMULT_ACCUM Parameters UG 01063 2014 12 19 INPUT_RE GISTE String Specifies the clock port for the atac operand of the first mE Values are UNREGISTERED CLOCKO CLOCK1 and cLock2 If omitted the default value is cLock0 The value must be set similar to the value of INPUT REGISTER A0 Or set as UNREGISTERED
10. N ERO_LOOPBACK_PIPELINE_ACLR String Specifies the asynchronous clear source for the second register on the zero_loopback input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and zERO_ LOOPBACK PIPELINE REGISTER is used the default value is acLR3 Altera Corporation ALTMULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 N Parameter Name ERO_LOOPBACK_OUTPUT_REGISTER ALTMULT_ADD Parameters 9 31 Type Requi Description red String No Specifies the clock source for the third register on the zero_ loopback input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is cLocKo N ERO_LOOPBACK_OUTPUT_ACLR String No _ Specifies the asynchronous clear source for the third register on the zero_loopback input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and zERO_ LOOPBACK OUTPUT REGISTER is used the default value is AcLR3 ACCUM SLOAD REGISTER String No Specifies the clock source for the first register on the accum s1oad input Values are UNREGISTERED CLOCKO0 CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO ACCUM SLOAD ACLR ACCUM SLOAD PIPELINE REGISTER String No Specifies the asynchronous clear source for the first register on the accum sload input Val
11. CHAINOUT_ADDER String No _ Specifies the chainout mode of the final adder stage Values are YEs and no If omitted the default value is no ACCUMULATOR String No _ Specifies the accumulator mode of the final adder stage Values are YES and no If omitted the default value is No When value is set to YES rounding is dynamic and you must initialize the accumulator while rounded data is acquired Table 9 9 ALTMULT ADD Megafunction Parameters Stratix Ill and Stratix IV Devices Only red WIDTH CHAININ Integer Width ofthe cnainin port WIDTH CHAININ equals WIDTH_ RESULT if port chainin is used If omitted the default value is 1 ALTMULT ADD Multiply Adder Altera Corporation LJ Send Feedback 9 26 ALTMULT_ADD Parameters Parameter Name OUTPUT_ROUNDING UG 01063 2014 12 19 Type Requi Description red String No _ Enables rounding handling at second adder stage If original design uses a Stratix II device in some cases this parameter can be derived from the Stratix II rounding settings Values are YES NO and VARIABLE A value of YES or NO specifies saturation handling setting permanently to on or off A value of VARIABLE allows dynamically controlled saturation handling OUTPUT_ROUND_TYPE String No _ Specifies the rounding mode Values are NEAREST_EVEN and NEAREST_INTEGER A value of NEAREST_EVEN specifies round to nearest even A v
12. The default value is UNUSED LPM TYPE String No Identifies the library of parameterized modules LPM entity name in VHDL design files Design Example 9 bit Square Root This design example uses the ALTSQRT megafunction to generate a 9 bit square root This example uses the MegaWizard Plug In Manager in the Quartus II software The following design files can be found in altsqrt DesignExample zip altsqrt qar archived Quartus II design files altsqrt ex msim ModelSim Altera files Understanding the Simulation Results The following settings are observed in this example e The width of the input port radical is set to 9 bits e The widths of the output ports q and remainder are set to 5 bits and 6 bits respectively e The asynchronous clear aclr and clock enable ena input ports are enabled Theoutput latency is set to two clock cycles Hence the result is seen on the q port two clock cycles after the input data is available The following figure shows the expected simulation results in the ModelSim Altera software Figure 11 2 ALTSQRT Simulation Results 4 faltsqrt_ex_vig_vec_tst aclr 4 altsqrt ex vig vec tstjclk Jalsqrt ex vig vec tst ena jalsqrt ex vig vec tstjradical MEL Nr 4 jalsqrt ex vlg vec tstlremainder PME Ord oou Altera Corporation ALTSORT Integer Square Root C Send Feedback PARALLEL_ADD Parallel Adder 1 2 2014 12 19 UG 0
13. addnsub3 addsub1_round i addsub3_round i clock enad clock1 l enat mult is saturated i clock2 i ena2 clock3 ena3 i output_round output_saturate chainout_round chainout_saturate mult round chain out sat overflow mult saturation i 1zero chainout accum sload zero loopback chainin i1 shift right rotate inst gru oo0 0 C G GG A multiplier adder accepts pairs of inputs multiplies the values together and then adds to or subtracts from the products of all other pairs The ALTMULT ADD megafunction also offers many variations in dedicated DSP block circuitry Data input sizes of up to 18 bits are accepted Because the DSP blocks allow for one or two levels of 2 input add or subtract operations on the product this function creates up to four multipliers Stratix III and Stratix IV device families use two MAC blocks mac mult and mac out to form DSP operations multiply and add For Stratix V devices the multiplier blocks and adder accumulator block is combined in a single MAC block Altera Corporation ALTMULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Features 9 3 The multipliers and adders of the ALTMULT_ADD megafunction are placed in the dedicated DSP block circuitry of the Stratix devices If all of the input data widths are 9 bits wide or smaller the function uses the 9 x 9 bit input multip
14. The following figure shows the pre load constant implementation Figure 6 11 Pre load Constant constant Accumulator feedback MultO a0 bO r c result al F Mult gt S bl AS accum sload Refer to the following megafunctions in this user guide for other multiplier implementations e ALTMULT ACCUM Multiply Accumulate e ALTMEMMULT Memory based Constant Coefficient Multiplier e LPM MULT Multiplier Double Accumulator The double accumulator feature adds an additional register in the accumulator feedback path The double accumulator register follows the output register which includes the clock clock enable and aclr The additional accumulator register returns result with a one cycle delay This feature enables you to have two accumulator channels with the same resource count ALTERA MULT ADD Multiply Adder Altera Corporation C Send Feedback UG 01063 6 10 Verilog HDL Prototype 2014 12 19 The following figure shows the double accumulator implementation Figure 6 12 Double Accumulator Double Accu mulator Register Accumulator feedba ck lt MultO Co a0 bO Output result al Mult gt Output Register C9 bl Verilog HDL Prototype The following Verilog HDL pr
15. Table 3 3 LPM_DIVIDE Megafunction Output Ports quotient Yes Data output The size of the output port depends on the LPM_WIDTHN parameter value remain Data output The size of the output port depends on the LPM_WIDTHD parameter value Parameters LPM DIVIDE Divider Altera Corporation LJ Send Feedback 3 4 Parameters UG 01063 2014 12 19 The following table lists the parameters for the LPM_DIVIDE megafunction LPM_WIDTHN Integer Specifies the widths of the numer and quotient ports Values are 1 to 64 LPM_WIDTHD Integer Yes Specifies the widths of the denom and remain ports Values are 1 to 64 n LPM_NREPRE ENTATION String No Sign representation of the numerator input Values are SIGNED and UNSIGNED When this parameter is set to SIGNED the divider interprets the numer input as signed two s complement LPM_DREPRE n ENTATION String No Sign representation of the denominator input Values are SIGNED and uusrGNED When this parameter is set to SIGNED the divider interprets the denom input as signed two s complement LPM TYPE String No Identifies the library of parameterized modules LPM entity name in VHDL design files vhd LPM HINT String No When you instantiate a library of parameterized modules LPM function in a VHDL Design File vhd you mu
16. Post fit timing simulation netlist Optional Post fit timing simulation TimeQuest Timing Analyzer Device Programmer Note Post fit timing simulation is not supported for 28nm and later device archetectures Altera IP supports a variety of simulation models including simulation specific IP functional simulation models and encrypted RTL models and plain text RTL models These are all cycle accurate models The models support fast functional simulation of your IP core instance using industry standard VHDL or Verilog HDL simulators For some cores only the plain text RTL model is generated and you can simulate that model Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design Altera Corporation Integer Arithmetic Megafunctions C Send Feedback UG 01063 2014 12 19 Simulating Altera IP Cores in other EDA Tools 1 13 Related Information Simulating Altera Designs Integer Arithmetic Megafunctions Altera Corporation C Send Feedback LPM COUNTER Counter 2014 12 19 UG 01063 GX subscribe C Send Feedback The LPM_COUNTER megafunction is a binary counter that creates up counters down counters and up or down counters with outputs of up to 256 bits wide The following figure shows the ports for the LPM_COUNTER megafunction Figure 2 1 LPM_COUNTER Ports LPM COUNTER Features The LPM
17. coefsel0 coef Pre adder Input Mode In this mode one multiplier operand derives from the pre adder and the other operand derives from the datac input port The following settings are applied in this mode The width of the dataa input wIDTH_A must be less than or equals to 25 bits e The width of the datab input wIDTH_B must be less than or equals to 25 bits e The width of the datac input wIDTH_c must be less than or equals to 22 bits The number of multipliers must be set to 1 e All input registers must be registered with the same clock This mode is expressed in the following equation y at b xc The following shows the pre adder input mode of a multiplier Figure 6 4 Pre adder Input Mode a0 MultO SQ result b0 lt lt c0 Pre adder Square Mode In this mode both multiplier operands derive from the pre adder Altera Corporation ALTERA_MULT_ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Pre adder Constant Mode The following settings are applied in this mode e The width of the dataa input wIDTH_A must be less than or equals to 17 bits e The width of the datab input wIDTH_B must be less than or equals to 17 bits e The number of multipliers must be set to 2 This mode is expressed in the following equation yw a0 b0 a1 b1 2 The following shows the pre adder square mode of
18. Resource Utilization and Performance The following table provides resource utilization and performance information for the LPM_DIVIDE megafunction O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01063 3 2 Verilog HDL Prototype 2014 12 19 Table 3 1 LPM_DIVIDE Resource Utilization and Performance Logic Usage Input data Output ETG Dedicated Adaptive Device family width laten
19. trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any ie egistere products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG 01063 6 2 Features 2014 12 19 For Stratix V devices the multiplier blocks and adder accumulator block is combined in a single MAC block The multipliers and adders of the ALTERA MULT ADD megafunction are placed in the dedicated DSP block circuitry of the Stratix devices If all of the input data widths are 9 bits wide or smaller the function uses the 9 x 9 bit input multiplier configuration in the DSP block If not the DSP block uses 18 x 18 bit input multipliers to process data with widths between 10 bits and 18 bits If multiple ALTERA_MULT_ADD megafunctions occur in a design the functions are distributed to as many different DSP blocks as possible so t
20. Table 2 3 LPM_COUNTER Megafunction Output Ports qt No Data output from the counter The size of the output port depends on the LPM_WIDTH parameter value Either q or at least one of the eq 15 0 ports must be connected Altera Corporation LPM COUNTER Counter G send Feedback UG 01063 2014 12 19 Parameters 2 5 eq 15 0 No The eq 15 0 Counter decode output The eq 15 0 port is not accessible using the MegaWizard Plug In Manager as it is for AHDL use only Either the q port or eq port must be connected Up to c eq ports can be used 0 lt c lt 15 Only the 16 lowest count values are decoded When the count value is c the eqc output is asserted high 1 For example when the count is 0 eq0 1 when the count is 1 eq1 1 and when the count is 15 eq 15 1 Decoded output for count values of 16 or greater require external decoding outputs are asynchronous to the q output cout No Carry out port of the counter s MSB bit It can be used to connect to another counter to create a larger counter Parameters The following table lists the parameters for the LPM_COUNTER megafunction Table 2 4 LPM_COUNTER Megafunction Parameters LPM WIDTH Integer Specifies the widths of the aatat and at ports if they are used LPM DIRECTION String No Values are UP Down and UNUSED If the LPM_ DIRECTION parameter is used the updown port cannot be connect
21. a0 MultO bO Output result al Multl gt lt Output Register bl a Resource Utilization and Performance The following table provides resource utilization and performance information for the ALTMULT_ADD megafunction Table 9 1 ALTMULT_ADD Resource Utilization and Performance Logic Usage Input data Output Adaptive Dedicated Adaptive Device family width rane Look Up Logic 18 bit DSP fmax MHz 9 Table Register ALUT 578 Stratix III 16x 16 3 0 0 0 2 645 32x32 3 0 0 0 4 454 64 x 64 3 217 128 146 16 145 Verilog HDL Prototype To view the Verilog HDL prototype for the megafunction refer to the Verilog Design File v altera mf v in the Quartus Il installation directory Yeda synthesis directory VHDL Component Declaration 9 The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column ALTMULT ADD Multiply Adder Altera Corporation LJ Send Feedback UG 01063 9 12 VHDL LIBRARY_USE Declaration 2014 12 19 To view the VHDL component declaration for the megafunction refer to the VHDL Design File vhd altera mf components vhd in the Quartus II installation directory gt libraries vhdl altera_mf directory VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the
22. altera mf components vhd in the Quartus Il installation directory gt libraries vhdl altera_mf directory VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY altera mf USI E altera_mf altera_mf_components all ALTMULT_ACCUM Ports The following tables list the input and output ports for the ALTMULT_ACCUM megafunction Note For Arria V Cyclone V and Stratix V devices each register can select between two asynchronous clear signals ACLRO ACLR1 and three clock enable pairs cLocko i E NAO CLOCK1 1 ENA1 CLOCK2 ENA2 Table 8 2 ALTMULT ACCUM Megafunction Input Ports accum_sload No Causes the value on the accumulator feedback path to go to into the accumulator zero 0 or to accum_sload_upper_data when concatenated with 0 If the accumulator is adding and the accum_sload port is high then the multiplier output is loaded into the accumulator If the accumulator is subtracting then the opposite negative value of the multiplier output is loaded Beginning from Stratix V devices onwards the accum_sload port causes the value on the accumulator feedback path to go to zero 0 or to accum_sload_upper_data when concaten ated with 1 and loads the multiplier output if the accum_sload port is low aclr0 No The first asynchronous clear input The ac1x0 port is active high acirl No The second asynchronous clear
23. shift right No Specifies dynamically controlled port shift right or left in shift mode Values are 0 and 1 A value of 0 specifies a shift to the left a value of 1 specifies a shift to the right Table 9 4 ALTMULT ADD Megafunction Input Ports Arria V Cyclone V and Stratix V Devices Only datac Yes Data input to the multiplier Input port NUMBER OF MULTIPLIERS WIDTH C 1 0 wide coefsel0 No Coefficient input port 0 3 to the first multiplier coefsell No Coefficient input port 0 3 to the second multiplier coefsel2 No Coefficient input port 0 3 to the third multiplier coefsel3 No Coefficient input port 0 3 to the fourth multiplier Table 9 5 ALTMULT ADD Megafunction Output Ports result Yes Multiplier output port Output port WIDTH RESULT 1 0 wide overflow No Overflow flag If output saturation is enabled overflow flag is set ALTMULT ADD Multiply Adder LJ Send Feedback Altera Corporation UG 01063 9 14 ALTMULT_ADD Parameters 2014 12 19 scanouta No Output of scan chain A Output port WIDTH A 1 0 wide When designing with Stratix III devices port cannot be selected when scaninb is in use Do not use scanina and scaninb simultaneously scanoutb No Output of scan chain B Output port WIDTH_B 1 0 wide When designing with Stratix III devices port cannot be selected when scanina is in use Do not us
24. E m signal of the register that follows the corresponding multiplier Values are NONE ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding MULTIPLIER REGISTER is used the default value is ACLR3 Altera Corporation ALTMULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 ALTMULT_ADD Parameters 9 2 red MUTIPLIER1_DIRECTION String Specifies whether the second multiplier adds or subtracts its value from the sum Values are ADD and sus If the addnsub1 port is used this parameter is ignored If omitted the default value is ADD MUTIPLIER3 DIRECTION String No Specifies whether the fourth and all subsequent odd numbered multipliers add or subtract their results from the total Values are ADD and sus If the addnsub3 port is used this parameter is ignored If omitted the default value is ADD ACCUM DIRECTION String Specifies whether to use the accumulator and whether the accumulator adds or subtracts its value from the sum Values are ADD and sus If omitted the default value is app OUTPUT REGISTER String Specifies the clock signal for the second adder register Values are UNREGISTERED CLOCKO CLOCK cLock2 and cLock3 If omitted the default value is CLOCKO OUTPUT_ACLR String Specifies the asynchronous clear signal for the second adder register Values are NONE ACLRO
25. IP core in simulation and compilation in the Quartus II software using the OpenCore evaluation feature Some Altera IP cores such as MegaCore functions require that you purchase a separate license for production use You can use the OpenCore Plus feature to evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and performance After you purchase a license visit the Self Service Licensing Center to obtain a license number for any Altera product Figure 1 1 IP Core Installation Path C acds Sm quartus Contains the Quartus II software ip Contains the Altera IP Library and third party IP cores E altera Contains the Altera IP Library source code IP core name gt Contains the IP core source files Note The default IP installation directory on Windows is drive Valtera version number on Linux it is home directory gt altera version number Related Information e Altera Licensing Site e Altera Software Installation and Licensing Manual Customizing and Generating IP Cores You can customize IP cores to support a wide variety of applications The Quartus II IP Catalog and parameter editor allow you to quickly select and configure IP core ports features and output files Altera Corporation Integer Arithmetic Megafunctions C Send Feedback UG 01063 2014 12 19 IP Catalog and Parameter
26. and Cyclone II handbooks on the Literature and Technical Documentation page The following table provides resource utilization and performance information for the LPM MULT megafunction Table 4 1 LPM MULT Resource Utilization and Performance Logic Usage Te TV fe ELG Output Adaptive Dedicated Adaptive Device family width Ens Look Up Logic 18 bit DSP fmax MHz Table Register ALUT 5781 Stratix III 8x8 0 0 0 0 1 16 x 16 0 0 0 0 2 N A 32 x 32 0 0 0 0 4 16 x 16 3 0 0 0 2 645 32x32 3 0 0 0 4 454 64 x 64 3 92 128 82 16 191 Verilog HDL Prototype The following Verilog HDL prototype is located in the Verilog Design File v Ipm v in the Quartus II installation directory eda Wynthesis directory module lpm mult result dataa datab sum clock clken aclr parameter lpm type lpm mult parameter lpm widtha 1 parameter lpm widthb 1 parameter lpm widths 1 parameter lpm widthp 1 parameter lpm representation UNSIGNED parameter lpm pipeline 0 parameter lpm hint UNUSED input clock input clken input aclr input 1pm widtha 1 0 dataa input 1pm widthb 1 0 datab 9 The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column Altera Corporation LPM MULT Multip
27. ccsccascsssecssecssavssverncvsesbevssnesedovsseetedecuvesvabevvies 12 1 HO ALU 12 1 Resource Utilization and Perlormalte oues nabo Ret do ab ax Rea Re ud RR 12 1 Verilog HDL Proto igo EN 12 2 VHDL Component Declaration oie oet eae X i es e e tees o e p Res UMEN etas 12 2 VHDL LIBRARY USE Declaration eer ertet ete bnenthee E ese e NER E 12 3 POTUS 12 3 Parameters esceibeloene ERU TIBe I ER HN ER RUNRWE 12 4 Dese Example SbuftAGCumiulat OE uoo ueeetreceir adita ertt tle bal o toad codice teu inpia d Fourier 12 4 Understanding the Simulation Results tepido da risa oscieprudi dax beue iip 12 5 Document Revision HISDOELV i eos ee epp ra us eee FIR TH E eee o pU eap UE C o eK FER EFI RP EEEP 13 1 Altera Corporation Integer Arithmetic Megafunctions 1 2014 12 19 UG 01063 GX subscribe Send Feedback You can use Altera integer megafunction IP cores to perform mathematical operations in your design These functions offer more efficient logic synthesis and device implementation than coding your own functions You can customize the IP cores to accommodate your design requirements Altera integer arithmetic megafunctions are divided into the following two categories e Library of parameterized modules LPM IP cores e Altera specific ALT IP cores The following table lists the integer arithmetic IP cores Tabl
28. imag Yes Imaginary input value for the data A port of the complex multiplier The size of the input port depends on the wipTH A parameter value dataa real Yes Real input value for the data A port of the complex multiplier The size of the input port depends on the wIDTH_A parameter value datab imag Yes Imaginary input value for the data B port of the complex multiplier The size of the input port depends on the wipTH 8 parameter value datab real Yes Real input value for the data B port of the complex multiplier The size of the input port depends on the wIDTH_B parameter value Active high clock enable for the clock port of the complex multiplier Table 10 3 ALTMULT COMPLEX IP Core Output Ports result imag Yes Imaginary output value of the multiplier The size of the output port depends on the WIDTH_RESULT parameter value result reel Yes Real output value of the multiplier The size of the output port depends on the WIDTH_RESULT parameter value ALTMULT_COMPLEX Parameters The following table lists the parameters for the ALTMULT_COMPLEX megafunction Altera Corporation ALTMULT_COMPLEX Complex Multiplier C Send Feedback UG 01063 2014 12 19 Table 10 4 ALTMULT_COMPLEX Megafunction Parameters ALTMULT_COMPLEX Parameters 10 7 IMPLEMENTATION_STYLE String Specifies the representation algorithm and the number of bits per channe
29. in value of 35 and a coefficient of 3 at 350 ns The valid result 105 of the computation is displayed at 470 ns Note Altera recommends that you do not assert both the sload_coeff and sload data signals at the same time to prevent the programming and computation processes from occurring simultane ously ALTMEMMULT Memory based Constant Coefficient Multiplier C Send Feedback ALTMULT_ACCUM Multiply Accumulate 2014 12 19 UG 01063 GX subscribe C Send Feedback The ALTMULT ACCUM megafunction allows you to implement a multiplier adder The following figure shows the ports for the ALTMULT ACCUM megafunction Figure 8 1 ALTMULT ACCUM Ports ALTMULT ACCUM dataa scanina scanouta sourcea signa datab scaninb scanoutb sourceb ji signb result j datac overflow E coefsel accum_sload accum_sload_upper_data addnsub mult_round mult_saturation clock0 ena0 clock1 enal clock2 ena2 clock3 ena3 mult_is_saturated accum is saturated O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants pe
30. inputs of the second multiplier The number of coefficient bits must be set similar to the value of WIDTH_COEF COEF2_ Integer No Specifies the coefficient value 0 7 for the inputs of the third multiplier The number of coefficient bits must be set similar to the value of WIDTH_COEF COEF3 Integer No Specifies the coefficient value 0 7 for the inputs of the fourth multiplier The number of coefficient bits must be set similar to the value of WIDTH_COEF DOUBLE_ACCUMULATOR String No Enables the double accumulator register Values are ves and no This parameter is only available for family Arria V INPUT A 0 3 LATENCY CLOCK String No Specifies the clock signal for the pipeline register on the corresponding dataa port Values are UNREGISTERED CLOCK0 CLOCK1 and cLock2 If omitted the default value is UNREGISTERED INPUT A 0 3 LATENCY ACLR String No Specifies the asynchronous clear signal for the pipeline register on the corresponding dataa port Values are NONE ACLRO ACLR1 If omitted the default value is NoNE ALTERA MULT ADD Multiply Adder Altera Corporation C Send Feedback 6 18 ALTERA_MULT_ADD Parameters UG 01063 2014 12 19 INE UBS 3 LATENCY_CLOCK String Specifies the clock signal for the ni register on the corresponding datab port Values are UNREGISTERED CLOCK0 CLOCK
31. is applied in a transmission application data read from the source are encoded before being sent to the receiver The output code word from the encoder consists of the raw data appended with the number of parity bits The exact number of parity bits appended depends on the number of bits in the input data The generated code word is then transmitted to the destination The receiver receives the code word and decodes it Information obtained by the decoder determines whether an error is detected The decoder detects single bit and double bit errors but can only fix single bit errors in the corrupted data This type of ECC is called a single error correction double error detection SECDED Altera provides two megafunctions the ALTECC ENCODER and ALTECC_DECODER to implement the ECC functionality The data input to the ALTECC ENCODER megafunction is encoded to generate a code word that is a combination of the data input and the generated parity bits The generated code word is transmitted to the ALTECC_DECODER megafunction for decoding just before reaching its destination block The ALTECC_DECODER megafunction generates a syndrome vector to determine if there is any error in the received code word It fixes the data only if the single bit error is from the data bits No signal is flagged if the single bit error is from the parity bits The megafunction also has flag signals to show the status of the data received and the action taken by the ALTECC_DEC
32. red TNEUTER EGIST ER Al String Specifies the clock port for the dataa operand of the second multiplier Values are uNREGIS TERED CLOCKO CLOCK1 CLOCK2 and cLock3 If omitted the default value is cLocko For Stratix III devices the values for INPUT_REGISTER_A 1 3 must be set similar to the value of INPUT_REGISTER_AO INPUT_RE GISTE R_A2 String No Specifies the clock port for the dataa operand of the third multiplier Values are UNREGIS TERED CLOCKO CLOCK1 CLOCK2 and cLock3 If omitted the default value is cLocKo For Stratix III devices the values for INPUT REGISTER A 1 3 must be set similar to the value of INPUT REGISTER AQ INPUT R EGIST ER A3 String No Specifies the clock port for the dataa operand of the fourth and corresponding multiplier Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is cLocxo For Stratix III devices the values for INPUT_ REGISTER A 1 3 must be set similar to the value of INPUT_ REGISTER AO INPUT RE GISTE R BO String No Specifies the clock port for the datab operand of the first multiplier Values are UNREGIS TERED CLOCK0 CLOCK1 CLOCK2 and cLock3 If omitted the default value is cLocko For Stratix III devic
33. the default value is cLocko CHAINOUT ROUND PIPELINE ACLR String Specifies the asynchronous clear source for the second register on the chainout round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and CHAINOUT ROUND PIPELINE REGISTER is used the default value is ACLR3 CHAINOUT ROUND OUTPUT REGISTER String No Specifies the clock source for the third register on the chainout_ round input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocko Altera Corporation ALTMULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Parameter Name CHAINOUT_ROUND_OUTPUT_ACLR Type String Requi red No ALTMULT_ADD Parameters 9 29 Description Specifies the asynchronous clear source for the third register on the chainout_round input Values are ACLRO ACLR1 ACLR2 and AcLR3 If omitted and CHAINOUT ROUND OUTPUT_ REGISTER is used the default value is ACLR3 CHAINOUT SATURATION String No Enables saturation handling at the chainout stage Values are YES NO and VARIABLE A value of YES or No specifies saturation handling setting permanently to on or off A value of VARIABLE allows dynamically controlled saturation handling If omitted the default value is uo CHAINOUT SATURATE REGISTE
34. 01063 GX subscribe _ Send Feedback The LPM_MULT megafunction implements a multiplier to multiply two input data values to produce a product as an output The following figure shows the ports for the LPM_MULT megafunction Figure 4 1 LPM Mult Ports Features The LPM MULT megafunction offers the following features e Generates a multiplier that multiplies two input data values e Supports data width of 1 256 bits e Supports signed and unsigned data representation format e Supports area or speed optimization e Supports pipelining with configurable output latency e Provides an option for implementation in dedicated digital signal processing DSP block circuitry or logic elements LEs Note When building multipliers larger than the natively supported size there may will be a perform ance impact resulting from the cascading of the DSP blocks e Supports optional asynchronous clear and clock enable input ports Resource Utilization and Performance O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to cur
35. 16 292 64 14 91 8 47 16 291 Verilog HDL Prototype The following Verilog HDL prototype is located in the Verilog Design File v altera_mf v in the lt Quartus II installation directory gt eda synthesis directory module altmult_complex parameter intended_device_family unused parameter implementation_style AUTO parameter pipeline 4 The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column Altera Corporation ALTMULT COMPLEX Complex Multiplier C Send Feedback UG 01063 2014 12 19 VHDL Component Declaration 10 5 parameter representation_a SIGNED parameter representation_b SIGNED parameter width a 1 parameter width b 1 parameter width result 1 parameter lpm type altmult complex parameter lpm hint unused input wire aclr input wire clock input wire complex input wire width a 1 0 dataa imag input wire width a 1 0 dataa real input wire width b 1 0 datab imag input wire width b 1 0 datab real input wire ena output wire width result 1 0 result imag output wire width result 1 0 result real endmodule VHDL Component Declaration The VHDL component declaration is located in the VHDL Design File vhd altera mf components vhd in the Quartus II installation directory gt libraries vhdl altera_
36. ACLR String No Specifies the asynchronous clear signal for the pipeline register on the corresponding accum sload Or sload accum input Values are NONE ACLRO and ACLR1 If omitted the default value is NONE Design Example Implementing a Simple Finite Impulse Response FIR Filter This design example uses the ALTMULT ADD megafunction to implement a simple FIR filter as shown in the following equation This example uses the MegaWizard Plug In Manager in the Quartus II software n 1 y t YA iBG i 0 n represents the number of taps A t represents the sequence of input samples and B i represents the filter coefficients The number of taps n can be any value but this example is of a simple FIR filter with n 4 which is called a 4 tap filter To implement this filter the coefficients of data B is loaded into the B registers in parallel and a shiftin register moves data A 0 to A 1 to A 2 and so on With a 4 tap filter at a given time t the sum of four products is computed This function is implemented using the shift register chain option in the ALTMULT_ADD megafunction With reference to the equation input B represents the coefficients and data A represents the data that is shifted into The A input data is shifted in with the main clock named clocko The B input coefficients is loaded at the rising edge of clock1 with the enable signal held high The following design files can be found in
37. DSP blocks in any of the Stratix Stratix GX and Arria GX device series refer to the DSP Blocks chapter of the respective handbooks on the Literature and Technical Documentation page For more information about the embedded memory blocks in any of the Stratix Stratix GX and Arria GX device series refer to the TriMatrix Embedded Memory Blocks chapter of the respective handbooks on the Literature and Technical Documentation page For more information about embedded multiplier blocks in the Cyclone II and Cyclone III devices refer to the DSP Blocks chapter of the respective handbooks on the Literature and Technical Documentation page For more information about implementing multipliers using DSP and memory blocks in Altera FPGAs refer to AN 306 Implementing Multipliers in FPGA Devices The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column ALTMULT ACCUM Multiply Accumulate Altera Corporation LJ Send Feedback 8 4 Verilog HDL Prototype Verilog HDL Prototype UG 01063 2014 12 19 To view the Verilog HDL prototype for the megafunction refer to the Verilog Design File v altera_mf v in the Quartus Il installation directory gt eda synthesis directory VHDL Component Declaration To view the VHDL component declaration for the megafunction refer to the VHDL Design File vhd
38. Editor 1 3 IP Catalog and Parameter Editor The Quartus II IP Catalog Tools gt IP Catalog and parameter editor help you easily customize and integrate IP cores into your project You can use the IP Catalog and parameter editor to select customize and generate files representing your custom IP variation Note The IP Catalog Tools gt IP Catalog and parameter editor replace the MegaWizard Plug In Manager for IP selection and parameterization beginning in Quartus II software version 14 0 Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores The IP Catalog lists IP cores available for your design Double click any IP core to launch the parameter editor and generate files representing your IP variation The parameter editor prompts you to specify an IP variation name optional ports and output file generation options The parameter editor generates a top level Qsys system file qsys or Quartus II IP file qip representing the IP core in your project You can also parameterize an IP variation without an open project Use the following features to help you quickly locate and select an IP core e Filter IP Catalog to Show IP for active device family or Show IP for all device families e Search to locate any full or partial IP core name in IP Catalog Click Search for Partner IP to access partner IP information on the Altera website e Right click an IP core name in IP Catalog to display details about suppo
39. Enables saturation handling at second adder stage If original design uses a Stratix II device in some cases this parameter can be derived from the Stratix II rounding settings Values are YES NO and VARIABLE A value of YES or NO specifies saturation handling setting permanently to on or off A value of VARIABLE allows dynamically controlled saturation handling If omitted the default value is No OUTPUT_SATURATE_REGISTER String No _ Specifies the clock source for the first register on the output_ saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is UNREGIS TERED OUTPUT_SATURATE_ACLR String No _ Specifies the asynchronous clear source for the first register on the output_saturate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and OUTPUT_ SATURATE REGISTER is used the default value is ACLR3 OUTPUT SATURATE PIPELINE REGISTER String No Specifies the clock source for the second register on the output saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is cLocxo OUTPUT_SATURATE_PIPELINE_ACLR String No _ Specifies the asynchronous clear source for the second register on the output_saturate input Values are ACLRO ACLR1 ACLR2 and acur3 If omitted and OUTPUT SA
40. MegaWizard Plug In Manager in the Quartus II software The following design files can be found in altecc DesignExamplel zip e altecc encode qar archived Quartus II design files e altecc encode ex msim ModelSim Altera files Understanding the Simulation Results The following settings are observed in this example e Theaata input width is set to 8 bits e The output port q has a width of 13 bits e The clock enable clocken signal is enabled e Pipelining is enabled with an output latency of 2 clock cycles Hence the result is seen on the g port two clock cycles after the input data is available The following figure shows the expected simulation results in the ModelSim Altera software ALTECC Error Correction Code Encoder Decoder C Send Feedback Altera Corporation UG 01063 5 10 Understanding the Simulation Results 2014 12 19 Figure 5 4 Design Example 1 Simulation Waveform for the ECC Encoder skecc encode vig vec tstjclock 4 akecc encode vig vec tsticlocken 4 akecc encode vig vec tst data Jakecc encode vig vec tst q Altera Corporation ALTECC Error Correction Code Encoder Decoder C Send Feedback UG 01063 2014 12 19 Understanding the Simulation Results 5 11 The following sequence corresponds with the numbered items in the figure e Data FO is fed to the ECC encoder As pipelining is enabled to have an output latency of 2 clock cycles the result of the encoding operation appe
41. NONE ACLRO and ACLR1 If omitted and the corresponding COEFFSEL REGISTER is used the default value is ACLRO The value must be set similar to the value of INPUT_ ACLR AQ COE FFSE L D ACLR Specifies the asynchronous clear source for the coefficient inputs to the fourth and corresponding multiplier Values are NONE ACLRO and ACLR1 If omitted and the corresponding COEFFSEL REGISTER is used the default value is ACLRO The value must be set similar to the value of INPUT_ ACLR AO ALTMULT ACCUM Multiply Accumulate LJ Send Feedback Altera Corporation 8 18 ALTMULT_ACCUM Parameters UG 01063 2014 12 19 SYSTOLIC_DELAY1 String Specifies the clock source for the systolic register inputs of the first multiplier Values are UNREGISTERED CLOCKO CLOCK1 and cLocKk2 The value must be set similar to the value of ouTPUT_ REGISTER Or setas UNREGIS TERED SYSTOLIC DELAY3 String Specifies the clock source for the systolic register inputs of the third multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOcK2 The value must be set similar to the value of ouTPUT_ REGISTER Or set aS UNREGIS TERED SYSTOLIC ACLR1 String No Specifies the asynchronous clear source for the systolic register inputs of the first multiplier Values ar
42. Optimization Technique option is used instead If the value of MAXIMIZE SPEED is 6 Or higher the Compiler optimizes the LPM_DIVIDE megafunctions for higher speed by using carry chains if the value is 5 or less the compiler implements the design without carry chains LPM_PIPELINE Integer No Specifies the number of clock cycles of latency associated with the quotient and remain outputs A value of zero 0 indicates that no latency exists and that a purely combinational function is instantiated If omitted the default value is 0 non pipelined You cannot specify a value for the LPM_PIPELINE parameter that is higher than LPM_WIDTHN LPM_DIVIDE Divider CJ Send Feedback Altera Corporation 3 6 Parameters UG 01063 2014 12 19 NTENDED_DEVICE_FAMILY String This parameter is used for modeling and behavioral simulation purposes Create the LPM_DIVIDE megafunc tion with the MegaWizard Plug In Manager to calculate the value for this parameter SKIP_BITS Integer No Allows for more efficient fractional bit division to optimize logic on the leading bits by providing the number of leading GND to the LPM_DIVIDE megafunction Specify the number of leading GND on the quotient output to this parameter Altera Corporation LPM_DIVIDE Divider C Send Feedback LPM_MULT Multiplier 2014 12 19 UG
43. Send Feedback UG 01063 9 4 Pre adder 2014 12 19 Pre adder With pre adder additions or subtractions are done prior to feeding the multiplier There are five pre adder modes e Simple mode e Coefficient mode e Input mode e Square mode e Constant mode Note When pre adder is used pre adder coefficient input square mode all data inputs to the multiplier must have the same clock setting Pre adder Simple Mode In this mode both operands derive from the input ports and pre adder is not used or bypassed This is the default mode Figure 9 2 Pre adder Simple Mode a0 MultO result b0 Pre adder Coefficient Mode In this mode one multiplier operand derives from the pre adder and the other operand derives from the internal coefficient storage The coefficient storage allows up to 8 preset constants The coefficient selection signals are coe se1 0 3 The following settings are applied in this mode e The width of the dataa input wIpDTH_A must be less than or equals to 25 bits e The width of the datab input wIDTH_B must be less than or equals to 25 bits e The width of the coefficient input must be less than or equals to 27 bits This mode is expressed in the following equation y a b x coef The following shows the pre adder coefficient mode of a multiplier Altera Corporation ALTMULT_ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Figure 9 3 Pre adder Coef
44. altmult_add_DesignExample zip fir fourtap qar archived Quartus II design files ALTERA MULT ADD Multiply Adder Altera Corporation C Send Feedback UG 01063 6 20 Understanding the Simulation Results 2014 12 19 altmult_add_ex_msim ModelSim Altera files Understanding the Simulation Results The following settings are observed in this example e The widths of the data inputs are all set to 16 bits e The width of the output port result is set to 34 bits e The input registers are all operating on the same clock The following figure shows the expected simulation results in the ModelSim Altera software Figure 6 13 ALTMULT ADD Simulation Results jfi fourtap vlg vec tst clocko 4 jfir fourtap vlg vec tst dataa 0 fr fourtap vlg vec tst datab 0 4 jfi fourtap vlg vec tstdatab 1 Ifir Fourtap vlg vec tst datab 2 A jfir fourtap vlg vec tst datab 3 fir Fourtap vlg vec tstlena 4 jfir Fourtap vlg vec tst signa fir Fourtap vlg vec tst signb Jfir Fourtap vg vec tst result LE N N uae Oooo 2000 ns Cursor 1 200ns Altera Corporation ALTERA_MULT_ADD Multiply Adder C Send Feedback ALTMEMMULT Memory based Constant Coefficient Multiplier 2014 12 19 UG 01063 GX subscribe _ Send Feedback The ALTMEMMULT megafunction is used to create memory based multipliers using the on chip memory blocks found in Altera FPGAs with M512 M4K M9K and MLAB memory blocks This megafunction is useful
45. are done prior to feeding the multiplier There are five pre adder modes Simple mode Coefficient mode Input mode Square mode Constant mode Note When pre adder is used pre adder coefficient input square mode all data inputs to the multiplier must have the same clock setting Pre adder Simple Mode In this mode both operands derive from the input ports and pre adder is not used or bypassed This is the default mode Figure 6 2 Pre adder Simple Mode MultO a0 result bO Pre adder Coefficient Mode In this mode one multiplier operand derives from the pre adder and the other operand derives from the internal coefficient storage The coefficient storage allows up to 8 preset constants The coefficient selection signals are coe se1 0 3 The following settings are applied in this mode The width of the dataa input wIDTH_A must be less than or equals to 25 bits The width of the datab input wIDTH_B must be less than or equals to 25 bits The width of the coefficient input must be less than or equals to 27 bits This mode is expressed in the following equation y a b x coef ALTERA_MULT_ADD Multiply Adder Altera Corporation C Send Feedback UG 01063 6 4 Pre adder Input Mode 2014 12 19 The following shows the pre adder coefficient mode of a multiplier Figure 6 3 Pre adder Coefficient Mode Preadder a0 MultO H I result bO
46. complex canonical vig vec tstidataa imag complex canonical vig vec tstidatab real ME Eo ALTMULT COMPLEX Complex Multiplier LJ Send Feedback Altera Corporation ALTSQRT Integer Square Root 1 2014 12 19 UG 01063 GX subscribe Send Feedback The ALTSQRT megafunction implements a square root function that calculates the square root and remainder of an input The following figure shows the ports for the ALTSORT megafunction Figure 11 1 ALTSORT Ports radical clk remainder ena aclr Features The ALTSQRT megafunction offers the following features e Calculates the square root and the remainder of an input e Supports data width of 1 256 bits e Supports pipelining with configurable output latency e Supports optional asynchronous clear and clock enable input ports Resource Utilization and Performance The following table provides resource utilization and performance information for the ALTSQRT megafunction O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specif
47. countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 12 2 Verilog HDL Prototype Table 12 1 PARALLEL_ADD Resource Utilization and Performance Logic Usage UG 01063 2014 12 19 Device family evn js gem Ope En fmax MHz 9 Table ALUT Register Module DLR ALM 8 1 40 0 21 793 Stratix III 32 5 142 0 102 378 64 10 283 0 189 280 8 1 40 0 21 854 Stratix IV 32 5 142 0 103 472 64 10 283 0 199 346 Verilog HDL Prototype The following Verilog HDL prototype is located in the Verilog Design File v altera_mf v in the lt Quartus II installation directory gt eda synthesis directory module parallel_add
48. function addnsub3 Controls the functionality of the first adder If the addnsub3 port is high the first adder performs an add function If the addnsub3 port is low the adder performs a subtract function coefselO Coefficient input port 0 3 to the first multiplier coefsell Coefficient input port 0 3 to the second multiplier coefsel2 coefsel3 Coefficient input port 0 3 to the third multiplier Coefficient input port 0 3 to the fourth multiplier ALTERA MULT ADD Multiply Adder C Send Feedback Altera Corporation 6 12 ALTERA_MULT_ADD Parameters Table 6 2 ALTERA_MULT_ADD MegaFunction Output Ports UG 01063 2014 12 19 result Yes Multiplier output port Output port WIDTH RESULT 1 0 wide scanouta No Output of scan chain A Output port WIDTH_A 1 0 wide ALTERA MULT ADD Parameters The following table lists the parameters for the ALTERA MULT ADD megafunction Table 6 3 ALTMULT ADD Megafunction Parameters BER OF MULTIPLIE Integer Y Number of multipliers to be added together Values are 1 up to 4 WIDTH A Integer Yes Width of the dataa port WIDTH B Width of the datab port WIDTH RESULT Integer Yes Width of the result port INPUT REGISTE INPUT REGISTE R A 0 3 13 NOR String String No No Specifies the clock port for the aataa
49. in a VHDL Design File vhd you must use the LPM_HINT parameter to specify an Altera specific parameter For example LPM_ HINT CHAIN SIZE 8 ONE INPUT IS CONSTANT YES The default value is uNUSED LPM TYPE String No Identifies the library of parameterized modules LPM entity name in VHDL design files MAX CLOCK CYCLES PER RE SULT Integer No Specifies the number of clock cycles per result NUMBER OF COEFFICIENTS Integer No Specifies the number of coefficients that are stored in the lookup table RAM BLOCK TYPE String No Specifies the ram block type Values are AUTO SMALL MEDIUM M512 and M4K If omitted the default value is AUTO Design Example 8 x 8 Multiplier This design example uses the ALTMEMMULT megafunction to generate a basic multiplier using RAM blocks to determine the 16 bit product of two unsigned 8 bit numbers This example uses the MegaWizard Plug In Manager in the Quartus II software The following design files can be found in altmemmult DesignExample zip memmult ex qar archived Quartus II design files altmemmult ex msim ModelSim Altera files ALTMEMMULT Memory based Constant Coefficient Multiplier LJ Send Feedback Altera Corporation UG 01063 7 6 Understanding the Simulation Results 2014 12 19 Understanding the Simulation Results The following settings are obs
50. meti ind puru idiot dp e its 5 12 ALTERA MULT ADD Multiply Adder eene 6 1 POALUL c 6 2 reu M 6 3 Systolic Delay Reglstetiauiacss e neci tiis FIOI EMERGERE 6 6 Pr l ad Ic M AES Eikan 6 9 Double Accuradilatofs qose eestisse b esr dris d x as excelsi Quid dr toc EREEREER 6 9 Verilog HDL uin e 6 10 VHDL Component Declaration etes irent persi tene t Urna nias tup dte vov to via a be be eeiam ines 6 10 VHDL LIBRARY USE Declaratioti 5 oreet n e n en nine de n EE eris ein 6 10 POTS E M 6 10 ALTERA MULT ADD Paramietets iei tera tre rte t t p b ka o C eee Eae 6 12 Design Example Implementing a Simple Finite Impulse Response FIR Filter 6 19 Understanding the Simulation Resultss isisssstsnssssssdecsssssasssscnsnsansssinnssnssnunssntsssssuisvsntiersvansatesacassvssseatacets 6 20 ALTMEMMULT Memory based Constant Coefficient Multiplier 7 1 uu 7 1 Resource Utilization dnd PettorbuidtiCe ues ses Gries eia dtd abeseq taceat pa pe ri t irre ne ein 7 2 Verilog HDL Prototype e 7 2 VHDL Component DeclaratOniy iccasiaciexsnniosmninrnicuiietnmomnmciqummabincdnnisansmarunsenents 7 3 POLS
51. omitted the default value is CLOCKO OUTPUT ACLR String No Specifies the asynchronous clear signal for the registers on the outputs Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default value is ACLR3 OUTPUT REG String No Specifies the clock signal for the registers on the outputs Values are CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is CLOCKO PORT ADDNSUB String No Specifies the usage of the addnsub input port Values are PORT USED PORT_ UNUSED and PORT_ CONNECTIVITY port usage is determined by checking the port connectivity If omitted the default value is PoRT_ CONNECTIVITY PORT_SIGNA String No Specifies the usage of the signa input port Values are PORT_USED PORT_UNUSED and PORT_CONNECTIVITY If omitted the default value is PORT_CONNECTIVITY Beginning from Stratix V devices onwards the PORT_ CONNECTIVITY parameter is not supported The default value is PORT_UNUSED Altera Corporation ALTMULT_ACCUM Multiply Accumulate C Send Feedback UG 01063 2014 12 19 ALTMULT_ACCUM Parameters 8 11 PORT_SIGNB String Specifies the usage of the signb input port Values are PORT_USED PORT_UNUSED and PORT_CONNECTIVITY If omitted the default value is PORT_CONNECTIVITY Beginning from Stratix V devices onwards the PoRT_ CONNECTIVITY parameter is not supported The default value i
52. std logic 0 clken in std logic 1 result out std logic vector widthr 1 downto 0 end component VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY altera mf USI Ports E altera mf altera mf components all The following tables list the input and output ports ofthe PARALLEL ADD megafunction Table 12 2 PARALLEL ADD Megafunction Input Ports data Yes Data input to the parallel adder Input port SIZE 1 DOWNTO 0 WIDTH 1 DOWNTO 0 wide clock No Clock input to the parallel adder This port is required if the PIPELINE parameter has a value of greater than 0 clken No Clock enable to the parallel adder If omitted the default value is 1 aclr No Active high asynchronous clear input to the parallel adder Table 12 3 PARALLEL ADD Megafunction Output Ports result Yes PARALLEL ADD Parallel Adder LJ Send Feedback Adder output port The size of the output port depends on the wipTHR parameter value Altera Corporation 12 4 Parameters Parameters The following table lists the parameters for the PARALLEL_ADD megafunction Table 12 4 PARALLEL_ADD Megafunction Parameters UG 01063 2014 12 19 WIDTH Integer Specifies the width of the dat a input port SIZE Integer Yes Specifies the number of inputs to add WIDTHR Integer Specifies the wid
53. table lists the parameters for the ALTMEMMULT megafunction Table 7 4 ALTMEMMULT Megafunction Parameters Integer Specifies the width of the aata in port WIDTH_C Integer Yes Specifies the width of the coeff_in port WIDTH_R Integer Yes Specifies the width of the result port WIDTH_S Integer No Specifies the width of the se1 port COEFFICIENTO Integer Yes Specifies value of the first fixed coefficient TOTAL LATENCY Integer Yes Specifies the total number of clock cycles from the start of a multiplica tion to the time the result is available at the output Altera Corporation ALTMEMMULT Memory based Constant Coefficient Multiplier C Send Feedback UG 01063 2014 12 19 Design Example 8 x 8 Multiplier 7 5 DATA_REPRESENTATION String Specifies whether the coeff_in input port and the pre loaded coefficients are signed or unsigned COEFF_REPRESENTATION String No Specifies whether the coeff_in input port and the pre loaded coefficients are signed or unsigned INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes Create the ALTMEMMULT megafunction with the MegaWizard Plug In Manager to calculate the value for this parameter LPM_HINT String No When you instantiate a library of parameterized modules LPM function
54. the VHDL Design File vhd altera_mf_components vhd in the lt Quartus II installation directory gt libraries vhdl altera_mf directory component altmemmult generic coeff_representation string SIGNED coefficientO0 string UNUSED data_representation string SIGNED intended_device_family string unused max clock cycles per result natural 1 number of coefficients natural 1 ram block type string AUTO total latency natural width c natural width d natural width r natural width s natural 1 lpm hint string UNUSED lpm type string altmemmult port clock in std logic coeff in in std logic vector width c 1 downto 0 data in in std logic vector width d 1 downto 0 load done out std logic result out std logic vector width r 1 downto 0 result valid out std logic Sclr in std logic 0 sel in std logic vector width s 1 downto 0 sload coeff in std logic 0 sload data in std logic 0 end component others gt 0 others gt 0 Ports The following tables list the input and output ports for the ALTMEMMULT megafunction Table 7 2 ALTMEMMULT Megafunction Input Ports clock Yes Clock input to the multiplier coeff_in No Coefficient input port for the multiplier The size of the input port depends on the wIDTH_c parameter value data in Yes Data input port to the multiplier The size of the input port de
55. the data source of the third multiplier Values are DATAB and scans If this parameter is set to DATAB then the adder uses the values from the datab port If this parameter is set to SCANB then the adder uses values from the scan chain If omitted the default value is patas For Stratix II devices a value of VARIABLE is available for the adder to perform rounding and saturation on the data source before feeding the result to the multiplier For Stratix III in sum 2 sum of two mode a value of LOOPBACK is available INPUTSSOUREG E B3 String No Specifies the data source of the fourth and corresponding multiplier Values are DATAB and scans If this parameter is set to DATAB then the adder uses the values from the datab port If this parameter is set to SCANB then the adder uses values from the scan chain If omitted the default value is patas For Stratix II devices a value of VARIABLE is available for the adder to perform rounding and saturation on the data source before feeding the result to the multiplier For Stratix III devices in sum 2 sum of two mode a value of LOOPBACK is available Altera Corporation ALTMULT_ADD Multiply Adder C Send Feedback UG 01063 Parameter Name Type Requi Description red ENTATION_A String Specifies the numerical represen tation of the multiplier input A Values are UNSIGNED SIGNED and VARIABLE When this parameter is set
56. word has an even number of 1 s For example if the data width is 4 bits 4 parity bits are appended to the data to become a code word with a total of 8 bits If 7 bits from the LSB of the 8 bit code word have an odd number of 1 s the 8th bit MSB of the code word is 1 making the total number of 1 s in the code word even The following figure shows the generated code word and the arrangement of the parity bits and data bits in an 8 bit data input Figure 5 3 Parity Bits and Data Bits Arrangement in an 8 Bit Generated Code Word MSB LSB 8 1 The ALTECC_ENCODER megafunction accepts only input widths of 2 to 64 bits at one time Input widths of 12 bits 29 bits and 64 bits which are ideally suited to Altera devices generate outputs of 18 bits 36 bits and 72 bits respectively The bit selection limitation is controlled by the MegaWizard Plug In Manager Resource Utilization and Performance The following tables provide resource utilization and performance information for the ALTECC megafunction ALTECC Error Correction Code Encoder Decoder Altera Corporation J send Feedback 5 4 Resource Utilization and Performance UG 01063 2014 12 19 Table 5 2 ALTECC Resource Utilization and Performance for Stratix Ill Devices Logic Usage i l Output Adaptive Dedicated Adaptive Configuration latency Look Up Logic Logic Table Register Module ALUT 3 8 ALM 12 0 8 0 4 1161 29
57. 0 endmodule remainder VHDL Component Declaration The VHDL component declaration is located in the VHDL Design File vhd altera mf components vhd in the Quartus II installation directory gt libraries vhdl altera_mf directory component altsqrt generic lpm hint string UNUSED lpm type string altsqrt pipeline natural 0 q port width natural 1 r port width natural 1 width natural port aclr in std logic 0 9 The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column Altera Corporation ALTSQRT Integer Square Root C Send Feedback UG 01063 2014 12 19 VHDL LIBRARY_USE Declaration 11 3 clk in std logic 1 ena in std logic 1 q out std logic vector Q PORT WIDTH 1 downto 0 radical in std logic vector WIDTH 1 downto 0 remainder out std logic vector R PORT WIDTH 1 downto 0 end component VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY altera mf USE altera mf altera mf components all Ports The following tables list the input and output ports for the ALTSQRT megafunction Table 11 1 ALTSQRT Megafunction Input Ports radical Yes Data input port The size of the input port depends on the wipTH parameter value ena N
58. 0 21 0 13 1076 32 0 19 0 12 979 ALTECC_ 64 0 40 0 a Bs ENCODER 12 2 8 30 19 1188 29 2 20 65 36 1021 32 2 19 71 40 1013 64 p 39 136 79 926 12 0 8 0 4 1161 29 0 21 0 13 1076 32 0 19 0 12 979 ALTECC_ 64 0 40 0 p 758 DECODER 12 2 8 30 19 1188 29 D 20 65 36 1021 32 2 19 71 40 1013 64 2 39 136 79 926 3 The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column Altera Corporation ALTECC Error Correction Code Encoder Decoder C Send Feedback UG 01063 2014 12 19 Verilog HDL Prototype ALTECC_ENCODER 5 5 Logic Usage Configuration mee Sots epp 1 Adaptive Table Register A d ALUT DLR 12 0 8 0 4 1128 29 0 21 0 13 1072 32 0 19 0 12 1054 ALTECC 64 0 40 0 p 901 ENCODER 12 2 8 30 19 1104 29 2 20 65 38 1082 32 2 19 71 42 1061 64 D 39 136 78 905 12 0 8 0 4 1128 29 0 21 0 13 1072 32 0 19 0 12 1054 ALTECC 64 0 40 0 27 901 DECODER 12 2 8 30 19 1104 29 2 20 65 38 1082 32 2 19 71 42 1061 64 2 39 136 78 905 Verilog HDL Prototype ALTECC ENCODER The following Verilog HDL prototype is located in the Verilog Design File v Ipm v in the Quartus II installation directory Yeda synthesis directory module altecc encoder parameter intended device family unused parameter lpm pipeli
59. 1 and cLock2 If omitted the default value is UNREGISTERED INPUT B 0 3 LATENCY ACLR String Specifies the asynchronous clear signal for the pipeline register on the corresponding datab port Values are NONE ACLRO ACLR1 If omitted the default value is NoNE INTENTI CLO 3 LATENCY CELOCK String No Specifies the clock signal for the pipeline register on the corresponding datac port Values are UNREGISTERED CLOCK0 CLOCK1 and cLock2 If omitted the default value is UNREGISTERED INPUT C 0 3 LATENCY ACLR COREES EL 0 3 LATENCY CLOCK String String No Specifies the asynchronous clear signal for the pipeline register on the corresponding datac port Values are NONE ACLRO ACLR1 If omitted the default value is NoNE Specifies the clock signal for the pipeline register on the corresponding coefficient inputs Values are UNREGISTERED CLOCKO CLOCK1 and CLOCK2 COEFFSE L 0 3 LATENCY ACLR String Specifies the asynchronous clear signal for the pipeline register on the corresponding coefficient inputs Values are NONE ACLRO and ACLR1 If omitted the default value is NONE SIGNE iD gi ENCY CLOCK String No Parameter A B Specifies the clock signal for the pipeline register on the corresponding
60. 1063 1 12 Simulating Altera IP Cores in other EDA Tools 2014 12 19 Simulating Altera IP Cores in other EDA Tools The Quartus II software supports RTL and gate level design simulation of Altera IP cores in supported EDA simulators Simulation involves setting up your simulator working environment compiling simulation model libraries and running your simulation You can use the functional simulation model and the testbench or example design generated with your IP core for simulation The functional simulation model and testbench files are generated in a project subdirectory This directory may also include scripts to compile and run the testbench For a complete list of models or libraries required to simulate your IP core refer to the scripts generated with the testbench You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts NativeLink launches your preferred simulator from within the Quartus II software Figure 1 8 Simulation in Quartus Il Design Flow Design Entry HDL Qsys DSP Builder Altera Simulation Models NENNEN Gate Level Simulation Post synthesis functional Post synthesis simulation netlist Quartus II Design Flow Analysis amp Synthesis functional simulation EDA Fitter T i Netlist Post fit functional lace and route i i i i p Writer simulation netlist Post fit functional simulation
61. 1063 GX subscribe C Send Feedback The PARALLEL ADD megafunction performs add or subtract operations on a selected number of inputs to produce a single sum result You can add or subtract more than two operands and automatically shift the input operands upon entering the function The method of shifting input operands is useful for serial FIR filter structures requiring a shift and accumulate of the partial products The following figure shows the ports for the PARALLEL ADD megafunction Figure 12 1 PARALLEL ADD Ports PARALLEL ADD data clock result aclr Feature The PARALLEL_ADD megafunction offers the following features e Performs add or subtract operations on a number of inputs to produce a single sum result e Supports data width of 8 128 bits e Supports signed and unsigned data representation format e Supports pipelining with configurable output latency e Supports shifting data vectors e Supports addition or subtraction of the most significant input operands e Supports optional asynchronous clear and clock enable ports Resource Utilization and Performance The following table provides resource utilization and performance information for the PARALLEL ADD megafunction O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other
62. 14 12 19 This mode is expressed in the following equation y a0 b0 2 a1 b1 The following shows the pre adder square mode of two multipliers Figure 9 5 Pre adder Square Mode a0 MultO Lu bO result al Multl bl G9 Pre adder Constant Mode In this mode one multiplier operand derives from the input port and the other operand derives from the internal coefficient storage The coefficient storage allows up to 8 preset constants The coefficient selection signals are coe se1 0 3 The following settings are applied in this mode e The width of the dataa input wIDTH_A must be less than or equals to 27 bits e The width of the coefficient input must be less than or equals to 27 bits e The datab port must be disconnected This mode is expressed in the following equation y a0x coef The following figure shows the pre adder constant mode of a multiplier Figure 9 6 Pre adder Constant Mode MultO a0 x result coefsel0 coef Altera Corporation ALTMULT_ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Systolic Delay Register 9 7 Systolic Delay Register In a systolic architecture the input data is fed into a cascade of registers acting as a data buffer Each register delivers an input sample to a multiplier where it is multiplied by the respectiv
63. 20 where N LOADCONST_VALUE When the LOADCONST_VALUE is set to 64 the constant value is equal to 0 This function can be used as biased rounding The following figure shows the pre load constant implementation Figure 9 11 Pre load Constant __ constant Accumulator feedback 25d a0 MultO bO r c result al F Mult gt S bl AS accum sload Refer to the following megafunctions in this user guide for other multiplier implementations e ALTMULT ACCUM Multiply Accumulate e ALTMEMMULT Memory based Constant Coefficient Multiplier e LPM MULT Multiplier Double Accumulator The double accumulator feature adds an additional register in the accumulator feedback path The double accumulator register follows the output register which includes the clock clock enable and aclr The additional accumulator register returns result with a one cycle delay This feature enables you to have two accumulator channels with the same resource count Altera Corporation ALTMULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Resource Utilization and Performance 9 11 The following figure shows the double accumulator implementation Figure 9 12 Double Accumulator Double Accu mulator Register Accumulator feedba ck lt
64. 3L 5L 5L 5 your ip html Contains memory map simulation IP simulation files f lt your_ip gt sip NativeLink simulation integration file f lt your_ip gt v vhd vo vho HDL or IPFS models simulator vendor gt Simulator setup scripts lt simulator_setup_scripts gt synthesis IP synthesis files c lt your_ip gt qip Lists files for synthesis f lt your_ip gt debuginfo Lists files for synthesis f your ip v or vhd Top level IP variation synthesis file testbench Simulation testbench files 1 f testbench hdl files ds simulator vendor Testbench for supported simulators lt simulation_testbench_files gt your ip tb Testbench for supported simulators f your ip tb v or vhd Top level HDL testbench file Notes 1 If supported and enabled for your IP variation 2 f functional simulation models are generated Upgrading IP Cores IP core variants generated with a previous version of the Quartus II software may require upgrading before use in the current version of the Quartus II software Click Project Upgrade IP Components to identify and upgrade IP core variants The Upgrade IP Components dialog box provides instructions when IP upgrade is required optional or unsupported for sp
65. ACLR1 ACLR2 and AcLR3 If omitted the default value is ACLR3 PORTESGEGN String Parameter A B Specifies the corresponding sign input port usage Values are PORT_USED PORT_UNUSED and PORT_ CONNECTIVITY If omitted the default value is PORT_ CONNECTIVITY CHAINOUT_ROUND_TYPE String Specifies the rounding mode at the chainout stage Values are BIASED and UNBIASED A value of BIASED specifies round to nearest integer A value of UNBIASED specifies round to nearest even ALTMULT_ADD Multiply Adder CJ Send Feedback Altera Corporation 9 2 ALTMULT_ADD Parameters UG 01063 2014 12 19 red EXTRA_LATENCY String Specifies the number of clock cycles of latency LPM_HINT String No When you instantiate a library of parameterized modules LPM function in a VHDL Design File vhd you must use the LPM_ HINT parameter to specify an Altera specific parameter For example LPM HINT CHAIN SIZE 8 ONE INPUT IS CONSTANT YES The default value is UNUSED EEMAEY PE String No Identifies the library of parameterized modules LPM entity name in VHDL design files INTENDE D DEVICE FAMILY String No This parameter is used for modeling and behavioral simulation purposes Create the ALTMULT ADD megafunction with the MegaWizard Plug in Manager to calculate the value
66. ADD PREADDE R DIRE CTION 2 String Specifies whether the pre adder of the third multiplier adds or subtracts its value from the sum Values are ADD and sus If omitted the default value is app ALTMULT ACCUM Multiply Accumulate J send Feedback Altera Corporation 8 16 ALTMULT_ACCUM Parameters UG 01063 2014 12 19 READD ER DIRE CTION 3 String Specifies whether the pre adder of the fourth and corresponding multiplier adds or subtracts its value from the sum Values are ADD and sus If omitted the default value is ADD COE FFSELO R EGISTE Specifies the clock source for the coefficient inputs of the first multiplier Values are UNREGISTERED CLOCKO CLOCK1 and cLock2 The value must be set similar to the value of INPUT_ REGISTER_AO or set as UNREGISTERED CO EFFS EL1 RE GISTE Specifies the clock source for the coefficient inputs of the second multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOcK2 The value must be set similar to the value of INPUT_ REGISTER_AO or set as UNREGISTERED CO BEES EL2 RE GIST Specifies the clock source for the coefficient inputs of the third multiplier Values are UNREGISTERED CLOCKO CLOCK1 and cLock2 The value must be set sim
67. ALTCLKCTRL altcikctri E ALTCLKCTRL Name altcikctri Ahakari of ol E DNE kock symbol i Version 14 0 Altcikctrl represents clock buffers that drive the Global Clock Network the Regional Clock Network and the dedicated External Clock path How do you want to use the ALTCLKCTRI For global clock How many clock inputs would you like lily C Create ena port to enable or disable the clock network driven by this buffer How do you want to register the ena port C Ensure glitch free switchover implementation Your IP settings will be saved in a qsys file Top level Name E HEEMTII AMEN 6 Author Altera Corporation Description no description Group Basic Functions Clocks E PLLs and Resets Altcikctrl Presets for altclkctri_O Name unnamed iProjec d New t Device Settings F zd Device Family Stratix V v 5 eerie Device Unknown iw Type Ja E o 9 3 infi B info Your IP will be saved in unnamed qsys Q unsa Q unsa Q unsa I I library 1 lo presets for ALTCLKCTRL 14 0 0 Errors O Warnings Generate HDL Finish Specify your IP variation name i and target device Apply preset parameters for ud specific applications UG 01063 2014 12 19 View IP port and parameter details Specifying IP Core Parameters and Options Legacy Parameter Edito
68. Arithmetic IP Cores User Guide TOC 3 ALTECC Error Correction Code Encoder Decoder 5 1 ALTECG ENCODER Peatubes aoucseuescedba ictu P REED IDEA FAR I ONU AEN aM UM AN EE 5 2 Resource Utilization and DRE INNING euam etie hiubi ead orc Dd boaun Ped rut do ed eif resn ic lad 5 3 Verilog HDL Prototype AL LECC BINGO DER usciti aere rreserrin sto t b rtr tn RIEN Ride Rx E pU 5 5 Verilog HDL Prototype AL TECK DECODER c easecctt sitiecitett tentes densae dune einer ERN D AEN 5 5 VHDL Component Declaration ALTECC ENCODER eese ene tneen nente ene ene 5 6 VHDL Component Declaration ALTECC DECODER esee eene te tentntn tnter en enne 5 6 VHDL LIBRARY USE Declaration eee eeeeesssseneeeeeeseneseneecescscsesseesececscseaesncecucueseanencecesseseanenseeseas 5 7 Ports ALTECC_ ENCODER htt ERE REM REI ERR I aaa E EnaA EEEa REANA 5 7 Ports ALTEGG DEGODER sse aieteitian i RE RR eae E UOTE 5 7 Parameters ALTECC ENCODER esee entrent tenet Ar senten tette tests teinte testen 5 8 Parameters ALTECC DECODER eere eren ennnn entente itt tn sa tette eaten enses th tesa ss tnn 5 8 Desigit Example 1 ALTECC BNOODEDB adea d Mut ARM DEA RAR ERRARE OA 5 9 Understanding the Simulation Results ctia pertice yt prre co SM pu ria tos 5 9 Design Example 2 ALTECC DECODER wi ssisacdssasshussiocdesaspasatuntead Rt pte AATA E RE RR 5 12 Understanding the Simulation Results aee
69. B_MULTIPLIE EGISTE String Parameter 1 3 Specifies the clock signal for the register on the corresponding addnsub input Values are UNREGISTERED CLOCKO CLOCK1and cLock2 If the corresponding addnsub port is UNUSED this parameter is ignored If omitted the default value is UNREGISTERED ADDNSUB_MULTIPLIER_ACLR String No Parameter 1 3 Specifies the asynchronous clear signal for the first register on the corresponding addnsub input Values are NONE ACLRO and ACLR1 If the corresponding addnsub port value is UNUSED this parameter is ignored If omitted the default value is NoNE PORT ADDNSUB String No Parameter 1 3 Specifies the usage of the corresponding addnsub input port Values are PORT USED and PORT_UNUSED If omitted the default value is PoRT UNUSED CHAINOUT ADDER WIDTH CHAININ String Integer No No Specifies the chainout mode of the final adder stage Values are ves and no If omitted the default value is no Width of the chainin port WIDTH_ CHAININ equals WIDTH_RESULT if chainin port is used If omitted the default value is 1 ACCUM SLOAD REGISTER String No Specifies the clock source for the first register on the accum s1oad or sload accum input Values are UNREGISTERED CLOCKO CLOCK1 and crock2 If omitted the default value is UNREGISTERED
70. C ENCODER megafunction Table 5 3 ALTECC ENCODER Megafunction Input Ports data Yes Data input port The size of the input port depends on the wrpTH_ DATAWORD parameter value The data port contains the raw data to be encoded clock Yes Clock input port that provides the clock signal to synchronize the encoding operation The clock port is required when the LPM PIPELINE value is greater than 0 clocken No Clock enable If omitted the default value is 1 aclr No Asynchronous clear input The active high acir signal can be used at any time to asynchronously clear the registers Table 5 4 ALTECC ENCODER Megafunction Output Ports Yes Encoded data output port The size of the output port depends on the WIDTH CODEWORD parameter value Ports ALTECC DECODER The following tables list the input and output ports for the ALTECC_DECODER megafunction Table 5 5 ALTECC DECODER Megafunction Input Ports data Yes Data input port The size of the input port depends on the wIDTH_ CODEWORD parameter value ALTECC Error Correction Code Encoder Decoder Altera Corporation C Send Feedback 5 8 Parameters ALTECC_ENCODER UG 01063 2014 12 19 clock Yes Clock input port that provides the clock signal to synchronize the encoding operation The clock port is required when the LPM_PIPELINE value is greater than 0 clocken No Clock enable If omitted the default value is 1 aclr No Asy
71. IDTHP 1 downto 0 end component VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY lpm USE lpm lpm components all Ports The following tables list the input and output ports for the LPM_COUNTER megafunction Table 2 2 LPM_COUNTER Megafunction Input Ports data No Parallel data input to the counter The size of the input port depends on the LPM_WIDTH parameter value clock Yes Positive edge triggered clock input clk en No Clock enable input to enable all synchronous activities If omitted the default value is 1 LPM COUNTER Counter LJ Send Feedback Altera Corporation 2 4 Ports UG 01063 2014 12 19 cnt en No Count enable input to disable the count when asserted low without affecting sload sset or sclr If omitted the default value is 1 updown Controls the direction of the count When asserted high 1 the count direction is up and when asserted low 0 the count direction is down If the LPM_DIRECTION parameter is used the updown port cannot be connected If LPM_DIRECTION is not used the updown port is optional If omitted the default value is up 1 cin No Carry in to the low order bit For up counters the behavior of the cin input is identical to the behavior of the cnt en input If omitted the default value is 1 VCC aclr aseu No Asynchronous clear
72. II software determines whether to use the dedicated multiplier circuitry based on the multiplier width If a device does not have dedicated multiplier circuitry the DEDICATED_ MULTIPLIER_CIRCUITRY parameter has no effect and the value defaults to wo Altera Corporation LPM MULT Multiplier CJ Send Feedback UG 01063 2014 12 19 LPM_MULT Parameters 4 7 DSP_BLOCK_BALANCING String Specifies whether to use a dedicated multiplier circuitry implementation Values are UNUSED AUTO DSP BLOCKS and LOGIC ELEMENTS If omitted the default value is UNUSED This parameter is available for all Altera devices except Cyclone HardCopy MAX II MAX 3000 and MAX 7000 devices T LOGIC ELEMENTS String No Specifies whether to use a logic element implementation based on the selected device family When implemented in LEs the LPM MULT megafunction uses a variation on the Booth algorithm for all device families Values are OFF SIMPLE 18 BIT MULTIPLIERS SIMPLE MULTIPLIERS WIDTH 18 BIT MULTIPLIERS and LOGIC ELEMENTS T DEDICATED_MULTIPLIER MIN_INPUT_WIDTH_FOR_AUTO Integer No Altera specific parameter You must use the LPM_HINT parameter to specify the DEDICATED MULTIPLIER MIN OUTPUT WIDTH FOR AUTO parameter in VHDL design files If the DEDICATED_ MULTI
73. IP that are not available in the Quartus II IP Catalog For more information about using the Qsys IP Catalog refer to Creating a System with Qsys in the Quartus II Handbook Using the Parameter Editor The parameter editor helps you to configure IP core ports parameters and output file generation options e Use preset settings in the parameter editor where provided to instantly apply preset parameter values for specific applications e View port and parameter descriptions and links to documentation e Generate testbench systems or example designs where provided Figure 1 3 IP Parameter Editors A IP Parameter Editor unnamed qsys users jbrossar unnamed qsys s Tow View IP por t File Edit System Generate View Tools Help i i and parameter 4 Parameters mm a Details 3 Block Symbol 5 f PPE i details Tk aa Name altclketrl E i s J About this C Ancikctri H Version 140 W About this Core Author Altera Corporation aka k buffers that drive the Global Clock Network the Regional Clock Network Description no description amp oe id th I Clock path H i ee jGroup BasicFuncions Clocks Legacy parameter How d the ALTCLKCTRI For global clock i i Ainai Reset ST How many clack inputs would vou ike 1T zi i editors Re create ena por to enable or disable the clock network driven
74. Integer Arithmetic IP Cores User Guide Subscribe UG 01063 2014 12 19 LJ Send Feedback 101 Innovation Drive San Jose CA 95134 N OPS BJAN www altera com TOC 2 Integer Arithmetic IP Cores User Guide Contents Integer Arithmetic Megafunctions s sesssessssesssesssessscessessssesssesssesssessssesssessoe 1 1 Rcgi vin gg e TN 1 2 lastalling and Licensing IP dro C T 1 2 Customizing and Generating IP COres ess sseesssesssssessstesstetsstessrtresreeesreessrtentetntesntensntesnteesnteeneresrereret 1 2 IP Catalog and Parameter EGHOEP a uaa pntat c d bu Hc inii a ERAN zn REED ta po dt 1 3 Using the ricis Me 1 4 Specifying IP Core Parameters and ODBONHS aduenit ashes hib tette bc i m toca dita 1 4 Specifying IP Core Parameters and Options Legacy Parameter Editors sss 1 6 Files Generated for Altera IP Cores Legacy Parameter Editor sss 1 7 Upgrading IP Br 1 8 Migrating IP Cores to a Different DEVICOL oisi etr tapis ns pliste eei pits dta un dada 1 11 Simulating Altera IP Cores in other EDA TO0lS uode NW RpPd pi e PISb in repere Ren e pra Ur AE EE 1 12 LPM_COUNTER iCOUDter oven e A eaveEDvE E WV Vern m e ev ME 2 1 HOAUULES M 2 1 Resource Utilization and Derfofmatice ovd dere mdi ic ti Dd dca cde der L a RN 2 2 Verilog HDL uen sg D
75. K2 and CLOCK3 If omitted the default value is CLOCKO INPUT REG B String No Specifies the clock port for the datab port Values are UNREGISTERED CLOCKO CLOCK1 and cLocxz If omitted the default value is CLOCKO INTENDED DEVICE FAMILY String This parameter is used for modeling and behavioral simulation purposes Create the ALTMULT ACCUM megafunction with the MegaWizard Plug In Manager to calculate the value for this parameter LPM HINT String No When you instantiate a library of parameterized modules LPM function in a VHDL Design File vhd you must use the LPM_HINT parameter to specify an Altera specific parameter For example LPM HINT CHAIN SIZE 8 ONE INPUT IS CONSTANT YES The default value is UNUSED LPM TYPE String Identifies the library of parameterized modules LPM entity name in VHDL design files ALTMULT ACCUM Multiply Accumulate LJ Send Feedback Altera Corporation UG 01063 MULTIPLIER_ACLR String Specifies the asynchronous clear signal for the register immediately following the multiplier Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default value is ACLR3 MULTIPLIER_REG String No Specifies the clock signal for the register that immediately follows the multiplier Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If
76. LTECC_DECODER This design example uses the ECC decoder to decode input code words of 13 bit widths to generate 8 bits of output data An asynchronous clear signal is also used to illustrate how the signal affects the registered ports This example uses the MegaWizard Plug In Manager in the Quartus II software The following design files can be found in altecc DesignExample2 zip e altecc decode qar archived Quartus II design files e altecc decode ex msim ModelSim Altera files Understanding the Simulation Results The following settings are observed in this example e Thedata input width is set to 13 bits The output port q has a width of 8 bits e The asynchronous clear acir signal is enabled e Pipelining is enabled with an output latency of 2 clock cycles Hence the result is seen on the g port two clock cycles after the input data is available The following figure shows the expected simulation results in the ModelSim Altera software Figure 5 6 Design Example 2 Simulation Waveform for the ECC Decoder 4 jalecc decode vlg vec tstjadr 4 jalkecc decode vlg vec tsticiock E3X jalkecc decode vig vec tst data Ex jaltecc decode vlg vec tstjq 4 jaltecc decode vlg vec tstjerr corrected 4 jaltecc decode vig vec tst err detected 4 jaltecc decode vlg vec tstjerr fatal The following sequence corresponds with the numbered items in the figure 1 The decoder decodes the code word 14FO at the first rising edge of the
77. Multiply Adder C Send Feedback ALTMULT_COMPLEX Complex Multiplier 1 0 2014 12 19 UG 01063 GX subscribe C Send Feedback The ALTMULT COMPLEX megafunction implements the multiplication of two complex numbers and offers the conventional implementation mode You can use the conventional representation for the following e All supported Altera devices e Input data widths of any size The ALTMULT COMPLEX megafunction implements the multiplication of two complex numbers and offers the following two implementation modes e Canonical You can use the canonical representation for the following e All supported Altera devices prior to Stratix III devices The canonical representation is no longer supported from Stratix III onwards e Input data widths of less than 18 bits e Conventional You can use the conventional representation for the following e All supported Altera devices e Input data widths of any size With the conventional representation you can use the ALTMULT ADD megafunction to implement the complex multiplier by instantiating two multipliers The following figure shows the ports for the ALTMULT COMPLEX megafunction O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trad
78. No Clock input for pipelined usage For LPM_PIPELINE values other than 0 default the clock port must be enabled clken No Clock enable for pipelined usage When the clken port is asserted high the adder subtractor operation takes place When the signal is low no operation occurs If omitted the default value is 1 LPM MULT Multiplier Altera Corporation J send Feedback UG 01063 4 4 LPM_MULT Parameters 2014 12 19 aclr No Asynchronous clear port used at any time to reset the pipeline to all 0s asynchronously to the clock signal The pipeline initializes to an undefined X logic level The outputs are a consistent but non zero value Table 4 3 LPM_MULT IP Core Output Ports result Yes Data output The size of the output port depends on the LPM WIDTHP parameter value If LPM_WIDTHP lt max LPM_ WIDTHA LPM_WIDTHB LPM_WIDTHS or LPM_WIDTHA LPM_ WIDTHS only the LPM_WIDTHP MSBs are present LPM MULT Parameters The following table lists the parameters for the LPM MULT megafunction Table 4 4 LPM MULT Megafunction Parameters LPM WIDTH Integer Y Specifies the width of the dataa port LPM_WIDTHB Integer Yes Specifies the width of the dat ab port LPM_WIDTHP Integer Yes Specifies the width of the result port LPM_REPRESENTATION String No Specifies the type of multiplication performed Values are SIGNED and UNSIGNED If omitted the default value is
79. ODER megafunction if any The following figures show the ports for the ALTECC megafunction O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG 01063 5 2 ALTECC_ENCODER Features 2014 12 19 Figure 5 1 ALTECC_ENCODER Ports ALTECC_ENCODER i clocken i inst Figure 5 2 ALTECC DECODER Ports Sink sue ERE ad Sood E vee LAE a E RA RR ERE RAN ERA RE RA ERE RV RR ALTECC DECODER data cl
80. PLIER CIRCUITRY parameter setting is AUTO this parameter specifies the minimum value of the sum of the LPM_ WIDTHA and LPM WIDTHB parameters in order for the multiplier to be built using dedicated circuitry INPUT A FIXED VALUE String No Specifies the value for the dataa port This parameter is used when the INPUT_A_ IS CONSTANT parameter is set to FIXED For example to pass a four bit value of 3 to the dataa port the INPUT A FIXED VALUE parameter must be set to B0011 INPUT B FIXED VALUE String No Specifies the value for the datab port This parameter is used when the INPUT_B IS CONSTANT parameter is set to FIXED For example to pass a four bit value of 3 to the datab port the INPUT B FIXED VALUE parameter must be set to B0011 LPM MULT Multiplier LJ Send Feedback Altera Corporation ALTECC Error Correction Code Encoder Decoder 5 2014 12 19 UG 01063 GX subscribe C Send Feedback The error correction code ECC is a error detection and correction method in digital data transmission Its primary purpose is to detect corrupted data that occurs at the receiver side during data transmission This error correction method is best suited for situations where errors occur at random rather than in bursts The ECC detects errors through the process of data encoding and decoding For example when the ECC
81. R String Specifies the clock source for the first register on the chainout_ saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocko CHAINOUT SATURATI MEAGER REGISTER CHAINOUT_SATURAT E PIPELINE String String Specifies the asynchronous clear source for the first register on the chainout_saturate input Values are ACLRO ACLR1 ACLR2 and AcLR3 If omitted and CHAINOUT_SATURATE_REGISTER is used the default value is AcLR3 Specifies the clock source for the second register on the chainout saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocko CHAINOUT SATURAT E OUTPUT R EGIST ER String Specifies the clock source for the third register on the chainout saturate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocKo ALTMULT ADD Multiply Adder LJ Send Feedback Altera Corporation 9 30 ALTMULT_ADD Parameters Parameter Name CHAINOUT_SATURATE_OUTPUT_ACLR Type String Requi red No UG 01063 2014 12 19 Description Specifies the asynchronous clear source for the third register on the chainout_saturate input Values are ACLRO ACLR1 ACLR2 and acrn3 If omitted a
82. TURATE PIPELINE REGISTER is used the default value is ACLR3 ALTMULT_ADD Multiply Adder Altera Corporation CJ Send Feedback 9 28 ALTMULT_ADD Parameters Parameter Name CHAINOUT_ROUNDING Type String Requi red No UG 01063 2014 12 19 Description Enables rounding handling at the chainout stage Values are vs NO and VARIABLE A value of YES or No specifies saturation handling setting permanently to on or off A value of VARIABLE allows dynamically controlled saturation handling If the value of CHAINOUT_ ROUNDING is YES the symmetric saturation at the second adder output stage is not allowed If omitted the default value is no CHAINOUT_ROUND_REGISTER String No Specifies the clock source for the first register on the chainout_ round input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocko CHAINOUT ROUND ACLR String Specifies the asynchronous clear source for the first register on the chainout round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and cHAINOUT_ ROUND REGISTER is used the default value is ACLR3 CHAINOUT ROUND PIPELINE R EGISTER String Specifies the clock source for the second register on the chainout_ round input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted
83. ULT_ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Systolic Delay Register 9 9 Figure 9 9 Systolic Delay Register Implementation of 4 Multipliers a0 bO al bl a2 b2 a3 b3 chainin MultO Systolic registers gt Multl chainin gt result Mult2 MENO Q9 gt Mult3 4e gt result The sum of four multipliers is expressed in the following equation Figure 9 10 Sum of 4 Multipliers y t a3 t x b3 t a2 t 1 x b2 t 1 al t 2 x b1 t 2 a0 t 3 x bO t 3 ALTMULT ADD Multiply Adder LJ Send Feedback Altera Corporation UG 01063 9 10 Pre load Constant 2014 12 19 The following lists the advantages of systolic register implementation e Reduces DSP resource usage e Enables efficient mapping in the DSP block using the chain adder structure The systolic delay implementation is only available for the following pre adder modes e Pre adder coefficient mode e Pre adder simple mode e Pre adder constant mode Pre load Constant The pre load constant controls the accumulator operand and complements the accumulator feedback The valid LoaDconst_vaLUE ranges from 0 64 The constant value is equal to
84. UNSIGNED When this parameter value is set to SIGNED the multiplier interprets the data input as signed two s complement LPM_PIPELINE String No Specifies the number of latency clock cycles associated with the result output A value of zero 0 indicates that no latency exists and that a purely combinational function will be instanti ated For Stratix and Stratix GX devices if the design uses DSP blocks you can increase the performance of the design when the value of the LPM_PIPELINE parameter is 3 or less Altera Corporation LPM MULT Multiplier CJ Send Feedback UG 01063 2014 12 19 LPM_MULT Parameters 4 5 IONIE OSE JAILS COINS WANE String You must use the LPM_HINT parameter to specify the INPUT_A_IS_CONSTANT parameter in VHDL design files Values are YES No and UNUSED If dataa is connected to a constant value setting INPUT_A_IS_CONSTANT to YES optimizes the multiplier for resource usage and speed If omitted the default value is no INPUT_B_IS_CONSTANT String No You must use the LPM_HINT parameter to specify the INPUT_B_IS_CONSTANT parameter in VHDL design files Values are YES NO and UNUSED If datab is connected to a constant value setting INPUT B IS CONSTANT to YES optimizes the multiplier for resource usage and speed The default value is no USE EAB String No Specifies RAM block us
85. USED port NUMER in std logic vector LPM WIDTHN 1 downto 0 Altera Corporation LPM DIVIDE Divider C Send Feedback UG 01063 2014 12 19 VHDL LIBRARY_USE Declaration 3 3 UOTIENT out std logic vector LPM WIDTHN 1 downto 0 EMAIN out std logic vector LPM WIDTHD 1 downto 0 end component DENOM in std logic vector LPM WIDTHD 1 downto 0 ACLR in std logic 0 CLOCK in std logic 0 CLKEN in std logic 1 Q RI VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY lpm USE lpm lpm components all Ports The following tables list the input and output ports for the LPM_DIVIDE megafunction Table 3 2 LPM DIVIDE Megafunction Input Ports numer Yes Numerator data input The size of the input port depends on the LPM_WIDTHN parameter value Denominator data input The size of the input port depends on the LPM_WIDTHD parameter value denom clock Clock input for pipelined usage For PM PIPELINE values other than 0 default the clock port must be enabled clken Clock enable pipelined usage When the clken port is asserted high the division operation takes place When the signal is low no operation occurs If omitted the default value is 1 Asynchronous clear port used at any time to reset the pipeline to all o s asynchronously to the clock input aclr
86. VHDL Component Declaration LIBRARY altera mf USE altera mf altera mf components all ALTMULT ADD Ports The following tables list the input and output ports for the ALTMULT ADD megafunction Note For Arria V Cyclone V and Stratix V devices each register can only select between two asynchro nous signals ACLRO ACLR1 and three clock enable pairs CLOCK0 ENAO CLOCK1 ENA1 CLOCK2 ENA2 Table 9 2 ALTMULT ADD Megafunction Input Ports dataa Yes Data input to the multiplier Input port NUMBER OF MULTIPLIERS WIDTH A 1 0 wide datab Yes Data input to the multiplier Input port NUMBER OF MULTIPLIERS WIDTH B 1 0 wide clock No Clock input port 0 3 to the corresponding register This port can be used by any register in the megafunction aclr No Input port 0 3 Asynchronous clear input to the corresponding register ena No Input port 0 3 Clock enable for the corresponding clock port signa No Specifies the numerical representation of the dataa port If the signa port is high the multiplier treats the dataa port asa signed two s complement number If the signa port is low the multiplier treats the dataa portas an unsigned number signb No Specifies the numerical representation of the dat ab port If the signb port is high the multiplier treats the datab port asa signed two s complement number If the signb port is low the mu
87. _COUNTER megafunction offers the following features e Generates up down and up down counters e Generates the following counter types e Plain binary the counter increments starting from zero or decrements starting from 255 e Modulus the counter increments to or decrements from the modulus value specified by the user and repeats e Supports optional synchronous clear load and set input ports e Supports optional asynchronous clear load and set input ports e Supports optional count enable and clock enable input ports e Supports optional carry in and carry out ports O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are adv
88. acts its value from the sum Values are ADD and sus If the addnsub1 port is used this parameter is ignored If omitted the default value is app Specifies whether the fourth multiplier adds or subtracts their results from the total Values are App and sus If the addnsub3 port is used this parameter is ignored If omitted the default value is ADD ACCUMULATOR String No Specifies the accumulator mode of the final adder stage Values are ves and no If omitted the default value is no ACCUM_DIRECTION String Specifies whether the accumulator adds or subtracts its value from the previous sum Values are app and sus If omitted the default value is ADD OUTPUD REGISTER String Specifies the clock signal for the output register Values are UNREGISTERED CLOCKO CLOCK1 and crock2 If omitted the default value is UNREGISTERED OUTPUT ACLR String Specifies the asynchronous clear signal for the second adder register Values are NONE ACLRO and ACLR1 If omitted the default value is NONE PORT SIGN String No Parameter A B Specifies the corresponding sign a b input port usage Values are PoRT UsED and PORT UNUSED If omitted the default value is PORT UNUSED Altera Corporation ALTERA MULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 ALTERA_MULT_ADD Parameters 6 15 ADDNSU
89. afunction which fills up the lowest bit position starting with the LSB This bit order reduces the complexity of the circuit design Table 5 10 Design Example 1 Filling of Data Bits 1111 0000 for a 13 Bit Code Word BESSEREN E CIUS ee EOM ENTERS Parity Bits and Data Bits e Each parity bit calculates the parity for some of the bits in the code word The position of the parity bit determines the sequence of bits that it alternately checks and skips The following section list the sequence of bits that each parity bit checks Parity bit 1 check 1 bit skip 1 bit check 1 bit skip 1 bit 1 3 5 7 9 11 Parity bit 2 check 2 bits skip 2 bits check 2 bits skip 2 bits 2 3 6 7 10 11 Parity bit 4 check 4 bits skip 4 bits check 4 bits skip 4 bits 4 5 6 7 1 2 Parity bit 8 check 8 bits skip 8 bits check 8 bits skip 8 bits 8 9 10 11 12 Table 5 11 Design Example 1 Calculation of Parity Bits Ee EB DENN BUS KC RR LEUR E Parity Bits P1 and Data Bits ALTECC Error Correction Code Encoder Dec Calculate P2 oder Alte Corporation culate P3 Calculate P4 4 3 MRT Dem f cot UG 01063 5 12 Design Example 1 Calculation of Parity Bits 2014 12 19 e The encoded input data for FO is 14F0 1 0100 1111 0000 in binary as seen on the output port q at 17 5 ns Design Example 1 Calculation of Parity Bits Design Example 2 A
90. age Values are on and orr Setting the USE_EAB parameter to oN allows the Quartus II software to use embedded array blocks EABs to implement 4 x 4 or 8 x const value building blocks in some obsolete devices Altera recommends that you set USE_EAB to on only when LCELLS are in short supply This parameter is not available for simulation with other EDA simulators If you wish to use this parameter when you instantiate the function in a Block Design File bdf you must specify it by entering the parameter name and value manually with the Parameters tab in the Symbol Properties dialog box or in the Block Properties dialog box You can also use this parameter name in a Text Design File tdf or a Verilog Design File v You must use the LPM_HINT parameter to specify the USE_EAB parameter in VHDL design files LPM_MULT Multiplier LJ Send Feedback Altera Corporation 4 6 LPM_MULT Parameters UG 01063 2014 12 19 MAXIMIZE Integer N Altera specific parameter You must use the LPM_HINT parameter to specify the MAXIMIZE_SPEED parameter in VHDL design files You can specify a value between 0 and 10 If used the Quartus II software attempts to optimize a specific instance of the LPM_MULT function for speed rather than area and overrides the setting of the Optimization Technique logic option If MAxIMIZE_SPEED is unused the value of the Optimization Technique option
91. alue of NEAREST_INTEGER specifies round to nearest integer If omitted the default value is NEAREST_INTEGER OUTPUT_ROUND_REGISTER String No Specifies the clock source for the first register on the output round input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is cLocKo OUTPUT ROUND ACLR OUTPUT ROUND PIPELINE R EGISTE String No Specifies the asynchronous clear source for the first register on the output round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ourPuT ROUND REGISTER is used the default value is ACLR3 String No Specifies the clock source for the second register on the output round input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLock3 If omitted the default value is cLocko OUTPUT ROUND PIPELINE ACLR String No Specifies the asynchronous clear source for the second register on the output round input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and OUTPUT_ ROUND PIPELINE REGISTER is used the default value is ACLR3 Altera Corporation ALTMULT ADD Multiply Adder G send Feedback UG 01063 2014 12 19 ALTMULT_ADD Parameters 9 27 Parameter Name Type Requi Description red OUTPUT_SATURATION String No
92. ameters 2 7 LPM_PORT_UPDOWN String Specifies the usage of the updown input port If omitted the default value is PORT_ CONNECTIVITY When the port value is set to PORT_USED the port is treated as used When the port value is set to PORT_UNUSED the port is treated as unused When the port value is set to PORT_CONNECTIVITY the port usage is determined by checking the port connectivity LPM_COUNTER Counter CJ Send Feedback Altera Corporation LPM_DIVIDE Divider 2014 12 19 UG 01063 GX subscribe _ Send Feedback The LPM_DIVIDE megafunction implements a divider to divide a numerator input value by a denominator input value to produce a quotient and a remainder The following figure shows the ports for the LPM_DIVIDE megafunction Figure 3 1 LPM_DIVIDE Ports LPM_DIVIDE numer quotient denom remain clock clken aclr Features The LPM_DIVIDE megafunction offers the following features e Generates a divider that divides a numerator input value by a denominator input value to produce a quotient and a remainder e Supports data width of 1 256 bits e Supports signed and unsigned data representation format for both the numerator and denominator values e Supports area or speed optimization e Provides an option to specify a positive remainder output e Supports pipelining configurable output latency e Supports optional asynchronous clear and clock enable ports
93. ars at the output port q 2 clock cycles later The 8 bit input data F0 is encoded to generate a 13 bit output code word 14F0 The input data is appended with 5 parity bits The ECC encoder encodes the data based on the Hamming Code scheme The following steps describe the Hamming Code algorithm and explain how the ECC encoder encodes input data FO to generate the output code word of 14F0 e Ina 13 bit code word there are 13 locations bit positions and each location holds 1 bit There are 8 bits of original data and the appended 5 parity bits The locations bit positions for the bits must be defined bit positions that are powers of 2 are used as parity bits positions 1 2 4 8 e The following table lists the bit positions and the position of the parity bits of a 13 bit code word P5 is the extra parity bit added The prefix P denotes parity Table 5 9 Design Example 1 Position of Parity Bits for a 13 Bit Code Word ESPECIE CE EAS AE Parity Bits P1 e All other bit positions are for the data to be encoded The least significant bit LSB of the data bit fills the lowest bit position In this case starting from the LSB of the data FO 1111 0000 in binary fills the empty bit positions starting from position 3 as shown in the following table The prefixes P and D denote parity and data respectively For the standard Hamming Code algorithm the MSB of the data bit fills the lowest bit position unlike the Altera ECC meg
94. ation From Complex Multiplication equation the multiplication of two complex numbers can be represented in two parts real and imaginary The following equation shows that the xy_real variable represents real representation Altera Corporation ALTMULT_COMPLEX Complex Multiplier C Send Feedback UG 01063 2014 12 19 Conventional Representation 10 3 xy real ac bd ac bd ad bc ad bc ac ad bc bd ad bc a b c d ad bc xy real represents the real part The following equation shows that the xy imaginary variable represents imaginary representation xy imaginary ad bc xy imaginary represents imaginary Both equations derived from Complex Multiplication equation Note The canonical representation is available for all supported Altera devices prior to Stratix III devices Related Information Complex Multiplication on page 10 2 Conventional Representation The multiplication of two complex numbers can be represented in two parts real and imaginary The xy real variable in the following equation represents the real part xy real ac bd The xy imaginary variable in the following equation represents the imaginary part xy imaginary ad bc Features The ALTMULT COMPLEX megafunction offers the following features e Generates a multiplier to perform multiplication operations of two complex numbers Note When building multipliers large
95. ation of the multiplier input A If the signa port is high the multiplier treats the multiplier input A port as a signed number If the signa port is low the multiplier treats the multiplier input A port as an unsigned number signb No Specifies the numerical representation of the multiplier input B port If the signb port is high the multiplier treats the multiplier input B port as a signed two s complement number If the signb port is low the multiplier treats the multiplier input B port as an unsigned number scanina Input for scan chain A Input port WIDTH A 1 0 wide When the INPUT_SOURCE_A parameter has a value of scana the scanina port is required accum_sload No Dynamically specifies whether the accumulator value is constant If the accum_sload port is high then the multiplier output is loaded into the accumulator Do not use accum_sload and sload_accum simultaneously sload_accum Dynamically specifies whether the accumulator value is constant If the sload_accun port is low then the multiplier output is loaded into the accumulator Do not use accum_sload and sload_accum simultaneously chainin Adder result input bus from the preceding stage Input port WIDTH CHAININ 1 0 wide addnsubl Controls the functionality of the first adder If the addnsub1 port is high the first adder performs an add function If the addnsub1 port is low the adder performs a subtract
96. bility arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN Of p AN 101 Innovation Drive San Jose CA 95134 UG 01063 1 2 Design Example Files 2014 12 19 Altera also provides floating point IP cores For more information about the floating point IP cores refer to the Floating Point IP Cores User Guide Design Example Files Altera provides design example files that are simulated in the ModelSim Altera software to generate a waveform display of the device behavior You should be familiar with the ModelSim Altera software before using the design examples To get started with the ModelSim Altera software refer to the ModelSim Altera Software Support page on the Altera website The support page includes links to such topics as installation usage and troubleshooting For more details about the design example for a specific IP core refer to the Design Example section for that megafunction Design examples are provided only for some IP cores in this user guide Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for production use without purchasing an additional license You can evaluate any Altera
97. by this buffer Efcke Ee How do you want to register the ena pon T i s Set Up Simulation C Ensure glitch free switchover implementation B 7 j gj Top level Name Name unnamed _ Device Settings IStratix V Unknown Tel O 5 Oio vouie wi be saved in unnamedasys uns O nsi unsd L 0 Errors 0 Warnings H E Generate HDL Specify your IP variation name i Apply preset parameters for o E and target device specific applications Specifying IP Core Parameters and Options The parameter editor GUI allows you to quickly configure your custom IP variation Use the following steps to specify IP core options and parameters in the Quartus II software Refer to Specifying IP Core Parameters and Options Legacy Parameter Editors for configuration of IP cores using the legacy parameter editor Altera Corporation Integer Arithmetic Megafunctions C Send Feedback UG 01063 2014 12 19 Specifying IP Core Parameters and Options 1 5 1 In the IP Catalog Tools gt IP Catalog locate and double click the name of the IP core to customize The parameter editor appears 2 Specify a top level name for your custom IP variation The parameter editor saves the IP variation settings in a file named lt your_ip gt qsys Click OK 3 Specify the parameters and options for your IP variation in the parameter editor including one or more of the following Refer to your IP core user guide for i
98. ccumulate C Send Feedback UG 01063 2014 12 19 ALTMULT_ACCUM Parameters 8 15 MUTIPL IER3_DIRECTION String Specifies whether the fourth and all subsequent odd numbered multipliers add or subtract their results from the total Values are app and sus If the addnsub3 port is used this parameter is ignored If omitted the default value is ADD NUMBER_OF_MULTIPLIERS Integer Yes Number of multipliers to be added together Values are 1 up to 4 WIDTH Integer Yes Specifies the width of the datac port WIDTH COEF Integer Yes Specifies the width of the coefsel port LOADCONST VALUE Integer Pre load constant value to complement accumulator mode Values are 2 N where 0 lt N lt 64 PREADD ER MODE String No Specifies the mode of pre adder settings to be used Values are SIMPLE COEF INPUT SQUARE and CONSTANT The default value is SIMPLE PREADDE R DIRE CTION 0 String No Specifies whether the pre adder of the first multiplier adds or subtracts its value from the sum Values are ADD and sus If omitted the default value is app PREADDE R DIRE CTION 1 String No Specifies whether the pre adder of the second multiplier adds or subtracts its value from the sum Values are ADD and SUB If omitted the default value is
99. chainin input port to form the final result Each multiply add element must be delayed by a single cycle so that the results synchronize appropriately when added together Each successive delay is used to address both the coefficient memory and the data buffer of their respective multiply add elements For example a single delay for the second multiply add element two delays for the third multiply add element and so on Figure 6 7 Systolic Registers Systolic registers TEE E a c 0 c 1 e c N 1 S gi Sa S ae gt eee me gt y4 x t represents the results from a continuous stream of input samples and y t represents the summation of a set of input samples and in time multiplied by their respective coefficients Both the input and output results flow from left to right The c 0 to c N 1 denotes the coefficients The systolic delay registers are denoted by S t whereas the represents a single clock delay Systolic delay registers are added at the inputs and outputs for pipelining in a way that ensures the results from the multiplier operand and the accumulated sums stay in synch This processing element is replicated to form a circuit that computes the filtering function This function is expressed in the following equation Altera Corporation ALTERA_MULT_ADD Multiply Adder C Send F
100. cifies the asynchronous clear for the dataa operand of the first multiplier Values are ACLRO ACLR1 ACLR2 and AcLR3 If omitted and corresponding INPUT REGISTER A is used the default value is ACLR3 INPUT ACLR A1 String No Specifies the asynchronous clear for the dataa operand of the second multiplier Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding INPUT REGISTER A is used the default value is ACLR3 Altera Corporation ALTMULT_ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 ALTMULT_ADD Parameters 9 1 red INPUT_ACLR_A2 String Specifies the asynchronous clear for the dataa operand of the third aaeei Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding INPUT REGISTER A is used the default value is ACLR3 INPUT ACLR A3 String No Specifies the asynchronous clear for the dataa operand of the fourth and corresponding multiplier Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding INPUT REGISTER A is used the default value is ACLR3 INPUT ACLR BO String Specifies the asynchronous clear for the datab operand of the first multiplier Values are ACLRO ACLRI1 ACLR2 and AcLR3 If omitted and corresponding INPUT REGISTER B is used the default value is ACLR3 INPUT ACLR B1 String No Specifies the asynchr
101. clock at 2 5 ns In this case the input code word is not corrupted The 13 bit input code word 14F0 10100 1111 0000 in binary is decoded to generate an 8 bit output data of FO The following table lists the arrangement of parity bits and data bits in the code word 14F0 The prefixes P and D denote parity and data respectively Altera Corporation ALTECC Error Correction Code Encoder Decoder C Send Feedback UG 01063 2014 12 19 Understanding the Simulation Results 5 13 Table 5 12 Design Example 2 Arrangement of Parity Bits and Data Bits in Code Word 14F0 LSB ps PA P3 P2 P1 D7 D6 DS D4 D3 D2 Di Do 1 0 1 0 0 1 1 1 1 0 0 0 0 The ECC decoder decodes the code word based on the Hamming Code scheme The following steps describe the Hamming Code algorithm and explain how the ECC decoder decodes input code word 14F0 to generate output data FO ALTECC Error Correction Code Encoder Decoder Altera Corporation C Send Feedback UG 01063 5 14 Understanding the Simulation Results 2014 12 19 e All bits have their bit positions and bit positions that are powers of 2 are used as parity bits positions 1 2 4 8 Table 38 lists the bit positions and the positions of the parity bits in a 13 bit code word Table 5 13 Design Example 2 Position of Parity Bits for a 13 Bit Code Word ESS ECA EA EN EAS E Parity Bits and Data Bits e All other bit positions are for the data bits The LSB of the data bit fi
102. corresponding sign port is unused SIGN REG String No Parameter A B Specifies the clock signal for the first register on the corresponding sign port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is LOcKO This parameter is ignored if the corresponding sign port is unused Q WIDTH A Integer Yes Specifies the width of the dataa port WIDTH B WIDTH RESULT Integer Integer Yes Specifies the width of the datab port Specifies the width of the result port Table 8 6 ALTMULT ACCUM Megafunction Parameters Stratix Il Stratix Il GX Stratix III Stratix IV Arria GX and HardCopy devices only MULTIPLIER SATURATION String Specifies multiplier saturation Values are No YES and VARIABLE If omitted the default value is NO Altera Corporation ALTMULT ACCUM Multiply Accumulate C Send Feedback UG 01063 2014 12 19 ALTMULT_ACCUM Parameters 8 13 Table 8 7 ALTMULT_ACCUM Megafunction Parameters Arria V Cyclone V and Stratix V Devices Only INPUT_ACLR_CO String Specifies the asynchronous clear for the datac operand of the first multiplier Values are ACLRO and acrnRi If omitted and corresponding INPUT_ REGISTER_C is used the default value is acLRO The value for INPUT_ACLR_CO must be set similar to the value of INPUT_ACLR_AO
103. cy Look Up Logic Logic Table ALUT Register Module DLR ALM 10 1 131 0 70 133 Stratix III 30 5 1017 0 635 71 64 10 4345 0 2623 41 10 1 131 0 70 138 Stratix IV 30 5 1018 0 642 82 64 10 4347 0 2634 48 Verilog HDL Prototype The following Verilog HDL prototype is located in the Verilog Design File v Ipm v in the Quartus II installation directory gt eda synthesis directory module lpm_divide quotient remain numer denom clock clken acir parameter lpm_type lpm_divide parameter lpm_widthn 1 parameter lpm_widthd 1 parameter lpm_nrepresentation UNSIGNED parameter lpm_drepresentation UNSIGNED parameter lpm_remainderpositive TRUE parameter lpm_pipeline 0 parameter lpm hint UNUSED input clock input clken input aclr input 1pm widthn 1 0 numer input 1pm widthd 1 0 denom output lpm widthn 1 0 quotient output lpm_widthd 1 0 remain endmodule VHDL Component Declaration The VHDL component declaration is located in the VHDL Design File vhd LPM_PACK vhd in the Quartus II installation directory gt libraries vhdl lpm directory component LPM DIVIDE generic LPM WIDTHN natural LPM WIDTHD natural ENTATION string LPM NREPRES UNSIGNED LPM DREPRESENTATION string UNSIGNED LPM PIPELINE natural 0 LPM TYPE string L DIVIDE LPM HINT string UN
104. data clock acti clken result parameter parameter parameter parameter parameter parameter parameter width size 2 widthr 4 shift 0 msw_subtract representation pipeline 0 parameter result_alignment LSB parameter lpm_type parallel_add input width size 1 0 data input clock input aclr input clken output widthr 1 0 4 i NO or YES UNSIGNED or MSB result endmodule VHDL Component Declaration 9 The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column Altera Corporation PARALLEL ADD Parallel Adder C Send Feedback UG 01063 2014 12 19 VHDL LIBRARY_USE Declaration 12 3 The VHDL component declaration is located in the VHDL Design File vhd altera mf components vhd in the Quartus II installation directory gt libraries vhdl altera_mf directory component parallel add generic width natural 4 size natural 2 widthr natural 4 shift natural 0 msw subtract string NO representation string UNSIGNED pipeline natural 0 result alignment string LSB lpm hint string UNUSED lpm type string parallel add port data in altera mf logic 2D size 1 downto 0 width 1 downto 0 clock in std logic 1 aclr in
105. der The following figure shows the ports for the ALTMULT ADD megafunction O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01063 9 2 ALTMULT_ADD Multiply Adder 2014 12 19 Figure 9 1 ALTMULT_ADD Ports ALTMULT_ADD dataa signa scanouta datab signb datac coefselo coefselt scanoutb coefsel2 l coefsel3 result e addnsub1 overflow
106. e Click Project gt Archive Project to save the project in your previous version of the Quartus II software This archive preserves your original design source and project files Restore the archived project in the latest version of the Quartus II software Click Project gt Restore Archived Project Click OK if prompted to change to a supported device or overwrite the project database File paths in the archive must be relative to the project directory File paths in the archive must reference the IP variation v or vhd file or qsys file not the qip file In the latest version of the Quartus II software open the Quartus II project containing an outdated IP core variation The Upgrade IP Components dialog automatically displays the status of IP cores in your project along with instructions for upgrading each core Click Project gt Upgrade IP Components to access this dialog box manually To simultaneously upgrade all IP cores that support automatic upgrade click Perform Automatic Upgrade The Status and Version columns update when upgrade is complete Example designs provided with any Altera IP core regenerate automatically whenever you upgrade the IP core Integer Arithmetic Megafunctions Altera Corporation CJ Send Feedback UG 01063 1 10 Upgrading IP Cores 2014 12 19 Figure 1 7 Upgrading IP Cores e Upgrade IP Components x The following IP components are used in your design You should upgrade outdated components to t
107. e 1 1 List of IP Cores IP Cores Function Overview LPM Megafunctions LPM_COUNTER Counter Counter LPM_DIVIDE Divider Divider LPM_MULT Multiplier Multiplier Altera specific ALT Megafunctions ALTECC ECC Encoder Decoder ALTERA_MULT_ADD Multiply Adder Multiplier Adder ALTMEMMULT Memory based Constant Memory based Constant Coefficient Multiplier Coefficient Multiplier ALTMULT ACCUM Multiply Accumulate Multiplier Accumulator ALTERA MULT ADD Multiply Adder Multiplier Adder ALTMULT COMPLEX Complex Multiplier Complex Multiplier ALTSQRT Integer Square Root Integer Square Root PARALLEL ADD Parallel Adder Parallel Adder If you are unfamiliar with IP cores refer to the Introduction to IP Cores User Guide O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or lia
108. e NONE ACLRO and ACLR1 If omitted and the corresponding SYSTOLIC DELAY is used the default value is AcLRO The value must be set similar to the value of oUTPUT ACLR SYSTOLIC ACLR3 String Specifies the asynchronous clear source for the systolic register inputs of the third multiplier Values are NONE ACLRO and Acrn1 If omitted and the corresponding SYSTOLIC DELAY is used the default value is AcLRO The value must be set similar to the value of oUTPUT ACLR COEFO Integer No Specifies the coefficient value for the inputs of the first multiplier The number of coefficient bits must be set similar to the value of wIDTH_ COME Altera Corporation ALTMULT_ACCUM Multiply Accumulate C Send Feedback UG 01063 2014 12 19 Design Example Shift Accumulator 8 19 COEF 1_ Integer eee the coefficient value 0 7 for the inputs of the oo multiplier The number of coefficient bits must be set similar to the value of WIDTH_COEF Comm Integer Specifies the coefficient value 0 7 for the inputs of the third multiplier The number of coefficient bits must be set similar to the value of wIDTH_ COEF COEF3 Integer Specifies the coefficient value 0 7 for the inputs of the fourth multiplier The number of coefficient bits must be set similar to the value of WIDTH_COEF Design Example Shift Accumulato
109. e coefficient The chain adder stores the gradually combined results from the multiplier and the previously registered result from the chainin input port to form the final result Each multiply add element must be delayed by a single cycle so that the results synchronize appropriately when added together Each successive delay is used to address both the coefficient memory and the data buffer of their respective multiply add elements For example a single delay for the second multiply add element two delays for the third multiply add element and so on Figure 9 7 Systolic Registers Systolic registers a un i l gt gt qe gt c 0 c 1 60 c 2 c N 1 E Sa St S on soo y t x t represents the results from a continuous stream of input samples and y t represents the summation of a set of input samples and in time multiplied by their respective coefficients Both the input and output results flow from left to right The c 0 to c N 1 denotes the coefficients The systolic delay registers are denoted by S71 whereas the represents a single clock delay Systolic delay registers are added at the inputs and outputs for pipelining in a way that ensures the results from the multiplier operand and the accumulated sums stay in synch This processing element is replicated to form a circuit that computes the filtering function This function is expressed in the following equation
110. e scanina and scaninb simultaneously Table 9 6 ALTMULT ADD Megafunction Output Ports Stratix Ill and Stratix IV Devices Only chainout sat overflow No Overflow flag for the chainout saturation ALTMULT ADD Parameters The following table lists the parameters for the ALTMULT ADD megafunction Note For Stratix III Stratix IV and Arria II GX devices when the output result is gt 36 bits for example when you set width a 18 and width 5 18 the option for rounding and saturation is disabled This is because additional logic is used to generate the MSB Table 9 7 ALTMULT ADD Megafunction Parameters red NUMBER_OF_MULTIPLIE Integer Number of multipliers to be added together Values are 1 up to 4 WIDTH_A Integer Yes Width ofthe dataa port WIDTH_B Integer Yes Width of the datab port WIDTH_RESULT Integer Yes Width of the result port Value includes all bits before rounding and saturation INPUT_REGISTER_AO String No _ Specifies the clock port for the dataa operand of the first multiplier Values are UNREGIS TERED CLOCK0 CLOCK1 CLOCK2 and cLock3 If omitted the default value is cLocko For Stratix III devices INPUT REGISTER A0 must have similar values with zNPUT REGISTER A 1 3 Altera Corporation ALTMULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 ALTMULT_ADD Parameters 9 1
111. ecific IP cores in your design You must upgrade IP cores that require it before you can Integer Arithmetic Megafunctions C Send Feedback Altera Corporation UG 01063 2014 12 19 Upgrading IP Cores 1 9 compile the IP variation in the current version of the Quartus II software Many Altera IP cores support automatic upgrade The upgrade process renames and preserves the existing variation file v sv or vhd as lt my_variant gt _ BAK v sv vhd in the project directory Table 1 2 IP Core Upgrade Status IP Core Status Corrective Action Required Upgrade IP You must upgrade the IP variation before compiling in the current version of Components the Quartus II software Optional Upgrade IP Upgrade is optional for this IP variation in the current version of the Quartus Components II software You can upgrade this IP variation to take advantage of the latest development of this IP core Alternatively you can retain previous IP core characteristics by declining to upgrade Upgrade Unsupported Upgrade of the IP variation is not supported in the current version of the Quartus II software due to IP core end of life or incompatibility with the current version of the Quartus II software You are prompted to replace the obsolete IP core with a current equivalent IP core from the IP Catalog Before you begin Archive the Quartus II project containing outdated IP cores in the original version of the Quartus II softwar
112. ed ACCUM SLOAD REG String No Specifies the clock signal for the accum s1oad port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is cLocko This parameter is ignored if the accum sload port is unused ADDNSUB ACLR String No Specifies the asynchronous clear for the addnsub port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default value is AcLRO This parameter is ignored if the addnsub port is unused ADDNSUB_PIPELINE_ACLR String No Specifies the asynchronous clear for the second register on the addnsub port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default value is ACLRO This parameter is ignored if the addnsub port is unused ALTMULT_ACCUM Multiply Accumulate Altera Corporation CJ Send Feedback 8 8 ALTMULT_ACCUM Parameters UG 01063 2014 12 19 ADDNSUB_PIPE String Specifies the clock for the second register on the addnsub port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO This parameter is ignored if the addnsub port is unused ADDNSUB_REG String Specifies the clock for the addnsub port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO This parameter is ignored if the addnsub port is unused
113. ed When the updown port is not connected the LPM DIRECTION parameter default value is up LPM_MODULUS Integer The maximum count plus one Number of unique states in the counter s cycle If the load value is larger than the LPM_MODULUS parameter the behavior of the counter is not specified LPM_AVALUE Integer String Constant value that is loaded when aset is asserted high If the value specified is larger than or equal to lt modulus gt the behavior of the counter is an undefined X logic level where lt modulus gt is LPM_MODULUS if present or 2 LPM_WIDTH Altera recommends that you specify this value as a decimal number for AHDL designs LPM SVALUE Integer String Constant value that is loaded on the rising edge of the clock port when the sset port is asserted high Altera recommends that you specify this value as a decimal number for AHDL designs LPM COUNTER Counter LJ Send Feedback Altera Corporation UG 01063 2 6 Parameters 2014 12 19 PERERIN String When you instantiate a library of parameterized modules LPM function in a VHDL Design File vhd you must use the LPM_HINT parameter to specify an Altera specific parameter For example LPM_HINT CHAIN_SIZE 8 ONE_INPUT_IS_ CONSTANT YES The default value is UNUSED LPM_TYPE String No Identifies the library of parameterized modules LPM enti
114. ed MegaWizard Plug In Manager information with IP Catalog e Added standard information about upgrading IP cores e Added standard installation and licensing information e Removed outdated device support level information IP core device support is now available in IP Catalog and parameter editor June 2015 4 0 e Added ALTERA MULT ADD Multiply Adder on page 6 1 section e Removed the following obsoleted megafunctions LPM ABS ALTACCUMULATE ALTMULT ACCUM ALTMULT_ ADD 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any E inis egistere products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published info
115. eedback UG 01063 2014 12 19 Systolic Delay Register 6 7 N 1 y t B i A t i i 0 N represents the number of cycles of data that has entered into the accumulator y t represents the output at time f A t represents the input at time f and B i are the coefficients The t and i in the equation correspond to a particular instant in time so to compute the output sample y t at time t a group of input samples at N different points in time or A n A n 1 A n 2 A n N 1 is required The group of N input samples are multiplied by N coefficients and summed together to form the final result y The systolic register architecture is available only for sum of 2 and sum of 4 modes The following figure shows the systolic delay register implementation of 2 multipliers Figure 6 8 Systolic Delay Register Implementation of 2 Multipliers chainin a0 MultO Systolic registers b0 g gt Multl al LOH bl gt result The sum of two multipliers is expressed in the following equation y t al f x b1 t a0 t 1 x bO t 1 The following figure shows the systolic delay register implementation of 4 multipliers ALTERA_MULT_ADD Multiply Adder Altera Corporation LJ Send Feedback 6 8 Systolic Delay Register UG 01063 2014 12 19 Figure 6 9 Systolic Delay Register Implementation of 4 Multipli
116. emarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG 01063 10 2 Complex Multiplication 2014 12 19 Figure 10 1 ALTMULT_COMPLEX Ports ALTMULT_COMPLEX dataa_real result_real dataa_imag result_imag datab_real datab_imag clock ena aclr Complex Multiplication Complex numbers are numbers in the form of the following equation a ib Where e aand bare real numbers e iis an imaginary unit that equals the square root of 1 V 1 Two complex numbers x a ib and y c id are multiplied as shown in the following equations Xy a ib c id ac ibc iad bd ac bd i ad bc Related Information Canonical Representation on page 10 2 Canonical Represent
117. ers a0 bO al bl a2 b2 a3 b3 chainin MultO Systolic registers gt Multl chainin gt result Mult2 MENO Q9 gt Mult3 4e gt result The sum of four multipliers is expressed in the following equation Figure 6 10 Sum of 4 Multipliers y t a3 t x b3 t a2 t 1 x b2 t 1 a1 t 22 x b1 t 2 a0 t 3 x b0 t 3 Altera Corporation ALTERA MULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Pre load Constant 6 9 The following lists the advantages of systolic register implementation e Reduces DSP resource usage e Enables efficient mapping in the DSP block using the chain adder structure The systolic delay implementation is only available for the following pre adder modes e Pre adder coefficient mode e Pre adder simple mode e Pre adder constant mode Pre load Constant The pre load constant controls the accumulator operand and complements the accumulator feedback The valid LoaDconst_vaLUE ranges from 0 64 The constant value is equal to 2 where N LOADCONST_VALUE When the LOADCONST_VALUE is set to 64 the constant value is equal to 0 This function can be used as biased rounding
118. erved in this example e The data_in and coeff in input widths are both set to 8 bits e The output port result is set to a width of 16 bits e The initial coefficient is 2 e The output latency is fixed to seven clock cycles based on the input widths set Thefollowing figure shows the expected simulation results in the ModelSim Altera software Figure 7 2 ALTMEMMULT Simulation Results 4 memmult ex vig vec tst clock memmult ex vig vec tstjdata in memmult ex vig vec tsticoeff in 4 memmult ex vig vec tst sload coeff jO 4 jmermtnult ex vig vec tst sload data 4 memmult ex vig vec tstjload done memmult ex vlg vec tstjresult 4 jmemmult ex vig vec tstiresuit valid Sto This design example implements a multiplier for unsigned 8 bit numbers If the value of the MAX CLOCK CYCLES PER RESULT parameter is more than 1 the sload data signal indicates a new multiplication and the result valid signal indicates the validity of the multiplication result If the value of the MAX CLOCK CYCLES PER RESULT parameter is 1 the sload data signal is not used and every positive clock edge starts a new multiplication In this design example with the MAX CLOCK CYCLES PER RESULT parameter set to 4 the design requires no less than four clock cycles to compute the multiplication The sload data signal is used to indicate a new multiplication Altera recommends that you do not pull the sload data signal high during the fo
119. es INPUT REGISTER B0 must have similar values with INPUT REGISTER Bilsa ALTMULT_ADD Multiply Adder CJ Send Feedback Altera Corporation 9 1 ALTMULT_ADD Parameters UG 01063 2014 12 19 red INPUT REGISTER B1 String Specifies the clock port for the datab operand of the second multiplier Values are UNREGIS TERED CLOCKO CLOCK1 CLOCK2 and cLock3 If omitted the default value is cLocko For Stratix III devices the values for INPUT REGISTER B 1 3 must be set similar to the value of INPUT REGISTER BO INPUT REGISTER B2 String No Specifies the clock port for the datab operand of the third multiplier Values are UNREGIS TERED CLOCKO CLOCK1 CLOCK2 and cLock3 If omitted the default value is cLocKo For Stratix III devices the values for INPUT_REGISTER_B 1 3 must be set similar to the value of INPUT_REGISTER_BO INPUT_REGISTER_B3 String No Specifies the clock port for the datab operand of the fourth and corresponding multiplier Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is cLOcKO For Stratix III devices the values for INPUT_ REGISTER_B 1 3 must be set similar to the value of INPUT_ REGISTER_BO INPUT_ACLR_AO String No Spe
120. es are NONE ACLRO ACLR1 If omitted the default value is none The INPUT_ACLR_C 1 3 value must be set similar to the value of INPUT ACLR CO LOADCONST VALU B Integer No Preload constant value to complement accumulator mode Values are 2 N where 0 N 64 PRE ADDE R MODE String Specifies the mode of pre adder settings to be used Values are SIMPLE COEF INPUT SQUARE and consTANT The default value is SIMPLE PR EADD ER DIRECTION COE FFSE L REGISTER String String No Parameter 0 3 Specifies whether the pre adder of the corresponding multiplier adds or subtracts its value from the sum Values are ADD and sus If omitted the default value is ADD Parameter 0 3 Specifies the clock source for the coefficient inputs of the corresponding multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOCK2 The value must be set similar to the value of INPUT_REGISTER_AO or set as UNREGISTERED CO EFFS EL ACLR String No Specifies the asynchronous clear source for the coefficient inputs to the first multiplier Values are none ACLRO and acta If omitted the default value is None The value must be set similar to the value of INPUT_ ACERIAO SYSTOLIC_DELAY1 String Specifies the clock source for the sy
121. esource Utilization and Performance Logic Usage Device family width indiens Look Up Logic 18 bit DSP fmax MHz Table Register ALUT 018 3 481 16 x16 1 0 0 0 4 Stratix III 16 x16 p 0 0 0 4 A81 16 x16 1 0 0 0 4 443 Stratix IV 16 x16 p 0 0 0 4 443 In the Stratix Stratix GX and Arria GX device series the multiplier and the accumulator of the ALTMULT ACCUM megafunction are placed in the DSP block circuitry For Stratix V devices the multiplier blocks and adder accumulator block mac mult and mac out are combined into a single multiplier accumulator MAC block The DSP blocks use the 18 bit x 18 bit input multiplier to process data with widths of up to 18 bits The registers and extra pipeline registers for the following signals are also placed inside the DSP block e Data input e Signed or unsigned select e Add or subtract select e Synchronous load e Products of multipliers In the case of the output result the first register is placed in the DSP block The extra latency registers are placed in logic elements outside the block Cyclone II and Cyclone III devices have embedded multiplier blocks When the ALTMULT_ACCUM megafunction is implemented in Cyclone II and Cyclone III devices the multiplier is implemented in the embedded multiplier blocks while the accumulator is put in LEs In Cyclone devices both the multiplier and accumulator are placed in LEs For more information about
122. ficient Mode Pre adder Input Mode 9 5 Preadder MultO a0 bO H 69 result coefsel0 Pre adder Input Mode coef In this mode one multiplier operand derives from the pre adder and the other operand derives from the datac input port The following settings are applied in this mode The width of the dataa input wrp1 The width of the datab input wID7 The width of the datac input wID7 rH A must be less than or equals to 25 bits rH B must be less than or equals to 25 bits rH C must be less than or equals to 22 bits The number of multipliers must be set to 1 All input registers must be registered with the same clock This mode is expressed in the following equation y a b xc Y The following shows the pre adder input mode of a multiplier Figure 9 4 Pre adder Input Mode a0 MultO bO S result c0 Pre adder Square Mode In this mode both multiplier operands derive from the pre adder The following settings are applied in this mode The width of the dataa input wID7 The width of the datab input wID7 rH A must be less than or equals to 17 bits rH B must be less than or equals to 17 bits The number of multipliers must be set to 2 ALTMULT_ADD Multiply Adder CJ Send Feedback Altera Corporation UG 01063 9 6 Pre adder Constant Mode 20
123. for this parameter DSP BLOCK BALANCING String No If omitted the default value is AUTO DEDICATE D_MULTIPLIE R_CIRCUITRY String No Specifies whether to use the DSP block to implement the circuit Values are YES No and auto The circuit is implemented using the DSP block when the value is set to YES If omitted the default value is AUTO Altera Corporation ALTMULT_ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 ALTMULT_ADD Parameters 9 25 Table 9 8 ALTMULT_ADD Megafunction Parameters Stratix II Stratix Ill and Stratix IV Devices Only red OUTPUT_SATURATE String Specifies the saturation mode Values are SYMMETRIC and ASYMMETRIC A value of SYMMETRIC specifies the absolute value of the maximum negative number equal to the maximum positive number A value of ASYMMETRIC specifies the maximum negative number is larger than the maximum positive number If omitted the default value is ASYMMETRIC WIDTH_SATURATE_SIGN String No _ Specifies the saturation position The value is determined by counting the bits that become the sign bits after saturation Values are calculated according to the following modes wIDTH_a WIDTH_B and WIDTH_RESULT Value must be an unsigned integer If a positive number is unavailable no saturation is allowed in your input output width and mode setting If omitted the default value is 1
124. ft Accumulator Altera Corporation PARALLEL_ADD Parallel Adder C Send Feedback UG 01063 2014 12 19 Understanding the Simulation Results 12 5 This design example uses the LPM_MULT and PARALLEL_ADD megafunctions to generate a shift accumulator This function implements the shift and accumulate operation after the multiplication process in a design block such as a serial FIR filter This example uses the MegaWizard Plug In Manager in the Quartus II software The following design files can be found in parallel_adder_DesignExample zip e shift accum qar archived Quartus II design files e parallel adder ex msim ModelSim Altera files Understanding the Simulation Results The following settings are observed in this example The widths of the input ports dataa and datab are set to 9 bits The width of the output port resultant is set to 10 bits The asynchronous clear ac1x and clock enable clocken input ports are enabled The latency is set to one clock cycle for the multiplier and one clock cycle for the parallel adder resulting in a total output latency of two clock cycles Hence the result is seen on the resultant port two clock cycles after the input data is available The following figure shows the expected simulation results in the ModelSim Altera software Figure 12 2 PARALLEL ADDER Simulation Results 4 shift accum vlg vec tst aclr shift_accum_vig_vec_tst clhen shift_accum_vig_vec_tst cloc
125. g edge of the clock at 17 5 ns the err_detected and err corrected signals are asserted to show that an error is detected and the single bit error is corrected At 20 ns a double bit error in the input code word changes the code word to 14F3 In this case assume that two of the data bits bit 0 and bit 1 are corrupted and are inverted from 0 to 1 This causes the code word to become 14F3 The decoder decodes the code word 14F3 at 20 ns and shows the data F3 at 27 5 ns The ECC decoder performs only SECDED therefore it does not fix the corrupted data that contains double bit errors Instead the err_fatal signal is asserted together with the err_detected signal The following figure shows the effects of the asynchronous clear signal on the registered ports Figure 5 7 Design Example 2 Asynchronous Clear Feature of ECC gt faltecc_decode_vlg_vec_tst aclr jalkecc decode vlg vec tsticlock g jakecc decode vlg vec tstjdata g jalkecc decode vlg vec tstq jakecc decode vlg vec tst err corrected 4 jaltecc decode vlg vec tst err detected jalecc decode vlg vec tst err fatal This figure shows that when the ac1r signal is asserted at 37 5 ns the output and status signals are cleared immediately If you do not want to use the corrupted data when the err_fatal signal is asserted you can assert the asynchronous clear signal ac1x to clear the output port q and other status signals that are registered You must enab
126. g features e Generates a multiplier to perform multiplication operations of two complex numbers e Supports data widths of 1 256 bits e Supports signed and unsigned data representation format e Supports pipelining with configurable output latency Provides a choice of implementation in dedicated DSP block circuitry or logic elements LEs Note When building multipliers larger than the natively supported size there may will be a perform ance impact resulting from the cascading of the DSP blocks e Provides an option to dynamically switch between signed and unsigned data support e Provides an option to dynamically switch between add and subtract operation e Provides an option to set up data shifting register chains e Supports hardware saturation and rounding for selected device families only e Supports optional asynchronous clear and clock enable input ports e Supports systolic delay register mode for Arria V Cyclone V and Stratix V devices only e Supports pre adder with 8 pre load coefficients per multiplier for Arria V Cyclone V and Stratix V devices only e Supports pre load constant to complement accumulator feedback for Arria V Cyclone V and Stratix V devices only e In Arria V Cyclone V and Stratix V devices the pre adder coefficient storage and systolic delay register features are added to maximize flexibility The following sections describe the new features ALTMULT ADD Multiply Adder Altera Corporation LJ
127. hat routing to these blocks is more flexible Fewer multipliers per DSP block allow more routing choices into the block by minimizing paths to the rest of the device The registers and extra pipeline registers for the following signals are also placed inside the DSP block e Data input e Signed or unsigned select e Add or subtract select e Products of multipliers In the case of the output result the first register is placed in the DSP block However the extra latency registers are placed in logic elements outside the block Peripheral to the DSP block including data inputs to the multiplier control signal inputs and outputs of the adder use regular routing to communicate with the rest of the device All connections in the function use dedicated routing inside the DSP block This dedicated routing includes the shift register chains when you select the option to shift a multiplier s registered input data from one multiplier to an adjacent multiplier For more information about DSP blocks in any of the Stratix Stratix GX and Arria GX device series refer to the DSP Blocks chapter of the respective handbooks on the Literature and Technical Documentation page For more information about the embedded memory blocks in any of the Stratix Stratix GX and Arria GX device series refer to the TriMatrix Embedded Memory Blocks chapter of the respective handbooks on the Literature and Technical Documentation page For more information on embedded
128. he latest version IP Upgrade requires the IP core s qip or qsys file within the original Quartus Il generated file structure Displays upgrade o amp 6 e Search status for all IP cores Auto i Entity IP Component Version Device Family Status Description File in the Project pna IP does not support selected X mysdi SDI 131 device family Core mustbe mysdi qip removed from project Double clickto rie 24 mysfi Serial Flash Loader 131 ue to upgrade P nysfi qip individually migrate IP will be converted to use IP F mystp SignalTap Il Logic Analyzer 131 Parameter Editor mystp qip IP will be converted to use IP Checked lPcores B v gt X mytse Triple Speed Ethernet 131 Parameter Editor mytse qip D Release Notes support Auto Upgrade z Double click to upgrade IP Q amp myviterbi Viterbi 131 Lu myviterbi qip Successful 7 E Virtual JTAG 131 IP will be converted to use IP ta ores AT Parameter Editor myra Auto Upgrade naaa Ten 9 ES phyreset Transceiver PHY Reset Controller 14 0 Arria 10 w Success Release Notes phyreset qsys IP does not support selected janine X pipe phy PHY IP Core for PCI Express PIPE 131 device family Core mustbe pipe phy qip pgrade na ail la b le removed from project unavali 4 r Warming Upgrading IP components changes your design files Altera recommends archiving your design before upgrading IP components jrade in Editor Close Archive Hel
129. ications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 11 2 Verilog HDL Prototype Logic Usage UG 01063 2014 12 19 Device family Aaa E s AID piri poe fmax MHz Table ALUT Register Module DLR ALM 8 1 28 0 14 547 Stratix III 20 5 131 0 90 321 30 3 256 0 152 71 8 1 28 0 14 350 Stratix IV 20 5 131 0 94 267 30 3 256 0 154 66 Verilog HDL Prototype The following Verilog HDL prototype is located in the Verilog Design File v altera_mf v in the lt Quartus II installation directory gt eda synthesis directory module altsqrt parameter lpm hint UNUSED parameter lpm type altsqrt parameter pipeline 0 parameter q port width 1 parameter r port width 1 parameter width 1 input wire aclr input wire clk input wire ena output wire q port width 1 0 q input wire width 1 0 radical output wire r port width 1
130. if you do not have sufficient resources to implement the multipliers in logic elements LEs or dedicated multiplier resources The ALTMEMMULT megafunction is a synchronous function that requires a clock The ALTMEMMULT megafunction and the MegaWizard Plug In Manager create a multiplier with the smallest throughput and latency possible for a given set of parameters and specifications The following figure shows the ports for the ALTMEMMULT megafunction Figure 7 1 ALTMEMMULT Ports ALTMEMMULT result sload_data result_valid coeff in load done sload_coeff i selr Features The ALTMEMMULT megafunction offers the following features e Creates only memory based multipliers using on chip memory blocks found in Altera FPGAs e Supports data width of 1 512 bits e Supports signed and unsigned data representation format e Supports pipelining with fixed output latency e Stores multiples constants in random access memory RAM e Provides an option to select the RAM block type e Supports optional synchronous clear and load control input ports O 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as de
131. ifies the asynchronous clear source for the first register on the rotate input Values are ACLRO ACLRI1 ACLR2 and AcLR3 If omitted and ROTATE REGISTER is used the default value is acLR3 ROTATE PIP ELIN F REGIST String Specifies the clock source for the second register on the rotate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO ROTAT E PIPE LINE ACLR String No Specifies the asynchronous clear source for the second register on the rotate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ROTATE_ PIPELINE_REGISTER is used the default value is ACLR3 ROTAT E_OUTPUT_R EGISTER String Specifies the clock source for the third register on the rotate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO Altera Corporation ALTMULT_ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Parameter Name ROTATE_OUTPUT_ACLR ALTMULT_ADD Parameters 9 33 Type Requi Description red String No _ Specifies the asynchronous clear source for the third register on the rotate input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ROTATE_OUTPUT_ REGISTER is used the default value is ACLR3
132. ilar to the value of INPUT_ REGISTER_AO or set as UNREGISTERED CO EFFS EL3 RE GISTE Specifies the clock source for the coefficient inputs of the fourth and corresponding multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOcK2 The value must be set similar to the value of INPUT_ REGISTER_AO or set as UNREGISTERED Altera Corporation ALTMULT_ACCUM Multiply Accumulate C Send Feedback UG 01063 2014 12 19 ALTMULT_ACCUM Parameters 8 17 OEFFS EL A ACLR String Specifies the asynchronous clear source for the coefficient inputs to the first multiplier Values are NONE ACLRO and ACLR1 If omitted and corresponding COEFFSEL REGISTER is used the default value is ACLRO The value must be set similar to the value of INPUT_ ACLR AO COE FFSE L B ACLR String No Specifies the asynchronous clear source for the coefficient inputs to the second multiplier Values are NONE ACLRO and ACIR1 If omitted and corresponding COEFFSEL REGISTER is used the default value is ACLRO The value must be set similar to the value of INPUT_ ACLR AO CO EFFES EL C ACLR String No Specifies the asynchronous clear source for the coefficient inputs to the third multiplier Values are
133. imulation Results 7 7 Figure 7 3 Multiplication with Coefficient of 2 memmult ex vig vec tst clock memmult ex vig vec tst data in Imemmult amp ex vig vec tsticoeff in memmult_ex_vig_vec_tst sload_coeff mermmult_ex_vig_vec_tst sload_data memmult ex vig vec tst load done mernmult amp x vig vec tst result memrmult_ex_vig_vec_tst result_valid Now Cursor 1 The following sequence corresponds with the numbered items in the figure 1 The following sequence corresponds with the numbered items in the figure At 30 ns the sload_data signal asserts and triggers the first multiplication between the data_in value of 3 and the COEFFICIENTO value of 2 The result is sent to the result port seven clock cycles later at 150 ns The result valid signal asserts to indicate that the multiplication is valid 2 At 70 ns the sload_coeff signal asserts to register a new coefficient value of 12 into the register 3 Theload done signal pulls low to begin loading the new value into the memory and pulls high at 170 ns when loading is complete In this example the load time is five clock cycles The following figure shows the simulation results for the multiplication implementation with coefficient of 3 ALTMEMMULT Memory based Constant Coefficient Multiplier Altera Corporation LJ Send Feedback 7 8 Und Y UG 01063 erstanding the Simulation Results 2014 12 19 Figure 7 4 Multiplication with Coefficient of 3 Imemm
134. ing and saturation on the data source before feeding the result to the multiplier INPUT SOURC E BO String No Specifies the data source of the first multiplier Values are DATAB and scans If this parameter is set to DATAB then the adder uses the values from the datab port If this parameter is set to SCANB then the adder uses values from the scan chain If omitted the default value is patas For Stratix II devices a value of VARIABLE is available for the adder to perform rounding and saturation on the data source before feeding the result to the multiplier For Stratix III devices in sum 2 sum of two mode a value of LOOPBACK is available INPUT_SOURC E Bl String No Specifies the data source of the second multiplier Values are DATAB and Scans If this parameter is set to DATAB then the adder uses the values from the datab port If this parameter is set to SCANB then the adder uses values from the scan chain If omitted the default value is DATAB For Stratix II devices a value of VARIABLE is available for the adder to perform rounding and saturation on the data source before feeding the result to the multiplier For Stratix III devices in sum 2 sum of two mode a value of LOOPBACK is available ALTMULT ADD Multiply Adder LJ Send Feedback Altera Corporation 9 2 ALTMULT_ ADD Parameters UG 01063 2014 12 19 red INPUT_SOURCE String Specifies
135. input If both aset and ac1r are used and asserted acir overrides aset If omitted the default value is 0 disabled Asynchronous set input Specifies the q outputs as all 1s or to the value specified by the LpM_AVALUE parameter If both the aset and acir ports are used and asserted the value of the acir port overrides the value of the aset port If omitted the default value is 0 disabled aload Asynchronous load input that asynchronously loads the counter with the value on the data input When the aload port is used the data port must be connected If omitted the default value is 0 disabled sclr No Synchronous clear input that clears the counter on the next active clock edge If both the ssec and scir ports are used and asserted the value of the scr port overrides the value of the sset port If omitted the default value is 0 disabled sset Synchronous set input that sets the counter on the next active clock edge Specifies the value of the q outputs as all 1s or to the value specified by the LpM_sVALUE parameter If both the ssec and sclr ports are used and asserted the value of the sclr port overrides the value of the sset port If omitted the default value is 0 disabled sload Synchronous load input that loads the counter with ata on the next active clock edge When the s1oad port is used the data port must be connected If omitted the default value is 0 disabled
136. input The ac1x1 port is active high Altera Corporation ALTMULT ACCUM Multiply Accumulate C Send Feedback UG 01063 2614115 18 ALTMULT_ACCUM Ports 8 5 aclr2 No The third asynchronous clear input The aclr2 port is active high aclr3 No The fourth asynchronous clear input The ac1x3 port is active high addnsub No Controls the functionality of the adder If the addnsub port is high the adder performs an add function if the addnsub port is low the adder performs a subtract function clock0 No Specifies the first clock input usable by any register in the megafunction clock1 No Specifies the second clock input usable by any register in the megafunction clock2 No Specifies the third clock input usable by any register in the megafunction clock3 No Specifies the fourth clock input usable by any register in the megafunction dataa Yes Data input to the multiplier The size of the input port depends on the wrpTH A parameter value datab Yes Data input to the multiplier The size of the input port depends on the wrpTH B parameter value ena0 No Clock enable for the clocko port enal No Clock enable for the clock1 port ena2 No Clock enable for the clock2 port ena3 No Clock enable for the clock3 port signa No Specifies the numerical representation of the dataa port If the signa port is high the multiplier treats the dataa port as signed two s complemen
137. ion The parameter editor generates the files for your IP variation according to your specifications Click Exit if prompted when generation is complete The parameter editor adds the top level qip file to the current project automatically Note To manually add an IP variation generated with legacy parameter editor to a project click Project Add Remove Files in Project and add the IP variation qip file Files Generated for Altera IP Cores Legacy Parameter Editor The Quartus II software version generates the following output for your IP core that uses the legacy parameter editor Integer Arithmetic Megafunctions Altera Corporation CJ Send Feedback z UG 01063 1 8 Upgrading IP Cores 2014 12 19 Figure 1 6 IP Core Generated Files 71 Project Directory gt your ip qip or qsys System or IP integration file f lt your_ip gt sopcinfo Software tool chain integration file lt your_ip gt IP core variation files your ip bb v Verilog HDL black box EDA synthesis file your ip inst v or vhd Sample instantiation template SLA lt your_ip gt _generation rpt IP generation report lt your_ip gt bsf Block symbol schematic file lt your_ip gt ppf XML 1 0 pin information file lt your_ip gt spd Combines individual simulation startup scripts l lt your_ip gt _syn v or vhd Timing amp resource estimation netlist l 3L
138. ird register on the shift_right input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and sHIFT_ RIGHT OUTPUT REGISTER is used the default value is acLR3 ALTMULT ADD Multiply Adder LJ Send Feedback Altera Corporation 9 3 Design Example Implementing a Simple Finite Impulse Response FIR Filter UG 01063 2014 12 19 red PORT_OUTPUT_IS_OVERF LOW String Specifies port usage Values are PORT_UNUSED and PORT_USED When the value is set to PORT USED output pin overflow is added If omitted the default value is PORT UNUSED PORT CHAINOUT SAT IS OVERFLOW String Specifies port usage Values are PORT UNUSED and PORT USED When the value is set to PORT_ USED Output pin chainout sat overflow is added If omitted the default value is PORT_UNUSED SCANOUTA_REGISTER String Specifies the clock source for the scanouta data bus registers Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is UNREGISTERED SCANOUTA_ACLR CHAINOUT_REGISTER String String Specifies the asynchronous clear source for the scanouta data bus registers Values are NONE ACLRO ACLR1 ACLR2 and ACLR3 If omitted and SCANOUTA_REGISTER is used the default value is ACLR3 Specifies the clock source for the chainout mode result register Th
139. is is an additional stage after the second adder Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocko CHAINOUT ACLR String No Specifies the asynchronous clear for the chainout mode result register This is an additional stage after the second adder Values are NONE ACLRO ACLR1 ACLR2 and ACLR3 If omitted and CHAINOUT_REGISTER is used the default value is ACLR3 Design Example Implementing a Simple Finite Impulse Response FIR Filter Altera Corporation ALTMULT_ADD Multiply Adder G send Feedback UG 01063 2014 12 19 Understanding the Simulation Results 9 35 This design example uses the ALTMULT ADD megafunction to implement a simple FIR filter as shown in the following equation This example uses the MegaWizard Plug In Manager in the Quartus II software n 1 y t Y A t i B i i 0 n represents the number of taps A t represents the sequence of input samples and B i represents the filter coefficients The number of taps n can be any value but this example is of a simple FIR filter with n 4 which is called a 4 tap filter To implement this filter the coefficients of data B is loaded into the B registers in parallel and a shiftin register moves data A 0 to A 1 to A 2 and so on With a 4 tap filter at a given time t the sum of four products is computed This function is implemented using the shift register chain
140. is used instead For a SIGNED multiplier with no inputs being a constant if the setting for MAXIMIZE_SPEED is 9 10 the Compiler optimizes the LPM_MULT megafunction for larger area These settings are for backward compatibility only If the setting is between 6 8 the Compiler optimizes for larger area and higher speed If the setting is between 1 5 the Compiler optimizes for smaller area and high speed If the setting is 0 the smallest and generally slowest design results For designs with LPM_WIDTHB parameters that are non power o 2 the default setting is 1 5 For designs with LPM_WIDTHB parameters that are a power o 2 the default value is 6 8 For an UNSIGNED multiplier with no inputs being a constant if the setting for MAXIMIZE SPEED is 6 or higher the Compiler optimizes for larger area and higher speed If the setting is 0 up to 5 which is the default value the Compiler optimizes for smaller area Note that specifying a value for MAXIMIZE_SPEED has an effect only if LPM_REPRESENTATION is set to SIGNED DEDICATE D_MULTIPLIE TUNES E WIL IIR String No Specifies whether to use the default dedicated multiplier circuitry implementa tion Values are AUTO YES NO and FIRM If omitted the default value is auto For Stratix and Stratix GX devices the value of AUTO specifies that the Quartus
141. ised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 S UG 01063 2 2 Resource Utilization and Performance 2014 12 19 Resource Utilization and Performance The following table provides resource utilization and performance information for the LPM_COUNTER megafunction Table 2 1 LPM COUNTER Resource Utilization and Performance Logic Usage Input data Output Adaptive Dedicated Adaptive Device family width latency Look Up Logic Logic fmax MHz Table ALUT Register Module DLR ALM 4 9 4 6 723 8 9 8 5 808 16 17 16 9 705 Stratix III 24 25 24 13 583 32 33 32 17 489 64 65 64 33 329 4 9 4 6 768 8 9 8 5 896 16 17 16 9 825 Stratix IV 24 25 24 13 716 32 33 32 17 639 64 65 64 33 470 Verilog HDL Prototype The following Verilog HDL prototype is located in the Verilog Design File v Ipm v in the Quartus II installation directory gt eda synthesis directory module lpm_counter q data clock cin cout clk en cnt en updown aset aclr aload sset sclr sload eq parameter lpm type lpm counter parameter lpm width 1 parameter lpm modulus 0 parameter lpm direction UNUSED parameter lpm avalue UNUSED parameter lpm svalue UNUSED paramete
142. ized modules LPM entity name in VHDL design files Design Example Multiplication of 8 bit Complex Numbers Using Canonical Representation This design example uses the ALTMULT COMPLEX megafunction to implement a complex multiplier with an 8 bit input data width using the canonical representation This example uses the MegaWizard Plug In Manager in the Quartus II software The following design files can be found in altmult complex DesignExample zip complex canonical qar archived Quartus II design files altmult complex ex msim ModelSim Altera files Understanding the Simulation Results Altera Corporation ALTMULT COMPLEX Complex Multiplier C Send Feedback UG 01063 2014 12 19 Understanding the Simulation Results 10 9 The following settings are observed in this example e The widths of the data inputs are all set to 8 bits e The widths of the output ports are set to 16 bits e The asynchronous clear acir and clock enable ena signals are enabled e Pipelining is enabled with an output latency of four clock cycles Hence the result is seen on the output ports four clock cycles after the input data is available The following figure shows the expected simulation results in the ModelSim Altera software Figure 10 2 ALTMULT COMPLEX Simulation Results 4 complex canonical vig vec tst clock 4 complex canonical vig vec tst ena jcomplex canonical vig vec tstjacir complex canonical vig vec tstidataa real
143. k jshift accum vig vec tst dataa shift accum vig vec tst dakab shift accum vig vec tst resultant Note At start up an undefined value is seen on the resultant port but this value is merely due to the behavior of the system during start up and hence can be ignored PARALLEL ADD Parallel Adder Altera Corporation LJ Send Feedback Document Revision History 1 3 2014 12 19 UG 01063 GX subscribe Send Feedback The following table lists the revision history for this document Table 13 1 Document Revision History ENTER OR c December 2014 2014 12 19 Removed the LPM ADD SUB and LPM COMPARE IPs because these IPs are no longer supported e Added a note to clarify that when building multipliers larger than the natively supported size there may be a performance impact resulting from the cascading of the DSP blocks in LPM_ MULT ALTERA MULT ADD ALTMULT ACCUM ALTMULT ADD and ALTMULT COMPLEX IP cores e Added information about the Create a sync_e port parameter and the sync e signal for ALTECC_DECODER IP core e Removed sconst port information as the port is no longer available for LPM_COUNTER IP core e Provided an example to use the LPM HINT parameter August 2014 2014 08 18 Updated parameterization steps for legacy and latest parameter editors e Added note for IP cores that do not support Arria 10 designs e Added device migration information June 2014 5 0 e Replac
144. l Values are AUTO CANONICAL and CONVENTIONAL If omitted the default value is Auto When set to auto the Quartus II software determines the best implementation based on the selected device family and input width A value of CANONICAL is available for input widths that are less than 18 bits and for all supported devices except for Stratix III devices A value of CONVENTIONAL is available for all supported device families for all input ranges 1 to 256 bits PIPELINE Integer Yes Specifies the amount of latency in clock cycles needed to produce the result Values are 0 14 If omitted the default value is 4 If the value of IMPLEMENTATION_STYLE is CANONICAL the maximum value of PIPELINE is 14 and if the value of the IMPLEMENTA TION_STYLE parameter is CONVENTIONAL the maximum value of PIPELINE is 11 REPRESENTATION_A String Yes Specifies the number representation of data a Values are UNSIGNED and SIGNED If omitted the default value is UNSIGNED The data a inputs are interpreted as unsigned numbers when the value is set to UNSIGNED and as two s complement when the value is set to SIGNED REPRESENTATION_B String Yes Specifies the number representation of data B Values are UNSIGNED and SIGNED If omitted the default value is UNSIGNED The data B inputs are inte
145. lated Information Altera IP Release Notes Migrating IP Cores to a Different Device IP migration allows you to target the latest device families with IP originally generated for a different device Some Altera IP cores require individual migration to upgrade The Upgrade IP Components dialog box prompts you to double click IP cores that require individual migration 1 To display IP cores requiring migration click Project gt Upgrade IP Components The Description field prompts you to double click IP cores that require individual migration Double click the IP core name and then click OK after reading the information panel The parameter editor appears showing the original IP core parameters For the Currently selected device family turn off Match project default and then select the new target device family Click Finish and then click Finish again to migrate the IP variation using best effort mapping to new parameters and settings Click OK if you are prompted that the IP core is unsupported for the current device A new parameter editor opens displaying best effort mapped parameters Click Generate HDL and then confirm the Synthesis and Simulation file options Verilog is the parameter editor default HDL for synthesis files If your original IP core was generated for VHDL select VHDL to retain the original output HDL format To regenerate the new IP variation for the new target device click Generate When genera
146. le bit or double bit error 2 In this case the syndrome code is zero S5 S4S3S2S1 0 0000 No error is detected and no correction Altera Corporation ALTECC Error Correction Code Encoder Decoder C Send Feedback UG 01063 2014 12 19 Cursor 1 37 5ns Understanding the Simulation Results 5 15 is needed on the retrieved data FO DBD7D6D5D4D3D2D1 1111 0000 based on the generated syndrome code Therefore the flag signals ex detected err corrected and err fatal are deasserted indicating that the data is not corrupted The decoding for 14F0 is FO 1111 0000 in binary Note Even if the generated syndrome code indicates a single bit error the err_detected and err corrected signals are asserted only if the corrupted bit is from the data bits and not from the parity bits At 10 ns a single bit error occurred in the input code word that changes the code word to 14F1 In this case assume that one of the data bits the LSB is corrupted and is inverted from 0 to 1 This causes the code word to become 14F1 With the same method of decoding using the Hamming Code scheme the generated syndrome code is 1 0011 S5 equals to 1 single error detected and S4S3S251 equals to 0011 the bit at position 3 is corrupted Because only one of the data bits is corrupted the decoder is able to correct it by flipping the error bit Therefore the corrupted data F1 is decoded as FO When FO is shown at the output port at the next risin
147. le the pipelining option in the MegaWizard Plug In Manager to use this feature ALTECC Error Correction Code Encoder Decoder Altera Corporation C Send Feedback ALTERA_MULT_ADD Multiply Adder 2014 12 19 UG 01063 GX subscribe _ Send Feedback The ALTERA MULT ADD megafunction allows you to implement a multiplier adder The following figure shows the ports for the ALTERA MULT ADD megafunction Figure 6 1 ALTERA MULT ADD Ports ALTERA MULT ADD dataa signa scanouta datab result i signb datac coefselO coefsell coefsel2 coefsel3 addnsubl addnsub3 aclr scanina clock0 clock1 clock2 enaO enal ena2 sload_accum accum_sload chainin inst A multiplier adder accepts pairs of inputs multiplies the values together and then adds to or subtracts from the products of all other pairs The ALTERA MULT ADD megafunction also offers many variations in dedicated DSP block circuitry Data input sizes of up to 18 bits are accepted Because the DSP blocks allow for one or two levels of 2 input add or subtract operations on the product this function creates up to four multipliers 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as
148. lier L3 Send Feedback UG 01063 2014 12 19 VHDL Component Declaration 4 3 input lpm_widths 1 0 sum output lpm_widthp 1 0 result endmodule VHDL Component Declaration The VHDL component declaration is located in the VHDL Design File vhd LPM_PACK vhd in the Quartus II installation directory gt libraries vhdl lpm directory component LPM_MULT generic LPM_WIDTHA natural LPM_WIDTHB natural LPM_WIDTHS natural 1 LPM_WIDTHP natural LPM REPRESENTATION string UNSIGNED LPM_PIPELINE natural 0 LPM_TYPE string L_MULT LPM_HINT string UNUSED port DATAA in std logic vector LPM WIDTHA 1 downto 0 DATAB in std logic vector LPM WIDTHB 1 downto 0 ACLR in std logic 0 CLOCK in std logic ngrys CEKEN in std logic z rT SUM in std logic vector LPM WIDTHS 1 downto 0 OTHERS gt 0 RESULT out std logic vector LPM WIDTHP 1 downto 0 end component VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY lpm USE lpm lpm components all LPM MULT Ports Table 4 2 LPM MULT IP Core Input Ports dataa Yes Data input The size of the input port depends on the LPM_ WIDTHA parameter value datab Yes Data input The size of the input port depends on the LPM_ WIDTHB parameter value clock
149. lier configuration in the DSP block If not the DSP block uses 18 x 18 bit input multipliers to process data with widths between 10 bits and 18 bits If multiple ALTMULT_ADD megafunctions occur in a design the functions are distributed to as many different DSP blocks as possible so that routing to these blocks is more flexible Fewer multipliers per DSP block allow more routing choices into the block by minimizing paths to the rest of the device The registers and extra pipeline registers for the following signals are also placed inside the DSP block e Data input e Signed or unsigned select e Add or subtract select e Products of multipliers In the case of the output result the first register is placed in the DSP block However the extra latency registers are placed in logic elements outside the block Peripheral to the DSP block including data inputs to the multiplier control signal inputs and outputs of the adder use regular routing to communicate with the rest of the device All connections in the function use dedicated routing inside the DSP block This dedicated routing includes the shift register chains when you select the option to shift a multiplier s registered input data from one multiplier to an adjacent multiplier For more information about implementing multipliers using DSP and memory blocks in Altera FPGAs refer to AN 306 Implementing Multipliers in FPGA Devices Features The ALTMULT_ADD megafunction offers the followin
150. lls the lowest bit position In this case starting from the LSB of the data FO 1111 0000 in binary fills the empty bit positions starting from position 3 as shown in the following table Table 5 14 Design Example 2 Filling of Data Bits 1111 0000 for a 13 Bit Code Word eo EA a ee a ISO GERM EE SSH LER Y Parity Bits and Data Bits e Recalculate parity bits to generate the syndrome code Each syndrome bit calculates the parity even parity for some of the bits in the code word The following table lists how the syndrome bits are derived Table 5 15 Design Example 2 Calculation of Parity Bits Leven Dov Do boo Do Lo Df ovo london oo Parity Bits Syndrome and Data 6 og 1a oc amp e oe a a Pe a ai m Bits Calculate 0 0 0 0 1 1 S1 0 Pl Calculate 0 0 0 0 1 1 S2 0 P2 Calculate 1 0 0 0 1 S320 P3 Calculate 0 1 1 1 1 S4 0 P4 Calculate 0 0 0 1 0 0 0 0 1 1 1 1 S5 0 P5 e Calculate the additional syndrome bit using an even parity checking on all the bits in the code word In this example the additional syndrome bit S5 is calculated using an even parity checking on all the bits from position 1 to position 13 as shown in the table The generated syndrome code gives the status of the data whether an error has occurred and if so whether it is a sing
151. lowing table lists the parameters for the ALTMULT_ACCUM megafunction Table 8 5 ALTMULT_ACCUM Megafunction Parameters ACCUM_DIRECTION String Specifies whether the accumulator performs an add or subtract function Values are ADD and sus When this parameter is set to app the accumulator adds the product to the current accumulator value When this parameter is set to SUB the accumulator subtracts the product from the current accumulator value If omitted the default value is App This parameter is ignored if the addnsub port is used ACCUM SLOAD ACLR Specifies the asynchronous clear signal for the accun sload port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default value is ACLR3 This parameter is ignored if the accum s1oad port is unused Altera Corporation ALTMULT ACCUM Multiply Accumulate C Send Feedback UG 01063 ACCUM_SLOAD_PIPELINE_ACLR String Specifies the asynchronous clear signal for the second register on the accum_sload port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default value is ACLR3 This parameter is ignored if the accum_sload port is unused ACCUM SLOAD PIPELINE REG String No Specifies the clock signal for the second register on the accum sload port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO This parameter is ignored if the accum s1oad port is unus
152. ltiplier treats the datab port as an unsigned number Table 9 3 ALTMULT ADD Megafunction Input Ports Stratix Ill and Stratix IV Devices Only Ports Available in Stratix III and Stratix IV devices only Altera Corporation ALTMULT ADD Multiply Adder G send Feedback UG 01063 2014 12 19 ALTMULT_ADD Ports 9 13 output_round No Enables dynamically controlled output rounding When ouTPuT_ ROUNDING is set to VARIABLE output round enables the final adder stage of rounding output saturate No Enables dynamically controlled output saturation When ouTPuT_ SATURATION is set to VARIABLE output saturate enables the final adder stage of saturation chainout round No Enables dynamically controlled cnainout stage rounding When CHAINOUT ROUNDING is set to VARIABLE chainout round enables the chainout stage of rounding chainout saturate No Enables dynamically controlled cnainout stage saturation When CHAINOUT SATURATION is set to VARIABLE chainout saturate enables the chainout stage of saturation zero chainout No Dynamically specifies whether the cnainout value is zero zero loopback No Dynamically specifies whether the loopback value is zero accum sload No Dynamically specifies whether the accumulator value is zero chainin No Adder result input bus from the preceding stage Input port WIDTH CHAININ 1 0 wide rotate No Specifies dynamically controlled port rotation in shift mode
153. lues are DATAA and scana If this parameter is set to pATAA the adder uses the values from the dataa port If this parameter is set to SCANA the adder uses values from the scan chain If omitted the default value is DATAA For Stratix II devices a value of VARIABLE is available for the adder to perform rounding and saturation on the data source before feeding the result to the multiplier INPUT SOURC E A2 String No Specifies the data source to the third multiplier Values are DATAA and scana If this parameter is set to DATAA the adder uses the values from the dataa port If this parameter is set to scana the adder uses values from the scan chain If omitted the default value is DATAA For Stratix II devices a value of VARIABLE is available for the adder to perform rounding and saturation on the data source before feeding the result to the multiplier Altera Corporation ALTMULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 ALTMULT_ADD Parameters 9 1 red INPUT_SOURCE String Specifies the data source to the fourth and corresponding multiplier Values are pataa and SCANA If this parameter is set to DATAA the adder uses the values from the dataa port If this parameter is set to SCANA the adder uses values from the scan chain If omitted the default value is DATA For Stratix II devices a value of vaR1ABLE is available for the adder to perform round
154. mf directory component altmult complex generic intended device family string unused implementation style string AUTO pipeline natural 4 representation a string SIGNED representation b string SIGNED width a natural width b natural width result natural lpm hint string UNUSED lpm type string altmult complex port aclr in std logic 0 clock in std logic 0 complex in std logic 1 width a 1 downto width a 1 downto width b 1 downto width b 1 downto dataa imag in std logic vector dataa real in std logic vector datab imag in std logic vector datab real in std logic vector ena in std logic 1 result imag out std logic vector width result 1 downto 0 result real out std logic vector width result 1 downto 0 end component Nee 0 0 0 0 VHDL LIBRARY_USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY altera_mf USE altera_mf altera_mf_components all ALTMULT_COMPLEX Complex Multiplier Altera Corporation CJ Send Feedback 10 6 ALTMULT_COMPLEX Ports ALTMULT_COMPLEX Ports UG 01063 2014 12 19 Table 10 2 ALTMULT_COMPLEX IP Core Input Ports aclr No Asynchronous clear for the complex multiplier When the aclr port is asserted high the function is asynchronously cleared clock Yes Clock input to the ALTMULT_COMPLEX function dataa
155. multiplier blocks in the Cyclone II and Cyclone III devices refer to the DSP Blocks chapter of the respective handbooks on the Literature and Technical Documentation page For more information about implementing multipliers using DSP and memory blocks in Altera FPGAs refer to AN 306 Implementing Multipliers in FPGA Devices Features The ALTERA_MULT_ADD megafunction offers the following features e Generates a multiplier to perform multiplication operations of two complex numbers Note When building multipliers larger than the natively supported size there may will be a perform ance impact resulting from the cascading of the DSP blocks e Supports data widths of 1 256 bits e Supports signed and unsigned data representation format e Supports pipelining with configurable output latency e Provides an option to dynamically switch between signed and unsigned data support Altera Corporation ALTERA MULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Pre adder 6 3 Provides an option to dynamically switch between add and subtract operation Supports optional asynchronous clear and clock enable input ports Supports systolic delay register mode Supports pre adder with 8 pre load coefficients per multiplier Supports pre load constant to complement accumulator feedback Pre adder coefficient storage and systolic delay register features are added to maximize flexibility Pre adder With pre adder additions or subtractions
156. n the natively supported size there may will be a perform ance impact resulting from the cascading of the DSP blocks e Provides an option to dynamically switch between add and subtract operations in the accumulator e Provides an option to dynamically switch between signed and unsigned data support e Provides an option to set up data shift register chains e Supports hardware saturation and rounding for Stratix III and Stratix IV devices only e Supports optional asynchronous clear and clock enable input ports e Supports systolic delay register mode for Arria V Cyclone V and Stratix V devices only e Supports pre adder with 8 coefficients per multiplier for Arria V Cyclone V and Stratix V devices only e Supports pre load constant to complement accumulator feedback for Arria V Cyclone V and Stratix V devices only Refer to the following megafunctions in this user guide for other multiplier implementations e Multiplier Adder Megafunction ALTMULT ADD e Memory based Constant Coefficient Multiplier ALTMEMMULT Memory based Constant Coefficient Multiplier e Multiplier Megafunction LPM MULT Multiplier Resource Utilization and Performance The following table provides resource utilization and performance information for the ALTMULT ACCUM megafunction Altera Corporation ALTMULT ACCUM Multiply Accumulate C Send Feedback UG 01063 ve tk 2014 12 19 Resource Utilization and Performance 8 3 Table 8 1 ALTMULT_ACCUM R
157. nchronous clear input The active high acir signal can be used at any time to asynchronously clear the registers Table 5 6 ALTECC_DECODER Megafunction Output Ports qi Yes Decoded data output port The size of the output port depends on the WIDTH DATAWORD parameter value err detected Yes Flag signal to reflect the status of data received and specifies any errors found err corrected Yes Flag signal to reflect the status of data received Denotes single bit error found and corrected You can use the data because it has already been corrected err fatal Yes Flag signal to reflect the status of data received Denotes double bit error found but not corrected You must not use the data if this signal is asserted syn e No An output signal which will go high whenever a single bit error is detected on the parity bits Parameters ALTECC ENCODER The following table lists the parameters for the ALTECC ENCODER megafunction Table 5 7 ALTECC ENCODER Megafunction Parameters TH DATAWORD Integer Specifies the width of the raw data Values are from 2 to 64 If omitted the default value is 8 WIDTH CODEWORD Integer Yes Specifies the width of the corresponding code word Valid values are from 6 to 72 excluding 9 17 33 and 65 If omitted the default value is 13 LPM PIPELINE Integer No Specifies the pipeline for the circuit Values are from 0 to 2 If the value i
158. nd CHAINOUT SATURATE OUTPUT REGISTER is used the default value is ACLR3 N ERO CHAINOUT OUTPUT REGISTER String No Specifies the clock source for the first register on the zero_ chainout input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocko N ERO_CHAINOUT_OUTPUT_ACLR String Specifies the asynchronous clear source for the first register on the zero_chainout input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and zERO_CHAINOUT_ OUTPUT_ REGISTER is used the default value is AcLR3 LH N N ERO_LOOPBACK_REGISTER ERO_LOOPBACK_ACLR String String No Specifies the clock source for the first register on the zero_ loopback input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocko Specifies the asynchronous clear source for the first register on the zero loopback input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and ZERO_LOOPBACK_ PIPELINE REGISTER is used the default value is ACLR3 N ERO_LOOPBACK_PIPELINE_REGISTER String No Specifies the clock source for the second register on the zero_ loopback input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If omitted the default value is cLocko
159. ne 0 parameter width codeword 8 parameter width dataword 8 parameter lpm type altecc encoder parameter lpm hint unused input wire aclr input wire clock input wire clocken input wire width dataword 1 0 data output wire width codeword 1 0 q endmodule Verilog HDL Prototype ALTECC DECODER ALTECC Error Correction Code Encoder Decoder Altera Corporation C Send Feedback 5 6 VHDL Component Declaration ALTECC_ENCODER The following Verilog HDL prototype is located in the Verilog Design File v Ipm v in the Quartus II installation directory gt eda synthesis directory module altecc_decoder parameter intended_device_family unused parameter lpm_pipeline 0 parameter width_codeword 8 parameter width_dataword 8 parameter lpm_type altecc_decoder parameter lpm_hint unused input wire aclr input wire clock input wire clocken input wire width_codeword 1 0 data output wire err_corrected output wire err_detected outut wire err_fatal output wire width_dataword 1 0 q endmodule VHDL Component Declaration ALTECC_ENCODER The VHDL component declaration is located in the VHDL Design File vhd altera_mf_components vhd in the lt Quartus II installation directory gt libraries vhdl altera_mf directory component altecc_encoder generic intended_device_family string unused lpm_pipeline natural 0 width_codeword natu
160. nformation about specific IP core parameters e Optionally select preset parameter values if provided for your IP core Presets specify initial parameter values for specific applications e Specify parameters defining the IP core functionality port configurations and device specific features e Specify options for processing the IP core files in other EDA tools 4 Click Generate HDL the Generation dialog box appears 5 Specify output file generation options and then click Generate The IP variation files generate according to your specifications 6 To generate a simulation testbench click Generate gt Generate Testbench System 7 To generate an HDL instantiation template that you can copy and paste into your text editor click Generate gt HDL Example 8 Click Finish The parameter editor adds the top level qsys file to the current project automatically If you are prompted to manually add the qsys file to the project click Project gt Add Remove Files in Project to add the file 9 After generating and instantiating your IP variation make appropriate pin assignments to connect ports Integer Arithmetic Megafunctions Altera Corporation C Send Feedback 1 6 Specifying IP Core Parameters and Options Legacy Parameter Editors Figure 1 4 IP Parameter Editor A IP Parameter Editor unnamed qsys users jbrossar unnamed 4sys File Edit System Generate View Tools Help E Parameters unsaved gt altclkctri_O
161. o Active high clock enable input port clk No Clock input port that provides pipelined operation for the ALTSORT megafunction For the values of PIPELINE parameter other than 0 default value the clock port must be connected aclr No Asynchronous clear input port that can be used at any time to reset the pipeline to all os asynchronously to the clock signal Table 11 2 ALTSQRT Megafunction Output Ports remainder Yes The square root of the radical The size of the remainder port depends on the R_PORT_WIDTH parameter value qt Yes Data output The size of the qt port depends on the 9_PORT_WIDTH parameter value Parameters The following table lists the Preces for the ALTSQRT megafunction WIDTH Integer Specifies the widths of the xaaical input port Q PORT WIDTH Integer Yes Specifies the width of the q output port ALTSQRT Integer Square Root Altera Corporation C Send Feedback UG 01063 11 4 Design Example 9 bit Square Root 2014 12 19 R_PORT_WIDTH Integer Yes Specifies the width of the remainder output port PIPELINE Integer No Specifies the number of clock cycles of latency to add le String No When you instantiate a library of parameterized modules LPM function in a VHDL Design File vhd you must use the LPM_HINT parameter to specify an Altera specific parameter For example LPM HINT CHAIN SIZE 8 ONE INPUT IS CONSTANT YES
162. ock err_detected clocken err_corrected err fatal ALTECC ENCODER Features The ALTECC ENCODER megafunction offers the following features e Performs data encoding using the Hamming Coding scheme e Supports data width of 2 64 bits e Supports signed and unsigned data representation format e Support pipelining with output latency of either one or two clock cycles e Supports optional asynchronous clear and clock enable ports The ALTECC ENCODER megafunction takes in and encodes the data using the Hamming Coding scheme The Hamming Coding scheme derives the parity bits and appends them to the original data to produce the output code word The number of parity bits appended depends on the width of the data The following table lists the number of parity bits appended for different ranges of data widths The Total Bits column represents the total number of input data bits and appended parity bits Table 5 1 Number of Parity Bits and Code Word According to Data Width Data Width Number of Parity Bits Total Bits Code Word 2 4 341 6 8 5 11 441 10 16 12 26 541 18 32 Altera Corporation ALTECC Error Correction Code Encoder Decoder C Send Feedback ese 9 Resource Utilization and Performance 5 3 27 57 6 1 34 64 58 64 7 1 66 72 The parity bit derivation uses an even parity checking The additional 1 bit shown in tthe table as 1 is appended to the parity bits as the MSB of the code word This ensures that the code
163. onous clear for the datab operand of the second multiplier Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding INPUT_REGISTER_B is used the default value is ACLR3 INPUT_ACLR_B2 String Specifies the asynchronous clear for the datab operand of the third multiplier Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and corresponding INPUT REGISTER B is used the default value is ACLR3 INPUT_ACLR_B3 String Specifies the asynchronous clear for the datab operand of the fourth and corresponding multiplier Values are ACLRO ACLRI1 ACLR2 and AcLR3 If omitted and corresponding INPUT_REGISTER_B is used the default value is ACLR3 ALTMULT_ADD Multiply Adder CJ Send Feedback Altera Corporation 9 1 ALTMULT_ ADD Parameters UG 01063 2014 12 19 red INPUT_SOURCE String Specifies the data source to the first multiplier Values are DATAA and scana If this parameter is set to DATAA the adder uses the values from the dataa port If this parameter is set to scana the adder uses values from the scan chain If omitted the default value is DATAA For Stratix II devices a value of VARIABLE is available for the adder to perform rounding and saturation on the data source before feeding the result to the multiplier INPUT SOURC E A1 String No Specifies the data source to the second multiplier Va
164. operand of the multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOCK2 If omitted the default value is UNREGISTERED INPUT REGISTER A 1 3 must have similar values with INPUT_ REGISTER AQ Specifies the clock port for the aatab operand of the multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOCK2 If omitted the default value is UNREGISTERED INPUT_REGISTER_B 1 3 must have similar values with INPUT_ REGISTER_BO INPUT_ACLR_A 0 3 String No Specifies the asynchronous clear for the dataa operand of the multiplier Values are NONE ACLRO ACLR1 If omitted the default value is none The INPUT ACLR A 1 3 value must be set similar to the value of INPUT ACLR AO TNEUTEACCRER OTS String No Specifies the asynchronous clear for the datab operand of the multiplier Values are NONE ACLRO ACLR1 If omitted the default value is none The INPUT_ACLR_B 1 3 value must be set similar to the value of INPUT ACLR BO Altera Corporation ALTERA MULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 ALTERA_MULT_ADD Parameters 6 13 INPUT_SOURCE String Specifies the data source to the first multiplier Values are pATAA and scana If this parameter is set to DATA the adder uses the values from the dataa port If this parameter is set to scana the adde
165. option in the ALTMULT ADD megafunction With reference to the equation input B represents the coefficients and data A represents the data that is shifted into The A input data is shifted in with the main clock named clocko The B input coefficients is loaded at the rising edge of c1ock1 with the enable signal held high The following design files can be found in altmult add DesignExample zip fir fourtap qar archived Quartus II design files altmult add ex msim ModelSim Altera files Understanding the Simulation Results The following settings are observed in this example e The widths of the data inputs are all set to 16 bits e The width of the output port result is set to 34 bits e The input registers are all operating on the same clock The following figure shows the expected simulation results in the ModelSim Altera software ALTMULT ADD Multiply Adder Altera Corporation LJ Send Feedback UG 01063 9 36 Understanding the Simulation Results 2014 12 19 Figure 9 13 ALTMULT ADD Simulation Results Ifir fourtap vig vec tst clock fir fourtap vig vec tst dataa 0 Ifi fourtap vig vec tst datab 0 fir fourtap vlg vec tst datab 1 Ifir Fourtap vig vec tstidatab 2 fir_Fourtap_vig_vec_tst datab_3 fir fourtap vlg vec tst ena lfir Fourtap vlg vec tst signa lfir Fourtap vlg vec tst signb lfir Fourtap vlg vec tst result 2000 ns Cursor 1 200ns IE N NN UN NET ET Altera Corporation ALTMULT ADD
166. ototype is located in the Verilog Design File v in the lt Quartus II installa tion directory gt eda synthesis directory VHDL Component Declaration The VHDL component declaration is located in the VHDL Design File vhd in the lt Quartus II installa tion directory gt directory VHDL LIBRARY_USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY altera_mf USE altera_mf altera_mf_components all Ports The following tables list the input and output ports of the ALTERA_MULT_ADD megafunction Table 6 1 ALTERA_MULT_ADD MegaFunction Input Ports dataa Yes Data input to the multiplier Input port NUMBER OF MULTIPLIERS WIDTH A 1 0 wide Altera Corporation ALTERA MULT ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 Ports 6 11 datab Yes Data input to the multiplier Input port NUMBER OF MULTIPLIERS WIDTH B 1 0 wide datac No Data input to the multiplier Input port NUMBER OF MULTIPLIERS WIDTH C 1 0 wide GLO Clock input port 0 2 to the corresponding register This port can be used by any register in the megafunction aclr ena Input port 0 1 Asynchronous clear input to the corresponding register Input port 0 2 Enable signal input to the corresponding register signa Specifies the numerical represent
167. p Perform Automatic upgrade Jpg gt T Upgrades all IP core that support Auto Upgrade Upgrades individual IP cores unsupported by Auto Upgrade Example 1 1 Upgrading IP Cores at the Command Line You can upgrade IP cores that support auto upgrade at the command line IP cores that do not support automatic upgrade do not support command line upgrade To upgrade a single IP core that supports auto upgrade type the following command quartus sh ip upgrade variation files my ip filepath my ip hdl qii project Example quartus sh ip upgrade variation files mega pll25 v hps testx To simultaneously upgrade multiple IP cores that support auto upgrade type the following command quartus sh ip upgrade variation files my ip filepath my ipl hdl my ip filepath my ip2 5 hdl qii project Example quartus sh ip upgrade variation files mega pll tx2 v mega pll3 v hps testx Note IP cores older than Quartus II software version 12 0 do not support upgrade Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core The Altera IP Release Notes reports any verifica tion exceptions for Altera IP cores Altera does not verify compilation for IP cores older than the previous two releases Altera Corporation Integer Arithmetic Megafunctions C Send Feedback UG 01063 2014 12 19 Migrating IP Cores to a Different Device 1 11 Re
168. pecifies the clock signal for the first register on the corresponding sign port Values are UNREGISTERED CLOCKO CLOCK1 and cLock2 If the corresponding sign port value is UNUSED this parameter is ignored If omitted the default value is UNREGISTERED The value must be set similar to the value of INPUT_ REGISTER A0 Or set as UNREGISTERED Altera Corporation 6 14 ALTERA_MULT_ADD Parameters UG 01063 2014 12 19 SIGNED_ACLR_ String Parameter A B Specifies the asynchro nous clear signal for the first register on the corresponding sign port Values are NONE ACLRO and acrni If omitted the default value is none The value must be set similar to the value of INPUT_ACLR_AO X MULTIPLIER REGISTER String Parameter 0 3 Specifies the clock source of the register that follows the corresponding multiplier Values are UNREGISTERED CLOCKO CLOCK1 and crock2 If omitted the default value is UNREGISTERED MULTIPLIER ACLR String Parameter 0 3 Specifies the asynchronous clear signal of the register that follows the corresponding multiplier Values are NONE ACLRO and ACLR1 If omitted the default value is NONE MULTIPLIER1_DIRE CTION MULTIPLIER3_DIRE CTION String String Specifies whether the second multiplier adds or subtr
169. pends on the WIDTH_D parameter value sclr No Synchronous clear input If unused the default value is active high ALTMEMMULT Memory based Constant Coefficient Multiplier LJ Send Feedback Altera Corporation 7 4 Parameters UG 01063 2014 12 19 sel No Fixed coefficient selection The size of the input port depends on the WIDTH_S parameter value sload_coeff No Synchronous load coefficient input port Replaces the current selected coefficient value with the value specified in the coeff_in input sload_data No Synchronous load data input port Signal that specifies new multiplication operation and cancels any existing multiplication operation If the MAx CLOCK CYCLES PER RESULT parameter has a value of 1 the s1oad data input port is ignored Table 7 3 ALTMEMMULT Megafunction Output Ports result Yes Multiplier output port The size of the input port depends on the WIDTH R parameter value result valid Yes Indicates when the output is the valid result of a complete multipli cation If the xAx CLOCK CYCLES PER RESULT parameter has a value of 1 the result valid output port is not used load done No Indicates when the new coefficient has finished loading The load_ done signal asserts when a new coefficient has finished loading Unless the 10ad done signal is high no other coefficient value can be loaded into the memory Parameters The following
170. r A multiplier accumulator can be used to implement FIR filters This design example uses the ALTMULT_ACCUM megafunction to implement a serial FIR filter in which both the data and coefficient are shifted serially into the multiplier and then summed in the accumulator This example uses the MegaWizard Plug In Manager in the Quartus II software The following design files can be found in altmult_accum_DesignExample zip serial_fir qar archived Quartus II design files altmult accum ex msim ModelSim Altera files Understanding the Simulation Results The following settings are observed in this example e The dataa and datab input widths are both set to 16 bits The output port result is set to a width of 33 bits e The accum sload input is enabled The following figure shows the expected simulation results in the ModelSim Altera software ALTMULT ACCUM Multiply Accumulate J send Feedback Altera Corporation Y UG 01063 8 20 Understanding the Simulation Results 2014 12 19 Figure 8 2 ALTMULT_ACCUM Simulation Results 4 serial_fr_vig_vec_tsticiokd 4 serial_fir_vig_vec_tstiaccum_sload 4 serial_fir_vig_vec_tstidataa serial fir vig vec tstidatab MEL A RN d Ad Cursor 1 Altera Corporation ALTMULT ACCUM Multiply Accumulate C Send Feedback ALTMULT_ADD Multiply Adder 2014 12 19 UG 01063 GX subscribe C Send Feedback The ALTMULT ADD megafunction allows you to implement a multiplier ad
171. r Altera Corporation LJ Send Feedback 9 2 ALTMULT_ADD Parameters UG 01063 2014 12 19 red SIGNED PIPELINE REGISTER String Parameter A B Specifies the clock eal for the second register on the corresponding sign port Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and cLocx3 If the corresponding sign port value is UNUSED this parameter is ignored If omitted the default value is CLOCKO SIGNED ACLR String No Parameter A B Specifies the asynchronous clear signal for the first register on the corresponding sign port Values are NONE ACLRO ACLR1 ACLR2 and AcLR3 If omitted and corresponding SIGNED REGISTER is used the default value is ACLR3 SIGNED PIPELINE ACLR String No Parameter A B Specifies the asynchronous clear signal for the second register on the corresponding sign port Values are NONE ACLRO ACLR1 ACLR2 and ACLR3 If omitted and the corresponding SIGNED PIPELINE REGISTER is used the default value is acLR3 MULTIPLIER REGISTER String No Parameter Specifies the clock source a register that follows the corresponding multiplier Values are UNREGIS TERED CLOCK0 CLOCK1 CLOCK2 and crocxa3 If omitted the default value is CLOCKO MULTIPLIER ACLR String No Parameter Specifies the
172. r lpm pvalue UNUSED parameter lpm port updown PORT CONNECTIVITY parameter lpm hint UNUSED output lpm width 1 0 q 0 The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column Altera Corporation LPM COUNTER Counter C Send Feedback UG 01063 2014 12 19 output output input input input input input endmodu VHDL Component Declaration 2 3 cout 15 0 eq cin lpm_width 1 0 data clock clk_en cnt_en updown aset aclr aload sset sclr sload le VHDL Component Declaration The VHDL component declaration is located in the VHDL Design File vhd LPM_PACK vhd in the lt Quartus II installation directory gt libraries vhd lpm directory component LPM_MULT generic LPM_WIDTHA natural LPM_WIDTHB natural LPM_WIDTHS natural 1 LPM_WIDTHP natural LPM_REPRESENTATION string UNSIGNED LPM_PIPELINE natural 0 LPM_TYPE string L_MULT LPM HINT string UNUSED port DATAA in std logic vector LPM WIDTHA 1 downto 0 DATAB in std logic vector LPM WIDTHB 1 downto 0 ACLR in std logic 0 CLOCK in std logic 0 CLKEN in std logic 1 SUM in std logic vector LPM WIDTHS 1 downto 0 OTHERS gt 0 RESULT out std logic vector LPM W
173. r than the natively supported size there may will be a perform ance impact resulting from the cascading of the DSP blocks e Supports data width of 1 256 bits e Supports signed and unsigned data representation format e Supports canonical and conventional implementation modes e Supports pipelining with configurable output latency e Supports optional asynchronous clear and clock enable input ports Provides an option to dynamically switch between 36 x 36 normal mode and 18 x 18 complex mode for Stratix V devices only ALTMULT COMPLEX Complex Multiplier Altera Corporation LJ Send Feedback E UG 01063 10 4 Resource Utilization and Performance 2014 12 19 Resource Utilization and Performance The following table provides resource utilization and performance information for the ALTMULT COMPLEX megafunction Table 10 1 ALTMULT COMPLEX Resource Utilization and Performance Mote AIET S Inputdata Output Adaptive Dedicated Adaptive 18 bit DSP fmax MHz 7 Device family width latency Look Up Logic Logic Table Register Module ALUT 3 85 ALM 8 0 0 0 0 4 529 16 0 0 0 0 4 531 32 0 73 0 37 16 291 64 0 73 0 37 16 292 Stratix III 8 14 19 10 10 4 492 16 14 19 10 10 4 502 32 14 91 8 47 16 265 64 14 91 8 47 16 268 8 0 0 0 0 4 487 16 0 0 0 0 4 487 32 73 0 37 16 293 64 0 73 0 37 16 293 Stratix IV 8 14 19 10 10 4 489 16 14 20 10 10 4 493 32 14 91 8 47
174. r uses values from the scanina If omitted the default value is DATAA REPRESENTATION A String No Specifies the numerical representation of the multiplier input A Values are UNSIGNED and SIGNED When this parameter is set to SIGNED the adder interprets the multiplier input A as a signed number When this parameter is set to UNSIGNED the adder interprets the multiplier input A as an unsigned number If omitted the default value is UNSIGNED If the corresponding PORT_SIGNA value is USED this parameter is ignored Use the parameter PORT SIGNA to access the signa input port for dynamic control of the representation through the signa input port REPRESENTATION B String No Specifies the numerical representation of the multiplier input B Values are UNSIGNED and SIGNED When this parameter is set to SIGNED the adder interprets the multiplier input B as a signed number When this parameter is set to UNSIGNED the adder interprets the multiplier input B as an unsigned number If omitted the default value is UNSIGNED If the corresponding PORT SIGNB value is USED this parameter is ignored Use the parameter PORT SIGNB to access the signb input port for dynamic control of the representation through the signb input port SIGNED REGISTER ALTERA MULT ADD Multiply Adder C Send Feedback String No Parameter A B S
175. ral 8 width_dataword natural 8 lpm hint string UNUSED lpm type string altecc encoder port aclr in std logic 0 clock in std logic 0 clocken in std logic 1 data in std logic vector width dataword 1 downto 0 q out std logic vector width codeword 1 downto 0 end component VHDL Component Declaration ALTECC DECODER The VHDL component declaration is located in the VHDL Design File vhd altera mf components vhd in the Quartus II installation directory gt libraries vhdl altera_mf directory component altecc decoder UG 01063 2014 12 19 generic intended device family string unused lpm pipeline natural 0 width codeword natural 8 width dataword natural 8 lpm hint string UNUSED lpm type string altecc decoder port aclr in std logic 0 clock in std logic 0 clocken in std logic 1 Altera Corporation ALTECC Error Correction Code Encoder Decoder C Send Feedback UG 01063 2014 12 19 VHDL LIBRARY_USE Declaration 5 7 data in std logic vector width codeword 1 downto 0 q out std logic vector width dataword 1 downto 0 end component VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY altera mf USE altera mf altera mf components all Ports ALTECC ENCODER The following tables list the input and output ports for the ALTEC
176. rent specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 Verilog HDL Prototype UG 01063 2014 12 19 The LPM_MULT megafunction can be implemented using either logic resources or dedicated multiplier circuitry in Altera devices Typically the LPM_MULT megafunction is translated to the dedicated multiplier circuitry when it is available because it provides better performance and resource utilization If all of the input data widths are smaller than or equal to nine bits the function uses the 9 x 9 multiplier configuration in the dedicated multiplier Otherwise 18 x 18 multipliers are used to process data with widths between 10 bits and 18 bits For information about the architecture of the DSP blocks and embedded multipliers and for detailed information about the hardware conversion process refer to the DSP block and embedded multiplier chapters in the Stratix device series Stratix II Stratix III
177. rformance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any pb visis egistere products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG 01063 8 2 Features 2014 12 19 A multiplier accumulator accepts a pair of inputs multiplies the two inputs together and feeds their result into an accumulator to be added to or subtracted from its previous registered result This function is expressed in the following equation N 1 y gt 41 x A x Bj i 0 Where N is the number of cycles of data that has been entered into the accumulator Features The ALTMULT_ACCUM megafunction offers the following features e Generates a multiplier accumulator e Supports data widths of 1 256 bits e Supports signed and unsigned data representation format e Supports pipelining with configurable output latency e Provides a choice of implementation in dedicated DSP block circuitry or logic elements LEs Note When building multipliers larger tha
178. rmation and before placing orders for products or services JAN Of p AN 101 Innovation Drive San Jose CA 95134 13 2 Document Revision History UG 01063 2014 12 19 a CN February 2013 February 2012 3 1 3 0 Updated Table 52 on page 63 to include Stratix V information for accum_sload port Updated Table 54 on page 65 to include Stratix V information for PORT_SIGNA and PORT_SIGNB parameters Added Arria V and Cyclone V device support Updated the parameter description for the following section e ALTMULT ACCUM Multiply Accumulate ALTMULT ADD Multiply Add Added the Double Accumulator section July 2010 2 0 Updated architecture information for the following sections e ALTMULT ACCUM Multiply Accumulate e ALTMULT ADD Multiply Add e ALTMULT COMPLEX Complex Multiplier Added specification information for all megafunctions November 2009 1 0 Initial release Altera Corporation Document Revision History C Send Feedback
179. rpreted as unsigned numbers when the value is set to UNSIGNED and as two s complement when the value is set to SIGNED WIDTH_A Integer Yes Specifies the width of the dataa_ real and dataa imag ports Value must be 256 bits or less If omitted the default value is 18 ALTMULT COMPLEX Complex Multiplier LJ Send Feedback Altera Corporation UG 01063 10 8 Design Example Multiplication of 8 bit Complex Numbers Using Canonical 2014 12 19 Representation WIDTH_B Integer Yes Specifies the width of the dat ab_ real and datab imag ports Value must 256 bits or less If omitted the default value is 18 WIDTH_RESULT Integer Yes Specifies the width of the result_ real and result imag ports Value must be 256 bits or less If omitted the default value is 36 INTENDED DEVICE FAMILY String No This parameter is used for modeling and behavioral simulation purposes Create the ALTMULT COMPLEX megafunction with the MegaWizard Plug in Manager to calculate the value for this parameter LEM HINT String No When you instantiate a library of parameterized modules LPM function in a VHDL Design File vhd you must use the LPM_HINT parameter to specify an Altera specific parameter For example LPM HINT CHAIN SIZE 8 ONE INPUT IS CONSTANT YES The default value is UNUSED LPM TYPE String No Identifies the library of parameter
180. rs Some IP cores use a legacy version of the parameter editor for configuration and generation Use the following steps to configure and generate an IP variation using a legacy parameter editor Note The legacy parameter editor generates a different output file structure than the latest parameter editor Refer to Specifying IP Core Parameters and Options for configuration of IP cores that use the Altera Corporation latest parameter editor Integer Arithmetic Megafunctions C Send Feedback UG 01063 2014 12 19 Files Generated for Altera IP Cores Legacy Parameter Editor 1 7 Figure 1 5 Legacy Parameter Editors wa About this Core E Documentation 1 Legacy parameter PB ence editors E FP step 2 eal Set Up Simulation Step 3 Generate Viterbi Compiler nager page tanca sack Ne Brien 1 In the IP Catalog Tools gt IP Catalog locate and double click the name of the IP core to customize The parameter editor appears 2 Specify a top level name and output HDL file type for your IP variation This name identifies the IP core variation files in your project Click OK 3 Specify the parameters and options for your IP variation in the parameter editor Refer to your IP core user guide for information about specific IP core parameters 4 Click Finish or Generate depending on the parameter editor vers
181. rted devices open the IP core s installation folder andor view links to documentation Figure 1 2 Quartus II IP Catalog IP Catalog REX Search and filter IP for your target device Q x z 5 Installed IP Refresh IP catalog Ctri R poa a i v Show IP for all device families Library Show IP for active device family Basic Functions Arithmetic Bridges and Adaptors Clocks PLLs and Resets ALTCUKCTBL PLL Configuration and Programming VO Miscellaneous Double click to customize right click for information altcikctri Add version 14 0 Details d ALTCLKCTRL altcikctri On Chip Memory Simulation Debug and Verification Arria 10 Arria Il GX Cyclone IV GX Stratix V Stratix IV DSP Altera Corporation Interface Protocols Memory Interfaces and Controllers Installed version 14 0 Processors and Peripherals Supported Device Families Arria Il GZ Arria V Arria V GZ Cyclone IV E Cyclone V System S earch for Partner IP MAX 10 FPGA Location tools acdskit 14 0 184 linux64 ip altera megafunctions altcikctri altclkctrl hw tcl iy Open Component Folder P Add Integer Arithmetic Megafunctions Altera Corporation CJ Send Feedback P UG 01063 1 4 Using the Parameter Editor 2014 12 19 Note The IP Catalog is also available in Qsys View gt IP Catalog The Qsys IP Catalog includes exclusive system interconnect video and image processing and other system level
182. s 0 the ports are not registered If the value is 1 the output ports are registered If the value is 2 the input and output ports are registered If omitted the default value is 0 Parameters ALTECC DECODER Altera Corporation ALTECC Error Correction Code Encoder Decoder C Send Feedback UG 01063 2014 12 19 Design Example 1 ALTECC_ENCODER 5 9 The following table lists the parameters for the ALTECC_DECODER megafunction Table 5 8 ALTECC_DECODER Megafunction Parameters TH_DATAWORD Integer Specifies the width of the raw data Values are 2 to 64 The default value is 8 WIDTH CODEWORD Integer Specifies the width of the corresponding code word Values are 6 to 72 excluding 9 17 33 and 65 If omitted the default value is 13 LPM PIPELINE Integer Specifies the register of the circuit Values are from 0 to 2 If the value is 0 no register is implemented If the value is 1 the output is registered If the value is 2 both the input and the output are registered If the value is greater than 2 additional registers are implemented at the output for the additional latencies If omitted the default value is 0 Create a syn e port Integer Turn on this parameter to create a syn e port Design Example 1 ALTECC ENCODER This design example uses the ECC encoder to encode an 8 bit wide input data to generate 13 bits of output code word This example uses the
183. s PORT_UNUSED REPRESENTATION_ String No Parameter A B Specifies the m um of the corresponding data port Values are UNSIGNED and stcnep When this parameter is set to SIGNED the accumulator interprets the dataa input as signed two s complement If omitted the default value is UNSIGNED This parameter is ignored if the signa port is used SIGN ACLR String No Parameter A B Specifies the asynchronous clear signal for the first register on the corresponding sign port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default value is AcLR3 This parameter is ignored if the corresponding sign port is unused SIGN PIPELINE ACER B Parameter A B Specifies the dne clear signal for the second register on the corresponding sign port Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted the default value is AcLR3 This parameter is ignored if the corresponding sign port is unused ALTMULT ACCUM Multiply Accumulate LJ Send Feedback Altera Corporation 8 12 ALTMULT_ACCUM Parameters UG 01063 2014 12 19 SIGN PIPELINE REG String Parameter A B Specifies the clock signal for the second register on the corresponding sign port Values are UNREGISTERED CLOCKO0 CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is cLocko This parameter is ignored if the
184. scribed at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO amp RYA 101 Innovation Drive San Jose CA 95134 S UG 01063 7 2 Resource Utilization and Performance 2014 12 19 Resource Utilization and Performance The following table provides resource utilization and performance information for the ALTMEMMULT megafunction Table 7 1 ALTMEMMULT Resource Utilization and Performance Logic Usage Output Adaptive Dedicated Adaptive Device family Input data width rence Look Up Logic Logic fmax MHz 9 Table ALUT Register Module 78 3 ALM data 4 x coeff 4 2 61 62 41 445 Stratix III data 8 x coeff 8 7 65 88 55 567 data 16 x 7 151 175 107 445 coeff 16 data 4 x coeff 4 2 43 55 36 623 Stratix IV data 8 x coeff 8 7 65 88 56 605 data 16 x 7 109 156 96 570 coeff 16 Verilog HDL Pro
185. sign port Values are UNREGISTERED CLOCKO CLOCK1 and CLOCK2 If omitted the default value is UNREGISTERED SIGNE D_LATE NCY ACLR String Parameter A B Specifies the asynchro nous clear signal for the pipeline register on the corresponding sign port Values are NONE ACLRO and ACLR1 If omitted the default value is NONE ADDNSUB MULTIPLIER LATENCY CLOCK String No Parameter 1 3 Specifies the clock signal for the pipeline register on the corresponding addnsub input Values are UNREGISTERED CLOCK0 CLOCK1 and CLOCK2 If omitted the default value is uNREGIS TERED Altera Corporation ALTERA MULT ADD Multiply Adder C Send Feedback UG 01063 i 2 2014 12 19 Design Example Implementing a Simple Finite Impulse Response FIR Filter 6 19 ADDNSUB MULTIPLIER LATENCY String Parameter 1 3 Specifies the asynchro ACLR nous clear EU for the pipeline register on the corresponding addnsub input Values are NONE ACLRO and ACLR1 If omitted the default value is NONE ACCUM SLOAD LATENCY CLOCK String No Specifies the clock signal for the pipeline register on the corresponding accum_sload or sload_accum input Values are UNREGIS TERED CLOCK0 CLOCK1 and crock2 If omitted the default value is UNREGISTERED ACCUM SLOAD LATENCY
186. st use the LPM HINT parameter to specify an Altera specific parameter For example LPM HINT CHAIN SIZE 8 ONE INPUT IS CONSTANT YES The default value is UNUSED Altera Corporation LPM DIVIDE Divider G send Feedback UG 01063 2014 12 19 Parameters 3 5 LPM_REMAINDE RPOSITIVE String Altera specific parameter You must use the LPM_HINT parameter to specify the LPM REMAINDERPOSITIVE parameter in VHDL design files Values are TRUE or FALSE If this parameter is set to TRUE then the value ofthe remain port must be greater than or equal to zero If this parameter is set to TRUE then the value of the remain port is either zero or the value is the same sign either positive or negative as the value of the numer port In order to reduce area and improve speed Altera recommends setting this parameter to TRUE in operations where the remainder must be positive or where the remainder is unimportant MAXIMIZE SPEE Integer No Altera specific parameter You must use the LPM_HINT parameter to specify the MAXIMIZE SPEED parameter in VHDL design files Values are 0 9 If used the Quartus II software attempts to optimize a specific instance of the LPM_DIVIDE function for speed rather than routability and overrides the setting of the Optimiza tion Technique logic option If MAXIMIZE SPEED is unused the value of the
187. stolic register inputs of the first multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOCK2 The value must be set similar to the value of OUTPUT_REGISTER or set as UNREGISTERED Altera Corporation ALTERA_MULT_ADD Multiply Adder C Send Feedback UG 01063 2014 12 19 ALTERA_MULT_ADD Parameters 6 1 7 SYSTOLIC_DELAY3 String Specifies the clock source for the systolic register inputs of the third multiplier Values are UNREGISTERED CLOCKO CLOCK1 and CLOCK2 The value must be set similar to the value of OUTPUT_REGISTER or Set as UNREGISTERED SYSTOLIC_ACLR1 String No Specifies the asynchronous clear source for the systolic register inputs of the first multiplier Values are NONE ACLRO and ACLR1 If omitted the default value is NoNE The value must be set similar to the value of OUTPUT ACLR SYSTOLICLACLR String No Specifies the asynchronous clear source for the systolic register inputs of the third multiplier Values are NONE ACLRO and ACLR1 If omitted the default value is None The value must be set similar to the value of OUTPUT ACLR COEFO Integer No Specifies the coefficient value 0 7 for the inputs of the first multiplier The number of coefficient bits must be set similar to the value of WIDTH_COEF COEF1_ Integer No Specifies the coefficient value 0 7 for the
188. t If the signa port is low the multiplier treats the dataa port as an unsigned number signb No Specifies the numerical representation of the aatab port If the signb port is high the multiplier treats the datab port as signed two s complement If the signb port is low the multiplier treats the dat ab port as an unsigned number Table 8 3 ALTMULT ACCUM Megafunction Input Ports Stratix Ill and Stratix IV Devices Only accum round No Enables accumulator rounding Table 8 4 ALTMULT ACCUM Megafunction Output Ports overflow No Overflow port for the accumulator ALTMULT ACCUM Multiply Accumulate Altera Corporation LJ Send Feedback 8 6 ALTMULT_ACCUM Parameters UG 01063 2014 12 19 result Accumulator output port The size of the output port depends on the WIDTH_RESULT parameter value scanouta Output of the first shift register The size of the output port depends on the wibTH A parameter value When instantiating the ALTMULT ACCUM megafunction with the MegaWizard Plug In Manager the MegaWizard Plug In Manager renames the scanouta port to sniftouta port scanoutb Output of the second shift register The size of the input port depends on the wIDTH_B parameter value When instantiating the ALTMULT_ACCUM megafunction with the MegaWizard Plug In Manager the MegaWizard Plug In Manager renames the scanoutb port to shiftoutb port ALTMULT_ACCUM Parameters The fol
189. th of the result output port SEE i Integer Specifies the relative shift of the data vectors NEW_SUBTRACT String Specifies whether to add or subtract the most significant input word bit Values are No or ves If omitted the default value is no REPRESENTATION PIPELINE String Integer No Specifies whether the input is signed or unsigned Values are UNSIGNED or SIGNED If omitted the default value is UNSIGNED Specifies the value in clock cycles of the output latency RESULT_ALIGNM ENT String No Specifies the alignment of the result port Values are MsB or LSB If omitted the default value is LSB DE VICE INTENDED FAMILY String No This parameter is used for modeling and behavioral simulation purposes Create the ALTCDR RX megafunction with the MegaWizard Plug In Manager to calculate the value for this parameter LPM HINT String No When you instantiate a library of parameter ized modules LPM function in a VHDL Design File vhd you must use the LPM_ HINT parameter to specify an Altera specific parameter For example LPM HINT CHAIN SIZE 8 ONE INPUT IS CONSTANT YES The default value is UNUSED LPM_TYPE String No Identifies the library of parameterized modules LPM entity name in VHDL design files Design Example Shi
190. tion is complete click Close Click Finish to complete migration of the IP core Click OK if you are prompted to overwrite IP core files The Device Family column displays the migrated device support The migration process replaces my ip qip with the my ip qsys top level IP file in your project Note If migration does not replace my ip qip with lt my_ip gt qsys click Project gt Add Remove Files in Project to replace the file in your project Review the latest parameters in the parameter editor or generated HDL for correctness IP migration may change ports parameters or functionality of the IP core During migration the IP cores HDL generates into a library that is different from the original output location of the IP core Update any assignments that reference outdated locations If your upgraded IP core is represented by a symbol in a supporting Block Design File schematic replace the symbol with the newly generated my ip bsf after migration Note The migration process may change the IP variation interface parameters and functionality This may require you to change your design or to re parameterize your variant after the Upgrade IP Components dialog box indicates that migration is complete The Description field identifies IP cores that require design or parameter changes Related Information Altera IP Release Notes Integer Arithmetic Megafunctions Altera Corporation CJ Send Feedback UG 0
191. to SIGNED the adder interprets the multiplier input A as a signed two s complement number When this parameter is set to UNSIGNED the adder interprets the multiplier input A as an unsigned number If omitted the default value is UNSIGNED Use the VARIABLE setting to access the SIGNED_ REGISTER_A and the SIGNED_ PIPELINE_REGISTER_A parameter options for the signa input port REPRESENTATIONS_B String No _ Specifies the numerical represen tation of the multiplier input B port Values are UNSIGNED SIGNED and VARIABLE When this parameter is set to UNSIGNED the adder interprets the multiplier input B as an unsigned number When this parameter is set to SIGNED the adder interprets the multiplier input B as a signed two s complement number If omitted the default value is UNSIGNED Use the VARIABLE setting to access the SIGNED REGISTER B and the SIGNED PIPELINE REGISTER B parameter options for the signb input port I SIGNED REGISTER String No Parameter a B Specifies the clock signal for the first register on the corresponding sign port Values are UNREGISTERED CLOCKO0 CLOCK1 CLOCK2 and CLOCK3 If the corresponding sign port value is UNUSED this parameter is ignored If omitted the default value is cLOCKO ALTMULT ADD Multiply Adde
192. totype The following Verilog HDL prototype is located in the Verilog Design File v altera mf v in the Quartus II installation directory YedaWynthesis directory module altmemmult parameter coeff representation SIGNED parameter coefficientO UNUSED parameter data_representation SIGNED parameter intended_device_family unused parameter max_clock_cycles_per_result 1 parameter number of coefficients 1 parameter ram block type AUTO parameter total latency 1 parameter width c 1 parameter width d 1 parameter width r 1 parameter width s 1 altmemmult unused parameter lpm type parameter lpm hint input wire clock input wire width c 1 0 coeff in input wire width d 1 0 data in output wire load done output wire width r 1 0 result output wire result valid 9 The performance of the megafunction is dependant on the value of the maximum allowable ceiling fmax that the selected device can achieve Therefore results may vary from the numbers stated in this column Altera Corporation ALTMEMMULT Memory based Constant Coefficient Multiplier C Send Feedback UG 01063 2014 12 19 VHDL Component Declaration 7 3 wire wire input input input wire input wire endmodule sclr width_s 1 0 sload_coeff sload_data synthesis syn_black_box 1 sel VHDL Component Declaration The VHDL component declaration is located in
193. two multipliers Figure 6 5 Pre adder Square Mode a0 MultO HQ bO result al L Multl bl K Pre adder Constant Mode 6 5 In this mode one multiplier operand derives from the input port and the other operand derives from the internal coefficient storage The coefficient storage allows up to 8 preset constants The coefficient selection signals are coe se1 0 3 The following settings are applied in this mode e The width of the dataa input wIDTH_A must be less than or equals to 27 bits e The width of the coefficient input must be less than or equals to 27 bits e The datab port must be disconnected This mode is expressed in the following equation y a0 x coef The following figure shows the pre adder constant mode of a multiplier ALTERA MULT ADD Multiply Adder Altera Corporation CJ Send Feedback UG 01063 6 6 Systolic Delay Register 2014 12 19 Figure 6 6 Pre adder Constant Mode MultO a0 O0 result coefselO coef Systolic Delay Register In a systolic architecture the input data is fed into a cascade of registers acting as a data buffer Each register delivers an input sample to a multiplier where it is multiplied by the respective coefficient The chain adder stores the gradually combined results from the multiplier and the previously registered result from the
194. ty name in VHDL design files INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes Create the LPM_COUNTER megafunction with the MegaWizard Plug In Manager to calculate the value for this parameter CARRY_CNT_EN String No Altera specific parameter You must use the LPM HINT parameter to specify the cARRY_ CNT EN parameter in VHDL design files Values are SMART ON OFF and UNUSED Enables the LpM_CoUNTER function to propagate the cnt_en signal through the carry chain In some cases the CARRY_CNT_ EN parameter setting might have a slight impact on the speed so you might want to turn it off The default value is smart which provides the best trade off between size and speed LABWIDE SCLR String No Altera specific parameter You must use the LPM HINT parameter to specify the jABWIDE SCLR parameter in VHDL design files Values are ON OFF or UNUSED The default value is ox Allows you to disable the use of the LAB wide scir feature found in obsoleted device families Turning this option off increases the chances of fully using the partially filled LABs and thus may allow higher logic density when scur does not apply to a complete LAB This parameter is available for backward compatibility and Altera recommends you not to use this parameter Altera Corporation LPM COUNTER Counter C Send Feedback UG 01063 2014 12 19 Par
195. ue leen ore Es Eiaa aS 10 5 VHDL LIBRARY USE Declaration es aset sairaista air aena ea ete ER keen ei 10 5 ALIMULT COMPLEX Ports ttr tereti ect e de Eiee 10 6 ALIMULT COMPLEX Parametets 2 dor trecenti irte te teet dant tata Le ra ada et n 10 6 Design Example Multiplication of 8 bit Complex Numbers Using Canonical Representation 10 8 Understanding the Simulation Results uie ett irte ata ARAM Ar Pie ERA OA tup AS RA E 10 8 ALTSQRT Integer Square Ro0f onov EVE IRE Mag fS ERN RI Up PIPER UUA 11 1 hil e 11 1 Resource Utilization and Perfolbidlo6 ase e t UEBER E TUER UN ERR nO ER HE TUS 11 1 Verilog HDL Prototype sesse P EE Sy 11 2 VHDL Component Declaration enirn epe korst cont selasuysycersnccvevs cpacaacevscebecseecuabansteedee 11 2 VHDL LIBRARY USE Declarations csssscscsccscaccscesessandectscssseedsdecsnssstncaadencactscnenutvesasceeedecsnesnisenndesavindances 11 3 lo m 11 3 h icai M 11 3 Altera Corporation Integer Arithmetic IP Cores User Guide TOC 5 Design Example 9 bit Square RO Ob sccissssiiecnivecassasivectsiseveactswensetonsthasssasuisilenciesavnensvieusrdapasivaciwenneciaueers 11 4 Understanding the Simulation Res Ng sg ecaysssa ts acicsassnyzapnassvnsnapncsaphspocbeihens d eap AURATA Rina cis 11 4 PARALLEL ADD Parallel AGdG
196. ues are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and accum_sLoaD_ REGISTER is used the default value is ACLR3 String No Specifies the clock source for the second register on the accum sload input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is cLocko ACCUM SLOAD PIPELINE ACLR String No Specifies the asynchronous clear source for the second register on the accum s1oad input Values are ACLRO ACLR1 ACLR2 and ACLR3 If omitted and accum_ SLOAD PIPELINE REGISTER S used the default value is ACLR3 ALTMULT ADD Multiply Adder LJ Send Feedback Altera Corporation 9 3 ALTMULT_ADD Parameters UG 01063 2014 12 19 red SEMER MODE String Specifies the shift mode Values are NO LEFT RIGHT ROTATION and VARIABLE If VARIABLE is selected rotate and shift_right are used to specify shift left shift right or rotation If omitted the default value is No Note that this parameter is supported only when inputs equal 32 bits each output equals 32 bits and the number of multipliers equals 1 ROTATE REGISTE String Specifies the clock source for the first register on the rotate input Values are UNREGISTERED CLOCKO CLOCK1 CLOCK2 and CLOCK3 If omitted the default value is CLOCKO ROTATI E ACLR String Spec
197. uk ex vig vec tst clock Imemmout ex vig vec tst data in memmult ex vig vec tsticoeff in Imemmuk ex vig vec tstisload coeff Imemmul ex vig vec tst sload data Imemmuk ex vig vec tst load done 4 memmuk ex vig vec tstiresult nn n 4 n 4 imemmuk_ex_vig_vec_tst result_valid memmut ex vig vec tstidock memmuk ex vig vec tstidata in Imemmui ex vig vec tsticoeff in memmok ex vig vec tstisload coeff memmuR_ex_vig_vec_tst sioad_data jmemmuk ex vig vec tstfioad done memmuk ex vig vec tstjresult Imemmuk ex vig vec tstjresult valid m Cursor 1 350 ns The following sequence corresponds with the numbered items in the figure l Altera Corporation At 190 ns the sload_coeff signal asserts to register a new coefficient value of 3 The sload data signal asserts and triggers a new multiplication The latest value of the coefficient loaded into the memory is 12 Multiplication occurs between the data in value of 19 and a coefficient of 12 At the same time at 190 ns the sload_coeff signal asserts and triggers the programming of coefficient 3 Although the multiplication result of 228 at 310 ns is valid the result valid signal does not pull high At 300 ns the sload data signal asserts and triggers a new multiplication However at 350 ns less than four clock cycles after 300 ns the sload data signal pulls high again and cancels the previous multipli cation process Multiplication finally occurs between the data
198. ur clock cycles when the multiplication is taking place to avoid getting unpredictable results The megafunction only receive new inputs after four clock cycles With the TOTAL LATENCY parameter set to 7 all multiplication results require seven clock cycles to appear at the result port The COEFFICIENTO parameter holds the value of the first fixed coefficient which is set to 2 COEFFICIENTO 2 for this design example The megafunction uses the latest coefficient value for every multiplication The sload data signal asserts when a new coefficient value is written into the register The load done signal pulls low one clock cycle after the sload data signal deasserts When the load done signal is low the new coefficient value is reprogrammed into the RAM look up table Until theload done signal pulls high no other coefficient value can be loaded into the memory regardless of whether the sload data signal asserts anytime in between The load done signal asserts when programming completes The load time required to write a new coefficient value into the register is the same for any instance of the ALTMEMMULT megafunction However the load time can vary depending on the size of the RAM used The following figure shows the simulation results for the multiplication implementation with coefficient of 2 Altera Corporation ALTMEMMULT Memory based Constant Coefficient Multiplier C Send Feedback UG 01063 2014 12 19 Understanding the S

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