Reed-Solomon II IP Core User Guide
Contents
1. lt your_ip gt bsf Block symbol schematic lt your_ip gt spd Combines simulation scripts for multiple cores lt EDA tool setup scripts gt f lt your_ip gt v or hd Top level IP synthesis file A HDL files gt f lt HDL files gt ee Deser pt on lt my_ip gt qsys The Qsys system or top level IP variation file lt my_ip gt is the name that you give your IP variation lt system gt sopcinfo Describes the connections and IP component parameterizations in your Qsys system You can parse its contents to get requirements when you develop software drivers for IP components Downstream tools such as the Nios II tool chain use this file The sopcinfo file and the system h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave Different masters may have a different address map to access a particular slave component Reed Solomon II IP Core Getting Started GO Send Feedback Altera Corporation 2 6 Files Generated for Altera IP Cores UG 01090 2015 05 01 RN SS lt my_ip gt cmp The VHDL Component Declaration cmp file is a text file that contains local generic and port definitions that you can use in VHDL design files lt my_ip gt html A report that contains connection information a memory map showing the address of each slave with respect to each master to whi2. DSP IP Core Verification Before releasing a version of an IP core Altera runs comprehensive regression tests to verify its quality and correctness Altera generates custom variations of the IP core to exercise the various parameter options and thoroughly simulates the resulting simulation models with the results verified against master simulation models Reed Solomon II IP Core Release Information Use the release information when licensing the IP core Table 1 2 Release Information a Version 15 0 Release Date May 2015 Ordering Code IP RSCODECII Primary License IPR RSCODECII Renewal License Altera Corporation About the Reed Solomon II IP Core GJ Send Feedback UG 01090 2015 05 01 Reed Solomon ll IP Core Performance and Resource Utilization 1 3 HE HEMETE HE EEEMKME REN Product ID 00E5 Encoder Decoder Vendor ID 6AF7 Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core Altera does not verify that the Quartus II software compiles IP core versions older than the previous version The Altera IP Release Notes lists any exceptions Related Information e Altera IP Release Notes Errata for Reed Solomon IP core in the Knowledge Base Reed Solomon II IP Core Performance and Resource Utilization Table 1 3 Performance and Resource Utilization Typical expected performance for a Reed Solomon II IP Core using the Quartus II software with the
3. Shortened Codewords The RS II IP core supports shortened codewords A shortened codeword contains fewer symbols than the maximum value of N which is 2M 1 where N is the total number of symbols per codeword and M is the number of bits per symbol A shortened codeword is mathematically equivalent to a maximum length code with the extra data symbols at the start of the codeword set to 0 For example 204 188 is a shortened codeword of 255 239 Both of these codewords use the same number of check symbols 16 To use shortened codewords with the decoder use the parameter editor to set the codeword length to the correct value for the encoder assert endofpacket once it generates enough symbols Decoder When the decoder receives the encoded codeword it uses the check symbols to detect errors and correct them Altera Corporation Reed Solomon II IP Core Functional Description GJ Send Feedback UG 01090 2015 05 01 Decoder 3 3 Figure 3 3 Codeword Decoding Encoded Codeword plus noise Decoded Codeword A AL RS II Decoder 1 237 238 239 240 255 gt 4a gt The received encoded codeword may differ from the original codeword due to the noise in the channel The decoder detects errors using several polynomials to locate the error location and the error value When the decoder obtains the er
4. j in_startofpacket a Fm in_endofpacket EE in_data 7 0 0 LT 4 Ls Ve W105 21611931 1371438 139 Ma naza 246 247 za 249 25012511 2521 253 25412451246 124712481249 125012511252 in_ready j out_valid ji ji W out_startofpacket a fF out_endofpacket mm out_data 7 0 0 L x I 1 1 VY Ia 5 Ve Wrost216h193 1137143803940 141 out_ready j out_error j ji ji nm status_error_value 7 0 0 0 0 r4 0 0 Ly status_num_error_symbol 3 0 0 0 0 WW Lal status_num_error_bit 6 0 0 0 0 LI 0 Reed Solomon II IP Core Functional Description Altera Corporation aa Send Feedback UG 01090 3 4 Multiple Input Channels 2015 05 01 The codeword starts when you assert the in_valid signal and the in_startofpacket signal The decoder accepts the data at in_data as valid data The codeword ends when you assert the in_endofpacket signal For a 1 channel codeword assert the in_startofpacket and in_endofpacket signals for one clock cycle When the decoder deasserts the in_ready signal the decoder cannot process any more data until it asserts the in_ready signal again At the output the operation is identical When the decoder asserts the out_valid signal and the out_startofpacket signal the decoder provides valid data on out_data The decoder asserts the out_startofpacket signal and the out_endofpacket signal to indicate the start and end of a codeword The decoder automatically detects
5. 2 Decoder 2015 05 01 Figure 3 2 Encoder Timing One Channel Shows the timing diagram of the RS II encoder with one channel dkak J U U UU UU UU UU U UU U U U U U U UU VV U U U U W U U U UT reset_reset_n ii in_valid j in_startofpacket O ji madam j in_endofpacket l in_datal7 0 in_ready i out valid out_startofpacket ji ji j out_endofpacket i out_data 7 0 OT E E AS 6 7 8 YF 10 7 V2 3 TA T 16 PBYZIS 236 237 NE ST 30 2 75 7 T2 out_ready The in_startofpacket signal starts a codeword the in_endofpacket signals its termination An asserted in_valid signal indicates valid data The in_startofpacket signal is only valid when you assert the in_valid signal For a 1 channel codeword assert the in_startofpacket and in_endofpacket signals for one clock cycle The encoder uses backpressure by deasserting the in_ready signal when it receives the in_endofpacket signal During this time the encoder signals that it cannot accept more incoming symbols and generates the check symbols for the current codeword The IP core does not verify if the number of symbols N exceeds the maximum symbols per codeword You must ensure that the codeword sent to the core has a valid N The reset_reset_n signal is active low and you can assert this signal asynchronously However you have to deassert the reset_reset_n signal synchronously with the clk_clk signal
6. Arria V SAGXFB3H4F40C4 Cyclone V 5CGXFC7D6F31C6 and Stratix V oa EE N devices Parameters Memory Registers Device Type ae Bits Per Bits Per ALM Primary Secondary fMAX Symbols Symbol Check MHz Symbol Arria V Erasures 8 204 1 687 1 765 291 217 decoder Arria V Erasures 16 8 204 1 688 1 1 810 269 213 variable decoder Arria V Full 16 8 204 952 1 989 170 239 error decoder Arria V Split 16 8 204 976 1 999 144 224 error decoder Arria V Standard 32 8 255 1 628 1 1 751 285 215 decoder large Arria V Standard decoder medium Arria V standard 6 4 15 201 1 ae 272 23 315 decoder small i 6 8 204 944 l 974 178 225 About the Reed Solomon ll IP Core Altera Corporation CJ Send Feedback 1 4 Reed Solomon ll IP Core Performance and Resource Utilization Parameters Registers UG 01090 2015 05 01 fMAX Device Type Check Bits Per Bits Per ALM Primary Secondary Symbols Symbol Check MHz Symbol Arria V Standard 16 8 204 87 164 0 422 encoder Arria V Variable 16 8 204 964 1 019 174 209 decoder Arria V Variable 32 8 204 904 299 0 234 encoder large Arria V Variable 16 8 204 444 169 0 259 encoder small Cyclone Erasures 16 8 204 1 670 1 769 366 192 M decoder Cyclone Erasures 16 8 204 1 683 1 812 342 196 V variable decoder Cyclone
7. warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 UG 01090 1 2 DSP IP Core Verification 2015 05 01 Altera offers the following device support levels for Altera IP cores e Preliminary support Altera verifies the IP core with preliminary timing models for this device family The IP core meets all functional requirements but might still be undergoing timing analysis for the device family You can use it in production designs with caution e Final support Altera verifies the IP core with final timing models for this device family The IP core meets all functional and timing requirements for the device family You can use it in production designs Table 1 1 DSP IP Core Device Family Support Arria II GX Final Arria II GZ Final Arria V Final Arria 10 Final Cyclone IV Final Cyclone V Final MAX 10 FPGA Final Stratix IV GT Final Stratix IV GX E Final Stratix V Final Other device families No support
8. 2 299 0 397 encoder large Stratix V Variable 16 8 204 435 169 0 434 encoder small About the Reed Solomon II IP Core CJ Send Feedback Altera Corporation 2015 05 01 Reed Solomon II IP Core Getting Started UG 01090 X subscribe _ Send Feedback Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license Some Altera MegaCore IP functions require that you purchase a separate license for production use However the OpenCore feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software After you are satisfied with functionality and perfformance visit the Self Service Licensing Center to obtain a license number for any Altera product Figure 2 1 IP Core Installation Path C acds quartus Contains the Quartus II software ip Contains the Altera IP Library and third party IP cores altera Contains the Altera IP Library source code Si lt IP core name gt Contains the IP core source files Note The default IP installation directory on Windows is lt drive gt altera lt version number gt on Linux it is lt home directory gt altera lt version number gt Related Information Altera Licensing Site Altera Software Installation and Licensing Manual OpenCor
9. C channel codeword startofpacket must be high for C consecutive cycles endofpacket indicates the last symbol of a codeword per channel For a C channel codeword endofpacket must be high for C consecutive cycles valid startofpacket _ endofpacket channel 0 1 0 1 i 0 1 0 1 0 1 data ch0 N 1 dh1 N 1 ch1 N 1 ch1 N 1 gt aor a choo a o an i Ja N k gt Codeword 0 Codeword 1 Note The startofpacket and endofpacket governs the number of symbols per codeword N The IP core does not verify if N exceeds the maximum symbols per codeword The IP core also does not verify the channel or data pattern You must ensure that the codeword sent to the IP core has a valid N and a valid pattern Altera Corporation Reed Solomon II IP Core Functional Description GJ Send Feedback UG 01090 2015 05 01 Reed Solomon ll IP Core Parameters 3 5 Figure 3 6 Encoder Timing Two Channels For a two channel codeword the encoder asserts the in_startofpacket and in_endofpacket signals for two consecutive cycles dk_dk PUP LLLP LLLP LLLP ALP PLA reset_reset_n J i in_valid in_startofpacket F i in_endofpacket ji ji in_data 7 0 0 I 12 3 415 6 I 7 8 9 Wo 11 12 13 14 15 2177219 219 220 22 1222 223 223 1224223224227224 229 230 23 11234 in_channel Da Le SL ji
10. Debug and Verification camel version 15 0 p DSP Supported Device Families Arria li GZ Arria V Arria V GZ Cyclone IV E Cyclone V Interface Protocols Arria 10 Arria li GX Cyclone IV GX Stratix V Stratix IV gt Low Power MAX 10 Memory Interfaces and Controllers Location Aoots acds 15 0 1 39 finux64 p attera megafunctions altcikctrVaitcikctrt_nw tcl gt Processors and Peripherals j DATASHEET University Program Search for Partner IP lt 2 Open Component Folder Note The IP Catalog is also available in Qsys View gt IP Catalog The Qsys IP Catalog includes exclusive system interconnect video and image processing and other system level IP that are not available in the Quartus II IP Catalog For more information about using the Qsys IP Catalog refer to Creating a System with Qsys in the Quartus II Handbook Specifying IP Core Parameters and Options You can quickly configure a custom IP variation in the parameter editor Use the following steps to specify IP core options and parameters in the parameter editor Refer to Specifying IP Core Parameters and Options Legacy Parameter Editors for configuration of IP cores using the legacy parameter editor 1 In the IP Catalog Tools gt IP Catalog locate and double click the name of the IP core to customize The parameter editor appears 2 Specify a top level name for your custom IP variation The parameter editor saves the IP variation settings in a file named lt you
11. FAFAFA in_ready ji out_valid ly out_startofpacket E ji ji ERK out_endofpacket ji ji L out_data 7 0 0 LL 2 3 475 6 7 8 9 10 HI 2 13 W121 217721821 9 220 22 1222 164 21 15 11 68 1157115223920770 223 224225 224 22122922923 out_channel UU U U UW Lee NL LL Le Le LP LE LF 11 out_ready j Figure 3 7 Decoder Timing Two Channels For a two channel codeword the decoder asserts the in_startofpacket and in_endofpacket signals for two consecutive cycles dkak DUALS PSAP PLLA reset_reset_n i li in_valid i W W in_startofpacket rm r ji in_endofpacket mm ji in_data 7 0 0 LT N23 YAS OV aA BAY aA BHT ASS LITT OHO ATO TOG OA TON FSIS THIS E HI 5A T5166 Te a BO 87 BB 89 901 92 93 94 95 D6 97 9B HTIN in_channel MPLA rra vv ALI y LLL ALL in_ready li j out_valid WV out_startofpacket ji m m out_endofpacket ji Eo out_data 7 0 0 Cx rr Tj 1 WTI YAETAT T Baa A out_channel hm TOU ee ee out_ready ly yi out_error r status_error_value 7 0 0 0 0 0 i status_num_error_symbol 3 0 0 0 0 BE I status_num_error_bit 6 0 0 0 li 0 li LLI I Reed Solomon II IP Core Parameters Table 3 2 Parameters Reed Solomon Encoder or Decoder Encoder Specifies an encoder or a decoder Number of 1 to 16 1 Specifies the number
12. Full 16 8 204 953 989 232 215 V error decoder Cyclone Split 16 8 204 968 1 003 198 209 V error decoder Cyclone Standard 32 8 255 1 631 1 752 409 193 V decoder large Cyclone Standard 16 8 204 938 972 227 222 V decoder medium Cyclone standard 6 4 15 200 272 56 275 V decoder small Cyclone Standard 16 8 204 87 164 0 372 V encoder Cyclone Variable 16 8 204 968 1 016 241 220 V decoder Cyclone Variable 32 8 204 905 299 0 188 V encoder large Cyclone Variable 16 8 204 444 169 0 217 V encoder small Altera Corporation About the Reed Solomon ll IP Core O Send Feedback UG 01090 Reed Solomon ll IP Core Performance and Resource Utilization 2015 05 01 Parameters Registers Device Type Check Bits Per BitsPer ALM de Secondary fMAX Symbols Symbol Check MHz Symbol Stratix V Erasures 16 8 204 1 648 1 765 367 decoder Stratix V Erasures 16 8 204 1 664 1 802 405 368 variable decoder Stratix V Full 16 8 204 955 987 252 424 error decoder Stratix V Split 16 8 204 969 1 003 248 424 error decoder Stratix V Standard 32 8 255 1 624 1 749 432 404 decoder large Stratix V Standard 16 8 204 939 972 281 410 decoder medium Stratix V standard 6 4 15 197 272 52 525 decoder small Stratix V Standard 16 8 204 87 164 0 610 encoder Stratix V Variable 16 8 204 966 1 017 270 409 decoder Stratix V Variable 32 8 204 90
13. P Core 2015 05 01 UG 01090 X subscribe C_ Send Feedback Altera DSP IP Core Features Avalon Streaming Avalon ST interfaces DSP Builder ready e Testbenches to verify the IP core e IP functional simulation models for use in Altera supported VHDL and Verilog HDL simulators Reed Solomon II IP Core Features High performance encoder or decoder for error detection and correction e e Fully parameterizable e Number of channels e Number of bits per symbol e Number of symbols per codeword e Number of check symbols per codeword e Field polynomial e Erasures supporting decoder the decoder can correct symbol errors up to the number of check symbols if you give the location of the errors to the decoder e Error symbol output the decoder provides the error values e Bit error output either split count or full count e Multiple channels for resource sharing DSP IP Core Device Family Support 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard
14. P Core Functional Description GJ Send Feedback Document Revision History 2015 05 01 UG 01090 X subscribe Send Feedback Reed Solomon II IP Core User Guide revision history a HEEKZAEE HEKE 2015 05 01 15 0 e Added in_ data information 2014 12 15 14 1 e Added final support for MAX10 and Arria 10 devices e Removed Appendix A August 2014 14 0 Arria 10 Edition e Added support for Arria 10 devices e Added Arria 10 generated files description e Removed table with generated file descriptions June 2014 14 0 e Removed support for Cyclone III and Stratix III devices e Added support for MAX 10 FPGAs e Added instructions for using IP Catalog 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product o
15. Reed Solomon II IP Core User Guide EX Subscribe UG 01090 2015 05 01 GO Send Feedback 101 Innovation Drive am San Jose CA 95134 AHNERA www altera com TOC 2 Contents About the Reed Solomon II IP CoOre ehheeeeeeeexeeexeeekeeekeeekeK K HEKA K Ke 1 1 Altera DSP IP Gore Fealt r 5 4 xasa k n lekar ar Er M ai esa TEN E kak jkaN 1 1 Reed Solomon IIP Core F a ttll 8ii cissie desp kek yaaa sil eka EEES Kena besek adar 1 1 DSP IP Core Device Family S ppOL 4i x 4c xaka tune andes belek n kn ca M01 e keyna e leka ea Essais isisa 1 1 DSP IP Core Verification dal d l nail d r danani cisn ake caye kad RA k sa k n ab lane SERERE ENAS 1 2 Reed Solomon II IP Core Release Information eee erer eker ekere eker ek eker eker kK e kk e KAK HA 1 2 Reed Solomon II IP Core Performance and Resource Utilization eee eeereeekekeeee 1 3 Reed Solomon II IP Core Getting Started menneeeneeekeeekeeeeeee 2 1 Tustallng and Licensing IPC Ores nii 4 3i 54n0ik 030 niN kk suave cass DievassaueavassuvadsussactsbacnsdanseudRundoniarbasnsnieads 2 1 OpenCore Plus IP Evaluation nen belek WE E iin 2 1 Reed Solomon II IP Core OpenCore Plus Timeout Behavior E eeeeeeerekee 2 2 IP Catalog and Parameter Bait tccscsscsiessssscsssstnaseisaeraseraenensveriarcansstareareuaenoramumamamanian 2 2 Specifying IP Core Parameters and Oni i
16. Started Send Feedback Altera Corporation 2 8 DSP Builder Design Flow Figure 2 5 Simulation in Quartus ll Design Flow Quartus ll Design Flow Analysis amp Synthesis Fitter place and route TimeQuest Timing Analyzer Device Programmer Design Entry HDL Qsys DSP Builder EDA Netlist Writer Altera Simulation Models Gate Level Simulation UG 01090 2015 05 01 Post synthesis Post synthesis functional simulation netlist Post fit functional simulation netlist Post fit timing simulation netlist functional simulation Post fit functional simulation Optional Post fit timing simulation Note Post fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current version of the Quartus II software Altera IP supports a variety of simulation models including simulation specific IP functional simulation models and encrypted RTL models and plain text RTL models These are all cycle accurate models The models support fast functional simulation of your IP core instance using industry standard VHDL or Verilog HDL simulators For some cores only the plain text RTL model is generated and you can simulate that model Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design Related Info
17. and corrects errors in a codeword and asserts the out_error signal when it encounters a non correctable codeword The decoder outputs the full codeword including the check symbols which you should remove Variable Decoding Under normal circumstances the decoder allow variable decoding you can change the number of symbols per codeword N using sink_eop but not the number of check symbols while decoding However you cannot change the length of the codeword if you turn on the erasure supporting option If you turn on the variable option you can vary the number of symbols per codeword using the numn signal and the number of check symbols using the numcheck signal in real time from their minimum allowable values up to their selected values even with the erasures supporting option turned on Multiple Input Channels The RS II IP core processes multiple input channels simultaneously The IP core receives codewords in a fixed pattern Symbols coming in through the channels are interleaved The IP core samples the first symbol of channel one on the first rising clock edge then the first symbol of channel two on the second rising clock edge etc Both information and check symbols are output in the same sequence Figure 3 5 Codeword for CChannels and N Symbols The channel signal indicates the channel associated to the current symbol The channel sequence is fixed startofpacket indicates the first symbol of a codeword per channel For a
18. ble However the sink only captures the data from the source when the IP core asserts the in_ready signal in_data data Input Data input for each codeword symbol by symbol Valid only when you assert the in_valid signal For Qsys systems the in_data bus is numn numcheck data If you have no variable check it is numn data For example for a maximum codeword length of 255 corresponding to 8 bits e in_data 7 0 data e indata 15 0 numn in_channel channel Input Specifies the channel number for data the IP core transfers on the current cycle The in_channel signal is available only when you configure the IP core to support multiple channels in_startof packet Ena endofpacket sop eop Input Input Start of packet codeword signal End of packet codeword signal Altera Corporation Reed Solomon ll IP Core Functional Description Send Feedback UG 01090 2015 05 01 Reed Solomon II IP Core Signals 3 9 in_error error Input Error signal Specifies if the input data symbol is an error and whether the decoder can consider it as an erasure Erasures supporting decoders only out SEA ENE packet sop Output Start of packet codeword signal This signal indicates the codeword boundaries on the in_ data bus When the IP core drives this signal high it indicates that the start of packet is present on the in_data bus The IP core as
19. ch it is connected and parameter assignments lt my_ip gt _generation rpt IP or Qsys generation log file A summary of the messages during IP generation lt my_ip gt debuginfo Contains post generation information Used to pass System Console and Bus Analyzer Toolkit information about the Qsys interconnect The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect lt my_ip gt qip Contains all the required information about the IP component to integrate and compile the IP component in the Quartus II software Contains information about the upgrade status of the IP component lt my_ip gt csv lt my_ip gt bsf A Block Symbol File bsf representation of the IP variation for use in Quartus II Block Diagram Files bdf lt my_ip gt spd Required input file for ip make simscript to generate simulation scripts for supported simulators The spd file contains a list of files generated for simulation along with information about memories that you can initialize lt my_ip gt ppf The Pin Planner File ppf stores the port and node assignments for IP components created for use with the Pin Planner lt my_ip gt _bb v You can use the Verilog black box _bb v file as an empty module declaration for use as a black box lt my_ip gt sip Contains information required for NativeLink simulation of IP components You must add the sip file to your Quartus proje
20. ct lt my_ip gt _inst v or _inst vhd HDL example instantiation template You can copy and paste the contents of this file into your HDL file to instantiate the IP variation lt my_ip gt regmap If the IP contains register information the regmap file generates The regmap file describes the register map information of master and slave interfaces This file complements the sopcinfo file by providing more detailed register information about the system This enables register display views and user customizable statistics in System Console Altera Corporation Reed Solomon II IP Core Getting Started O Send Feedback UG 01090 2015 05 01 Simulating Altera IP Cores in other EDA Tools 2 7 NEBE GE EEE wen lt my_ip gt svd Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system During synthesis the svd files for slave interfaces visible to System Console masters are stored in the sof file in the debug section System Console reads this section which Qsys can query for register map information For system slaves Qsys can access the registers by name lt my_ip gt v or lt my_ip gt vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation mentor Contains a ModelSim script msim_setup tcl to set up and run a simulation aldec Contains a Riviera PRO script rivierapro_setup tcl to setup and run a
21. e Plus IP Evaluation Altera s free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase You need only purchase a license for MegaCore IP cores if you decide to take your design to production OpenCore Plus supports the following evaluations Simulate the behavior of a licensed IP core in your system Verify the functionality size and speed of the IP core quickly and easily Generate time limited device programming files for designs that include IP cores Program a device with your IP core and verify your design in hardware 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera custome
22. e codeword On or off Off Specifies variable codeword length with length numn signal Variable number of On or off Off Specifies check symbols with numcheck check symbols signal Error symbol value On or off On Specifies whether the decoder indicates the error symbols Error symbol count On or off On Specifies whether the decoder indicates the number of error symbols per codeword Error bit count On or off On Specifies whether the decoder indicates the number of error bits per codeword Altera Corporation Reed Solomon II IP Core Functional Description CJ Send Feedback UG 01090 2015 05 01 Reed Solomon ll IP Core Interfaces and Signals 3 7 Error bits count Full or split Specifies full or split count format e With full count the decoder just counts the number of received error bit e With split count the decoder counts the number of received error bits with initial value 1 then corrects to value 0 and outputs num_error_bit1 It also counts the number of received error bits with initial value 0 then corrects to the value 1 and outputs num_error_bit0 Reed Solomon II IP Core Interfaces and Signals The RS II Avalon ST interface supports backpressure which is a flow control mechanism where a sink can indicate to a source to stop sending data The ready latency on the Avalon ST input interface is 0 the number of symbols per beat is fixed to 1 The clock and reset interfaces drive o
23. eatures to help you quickly locate and select an IP core e Filter IP Catalog to Show IP for active device family or Show IP for all device families If you have no project open select the Device Family in IP Catalog e Type in the Search field to locate any full or partial IP core name in IP Catalog e Right click an IP core name in IP Catalog to display details about supported devices open the IP core s installation folder and view links to documentation e Click Search for Partner IP to access partner IP information on the Altera website Altera Corporation Reed Solomon ll IP Core Getting Started GJ Send Feedback UG 01090 sae 3 2015 05 01 Specifying IP Core Parameters and Options 3 Figure 2 2 Quartus II IP Catalog IP Catalog Eg Device Family Cyclone V E GX GT SX SE ST et di distin Ui a Eb IOM mA oes OEE EA Show IP only for target device a Serena ev Search for installed IP cores lt lt Installed IP Refresh IP catalog Ctrl R Project Directory No Selection Available v Show IP for all device families v Library Show IP for active device family smn v Basic Functions gt Arithmetic gt Bridges and Adaptors v Clocks PLLs and Resets A rat an DN ron Double dick to customize right click for p PLL oe detailed information gt Configuration anc lt c r 1 0 Add version 15 0 gt Miscellaneous Details ALTCLKCTAL altetketr gt On Chip Memory Altera Corporation gt Simulation
24. ed gt altclkctri_O ALTCLKCTRL altclkctri Atelkcetrt Altcikctrl represents clock buffers that drive the Global Clock Network the Regional Clock Network and the dedicated External Clock path How do you want to use the ALTCLKCTRL For global clock jen How many clock inputs would you like hile C Create ena port to enable or disable the clock network driven by this buffer How do you want to register the ena port j Ensure glitch free switchover implementation New IP Instance New IP Variation our IP settings will be saved in a _qsys file Create IP Variation Entityname junnamed Save in folder users jbrossar 141_sv_source Target Device E om men Device Unknown F 0 3 Infi ma info Your IP will be saved in Jusers jorossar 141_sv source unnamed asys unsa unsa i r 0 Errors 0 Warnings IP Parameter Editor unnamed qsys users jbrossar unnamed qsys H Description ii Group of m EJ TEA T Block Symbol After generating and instantiating your IP variation make appropriate pin assignments to connect ALTCLKCTRL Name altclkctrl Version 14 0 Author Altera Corporation no description PLLs and Resets Altcikctri Basic Functions Clocks am View IP port z and parameter details ALTCLKCTRL 14 0 Specify your IP variation name j and target device Files Generated for Altera IP Core
25. er only Valid when the IP core asserts out_endofpacket Table 3 5 Status Interface Signals Reed Solomon II IP Core Functional Description status_error_value CJ Send Feedback Output Error correction value for every valid data symbol Altera Corporation 3 10 Reed Solomon II IP Core Signals UG 01090 2015 05 01 status_num_error_ symbol conduit Output Number of error symbols in a codeword This signal is valid when the IP core asserts out_ endofpacket Only available when you turn on Error symbol count status_num_error_ bit conduit Output Number of error bits in a codeword This signal is valid when the IP core asserts the out_ endofpacket Only available when you turn on Error bit count and select Full for Error bits count format status_num_error_ bito conduit Output Number of bit errors for the correction from bit 1 to bit 0 The latest is the correct bit This signal is valid when the IP core asserts the out_endofpacket Only available when you turn on Error bit count and select Split for Error bits count format status_num_error_ bito conduit Output Number of bit errors for the correction from bit 0 to bit 1 The latest is the correct bit This signal is valid when the IP core asserts the out_endofpacket Only available when you turn on Error bit count and select Split for Error bits count format Altera Corporation Reed Solomon II I
26. ion with new device family support Updated Functional Descrip tion with new status ports and timing diagrams May 2011 December 2010 2 0 1 0 Initial release Document Revision History CJ Send Feedback Altera Corporation
27. its FIFO buffers are full or when it has congestion on its output Related Information e Avalon Interface Specifications Reed Solomon II IP Core Signals Reed Solomon II IP Core Functional Description Altera Corporation a Send Feedback 3 8 Reed Solomon II IP Core Signals Table 3 3 Clock and Reset Signals UG 01090 2015 05 01 clk_clk Input The main system clock The whole IP core operates on the rising edge of clk_clk reset_ reset_n Input An active low signal that resets the entire system reset_n when asserted You can assert this signal asynchro nously However you must deassert it synchronous to the clk_c1k signal When the IP core recovers from reset ensure that the data it receives is a complete packet Table 3 4 Avalon ST Input and Output Interface Signals in_ready ready Output Data transfer ready signal to indicate that the sink is ready to accept data The sink interface drives the in_ready signal to control the flow of data across the interface The sink interface captures the data interface signals on the current clk rising edge in_valid vy all ate Input Data valid signal to indicate the validity of the data signals When you assert the in_valid signal the Avalon ST data interface signals are valid When you deassert the in_valid signal the Avalon ST data interface signals are invalid and must be disregarded You can assert the in_valid signal whenever data is availa
28. of input channels C channels to process The channel pattern is fixed Reed Solomon II IP Core Functional Description Altera Corporation CJ Send Feedback Reed Solomon ll IP Core Parameters UG 01090 2015 05 01 Number of bits per 3 to 12 Specifies the number of bits per symbol symbol M Number of symbols 1 to 2M 1 255 Specifies the total number of symbols per per codeword codeword N The decoder accept a new symbol every clock cycle if 6 5R lt N If N gt 6 5R 1 the decoder shows continuous behavior Number of check 1 to N 1 16 Specifies the number of check symbols per symbols per codeword R codeword Field Polynomial Any valid polynomial 285 Specifies the primitive polynomial defining the Galois field The parameter editor allows you to select only legal values If you cannot find your intended field polynomial contact Altera MySupport Type of generator Classicalor CCSDS Classical Specifies the representation of the polynomial like generator polynomial First root of the 1 to 2M 2 0 Specifies the first root of the generator polynomial polynomial generator Root spacing in the Any primitive 1 Specifies spacing between roots in the polynomial elements in the field generator polynomial generator Erasures On or off Off Specifies the erasures supporting decoder supporting decoder This option substantially increases the logic resources the design uses Variabl
29. r receive the clock and reset signal to synchronize the Avalon ST interfaces and provide reset connectivity The status interface is a conduit interface that consists of three error status signals for a codeword The decoder obtains the error symbol value number of error symbols and number of error bits in a codeword from the status signals Avalon ST Interfaces in DSP IP Cores Avalon ST interfaces define a standard flexible and modular protocol for data transfers from a source interface to a sink interface The input interface is an Avalon ST sink and the output interface is an Avalon ST source The Avalon ST interface supports packet transfers with packets interleaved across multiple channels Avalon ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries Such interfaces typically contain data ready and valid signals Avalon ST interfaces can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels The Avalon ST interface inherently synchro nizes multichannel designs which allows you to achieve efficient time multiplexed implementations without having to implement complex control logic Avalon ST interfaces support backpressure which is a flow control mechanism where a sink can signal to a source to stop sending data The sink typically uses backpressure to stop the flow of data when
30. r service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN Of RYA 101 Innovation Drive San Jose CA 95134 4 2 Document Revision History UG 01090 2015 05 01 HE HEKE HERKE HEEKKEIEEEN November 2013 13 1 Updated performance data e Added erasures supporting decoder Added status signals to parameters description e Added in_error signal description for erasures supporting decoder e Added new wizard parameters e Number of bits per symbol Field polynomial e Type of generator polynomial e First root of the generator polynomial e Root spacing in the generator polynomial e Erasures supporting decoder e Decoder status signals e Removed support for the following devices e Arria GX e Cyclone II e HardCopy II e HardCopy III e HardCopy IV e Stratix e Stratix II e Stratix GX e Stratix II GX e Added final support for the following devices ArriaV e Stratix V May 2013 13 0 Added support for Cyclone IV E devices November 2012 12 1 Added support for Arria V GZ devices Altera Corporation Document Revision History O Send Feedback UG 01090 2015 05 01 Document Revision History 4 3 HE HEME HERKE REE HEEKKEEEEN e Updated About This MegaCore Funct
31. r_ip gt qsys Click OK 3 Specify the parameters and options for your IP variation in the parameter editor including one or more of the following Refer to your IP core user guide for information about specific IP core parameters Reed Solomon II IP Core Getting Started Altera Corporation aa Send Feedback Files Generated for Altera IP Cores UG 01090 2015 05 01 e Optionally select preset parameter values if provided for your IP core Presets specify initial parameter values for specific applications Specify parameters defining the IP core functionality port configurations and device specific features Specify options for processing the IP core files in other EDA tools Click Generate HDL the Generation dialog box appears 5 Specify output file generation options and then click Generate The IP variation files generate according to your specifications To generate a simulation testbench click Generate gt Generate Testbench System 7 To generate an HDL instantiation template that you can copy and paste into your text editor click Generate gt HDL Example Click Finish The parameter editor adds the top level qsys file to the current project automatically If you are prompted to manually add the qsys file to the project click Project gt Add Remove Files in Project to add the file ports Figure 2 3 IP Parameter Editor File Edit System Generate View Tools Help A Parameters unsav
32. ream component when it generates the check symbols Figure 3 1 Reed Solomon II Codeword Encoding Data Symbol _AL 1 2 hs 237 a 239 oy RS II Encoder Encoded Codeword 237 238 239 P1 P15 P16 T Check Symbols 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYA UG 01090 3
33. rmation Simulating Altera Designs DSP Builder Design Flow DSP Builder shortens digital signal processing DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm friendly development environment This IP core supports DSP Builder Use the DSP Builder flow if you want to create a DSP Builder model that includes an IP core variation use IP Catalog if you want to create an IP core variation that you can instantiate manually in your design For more information about the DSP Builder flow refer to the Altera Corporation Reed Solomon II IP Core Getting Started GJ Send Feedback UG 01090 z 2015 05 01 DSP Builder Design Flow 2 9 Related Information Using MegaCore Functions chapter in the DSP Builder Handbook Reed Solomon II IP Core Getting Started Altera Corporation GO Send Feedback Reed Solomon II IP Core Functional Description 2015 05 01 UG 01090 X subscribe _ Send Feedback This topic describes the IP core s architecture interfaces and signals Architecture You can parameterize the Reed Solomon II IP core as an encoder or a decoder The encoder receives data packets and generates the check symbols the decoder detects and corrects errors Encoder When the encoder receives data symbols it generates check symbols for a given codeword and sends the input codeword together with the check symbols to the output interface The encoder uses backpressure on the upst
34. ror location and value the decoder corrects the errors in a codeword and sends the codeword to the output As the number of errors increases the decoder gets to a stage where it can no longer correct but only detect errors at which point the decoder asserts the out_error signal Table 3 1 Decoder Detection and Correction Lists how the decoder corrects and detects errors e depending on the number of check symbols R e lt R 2 Decoder detects and corrects errors R 2 lt e lt R Decoder asserts error signal and can only detect errors e gt R Unpredictable results For small numbers of check symbols out_error is not always reliable RS codewords have at least d different symbols d R 1 A received packet containing e errors can be either the transmitted codeword tl with e errors or another valid codeword t2 with d e errors if t2 exists When e gt R 2 the received packet looks more like f2 than f1 because d e lt e so the decoder outputs t2 and does not assert out_error The probability that 2 exists is inferior or equal to the inverse of factorial of R 2 It decreases exponentially as R increases but is nonetheless significant for small numbers of check symbols Figure 3 4 Decoder Timing One Channel shows the timing diagram of the RS II decoder with one channel akak JU U LLL LLL SLL LL LLL reset reset n ______ j W in_valid
35. rs are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JNO TS RYA 101 Innovation Drive San Jose CA 95134 UG 01090 2 2 Reed Solomon II IP Core OpenCore Plus Timeout Behavior 2015 05 01 OpenCore Plus evaluation supports the following two operation modes Untethered run the design containing the licensed IP for a limited time e Tethered run the design containing the licensed IP for a longer time or indefinitely This requires a connection between your board and the host computer Note All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times out Reed Solomon II IP Core OpenCore Plus Timeout Behavior All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one IP core in a design the time out behavior of the other IP cores may mask the time out behavior of a specific IP core All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one IP core in a design a specific IP core s time out behavior may be masked by the time out behavior of the other IP cores For IP cores the untethered time out is 1 hour the tethered time out value is indefinite Your design stops working after the hardware evaluation time expires The Quartus II software use
36. s Generate HDL Finish New i Apply preset parameters fot on specific applications The Quartus II software generates the following IP core output file structure Altera Corporation Reed Solomon II IP Core Getting Started GJ Send Feedback UG 01090 2015 05 01 Files Generated for Altera IP Cores 2 5 Figure 2 4 IP Core Generated Files lt your_ip gt v or hd Top level simulation file an lt simulator_setup_scripts gt Table 2 1 IP Core Generated Files lt your_ip gt qsys System or IP integration file lt your_ip gt sopcinfo Software tool chain integration file lt testbench gt _tb testbench system lt your_ip gt _tb qsys Testbench system file lt your_ip gt cmp VHDL component declaration file lt your_ip gt _bb v Verilog HDL black box EDA synthesis file lt your_ip gt _inst v or vhd Sample instantiation template lt testbench gt _tb lt your_ip gt ppf XML 1 0 pin information file testbench files lt your_ip gt qip Lists IP synthesis files f lt your_testbench gt _tb csv lt your_ip gt sip Contains assingments for IP simulation files lt your_testbench gt _tb spd lt your_ip gt _generation rpt IP generation report lt your_ip gt debuginfo Contains post generation information sim lt your_ip gt html Connection and memory map data simulation files
37. s OpenCore Plus Files ocp in your project directory to identify your use of the OpenCore Plus evaluation program After you activate the feature do not delete these files When the evaluation time expires for encoders out_data goes low rst goes high for decoders data goes low rst goes high Related Information AN 320 OpenCore Plus Evaluation of Megafunctions IP Catalog and Parameter Editor The Quartus II IP Catalog Tools gt IP Catalog and parameter editor help you easily customize and integrate IP cores into your project You can use the IP Catalog and parameter editor to select customize and generate files representing your custom IP variation Note The IP Catalog Tools gt IP Catalog and parameter editor replace the MegaWizard Plug In Manager for IP selection and parameterization beginning in Quartus II software version 14 0 Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores The IP Catalog lists installed IP cores available for your design Double click any IP core to launch the parameter editor and generate files representing your IP variation The parameter editor prompts you to specify an IP variation name optional ports and output file generation options The parameter editor generates a top level Qsys system file qsys or Quartus II IP file qip representing the IP core in your project You can also parameterize an IP variation without an open project Use the following f
38. serts this signal on the first transfer of every codeword out endofpacket eop Output End of packet codeword signal This signal indicates the packet boundaries on the in_data bus When the IP core drives this signal high it indicates that the end of packet is present on the in_data bus The IP core asserts this signal on the last transfer of every packet out_ready out_valid ready valid Input Output Data transfer ready signal to indicate that the downstream module is ready to accept data The source provides new data if available when you assert the out_ready signal and stops providing new data when you deassert the out_ready signal If the source is unable to provide new data it deasserts out_valid for one or more clock cycles until it is prepared to drive valid data interface signals Data valid signal The IP core asserts the out_valid signal high whenever a valid output is on out_ data the IP core deasserts the signal when there is no valid output on out_data out_data data Output Contains decoded output when the IP core asserts the out_valid signal The corrected symbols are in the same order that they are entered out_channel channel Output Specifies the channel whose result is presented at out_data Available only when you configure the IP core to support multiple channels out error SCCO Output Indicates non correctable codeword decod
39. simulation synopsys vcs Contains a shell script vcs_setup sh to set up and run a VCS simulation synopsys vcsmx Contains a shell script vcsmx_setup sh and synopsys_ sim setup file to set up and run a VCS MX simulation cadence Contains a shell script ncsim_setup sh and other setup files to set up and run an NCSIM simulation submodules Contains HDL files for the IP core submodule lt child IP cores gt For each generated child IP core directory Qsys generates synth and sim sub directories Simulating Altera IP Cores in other EDA Tools The Quartus II software supports RTL and gate level design simulation of Altera IP cores in supported EDA simulators Simulation involves setting up your simulator working environment compiling simulation model libraries and running your simulation You can use the functional simulation model and the testbench or example design generated with your IP core for simulation The functional simulation model and testbench files are generated in a project subdirectory This directory may also include scripts to compile and run the testbench For a complete list of models or libraries required to simulate your IP core refer to the scripts generated with the testbench You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts NativeLink launches your preferred simulator from within the Quartus II software Reed Solomon II IP Core Getting
40. sts esvtnasn sei taasyineseaand tunacevncedeetameabenedateateceaiusninebseaeadiiabien 2 3 Files Generated for Altera IP O66 c5ccs aon csusesatsneheocee vecdeactenietearsueanen eine ounces 2 4 Simulating Altera IP Cores in other EDA T OolS rere ekere re asiechohedbasnsanitadsss 2 7 DSP Builder Design P OW Ss sod n l nie bei Hes ye er yi Ware Ye kak deyl Are NY H KA r de eeE 2 8 Reed Solomon II IP Core Functional Description hheerrekkee 3 1 wana ncdd gt e gt h_o e _r e eerr e e w w w w waw Xemm i 3 1 12ine cl e e A A DD r r YA 3 1 DIE OTe LE ca sacscos T T N E EE 3 2 Multiple Inp t ChanhelS sisriisisessssiriessrossriisririoriiinsits k Tetin A N R NNE AAEE NEATA EES 3 4 Reed Solomon II IP Core ParameterS sse ssssessessesessereesreessesstesstestesntesseestesstestenteesteseesstessenteessteseeseress 3 5 Reed Solomon II IP Core Interfaces and Siemals assssssinscadsssesosnvessienssniatvosniundsnsodbosnsennsadubasuasabnssvessaess 3 7 Avalon ST Interfaces in DSP IP Cores es ssessssssseesssesstessstessteessteesteessteesseessseessressreesseessteesseeess 3 7 Reed Solomon IIP Cor Sia ssacsuscassessasveabecsaiicrstbhoraascessdeednatiunsnnsasiwcssadcsthucsalisdassnducsnisepiaees 3 7 Document Revision HistorY eesssesssssesesesssssecececeeeeessssssoeoooeceseeeeeeessssssoooooeeeeeeeeeee 4 1 Altera Corporation About the Reed Solomon II I
Download Pdf Manuals
Related Search