Home

Altera SoC Embedded Design Suite User Guide

1. as C C Eclipse Platform File Edit Source Refactor Navigate Search Run Window Help e vs vul I bane Open Project Quar X r Close Project Quick Access ES i Build All Ctrl B 5 Bc g cm Build Configurations gt i eae eet An outline is not Includes Build Working Set gt available A alt pt c Clean h alt pt h v Build Automatically A qspi demo blockio c qspi demo dma c Make Target d qspi demo erase c Propeta qspi demo indirect c A qspi demo c B qspi demo h Altera SoCFPGA Har altera socfpga hoste m 3 debug hosted ds i Problems 23 4 ks E gt 0 Makefile 0 items Description Resource Path Location n LI 4 m LI 0 items selected If the compilation tools issue errors ARM DS 5 AE parses and formats them for you and displays them in the Problems view 5 Build a software project in ARM DS 5 AE GCC Based Bare Metal Project Management This section shows how the Bare metal toolchain plugin can be used to manage GCC based projects in a GUI environment Creating Project 1 Start Eclipse 2 Go to File gt New C Project 3 Determine if you want to create an Executable empty project or a Bare metal library empty project a Bare metal executable Select Project Type to be Executable gt Empty Project then Toolchain to be Altera Baremetal GCC then click Finish ARM DS 5 AE Altera Corporation C Send Feedback ug 1137 6 6 Creating Project
2. Build Settings 1 Once the project is created the project properties can be accessed by going to Project gt Properties Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 Figure 6 15 Project Properties Build Settings gt K Includes ARM DS 5 AE Open Project Close Project Build All Build Configurations Build Project Build Working Set Clean Build Automatically Make Target C C Index Ei Problems X 4j Tasks E Console 7 Properties 0 items An outline is not available Description 5 Resource 6 17 2 Then in the Project Properties window the Compilation settings can be accessed by selecting C C Build gt Settings GJ Send Feedback Altera Corporation ug 1137 6 18 Debugging 2015 08 06 Figure 6 16 Project Settings type filter text Settings Resource Builders 4 C C Build Configuration Debug Active v Manage Configuratio Build Variables Environment Logging Tool Settings Build Steps Build Artifact jx Binary Parsers Error Parsers Settings Tool Chain Editor 4 ARM C Compiler 5 Command armcc gt C C General Target All options 00 g Project References I Preprocessor Refactoring History Includes Run Debug Settings Source Language Q3 Optimizations 3 Debugging Q3 Warnings and Errors Expert settings 3 Miscellaneous Command P 4 b ARM Assembler 5 line putters S
3. 2015 08 06 Figure 6 1 Creating a Project with Existing Code Alt Shift N gt c5 C Project Ctrl W S ens Close All Ctrl Shift W Vues Ctrl S Source Folder Ctrl Shift S Foka Source File Header File File from Template Ctrl P ARM DS 5 AE LJ Send Feedback Altera Corporation Bare Metal Project Management Using Makefiles Figure 6 2 Import Existing Code e New Project EHI Import Existing Code Create a new Makefile project from existing code in that same directory Project Name sample project Existing Code Location cAsample project Languages VIC W C Toolchain for Indexer Settings lt none gt ARM Compiler 5 DS 5 built in ARM ee DS 5 built in Cygwin GCC GCC 4 x arm linux gnueabihf DS 5 built in GCC for ARM Bare metal MinGW GCC V Show only available toolchains that support this platform amp ug 1137 2015 08 06 4 Create a Makefile in that folder and define the rules required for compiling the code Make sure it has Altera Corporation the all and the clean targets ARM DS 5 AE now offers the possibility of invoking the build process from the IDE and allows you to build your project as shown in the following figure ARM DS 5 AE C Send Feedback 1137 201 5 08 06 GCC Based Bare Metal Project Management 6 5 Figure 6 3 Eclipse IDE Build Process Invoked Building a Software Project in ARM DS 5 AE
4. EE KEEN CK oen NN settings lt settings file gt Yes This option specifies the path to an existing BSP settings file Boot Tools User Guide Altera Corporation LJ Send Feedback ug 1137 7 8 bsp generate files 2015 08 06 SE See SS Se get lt name gt No This option instructs bsp query settings to return the value of the BSP setting lt name gt a UT a No This option shows all the BSP settings values When using get all you must also use show names due cuis No This option only takes effect when used together with get lt name gt or get all When used with one of these options names and values of the BSP settings are shown side by side bsp generate files The bsp generate files tool generates the files and settings stored in BSP settings file as shown in the following examples Example 7 4 Generating Files After BSP Creation The following commands create a settings file based on the handoff folder and then generate the BSP files based on those settings bsp create settings type spl bsp dir settings settings bsp preloader settings dir hps isw handoff hps entity name bsp generate files settings settings bsp bsp dir Example 7 5 Generating Files After BSP Updates The following commands update the settings of a an existing BSP settings file and then generate the BSP files based on those settings bsp update settings settings settings bsp
5. fpga2sdram2regionOaddr limit fpga2sdram2regionladdr limit fpga2sdram2region2addr limit fpga2sdram2region3addr limit Second Stage Bootloader Image Tool mkpimage The Second Stage Bootloader SSBL Image Tool mkpimage creates an Altera BootROM compatible image of the Arria V and Cyclone V Preloader or Arria 10 Bootloader The tool can also decode the header of previously generated images The mkpimage tool makes the following assumptions e The input file format is raw binary You must use the objcopy utility provided with the GNU Compiler Collection GCC tool chain from the Mentor Graphics website to convert other file formats such as Executable and Linking Format File elf Hexadecimal Intel Format File hex or S Record File srec to a binary format e The output file format is binary e The tool always creates the output image at the beginning of the binary file If the image must be programmed at a specific base address you must supply the address information to the flash program ming tool e The output file contains only Preloader or Bootloader images Other images such as Linux SRAM Object File sof and user data are programmed separately using a flash programming tool or related utilities in the U boot on the target system Figure 7 5 Basic Operation of the mkpimage Tool Padding CRC Checksum SSBL CRC Checksum T E SSBL Head
6. This option specifies the start address of the operation to be performed size No This option specifies the number of bytes of data to be performed by the operation size is optional repeat interval No These options must be used together The HPS BOOT flow supports up to four images where each image is identical and these options duplicate the operation data therefore you do not need eSW to create a large file containing duplicate images repeat specifies the number of duplicate images for the operation to perform interval specifies the repeated address The default value is 64 kilobytes KB repeatand intervalare optional HPS Flash Programmer Command Line Examples Typequartus hps help to obtain information about usage You can also type quartus hps help option to obtain more details about each option For example quartus hps help o Altera Corporation HPS Flash Programmer User Guide C Send Feedback ug 1137 2015 08 06 HPS Flash Programmer Command Line Examples 9 5 Example 9 1 Program File to Address 0 of Flash quartus hps c 1 o P input bin programs the input file input bin into the flash starting at flash address 0 using a cable M Example 9 2 Program First 500 Bytes of File to Flash Decimal quartus hps c 1 o PV a 1024 s 500 input bin programs the first 500 bytes of the input file input bin into the flash starting at flash address 102
7. Tool Options mkimage invokes the mkimage tool and the help option provides the tool description and option information mkimage help Usage mkimage 1 image l gt list image header information mkimage x A arch O os T typ C comp a addr e ep n name d data file data file image A gt set architecture to arch O gt set operating system to os T gt set image type to type C set compression type comp a gt set load address to addr hex e gt set entry point to ep hex n gt set image name to name d gt use image data from datafile x gt set XIP execute in place mkimage D dtc options f fit image its fit image mkimage V gt print version information and exit Altera Corporation Boot Tools User Guide C Send Feedback ug 1137 2015 08 06 Usage Examples Usage Examples Example 7 6 Creating a U boot Image mkimage A arm T firmwar C non O u boot a 0x08000040 e 0 n U Boot 2014 10 for SOCFGPA board d u boot bin u boot img Example 7 7 Creating a Bare metal Application Image mkimag A arm O u boot T standalone C none a 0x02100000 e 0 n baremetal image d hello world bin hello world img Building the Second Stage Bootloader 7 29 This section presents the details of how the bootable SSBL image is created with the aid of the generated Makefile for both Cyclone V and Arria V Preloader and Arria 10 Bootloader
8. Bare Metal Project Management ARM DS 5 AE enables convenient project management for bare metal projects using two different methods e Using Makefiles e Using the ARM DS 5 AE graphical interface Some users prefer Makefiles because they allow the option for the project compilation to be performed from scripts Other users prefer to use a GUI to manage the project and this is available for both GCC and ARM Compiler bare metal projects Makefile Scripted compilation GCC ARM DS 5 AE graphical Multiple toolchain support GCC ARM Compiler interface Bare Metal Project Management Using Makefiles The ARM DS 5 AE enables convenient project management using makefiles The sample projects that are provided with SoC EDS use makefiles to manage the build process Note This option refers to just the DS 5 specific aspects If you are not familiar with defining and using makefiles please use the ARM DS 5 AE GUI option detailed in the next section To allow ARM DS 5 AE to manage a makefile based project create a project as follows 1 Create a folder on the disk 2 Create the project by selecting File New Makefile Project with Existing Code Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 3 Type the folder name in the Existing Code Location edit box and then click Finish Bare Metal Project Management Using Makefiles 6 3 Makefile Project with Existing Code Convert to a C C Project Adds C C Nature
9. Table 7 10 Arria 10 Bootloader F2S Firewall BSP Settings Group enable fpga2sdramOregionO True enable fpga2sdram0regionl True enable fpga2sdram0region2 True enable fpga2sdram0region3 False enable fpga2sdramlregion0 False enable fpga2sdramlregionl False Boolean Enable F2S Firewall regions enable fpga2sdramlregion2 False enable fpga2sdramlregion3 False enable fpga2sdram2region0 False enable fpga2sdram2regionl False enable fpga2sdram2region2 False enable fpga2sdram2region3 False fpga2sdram0region0addr base fpga2sdram0regionladdr base fpga2sdramOregion2addr base fpga2sdram0region3addr base fpga2sdramlregionOaddr base fpga2sdramlregionladdr base Hexadecimal 0x0 F2S Firewall region bases fpga2sdramlregion2addr base fpga2sdramlregion3addr base fpga2sdram2region0addr base fpga2sdram2regionladdr base fpga2sdram2region2addr base fpga2sdram2region3addr base Boot Tools User Guide Altera Corporation LJ Send Feedback ug 1137 7 22 Second Stage Bootloader Image Tool mkpimage 2015 08 06 fpga2sdramOregionOaddr limit fpga2sdramOregionladdr limit fpga2sdram Oregion2addr limit fpga2sdram0region3addr limit fpga2sdramlregion0addr limit fpga2sdramlregionladdr limit Hexadecimal Oxffff F2S Firewall region limits fpga2sdramlregion2addr limit fpga2sdramlregion3addr limit
10. help option provides a tool description and tool usage and option information mkpimage help mkpimage version 15 0 build 145 Description This tool creates an Altera BootROM compatible image of SecondStage Boot Loader SSBL The input and output files are in binary format It can also decode and check the validity of previously generated imag Usage Create quad image mkpimage options hv num o outfile lt infile gt lt infile gt lt infile gt lt infile gt Create single imag mkpimage options hv num o lt outfile gt lt infile gt Decode single quad image mkpimage d a lt num gt lt infile gt Options a alignment num Address alignment in kilobytes valid value starts from 64 128 256 etc default to 64 for header version 0 and 256 for header version 1 override if the NAND flash has a larger block size d decode Flag to decode the header information from input file and display it f force Flag to force decoding even if the input file is an unpadded image h help Display this help message and exit hv header version num Header version to be created Arria Cyclone V 0 Arria 10 1 o output outfile Output file relative and absolute path supported off offset num Program entry offset relative to start of header 0x40 default to 0x14 Used for header version 1 only v version Display version and exit Outp
11. useful when UART is not available The address is specified by Spl debug DEBUG MEMORY ADDR spl debug SEMIHOSTING Boolean False This setting enables semihosting support in the preloader for use with a debugger tool spl debug SEMIHOS TING is useful when UART is unavailable spl debug SKIP_SDRAM Spl performance Sl ERIAL SUPPORT Boolean Boolean False True The preloader skips SDRAM initializa tion and calibration when this setting is enabled This setting enables UART print out support enabling preloader code to call printf at runtime with debugging information stdout output from printf is directed to the UART You can view this debugging information by connecting a terminal program to the UART specified peripheral Boot Tools User Guide CJ Send Feedback Altera Corporation 7 14 Cyclone V and Arria V BSP Settings ug 1137 2015 08 06 reset assert DMA Boolean False spl reset assert GPIO0 Boolean False spl reset assert GPIOl Boolean False spl spl reset_assert GPIO2 reset_assert L4WD1 Boolean Boolean False False spl reset_assert OSC1TIMI ERI Boolean False spl reset_assert SDR Boolean False spl reset_assert SPTIMER 0 Boolean False spl reset_assert SPTIMER 1 Boolean False When enabled this setti
12. 201 Head Example 7 1 Creating a New BSP Settings File The following example creates a new Preloader BSP settings file based on the hardware handoff information and using the default BSP settings bsp create settings type spl bsp dir settings settings bsp preloader settings dir hps isw handoff hps entity name Table 7 1 User Parameters bsp create settings EE KEEN EE CH oen NN SEP SPOD Den Yes This option specifies the type of BSP Allowed values are spl for Cyclone V Arria V Preloader and uboot for Arria 10 Bootloader E uu c Yes This option specifies the path to a BSP settings file The file is created with default settings Altera recommends that you name the BSP settings file settings bsp prelgsceccusbpeagneu Yes This option specifies the path to directory the hardware handoff files bsp dir directory Yes This option specifies the path where the BSP files are generated When specified bsp create settings generates the files after the settings file has been created Altera recommends that you always specify this parameter with bsp create settings A cR ud No This option sets the BSP setting lt name gt to the value value Multiple instances of this option can be used with the same command Refer to BSP Settings for a complete list of available setting names and descriptions bsp update settings The bsp update settings tool updates
13. 30150806 Figure 6 4 Bare Metal Executable Project Type C Project Create C project of selected type Project name TestProject Use default location Location C Workspace TestProject Browse Choose file systern default v Project type Toolchains a Executable ARM Compiler 5 DS 5 built in Empty Project ARM Compiler 6 DS 5 built in Hello World ANSI C Project Altera Baremetal GCC gt g Shared Library Cygwin GCC gt Static Library GCC 4 x arm linux gnueabihf DS 5 built in gt Makefile project GCC for ARM Bare metal MinGW GCC 7 Show project types and toolchains only if they are supported on the platform lt Bock ates b Static Library Select Bare metal Library gt Empty Project and click Finish Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 nice Build Settings 6 7 Figure 6 5 Bare Metal Library Project Type Create C project of selected type Project name TestLibrary Use default location Browse Location C Workspace TestLibrary Choose file syster default v Project type Toolchains gt Executable ARM Compiler 5 DS 5 built in gt Shared Library ARM Compiler 6 DS 5 built in 4 Static Library Altera Baremetal GCC Empty Project Cygwin GCC gt Makefile project GCC 4 x arm linux gnueabihf DS 5 built in GCC for ARM Bare metal MinGW GCC V Show proj
14. Address Use RSE Host Port 5000 Use Extended Mode iS A mj Note For the Linux Application Debug the Connection needs to be configured in the Remote System Explorer view as shown in Getting Started with Linux Application Debugging Related Information e DTSL Options on page 6 31 For more information about the option on the Connections tab refer to the DTSL Options section Debugger Options on page 6 28 Getting Started Guides on page 5 1 ARM DS 5 AE LJ Send Feedback Altera Corporation ug 1137 6 28 Files Options 2015 08 06 Files Options The Files tab allows the following settings to be configured e Application on host to download the file name of the application to be downloaded to the target It can be entered directly in the edit box or it can be browsed for in the Workspace or on the File System e Files contains a set of files A file can be added to the set using the button and files can be removed from the set using the button Each file can be one of the following two types Load symbols from file the debugger will use that file to load symbols from it Add peripheral description files from directory the debugger to load peripheral register descrip tions from the SVD files stored in that directory The SVD file is a result of the compilation of the hardware project Figure 6 23 Files Settings c Connection Files E Debugger e OS Awareness 69 Arguments P Envi
15. Bare Metal and RTOS Developer As either a bare metal or a RTOS developer you need JTAG debugging and low level visibility into the system Use the bare metal compiler to compile your code and the SoC Hardware Library to control the hardware in a convenient and consistent way Use the Flash Programmer to program the flash memory on the target board These tasks require JTAG debugging which is enabled only in the Subscription Edition For more information see the Licensing section Related Information Licensing on page 3 1 Linux Kernel and Driver Developer As a Linux kernel or driver developer you may use the same tools the RTOS developers use because you need low level access and visibility into the system However you must use the Linux compiler instead of the bare metal compiler You can use the Linux device tree generator DTG to generate Linux device trees These tasks require JTAG debugging which is enabled only in the Subscription Edition For more information see the Licensing chapter Related Information Licensing on page 3 1 Linux Application Developer As a Linux application developer you write code that targets the Linux OS running on the board Because the OS provides drivers for all the hardware you do not need low level visibility over JTAG DS 5 offers a very detailed view of the OS showing information such as which threads are running and which drivers are loaded These tasks do not require JTAG debu
16. Building the Cyclone V and Arria V Preloader The following figure presents the Cyclone V and Arria V Preloader build flow as performed by the generated Makefile when invoking make In order to keep the illustration simple the generated Makefile itself is not shown Figure 7 10 Cyclone V Arria V Preloader Build Flow GEN Preloader User CUR Generic P Source Code A aia Handoff Folder o on XML Files SSBL Pidonia Compiler Preloader E Customized p Binary Files Generator Toolchain Binary a Source code E Source Code g Legend Co O Part of SoC EDS Bootable Preloader Boot Tools User Guide Altera Corporation CJ Send Feedback 1137 7 30 Building the Arria 10 Bootloader 2015 08 06 The makefile performs the following tasks e Copies the generic preloader source code into lt bsp directory gt uboot socfpga Copies the generated BSP files and hardware handoff files to the source directory in bsp directory gt uboot socfpga board altera socfpga device e Configures the compiler tools to target an SoC FPGA e Compiles the source files in lt bsp directory gt uboot socfpga with the user specified cross compiler specified in the BSP settings and stores the generated preloader binary files in lt bsp directory gt uboot socfpga spl e Converts the preloader binary file to a preloader image lt bsp directory gt pr
17. Embedded Command Shell Eclipse needs to be started from the Embedded Command Shell so that all the utilities are added to the search path and they can be used directly from the makefiles without the full path To start the Eclipse IDE that the ARM DS 5 AE uses you must type eclipse amp at the command line 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYA ug 1137 6 2 Bare Metal Project Management 2015 08 06
18. Empty Project ARM Compiler 6 DS 5 built in Hello World ANSI C Project Altera Baremetal GCC gt Shared Library Cygwin GCC gt g Static Library GCC 4 x arm linux gnueabihf g Makefile project GCC for ARM Bare metal MinGW GCC b Select Static Library gt Empty Project and then for Toolchains select ARM Compiler 5 Click Finish Altera Corporation ARM DS 5 AE C Send Feedback 1137 201 5 08 06 Linker Script 6 11 Figure 6 9 Create an Empty ARM Compiler Bare metal Library Project C Project Create C project of selected type Project name TestLibrary V Use default location Location C Workspace TestLibrary f Choose file system default Project type Toolchains gt Executable ARM Compiler 5 DS 5 built in gt g Shared Library ARM Compiler 6 DS 5 built in 4 Static Library Altera Baremetal GCC Empty Project Cygwin GCC gt g Makefile project GCC 4 x arm linux gnueabihf GCC for ARM Bare metal MinGW GCC Show project types and toolchains only if they are supported on the platform Linker Script ARM DS 5 AE offers a visual tool to help create linker scripts 1 Go to File gt New gt Other ARM DS 5 AE CJ Send Feedback Altera Corporation ug 1137 6 12 Linker Script 36150806 Figure 6 10 Creating a Linker Script File Edit Source Refactor Navigate Search Project Run Window Help New Alt Sh
19. On Linux the embedded command shell is started from the Start menu or by running lt SoC EDS installa tion directory gt embedded_command_shell sh 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 2015 08 06 ug 1137 Getting Started Guides amp Subscribe E Send Feedback The Getting Started Guides chapter provides instructions on how to access complete Getting Started instructions including the followin
20. Settings ug 1137 2015 08 06 Spl boot FPGA MAX SIZE Hexadecimal 0x10000 This setting specifies the maximum code text and rodata size that can fit within the FPGA If the code build is bigger than the specified size a build error is triggered Spl boot FPGA DATA BASE Hexadecimal OxFFFF0000 This setting specifies the base location for the data region data bss heap and stack when execute on FPGA is enabled Spl boot FPGA DATA MAX SIZE Hexadecimal 0x10000 This setting specifies the maximum data data bss heap and stack size that can fit within FPGA If the code build is bigger than the specified size a build error is triggered Spl debug DE BUG ME MORY ADDR Hexadecimal OxFFFFFD00 This setting specifies the base address for storing preloader debug information enabled with the Spl debug DEBUG MEMORY WRITE setting spl debug DE Spl debug DE BUG ME BUG ME MORY SIZE MORY ADDR Hexadecimal Hexadecimal 0x200 OxFFFFFD00 This setting specifies the maximum size used for storing preloader debug information This setting specifies the base address for storing preloader debug information enabled with the Spl debug DEBUG MEMORY WRITE setting Altera Corporation Boot Tools User Guide G send Feedback ug 1137 2015 08 06 Arria 10 BSP Settin
21. can run the HPS flash programmer directly from the command line For the Quartus II software the HPS flash programmer is located in Altera installation directory gt quartus bin For the Quartus II Programmer the HPS flash programmer is located in Altera installation directory gt qprogrammer bin How the HPS Flash Programmer Works The HPS flash programmer is divided into a host and a target The host portion runs on your computer and sends flash programming files and programming instructions over a download cable to the target O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device
22. word 0x31305341 e Version field set to 0x0 e Flags field set to 0x0 Program length measured by the number of 32 bit words in the Preloader program e 16 bit checksum of the header contents 0x40 0x49 Table 7 11 Header Format Version 0 0x48 Reserved 0x0 0x46 Program length in 32 bit words n 0x45 Flags 0x44 Version 0x40 Validation word 0x31305341 Boot Tools User Guide Altera Corporation LJ Send Feedback 7 24 Header File Format Figure 7 6 Header Format Version 0 Ox4A 0x48 0x46 0x45 0x44 0x40 ug 1137 2015 08 06 Header Checksum Reserved 0x0 Program length in 32 bit words Flags Version Validation word 0x31305341 For Version 1 used for Arria 10 Bootloader the header includes the following e Validation word 0x31305341 e Version field set to 0x1 e Flags field set to 0x0 e Header length in bytes set to 0x14 20 bytes Total program length including the exception vectors and the CRC field in bytes For an image to be valid length must be a minimum of 0x5C 92 bytes and a maximum of 0x32000 200KiB e Program entry offset relative to the start of header 0x40 and should be 32 bit word aligned Default is 0x14 any value smaller than that is invalid e 16 bit checksum of the header contents 0x40 0x51 Figure 7 7 Header Format Version 1 0x52 0x50 Ox4C 0x48 0x46 0x45 0x44 0x40 Table 7 12 Header
23. 4 followed by a verification using a cable M Note Without the prefix 0x for the flash address the tool assumes it is decimal Example 9 3 Program First 500 Bytes of File to Flash Hexadecimal quartus hps c 1 o PV a 0x400 s 500 input bin programs the first 500 bytes of the input file input bin into the flash starting at flash address 1024 followed by a verification using a cable M Note With the prefix Ox the tool assumes it is hexadecimal Example 9 4 Program File to Flash Repeating Twice at Every 1 MB quartus hps c 1 o BPV t 2 i 0x100000 input bin programs the input file input bin into the flash using a cable M The operation repeats itself twice at every 1 megabyte MB of the flash address Before the program operation the tool ensures the flash is blank After the program operation the tool verifies the data programmed Example 9 5 Erase Flash on the Flash Addresses quartus hps c 1 o EB input bin erases the flash on the flash addresses where the input file input bin resides followed by a blank check using a cable M Example 9 6 Erase Full Chip quartus hps c 1 o Eerases the full chip using a cable M When no input file input bin is specified it will erase all the flash contents Example 9 7 Erase Specified Memory Contens of Flash quartus hps c 1 o E a 0x100000 s 0x400000 erases specified memory contents of the flash For example 4 MB worth of memory content residing in the f
24. ARM DS 5 AE Altera Corporation C Send Feedback ug 1137 6 36 ETF Settings 201 5 08 06 Figure 6 35 DTSL Configuration Editor ETF Cross Trigger Trace Buffer Cortex A9 STM ETR ETF V Configure the on chip trace buffer Size 0x1000 The following options are available Configure the on chip trace buffer check this if ETF is selected for trace destination on the Trace Capture tab e Size define the ETF size By default it is set up to 0x1000 4KB but it can be set to 0x8000 32KB to match the actual buffer size Altera Corporation ARM DS 5 AE C Send Feedback Boot Tools User Guide 2015 08 06 ug 1137 amp Subscribe EJ Send Feedback Introduction The boot flow for all Altera SoC devices includes the second stage bootloader SSBL The SSBL is usually referred to as preloader in the context of Cyclone V and Arria V devices and bootloader in the context of Arria 10 devices The SSBL is loaded by the boot ROM into the on chip RAM OCRAM and has the task of bringing up the SDRAM and loading and executing the next stage in the boot process Figure 7 1 Cyclone V and Arria V Typical Boot Flow SSBL BootROM Preloader Bootloader P Operating System Figure 7 2 Arria 10 Typical Boot Flow SSBL BootROM Bootloader Operating System For Cyclone V and Arria V devices the OCRAM size is 64 KB which limits the SSBL size and typically requires a
25. Altera SoC Embedded Design Suite User Guide c Subscribe ug 1137 2015 08 06 C Send Feedback 101 Innovation Drive mm San Jose CA 95134 JAN DTE R YA www altera com TOC 2 Contents Introduction to SoC Embedded Design Suite eere 1 1 OyeryieW m 1 1 Linux D vi WCE BIN ALY M 1 2 Hardware and Software Development ROLs uccisi teris tik rsen Per ipe uu ies Un br d enna 1 3 Hardware HE TUN MR pss 1 3 Bare Metal and RTOS Developer ee esieseeeee eerte tenete tete ten tete toten ene 1 4 Linux Kernel and Driver Developet uiiesenacnbe vereieakebasdto niei bana ta Hb pu nid d ria 1 4 Linux Application Developer ne e rhet D ee ERE a a east tesa snas 1 4 Hardware Software Development Flow eeeisd cso ead r itas tsi atate ub dde v RA X ERUREERR 1 5 Installing the Altera SoC Embedded Design Suite 2 1 J stallatioti MCL GE c 2 1 Installing the SoC BIOS T 2 1 Installing the ARM DS 5 Altera Edition TOOLKIT rates tatoet tudo boa tbe h ch r bv oa t hostel oia aen 2 2 Ici pDm S 3 1 Getting the LCOS RM T 3 1 Activating the UBC C X 3 2 Embedded Command Shel sic scssccsssssi
26. COMMAND S FLAGS S OUTPUT FLAG S OUTF Target Q3 Preprocessor Debugging Q3 Warnings and Errors Q3 Miscellaneous 4 amp ARM Linker 5 Target 3 Image Layout The build settings include detailed settings for all tools e Compiler e Assembler e Linker The Getting Started with ARM Compiler Bare Metal Project Management contains a link to complete instructions on how to create a project from scratch compile it and run it on an Altera SoC development board Related Information Getting Started Guides on page 5 1 Debugging The ARM DS 5 AE offers you a variety of debugging features Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 Accessing Debug Configurations Accessing Debug Configurations 6 19 The settings for a debugging session are stored in a Debug Configuration The Debug Configurations window is accessible from the Run Debug Configurations menu Figure 6 17 Accessing Debug Configurations c V V ur I lS vA v ubl E 63 v 4 S Altera SoCFPGA HelloW gt K Includes gt 6 hello c gt fe hello o arm le Altera SoCFPGA Hell lar hello axf amp hello axf map A hello axf objdump Makefile 3 semihost setup ds L Problems ATs CDT Build Console P arm aitera eabi g arm altera eabi gi File Edit Source Refactor Navigate Search Project Run Window Help Set Next Statement Ctrl Alt R Run Ctri F11 D
27. FPGA it is better to remove the FPGA complexities The version from the hardware design folder soc system dtb ghrd 5astfd5k3 dtb and ghrd 10as066n2 dtb are based on the GHRD design which is part of the GSRD Since the GHRD does contain soft IPs these DTB file versions notify Linux to load the soft IP drivers Therefore the FPGA needs to be programmed and the bridges released before booting Linux The script downloads the sources corresponding to the pre built Linux package Altera Corporation Introduction to SoC Embedded Design Suite C Send Feedback ug 1137 201 5 08 06 Hardware and Software Development Roles 1 3 Hardware and Software Development Roles Depending on your role in hardware or software development you need a different subset of the SoC EDS toolkit The following table lists some typical engineering development roles and indicates the tools that each role typically requires For more information about each of these tools refer to the SoC Embedded Design Suite page Table 1 1 Hardware and Software Development Roles This table lists typical tool usage but your actual requirements depend on your specific project and organization Tool Hardware Bare Metal RTOS Developer Linux Kernel and Linux Application Engineer Developer Driver Developer Developer y y y y y ARM DS 5 Debugging ARM DS 5 Y I Y Tracing ARM DS 5 Y Y Y Cross Triggering Hardware y y y Libraries Second Stage Y Y Y
28. Format Version 1 Header checksum Reserved 0x0 Program entry offset Program length in bytes Header length in bytes Flags Version Validation word 0x31305341 0x50 Reserved 0x0 Ox4c Program entry offset x 0x48 Program length in bytes n 0x46 Header length in bytes 0x45 Flags 0x44 Version 0x40 Validation word 0x31305341 The header checksum for both versions of the mkpimage header is the CRC checksum of the byte value from offset 0x0 to n 4 4 bytes where n is the program length Altera Corporation Boot Tools User Guide CJ Send Feedback ug 1137 2015 08 06 Tool Usage 7 25 The CRC is a standard CRC32 with the polynomial x32 x26 x23 x22 x16 x12 x11 x10 x8 x7 xb x4 x2 4 x 1 There is no reflection of the bits and the initial value of the remainder is OXFFFFFFFF and the final value is exclusive OR ed with OxFFFFFFFF Tool Usage The mkimage tool has three usage models e Single image creation Quad image creation e Single or quad image decoding If an error is found during the make image process the tool stops and reports the error Possible error conditions include e For Cyclone V and Arria V Preloaders input image is smaller than 81 bytes or larger than 60 KB e For Arria 10 Bootloaders input image is smaller than 92 bytes or larger than 200 KB mkpimage invokes the tool invoking the tool with the
29. HPS1 Cortex A9x2 SMP Linux Application Debug Connect to already running gdbserver Download and debug application Start dbgserver and debug target resident application Linux Kernel and or Device Driver Debug Debug HPSO0 Cortex A9 0 Debug HPSO Cortex A9 1 Debug HPSO Cortex A9x2 SMP Debug HPS1 Cortex A9 0 Debug HPS1 Cortex A9 1 Debug HPS1 Cortex A9x2 SMP Android Application Debug Native Application Library Debug e APK Native Library Debug via gdbserver e Attach to a running Android application e Download and debug an Android application Linux Application Debug Altera Corporation Application Debug Connections via gdbserver e Connect to already running gdbserver e Download and debug application e Start dbgserver and debug target resident application ug 1137 2015 08 06 ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 Connection Options 6 25 Depending on the selected Target the Connections panel will look different For Bare Metal Debug and Linux Kernel and or Device Driver Debug target types e A Target Connection option appears and it allows the user to select the type of connection to the target Altera USB Blaster and DSTREAM are two of the most common options e ADTSL option appears allowing the user to configure the Debug and Traces Services Layer detailed later e A Connections Browse button appears allowing the user to browse and select either the specific instance for the connection i e Alter
30. JA DTE RYA ARM DS 5 AE 2015 08 06 ug 1137 amp Subscribe E Send Feedback The ARM Development Studio 5 Toolkit AE ARM DS 5 AE is a device specific exclusive offering from Altera The ARM DS 5 AE is a powerful Eclipse based comprehensive Integrated Development Environment IDE Some of the most important provided features are e File editing supporting syntax highlighting and source code indexing e Build support based on makefiles e Bare metal debugging e Linux application debugging e Linux kernel and driver debugging e Multicore debugging e Access to HPS peripheral registers e Access to FPGA soft IP peripheral registers e Tracing of program execution through Program Trace Macrocells PTM e Tracing of system events through System Trace Macrocells STM e Cross triggering between HPS and FPGA e Connecting to the target using Altera USB Blaster II The ARM DS 5 AE is a complex tool with many features and options This chapter only describes the most common features and options and provides getting started scenarios to help you get started quickly You can access the ARM DS 5 AE reference material from Eclipse by navigating to Help gt Help Contents gt ARM DS 5 Documentation or online Related Information Online ARM DS 5 Documentation The ARM DS 5 AE reference material can be accessed online on the documentation page of the ARM website Starting Eclipse ARM DS 5 AE ARM DS 5 AE must be started from the
31. M ETF ETR Enable FPGA gt HPS Cross Trigger C Enable HPS gt FPGA Cross Trigger Apply Revert Trace Capture Settings The Trace Capture tab allows the selection of the destination of the trace information As mentioned in the introduction the destination can be one of the following None meaning the tracing is disabled ETR using any memory buffer accessible by HPS ETF using the 32KB on chip trace buffer e DSTREAM using the 4GB buffer located in the DSTREAM The DSTREAM option is available only if the Target connection is selected as DSTREAM in the Debug Configuration Figure 6 30 DTSL Configuration Editor Trace Capture Trace Capture Method Trace Capture Cortex A9 Cross Trigger STM ETF ETR Trace capture method ness eque System Memory Trace Buffer ETR Check board is correctl On Chip Trace Buffer ETF i DSTREAM 4GB Trace Buffer DSTREAM port width The Trace Buffer tab provides the option of selecting the timestamp frequency Figure 6 31 DTSL Configuration Editor Trace Capture gt Timestamp Frequency Trace Capture Cortex A9 Cross Trigger STM ETF ETR Trace capture method System Memory Trace Buffer ETR Timestamp frequency 25000000 E Check board is correctly configured before attempting to capture trace in DSTREAM buffer DSTREAM port width 4 bit mA ARM DS 5 AE LJ Send Feedback Altera Corporation ug 1137 6 34 Cort
32. Q3 Miscellaneous 4 GCC CLinker Q3 Image Libraries Q3 Objects Q3 Warnings Q9 Miscellaneous Tool Settings Build Steps P Build Artifact i Binary Parsers Error Parsers Command arm altera eabi gcc All options 00 g Wall Expert settings Command scoMMAND S FLAGS S OUTPUT FLAG S OUTPUT PREI line pattern The Build Settings incldue detailed settings for all tools Compiler e Assembler e Linker The Getting Started Guides chapter in this document contains a link to complete instructions on how to create a project from scratch compile it and run it on an Altera SoC development board ARM Compiler Bare Metal Project Management This section shows ARM DS 5 can be used to manage ARM compiler projects in a GUI environment ARM DS 5 AE C Send Feedback Altera Corporation ug 1137 6 10 Creating a Project 201 E abas Creating a Project l Start Eclipse 2 Goto File New C Project 3 Select one of the following options a Select Project Type as Executable gt Empty Project and then for Toolchains select ARM Compiler 5 Click Finish Figure 6 8 Create an Empty ARM Compiler Bare Metal Executable Project Create C project of selected type Project name TestProject Use default location Location C Workspace TestProject Browse file system default Project type Toolchains 4 amp Executable ARM Compiler 5 DS 5 built in
33. R and pin multiplexing If Spl boot BOOTROM HANDSHAKE CFGIO is enabled and warm reset occurs when the preloader is configuring IOCSR and pin multiplexing the boot ROM will reconfigure IOCSR and pin multiplexing again This option is enabled by default Spl boot WARMRST SKIP CFGIO Boolean True This setting enables the preloader to skip IOCSR and pin multiplexing configuration during warm reset Spl boot WARMRST SKIP CFGIOis only applicable if the boot ROM has skipped IOCSR and pin multiplexing configuration Spl boot SDRAM INITIALIZATION Boolean False Initialize the SDRAM to initialize the ECC bits Spl boot SDRAM R spl boo EGION_ ECC_INIT_BOOT EGION_START C SDRAM ECC_INIT_BOOT END Hexadecimal Hexadecimal 0x1000000 0x2000000 The start address of the memory region within the SDRAM to be initialized The end address of the memory region within SDRAM to be initialized Altera Corporation Boot Tools User Guide CJ Send Feedback ug 1137 2015 08 06 Cyclone V and Arria V BSP Settings 7 13 Spl boot SDRAM ECC INIT REMAIN REGION Boolean True Initialize the remaining SDRAM during the flash accesses to load the image spl debug DEBUG M EMORY WRITE Boolean False This setting enables the preloader to write debug informa tion to memory for debugging
34. Update just the Bootloader software Update both Preloader and Bootloader software In the context of this tool the term Bootloader simply means the next boot stage from Preloader In some usage scenarios it can be a bootloader while in other scenarios it could be a bare metal application or even an OS Note The Preloader file needs to have the mkpimage header as required by the boot ROM and the Bootloader file needs to have the mkimage header as required by the Preloader Both mkpimage and mkimage tools are delivered as part of SoC EDS The tool only updates the custom partition that stores the Altera SoC boot code The rest of the SD card or disk image file is not touched This includes the Master Boot Record MBR and any other partitions FAT EXT3 etc and free space O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes n
35. WLIB are expected to evolve and expand over time particularly as common use case patterns become apparent from practical application in actual systems In general the HWLIB assumes to be part of the system software that is executing on the Hard Processor System HPS in privileged supervisor mode and in the secure state The anticipated HWLIB clients include e Bare Metal application developers e Custom preloader and boot loader software developers Board support package developers e Diagnostic tool developers e Software driver developers Debug agent developers Board bring up engineers e Other developers requiring full access to SoC FPGA hardware capabilities Feature Description This section provides a description of the operational features and functional capabilities present in the HWLIB An overview and brief description of the HWLIB architecture is also presented The HWLIB is a software library architecturally comprised of two major functional components e SoC Abstraction Layer SoCAL e Hardware Manager HW Manager SoC Abstraction Layer SoCAL The SoC Abstraction Layer SoCAL presents the software API closest to the actual HPS hardware Its purpose is to provide a logical interface abstraction and decoupling layer to the physical devices and registers that comprise the hardware interface of the HPS The SoCAL provides the benefits of e A logical interface abstraction to the HPS physical devices and register
36. Y Bootloader Generator Flash y y y y Programmer Bare Metal Y V Y Y Compiler Linux Y Y Compiler Linux Device Y Tree Generator Hardware Engineer As a hardware engineer you typically design the FPGA hardware in Qsys You can use the debugger of ARM DS 5 AE to connect to the ARM cores and test the hardware A convenient feature of the DS 5 debugger is the soft IP register visibility using Cortex Microcontroller Software Interface Standard CMSIS System View Description svd files With this feature you can easily read and modify the soft IP registers from the ARM side Introduction to SoC Embedded Design Suite Altera Corporation LJ Send Feedback ug 1137 1 4 Bare Metal and RTOS Developer 2015 08 06 As a hardware engineer you may generate the Preloader for your hardware configuration The Preloader is a piece of software that configures the HPS component according to the hardware design As a hardware engineer you may also perform the board bring up You can use ARM DS 5 debugger to verify that they can connect to the ARM and the board is working correctly These tasks require JTAG debugging which is enabled only in the Subscription Edition For more information see the Licensing section Related Information e Licensing on page 3 1 e Hardware Software Development Flow on page 1 5 For more information about svd files refer to the Hardware Software Development Flow section
37. a USB Blaster or the DSTREAM instance Figure 6 20 Connection Options for Bare metal and Linux Kernel and or Device Driver Debug Name Sample Configuration Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9 0 4 Altera Arria V SoC 4 Cyclone V SoC Dual Core 4 Bare Metal Debug Debug Cortex A9 0 Debug Cortex A9 1 Debug Cortex A9x2 SMP m Linux Application Debug m Linux Kernel and or Device Driver Debug Target Connection USB Blaster v DTSL Options Edit Configure USB Blaster trace or other target options Using default configuration DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application Connections Bare Metal Debug Connection Browse For the Linux Application Debug targets the connection parameters will be different depending on which type of connection was selected The following two pictures illustrate the options ARM DS 5 AE Altera Corporation LJ Send Feedback ug 1137 6 26 Connection Options 2015 08 06 Figure 6 21 Linux Application Debugging Connect to a Running GDB Server Name Sample Configuration Files Bs Debugger s OS Awareness 69 Arguments P Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Linux Applic
38. ake changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 ug 1137 2 2 Installing the ARM DS 5 Altera Edition Toolkit 2015 08 06 5 Select All the components to be installed and click Next The installer displays a summary of the installation Click Next to start the installation process The installer displays a separate dialog box with the installation progress of the component installation When the installation is complete turn on Launch DS 5 Installation to start the ARM DS 5 installa tion and click Finish Note On some Linux based machines you can install the SoC EDS with a setup GUI similar to the Windows based setup GUI Because of the variety of Linux distributions and package require ments not all Linux machines can use the setup GUI If the GUI is not available use an equivalent command line process Download the Linux installation program from the SoC Embedded Design Suite Download Center page on the Altera website Related Information SoC Embedded De
39. allation directory to denote the location where Altera tools are installed e SoC EDS installation directory to denote the location where SoC EDS is installed Installing the SoC EDS Perform the following steps to install the SoC EDS Tool Suite in a Windows based system 1 Download the latest installation program from the SoC Embedded Design Suite Download Center page of the Altera website 2 Run the installer to open the Installing SoC Embedded Design Suite EDS dialog box and click Next to start the Setup Wizard 3 Accept the license agreement and click Next 4 Accept the default installation directory or browse to another installation directory and click Next Note If you have previously installed the Quartus II software accept the default SoC EDS installa tion directory to allow the Quartus II software and the SoC EDS Tool Suite to operate together O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to m
40. ation Debug Connect to already running gdb 4 Altera gt Arria V SoC 4 Cyclone V SoC Dual Core b Bare Metal Debug 4 Linux Application Debug Connect to already running gdbserver Download and debug application Start qdbserver and debug target resident application DS 5 Debugger will connect to an already running gdbserver on the target system Connections Address gdbserver TCP port 5000 Use Extended Mode Terminate gdbserver on disconnect ARM DS 5 AE C Send Feedback Altera Corporation ug 1137 a 5 08 06 Connection Options 6 27 Figure 6 22 Linux Application Debugging Download And Debug Application Name Sample Configuration Ho Connection 1 Files Bs Debugger f OS Awareness 69 Arguments P Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Linux Application Debug Download and debug application 4 Cyclone V SoC Dual Core Bare Metal Debug 4 Linux Application Debug gt m Connect to already running gdbserver Download and debug application Cied e dlo re ee be Se eee ee eee Q F 4al DS 5 Debugger will download your application to the target system and then start a new gdbserver sessiooug the application This configuration requires ssh and gdbserver on the target platform Connections RSE connection
41. board specific SoC FPGA files The generator consolidates the hardware settings and user inputs to create the BSP The BSP files include a makefile to create the preloader image The preloader image can then be downloaded to a Flash device or FPGA RAM to be used for booting HPS Figure 7 3 Arria V Cyclone V BSP Generator Flow User Options Preloader Handoff Folder Customized Hardware Quartus 11 XML Files SSBL Source code Design Binary Files Generator E Source Code Makefile pes Legend Preloader Generic Source Code qe Part of SoC EDS Altera Corporation Boot Tools User Guide C Send Feedback ug 1137 2015 08 06 ug 1137 2015 08 06 Arria 10 Flow 7 3 The hardware handoff information contains various settings that the user entered when creating the hardware design in Qsys and Quartus These include the following e Pin muxing for the HPS dedicated pins e I O settings for the HPS dedicated pins e Voltage e Slew rate Pull up down e State of HPS peripherals e Enabled e Disabled e Configuration of the bridges between HPS and FPGA e Clock tree settings e PLL settings e Clock divider settings Clock gatting settings e DDR settings e Technology e Width e Speed The handoff settings are output from the Quartus compilation and are located in the quartus project directory hps isw handoff hps entity name gt directory where lt hps entity name gt is the HPS c
42. cription of the registers of the HPS peripheral registers and registers for soft IP components in the FPGA portion of the SoC This file is used by the ARM DS 5 Debugger to allow these registers to be inspected and modified by the user The SOPC Information sopcinfo file containing a description of the entire system is used by the Linux device tree generator to create the device tree used by the Linux kernel For more information refer to the Linux Device Tree Generator chapter Note The soft IP register descriptions are not generated for all soft IP cores Related Information e BSP Generation Flow on page 7 2 e Linux Device Tree Generator e SoC Embedded Design Suite Download Page Introduction to SoC Embedded Design Suite Altera Corporation C Send Feedback Installing the Altera SoC Embedded Design Suite 2 2015 08 06 ug 1137 amp Subscribe E Send Feedback You must install the Altera SoC Embedded Design Suite EDS and the ARM DS 5 AE to run the SoC EDS on an Altera SoC hardware platform Installation Folders The default installation folder for SoC EDS is e SoC EDS installation directory e c altera 15 0 embedded on Windows e altera 15 0 embedded on Linux The default installation folder for Quartus Programmer is e Quartus installation directory c altera 15 0 qprogrammer on Windows e altera 15 0 qprogrammer on Linux Note The installation directories are defined as follows e Altera inst
43. dback 1137 2 5 08 06 Building the Arria 10 Bootloader 7 31 The makefile performs the following tasks Copies the bootloader source code into lt bsp directory gt uboot socfpga e Configures the bootloader to target the Arria 10 SoC Compiles the source files in lt bsp directory gt uboot socfpga and creates the Bootloader binary bsp directory gt uboot socfpga u boot bin e Creates the bootloader device tree file based on the hardware handoff information and user settings into lt bsp directory gt devicetree dts e Compiles the bootloader device tree source file by using dtc Device Tree Compiler into lt bsp directory gt devicetree dtb e Concatenates the bootloader device tree binary and the bootloader binary files into a combined binary file lt bsp directory gt u boot_w_dtb bin e Converts the combined binary file to a bootable combined image lt bsp directory gt uboot_w_dtb mkpimage bin with the mkpimage tool The makefile contains the following targets e make all builds everything e make src copies the bootloader source code folder e make uboot builds the bootloader binary e make dtb compiles the bootloader device tree source to device tree binary e make clean deletes all built files e make clean all deletes all built files and the bootloader source code folder Boot Tools User Guide Altera Corporation CJ Send Feedback Hardware Library 2015 08 06 ug 1137 amp Subscribe E Se
44. described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN DO fs S AN 101 Innovation Drive San Jose CA 95134 ug 1137 3 2 Activating the License 2015 08 06 30 Day Evaluation of Subscription Edition If you want to evaluate the SoC EDS Subscription Edition you can get a 30 Day Evaluation activation code from the SoC Embedded Design Suite download page on the Altera website and then activate your license in DS 5 as shown in the Activating the License section Related Information e SoC EDS Download Page e Activating the License on page 3 2 Activating the License This section presents the steps required for activating the license in the ARM DS 5 AE by using the serial license number or activation code that were mentioned in the Getting the License chapter Note An active user account is required to activate the DS 5 AE licen
45. e Interacts ioce nina estratti erbe id connu pea Vk 7 5 BSP Files and Folders uiae oitintii puede honestas ad oat oue pte eR pude dies 7 9 BSP I 7 9 Second Stage Bootloader Image Tool mkpimage es sse ssssrssseressressresssresssreessreesrressnresnressnresnreenrrrsss 7 22 Iria 7 23 Header FINS Mors NR 7 23 QUE i 7 25 nundudlnrnodb vd 7 25 U Boot Image T dol DE nda n T 7 27 TOOLODEOTSeiecea s eoe eque ironia amatus ME aD de ete 7 28 Usage EX ples a oO COMER RMann ND NN un i d pn pE MM DE 7 29 Building the Second Stage Bootlodtlet uuiossauosqed asp OFDM RI d c HEEL EH UESTRE GREEN 7 29 Building the Cyclone V and Arria V Preloader cusunonocecn oninia e e NER SE MIEEA 7 29 Building the Arria 10 Bootloadet iui eset ricttp petentis nnt durante teint 7 30 Hardware BY 2 v7 d 8 1 Feature Description seran sere ERR GERBER R E t HERE ASIN IR 8 2 Sac Abstraction Layer SOCAL uester nblstehtutis ond peste cep EAE AEK SEPARE TRR 8 2 Hardware Manager HW Manager ee ssssessseessreessressrreesresesrtessreesnteentesntensntesntessnteentreseereeeeesee 8 3 Hardware Library Reference DOCUDentatlOn auclor o nana Uc LO eiii oa a e t Ret aA 8 3 HPS Flash Programmer User Guide ssssscesessuccscuncdssssscestnansnsadssstacunsessaxassnassdiede
46. e U Boot Bootloader Arria 10 HPS e Version the SSBL version to use This release only supports the default 1 0 version e Use default locations checked by default to derive the location of the BSP from the location of the hardware handoff folder Uncheck if a custom path is desired instead Altera Corporation Boot Tools User Guide C Send Feedback ug 1137 2015 08 06 Using tcl Scripts 7 5 e BSP target directory the destination folder for new BSP files created by the generator This document refers to this as bsp directory The default directory name is spl bsp for the Arria V Cyclone V Preloader and uboot bsp for the Arria 10 Bootloader The directory name can be modified when Use default locations is unchecked e BSP settings file name the location and filename of the bsp file containing the BSP settings e Additional tcl scripting the location and filename ofa tcl script for overriding the default BSP settings 5 You can customize the BSP After creating or opening a bsp file access the Settings in the BSP Editor dialogue box The Settings are divided into Common and Advanced settings When you select a group of settings the controls for the selected settings appear on the right side of the dialogue box When you select a single setting the setting name description and value are displayed You can edit these settings in the BSP Editor dialogue box 6 Click Generate to generate the BSP 7 Click Ex
47. ebug Run History Run As Run Configurations Debug History Debug As Debug Configurations Toggle Breakpoint Ctrl Shift B Toggle Line Breakpoint Toggle Method Breakpoint Toggle Watchpoint arm altera eabi ot X Skip All Breakpoints arm altera eabi na 12 50 07 Build Fin Creating a New Debug Configuration A Remove All Breakpoints Breakpoint Types Manage Python Exception Breakpoints Disable Step into properties A Debug Configuration is created in the Debug Configurations window by selecting DS 5 Debugger as the type of configuration in the left panel and then right clicking with the mouse and selecting the New menu option ARM DS 5 AE C Send Feedback Altera Corporation ug 1137 6 20 Creating a New Debug Configuration 2015 08 06 Figure 6 18 Create New Debug Configuration Create manage and run configurations Create edit or choose a configuration to launch a DS 5 debugging session 75 X amp 2 Configure launch settings from this dialog type filter text 9 Press the New button to create a configuration of the selected type c C C Applicatic Press the Duplicate button to copy the selected configuration C Attach t E oce X Press the Delete button to remove the selected configuration Press the Filter button to configure filtering options or view an existing configuration by selecting it Duplicate X Delete launch perspecti
48. ect types and toolchains only if they are supported on the platform Le Jansen Build Settings Once the project is created the project properties can be accessed by going to Project gt Properties ARM DS 5 AE LJ Send Feedback Altera Corporation 6 8 Build Settings Figure 6 6 Project Properties File Edit Source Refactor Navigate Search Project Run Window Help ug 1137 2015 08 06 Open Project Close Project Build All Build Configurations Build Project Build Working Set Clean v Build Automatically Make Target C C Index Properties i Problems X 4j Tasks E Console 7 Properties 0 items Description Resource Path Then in the Project Properites window the Compilation settings can be accessed by selecting C C Build gt Settings Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 Figure 6 7 Project Settings type filter text Resource Builders 4 C C Build Build Variables Environment Logging Settings Tool Chain Editor C C General Project References Run Debug Settings Settings Configuration Debug Active Y Manage Configuratio ARM Compiler Bare Metal Project Management 6 9 a GCC C Compiler Q3 Target 3 Preprocessor Q3 Symbols Includes Q3 Optimization Debugging Q3 Warnings Q9 Miscellaneous 4 GCC Assembler Q9 Target Symbols Q3 Includes 9 Debugging Q9 Warnings
49. eloader mkpimage bin with the mkpimage tool The makefile contains the following targets e make all compiles the preloader e make clean deletes preloader mkpimage bin from the bsp directory e make clean all deletes bsp directory including the source files in the directory Building the Arria 10 Bootloader The following figure presents the Arria 10 Bootloader build flow as performed by the generated Makefile when invoking make In order to keep the illustration simple the generated Makefile itself is not shown Figure 7 11 Arria 10 Bootloader Build Flow User Options B ootloader Device Tree Binary Handoff Folder SSBL Bootloader XML Files Generator Device Tree Bootable D Combined Image Combined Binary Legend cum Part of SoC EDS Bootloader Compiler Bootloader Source Code Toolchain Binary Warning For this release of the tools the Bootloader compilation is only supported on Linux host machines The Bootloader compilation It is not supported on Windows host machines The rest of the flow is supported on both Linux and Windows host machines Note The Bootloader needs to be recompiled only when the boot source is changed SD MMC and QSPI are currently supported The Bootloader does not need to be recompiled when other settings are changed as those settings are encapsulated in the Bootloader Device Tree Altera Corporation Boot Tools User Guide C Send Fee
50. ensing The ARM License Manager uses the Eclipse settings to connect to the Internet The default Eclipse settings use the system wide configuration for accessing the Internet In case the License Manager cannot connect to the Internet you can try to change the Proxy settings by going to Window gt Preferences gt General gt Network Connections Ensure that HTTPS proxy entry is configured and enabled 8 After a few moments the ARM Ds 5 will activate the license and display it in the License Manager Click Close Figure 3 7 ARM License Manager amp ARM License Manager View and edit licenses Configure licenses and diagnose licensing problems Configuration Diagnostics D i Add License Delete License Select the toolkit that you intend to use DS 5 Altera Edition ARN 3 Related Information ARM website Getting the License on page 3 1 Licensing Altera Corporation LJ Send Feedback Embedded Command Shell 2015 08 06 ug 1137 amp Subscribe E Send Feedback The purpose of the embedded command shell is to provide an option for you to invoke the SoC EDS tools It enables you to invoke the SoC EDS tools without qualifying them with the full path Commands like eclipse bsp editor or arm altera eabi gcec can be executed directly On Windows the embedded command shell is started by running lt SoC EDS installation directory gt Embedded_Command_Shell bat
51. er TestProject D c gt RemoteSystemsTempFiles 4 cS TestProject Debug File name scatter scat uses Nen 4 The linker script file can be edited directly as shown in the example below Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 Linker Script 6 15 Figure 6 13 Linker Script Example 8 scatter scat 22 ENS 1 OCRAM exFFFFGG00 0x10000 2 3 APP CODE 40 5 4RO RW 4ZI 6 7 8 Application heap and stack 9 ARM LIB STACKHEAP 40 EMPTY 0x4000 10 tg 11 12 4 p Regions Sections scatter scat 5 The file can also be edited by using the tools on the Outline view for the file ARM DS 5 AE Altera Corporation LJ Send Feedback 1137 6 16 Build Settings Di ROS Figure 6 14 Editing Scatter scat File Using Tools on the Outline View p x Bz Outline 23 Make Target ER ese ok eX Y 4 E TestProject 4 9 OCRAM gt iS Includes z 4 Ot APP CODE 4 Debug 4RO RW ZI RO RW ZD L makefile ARM IIR STACKHFAP objects n Add load region sources r 3 Application oe io e ice ai jg Add execution region subdir m i E Add section B test d ler test o TestProje 6 test c 8 scatter scat Regions Sections scatter scat Rename Delete 2i Problems Tasks E Console Properties E Commands x Linked no current context No debugger is currently connected
52. er empty Exception Vector Header Exception Vector Altera Corporation Boot Tools User Guide LJ Send Feedback ug 1137 2015 08 06 Operation 7 23 Operation The mkpimage tool runs on a host machine The tool generates the header and CRC checksum and inserts them into the output image with the SSBL program image and its exception vector For certain flash memory tools the position of the SSBL images must be aligned to a specific block size the mkpimage tool generates any padding data that may be required The mkpimage tool optionally decodes and validates header information when given a pre generated SSBL image As illustrated the binary SSBL image is an input to the mkpimage tool The compiler leaves an empty space between the SSBL exception vector and the program The mkpimage tool overwrites this empty region with header information and calculates a checksum for the whole image When necessary the mkpimage tool appends the padding data to the output image The mkpimage tool can operate with either one or four input files Operation on four input files consists in processing each file individually then concatenating the four resulted images Header File Format The mkpimage header file format has two versions e Version 0 used for Cyclone V and Arria V SSBL Preloader e Version 1 used for Arria 10 SSBL Bootloader For Version 0 used for Cyclone V and Arria V Preloader the header includes the following e Validation
53. er containing files generated from the hardware handoff files For Arria 10 Bootloader BSPs the generated files include the following settings bsp file containing all BSP settings Makefile makefile used to compile the Bootloader convert the Bootloader device tree file to binary and create the combined Bootloader and Bootloader Device Tree image for more information refer to Preloader Compilation config mk makefile configuration file containing the boot source selection and whether the Bootloader compilation is selected devicetree dts Bootloader device tree containing the Bootloader customization details derived from the handoff files and the user settings uboot ds ARM DS 5 script that can be used to download and debug the Bootloader on a target device BSP Settings This section lists all the available BSP settings which can be accessed from either the Graphical User Interface application bsp editor or from the command line tools bsp create settings bsp update settings bsp query settings The available BSP settings are different between Cyclone V and Arria V SSBL Preloader and Arria 10 SSBL Bootloader Boot Tools User Guide Altera Corporation LJ Send Feedback 7 10 Cyclone V and Arria V BSP Settings Cyclone V and Arria V BSP Settings Table 7 5 Cyclone V and Arria V BSP Settings Spl PRELOADER TGZ spl CROSS_COMPILE String String SoC EDS installation director
54. era SoC devices The Altera SoC EDS contains development tools utility programs run time software and application examples that enable firmware and application software development on the Altera SoC hardware platform Overview The Altera SoC EDS enables you to perform all required software development tasks targeting the Altera SoCs including Board bring up Device driver development Operating system OS porting Bare metal application development and debugging OS and Linux based application development and debugging Debug systems running symmetric multiprocessing SMP Debug software targeting soft IP residing on the FPGA portion ofthe device The major components of the SoC EDS include ARM Development Studio 5 DS 5 AE AE Toolkit Compiler tool chains e Bare metal GNU Compiler Collection GCC tool chain from Mentor Graphics Bare metal compiler e Linux GCC compiler tool chain from Linaro Pre built Linux package including e Linux kernel executable e U boot image e Bootloader Device Tree Device tree blob consumed by u boot for A10 e Linux Device Tree Device tree blob consumed by Linux e Secure Digital SD card image e Script to download Linux source code from the GitHub repository SoC Hardware Library HWLIB O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and re
55. es run the command jtagconfig It will list the available cables like in the following example jtagconfig 1 USB Blaster USB 0 2 USB Blaster USB 1 3 USB Blaster USB 2 The c parameter can be the number of the programming cable or its name The following are valid examples for the above case c 1 c USB Blaster USB 2 HB BH Yes ifthereare This option specifies the index of the HPS multiple HPS device The tool will automatically detect the devices in the chain and determine the position of the HPS chain device however if there are multiple HPS devices in the chain the targeted device index must be specified HPS Flash Programmer User Guide Altera Corporation LJ Send Feedback HPS Flash Programmer Command Line Examples ug 1137 2015 08 06 Short Required Description Option operation This option specifies the operation to be performed The following operations are supported e IL Read IDCODE of SOC device and discover Access Port e S Read Silicon ID of the flash e E Erase flash e B Blank check flash e P Program flash e V Verify flash e EB Erase and blank check flash e BP Program lt BlankCheck gt flash e PV Program and verify flash e BPV Program blank check and verify flash e X Examine flash Note The program begins with erasing the flash operation before programming the flash by default addr Yes if the start address is not 0
56. ex A9 Settings 201 ires Cortex A9 Settings The Cortex A9 tab allows the selection of the desired core tracing options Figure 6 32 DTSL Configuration Editor Cortex A9 Cross Trigger Trace Buffer Cortex A9 gt STM ETR ETF 4 Enable Cortex A9 0 trace V Enable Cortex A9 1 trace PTM Triggers halt execution 4 Enable PTM Timestamps Timestamp period 4000 4 Enable PTM Context IDs Context ID Size 32 bit Y Cycle Accurate Trace capture range 0x0 OxFFFFFFFF The following Core Tracing Options are available e Enable Cortex A9 0 core trace check to enable tracing for core 0 e Enable Cortex A9 1 core trace check to enable tracing for core 1 e PTM Triggers halt execution check to cause the execution to halt when tracing Enable PTM Timestamps check to enable time stamping e Enable PMT Context IDs check to enable the context IDs to be traced Context ID Size select 8 16 or 32 bit context IDs Used only if Context IDs are enabled Cycle Accurate check to create cycle accurate tracing Trace capture range check to enable tracing only a certain address interval e Start Address End Address define the tracing address interval Used only if the Trace Capture Range is enabled STM Settings The STM tab allows you to configure the System Trace Macrocell STM Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 ETR Settings 6 35 Figure 6 33 DTSL Co
57. f Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 SoC Embedded Design Suite User Guide Document Revision History 1 4 2015 08 06 ug 1137 ca Subscribe Send Feedback e T vesen T ceas August 2015 2015 08 06 Added Arria 10 Removed content of the Getting Started Guides chapter and moved it to the Altera Wiki 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countrie
58. fy disk drive letter to write to options error disk not specified SD Card Boot Utility Altera Corporation CJ Send Feedback Linux Software Development Tools 2015 08 06 ug 1137 amp Subscribe E Send Feedback The Linux software development tools are listed below The Linux compiler and the linux device tree generator are described in the following sections of this chapter e Linux compiler SD card boot utility e Linux device tree generator DTG Linux Compiler on page 12 1 Linux Device Tree Generator on page 12 2 Related Information SD Card Boot Utility on page 11 1 Linux Compiler The Linaro Linux compiler version 4 8 3 is shipped with the SoC EDS For more information about the Linux compiler and to download the latest version of the tools refer to the download page at the Linaro website The compiler is a GCC based arm linux gnueabihf port It targets the ARM processor it assumes the target platform is running Linux and it uses the GNU embedded application binary interface EABI hard float HF conventions The Linux compiler is installed as part of the ARM DS 5 AE which is installed as part of the SoC EDS The compilation tools are located at lt SoC EDS installation directory gt ds 5 bin The Linux compiler comes with full documentation located at lt SoC EDS installation directory gt ds 5 documents gcc The documents are provided as HTML files Some of the provided documents are e Compiler ma
59. g Board Setup Running Linux Running the Tools Second Stage Bootloader Baremetal Debugging Hardware Libraries HWLibs Peripheral Register Visibility Baremetal Project Management Linux Application Debugging Linux Kernel and Driver Debugging Tracing Related Information SoCEDSGettingStarted Wiki Page For more information on how to access the Getting Started Guides 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Iso 9001 2008 Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134
60. gging You can perform them both in the Web and Subscription editions For more information see the Licensing section Related Information Licensing on page 3 1 Altera Corporation Introduction to SoC Embedded Design Suite C Send Feedback ug 1137 A 5 08 06 Hardware Software Development Flow 1 5 Hardware Software Development Flow The Altera hardware to software handoff utilities allow hardware and software teams to work independ ently and follow their respective familiar design flows Figure 1 1 Altera Hardware to Software Handoff di M posue aer Second Stage Handoff Bootloader 8 Bootloader Genertaor Hardware s Linux Device Tree Linux Device sopcinfo Design Generator Tree p aaen svd ds Debugger The following handoff files are created when the hardware project is compiled e Handoff folder contains information about how the HPS component is configured including things like which peripherals are enabled the pin MUXing and IOCSR settings and memory parameters e svd file contains descriptions of the HPS registers and of the soft IP registers on FPGA side implemented in the FPGA portion of the device e sopcinfo file contains a description of the entire system The handoff folder is used by the second stage bootloader generator to create the preloader For more information about the handoff folder refer to the BSP Generation Flow chapter The svd file contains the des
61. gistered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 101 Innovation Drive San Jose CA 95134 JA DTE RYA ug 1137 1 2 Linux Device Tree Binary 2015 08 06 Hardware to software interface utilities e Second stage bootloader generator e Linux device tree generator Sample applications Golden Hardware Reference Designs GHRD including e FPGA hardware project e FPGA hardware SRAM Object File sof file e Precompiled Second Stage Bootloaders e Preloader for Arria V and Cyclone V e Bootloader for Arria 10 Embedded command shell allowing easy invocation of the included tools SD Card Boot Utility Quartus II Programmer and SignalTap II Note T
62. gs 7 17 spl debug HARDWARE DIAGNOSTIC Boolean False Enable hardware diagnostic support To enable this at least IGB of memory is needed otherwise hardware diagnostic will fail to run properly Spl boot RAMBOOT PLLRESET Boolean True Execute RAM Boot PLL reset code on warm reset when CSEL 00 This option is required to enable correct warm reset functionality when using CSEL 00 When enabling this option the upper 4 KB of OCRAM are reserved and must not be modified by the user software Note Enabling this feature with CSEL 00 does not have any effect as the impacted code checks for this Arria 10 BSP Settings The Arria 10 BSP Settings are divided in four different groups e Main Group e MPU Firewall e L3 Firewall Group e F2S Firewall Group The following table presents the settings prefix to be added in front of the setting name for each of the groups They are presented in a table to make the rest of this section more readable Boot Tools User Guide CJ Send Feedback Altera Corporation 7 18 Arria 10 Main BSP Settings Group Table 7 6 Arria 10 BSP Firewall Setting Prefixes Settings Group Setting Group Prefix Main Group N A ug 1137 2015 08 06 MPU Firewall mpu_m0 noc_fw_ddr_mpu_fpga2sdram_ddr_scr L3 Firewall Group mpu m0 noc fw ddr 13 ddr scr F2S Firewall Group mpu m0 noc fw ddr mpu fpga2sd
63. he Linux package included in the SoC EDS is not an official release and is intended to be used only as an example Use the official Linux release described in the Golden System Reference Design GSRD User Manual available on the Rocketboards website or a specific release from the Git trees located on the GitHub repository for development Note The SoC EDS is tested only with the Linux release that comes with it Newer Linux releases may not be fully compatible with this release of SoC EDS Note The Golden Hardware Reference Design GHRD included with the SoC EDS is not an official release and is intended to be used only as an example For development purposes use the official GHRD release described in the GSRD User Manual available on the Rocketboards website Related Information Golden System Reference Design User Manual GitHub Repository Linux Device Tree Binary There are two different Linux device tree binary DTB file versions delivered as part of the SoC EDS The version from the prebuilt images folder socfpga cyclone5 dtb and socfpga_arria10 dtb are generic DTB files which do not have any dependency on soft IP FPGA programming and bridge releasing are not required before Linux starts running using this DTB This DTB file is intended for customers interested in bringing up a new board or just wanting to simplify their boot flow until they get to the Linux prompt If what is being developed or debugged does not involve the
64. he compound application of other functions in the HW Manager API to build more complex operations for example software controlled configuration of the FPGA Note The 15 0 1 release of the SoC EDS includes HW Manager support only for Cyclone V and Arria V SoCs Future versions will add support for Arria 10 SoC Hardware Library Reference Documentation Reference documentation for the SoCAL API and HW Manager API is distributed as part of the SoCEDS Toolkit This reference documentation is provided as online HTML accessible from any web browser The locations of the online SoC FPGA Hardware Library HWLIB Reference Documentation are e SoC Abstraction Layer SoCAL API Reference Documentation e Cyclone V and Arria V SoC EDS installation directory gt ip altera hps altera_hps doc soc_cv_av socal html index html Arria 10 SoC EDS installation directory lip altera hps altera hps doc soc a10 socal html index html e Hardware Manager HW Manager API Reference Documentation e Cyclone V and Arria V SoC EDS installation directory gt ip altera hps altera_hps doc hwmgr html index html Hardware Library Altera Corporation LJ Send Feedback HPS Flash Programmer User Guide 9 2015 08 06 ug 1137 amp Subscribe E Send Feedback The Altera Quartus II software and Quartus II Programmer include the HPS flash programmer Hardware designs such as HPS incorporate flash memory on the board to store FPGA configuration data or HPS prog
65. ift N gt Makefile Project with Existing Code Open File C Project Close Ctrl W C Project Close All Ctri Shifte W on Convert to a C C Project Adds C C Nature Source Folder Folder Source File Header File File from Template Class Ctri S Ctri Shift S Move Rename Refresh Convert Line Delimiters To d Qr DG 8I VARs Print Switch Workspace Restart Import Console Properties Export Properties Alt Enter 1 scatter scat altera 14 1 embedded 2 Select Scatter File Editor gt Scatter File and press Next Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 Figure 6 11 Creating a Scatter File Select a wizard Create a scatter file Wizards ARM DS 5 AE gt amp General gt g C C gt cvs gt DS 5 Configuration Database gt DS 5 Debugger 4 z DS 5 Platform Configuration Editor Platform Configuration File gt Java gt PyDev gt G Remote System Explorer 4 Scatter File Editor 8 Scatter File gt amp Target Configuration Editor Q m ezm 3 Select the location of the new file type in the file name and press Finish C Send Feedback Cancel Linker Script 6 13 Altera Corporation ug 1137 6 14 Linker Script 30150806 Figure 6 12 Create a New Scatter File Resource Scatter File Create a new scatter file resource Enter or select the parent fold
66. ing and Configuration chapter U Boot Image Tool mkimage Both the Preloader for Arria V Cyclone V and the Bootloader for Arria 10 require the presence of the U Boot image header at the beginning of the next stage boot image Depending on usage scenario other items that are loaded by either Preloader or Bootloader may also require the presence of the U Boot image header Boot Tools User Guide Altera Corporation J send Feedback ug 1137 7 28 Tool Options 2015 08 06 The mkimage utility is delivered with SoC EDS and can be used to append the U Boot image header to the next stage boot image or any other required files Figure 7 8 mkimage Header 0x0040 Input File 0x0000 mkimage Signature Header The header consists of the following items Image magic number determines if the image is a valid boot image e Image data size the length of the image to be copied e Data load address the entry point of the boot image not used for items that are not bootable images Operating system determines the type of image e Image name the name of the boot image e Image CRC the checksum value of the boot image Figure 7 9 mkimage Header Layout 0x0040 0x0030 Image Name 0x0020 0x0010 Data Load Address Entrypoint Image CRC OA T Cc 0x0000 Magic Number Header CRC Timestamp Image Data Size 0x4 0x8 OxC O Operating System A Architecture T Type C Compression
67. ing on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 ug 1137 10 2 Bare Metal Compiler 201 nbs Related Information e Mentor Graphics e SoC EDS Getting Started Guides Bare Metal Compiler C Send Feedback Altera Corporation SD Card Boot Utility 1 1 2015 08 06 ug 1137 amp Subscribe E Send Feedback The SoC EDS SD card boot utility is a tool for updating the boot software on an SD card The Preloader is typically stored in a custom partition with type 0xA2 on the SD card Optionally the next boot stage usually the Bootloader can also be stored on the same custom partition Since it is a custom partition without a file system the Preloader and or Bootloader cannot be updated by copying the new file to the card and a software tool is needed The SD card boot utility allows the user to update the Preloader and or Bootloader on a physical SD card or a disk image file The utility is not intended to create a new bootable SD card or disk image file from scratch In order to do that it is recommended to use fdisk on a Linux host OS Related Information Linux Software Development Tools on page 12 1 Usage Scenarios This utility is intended to update boot software on that resides on an existing e Existing SD card e Existing disk image file You can choose from these three usage scenarios e Update just the Preloader software e
68. ing problems Select the toolkit that you intend to use No toolkits available 4 In the Add License Obtain a new licenses dialog box select the type of license to enter In this example select the radio button Enter a serial number or activation code to obtain a license to enter the choices listed below When done click Enter a ARM License Number for Subscription Edition b ARM License Activation Code for Web Edition and 30 Day Evaluation Altera Corporation Licensing C Send Feedback ug 1137 2015 08 06 Activating the License 3 5 Figure 3 4 Add License Obtain a New License Obtain a new license Select the type of license to create for this computer Enter a serial number or activation code Use an existing license file or license server address Generate a 30 day evaluation license Manually obtain a license via www arm com website 5 Click Next 6 In the Add License Choose Host ID dialog box select the Host ID Network Adapter MAC address to tie the license to If there are more than one option select the one you desire to lock the license to and click Next Licensing Altera Corporation LJ Send Feedback ug 1137 3 6 Activating the License 2015 08 06 Figure 3 5 Add License Choose host ID Choose host ID Choose a host ID that the license will be locked to The license is locked to the selected host ID ARM recommends selec
69. it to exit the BSP Generator GUI Using tcl Scripts Instead of using the default settings you can create a tcl script file tcl to define custom settings during BSP creation set settingis the only available tcl command Refer to BSP Settings for a list of available settings The following shows example commands that are used to set parameters in the BSP settings file set setting spl boot BOOT FROM QSPI true set setting spl boot QSPI NEXT BOOT IMAGE 0x50000 Related Information BSP Settings on page 7 9 BSP Generator Command Line Interface The BSP command line tools can be invoked from the embedded command shell and provide all the features available in the BSP Generator GUI The bsp create settings tool creates a new BSP settings file The bsp update settings tool updates an existing BSP settings file e The bsp query settings tool reports the setting values in an existing BSP settings file The bsp generate files tool generates a BSP from the BSP settings file Note Help for each tool is available from the embedded command shell To display help type the following command lt name of tool gt help bsp create settings The bsp create settings tool creates a new BSP settings file with default settings You have the option to modify the BSP settings or generate the BSP files as shown in the following example Boot Tools User Guide Altera Corporation CJ Send Feedback ug 1137 7 6 bsp update settings
70. l disks in Linux just specify the device file For example dev mmcblk0 For physical disks in Windows specify the physical drive path such as WA physicaldrive2 or use the drive letter option d to specify a drive letter The drive letter option is the easiest method in Windows d Optional h Optional specify disk drive letter to write to Example d E When using this option the disk file option cannot be specified Displays help message and exits version Optional Displays script version number and exits Altera Corporation SD Card Boot Utility C Send Feedback ug 1137 2015 08 06 Tool Options 11 3 Figure 11 1 Sample Output from Utility alt boot disk util Altera Boot Disk Utility Copyright C 1991 2014 Altera Corporation Usage write preloader to disk alt boot disk util p preloader a write disk file write bootloader to disk alt boot disk util b bootloader a write disk file write BOOTloader and PREloader to disk alt boot disk util p preloader b bootloader a write disk file write BOOTloader and PREloader to disk drive E alt boot disk util p preloader b bootloader a write d E Options version show program s version number and exit h help show this help message and exit b FILE bootloader FILE bootloader image file p FILE preloader FILE preloader image file a ACTION action ACTION only supports write action d DRIVE drive DRIVE speci
71. lash address starting at 1 MB are erased using a cable M Example 9 8 Examine Data from Flash quartus hps c 1 o X a 0x98679 s 56789 output bin examines 56789 bytes of data from the flash with a 0x98679 flash start address using a cable M HPS Flash Programmer User Guide Altera Corporation LJ Send Feedback 9 6 Supported Memory Devices Supported Memory Devices Table 9 2 QSPI Flash ug 1137 2015 08 06 Micron 0x18BA20 Micron 0x19BA20 1 256 Micron 0x20BA20 2 512 Micron 0x21BA20 4 1024 Micron 0x18BB20 1 128 Micron 0x19BB20 1 256 Micron 0x20BB20 2 512 Micron 0x21BB20 4 1024 Micron 0x132020 1 4 Spansion 0x182001 1 128 Sector size of 64 KB Spansion 0x182001 1 128 Sector size of 256 KB Spansion 0x190201 1 256 Sector size of 64 KB Spansion 0x190201 1 256 Sector size of 256 KB Spansion 0x200201 1 512 Table 9 3 ONFI Compliant NAND Flash Micron 0x2C 0x68 Micron 0x2C 0x48 16 Micron 0x2C OxAI1 8 Micron 0x2C OxF1 8 Altera Corporation HPS Flash Programmer User Guide C Send Feedback ug 1137 aS 2015 08 06 Supported Memory Devices E Note Starting with version 14 1 the HPS Flash Programmer supports all ONFI compliant NAND flash devices that are supported by the HPS QSPI Flash Controller Note Starting with version 15 0 1 the HPS Flash Programmer supports the Cyclone V Arria V and Arria 10 SoC devices HPS Flash P
72. mal Oxffff MPU Firewall region limits mpuregion2addr limit mpuregion3addr limit Arria 10 Bootloader L3 Firewall BSP Settings Group Table 7 9 Arria 10 Bootloader L3 Firewall BSP Settings Group hpsregion0enable True nable hpsregionlenabl False nable hpsregion2enable False nable hpsregion3enabl False Boolean Enable L3 Firewall regions nable hpsregion4enabl False nable hpsregion5enable False nable hpsregion6enable False nable hpsregion7enabl False Boot Tools User Guide Altera Corporation LJ Send Feedback Arria 10 Bootloader L3 Firewall BSP Settings Group hpsregionOaddr base hpsregionladdr base hpsregion2addr base hpsregion3addr hpsregion4addr base base hpsregionb5addr base hpsregion6addr base hpsregion7addr base Hexadecimal ug 1137 2015 08 06 0x0 L3 Firewall region bases hpsregion0addr l imi hpsregionladdr l imi hpsregion2addr 1 imi hpsregion3addr l imi hpsregion4addr l imi hpsregion5addr l imi hpsregion6addr 1 imi hpsregion7addr 1 Altera Corporation imi Hexadecimal Oxffff L3 Firewall region limits Boot Tools User Guide C Send Feedback 1137 201 5 08 06 Arria 10 Bootloader F2S Firewall BSP Settings Group 7 21 Arria 10 Bootloader F2S Firewall BSP Settings Group
73. n additional bootloader stage which then is used to load an operating system For Arria 10 devices there is no need for an additional bootloader stage because the OCRAM size is 256 KB and the required functionality is included in the SSBL This chapter presents the tools that are used to enable the SSBL management e SSBL Support Package Generator enables the user to create and manage the SSBL e SSBL Image Tool mkpimage enables to user to add the boot ROM required header on top of the SSBL U Boot Image Tool mkimage enables the user to add the SSBL required header on top of the files loaded by SSBL O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in w
74. n directory host_tools mentor gnu arm baremetal share doc sourceryg arm altera eabi The documentation is offered in four different formats to accommodate various user preferences e HTML files e Info files e Man pages PDF files Among the provided documents are e Compiler manual e Assembler manual e Linker manual e Binutils manual GDB manual e Getting Started Guides e Libraries Manual 9 The Getting Started Guides are located on the SoCEDSGettingStarted page on the Altera Wiki O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before rely
75. ncscesicasscencsediveceseaccusedaschtcassssndardecsstucaosiveses 4 1 Getting Started Guldes e ooo Ebr b FUR RE EPUREI NAE ENDE WEN ERE ERES 5 1 PURINE DSS q d 6 1 Starting Eclipse ARM DS AE nistaire n aene dea ices dv ERISQUE ie rto a p 6 1 Pare Mletal Project Masiabemehl ceu SR rape RD BG DDR dM TI ap qe Md DR ER 6 2 Bare Metal Project Management Using Makefiles ssssssoissssssssstsosssenssssssossessonsisasensoesisussesasonss 6 2 GGC Based Bare Metal Project Mabapemehl ese eosqenqertom e gen bhekn an RH Dd peel De ED indian 6 5 ARM Compiler Bare Metal Project Management iccaisssassssiecsatsccsssacissosssssascastsssonvesesnssnsavesssesss 6 9 Bus p S 6 18 Accessing Debug Com SUPA OIG aces quib tn anat Du en Gel mad RECIEN HDD tuU 6 19 Creating d New Debug Cantor alii ob opima piec etae ERU Pete teil ruri Qune E REEL HA DLL KE 6 19 Debug Config ration ODEOBS uos dutteinnael t atr ux M abb eeu ERI Ta pO MUR X dada R 6 21 DISL Options titt Der e crie rc d rd ee A ER ERU c CREER RE o 6 31 BOGE Tools User Gunde T 7 1 TALI EURO hse casas en 7 1 Second Stage Bootloader Support Package Generator sse 7 2 Altera Corporation BSP Generation PION 7 2 BSP Generator Graphical User Interfaces ieionsaessenranndinnnenianbulamuamenen 7 4 BSP Generator Command Lin
76. nd Feedback The Altera SoC FPGA Hardware Library HWLIB was created to address the needs of low level software programmers who require full access to the configuration and control facilities of SOC FPGA hardware An additional purpose of the HWLIB is to mitigate the complexities of managing the operation of a sophisticated multi core application processor and its integration with hardened IP peripheral blocks and programmable logic in a SoC architecture Figure 8 1 HW Library Application Bare metal Operating Application System Hardware Within the context of the SOC HW SW ecosystem the HWLIB is capable of supporting software develop ment in conjunction with full featured operating systems or standalone bare metal programming environments The relationship of the HWLIB within a complete SOC HW SW environment is illustrated in the above figure 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to a
77. nfiguration Editor STM Cross Trigger Trace Buffer Cortex A9 STM gt ETR ETF Enable STM trace Only one option is available e Enable STM Trace check to enable STM tracing ETR Settings The ETR settings allow the configuration of the Embedded Trace Router ETR settings The Embedded Trace Router is used to direct the tracing information to a memory buffer accessible by HPS Figure 6 34 DTSL Configuration Editor ETR Cross Trigger Trace Buffer Cortex A9 STM ETR gt ETF 4 Configure the system memory trace buffer Start address 0x100000 Size 0x8000 Enable scatter gather mode The following options are available e Configure the system memory trace buffer check this if the ETR is selected for trace destination on the Trace Capture tab e Start Address Size define the trace buffer location in system memory and its size e Enable scatter gather mode use when the OS cannot guarantee a contiguous piece of physical memory The scatter gather table is setup by the operating system using a device driver and is read automatically by the ETR ETF Settings The ETF tab allows the configuration of the Embedded Trace FIFO ETF settings The Embedded Trace FIFO is a 32KB buffer residing on HPS that can be used to store tracing data to be retrieved by the debugger but also as an elastic buffer for the scenarios where the tracing data is stored in memory through ETR or on the external DSTREAM device using TPIU
78. ng will force the corresponding peripheral to remain in reset You must ensure the debugger does not read registers from these components spl warm reset handshake FPGA Boolean True This setting enables the reset manager to perform handshake with the FPGA before asserting a warm reset spl warm reset handshake ETR Boolean True This setting enables the reset manager to request that the Embedded Trace Router ETR stalls the Advanced eXtensible Interface AXI master and waits for the ETR to finish any outstanding AXI transactions before asserting a warm reset of the L3 interconnect or a debug reset of the ETR Altera Corporation Boot Tools User Guide CJ Send Feedback ug 1137 2015 08 06 Cyclone V and Arria V BSP Settings 7 15 Spl warm reset handshake SDRAM Boolean False Note This option allows the SDRAM contents to be preserved accros warm resets Note When using this option the SDRAM controller is not completely re initial ized when coming back from warm reset This may bea problem whenever the warm reset is generated by the Watchdog asa consequence of an SDRAM controller failure Also the SDRAM PLL is not re initial ized when this option is enabled and the system comes out of the warm reset Boot Tools User Guide LJ Send Feedback Altera Corporation 7 16 Cyclone V and Arria V BSP
79. ns e RTOS Awareness e Arguments e Environment e Event Viewer Related Information Getting Started Guides For examples on how to use the ARM DS 5 AE debugging features e Online ARM DS 5 Documentation Refer to the DS 5 reference documentation for the complete details ARM DS 5 AE Altera Corporation LJ Send Feedback ug 1137 6 22 Connection Options 2015 08 06 Connection Options The Connection tab allows the user to select the desired target The following targets are available for the Altera platforms Arria 10 SoC e Bare Metal Debug e Debug Cortex A9 0 e Debug Cortex A9 1 e Debug Cortex A9x2 SMP e Linux Application Debug e Connect to already running gdbserver Download and debug application e Start gdbserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug Cortex A9 0 e Debug Cortex A9 1 e Debug Cortex A9x2 SMP Arria V SoC e Bare Metal Debug e Debug Cortex A9 0 e Debug Cortex A9 1 e Debug Cortex A9x2 SMP e Linux Application Debug e Connect to already running gdbserver Download and debug application e Start dbgserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug Cortex A9 0 e Debug Cortex A9 1 e Debug Cortex A9x2 SMP Cyclone V SoC Single Core e Bare Metal Debug e Debug Cortex A9 0 e Linux Application Debug e Connect to already running gdbserver e Download and debug application e Start dbgse
80. nual e Assembler manual e Linker manual e Binutils manual GDB manual e Getting Started Guide Related Information Linaro Website 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 ug 1137 12 2 Linux Device Tree Generator 2015 08 06 Linux Device Tree Generator A device tree is a data structure that describes the underlying hardware to an operating system primarily Linux By passing this data struct
81. ny 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 ug 1137 8 2 Feature Description 2015 08 06 The HWLIB provides a symbolic register abstraction layer known as the SoC Abstraction Layer SoCAL that enables direct access and control of HPS device registers within the address space This layer is necessary for enabling several key stakeholders boot loader developers driver developers board support package developers debug agent developers and board bring up engineers requiring a precise degree of access and control of the hardware resources The HWLID also deploys a set of Hardware Manager HW Manager APIs that provides more complex functionality and drivers for higher level use case scenarios The HWLIB has been developed as a source code distribution The intent of this model is to provide a useful set of out of the box functionality and to serve as a source code reference implementation that a user can tailor accordingly to meet their target system requirements The capabilities of the H
82. o responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 11 2 Tool Options ug 1137 2015 08 06 Warning The users of this tool need administrative or root access to their computer to use this tool to write to physical SD cards These rights are not required when only working with disk image files Please contact the IT department if you do not have the proper rights on your PC Tool Options The utility is a command line program The table describes all the command line options and the figure shows the help output from the tool Table 11 1 Command Line Options p filename Required Specifies Preloader file to write b filename Required Specifies Bootloader file to write a write Required Specifies action to take Only write action is supported Example a write disk file Required unless d option is used Specifies disk image file or physical disk to write to A disk image file is a file that contains all the data for a storage volume including the partition table This can be written to a physical disk later with another tool For physica
83. of 64 KB But it the NAND block is 128 KB then the Preloader images will need to be located at 128 KB intervals Serial NOR Flash Each QSPI boot image occupies an integer number of sectors unless subsector erase is supported this ensures that updating one image does not affect other images SD MMC The master boot record located at the first 512 bytes of the device memory contains partition address and size information The Preloader and Bootloader images are stored in partitions of type 0xA2 Other items may be stored in other partition types according to the target file system format You can use the fdisk tool to set up and manage the master boot record When the fdisk tool partitions an SD MMC device the tool creates the master boot record at the first sector with partition address and size information for each partition on the SD MMC Padding The mkimage tool inserts a CRC checksum in the unused region of the image Padding fills the remaining unused regions The contents of the padded and unused regions of the image are undefined Related Information e Arria V Hard Processor System Technical Reference Manual For more information please refer to the Booting and Configuration chapter e Cyclone V Hard Processor System Technical Reference Manual For more information please refer to the Booting and Configuration chapter Arria 10 Hard Processor System Technical Reference Manual For more information please refer to the Boot
84. omponent name in Qsys You must update the hardware handoff files and regenerate the BSP each time a hardware change impacts the HPS such as after pin multiplexing or pin assignment changes Arria 10 Flow For Arria 10 the BSP Generator creates a customized BSP consisting of a makefile and a Bootloader Device Tree There is no source code generated as all customization is encapsulated in the Bootloader Device Tree and makefile settings The makefile can be used to create the combined bootloader image which contains both the bootloader executable and the bootloader device tree The combined image can then be downloaded to a Flash device or FPGA RAM to be used for booting HPS Figure 7 4 Arria 10 SSBL Support Package Generator Flow User Options E EEE S D Bootloader Device Tree Source Hardware uantus T Handoff Folder SSBL Design XML Files Generator Gomiinedipoctionier Makefile and Bootloader Device Tree Image Legend Bootloader Source Code es Part of SoC EDS Boot Tools User Guide Altera Corporation CJ Send Feedback ug 1137 7 4 BSP Generator Graphical User Interface 3015 08 06 The hardware handoff information contains various settings that the user entered when creating the hardware design in Qsys and Quartus These include the following e Pin muxing for the HPS dedicated pins e T O settings for the HPS dedicated pins e Voltage e Slew rate Pull up down e Pin muxing for the shared pins e S
85. on which types of debugging scenarios are enabled Web edition e Linux application debugging over ethernet Subscription edition e JTAG based Bare Metal Debugging 30 day evaluation of the subscription edition K o bate Ko end Dova e Linux Application Debugging over Ethernet Getting the License Depending on the licensing option it is necessary to follow the steps detailed for each option to obtain the license Subscription Edition If you have purchased the SoC EDS Subscription Edition then you have already received an ARM license serial number This is a 15 digit alphanumeric string with two dashes in between You will need to use this number to activate your license in DS 5 as shown in the Activating the License section Free Web Edition For the free SoC EDS Web Edition you will be able to use DS 5 perpetually to debug Linux applications over an Ethernet connection Get your ARM license activation code from the SoC Embedded Design Suite download page on the Altera website and then activate your license in DS 5 as shown in the Activating the License section 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as
86. orporation CJ Send Feedback ug 1137 6 30 Arguments 201 5 08 06 Figure 6 25 RTOS Awareness Settings Name New_configuration 4 gt Connection Files Bs Debugger Ta OS Awareness 9 Arguments d Select OS awareness Uoc done FreeRTOS Keil CMSIS RTOS RTX Nucleus RTXC ThreadX embOS pC OS I p C OS IlI Related Information Keil Website For more information about RTOS Awareness refer to the Embedded Development Tools page on the Keil TM website Arguments The Arguments tab allows the user to enter program arguments as text Figure 6 26 Arguments Settings Name Sample Configuration lt 4 Connection Files Debugger i OS Awareness 69 Arguments P Environment Program Arguments E Environment The Environment tab allows the user to enter environment variables for the program to be executed ARM DS 5 AE C Send Feedback Altera Corporation ug 1137 2015 08 06 DTSL Options 6 31 Figure 6 27 Environment Settings Name Sample Configuration 4 Connection Files Debugger i OS Awareness Arguments Environment Target environment variables to set Variable Value New Edit Remove DTSL Options The Debug and Trace Services Layer DTSL provides tracing features To configure trace options in your projects Debug Configuration window in the Connection tab click the Edit button to open the DTSL Configuration window ARM DS 5 AE Altera C
87. orporation LJ Send Feedback 6 32 Cross Trigger Settings Zon S ROS Figure 6 28 Debug Configurations DTSL Options Edit Name Sample Configuration B Connection gt is Files 9 Debugger OS Awareness Arguments P Environment Select target Select the manufacturer board project type and debug operation to use Currently selected Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9 0 4 Altera Arria V SoC 4 Cyclone V SoC Dual Core 4 Bare Metal Debug Debug Cortex A9_0 Debug Cortex A9 1 Debug Cortex A9x2 SMP F gt Linux Application Debug gt Linux Kernel and or Device Driver Debug X Target Connection DTSL Options Configure USB Blaster trace or other target options Using default configuration DS 5 Debugger will connect to an Altera USB Blaster to debug a bare metal application Connections Bare Metal Debug Connection Browse Cross Trigger Settings The Cross Trigger tab allows the configuration of the cross triggering option of the SoC FPGA The following options are available e Enable FPGA gt HPS Cross Trigger for enabling triggers coming from FPGA to HPS Enable HPS gt FPGA Cross Trigger for enabling triggers coming from HPS to FPGA Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 Trace Capture Settings 6 33 Figure 6 29 DTSL Configuration Editor Cross Trigger Name of configuration default Trace Capture Cortex A9 Cross Trigger gt ST
88. ram data The HPS flash programmer programs the data into a flash memory device connected to an Altera SoC The programmer sends file contents over an Altera download cable such as the USB Blaster II to the HPS and instructs the HPS to write the data to the flash memory The HPS flash programmer programs the following content types to flash memory e HPS software executable files Many systems use flash memory to store non volatile program code or firmware HPS systems can boot from flash memory Note The HPS Flash Programmer is mainly intended to be used for programming the Preloader image to QSPI or NAND flash Because of the low speed of operation it is not recommended to be used for programming large files e FPGA configuration data At system power up the FPGA configuration controller on the board or HPS read FPGA configuration data from the flash memory to program the FPGA The configuration controller or HPS may be able to choose between multiple FPGA configuration files stored in flash memory e Other arbitrary data files The HPS flash programmer programs a binary file to any location in a flash memory for any purpose For example a HPS program can use this data as a coefficient table or a sine lookup table The HPS flash programmer programs the following memory types e Quad serial peripheral interface QSPI Flash e Open NAND Flash Interface ONFI compliant NAND Flash HPS Flash Programmer Command Line Utility You
89. ram ddr scr Arria 10 Main BSP Settings Group Table 7 7 Arria 10 Main BSP Settings Group uboot boot device String SD MMC Select the source for the boot image Possible values are SD MMC and QSPI uboot model String SOCFPGA Arrial0 Dev iati V Name of the board to be displayed when bootloader starts uboot peripheral rbf filename String periph rbf Peripheral rbf filename used to configure the I O when the source of boot image is SD MMC uboot core rbf filename String core rbf Core rbf filename used to configure the FPGA fabric when the source of boot image is SD MMC uboot disable uboot build Boolean False Can be used to disable building U Boot and just generate the Bootloader Device Tree file Altera Corporation Boot Tools User Guide CJ Send Feedback 1137 251 5 08 06 Arria 10 Bootloader MPU Firewall BSP Settings Group 7 19 Arria 10 Bootloader MPU Firewall BSP Settings Group Table 7 8 Arria 10 Bootloader MPU Firewall BSP Settings Group mpuregion0enable True nable mpuregionlenabl False Boolean Enable MPU Firewall Regions nable mpuregion2enable False nable mpuregion3enabl False mpuregionOaddr base mpuregionladdr base Hexadecimal 0x0 MPU Firewall region bases mpuregion2addr base mpuregion3addr base mpuregionOaddr limit mpuregionladdr limit Hexadeci
90. riting by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 7 2 Second Stage Bootloader Support Package Generator Second Stage Bootloader Support Package Generator The Second Stage Bootloader SSBL Support Package Generator provides an easy safe and reliable way to customize the SSBL for the Altera SoC devices The SSBL Support Package is referred to as BSP and the SSBL Support Package Generator is referred to as BSP Generator for the remainder of this document The BSP Generator allows you to perform the following tasks e Create a new BSP e Report BSP settings e Modify BSP settings e Generate BSP files The generated BSP includes a makefile which can be used to build the corresponding bootable Preloader or Bootloader image The BSP Generator functionality can be accessed from a Graphical User Interface or by using a set of command line tools which allow complete scripting of the flow BSP Generation Flow This section presents the BSP generation flow for both the Cyclone V and Arria V Preloader and Arria 10 Bootloader While the flows are similar there are some important differences Cyclone V and Arria V Flow For Cyclone V and Arria V the BSP Generator creates a customized BSP with preloader generic source files and
91. rogrammer User Guide Altera Corporation LJ Send Feedback Bare Metal Compiler 1 0 2015 08 06 ug 1137 amp Subscribe E Send Feedback The bare metal compiler that is shipped with the SoC EDS is the Mentor Graphics Sourcery CodeBench Lite Edition version 4 9 1 For more information on the Sourcery CodeBench Lite Edition and to download the latest version of the tools refer to the Mentor Graphics website The compiler is a GCC based arm altera eabi port It targets the ARM processor it assumes bare metal operation and it uses the standard ARM embedded application binary interface EABI conventions The bare metal compiler is installed as part of the SoC EDS installation in the following folder SoC EDS installation directory gt host_tools mentor gnu arm baremetal The Embedded Command Shell opened by running the script from the SoC EDS installation directory sets the correct environment PATH variables for the bare metal compilation tools to be invoked After starting the shell commands like arm altera eabi gcc can be invoked directly When the ARM DS 5 AE environment is started from the embedded command shell it inherits the environment settings and it can call these compilation tools directly Alternatively the full path to the compilation tools can be used SoC EDS installation directory gt host_ tools mentor gnu arm baremetal bin The bare metal compiler comes with full documentation located at lt SoC EDS installatio
92. ronment Target Configuration Application on host to download File System Workspace Load symbols Files Debugger Options The Debugger tab offers the following configurable options e Run Control Options e Option to connect only debug from entry point or debug from user defined symbol e Option to run user specified target initialization script e Option to run user specified debug initialization script e Option to execute user defined debugger commands Host working directory used by semihosting e Paths allows the user to enter multiple paths for the debugger to search for sources Paths can be added with button and removed with button Altera Corporation ARM DS 5 AE C Send Feedback 1137 2 5 08 06 RTOS Awareness 6 29 Figure 6 24 Debugger Settings fac Connection lien Files Be Debugger OS Awareness 69 Arguments PS Environment Run control Connect only Debug from entry point 9 Debug from symbol main Run target initialization debugger script ds py File System Workspace Run debug initialization debugger script ds py File System Workspace T Execute debugger commands Host working directory Use default S workspace_loc File System Workspace RTOS Awareness The RTOS Awareness tab allows the user to enable RTOS awareness for the debugger ARM DS 5 AE Altera C
93. rria V every Preloader image has to be aligned to a 64KB boundary except for NAND devices For NAND devices each Preloader image has to be aligned to the greater of 64 KB or NAND block size For Arria 10 every Bootloader image has to be aligned to a 256 KB boundary except for NAND devices For NAND devices each Bootloader image has to be aligned to the greater of 256 KB or NAND block size The following tables present typical image layouts that are used for QSPI SD MMC and NAND devices with block size equal or less to 64 KB for Cyclone V Arria V or 256 KB for Arria 10 Table 7 13 Typical Arria V Cyclone V Preloader Image Layout 0x30000 Preloader Image 3 0x20000 Preloader Image 2 0x10000 Preloader Image 1 0x00000 Preloader Image 0 Table 7 14 Typical Arria 10 Bootloader Image Layout 0xC0000 Bootloader Image 3 0x80000 Bootloader Image 2 Altera Corporation Boot Tools User Guide CJ Send Feedback ug 1137 2015 08 06 NAND Flash 7 27 0x40000 Bootloader Image 1 0x00000 Bootloader Image 0 The mkpimage tool is unaware of the target flash memory type If you do not specify the block size the default is 64 KB NAND Flash Each Preloader or Bootloader image occupies an integer number of blocks A block is the smallest entity that can be erased so updates to a particular boot image do not impact the other images For example for Cyclone V and Arria V a single Preloader image has a maximum size
94. rver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug Cortex A9 0 Cyclone V SoC Dual Core Altera Corporation ARM DS 5 AE C Send Feedback ug 1137 2015 08 06 Connection Options 6 23 e Bare Metal Debug e Debug Cortex A9 0 e Debug Cortex A9 1 e Debug Cortex A9x2 SMP e Linux Application Debug e Connect to already running gdbserver Download and debug application e Start dbgserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug Cortex A9 0 e Debug Cortex A9 1 e Debug Cortex A9x2 SMP Dual Arria V SoC Two Dual Core SoCs e Bare Metal Debug e Debug HPSO Cortex A9 0 e Debug HPS0 Cortex A9 1 e Debug HPSO Cortex A9x2 SMP e Debug HPS1 Cortex A9 0 e Debug HPS1 Cortex A9 1 e Debug HPS1 Cortex A9x2 SMP e Linux Application Debug e Connect to already running gdbserver Download and debug application e Start dbgserver and debug target resident application e Linux Kernel and or Device Driver Debug e Debug HPSO Cortex A9 0 e Debug HPSO Cortex A9 1 e Debug HPSO Cortex A9x2 SMP e Debug HPS1 Cortex A9 0 e Debug HPS1 Cortex A9 1 e Debug HPS1 Cortex A9x2 SMP Dual Cyclone V SoC Two Dual Core SoCs ARM DS 5 AE Altera Corporation C Send Feedback 6 24 Connection Options Bare Metal Debug Debug HPSO0 Cortex A9 0 Debug HPS0 Cortex A9 1 Debug HPSO Cortex A9x2 SMP Debug HPS1 Cortex A9 0 Debug HPS1 Cortex A9 1 e Debug
95. s All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134
96. s 7 11 boot FAT BOOT PARTITION Decimal Number When FAT partition support is enabled this specifies the FAT partition where the boot image is located Spl boot FAT LOAD PAYLOAD NAME String u boot img When FAT partition supported is enabled this specifies the boot image filename to be used Spl boot WATCHDOG ENABLE Boolean True This setting enables the watchdog during the preloader execution phase The watchdog remains enabled after the preloader exits Spl boot CHECKSUM NEXT IMAGE Boolean True This setting enables the preloader to validate the checksum in the subsequent boot image header information Spl boot EXE ON FPGA Spl boot STATE REG ENABLE Boolean Boolean False True This setting executes the preloader on the FPGA Select Spl boot EXE ON FPGA when the preloader is configured to boot from the FPGA This setting enables writing the magic value to the INITSWSTATE register in the system manager when the preloader exists this indicates to the boot ROM that the preloader has run successfully Boot Tools User Guide LJ Send Feedback Altera Corporation 7 12 Cyclone V and Arria V BSP Settings ug 1137 2015 08 06 Spl boot BOOTROM HANDSHAKE _ CFGIO Boolean True This setting enables handshake with boot ROM when configuring the IOCS
97. s including the bit fields comprising them e A loosely coupled software interface to the underlying hardware that promotes software isolation from hardware changes in the system address map and device register bit field layouts Note The 15 0 1 release of the SoC EDS includes SoCAL support for Cyclone V Arria V and Arria 10 SoCs Altera Corporation Hardware Library C Send Feedback 1137 2015 oiu Hardware Manager HW Manager 8 3 Hardware Manager HW Manager The Hardware Manager HW Manager component provides a group of functional APIs that address more complex configuration and operational control aspects of selected HPS resources The HW Manager functions have the following characteristics e Functions employ a combination of low level device operations provided by the SoCAL executed in a specific sequence to effect a desired operation e Functions may employ cross functional such as from different IP blocks device operations to implement a desired effect e Functions may have to satisfy specific timing constraints for the application of operations and validation of expected device responses e Functions provide a level of user protection and error diagnostics through parameter constraint and validation checks The HW Manager functions are implemented using elemental operations provided by the SoCAL API to implement more complex functional capabilities and services The HW Manager functions may also be implemented by t
98. sane 9 1 HPS Flash Programmer Command Line Utility scssssscssissesseiocearsssscsasnsosssapesccasspsdvenstassesiesesndesssassreipasnsese 9 1 How the HPS Flash Programmer WOTKS acaien doge bateria gm nid pe eria Kite wisis 9 1 Using the Flash Programmer from the Command Uitte secs cui aae tots retos taes bae poa deae 9 2 HPS Flash Programmet sss ree pin aud ec UM En Ea IQ 9 2 HPS Flash Programmer Command Line Examples sore ley R i d 9 4 Supported Memory Devices acts sscitscesaveshsccassecsssseisenswasewaayensctes scuctausges ou posannasaupes ic EM Ped EP PME 9 6 Dare Metal Gun Ie 10 1 SD Card Boot Utility D 11 1 Usage SCOMALIOS M 11 1 gMeUeIitP 11 2 Linux Software Development Tools eere eene 12 1 IB aderunt 12 1 Linux Device Tree Generator ett eet IR e REI B E S b E Ee sine PH E E Regn 12 2 Support and Peed Dak em 13 1 Altera Corporation TOC 4 SoC Embedded Design Suite User Guide Document Revision History Altera Corporation 2015 08 06 ug 1137 Introduction to SoC Embedded Design Suite 1 amp Subscribe E Send Feedback The Altera system on a chip SoC Embedded Design Suite EDS provides the tools needed to develop embedded software for Altera s SoC devices The Altera SoC EDS is a comprehensive tool suite for embedded software development on Alt
99. se If you do not have an active user account it can be created on the ARM Self Service page available on the ARM website 1 The first time the ARM DS 5 is run it notifies you that it requires a license Click the Open License Manager button Figure 3 1 No License Found a No Licenses Found ARM DS 5 is license managed but there are no registered licenses Use the ARM License Manager to obtain and add licenses You can open the ARM License Manager at any time from the Eclipse Help menu Ignore Open License Manager 2 Ifat any time it is required to change the license select Help gt ARM License Manager to open the License Manager Altera Corporation Licensing C Send Feedback ug 1137 2015 08 06 Activating the License 3 3 Figure 3 2 Accessing ARM License Manager g Welcome to DS 5 2 Help Contents 92 Search Dynamic Help Key Assist Ctrl Shift L Tips and Tricks Cheat Sheets ARM License Manager ARM Extras Check for Updates Install New Software e Problems 22 JA Tasks E 0 items About ARM DS 5 About Eclipse Platform 3 The License Manager View and edit licenses dialog box opens and shows that a license is not available Click the Add License button Licensing Altera Corporation LJ Send Feedback ug 1137 3 4 Activating the License 2015 08 06 Figure 3 3 ARM License Manager View and edit licenses Configure licenses and diagnose licens
100. set spl debug SEMIHOSTING 1 bsp generate files settings settings bsp bsp dir Use the bsp generate files tool when BSP files need to be regenerated in one of the following conditions e bsp create settings created the BSP settings but the bsp dir parameter was not specified so BSP files were not generated e bsp update settings updated the BSP settings but the bsp dir parameter was not specified so the files were not updated You want to ensure the BSP files are up to date Altera Corporation Boot Tools User Guide CJ Send Feedback ug 1137 2015 08 06 BSP Files and Folders 7 9 Table 7 4 User Parameters bsp generate files EE CREER C KH oen NN settings lt settings file gt Ye This option specifies the path to an existing BSP settings file bsp dir lt bsp dir gt Yes This option specifies the path where the BSP files are generated BSP Files and Folders The files and folders created with the BSP Generator are stored in the location you specified in BSP target directory in the New BSP dialog box For Cyclone V Arria Preloader BSPs the generated files include the following settings bsp file containing all BSP settings Makefile makefile used to compile the Preloader and create the preloader image for more informa tion refer to Preloader Compilation preloader ds ARM DS 5 script that can be used to download and debug the Preloader on a target device generated fold
101. sign Suite Download Center Installing the ARM DS 5 Altera Edition Toolkit Before you begin For the last step of the SoC EDS installation process start the ARM DS 5 AE Toolkit installer Note Make sure you have the proper setting to access the internet 1 2 3 ONAA Altera Corporation When the Welcome message is displayed click Next Accept the license agreement and click Next Accept the default installation path to ensure proper interoperability between SoC EDS and ARM DS 5 AE and click Next Click Install to start the installation process The progress bar is displayed When a driver installation window appears click Next Accept the driver installation and click Install After successful installation click Finish ARM DS 5 AE installation is complete Click Finish Installing the Altera SoC Embedded Design Suite GJ Send Feedback Licensing 2015 08 06 ug 1137 ES Subscribe G Send Feedback The SoC EDS is available with three different licensing options e Subscription edition e Free web edition e 30 day evaluation of subscription edition The only tool impacted by the selected licensing option is the ARM DS 5 AE All the other tools offer the same level of features in all licensing options for example the second stage bootloader generator and the bare metal compiler offer the same features no matter which licensing option is used The main difference between the licensing options depends
102. specifications before relying on any published information and before placing orders for products or services JANOS RYA 101 Innovation Drive San Jose CA 95134 ug 1137 9 2 Using the Flash Programmer from the Command Line 2015 08 06 The target portion is the HPS in the SoC The target accepts the programming data flash content and required information about the target flash memory device sent by the host The target writes the data to the flash memory device Figure 9 1 HPS Flash Programmer Host Computer Flash Download Cable e g USB Blaster Memory Device The HPS flash programmer determines the type of flash to program by sampling the boot select BSEL pins during cold reset you do not need to specify the type of flash to program Using the Flash Programmer from the Command Line HPS Flash Programmer The HPS flash programmer utility can erase blank check program verify and examine the flash The utility accepts a Binary File with a required bin extension The HPS flash programmer command line syntax is quartus hps options lt file bin gt Note The HPS flash programmer uses byte addressing HPS Flash Programmer User Guide C Send Feedback Altera Corporation 1137 2015 dbi HPS Flash Programmer 9 3 Table 9 1 HPS Flash Programmer Parameters Short Required Description Option CcSRBEE This option specifies what download cable to use To obtain the list of programming cabl
103. tate of HPS peripherals e Enabled e Disabled e Configuration of the bridges between HPS and FPGA e Clock tree settings e PLL settings e Clock divider settings e Clock gatting settings The handoff settings are output from the Quartus compilation and are located in the lt quartus project directory gt hps_isw_handoff directory The user must run the BSP Generator and re generate the Bootloader device tree each time a hardware change results in a change of the above parameters However the user does not have to always recompile the Bootloader whenever a hardware setting is changed The Bootloader needs to be recompiled only when changing the boot source BSP Generator Graphical User Interface You must perform the following steps to use the BSP Generator GUL bsp editor 1 Start an embedded command shell 2 Run the bsp editor command in the embedded command shell to launch the BSP Generator GUI 3 To open and modify an existing BSP project click File gt Open and browse to an existing bsp file 4 To create a new BSP project click File gt New HPS BSP to open the New BSP dialog box The New BSP dialog box includes the following settings and parameters e Preloader settings directory the path to the hardware handoff files The generator inspects the handoff files to verify the validity of this path Operating system Select the type of SSBL from the following two options e U Boot SPL Preloader Cyclone V Arria V HPS
104. the settings stored in the BSP settings file as shown in the following example Altera Corporation Boot Tools User Guide CJ Send Feedback ug 1137 2015 08 06 bsp query settings 7 7 Example 7 2 Updating a BSP Settings File The following command changes the value of a parameter inside the file settings bsp bsp update settings settings settings bsp set spl debug SEMIHOSTING 1 Table 7 2 User Parameters bsp update settings ENCORE EE CR ERE 77 NN settings lt settings file gt Ves This option specifies the path to an existing BSP settings file to update cose lt sbsp dir gt No This option specifies the path where the BSP files are generated When this option is specified bsp create settings generates the BSP files after the settings file has been created E RA o o No This option sets the BSP setting lt name gt to the value value Multiple instances of this option can be used with the same command Refer to BSP Settings for a complete list of available setting names and descriptions bsp query settings The bsp query settings tool queries the settings stored in BSP settings file as shown in the following example Example 7 3 Querying a BSP Settings File The following command will retrieve all the settings from settings bsp and displays the setting names and values bsp query settings settings settings bsp get all show names Table 7 3 User Parameters bsp query settings
105. ting the host ID of a physical device If a virtual device is selected the license will stop working 7 In the Add License Developer account details dialog box enter an ARM developer Silver account If you do not have an account it can be created easily by clicking the provided link After entering the account information click Finish Figure 3 6 Add License Developer Account Details Enter the ARM developer Silver account details Enter account details Email GD Password eeeeeeeccce Forgot password Click here to reset your password Don t have an account Click here to create one Note The License Manager needs to be able to connect to the Internet in order to activate the license If you do not have an Internet connection you will need to write down your Ethernet MAC Altera Corporation Licensing C Send Feedback 1137 201 5 08 06 Activating the License 3 7 address and generate the license directly from the ARM Self Service web page on the ARM website then select the Already have a license option in the License Manger Note Only the Subscription Edition with an associated license number can be activated this way The Web Edition and Evaluation edition are based on activation codes and these codes cannot be used on the ARM Self Service web page on the ARM website They need to be entered directly in the License Manager which means an Internet connection is a requirement for lic
106. ure to the OS kernel a single OS binary may be able to support many variations of hardware This flexibility is particularly important when the hardware includes an FPGA The Linux Device Tree Generator DTG tool is part of Altera SoC EDS and is used to create linux device trees for SoC systems that contain FPGA designs created using Qsys The generated device tree describes the HPS peripherals selected FPGA Soft IP and peripherals that are board dependent Note The Arria 10 Bootloader also has an associated Device Tree called Bootloader Device Tree that is created and managed by the BSP Editor tool Related Information e Altera Wiki For more information about the Linux DTG refer to the Altera Wiki website e Linux Device Tree Generator User Guide For more details navigate to the Device Tree Generator User Guide located on the Device Tree Generator Documentation page on the Rocketboards website Altera Corporation Linux Software Development Tools C Send Feedback Support and Feedback 2015 08 06 ug 1137 amp Subscribe E Send Feedback Altera values your feedback Please contact your Altera TSFAE or submit a service request at myAltera to report software bugs potential enhancements or obtain any additional information Related Information myAltera Account Sign In O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks o
107. ut Image Layout Boot Tools User Guide Altera Corporation LJ Send Feedback 7 26 ug 1137 Base Address 2015 08 06 Base Address Size The bootable SSBL image must be placed at 0x0 for NAND and QSPI flash For SD MMC the image can also be placed at 0x0 but typically the image is placed at offset 0x0 in a custom partition of type 0xA2 The custom partition does not have a filesystem on it The boot ROM is able to locate the partition using the MBR Master Boot Record located at 0x0 on the SD MMC card The mkpimage tool always places the output image at the start of the output binary file regardless of the target flash memory type The flash programming tool is responsible for placing the image at the desired location on the flash memory device For Cyclone V and Arria V a single Preloader has a maximum 60 KB image size You can store up to four preloader images in flash If the boot ROM does not find a valid preloader image at the first location it attempts to read an image from the next location and so on To take advantage of this feature program four preloader images in flash For Arria 10 a single Bootloader has a maximum 200 KB image size You can store up to four Bootloader images in flash If the boot ROM does not find a valid Bootloader image at the first location it attempts to read the next one and so on To take advantage of this feature program four Bootloader images in flash Address Alignment For Cyclone V and A
108. ve settings from the Perspectives preference page Ju JUnit amp Jython run 2 Jython unittest Filter matched 19 of 19 ite Q In the ARM DS 5 AE you can assign a default name to the configuration which you can edit Altera Corporation ARM DS 5 AE C Send Feedback 1137 aioe Debug Configuration Options 6 21 Figure 6 19 Rename Debug Configuration Create manage and run configurations 9 Configuration for connection type Bare Metal Debug is not valid Connection cannot be empty ax oi B Connection gt ion Files amp Debugger i OS Awareness 9 Arguments 1 c C C Application i3 mm i c C C Attach to Applic E C C Postmortem Det c C C Remote Applicat 4 Jk DS 5 Debugger 2p Altera SoCFPGA Hel 2 New configuration 4 Altera amp Iron Python Run Arria V SoC Select target Select the manufacturer board project type and debug operation to use Currently sele Altera Cyclone V SoC Dual Core Bare Metal Debug Debug Cortex A9_0 amp Iron Python unittest Java Applet e Python Run Cyclone V SoC Dual Core Cyclone V SoC Sinale Core g Python unittest LS 77 Filter matched 20 of 20 items Debug Configuration Options This section lists the Debug Configuration options which allows you to specify the desired debugging options for a project e Connection Options e File Options e Debugger Optio
109. y host tools altera preloader uboot socfpga tar gz arm altera eabi ug 1137 2015 08 06 This setting specifies the path to archive file containing the preloader source files This setting specifies the cross compilation tool chain for use spl boot BOOT FROM OSPI Boolean False spl boot BOOT_FROM_SDMMC Boolean True Spl boot BOOT FROM RAM Boolean False spl boot BOOT FROM NAND Boolean False Select the source for the subsequent boot image Note that only one source can be active at a time When using bsp create settings or bsp update settings you must turn off the boot option that is currently turned on before you can turn on a different boot option spl boot OSPI NEXT BOOT IMAGE Hexadecimal 0x60000 This setting specifies the location of the subsequent boot image in QSPI spl boot SDMMC NEXT BOOT IMAGE Hexadecimal 0x40000 This setting specifies the location of the subsequent boot image in SD MMC Spl boot NAND NEXT BOOT IMAGE Hexadecimal 0xC0000 This setting specifies the location of the subsequent boot image in NAND Spl boot FAT SUPPORT Boolean False Enable FAT partition support when booting from SD MMC Altera Corporation Boot Tools User Guide J send Feedback ug 1137 2015 08 06 Cyclone V and Arria V BSP Setting

Altera SoC Embedded Design Suite User Guide

Contents

Download Pdf Manuals

Related Search

Related Contents