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Tri-Rate Serial Digital Interface Physical Layer IP Core User's Guide

1. The VPID bytes byte1 byte2 byte3 and byte4 are combined into one 32 bit word as byte4 byte3 byte2 byte1 for input output purposes Thus vpid1 in vpid2 in vpid1 out and vpid2 out follow the same byte organization for mat given above The line number for VPID insertion is determined by counting the line numbers from field transi tions and using the video format from the input VPID bytes On the receive side the VPID bytes are extracted if present and given out through vpid1 out port and vpid2 out port if 3G b video is received If the ANC data packet is recognized as a VPID ANC packet based on DID and SDID matches then vp1 valid is asserted high If a valid VPID is available at the expected line numbers vp1 lineok is asserted If VPID is valid then vp1_cserr and vp1 parerr indicate the occurrence of checksum and parity errors respectively When receiving 3G b video the status and error signals for stream 2 video are given out through vp2 valid vp2 lineok vp2 cserr and vp2 parerr ports Integer Frame Rate Applications Figure 2 8 shows a typical IP configuration and its connection with the SERDES for integer frame rate transmission applications The figure does not list all the signals and connections only the essential ones In this configuration the SERDES is configured to use REFCLK for transmit reference clock and FPGA fabric clock fo
2. pg_std_num Ib lan in tg_hdn_in hd_sdn_in pg_std_num Decimal vid_format frame_format Content SD 0 0 0 XXXXO 0 1440 x 486 60i 4 2 2 0 0 0 xxxx1 1 1440 x 576 50i 4 2 2 HD 0 0 1 x0000 0 1920 x 1035 60i 4 2 2 0 0 1 x0001 1 1920 x 1080 50i 295M 4 2 2 0 0 1 x0010 2 1920 x 1080 30p 4 2 2 0 0 1 x0011 3 1920 x 1080 60i 4 2 2 0 0 1 x0100 4 1920 x 1080 25p 4 2 2 0 0 1 x0101 5 1920 x 1080 50i 4 2 2 0 0 1 x0110 6 1920 x 1080 24p 4 2 2 0 0 1 x0111 7 1280 x 720 60p 4 2 2 0 0 1 x1000 8 2048x1080 24p 4 2 2 3G A 0 1 1 00000 0 1920 x 1080 60p 4 2 2 IPUG82_01 5 December 2011 43 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Application Support Table 5 1 Pattern Generator Standards Continued pg_std_num Ib lan in tg_hdn_in hd sdn_in pg_std_num Decimal vid_format frame_format Content 0 1 1 00001 1 1920 x 1080 50p 4 2 2 0 1 1 00010 2 1280 x 720 60p 4 4 4 4 0 1 1 00011 3 1280 x 720 50p 4 4 4 4 0 1 1 00100 4 1920 x 1080 30p 4 4 4 4 0 1 1 00101 5 1280 x 720 30p 4 4 4 4 0 1 1 00110 6 1920 x 1080 25p 4 4 4 4 0 1 1 00111 7 1280 x 720 25p 4 4 4 4 0 1 1 01000 8 1920 x 1080 24p 4 4 4 4 0 1 1 01001 9 1280 x 720 24p 4 4 4 4 0 1 1 01010 10 1920 x 1080 60i 4 4 4 4 0 1 1 01011 11 1920 x 1080 50i 4 4 4 4 0 1 1 01100 12 1920 x 1080 30p 4 4 4 12 bits
3. g_std_num Ib lan in tg_hdn_in hd_sdn_in pg_std_num Decimal vid_format frame_format Content 1 1 1 01011 11 1920 x 1080 50i 4 4 4 4 1 1 1 01100 12 1920 x 1080 30p 4 4 4 12 bits 1 1 1 01101 13 1920 x 1080 25p 4 4 4 12 bits 1 1 1 01110 14 1920 x 1080 24p 4 4 4 12 bits 1 1 1 01111 15 1920 x 1080 60i 4 4 4 12 bits 1 1 1 10000 16 1920 x 1080 50i 4 4 4 12 bits 1 1 1 10001 17 1920 x 1080 30p 4 2 2 4 12 bits 1 1 1 10010 18 1920 x 1080 25p 4 2 2 4 12 bits 1 1 1 10011 19 1920 x 1080 24p 4 2 2 4 12 bits 1 1 1 10100 20 1920 x 1080 60i 4 2 2 4 12 bits 1 1 1 10101 21 1920 x 1080 50i 4 2 2 4 12 bits Only the integer frame rates 24p 30p 60i and 60p are shown in Table 5 1 but the corresponding fractional frame rates 23 98p 29 97p 59 94i and 59 94p can be generated by using the fractional clocks 74 175 MHz and 148 35 MHz Implementing and Testing the Sample Design The sample designs can be implemented by simply opening the provided Diamond or ispLEVER project files e In Diamond check Bitstream File under Export Files in the Process tab Then right click Bitstream File and choose Run e In ispLEVER run the Generate Bitstream Data process in the Project Navigator The VPB requires that both the LatticeECP3 and MachXO devices on it be programmed for proper operation The MachXO controls several peripheral devices on the board including the clock generator and clock cleaner chip sets The Mac
4. Table 3 1 provides the list of user configurable parameters for the Tri Rate SDI PHY IP core The parameter set tings are specified using the Tri Rate SDI PHY IP core Configuration GUI in IPexpress The numerous Tri Rate SDI PHY IP core parameter options are partitioned across multiple GUI tabs as shown in this chapter Table 3 1 Parameter Specifications for the Tri Rate SDI PHY IP Core Parameters Range Options Default PHY Settings PHY function Tx Rx Both Both Enable 3G Level B Yes No Yes LN insertion Off On On CRC insertion Off On On VPID insertion Off On On LDR path for SD Yes No No Include PLL for LDR Yes No No 10 bit mode for SD Tx Yes No Yes Separate data input for SD Yes No No SD data width 8 bits 10 bits dynamic 8 10 bits 10 bits VPID extraction Off On On 10 bit mode for SD Rx Yes No Yes Optional Ports Clock enable port Yes No No Custom Format Settings Custom format support for HD Yes No No Custom format support for 3G Yes No No Value or Range Value Range Value EAV2SAV cycles Value 200 to 8000 EAV2SAV cycles Minimum 200 to 8000 i EAV2SAV Cycles Maximum 200 to 8000 7 SAV2EAV Cycles Value 200 to 6000 SAV2EAV Cycles Minimum 200 to 6000 SAV2EAV Cycles Maximum 200 to 6000 Advanced Settings 3G HD SD Program time 1 10 3 Lock match threshold 1 10 3 Unlock error threshold 1 10 3 IPUG82_01 5 Decemb
5. Lattice 555555 Semiconductor a Corporation LatticeCORE Tri Rate Serial Digital Interface Phvsical Laver IP Core User s Guide December 2011 IPUG82 01 5 22 Semiconductor Table of Contents uuu Corporation Lattice Chapter 1 Introduction 5 Quick Facts RYN NR i YAR AN ta e i a Aaa PEENE ANENA 6 a LLE Lu as DYN YNN FY YW HD RY YY NN HWNN NF NF FYNN Ii 6 Video Interface and Source Format Suppott i 6 Chapter 2 Functional Description o cereo een nene en aaan A YWAA ASYN diana 8 FRECEIVER si a ii L A FE FE FR RH a i FU YR FN cans 8 Decoder Descrambler PA 9 Word Alignment TRS Detection esessesssssssseseseseeeen nennen nnne nennen nnn NAEK tnn sistere nnns entrer nennen 9 Rate Detection and Control ias ai re e E RUN X peak Ec Ee vex gu aeuo 9 Format Detection RE G 10 1013102101 a e cpm 10 XYZ Word Decoder eee eren XXE IN a EEEFPEAE a ER SERE ria 10 LIN DE COGER 10 Mp see m ET 11 A e 5 M 11 A A NO 11 CRC GOmiputation FY EEF DYF en sak dc NR FY RY FFRYNT tata 11 VPID Insertioni ica GG FN EFE FA a NF AI HYF FN KE 12 LN GRG InsertiOl ie T i 12 Scrambler Encode ri iecit P kw EEk EN p i i YNA DDN ej DN FR 12 L ow Speed SerialiZeri YN YRR
6. etc Only families that support the particular IP core are listed e Part Name Specific targeted part within the selected device family IPUG82_01 5 December 2011 32 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor IP Core Generation Figure 4 1 IPexpress Dialog Box Diamond Version En IPexpress On e IPS Y Tri Rate SDI PHY 1 3 amp Cj Module E Gy IP Macro Type User Configurable IP Version 1 3 E E Communications a SGMII Gb Ethernet PCS EE Connectivity Project Path ects 3G_SMPTE Tests v 1 3b02 test Browse DVB ASI Gai Display Interface Multiplexer ji File Name mysdi Gt Display Interface Multiplexer Tri Rate SDI PHY 6 Tri Rate SDI PHY Device Family LatticeECP3 E psp a FIR Filter Part Name LFE3 95EA 7FN1156C E E E Processors Controllers and Peripherals Synthesis SynplifyPro DDR3 SDRAM Controller Gb LPDDR Memory Controller IP Name Tri Rate SDI PHY Module Output Verilog S Configuration Ey About Note that if the IPexpress tool is called from within an existing project Project Path Module Output Design Entry in ispLEVER Device Family and Part Name default to the specified project parameters Refer to the IPexpress tool online help for further information To generate an IP configuration the user clicks the Customize button in the IPexpress tool dialog box to display the Tri Rate
7. 0 1 1 01101 13 1920 x 1080 25p 4 4 4 12 bits 0 1 1 01110 14 1920 x 1080 24p 4 4 4 12 bits 0 1 1 01111 15 1920 x 1080 60i 4 4 4 12 bits 0 1 1 10000 16 1920 x 1080 50i 4 4 4 12 bits 0 1 1 10001 17 1920 x 1080 30p 4 2 2 12 bits 0 1 1 10010 18 1920 x 1080 25p 4 2 2 12 bits 0 1 1 10011 19 1920 x 1080 24p 4 2 2 12 bits 0 1 1 10100 20 1920 x 1080 60i 4 2 2 12 bits 0 1 1 10101 21 1920 x 1080 50i 4 2 2 12 bits 0 1 1 11000 24 2048 x 1080 30p 4 4 4 12 bits 0 1 1 11001 25 2048 x 1080 25p 4 4 4 12 bits 0 1 1 11010 26 2048 x 1080 24p 4 4 4 12 bits 0 1 1 11011 27 2048 x 1080 30p 4 4 4 4 10 bits 0 1 1 11100 28 2048 x 1080 25p 4 4 4 4 10 bits 0 1 1 11101 29 2048 x 1080 24p 4 4 4 4 10 bits 3G B Dual Stream 1 0 1 xx000 0 1920 x 1035 60i 4 2 2 1 0 1 xx001 1 1920 x 1080 50i 295 4 2 2 1 0 1 xx010 2 1920 x 1080 30p 4 2 2 1 0 1 xx011 3 1920 x 1080 60i 4 2 2 1 0 1 xx100 4 1920 x 1080 25p 4 2 2 1 0 1 xx101 5 1920 x 1080 50i 4 2 2 1 0 1 xx110 6 1920 x 1080 24p 4 2 2 1 0 1 xx111 7 1280 x 720 60p 4 2 2 3G B Dual Link 1 1 1 00000 0 1920 x 1080 60p 4 2 2 1 1 1 00001 1 1920 x 1080 50p 4 2 2 1 1 1 00100 4 1920 x 1080 30p 4 4 4 4 1 1 1 00110 6 1920 x 1080 25p 4 4 4 4 1 1 1 01000 8 1920 x 1080 24p 4 4 4 4 1 1 1 01010 10 1920 x 1080 60i 4 4 4 4 IPUG82_01 5 December 2011 44 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Application Support Table 5 1 Pattern Generator Standards Continued
8. 10 Bit Data Path for Tx r I pd_in i N 1 q I l 12 Basic Tri rate tx data i IP Tx module pdi_clk rA without 10 bits tx half clk 2 or LDR options l sesso 20 bits half i rate 148 5 i 74 25 13 5 I i i I I I I lisa o if sd_Idr 1 pd_in_sd l l r la if sd Idr 1 and pdinsd_port 0 I x I I H I 3 SD8bits Scrambler Serializer 51 i H gt txd_ldr clk27 in eN cue l PLL 5 i NI I i i li i SAC a clk270_in Notes on switch positions If sd_tx_10bits 1 connection 1 is active else connection 2 is active If pdinsd_port 0 connection 3 is active else connection 4 is active If sdpli_exclude 1 connection 5 is active else connection 6 is active SD 10 bit Mode for Tx The Tri Rate SDI PHY IP is designed to directly interface with the LatticeECP3 SERDES Since the width of the SERDES data interface has to be fixed at 20 bits for multi rate operation the data transfer frequency is fixed at 13 5 MHZ for SD rate In the simplest configuration the IP takes in 20 bits of SD data at 13 5 MHz to be consistent with the SERDES interface However since most SD video is typically available as 10 bit 27 MHz data the IP offers the 10 bit option for the SD interface The 10 bit SD options are provided separately
9. 3G b inputs the trs in should go high when the y channel 8FF or the sec ond 3FF occurs in the stream as shown in Figure 2 11 The line number for both cases must be set at least three cycles before the LNO word is given at pd in Figure 2 12 shows the timing for the rate select control signals for different transmit rates IPUG82 01 5 December 201 1 23 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Figure 2 12 Rate select Control Signals for Different Transmit Rates trs_in eav sav Ib lan in tg hdn in hd sdn in pd in 3Ga data HD data i SD data 3Gb data The timing diagram for the Rx side data and status signals for HD 3G a is shown in Figure 2 13 and that for 3G b is shown in Figure 2 14 The timing for the multi rate receive operation is shown in Figure 2 15 Figure 2 13 Rx Data and Status Signals for HD 3G a rx_clk Eo x y F Y coo J ono Y XYZ M No M LN1 Y CRO re ds M di kf d2 y d3 kf EE a Latency on xo y Y 000 Y 000 M XYZ M LNO N LN1 X CRO M CRI y di ke osi e hblank Mi vblank I
10. Generator to the input labeled SDI Rx 1 and a SDI Monitor to the output labeled SDI Tx 0 Set the desired rate and pattern in the signal generator and see the same video passed through to the output The DIP switches are not read in the passthrough mode IPUG82 01 5 December 201 1 47 Tri Rate SDI PHY IP User s Guide Semiconductor Core Verification Corporation L atti C e Chapter 6 The functionality of the Lattice Tri Rate SDI PHY IP core has been verified via simulation and hardware testing in a variety of environments including Simulation environment verifying Tri Rate SDI PHY functionality using Lattice video pattern generator Hardware testing of the simulation environment in loopback mode with a cable providing the loopback of serial transmit out to serial receive in The video stream was generated using the internal video pattern generator and the status of the received video was displayed on the LCD display Hardware testing in passthrough mode where an external video source was used for transmission The sample design received the video stream using the IP receiver and re transmitted it through the IP transmitter IPUG82 01 5 December 201 1 48 Tri Rate SDI PHY IP User s Guide 111 Semiconductor Support Resources uuum Corporation Lattice This chapter contains information about Lattice Technical Support additional references and document revision history Lattice Technical Suppo
11. ModelSim simulators The Tri Rate SDI PHY IP core simulation model is generated from the IPexpress tool with the name lt username gt _beh v This file is an obfuscated simulation model An obfuscated simulation model is Lattice s unique IP protection technique which scrambles the Verilog HDL while maintaining logical equivalence VHDL users will use the same Verilog model for simulation When compiling the Tri Rate SDI PHY IP core the file sdi_params v must be compiled with the model This files provides define constants that are necessary for the simulation model The ModelSim environment is located in lt project_dir gt sdi eval lt username gt sim modelsim Users can run the ModelSim simulation by performing the following steps 1 Open ModelSim 2 Under the File tab select Change Directory and choose folder lt project_dir gt sdi eval lt username gt sim modelsim scripts 3 Under the Tools tab select Tcl gt Execute Macro and execute one of the ModelSim do scripts shown depend ing on whether RTL or netlist simulation is required The Aldec Active HDL environment is located in Xeproject dir gt sdi eval lt username gt sim aldec Users can run the Aldec evaluation simulation by performing the following steps 1 Open Active HDL 2 Under the Tools tab select Execute Macro 3 Browse to the directory lt project_ dir gt sdi eval lt username gt sim aldec scripts and execute one of the Active HDL do s
12. SDI PHY IP core Configuration GUI as shown in Figure 4 2 From this dialog box the user can select the IP parameter options specific to their application Refer to Parameter Settings on page 26 for more informa tion on the Tri Rate SDI PHY IP core parameter settings IPUG82_01 5 December 2011 33 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor IP Core Generation Figure 4 2 Configuration Dialog Box Diamond Version Lattice IP Core Tri Rate SDI PHY Tri Rate SDI PHY pd_out 19 0 pdo_clk vid active vid fi 1 0 frame format 2 0 clk clk d 353 IPUG82_01 5 December 2011 34 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor IP Core Generation IPexpress Created Files and Top Level Directory Structure When the user clicks the Generate button in the IP Configuration dialog box the IP core and supporting files are generated in the specified Project Path directory The directory structure of the generated files is shown in Figure 4 3 Figure 4 3 LatticeECP3 Tri Rate SDI PHY Core Directory Structure C3 sdi_phy_test C3 sdi_eval C3 models a ecp3 pcs O pli_148 3 pll 148 74 3 sd pll 2 sdi_phy_core0 Q impl E precision El 3 core only A impli C3 loopback C impli CD Machxo O passthru impli E C3 synplify E C3 core only impli E C3 loopback impli C Machxo 3 C3 passthru impli IO sim E 3 aldec rtl C3 scripts E
13. and re transmit it through the IP to a SDI monitor This design does not use a pattern generator in the FPGA The passthrough scheme is shown in Figure 5 3 Figure 5 3 Passthrough Scheme LCD display l l Waveform Generator rxdata TG 700 etc 4 Tri Rate LatticeECP3 FIFO SERDES si Ai Waveform Monitor WFM 7100 7120 etc txdata lt LatticeECP3 FPGA IPUG82_01 5 December 2011 41 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Application Support As shown in Figure 5 3 the output data from the receiver is fed to the transmitter through a FIFO Another major change in passthrough design from the loopback design is the Tx clocking scheme Since the transmit rate must exactly match the receive rate the passthrough design uses the recovered clock from the SERDES receiver to clock the transmit logic A detailed block diagram of the passthrough design is shown in Figure 5 4 As shown in the figure the recovered clock is cleaned up using a GS 4915 clock cleaner and used as the transmit reference clock Figure 5 4 Block Diagram of the Passthrough Design LCD display hd_sdn_in rx_hd_sdn tg_hdn_in rx_tg_hdn rx_hd_sdn vid_active vid_format gt frame_format L
14. data flag ADF data identifier DID secondary data identifier SDID parity to each of the VPID bytes and the checksum word The IP also determines the interface line number of the input video line by monitor ing the XYZ words The VPID payload is inserted in line number 10 and line number 572 for interlaced transports after the last CRC word in the y channel of each stream The IP uses the video format information contained in the VPID bytes to determine the interface line number LDR Path for SD This control specifies whether an LDR low data rate path is included for SD transmission An LDR path is required to dynamically support SD and fractional frame rate HD 3G transmission in the same quad If LDR is enabled a serializer and some associated logic are included in the IP core to support the SD transmission Include PLL for LDR This control determines if a PLL needs to be included inside the IP to perform the 10x multiplication of the 27 MHz clock for LDR transmit path If this is not selected but the LDR option is selected an additional input port is pro vided for the user to supply a 270 MHz clock This option permits the use of PLL in only one of the IP instances when multiple IP instances are used 10 bit Mode for SD Tx This parameter specifies support for 10 bit 27 MHz SD input mode and allows the IP to accept SD parallel input data at 10 bits 27 MHz IPUG82_01 5 December 2011 28 Tri Rate SDI PHY IP User s Guide Latti
15. grammable logic makes FPGAs field programmable gate arrays ideal devices to be used for acquisition mixing storage editing processing and format conversion applications Simpler applications use FPGAs to acguire SDI data from one or more SD standard definition HD high definition or 3G 3 Gigabit HD sources perform simple processing and re transmit the video data in SDI format Such applications require an SDI PHY physical layer interface and some basic processing blocks like a color space converter In more complex applications the acguired video is taken through multiple processing phases like de interlacing video format conversion filtering scaling graphics mixing and picture in picture display FPGA devices can also be used as a bridge between SDI video sources and backplane protocols such as PCI Express or ethernet with or without any additional video pro cessing In an FPGA based SDI solution the physical interface portion is often the most challenging part of the solution This is because the PHY layer includes several device dependent components like the high speed l Os inputs out puts serializer de serializer clock data recovery word alignment and timing signal detection logic Video process ing on the other hand is algorithmic and is usually achieved using proprietary algorithms developed by the user s in house design engineering teams The Lattice Tri Rate SDI PHY intellectual property IP core is a complete SDI P
16. if the number of time out errors is more than the value set using 3G HD SD Programming time parameter the state machine advances to the Check state While in the Check state if the number of TRS matches reaches the value set for Lock match threshold param eter the state machine advances to Lock state On the other hana if the number of TRS mismatches and time out errors exceeds the Unlock error threshold value the state machine advances to the Check state for the next rate While in the Lock state the state machine continues to be in that state as long the number of time out and TRS mismatch errors are within Unlock error threshold value When the number of errors exceeds the threshold while in the Lock state the state machine advances to the Check state for the next rate SMPTE 292M and SMPTE 424M also define a fractional frame rate video stream compliant with the North Ameri can standards Thus SMPTE 292M includes a 1 4835 Gbps data rate in addition to the 1 485 Gbps rate and SMPTE 424M includes a 2 967 Gbps data rate in addition to the 2 97 Gbps rate This IP core supports both the integer and fractional frame rates as long as the data and clock inputs to the IP core are consistent with the corre sponding rates While the IP core can receive both integer and fractional frame rate standards it will not be able to distinguish between the two However integer or fractional frame
17. other status outputs The passthrough design can be used to test the received video data The loopback design is designed for and tested on the VPB that includes the LatticeECP3 95E 7 1156 ball foBGA package commercial grade silicon A detailed block diagram of the loopback design is shown in Figure 5 2 IPUG82 01 5 December 201 1 40 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Application Support Figure 5 2 Block Diagram of the Loopback Design LCD display vid_active FIHIRHRHRRR vid format I TER a half clk eho frame_format MES rx_half_clk_c 27 MHz OSC SI rxiclk_ch1 rx_clk L 148 5 MHz rxdata chi rxdata DIP switches PLL fpga_rxrefclk_cho gt i hd_sdn_in na H3B hdinp_chO San Equalizer x tg_hdn_in hdinn_chO0 Tri Rate b Jan in atho cbn connect for LatticeECP3 SDI PHY ana Ng loopback SERDES IP pg_std_num i hdoutp chO Driver hdoutn cho txdata A 148 5 MHz Uu txdata_ch0 fym pd ine m refclkp Tx 4915 alan txiclk chO pdi_clk Lattice Video 1 tx full clik cho tx half clk Pattern PLL tx half cik cho Generator tx half clk 27 MHz XTL tx full clk LatticeECP3 FPGA hd sdn in Passthrough Design The passthrough design is set up to receive video from a standard SDI source
18. the video data stream For 3G b video there are two line number input ports Int in and In2 in one for each of the two 3G b video streams CRC Computation The CRC computation module is optionally added if the CRC insertion option is enabled through the IP GUI The CRC is computed separately for each Y and C component of the entire active line encoded to two CRC words per component and embedded at the appropriate places in the next line For 3G b streams there are four separate IPUG82 01 5 December 201 1 11 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description CRC computations one for each component and each stream Line based CRC is supported only for HD 3G stan dards i e when the input hd_sdn_in is high The CRC is computed using the following polynomial equation CRC X X x X54 X 1 VPID Insertion This module prepares the VPID words and determines the checksum from the raw VPID value s read from vpid1_in and vpid2_in port for insertion into the video stream This module also determines the line number of the current video line and the appropriate line number when the VPID must be inserted for the current standard LN CRC Insertion This module inserts the computed CRC and LN words at appropriate places in the data stream before the data is sent to the Scrambler Encoder module Scrambler Encoder This module performs scrambling and NRZI Non Return to Zero Inverted encoding per the require
19. this output corresponds to stream 1 The stream 2 VPID valid in that case is available at vp2_valid port vp1_cserr vp2_cserr VPID checksum error output This output denotes a checksum error for the received VPID When receiving 3G b video this output corresponds to stream 1 video The stream 2 VPID checksum error in that case is available at vp2_cserr port vp1_parerr vp2_parerr VPID parity error output This output denotes a parity error for the received VPID When receiving 3G b video this output corresponds to stream 1 The stream 2 VPID parity error in that case is available at vp2_parerr port vp1_lineok vp2_lineok VPID line okay output This output indicates that the VPID was embedded in the correct line number of the received video VPID needs to be embedded at line 10 for progressive transports and lines 10 and 572 for interlaced transports When receiving 3G b video this output corresponds to stream 1 video The stream 2 VPID line okay indication in that case is available at vp2_lineok port rx_rate This input command controls the rates scanned by the receiver Each bit enables the scanning of one of the rates as shown below rx_rate 2 O disable 3G scan 1 enable 3G scan rx_rate 1 O disable HD scan 1 enable HD scan rx_rate 0 0 disable SD scan 1 enable SD scan This is an asynchronous control input The receiver scans only for the rates that are enabled However if the scan fo
20. used to recreate or modify the core in the IPexpress tool The IPX file holds references to all of the elements of an IP or Module after it is generated from the IPexpress tool Diamond version only The file is used to bring in the appropriate files during the design implementation and analysis It is also used to re load parameter settings into the IP Module generation GUI when an IP Module is being re generated These files contain the embedded block RAMs EBRs used by the IP core These files need to be pointed to by the Build step by using the search path property lt username gt lpc lt username gt ipx pmi_ ngo Most of the files required to use the Tri Rate SDI PHY IP core in a user s design reside in the root directory created by the IPexpress tool This includes the synthesis black box simulation model and post synthesis NGO files for the PMI modules The sdi eval and subtending directories provide files supporting Tri Rate SDI PHY IP core evaluation The sdi_eval directory contains files folders with content that is constant for all configurations of the Tri Rate SDI PHY IP core The lt username gt subfolder Nsdi phy evalo in this example contains files folders with content spe cific to the lt username gt configuration The Tri Rate SDI PHY ReadMe document is also provided in the sdi eval directory For example information and known issues on this core see the Lattice Tri Rate SDI PHY Read
21. 164 1 Performance and utilization data are generated using an LFE3 95EA 7FN1156C device with Lattice Diamond 1 3 software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family Table A 2 Parameter Settings for Sample Configurations Core Configuration Parameter Name 1 2 3 4 5 6 PHY function Both Both Both Both Tx Rx Enable 3G Level B Yes Yes No No Yes Yes LN insertion On On On On On CRC insertion On On On On On VPID insertion On Off On Off On LDR path for SD No No No No No Include PLL for LDR 10 bit mode for SD Tx Ves Ves Ves Ves Ves Separate input for SD SD data width 10 10 10 10 10 VPID extraction On Off On Off On 10 bit mode for SD Rx Yes Yes Yes Yes Yes Clock enable port No No No No No No 1 The Tri Rate SDI Physical Layer IP core is an IPexpress user configurable core and can be used to generate any allowable configuration Ordering Information The Ordering Part Number OPN for all configurations of the Tri Rate SDI Physical Layer IP core targeting LatticeECP3 devices is TR SDI PHY E3 U1 IPUG82_01 5 December 2011 51 Tri Rate SDI PHY IP User s Guide
22. 8 MHz allowing for both 8 bit and 10 bit data types This IP core supports all of SMPTE 125M and only the 13 5 MHz version of SMPTE 267M SMPTE 292 defines a serial data rate of 1 485 Gbps and 1 485 M Gbps where M 1 001 This interface standard supports the source formats defined in the four SMPTE standards SMPTE 260M SMPTE 295M SMPTE 274M and SMPTE 296M The IP core can transmit receive and identify all of these source formats In addition to these formats the IP core can be configured to receive any custom source format as long as the data conforms to the SMPTE 292M interface standard This is achieved by allowing the user to define the source format in terms of the number of words between SAV start of active video and the next EAV end of active video and the number of words between EAV and the next SAV It is also possible to have the IP receive multiple custom source formats by specifying a range for the above values The source format support for SMPTE 424M is specified by the SMPTE 425M specification 10 SMPTE 425 defines four mapping structures that map the HD source formats to the 3G interface The higher stream rate is used to accommodate 4 2 2 50p 4 2 2 60p 4 4 4 4 4 4 4 and 12 bit formats The Lattice Tri Rate SDI PHY IP core detects the interface standard as 3G and the source format as one of many video and frame formats The IP also supports the transmission and reception of 3G Level B video formats The following mapping nom
23. B modelsim rtl O scripts OD src El B beh rtl e ecp3 B params E a rtl top E e ecp3 frac led C3 testbench C3 patgenerator IPUG82 01 5 December 201 1 35 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor IP Core Generation Table 4 1 provides a list of key files and directories created by the IPexpress tool and how they are used The IPex press tool creates several files that are used throughout the design cycle The names of most of the created files are customized to the user s module name specified in the IPexpress tool Table 4 1 File List File Description lt username gt _inst v This file provides an instance template for the IP lt username gt _beh v This file provides the front end simulation library for the Tri Rate SDI PHY IP core sdi_params v This file provides the user options of the IP for the simulation model lt username gt _bb v This file provides the synthesis black box for the user s synthesis lt username gt ngo This file provides the synthesized IP core ecp3pcs txt This file contains the PCS SERDES memory map initialization This file must be copied in to the sim ulation directory as well as the software project directory This file contains the IPexpress tool and Tri Rate SDI PHY IP GUI options
24. CD Interface rx_half_clk_chO rxiclk_ch1 UL x full clk cho rxdata Spi iO rxdata_ch1 pd out J 9 ource Equalizer lF b lhdinn_ch0 sou Li pdo clk fpga rxrefclk chO Rx 4915 Ed A i 148 5 MHz LatticeECP3 Tri Rate FIFO SERDES SDI PHV PLL jt 27 MHz XTL IP SDI a I hdoutp_ch0 Dl i lt txdata gt Monitor hdoutn cho txdata cho gt refclkp A A P Tx 4915 Pl refclkn txiclk_chO pdi_clk lt 148 5 MHz tx_full_clk_cho tx_half_clk tx half cik cho LatticeECP3 FPGA tx half clk tx full clk hd sdn in Simulating the Sample Design The IP project directory contains the simulation environment to run loopback testing of the IP The environment includes the testbench test configuration file and simulation script file The testbench instantiates the loopback sample design with an additional pattern checker that is enabled for simulation To simulate the design using the Aldec ActiveHDL simulator 1 Open Aldec ActiveHDL 2 From the menu select Tools Execute Macro 3 Browse to project dir sdi eval module name sim aldec scripts module name rtl do 4 This will start the compilation and simulation After several minutes the simulation will end with the test status A simulation script is also provided for the ModelSim sim
25. D insertion extraction July 2010 01 2 1 1 Divided document into chapters Added table of contents Added Quick Facts tables in Chapter 1 Introduction Added new content in Chapter 4 IP Core Generation Added new content in Chapter 5 Application Support Added new content in Chapter 6 Core Verification July 2010 01 3 1 1 Updated Figure 2 9 November 2010 01 4 1 2 Added Diamond software support throughout December 2011 01 5 1 3 Added support for 8 bit TRS HD cameras Expanded custom support to include 2K formats IPUG82_01 5 December 2011 50 Tri Rate SDI PHY IP User s Guide Lattice p Semiconductor Resource Utilization a a a Corporation This appendix gives resource utilization information for Lattice FPGAs using the Tri Rate SDI PHY IP core IPexpress is the Lattice IP configuration utility and is included as a standard feature of the Diamond and ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and Diamond or ispLEVER help system For more information on the Diamond or ispLEVER design tools visit the Lattice web site at www latticesemi com software LatticeECP3 FPGAs Table A 1 Performance and Resource Utilization Sample Configuration Slices LUTs Registers Tx Clock Rx Clock 1 1306 2506 1795 181 150 2 918 1747 1283 248 176 3 926 1772 1243 185 178 4 733 1403 1009 285 149 5 436 845 491 182 6 905 1714 1321
26. FF NF FREE NHWF FR NN RF Y de 12 Signal Descriptions 2 e EF ee RR FE as 12 Interfacing with Tri Rate SDI PHY IP Core i 17 SERDES Board Tx Interface iioi etr ai aio 17 SD 10 bit MOod T r TX corna ras tries ae 18 SD LDR Mode i ini e i cach hidenus et an gaceees ea dha oad caea eee peeve ceed ade eb hadi sheave steed 18 zip crei me titi litio a 19 FPGA Tx IMC aCe socia rtp ot O 19 A PU OOO rx p re ud a En E VR RV RR A a a E Ra E AV 19 Advanced Settiligs io da 19 SERDES Board Rx Interface iii ene eet an 19 FPGA Rx Interface roni er E d n ER e RR aia 20 SD 10 Bit Mode for Axial seco dence na ta Re eH SH ER d ER EN KR RR a wa FWG A FWYN GY 20 Video Payload Identification and Extraction cnn ANA nc rn rra nennen nnns 20 Integer Frame Rate Applications 21 Fractional Frame Rate Applications i 22 Timing Specifications aisan ania eana aN ea 23 Chapter 3 Parameter Settings sm dci 26 PAY TaD E illa aaa N re 27 au NL Leu Le EE e a ea aiar A SF FE REN RY HR 27 Enable 3G Level Bionic aliada AE E ND ARR NENN YRR OU iaia 27 EN IN SONOMA JA RR An 28 A e A a sa 28 VPID IMSS ION m M 28 LDR Paih for SD iaia aa 28 Include PEE for EDR rtp ana nia 28 10 bit Mode for SD TX4 eiii YY aaa 28 Separate Data Input for SD i uy Gi i i as 29 SD Data Width HOH HR tata Asi 29 O 2011 Lattice Semiconductor Corp All Lattice trademarks registere
27. HY IP User s Guide Lattice Semiconductor Functional Description FPGA Rx Interface The FPGA Rx interface includes the parallel output data output clock video status format outputs video timing signals LN output CRC and EAV SAV error outputs VPID bytes and VPID status error outputs The parallel data output is synchronous with the pdo_clk if 10 bits mode for SD option is enabled and with the rx_clk otherwise The pdo_clk is derived by multiplexing rx_clk and rx_full_clk using FPGA logic as shown in Figure 2 6 Figure 2 6 SD 10 Bit Data Path for Rx Basic Tri rate IP Rx module without 10 bit SD Rx option 20 bit half rate 148 5 74 25 13 5 rx_clk rx_full_clk rxdata P pd out p gt pdo clk Su if sd_rx_10bits 1 The vid_format and frame_format values are determined from the relative EAV SAV positions in the received data and whether the field value is toggling or not The y channel data is always used for format determination For 3G b video the format determination is based on the y channel data of stream 1 video The line number output Int out and In2 out if receiving 3G b video is the line number contained in the LNO and LN1 words of the received y channel data If it is not necessary to scan for all the three rates it is possible to disable the scanning of a particular rate or rates The 3 bit r
28. HY interface that connects to the high speed SDI serial data on one side through LattiteECP3 SERDES and the formatted parallel video data on the other side It enables faster development of applications for processing storing and bridging SDI video data It is comprised of the following major functional blocks SDI encoder decoder word alignment CRC detection and checking VPID video payload identifier insertion and extraction and rate detection logic The IP core supports the following interface standards and source formats for SDI as specified in standards published by the Society for Motion Picture and Television Engineers SMPTE Interface SMPTE 259M 2006 1 SD SMPTE 292M 1998 2 HD and SMPTE 424 M 3 3G SD source formats SMPTE 125M 4 and SMPTE 267M 5 13 5 MHz only HD source formats SMPTE 260M 6 SMPTE 274M 7 SMPTE 295M 8 and SMPTE 296M 9 3G source formats SMPTE 425M 10 The Tri Rate SDI PHY IP core when connected with the LatticeECP3 SERDES can transmit and or receive any of the supported video standards and formats through a common physical serial interface The Tri Rate SDI PHY IP core can automatically scan and lock on to any of the supported video streams Receiving multiple standards reguires appropriate external clocks to be supplied by the application in response to commands from the Tri Rate SDI PHY IP core IPUG82_01 5 December 2011 5 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor I
29. Lattice Semiconductor Parameter Settings Figure 3 2 Custom Format Tab PHY Custom Format Advanced 3G Custom format support for 3G ku EAV2SAV cycles 10 to 5699 SAV2EAV cycles 10 to 5699 HD Custom format support for HD ES G EAV2SAV cycles 10 to 2833 SAV2EAV cycles 10 to 2899 Custom Format Support for HD This parameter enables custom HD format detection by the IP If custom format detection is required additional parameters need to be set Custom format is detected by accommodating user defined ranges for the number of words gap between SAV and EAV and between EAV and SAV Custom Format Support for 3G This parameter enables custom 3G format detection by the IP If custom format detection is required additional parameters need to be set Custom format is detected by accommodating user defined ranges for the number of words between SAV and EAV and between EAV and SAV Value or Range This control specifies how the SAV to EAV and EAV to SAV gaps are specified The IP accepts specific values as well as a range for these gap parameters EAV2SAV cycles Value This is the value for the gap between the EAV and the SAV The value is computed as Words total line Words active line 5 for HD 2 Words total line Words active line 5 for 3G a 2 Words total line Words active line 9 for 3G b IPUG82_01 5 December 2011 30 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Parameter Setting
30. Me document This file is available when the core is installed The document provides information on creating an evaluation version of the core for use in Diamond or ispLEVER and simulation The sdi eval directory provides an evaluation design which can be used to determine the size of the IP core and a design which can be pushed through the Diamond or ispLEVER software including front end and timing sim ulations The models directory provides the library element for the PCS and PLLs The lt username gt directory contains top level design for the configuration specified by the customer The lt username gt impl directory provides project files supporting Precision RTL and Synplify synthesis flows The sample top level design pulls the user ports out to external pins This design and associated project files can be used to determine the size of the core and to push it through the mechanics of the Diamond or ispLEVER software design flow The lt username gt sim directory provides project files supporting RTL and timing simulation for both the Active HDL and ModelSim simulators The lt username gt src directory provides the top level source code for the eval design The testbench directory provides a top level testbench file IPUG82_01 5 December 2011 36 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor IP Core Generation Running Functional Simulation Simulation support for the Tri Rate SDI PHY IP core is provided for Aldec and
31. P User s Guide Lattice Semiconductor IP Core Generation 5 Implement the complete design via the standard Diamond GUI flow To use the project file in ispLEVER 1 Choose File gt Open Project 2 Browse to lt project dir gt sdi eval lt username gt impl synplify or precision in the Open Project dia log box 3 Select and open lt usemame gt syn At this point all of the files needed to support top level synthesis and imple mentation will be imported to the project 4 Select the device top level entry in the left hand GUI window 5 Implement the complete design via the standard ispLEVER GUI flow Hardware Evaluation The Tri Rate SDI PHY IP core supports supports Lattice s IP hardware evaluation capability which makes it possi ble to create versions of the IP core that operate in hardware for a limited period of time approximately four hours without requiring the purchase of an IP license It may also be used to evaluate the core in hardware in user defined designs Enabling Hardware Evaluation in Diamond Choose Project gt Active Strategy gt Translate Design Settings The hardware evaluation capability may be enabled disabled in the Strategy dialog box It is enabled by default Enabling Hardware Evaluation in ispLEVER In the Processes for Current Source pane right click the Build Database process and choose Properties from the dropdown menu The hardware evaluation capability may be enabled disabled in the Prop
32. and should be exactly double the freguency of rx_clk while receiving SD video The Rx recov ered clock from the SERDES rx_full_clk_chx can be directly used for this clock rx_hd_sdn HD or SD status output This signal indicates the rate that is being received by the IP a zero value for SD and a one value for HD or 3G This signal can be used to set the SERDES to receive the right rate and or command the clock generator to output the appropriate clock rx_tg_hdn rx Ib lan 3G or HD status output This signal indicates the rate that is being received by the IP a zero value if SD or HD and a one value if 3G This signal can be used to set the SERDES to receive the right rate and or command the clock generator to output the appropriate clock 3G Level B or not status output This signal indicates whether the received video is a 3G Level B stream or not This output is one if the received video is 3G Level B and zero oth erwise SERDES Board Tx Int erface txdata 20 Transmit data parallel to the SERDES This data is synchronous with the tx_half_clk or pdi_clk depending on whether 10 bit mode for SD Tx is enabled or not txd_ldr Low data rate transmit data This is the transmit data for the SD rate serialized in the IP to be connected to the out of band transmit path of the SERDES channel This output is typ ically connected to txd_Idr_chx of the SERDES Common Interface rstn System wide as
33. ansport any rate or format A high level block diagram of the transmitter is shown in Figure 2 3 Figure 2 3 Multi Rate SDI Transmitter High Level Block Diagram In1_in LN I lt ini set Encoder 41 In2 in j n2 set 4 hd sdn in b lan in Scrambler t trs in txdata Encoder EF ENCORE Insertion sd0b meda I lt pdi_clk pd_in CRC Computation Low txd ldr 44 Speed VPID vpid1_in Serializer insertion T Scrambler a een fe mE The input data to the transmitter is SMPTE formatted parallel video data which typically includes active video blanking ANC Ancillary and TRS words If the CRC and line number LN words for HD 3G are available in the video stream the IP core can pass them on If the CRC and or LN information is not available from the stream the IP can fill them in and insert them in the stream at the right places The transmitter is comprised of the following logical modules LN encoder CRC computation VPID insertion LN CRC insertion scrambler encoder and low speed serializer A brief description of each of these modules is given below LN Encoder The LN encoder converts the raw line number value read from the input port to two LN words for insertion in the video stream This module is used only for HD 3G inputs This module is optional and used only when the LN words are not already available in
34. ce Semiconductor Parameter Settings Separate Data Input for SD This parameter provides a separate input port for SD data If this option is not selected the SD input is read in from the lower 10 bits of the common input data bus pd_in This option is available only if the LDR path for SD is selected SD Data Width This parameter configures the user data width for SD standard video If this is 10 bits the data is directly used If this is 8 bits the user data drives the most significant 8 bits of the internal data bus and the least significant 2 bits are filled by the IP with zeros except when the input 8 bits are all ones when they are filled with ones If configured as dynamic the 8 bit or 10 bit mode is decided by the input signal sd8b_mode VPID Extraction If this parameter is enabled the IP extracts the video payload identifier VPID from the received video stream The VPID bytes as well as some status error signals are given out independently for each video link 10 bit Mode for SD Rx This parameter enables the IP to provide SD parallel output data at 10 bits 27 MHz Clock Enable Port This parameter configures if a clock enable port is required in the IP core This option must be selected only if required as the clock enable port increases the resource utilization of the IP core Custom Format Tab Figure 3 2 shows the contents of the Custom Format tab IPUG82_01 5 December 2011 29 Tri Rate SDI PHY IP User s Guide
35. cripts shown Synthesizing and Implementing the Core in a Top Level Design The Tri Rate SDI PHY IP core itself is synthesized and provided in NGO format when the core is generated through the IPexpress tool You can combine the core in your own top level design by instantiating the core in your top level file and then synthesizing the entire design with either Synplify or Precision RTL Synthesis The top level file lt username gt _top v provided in lt project_dir gt sdi eval lt username gt src rtl top lt device family supports the ability to implement the Tri Rate SDI PHY IP core in isolation Push button implementation of this top level design with either Synplify or Precision RTL Synthesis is supported via the Diamond or ispLEVER software project files lt username gt _top syn located in the lt project_dir gt sdi eval lt username gt impl synplify core only and the lt project_dir gt sdi eval lt username gt impl precision core_ only directories respectively To use the project file in Diamond 1 Choose File gt Open gt Project 2 Browse to lt project dir gt sdi eval lt username gt impl synplify or precision in the Open Project dia log box 3 Select and open lt username gt ldf At this point all of the files needed to support top level synthesis and imple mentation will be imported to the project 4 Select the Process tab in the left hand GUI window IPUG82_01 5 December 2011 37 Tri Rate SDI PHY I
36. ctor Functional Description Figure 2 7 Format and Structure of Video Payload Identifier HD stream 20 bits at 74 25 MHz or 3G Level A stream 20 bits at 148 5 MHz VPID ANC data a ano N EAV LN CRC ADF nb ono VPID e SAV Other ANC data Data ex es es es ee ens wee likes ele le le eleleje e CCC EE fae Je HK IH le Je ls lo lala ly I gt gt gt S 5 t sls S2 lz S 9 3 e EF ES 2 3 3 3 ju EEN a lo la S 4 IS gt gt la lc Jos Bla iz 2 9 rt S S gt l gt gt o o o x FIEJEJE las las la lo gt gt in ja 2 9 8 9 9 9 2 JE slo lo lols 3 O10 O O lo tls i3 elz 88 ir gig 8 o o lo la S 15 9 O LIS ISIS lo jo co o o x 3G Level B stream 20 bits at 148 5 MHz VPID ANC data a Ono ep EAV LN CRC ADF ona VPID SAV Other ANC data Data asososososos ELIE E EE E ETE 8285 Osasosass els LKISISISISRESEEIIRISISE S E El PI BI is 2 2 2 o tila ele eisin ele blsa re gt S l je a I la la e co O o o S k O gt O 7 SSSSSSSSISSISSSSSs S S S LL LI BI BE ja SININSS NISI cn csesesesasiasilelo lt a E E E es esse SOS sss SSS eye e toc ioc R4 FE ll sl el II kal lol l l Y iiie jj eg 18 S KESSSSSEeeesesp B E El FI PI PI IIIS ititisjssSEBisklsz dadadada 4has59 9 9 5 lb E gt 3 3 o co es o o o o Se lO gt O
37. d clock generator to be set to that rate Once the clock generator and the SERDES are set to a data rate the receiver tries to receive the signal for that rate The receiver checks the TRS instances number of active words and total words to see if they are consis tent with the source formats for the interface standard that is being received If they match the receiver locks to this IPUG82_01 5 December 2011 9 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description video stream and asserts the vid_active signal On the other hand if the TRS instances are not consistent with the source formats that are expected for the current scanned rate the receiver advances to scan the next rate The rate detection state machine is set to scan for the HD rate first followed by 3G and SD rates and then to go back to scan HD to start the sequence over The state machine advances to scan the next rate only if that rate is enabled by the dynamic input signal rx_rate For each scan rate the state machine goes through three states Program Check and Lock The state advances are based on the number of TRS matches TRS mismatches and time out errors A time out error occurs when a TRS is not received in a reasonably long duration of time Dur ing the Program state the external clock sources are set to provide the relevant clocks and or the SERDES divid ers are set to receive the relevant rate If a TRS is received or
38. d trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice IPUG82_01 5 December 2011 2 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Table of Contents MPID Exact E eti rt RU e dri i 29 10 bit Mode for SD BOX zie ib eie Ete o t te ee Ire ob tos receta 29 Glock Enable Port uem n ada 29 Custom Format Tab er eto t ia ces stt eed Beet oak edt eee ee e Dag ted e tenes 29 Custom Format Support for HD i 30 Custom Format Support for SQ usi rtr e ci te fd Tydu de ea erre e Rete ne tori euet 30 Value OF Rango 3 conie tee nh A 30 EAV2SAV cycles Valle cri dei de eisai a Ep ee te Eee d eli 30 EAV2SAV Cycles Minimum i 31 EAV2SAV Cycles MaxiMUmi vile ari cade dae rte e eo aeos 31 SAV2EAV Cycles Valle dr t dalai 31 SAV2EAV Cycles MINIMUM cama ee Re alia e eyda FRY SAU 31 SAV2EAV Cycles Maximum ii 31 Advanced Mp Fn gd 31 36 AD SDPrograM lite sek i rtt ila illa alati 31 Lock Match Threshold eiu cte tret benedicto ala o dada e ee att 31 Unlock Error Threshold niii A RM Ge ER deg 31 Chapter 4 IP Core Generatiori i ii ki iii 32 Licensing theIP GOre iR ee tee ea Eee ap a Gast dea ea a aa 32 Gettin
39. deo this input provides the line number for In2 in stream 1 video In that case In2 in is used to read the line number for the stream 2 video and In2 set is used as strobe Line number set signal This signal is used as a strobe to read the value at the In1 in port In1 set 4 The line number must be set during or before LNO word is applied at the pd_in input In2_set When transmitting 3G b video this input serves as a strobe for the line number for stream 1 video In that case In2_set is used to strobe the line number for the stream 2 video Video payload identifier input This input is not used when transmitting SD video The vpid1_in 32 VPID bytes are organized in the following order byte4 byte3 byte2 byte1 When trans vpid2_in mitting 3G b video this input corresponds to the VPID for stream 1 The stream 2 VPID in that case is read from the vpid2_in input port This is the 27 MHz input clock for the optional 10 bit 27 MHz SD Tx interface This clock clk27_in 1 must be frequency synchronous with pdi_clk exactly double that of pdi_clk during SD operation if the parameter LDR path for SD is not selected This is the 270 MHz serial clock used for SD serialization in soft logic This port is available clk270_in 1 I ifthe LDR path for SD option is selected and the Include PLL for LDR option is not selected This clock frequency must be exactly 10 times that of clk27_in SD LDR clock output This 27 MHz clock is synchronous wi
40. ductor Application Support Table 5 2 Switch Connections on the VPB Continued Switch Name Description SW3 1 SW3 2 Standard number SW4 1 SW3 4 SW3 3 SW3 2 SW3 1 SW3 3 Video Standard See Table 5 1 for the format SW3 4 SW4 1 Color bar or pathological pattern type SW4 3 SW4 2 SW4 2 When patho_cbn 0 When patho_cbn 1 00 10095 color bar 00 SDI checkfield patho_cb_type 01 75 color bar 01 Equalizer pattern SW4 3 1x SMPTE color bar 10 PLL pattern 11 Undefined SW4 4 patho_cbn Pathological or color bar O Color bar 1 Pathological Note that the pattern generator interprets the Ib lan in tg_hdn_in and hd_sdn_in values differentiv from the IP The values shown in Table 5 1 and Table 5 2 are for the pattern generator For example the pattern generator dif ferentiates 3G Level B DS and 3G Level B DL using the values 101 and 111 for Ib lan in tg_hdn_in hd_sdn_in whereas the IP identifies all 3G Level B streams with the value 111 Transmitter Testing Connect the transmitter output BNC connector labeled SDI Tx 0 to an SDI monitor Set the DIP switches accord ing to the rate and pattern to be transmitted The selected pattern is displayed in the monitor Receiver Testing Connect an SDI source to the receiver input BNC connector labeled SDI Rx 1 The received rate and standard are displayed on the charact
41. e XYZ word appears at the output For 3G b video the hblank output corresponds to stream 1 video and it changes state when the y channel XYZ word appears at the output Int out In2 out eav error Line number output This provides the line number corresponding to the current parallel data output This output is not valid for SD video rates The value at this output changes when LN1 word is given out at pd out port When 3G b video is being received this output corresponds to stream 1 video and changes state when y channel LN1 word is given out at pd out port Line number output for stream 2 video This output is valid only when 3G b video is being received The output changes state when y channel LN1 word is given out at pd out port EAV error output This one cycle pulse indicates that an EAV has been received at an incorrect time instant or that the EAV has not been received when it should have been received Sav error SAV error output This one cycle pulse indicates that a SAV has been received at an incor rect time instant or that the SAV has not been received when it should have been received vi crc error This signal indicates that a CRC error has been detected for the y channel of the current line This output is not valid for SD video rates The CRC error output goes high during the clock cycle when the CRC comparison is made When 3G b video is being received this output denotes the CRC error for the y channel of s
42. e device resources the module will need To import the module into your project if it s not already there select Import IPX to Diamond Project not available in stand alone mode Click Generate Check the Generate Log tab to check for warnings and error messages 10 Click Close The IPexpress package file ipx supported by Diamond holds references to all of the elements of the generated IP core required to support simulation synthesis and implementation The IP core may be included in a user s design by importing the ipx file to the associated Diamond project To change the option settings of a module or IP that is already in a design project double click the module s ipx file in the File List view This opens IPexpress and the module s dialog box showing the current option settings Then go to step 6 above Regenerating an IP Core in ispLEVER To regenerate an IP core in ispLEVER 1 2 In the IPexpress tool choose Tools gt Regenerate IP Module In the Select a Parameter File dialog box choose the Lattice Parameter Configuration Ipc file of the IP core you wish to regenerate and click Open The Select Target Core Version Design Entry and Device dialog box shows the current settings for the IP core in the Source Value box Make your new settings in the Target Value box If you want to generate a new set of files in a new location set the location in the LPC Target File box The base of the Ipc file na
43. eated using the default parameters in the IP GUI The LatticeECP3 VPB has the LFE3 95E 7FN1156CES device on it If one or more parameters are changed in the IP GUI the sample designs can still be used but may reguire some changes depending on the parameters used to configure the IP Loopback Design The loopback design is meant to test the transmit Tx and receive Rx logic of the IP without the help of an exter nal SDI source or sink The design includes the Lattice video pattern generator module in FPGA logic LatticeECP3 SERDES PCS and a character LCD display interface in addition to the IP The loopback scheme is shown in Figure 5 1 Figure 5 1 The Loopback Scheme Optional Waveform Generator LCD display rxdata TG 700 etc P dd gt connect for LatticeECP3 Tri Rate Optional Waveform Monitor IE WFM txdata Lattice Video 7100 Ff AAA Pattern Generator 7120 etc LatticeECP3 FPGA A waveform monitor and or a waveform generator can be optionally used instead of the loopback cable to monitor and or source the SDI video All the transmit functions and most of the receive functions of the IP can be tested with the loopback setup One major output that is not tested using a loopback cable connection is the actual parallel received data and its relative timing to
44. el m field m vblank m gt hblank gt Ini out gt In2 out m eav_error m sav error m vi crc error m c1 crc error m V2 crc error m c2 crc error gt vpidi out gt vp1 valid c vp1_cserr m gt vp1_parerr gt vp1_lineok gt vpid2 out gt vp2 valid m vp2 cserr gt vp2 parerr m vp2 lineok x rate pd in pdi clk 4 xx half clk K0 pd in sd trs in hd sdn in Ib lan in sd8b mode n1 in In1_set n2 in In2 set 4 vpid1 in 4 vpid2 in clk27 in clk270 in gt clk27_out m clk270_out IPUG82 01 5 December 201 1 13 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Table 2 1 Top Level I O Interface Port Bits o Description SERDES Board Rx Interface rxdata 20 Received data parallel from the SERDES This input is read in using rx_clk rx_clk This clock is synchronous with rxdata The frequency of this clock is 148 5 MHz or 148 35 MHz for 3G 74 25 MHz or 74 175 MHz for HD and 13 5 MHz for SD This usually comes from the Rx recovered clock rx_half_clk_chx from the SERDES CDR rx_full_clk This clock is required if 10 bit 27 MHz SD output is enabled i e when the 10 bit mode for SD Rx option is selected This clock must be freguency synchronous with rx_clk
45. enclature speci fied in SMPTE 425M are supported SMPTE 372M dual link payloads on a 3 Gbps interface e 2x720 line video payloads on a 3 Gbps interface e 2x1080 line video payloads on a 3 Gbps interface IPUG82_01 5 December 2011 7 Tri Rate SDI PHY IP User s Guide 55 Semiconductor Functional Description uuu Corporation 3 Latti C a Chapter 2 This chapter describes the functionality of the Tri Rate SDI PHV IP core The high level functional diagram of the Tri Rate SDI PHY IP core is shown in Figure 2 1 Figure 2 1 Tri Rate SDI PHY IP Core High Level Functional Diagram VPID 2 HB vpid out rx_hd_sdn 4 Rate Extraction rx_tg_sdn 4 Detection rx_lb_lan 4 Control E CRC x Checker gt crc errors Word Pedale Pl Decoder Alignment Podi rx clk Descrambler gt TRS bl an E Detection vid active on gt vid format gt frame format Receive Logic Transmit Logic pd in Scrambler VPID CRC LN po_ txdata Encoder Insertion Insertion pdi ck trs in 1 fe vpid_in Low Speed txd_idr lt Serializer Figure 2 1 shows the top level functional view of the IP core As shown the Tri Rate SDI PHY IP core does not include the LatticeECP3 SERDES in it The top portion of the diagram shows the receiver and the bottom portion the transmitter The Tri Rate SDI PHY IP core i
46. er 2011 26 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Parameter Settings PHY Tab Figure 3 1 shows the contents of the PHY tab Figure 3 1 PHY Tab PHY Custom Format Advanced PHY Function C Tx C Rx Both IB Level B option v Enable 3G Level B GAD Transmit Options LN Insertion VPID insertion C Off On C Off On M CRC Insertion C Off On SD Transmit Options LDR path for SD Include PLL for LDR fw 10 bits mode for SD Tx Separate data input for SD SD data width C 8bits 10 bits C Dynamic 8 10 bits m 3G HD Receive option VPID extraction Off Dn ID Receive options v 10 bits mode for SD Rx m Optional ports TT Clock enable port PHY Function This parameter configures the IP core for Tx Rx or both Tx and Rx functions Tx Rx and Both parameters allow the user to specify receive only transmit only or both receive and transmit functions in the IP core Even if both functions are available the receive and transmit logic are independent of each other The transmit and receive rates however may be limited by the reference clock and banding requirements imposed by the SERDES quad Enable 3G Level B 3G Level B support is enabled if this box is checked This parameter enables both reception and transmission of 3G Level B video If 3G b support is not required this option may be t
47. er LCD display If the LCD display unit is not connected the status can also be read from the LEDs The LEDs also display the SERDES and CRC error status Note that the 3G Level B identified by the IP and displayed in the LCD is based on the format for stream 1 of the 3G video The LED status 0 is off 1 is lit is shown in Table 5 3 Table 5 3 LED Status Display LED Color Name Description D10 Blue rx_los_ch1 Rx loss of signal LOS 0 No LOS error 1 LOS error D11 Green rx_lol_ch1 Rx loss of lock 0 Rx CDR is locked 1 Rx CDR loss of lock error D12 Orange crc_error CRC error detected 0 No CRC error 1 CRC error D13 Red pll_lol SERDES transmit PLL loss of lock O PLL locked 1 PLL unlocked D14 Blue rx_hd_sdn Receiver s HD SD rate status 0 SD 1 HD D15 Green rx_tg_hdn Receiver s 3G HD rate status 0 Not 3G 1 3G D16 Orange Detected video format output D17 D16 00 1440x486 576 vid_format 01 1280x720 D17 Red 10 1920x1035 11 1920x1080 IPUG82 01 5 December 201 1 46 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Application Support Table 5 3 LED Status Display LED Color Name Description D22 Blue Detected frame format output D24 D23 D22 000 Reserved Des araen 001 24p or 23 98p or 23 98 psF 010 25p frame format 011 30p or 29 97p 100 50i Het Orange 101 60i or 59 94
48. erties dialog box It is enabled by default Updating Regenerating the IP Core By regenerating an IP core with the IPexpress tool you can modify any of its settings including device type design entry method and any of the options specific to the IP core Regenerating can be done to modify an existing IP core or to create a new but similar one Regenerating an IP Core in Diamond To regenerate an IP core in Diamond 1 In IPexpress click the Regenerate button 2 In the Regenerate view of IPexpress choose the IPX source file of the module or IP you wish to regenerate 3 IPexpress shows the current settings for the module or IP in the Source box Make your new settings in the Tar get box 4 If you want to generate a new set of files in a new location set the new location in the IPX Target File box The base of the file name will be the base of all the new file names The IPX Target File must end with an ipx exten sion 5 Click Regenerate The module s dialog box opens showing the current option settings 6 In the dialog box choose the desired options To get information about the options click Help Also check the About tab in IPexpress for links to technical notes and user guides IP may come with additional information As IPUG82_01 5 December 2011 38 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor IP Core Generation 8 9 the options change the schematic diagram of the module changes to show the l O and th
49. for Tx and Rx paths With the 10 bit mode for SD Tx option SD data is applied at the lower 10 bits of pd_in and the corresponding 27 MHz clock is applied at the pdi_clk input The clock synchronization used in the IP core for the SD 10 bits and SD LDR options are shown in Figure 2 5 SD LDR Mode This is the SD low data rate transmit mode This mode is used if it is necessary to transmit fractional frame rate HD or 3G video and SD video in different channels of the same SERDES quad LatticeECP3 SERDES has only one transmit PLL for each quad This means that the transmit frequencies of different channels in the quad must either be same or one of the permissible divided frequencies If the SERDES PLL is tuned for 2 97 GHz the channels can transmit 2 97 Gbps 1 485 Gbps and 270 Mbps However if the PLL is tuned for 2 967 GHz the channels can only transmit 2 967 Gbps and 1 4835 Gbps They cannot be used to transmit 270 Mbps In this scenario the LDR path is employed for transmitting the SD video In the LDR scheme a serializer is built in the soft logic and its out put is multiplexed with the SERDES serial output at the driver end of the SERDES The multiplexer at the output of the SERDES is dynamically controlled by the SERDES input control signals txd Idr en chx As shown in Figure 2 5 the parallel data for the LDR serializer can come from either the main input data bus pd_in or the dedicated 10 bit SD input bus pd in sd If the data is read from t
50. g Startedi Cem 32 IPexpress Created Files and Top Level Directory Structure i 35 Running Functional Simulation inesatta ate ta oe dy dada 37 Synthesizing and Implementing the Core in a Top Level Design na nn nanna nun nun 37 Hardware Evalu ation dre men Fu ee ect na Nid id enyn te La ee d deb Ba a 38 Enabling Hardware Evaluation in Diamond conan nnnnn nan mnn LLAN nennen nennen nnns 38 Enabling Hardware Evaluation in ispLEVER i 38 Updating Regenerating the IP Core iii 38 Regenerating an IP Core in Diamond i 38 Regenerating an IP Core in ispLEVER conan cana n car nnn nn ran nn ER HYLL LLYR ELLY LEE nanncinas 39 Chapter 5 Application SU pp OTE aar ear erT ea T ra pa cece ett cru eo cu eos ez op erue dina eten 40 Tri Rate SDI PHY IP Loopback and Passthrough Sample Designs i 40 L oopback DEesigni s EE 40 Passthrough Designi a gara deal Ra 41 Simulating th Sample Besign 2 wa p ja a ata 42 Testbench and Configuration File 43 Implementing and Testing the Sample Design i 45 Board Switch Assignments for Sample Designs conca nanna ann nat nc nnne 45 Transmitter Testing caleta a atea 46 Receiver Ostia era 46 EGD DISplay i ia TER 47 Loopback Tesir an enari ARR Y A oe ala E agentes 47 Passthrough Testing ctetu a ia 47 Chapter 6 Core VerlifiCatlOn 06i cruz recu s occu iaa ar
51. hXO source constraint and project files for the loopback and passthrough configurations are created under project dir gt sdi eval module name gt impl lt synplify precision gt Machxo Open the MachXO project by double clicking on the project file and create the bitstream by following the usual process Board Switch Assignments for Sample Designs Both the loopback and the passthrough sample designs use the following reset buttons e Pushbutton switch SW10 Master reset both logic and SERDES reset Depress the switch momentarily for reset Pushbutton switch SW9 SERDES Rx reset Depress the switch momentarily for reset The loopback design uses the DIP switches shown in Table 5 2 The switches have a 0 value when pushed toward the bottom of the board toward the PCI Express fingers They take on a 1 value when pushed toward the top of the board toward the channel link connector Table 5 2 Switch Connections on the VPB Switch Name Description SW1 1 hd_sdn_in SW1 2 tg_hdn_in SW1 3 Ib lan in Pattern generator transmit rate Ib lan in tg hdn in hd sdn in 000 SD 001 HD 011 3Ga 101 3Gb DS 111 3Gb DL Selects the LDR path for the SERDES output when the transmitted rate is SD The SW1 4 txd ldr en switch has no effect when transmitting 3G or HD rates 0 Selects SERDES path 1 Selects LDR path IPUG82_01 5 December 2011 45 Tri Rate SDI PHY IP User s Guide Lattice Semicon
52. he SERDES needs to be employed for SD transmission Figure 2 9 shows this application scenario As shown in the figure a 27 MHZ clock is required for this configuration in addition to the 148 35 MHz fractional frame rate reference clock The control Idr_core2tx_en is driven by hd_sdn_in to switch the SERDES output between the SERDES serializer and the LDR data from the IP core Figure 2 9 Tri Rate IP Usage for Fractional Frame Rate Applications rxiclk_chO rx half clk chO rx_clk folk rxdata_ch0 rxdata o 9 reic b 9 148 35 MHz E duda moda do u gt pd out Clock Source refolkn rx_div11_mode_c rx_hd_sdn Q 9 2 rx_div2_mode_ch0 rx_tg_hdn W f pdo_clk fpga rxrefclk chO E lt g o l Tri Rate hdinp_ch0 J9 9 LatticeECP3 SDI Physical hdinn_ch0 SERDES Layer IP Core hdoutp_ch0 444 txd Idr chO txd Idr 9 hdoutn_ch0 txdata_ch0 txdata 9 amp pd in 7 i lt Os l amp po in sd r P tx_div2_mode_ch0 Idr_core2tx_en r LE tx_div11_mode_ch0 o E l hd_sdn_in tx half clk chO 27 MHz gt txiclk_cho Clock Source CIK27 in pdi clk le tg hdn in IPUG82 01 5 December 201 1 22 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Two sample designs provided with the IP core can be used to implement a complete SDI tran
53. he common input bus the input clock pdi_clk and the LDR clock clk27_in must be freguency synchronized during the time SD is transmitted The 270 MHZ bit rate clock for LDR clk270_in must be exactly 10 times the frequency of clk27_in IPUG82_01 5 December 2011 18 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description VPID Extraction The VPID extraction option enables the extraction of VPID bytes embedded in the horizontal ancillary HANC data area of specific lines in the video stream In addition to the VPID bytes a few other signals are brought out to indi cate a valid VPID the appropriate lines carrying VPID information checksum error and parity error FPGA Tx Interface The FPGA side transmit interface consists of the parallel video data to be transmitted LN VPID input data clocks and rate identification inputs If SD transmission is not used or if the SD parallel data is available as 20 bit 13 5 MHZ data only one clock pdi_clk is required for the entire transmit logic In that case the pdi_clk as well as the txi_clk can both be connected to the Tx half clock from the SERDES However if the SD data is available as a 10 bit 27 MHz data stream the 10 bit mode for SD Tx option needs to be enabled In this case the additional tx_full_clk input can be connected to the Tx full clock from the SERDES The pdi_clk can be a multiplexed version of Tx full clock and Tx half clock from the SERDES Most of the transm
54. i 110 50p 111 60p or 59 94p D26 Red vid active Video active output O Receiver not locked to any video 1 Locked to video LCD Display There are four display pages in the LCD display as shown in Table 5 4 Table 5 4 Display Pages Page 0 Page 1 Page 2 Page 3 Line 1 Tx Rate Format TX VPID Rx VPID Rx PCT Line 2 Rx Rate Format The display for each of the pages is formatted as given below Tx or Rx Rate Format T 3Ga 1080 60i R 3Gb 1080 59 9p TX or RX VPID T VP lt byte1 gt lt byte2 gt lt byte3 gt lt byte4 gt R VP lt byte1 gt lt byte2 gt lt byte3 gt lt byte4 gt Rx PCT Rx Placer error Crc error Time PCT placer error crc error lt time gt Placer error is either a SAV error or an EAV error Time is the time elapsed since reset pushbutton SW8 Use pushbutton switch SW7 to cycle the LCD display through pages Use pushbutton switch SW8 to reset the errors and time Loopback Testing Connect the transmitter output labeled SDI Tx 0 to the receiver input labeled SDI Rx 1 Change the switches to generate different rates and formats and verify the reception at the LCD display You can also remove the loop back cable and connect the output to a SDI monitor and feed the input from a SDI generator Note that the Tx and Rx rates and formats are not related to each other and can be selected independently Passthrough Testing Connect a SDI
55. iani 48 Chapter 7 Support Resources sib i ei iii sea aiar ieri 49 Lattice Technical Support ia e Ba e d e ap EUER ai n a a 49 Online FOrUMSi ili iskrin HY FF NY 49 Telephone Support Hotline ii 49 E Mail Support tec ette add dao uten ics 49 Local SuppOrt ii se a ERR ERE EEPRERRL edis 49 ac a EN 49 Heferernces an uio nu ad 49 Lattice Tri Rate SDI PHY IP Website enne a aaa eE E e PAEA e aeaiia aaa Eai 49 SMTPE WAObSIte o Coed ere ii EET Do PE 49 IPUG82 01 5 December 201 1 3 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Table of Contents LattiCC EG PS FR ios a Ada o FF ra ia 50 Revision HIStory 12 eh chan ie etie ta o ted ic Cer e d ede E iet o three deed d nei 50 Appendix A Resource Utilization 5 eren eso eren tenian innen arabo nho run one d uada annua oaa aea oue E aa eu NUDD nennen 51 lattice ECPI FPGAS n n ht Fen e Sei beh eb tbt a a ef et o ie Eo tutae alieni te redet toe 51 Ordering Information cette p dj Ta Ba i a a aa 51 4 Tri Rate SDI PHY IP User s Guide IPUG82_01 5 December 2011 Semiconductor Introduction a a a a Corporation Lattice Serial Digital Interface SDI is the most popular raw video connectivity standard used in television broadcast stu dios and video production facilities The availability of high speed serial inputs outputs and general purpose pro
56. ing vblank and horizontal blanking hblank timing signals generation CRC computation error checking and insertion for HD 3G Line number LN decoding and encoding for HD 3G e Custom source format support for HD 3G Video Payload Identifier VPID insertion and extraction for HD 3G 10 bit parallel input output support for SD e Soft logic based low data rate LDR serializer for SD transmission Video Interface and Source Format Support This Tri Rate SDI PHY IP core supports SMPTE 259 SMPTE 292 and SMPTE 424 interface standards IPUG82_01 5 December 2011 6 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Introduction SMPTE 259 standard is applicable to 4 2 2 video streams defined by SMPTE 125M and SMPTE 267M These source formats are briefly described below 1 SMPTE 125M System M 525 lines and 60 fields based on ITU R BT 601 The video is transmitted in the form of one luminance Y and two color difference components scaled versions of R Y and B Y It follows a 4 2 2 family level of ITU R BT 601 with a nominal luminance sampling at 13 5 MHz allowing for both 8 bit and 10 bit data types 2 SMPTE 267M System M 525 lines and 59 94 fields wide screen 16x9 aspect ratio based on ITU R BT 601 The video is transmitted in the form of one luminance Y and two color difference components scaled versions of R Y and B Y It follows a 4 2 2 family level of ITU R BT 601 with a nominal luminance sampling at 13 5 MHz or 1
57. it logic and the data output to SERDES Tx uses tx_half_clk as shown in Figure 2 5 When the 10 bit mode for SD Tx option is enabled the 10 bit parallel input for SD video is applied at pd_in_sd In this case the SD transmit path is independent and asynchronous with the HD 3G transmit path The SD data is applied with respect to the clk27_in clock and the entire SD transmit logic operates with this clock In addition to the 27 MHZ clock another bit rate clock at 270 MHz having exactly 10 times the frequency of the 27 MHz clock is also required for the LDR transmission If the Include PLL for LDR option is selected the 270 MHz clock is inter nally generated within the IP In this case both the 27 MHz and the 270 MHz clocks are given out through clk27_out and clk270_ out ports Custom Format Valid HD and 3G rates are identified by matching the relative time instants of EAV and SAV timing signals to the possible source format standards in that rate The IP supports receiving non standard formats by accepting cus tom formats for 3G and HD rates The custom formats are specified by the time from EAV to SAV and from SAV to EAV The time can be specified as a fixed value or a range defined by a minimum and a maximum The custom for mat for 3G b is set based on the format of the stream 1HD component that is part of the 3G video Advanced Settings The Advanced Settings tab allows the user to specify the programming time and threshold values The pr
58. lynomials used are given in the sub section on the scrambler The decoder descrambler is imple mented in the 20 bit parallel path The input data is first decoded to NRZ and then descrambled following an essen tially reverse process of the encoding and scrambling operations Word Alignment TRS Detection The receiver reads the raw possibly misaligned parallel data from the SERDES The word alignment block deter mines the degree of misalignment offset by looking for the special TRS sequences in the data TRS is the unique sequence 3FFh 000h 000h in the video stream that marks either the end of active video EAV or the start of active video SAV time instants In HD and 3G Level A video streams since two independent video streams are interleaved the timing reference sequence to look for is 3FFp 3FFh 0004 000h 000 000 The TRS for 3G Level B video is 3FF 3FF 3FFh 3FFh 000 0005 0005 0004 0004 000 0004 0004 Once the offset is deter mined the words are re aligned using the offset value Rate Detection and Control This module is the heart of the multi rate SDI receiver infrastructure Rate detection is the process of determining the interface standard of the incoming video stream Rate detection is performed by sequentially scanning the input for different interface standards During each rate scan the receiver identifies the rate that is being scanned through some output ports to allow the external modules like the SERDES an
59. me will be the base of all the new file names The LPC Target File must end with an lpc exten sion Click Next The IP core s dialog box opens showing the current option settings In the dialog box choose desired options To get information about the options click Help Also check the About tab in the IPexpress tool for links to technical notes and user guides The IP core might come with addi tional information As the options change the schematic diagram of the IP core changes to show the I O and the device resources the IP core will need Click Generate Click the Generate Log tab to check for warnings and error messages IPUG82_01 5 December 2011 39 Tri Rate SDI PHY IP User s Guide 511 Semiconductor Application Support uuu Corporation Lattice crs This chapter provides application support information for the Tri Rate SDI PHY IP core Tri Rate SDI PHY IP Loopback and Passthrough Sample Designs When the Tri Rate SDI PHY IP core is generated using IPexpress two sample top level designs are created The designs named loopback and passthrough are created under lt project dir gt sdi eval impl lt synplify precision gt loopback and lt project dir gt sdi eval impl lt synplify precision gt passthru respectively Further informa tion about these two designs is given in the following sections The designs can be implemented directly on the LaiticeECP3 Video Protocol Board VPB if the IP was cr
60. ments set forth in SMPTE 259M SMPTE 292M and SMPTE 424M standards The scrambler implements the following equation G4 x x x 1 The NRZI encoder is defined by the following equation Go x 2 x 1 Low Speed Serializer This block is the FPGA fabric based serializer used for SD video transmission This is required when fractional frame rate HD 3G and SD streams are to be transmitted from different channels of the same SERDES quad In this scenario the low speed serializer replaces the SERDES serializer for SD transmission Signal Descriptions The top level interface for the Tri Rate SDI PHY IP core is shown in Figure 2 4 A brief description of the signals is given in Table 2 1 While the figure and table show the exhaustive port list for the IP core some ports may not be available for a selected configuration IPUG82 01 5 December 201 1 12 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Figure 2 4 Tri Rate SDI PHY IP Core Top Level Interface rxdata gt rx_clk T rx full ck gt rx hd sin amp 4 rx tg hdn amp __ rx lb lan 4 4 rsin Pl ce gt txd_ldr lt lt txdata amp SERDES Board Rx Interface Common Interface SERDES Board Tx Interface Tri Rate SDI PHY IP Core FPGA Rx Interface FPGA Tx Interface tt pd out m pdo_clk gt vid active gt vid format Pb frame format m trs out gt ychann
61. n1 out a In2 out previous line number M current line number yl crc error y1_crc_error X IPUG82_01 5 December 2011 24 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Figure 2 14 Rx Data and Status Signals for 3G b rx_clk Moe ary 3FF Y 000 X 000 X 000 X 000 X XYZ X xz y LNO X LNO X UNI X LN1 X GRO X GRO X CRI X E B i Latencv pd out I I i ee xX 3FF X 3FF Y 000 x 000 X 000 x 000 y XYZ X xz y LNO K LINO N UN1 X LN1 n GRO trs_out field hblank y vblank In1_out 1 e previous line number current line number In2 out yl crc error mM yl crc error i i Figure 2 15 Control Signals for Rx Side Rate Variations Rx input 3G SD men HD 3G stream n hd sdn q 3G SD HD 3G so HD 3G rx_tg_hdn pd out 3G SD e HD 3G vid_active IPUG82_01 5 December 2011 25 Tri Rate SDI PHY IP User s Guide Lattice cp 55 Semiconductor Parameter Settings a a a Corporation The IPexpress M tool is used to create IP and architectural modules in the Diamond and ispLEVER software Refer to IP Core Generation on page 32 for a description on how to generate the IP
62. ne clock cycle wide pulse that identifies the TRS instance in the parallel input data This input is high dur ing the start of the TRS sequence for HD and 3G a inputs i e during the time when FFFFF is presented on pd in For 3G b video this input is high during the Y channel FFFFFy word The trs_in signal is used for the computation of CRC as well as to deter mine CRC LN and VPID insertion instants This signal is not used for SD or if CRC LN and VPID insertions are all disabled for HD 3G hd_sdn_in HD SD input This input must be zero to transmit SD video and one for 3G or HD video Ib lan in 3G Level B indicator input This input must be one if the input is a 3G b video and zero otherwise sdab mode IPUG82 01 5 December 2011 SD 8 bit mode If this input is high the incoming data is considered to be 8 bits wide Only the most significant 8 bits bits 9 2 are read from the port The least significant 2 bits are set to zero for all data except the leading TRS sequence or ANC identifier When the most significant 8 bits are 1 s then the least significant 2 bits are made equal to 11 16 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Table 2 1 Top Level I O Interface Continued Port Bits I O Description Line number input This input is read in HD 3G modes only The line number is read in Int in 11 when In1 set is high When transmitting 3G b vi
63. ntroduction Quick Facts Table 1 1 gives quick facts about the Tri Rate SDI PHY IP core for LatticeECP3 devices Table 1 1 Tri Rate SDI PHY IP Core Quick Facts Tri Rate SDI PHY IP Core Tx Only Rx Only Both Tx and Rx FPGA Families Supported LatticeECP3 Core Requirements Minimal Devices Needed LFE3 17EA 6FTN256C Targeted Device LFE3 95EA 7FN1156C Data Path Width 20 Typical Resource Utilization LUTs 850 1700 2500 svsMEM EBRs 0 Registers 500 1300 1800 Lattice Implementation Lattice Diamond 1 3 or ispLEVER 8 1 Synopsys Synplify Pro for Lattice E 2011 03L Synthesis Mentor Graphics Precision RTL Synthesi 4 phics Precision ynthesis Design Tool Support 2010a_Update 2 254 Aldec Active HDL 8 2 Lattice Edition Simulation Mentor Graphics ModelSim SE 6 5 1 Design tool support for IP core version 1 3 Features e Dynamic reception of multiple interface standards over the same physical cable SD SDI HD SDI and 3G SDI interfaces Automatic Rx receive rate detection and dynamic Tx transmit rate selection Multiple SD source formats support SMPTE 125M 4 and SMPTE 267M 5 13 5 MHz only Multiple HD source formats support SMPTE 260M 6 SMPTE 274M 7 SMPTE 295M 8 and SMPTE 296M 9 e Support for 3G source formats including 3G Level B format SMPTE 425M 10 e Word alignment and timing reference sequence TRS detection Field vertical blank
64. ogram ming time is specified by a number proportional to the time from which the receiver waits from switching to a new rate and before looking for TRS matches for that rate Lock match threshold is the number of TRS matches to wait before locking to a video rate Unlock error threshold is the number of TRS or timeout errors after which the receiver unlocks to scan for the next rate SERDES Board Rx Interface The deserialized parallel output from the SERDES can be directly connected to the rxdata port The parallel data connection to and from the SERDES is always 20 bits wide irrespective of any SD 10 bit mode set in the IP The parallel data is read in using rx_clk If the data comes directly out of the SERDES Rx then the Rx recovered clock from the SERDES must be connected to the rx_clk input If the 10 bit mode for SD Rx option is enabled the IP core needs the 27 MHz recovered clock for the SD data to be applied at the rx_full_clk port The output signals rx_hd_sdn rx_tg_hdn and rx_Ib_lan indicate the rate that the receiver is trying to receive or lock on to It is important for that these signals be used to promptly change the SERDES divider settings or the fre quency of the clock generator that supplies the input clock ports The outputs rx_hd_sdn and rx_tg_hdn can be used to drive the clock divider controls of the LatticeECP3 SERDES to select one of the three rates 3G HD and SD to receive IPUG82_01 5 December 2011 19 Tri Rate SDI P
65. r one of the rates is disabled when that rate is being received the reception is not affected FPGA Tx Interface pd_in 20 Parallel data input This is the parallel video data for transmission The data is read with pdi_clk If the 10 bit mode for SD Tx is enabled only the lower 10 bits of the data are read in when reading SD data pdi_clk tx_half_clk Clock input for the parallel input data The data at pd_in is read using this clock This clock should have the same frequency as the transmit reference clock to the SERDES divided appropriately by 1 2 and 11 for 3G HD and SD respectively In a typical usage this clock is the same as Tx half clock from the SERDES if 10 bit mode for SD Tx is disabled and a multiplexed version of Tx half clock and Tx full clock if 10 bit mode for SD Tx is enabled This additional clock input is required if the 10 bit mode for SD Tx option is selected This clock must be frequency synchronous with pdi_clk and must correspond to the 20 bit data width The frequency of this clock is 148 5 MHz or 148 35 MHz for 3G 74 25 MHz or 74 175 MHZ for HD and 13 5 for SD The SERDES tx_half_clk output can be connected to this input as long as pdi_clk is derived from the same SERDES output clock pd_in_sd 10 Optional parallel data input for SD If available the data on this port is read in with clk27_in trs_in Timing Reference Sequence identifier for the input video stream This is a o
66. r s responsibility to make sure the CRC check words take into account the encoded LN words also CRC Insertion If this parameter is selected the core computes the CRC values for the incoming line and inserts them at the appropriate places in the line This is available for HD and 3G modes only The parallel input data from the pd_in port is directly used word by word for transmission in most cases If the input is HD or 3G there is an option to have the IP core compute CRC for each input data line and insert that in appro priate places in the transmitted data stream If the CRC Insertion option is disabled off then it is assumed that the incoming data comes with the appropriate CRC words in it VPID Insertion This control selects whether VPID is inserted by the IP If VPID insertion is enabled an input port vpid1_in is avail able if 3G b support is also enabled a second input port vpid2_in is provided for reading in the VPID bytes The VPID bytes read from the input port are formatted with other standard words and inserted at appropriate places in the input video stream depending on the format of the input as determined from the input VPID bytes VPID inser tion is available for HD and 3G modes only The VPID insertion option enables automatic insertion of the video payload identifier to the video stream according to SMPTE 352M specifications The IP converts the raw VPID bytes from the user to a 352M ANC payload by add ing ancillary
67. r the receive refer ence clock Only one clock source 148 5 MHz is required for the transmission and reception of all the three SDI rates Multi rate compatibility is achieved using the built in clock dividers and multiplexers in the SERDES IPUG82 01 5 December 201 1 21 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Figure 2 8 Tri Rate IP Usage for Integer Frame Rate Applications o rxiclk_chO rx_half_clk_chO rx_clk 8 o gt 5 refclk rxdata_chO rxdata 5 148 5 MHz ere yy E gt pd_out Clock Source refclKn gi rx_div11_mode_ch0 Pchd_sdn o E fpga_rxrefclk_chO rx_rate_mode_ch0 rx_tg_hdn lt im hdinp cho ml LatticeECP3 Tri Rate SERDES SDI Physical hdinn_ch0 M g Layer IP Core hdoutp_ch0 4 4 o E pdin o 8 hdoutn_ch0 4 E hd sdn in txdata cho txdata DE mp tx div2 mode chO ed x tx divi1 mode chO u Cl A tx_half_clk_chO iva pdi_clk txiclk_chO Lu 0 lt tg_hdn_in As shown above one 148 5 MHz clock source is sufficient for multi rate transmission reception as long as frac tional frame rate HD 3G transmission is not required Fractional Frame Rate Applications In order to transmit fractional frame rate HD or 3G simultaneously with SD transmission in the same SERDES quad the low data rate LDR transmit path in t
68. rate standards can be easily determined by con structing a small logic circuit outside the IP to compare the frequency of the receive recovered clock with that of another clock of known frequency like the receive reference clock or the 100 MHz clock available on the LatticeECP3 Video Protocol Board Format Detection This module determines the source format of the input video stream The format is based on the number of active words number of total words and whether the video is interlaced The format is provided through the vid_format and frame_format output ports For 3G Level B video 3G b the stream 1 video data is used for format detection CRC Checker The CRC checker computes the CRC values for each of the video streams and components and compares those with the CRC values available in CRO and CR1 words of the received video In HD and 3G Level A video 3G a streams there are two CRC words per line that contain the CRC value for the previous line The CRC checker com putes the CRC for each line compares with the received CRC and flags an error if there is a mismatch For 3G b there are four CRC words one each for the Y and C components of each stream Errors are flagged separately for each of the four CRC comparisons XYZ Word Decoder This block decodes the XYZ word that follows the TRS in the video stream By decoding the XYZ word the video timing signals field hblank horizontal blanking and vblank vertical blanking a
69. re determined XYZ word is also used to determine whether the TRS corresponds to an EAV or a SAV instant LN Decoder In HD and 3G video formats the line number is encoded as a two word sequence and inserted after the XYZ word of the EAV sequence The LN decoder block decodes the line number from the LN double words and gives out the line number value on the In1_out port For 3G b the line numbers for stream 1 and stream 2 video are separately given out on In1_out and In2_out ports respectively IPUG82_01 5 December 2011 10 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description VPID Extraction The VPID extraction module extracts the video payload information SMPTE 352M 11 embedded in the HANC part of the video stream In addition to the VPID bytes this module also provides some error and status signals The status signal vp1_valid indicates whether the last received VPID information was valid and the signal vp1_lineok indicates if the VPID was available in the appropriate line numbers for the received format The error signals vp1_cserr and vp1_parerr are used to denote the checksum error and parity error respectively Transmitter The transmitter supports dynamic multi rate operation catering to SD HD and 3G standards The transmit rate is set through the input ports hd_sdn_in and Ib_lan_in as well by the frequency of pdi_clk The transmitter and receiver are independent of each other and each can be used to tr
70. ri Rate SDI PHY IP User s Guide Lattice Semiconductor Support Resources 3 SMPTE 424M 2006 Television 3 Gbps Signal Data Serial Interface 4 SMPTE 125M 1995 Television Component Video Signal 4 2 2 Bit Parallel Digital Interface 5 ANSI SMPTE 267M 1995 Television Bit Parallel Digital Interface Component Video Signal 4 2 2 16x9 Aspect Ratio 6 SMPTE 260M 1999 Television 1125 60 High Definition Production System Digital Representation and Bit Parallel Interface 7 SMPTE 274M 2003 Television 1920 x 1080 Image Sample Structure Digital Representation and Digital Tim ing Reference Sequences for Multiple Picture Rates 8 SMPTE 295M 1997 Television 1920 x 1080 50 Hz Scanning and Interface 9 SMPTE 296M 2001 Television 1280 x 720 Progressive Image Sample Structure Analog and Digital Repre sentation and Analog Interface 10 SMPTE 425M 2006 3Gbps Signal Data Serial Interface Source Image Format Mapping 11 SMPTE 352M 2002 for Television Dynamic Video Payload Identification for Digital Interfaces 12 SMPTE 291M 2006 for Television Ancillary Data Packet and Space Formatting LatticeECP3 e HB1009 LatticeECP3 Family Handbook e EB39 LatticeECP3 Video Protocol Board User s Guide e TN1176 LatticeECP3 SERDES PCS Usage Guide Revision History Document IP Core Date Version Version Change Summary May 2009 01 0 1 0 Initial release October 2009 01 1 1 1 Added support for 3G Level B and VPI
71. rt There are a number of ways to receive technical support Online Forums The first place to look is Lattice Forums http www latticesemi com support forums cfm Lattice Forums contain a wealth of knowledge and are actively monitored by Lattice Applications Engineers Telephone Support Hotline Receive direct technical support for all Lattice products by calling Lattice Applications from 5 30 a m to 6 p m Pacific Time For USA amp Canada 1 800 LATTICE 528 8423 e For other locations 1 503 268 8001 In Asia call Lattice Applications from 8 30 a m to 5 30 p m Beijing Time CST 40800 UTC Chinese and English language only For Asia 86 21 52989090 E mail Support e techsupport Olatticesemi com e techsupport asia O latticesemi com Local Support Contact your nearest Lattice Sales Office Internet www latticesemi com References Lattice Tri Rate SDI PHY IP Website Information on the Lattice Tri Rate SDI PHY IP can be found at http www latticesemi com producis intellectualproperty ipcores triratesdiphy cfm SMTPE Website The Society of Motion Picture and Television Engineers SMPTE website contains specifications and documents referred to in this user s guide The SMPTE URL is http www smpte org 1 SMPTE 259M 2006 SDTV Digital Signal Data Serial Digital Interface 2 SMPTE 292M 1998 Television Bit Serial Digital Interface for high Definition Television Systems IPUG82_01 5 December 2011 49 T
72. s EAV2SAV Cycles Minimum When the custom format parameter is set to Range this parameter specifies the minimum value for the EAV2SAV cycles range EAV2SAV Cycles Maximum When the custom format parameter is set to Range this parameter specifies the maximum value for the EAV2SAV cycles range SAV2EAV Cycles Value This is the value for the gap between the SAV and the EAV The value is computed as Words active line 3 for HD 2 Words active line 3 for 3G a 2 Words active line 7 for 3G b SAV2EAV Cycles Minimum When the custom format parameter is set to Range this parameter specifies the minimum value for the SAV2EAV cycles range SAV2EAV Cycles Maximum When the custom format parameter is set to Range this parameter specifies the maximum value for the SAV2EAV cycles range Advanced Tab Figure 3 3 shows the contents of the Advanced tab Figure 3 3 Advanced Tab PHY Custom Format Advanced Advanced settings 36 programming time 3 HD programming time 3 SD programming time 3 Lock match threshold 3 Unlock error threshold 3 3G HD SDProgram Time Programming time for 3G HD SD This parameter defines how long to wait for the SERDES to be programmed after the Rx scan rate is changed The duration is specified by a number which is approximately equal to the number of total words in a line Lock Match Threshold This parameter specifies the number of TRS ma
73. s capable of receiving any of the video formats specified in the SMPTE 259M SMPTE 292M and SMPTE 424M interface standards through the same physical input without the need for any manual intervention The receiver can dynamically support the different video stream rates SD video at 270 Mbps HD integer frame rate video at 1 485 Gbps HD fractional frame rate video at 1 4835 Gbps 3G integer frame rate video at 2 97 Gbps and 3G fractional frame rate video at 2 967 Gbps The multi rate receiver cyclically scans for each of the video rates until it identifies and locks to the incoming video data When scanning for a video rate the IP core gives out the interface rate that it is trying to receive The SERDES settings and reference clocks have to be changed to match this rate information If there is a valid video corresponding to the scanned rate the IP core locks to the video source and provides the parallel data and status outputs for that video If no video is received or if there are multiple errors in the received data the receiver goes on to scan the next rate The scanning process continues until the receiver locks to the incoming video that is when the video data reception is valid and error free for a few lines of video data The Tri Rate SDI PHY IP core is also capable of supporting dynamically varied transmit rates The different video rates viz SD HD and 3G are identified by the rate select input signals The Tri Rate SDI PHY IP core ass
74. smit receive system on the LatticeECP3 Video Protocol Board The designs are available in the user s IP project directory after the Tri Rate SDI PHY IP is generated A detailed explanation of the sample designs and their usage is provided in the Tri Rate SDI PHY IP Loopback and Passthrough Sample Designs User s Guide available in the IP project directory Timing Specifications The timing for the Tx data and controls for HD 3G a is given in Figure 2 10 The Tx timing for 3G b is shown in Figure 2 11 Figure 2 10 Tx Data and Controls for HD 3G a pdi_clk T Set LN at least 3 cycles before LNO In1 set if i l l i 3 l Ini_in l l l l l l me TA e A Bil x Y X 000 Y cao Y XYZ M LNO Y LN1 kf cho M CRI Y anco Y dus Y 3FF M 000 Figure 2 11 Tx Data and Controls for 3G b pdi_clk In1_set o FTA In2 set po MEN pi 4 gt In1_in TIT y l Y Xi i i In i i x In2_in l L l j i i wn VT n xX ES WT Y 7 Y 000 y TEL K XYZ Y de K LNO K 1T y TT Y cro Y um Set LN at least 3 cycles before LNO For SD transmission the trs in signal is not used For HD and 3G a inputs trs in must coincide with the 3FF data as shown in Figure 2 10 However for
75. t This output identifies the number of fields and whether the video is interlaced or progressive as follows 000 Unknown or custom 001 24p or 23 98p or 23 98psF 010 25p 25psF 011 30p or 29 97p or 29 97psF 100 50i 101 60i or 59 94i 110 50p 111 60p or 59 94p For 3G b outputs the frame format corresponds to stream 1 video trs out Timing reference sequence output This output is high during the start of the TRS sequence i e during the time when 3FF or FFFFF is available on pd out For 3G b video this output is high during the Y channel FFFFF word ychannel Y channel indicator This output is meaningful only when 3G b video is received This out put is one when Y channel data is given out at pd out and zero when C channel data is given out field Field number This is the field number information available in the XYZ word The field value at this output changes state when the XYZ word appears at the output For 3G b video the field output corresponds to stream 1 video and it changes state when the y channel XYZ word appears at the output vblank Vertical blanking signal The value at this output changes state when the XYZ word appears at the output For 3G b video the vblank output corresponds to stream 1 video and it changes state when the y channel XYZ word appears at the output hblank Horizontal blanking signal The value at this output changes state when th
76. t an IP license The Tri Rate SDI PHY IP core also supports Lattice s IP hardware evaluation capability which makes it possible to create versions of the IP core that operate in hardware for a limited time approximately four hours without reguiring an IP license See Hard ware Evaluation on page 38 for further details However a license is reguired to enable timing simulation to open the design in the Diamond or ispLEVER EPIC tool and to generate bitstreams that do not include the hardware evaluation timeout limitation Getting Started The Tri Rate SDI PHY IP core is available for download from the Lattice IP Server using the IPexpress tool in Dia mond or ispLEVER The IP files are automatically installed using ispUPDATE technology in any customer specified directory After the IP core has been installed it will be available in the IPexpress GUI dialog box shown in Figure 4 1 The IPexpress tool GUI dialog box for the Tri Rate SDI PHY IP core is shown in Figure 4 1 To generate a specific IP core configuration the user specifies Project Path Path to the directory where the generated IP files will be loaded File Name username designation given to the generated IP core and corresponding folders and files Diamond Module Output Verilog or VHDL ispLEVER Design Entry Type Verilog HDL or VHDL Device Family Device family to which IP is to be targeted e g LatticeSCM Lattice ECP2M LatticeECP3
77. tches necessary for the receiver to be locked to the video Unlock Error Threshold This parameter specifies the number of TRS errors to tolerate before the receiver switches to the unlocked state or to scan for the next rate IPUG82 01 5 December 201 1 31 Tri Rate SDI PHY IP User s Guide Semiconductor IP Core Generation uuu Corporation 3 L atti C a Chapter 4 This chapter provides information on how to generate the Tri Rate SDI PHY IP core using the Diamond or isp LEVER software IPexpress tool and how to include the core in a top level design The Tri Rate SDI PHY IP core can be used in LatticeECP3 device families For information and known issues on this core see the Lattice Tri Rate SDI PHY IP Readme document This file is available once the core is installed in Diamond or ispLEVER The document provides information on creating an evaluation version of the core for use in Diamond or ispLEVER and simulation Licensing the IP Core An IP core and device specific license is required to enable full unrestricted use of the Tri Rate SDI PHY IP core in a complete top level design Instructions on how to obtain licenses for Lattice IP cores are given at http www latticesemi com products intellectualproperty aboutip isplevercoreonlinepurchas cfm Users may download and generate the Tri Rate SDI PHY IP core and fully evaluate the core through functional sim ulation and implementation synthesis map place and route withou
78. th clk270_out and is available if clk27_out 1 O Include PLL for LDR is selected This clock along with cIk270 out is useful for feeding another IP instance High speed SD LDR clock output This 270 MHz clock is synchronous with clk27_out and clk270_out 1 O is available if Include PLL for LDR is selected This clock along with clk27_out is useful for feeding another IP instance Interfacing with Tri Rate SDI PHY IP Core The Tri Rate SDI PHY IP core is a single channel transmit receive PHY and it does not include the SERDES This section provides some detail on interfacing with the IP including connecting the IP with the LatticeECP3 SERDES SERDES Board Tx Interface The encoded and formatted parallel data from the IP core is given out of the 20 bit txdata output port This directly connects to the SERDES parallel input for serialization The output from the IP is synchronous with tx_half_clk or pdi_clk depending on whether 10 bit mode for SD Tx is enabled or not By deriving the pdi_clk from SERDES Tx half clock and Tx full clock the data can be made synchronous with the SERDES Tx PLL clock The Tx half clock from the SERDES can then be used to drive data into SERDES Tx for SERDES txi_clk Refer to Figure 2 5 for an illustration of how the clocks and data are synchronized for the Tx path IPUG82_01 5 December 2011 17 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Figure 2 5 LDR and
79. tream 1 video ci crc error This signal indicates that a CRC error has been detected for the c channel of the current line This output is not valid for SD video rates The CRC error output goes high during the clock cycle when the CRC comparison is made When 3G b video is being received this output denotes CRC error for the c channel of stream 1 video y2 crc error This signal is valid only when receiving 3G b video This output indicates that a CRC error has been detected for the y channel of the current line of stream 2 video C2 crc error This signal is valid only when receiving 3G b video This output indicates that a CRC error has been detected for the c channel of the current line of stream 2 video vpidi out vpid2 out 32 Video payload identifier output This output is not valid when receiving SD video The VPID bytes are organized as follows byte4 byte3 byte2 byte1 When receiving 3G b video this output corresponds to the VPID for stream 1 The stream 2 VPID in that case is available at vpid2 out port IPUG82 01 5 December 201 1 15 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Table 2 1 Top Level I O Interface Continued Port Bits 1 0 Description vp1_valid vp2_valid O VPID valid output This output indicates that the VPID received is valid as determined by the ADF DID and SDID words When receiving 3G b video
80. ulator IPUG82 01 5 December 201 1 42 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Application Support Testbench and Configuration File The testbench instantiates and tests the demo design that includes the SDI IP Lattice video pattern generator and a data checker The testbench applies a number of different video streams each spanning a certain number of lines The total number of video streams to be applied and the rate standard and number of lines for each video stream are read from the configuration file sdi_config mem This configuration file can be edited to change the test patterns or their duration A sample configuration file with comments is shown below Sample sdi_config mem File All entries are in binary 00000110 gt Number of video streams to be applied 6 101 gt Rate 000 SD 001 HD 011 3Ga 101 3Gb DS 111 3Gb DL 00111 Video Pattern number refer to Table 1 000000000100 gt Number of lines of video to apply after lock 011 l 01111 Data for video stream 2 000000000100 001 01100 000000000100 111 l 01110 Data for video stream 4 000000000100 000 01010 000000000100 011 00010 000000000100 The Lattice video pattern generator module provided with the IP can generate different types of color bar and path ological patterns The pattern numbers for different video formats and rates are given in Table 5 1 Table 5 1 Pattern Generator Standards
81. umes that the clocks and the data applied at the inputs correspond to the rate select signals Receiver A high level block diagram of the tri rate SDI receiver is shown in Figure 2 2 The receive side logic is comprised of the following logic blocks decoder descrambler word alignment TRS detection rate detection and control format IPUG82_01 5 December 2011 8 Tri Rate SDI PHY IP Users Guide Lattice Semiconductor Functional Description detection CRC checker XYZ word decoder LN decoder and VPID extraction module A description of each of these blocks is given below Figure 2 2 Tri Rate SDI Receiver High Level Block Diagram rx lb lan 4 Rate lt rx_rate nctg_sdn 4 Detection p eav error rx hd sdn Control p sav error A pP vid active trs out Word us mala Decoder Alignment e ychannel Descrambler b TRS gt d_out Polk Detection RE Format gt vid format Detection M frame format Lp vi erc error CRC m c1 crc error Checker J y2 crc error m c2 crc error gt field gt vblank I hblank xyz Word Decoder LN gt In1 out Decoder gt In2_out Y vpidi_out VPID m vp1_valid gt vpi_cserr gt vp1_parerr gt vp1_lineok Extraction Decoder Descrambler All the interface standards supported by the Tri Rate SDI PHY IP core specify the same scrambling and encoding methods The po
82. urned off to reduce the device utilization The 3G Level B parameter enables the removal of 3G b support in the IP core when it is not required Disabling 3G b support in the IP results in reduced device utilization Since the 3G b video contains two independent HD streams the Level B option adds several I O ports to support the second stream These include ports for line num ber input line number output CRC error output VPID input VPID output and VPID status outputs IPUG82_01 5 December 2011 27 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Parameter Settings LN Insertion This parameter determines whether line number is calculated and inserted in the Tx data If LN insertion is selected the core reads the raw line number value s from the input port s encodes to LN words and inserts them at appropriate locations LN insertion is available for HD or 3G modes only If it is required to insert line numbers in the format required by the SMPTE 292 424 standards the IP core can be set to encode the raw line number information at the input ports to the two line number words in the stream The values at In1_in and In2_in are read into registers whenever the signals In1_set and In2_set respectively are asserted high The line number values at the registers are read in when the XYZ word is presented at pd_in encoded and inserted after the XYZ word in the transmitted stream If LN insertion is on and CRC insertion is off it is the use
83. x_rate input can be used to independently disable the scanning of a rate or a combination of rates The scan enable inputs can be dynamically changed Rate scan disable applies only when the receiver goes on to scan a rate Therefore disabling a rate that is being currently received or locked on to will not affect the reception of that rate SD 10 Bit Mode for Rx Similar to the 10 bit option for SD Tx the 10 bit option for SD Rx provides SD data output at 27 MHz and 10 bits A block diagram of the 10 bit mode is shown in Figure 2 6 The SD output is available at the lower 10 bits of the com mon pd_out port If this option is selected the IP provides an output clock pdo_clk that is synchronous with the output data The output clock pdo_clk is the multiplexed version of rx_half_clk and rx_full_clk the recovered clocks from the SERDES Video Payload Identification and Extraction The 4 byte video payload identifier VPID added to the ancillary data space of SDI interfaces is defined in the SMPTE 352M standard The VPID bytes are added as ancillary data and follow the general format of ANC data defined by the SMPTE 291M 12 standard The VPID is inserted in the y channel for 3G b in the y channel of both stream 1 and stream 2 videos on particular video lines depending on the video format Figure 2 7 shows the organization of VPID bytes in the SDI formatted data IPUG82_01 5 December 2011 20 Tri Rate SDI PHY IP User s Guide Lattice Semicondu
84. ynchronous active low reset signal This signal resets all the registers in the IP ce FPGA Rx Interface Optional clock enable signal A zero input at ce freezes all the switching operations in the IP It is useful for putting the IP in a power save mode pd_out 20 Parallel data output This is the parallel video data output from the receiver This data is synchronous with the receiver clock rx_clk if 10 bit mode for SD Rx is disabled It is syn chronous with the pdo_clk if 10 bits mode for SD Rx is enabled pdo_clk Parallel data output clock This clock port is available when the 10 bit mode for SD Rx option is selected This clock is a multiplexed version of rx_clk and rx_full_clk If this clock is available the output data as well as output status and control signals are synchronous with this clock vid_active Video active signal This output signal is high if the receiver is locked to a valid video stream at the receiver input vid_format Video format output The format is identified as follows 00 1440 x 486 576 01 1280 x 720 10 1920 x 1035 11 1920 x 1080 For 3G b outputs the video format corresponds to stream 1 video IPUG82 01 5 December 201 1 14 Tri Rate SDI PHY IP User s Guide Lattice Semiconductor Functional Description Table 2 1 Top Level I O Interface Continued Port Bits 1 0 Description frame_format Frame format outpu

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