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Signal Integrity Development Kit, Stratix V GT Edition User Guide

1. Power Monitor Control Port Molex x4 Transceivers Setting aggressor 1 aggressor 4 4 aggressor 2 aggressor 5 aggressor 3 aggressor 6 Data type Error control Detected errors 0 57 Inserted errors 0 Insert Error Bit error rate 5 185363 08 Loopback Tx Messages Detected XCVR 1 Project Stop Tx MBps 1289 0803 Rx MBps 1289 0808 No external loopback board is provided A loopback backplane can be purchased from Molex The following sections describe the controls on the Molex tab Status m The Status control displays status information during the loopback test For details on this control refer to Status on page 6 11 Port The Port control allows you to specify the type of test to run on the Molex port The following Molex port test is available m Molex x1 Transceivers Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 6 Board Test System 6 17 Using the Board Test System PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface For details refer to PMA Setting on page 6 12 Data Type The Data type control specifies the type of data contained in the transactions For details refer to Data Type on page 6 1
2. e EE 6 12 EtrotConttol doe er ante e Ed aes 6 13 Eger 6 13 The Amphenol rh ES RR CREE er RE e p eR eA nbl pk e er 6 14 Status ee eek abe EU S eC SR E ERG a eet 6 14 POPE bos RUD du 6 14 PMA Setting ae bet e EE E RERECEIE as Pade EE EE 6 15 Data TY pe e 6 15 Error IRR ERI MK 6 15 Loopback iyu seu ota eee t este Vl ate er pa aces 6 15 The Molex cr hee e RE hc UE Y ER ERG p GO OE dE 6 16 ER E AMI RA pe AP ee et aaa een tg AU e ADR nae 6 16 POPE ce Uia YS E AR GR p E KG RES 6 16 Setting es e p SHEER TR bodes ee RE bow Avs SE Yee td e EP e E 6 17 Data Type Ep 6 17 Etror Control 535r bre aa debe bus wh aa gana bebe aAa 6 17 Loopback orero ES 6 17 Tab soy ERE wee eb WA ad ae xt Va pt ed 6 18 eee Gace Rates 6 18 lo whats 6 18 PMA Setting dative ba ea cate KAY eR e Ried 6 19 Data vee eae pua we
3. The following sections describe the controls on the GXB MMPX tab Status The Status control displays status information during the loopback test For details on this control refer to Status on page 6 11 Port GTB Transceivers 0 GT channel 0 m GTB Transceivers 1 GT channel 1 m GTB Transceivers 2 GT channel 2 Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide February 2013 Altera Corporation Chapter 6 Board Test System 6 19 Using the Board Test System m Transceivers 3 GT channel 3 PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface For details refer to PMA Setting on page 6 12 Data Type The Data type control specifies the type of data contained in the transactions For details refer to Data Type on page 6 12 Error Control This control displays data errors detected during analysis and allows you to insert errors For details refer to Error Control on page 6 13 Loopback This control allows you control and analyze loopback performance For details refer to Loopback on page 6 13 February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide Chapter 6 Board Test System 6 20 Power Monitoring Power Monitoring To measure and view current power information for the development board you need to ins
4. 6 10 Chapter 6 Board Test System Using the Board Test System Status The Status control displays status information during the loopback test For details on this control refer to Status on page 6 11 Port Use the following controls to select an interface to apply PMA settings data type and error control m SFP m XFP PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface For details refer to PMA Setting on page 6 12 Data Type The Data type control specifies the type of data contained in the transactions For details refer to Data Type on page 6 12 Error Control This control displays data errors detected during analysis and allows you to insert errors For details refer to Error Control on page 6 13 Loopback This control allows you control and analyze loopback performance For details refer to Loopback on page 6 13 Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 6 Board Test System 6 11 Using the Board Test System The GXB SMA Tab The GXB SMA tab allows you to run transceiver SMA loopback tests on your board You can also load the design and use an oscilloscope to measure an eye diagram of the SMA transmit signals Figure 6 6 shows the GXB SMA tab Figure 6 6 The GXB SMA Tab ARET Test System Of x Configure Help About
5. 5 2 Chapter 6 Board Test System Preparing the Boardi De UE 6 2 Running the Board Test System 6 2 Using the Board Test System 6 3 The Configure Men vss eor ty hove iat ede baked peau EE SIRE PESE CX ge pad eg 6 3 The System Tab ee tone LU aleve ln ae ec ee ets 6 3 board Information br I ue ace tee ne ated eects Kd FECE ASA 6 4 MAX II Registers ixi km Ret EN RO Rad Le 6 4 JT AG Chain vedere Er EN Vague red vade expe Eas vs 6 5 Osys Memory Map eerie aie carseat sudes rd te eU 6 5 The GPIO Tab 54 beue E REM cers EAM REN esa des chen ERE iE Ser l4 6 6 Character LCD ERE GREY abend 6 6 User 5295 0 ETARE 6 6 User LEDS erie wk E eee nd EE 6 7 Push Button Switches 1 0 2 6 7 The Flash Tab 4 5 2k Aa BRIA ae 6 7 te Sein ae ean a eas eee Meenas Meee eed Meas 6 8 Write oae rac RR PE eI rp bU
6. System Info Flash WFPJSFP4 GXBSMA Amphenol Molex GTB MMPx ANU S n AN PLL lock locked Channel lock locked Pattern sync synced Control Port C GXB Transceivers PMA Setting GXB x5 Transceivers Power Monitor type Error control Detected errors 0 57 Inserted errors 0 Insert Error Bit error rate 3 396862e 09 Messages Detected XCVR 2 Project Loopback Ix Rx Stop Tx MBps 7062 6165 Rx MBps 7062 6135 The following sections describe the controls on the GXB SMA tab Status The Status control displays the following status information during the loopback test m PLLlock Shows the PLL locked or unlocked state Channel lock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded m Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 6 12 Chapter 6 Board Test System Using the Board Test System Port m GXB x1 Transceivers Controls the following single transceiver channel GXB_RXLp_11 GXB_TXLp_11 GXB x5 Transceivers Controls controls the following five transceiver channels GXB_RXLp_17 GXB_RXLp_
7. JTAG bus The Si570 programmable oscillator is connected to the MAX II device through a 2 wire serial bus Figure 6 11 shows the Clock Control Figure 6 11 The Clock Control Control loj x RIA 5 v4 vs ve Serial port registers HS DIV 9 Target frequency MHz get Frequency MHz 100 00 MHz RFREQ 02f41a197f Valid Frequency range values are fXTAL 114 2703 MHz 10 00000000 to 810 00000000 MHz Messages USB Blaster on sd hwlab2 USB 0 5M 1270ZF324 22 102 EPM221082 The following sections describe the Clock Control controls Serial Port Registers The Serial port registers control shows the current values from the 51570 registers For more information about the 51570 registers refer to the 51570 51571 datasheet available on the Silicon Labs website www silabs com fXTAL The fXTAL control shows the calculated internal fixed frequency crystal based on the serial port register values T For more information about the fyrar value and how it is calculated refer to the Si570 Si571 datasheet available on the Silicon Labs website www silabs com Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 6 Board Test System 6 23 Configuring the FPGA Using the Quartus Programmer amp Target Frequency The Target frequency control allows you to specify the frequency of the clock The Target frequency control
8. b and so on such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 57 The hand points to information that requires special attention The question mark directs you to a software help system with related information The feet direct you to another document website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide February 2013 Altera Corporation
9. Integrity Development Kit Stratix V GT Edition Installed Directory Structure install dir The default Windows installation directory is C altera lt version gt kits stratixVGT 5sgtea7 si E board_design_files E demos C documents examples C factory_recovery Note to Figure 3 2 1 Early release versions might have slightly different directory names Table 3 1 lists the file directory names and a description of their contents Table 3 1 Installed Directory Contents Directory Name Description of Contents Contains schematic layout assembly and bill of material board design files Use these files as a hoard aasian fes starting point for a new prototype board design demos Contains demonstration applications when available documents Contains the kit documentation February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 3 4 Chapter 3 Software Installation Installing the USB Blaster Driver Table 3 1 Installed Directory Contents Directory Name examples Description of Contents Contains the sample design files for the Transceiver Signal Integrity Development Kit Stratix V GT Edition factory_recovery Contains the original data programmed onto the board before shipment Use this data to restore the board with its original factory contents Installing the USB Blaster Driver The Stratix V G
10. before power cycling the board After you power cycled the board then reconnect the USB Blaster cable To configure the Stratix V GT FPGA perform the following steps 1 Start the Quartus II Programmer 2 Click Auto Detect to display the devices in the JTAG chain 3 Click Add File and select the path to the desired sof 4 Turn on the Program Configure option for the added file 5 Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 100 Using the Quartus II programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board Restart those applications after configuration is complete February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 6 24 Chapter 6 Board Test System Configuring the FPGA Using the Quartus Programmer Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide JA DTE RA A Programming the Flash Memory Device As you develop your own project using the Altera tools you can program the flash memory device so that your own design loads from flash memory into the FPGA on power up This appendix describes the preprogrammed contents of the common flash interface CFI flash memory device on the Stratix V GT development board and the N
11. board La As long as you don t overwrite the factory image in the flash memory device you can continue to use the Board Update Portal to write new designs to the user portion of flash memory If you do overwrite the factory image you can restore it by following the instructions in Restoring the Flash Device to the Factory Settings on page A 4 Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide N 84AN 6 Board Test System This kit includes an application called the Board Test System BTS and related design examples The BTS provides an easy to use interface to alter functional settings and observe the results You can use the BTS to test board components modify functional parameters observe performance and measure power usage While using the BTS you reconfigure the FPGA several times with test designs specific to the functionality you are testing To install the BTS follow the steps in Installing the Development Kit on page 3 3 The BTS communicates over the JTAG bus to a test design running in the Stratix V GT device Figure 6 1 shows the initial GUI for a board that is in the factory configuration Figure 6 1 Board Test System Graphical User Interface 2510 Configure Help About amp Telex AEA eo Flash Board information Board Name Transceiver Signal Integrity Kit Stratix V GX Ed
12. has the following sequence enable options PN apa m ON position 2p5V is enabled 2 m OFF position 2p5V is disabled Switch 2 has the following sequence enable options SW7 2 VCCR GTB position VCCR GTB is enabled ON m OFF position VCCR_GTB is disabled February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide Chapter 4 Development Board Setup Factory Default Switch Jumper Settings Table 4 3 SW7 DIP Switch Settings Switch ned Function Switch 3 has the following sequence enable options d SW7 3 VCCT_GTB ON position VCCT GTB is enabled m OFF position VCCT_GTB is disabled Switch 4 has the following sequence enable options 9W 4 VCCL GTB ON position VCCL_GTB is enabled 05 m OFF position VCCL_GTB is disabled 4 Set DIP switch bank SW4 to match Table 4 4 and Figure 4 1 Table 4 4 SW4 User DIP Switch Settings Switch Ped Function 5 Switch 1 has the following options m Closed 0 FACTORY command won t be issued JTAG will be locked out if FPGA is configured on 1 55 UNLOCK power up from flash Open 1 m Open 1 Unlock the FPGA and allow FACTORY command JTAG will be available even if FPGA is configured on power up from flash 2 8 DPI6 DPIO User defined options 5 Set DIP switch bank SW5 to match Table 4 5 and Figure 4 1 Table 4
13. might time out Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer Preparing the Board With the power to the board off following these steps 1 Connect the USB cable to the board gt If you connect an external USB Blaster download cable and power cycle the board the on board Blaster is disconnected and the 55 UNLOCK function Table 4 4 on page 4 4 does not allow JTAG access to the FPGA To successfully use the USB Blaster cable disconnect it before power cycling the board After you power cycle the board then reconnect the USB Blaster cable 2 Ensure that the development board DIP switches are set to the default positions as shown in the Factory Default Switch Jumper Settings section starting on page 4 2 3 Set the PGMSEL jumper J28 to the user image position jump pins 1 2 a For more information about the board s DIP switch and jumper settings refer to the Transceiver Signal Integrity Development Kit Stratix V GT Edition Reference Manual 4 Turn on the power to the board The board loads the design stored in the user portion of flash memory into the FPGA If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal the design loads the GPIO and flash memory tests To ensure operating stability keep the USB cable connected and the board pow
14. 002 001 0000 0000 0050 00000001 0000000A 00030002 00800000 0000 0060 00FE0000 00000003 00000002 00000000 0000 FFFFFFFF Sm Ades Messages zipfs html web cont 8 192KB 0x0616 0000 0695 FFFF 33 152KB 0 0410 0000 0615 FFFF User hardware 1 33 152KB 0 020 0000 O40F FFFF Factory hardware 33 152KB 0 0002 0000 0209 FFFF FL Option Bits 32kB 0 0001 8000 0001 FFFF Board information 32kB 0 0001 0000 0001 7FFF 32kB Ethernet Option Bits 0 0000 8000 O000 FFFF Detected the Flash GPIO Project The following sections describe the controls on the Flash tab February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 6 8 Chapter 6 Board Test System Using the Board Test System The Read control reads the flash memory on your board To see the flash memory contents type a starting address in the text box and click Read Values starting at the specified address appear in the table The flash memory sits at a base address of 0x0800 0000 To see flash memory contents type the address above the base and values starting at this address are displayed Valid entries are 0x0000 0000 through Ox07FF FFFF 57 If you enter an address outside of 0x0000 0000 to 0x07FF FFFF flash memory address space a warning message identifies the valid flash mem
15. 09 READ TEMPERATURE 1 28 09 MPR_TEMPERATURE_MIM_LTC2 978 25 44 lt Status Summary Status Global Ft L0 STATUS LTC2978 Status Paged Duc LIV 172978 0x011 Status Pads gt DC1613A USB to PMBus controller communicates with the LTC 2978 on board octal PMBus power supply monitor and controller at the U10 11 board reference For more information on the LTC2978 refer to the Transceiver Signal Integrity Development Kit Stratix V GT Edition Reference Manual The LTC2978 power monitor devices installed on this board are programmed with a project file that sets up each voltage rail according to a sequence Each voltage rail adjusts to its voltage level to within a certain tolerance These two voltage rails can be adjusted through switch SW2 Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 6 Board Test System 6 21 The Clock Control Table 6 2 lists the VCCRT_GXB and VCCA_GXB voltage rails and their voltage level depending on the switch position Table 6 2 Voltage Level Setting Switch Position 1 and 2 Schematic Net Name Voltage V VCCRT GXB 1 0 Close Default VCCA_GXB 3 0 VCCRT GXB 0 9 Open VCCA_GXB 2 5 If the board is powered off and powered on again with SW2 in the open position the voltages for VCCRT_GXB and VCCA_GXB voltage ra
16. 0x0001 0000 0x0001 7FFF Ethernet option bits 32 0x0000 8000 0x0000 FFFF User design reset vector 32 0x0000 0000 0x0000 7FFF Altera recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Altera tools If you unintentionally overwrite the factory hardware or factory software image refer to Restoring the Flash Device to the Factory Settings on page 4 February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide A 2 Appendix A Programming the Flash Memory Device Preparing Design Files for Flash Programming Preparing Design Files for Flash Programming You can obtain designs containing prepared flash files from the Transceiver Signal Integrity Development Kit Stratix V GT Edition page of the Altera website or create flash files from your own custom design The Nios II EDS sof2flash command line utility converts your Quartus II compiled Sof into the flash format necessary for the flash device Similarly the Nios II EDS elf2flash command line utility converts your compiled and linked Executable and Linking Format File elf software design to flash After your design files are in the flash format use the Board Update Portal or the Nios II EDS nios2 flash programmer utility to write the flash files to the user software locations of the flash memory For more information about Nios EDS software too
17. 15 GXB_RXLp_14 GXB_RXLp_13 GXB_RXLp_12 GXB_TXLp_17 GXB_TXLp_15 GXB_TXLp_14 GXB_TXLp_13 GXB_TXLp_12 PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes signals between the transmitter and the receiver Enter the following values to enable the serial loopbacks 0 high speed serial transceiver signals to loopback on the board 1 serial loopback 2 reverse serial loopback pre CDR 4 reverse serial loopback post CDR m VOD Specifies the voltage output differential of the transmitter buffer tap m Pre Specifies the amount of pre emphasis on the pre tap of the transmitter buffer m First post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer m Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer Data Type The Data type control specifies the type of data contained in the transactions Select the following available data types for analysis m PRBS7 pseudo random 7 bit sequences default m PRBS15 pseudo random 15 bit sequences m PRBS23 pseudo random 23 bit sequences m PRBS31 pseudo random 31 bit sequences m HFi highest frequen
18. 2 Error Control This control displays data errors detected during analysis and allows you to insert errors For details refer to Error Control on page 6 13 Loopback m This control allows you control and analyze loopback performance For details refer to Loopback on page 6 13 February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 6 18 GTB MMPX Tab Chapter 6 Board Test System Using the Board Test System The GTB MMPX tab allows you to run transceiver loopback tests on each GT channel at high data rates up to 28 Gbps You can also view each GT channel TX output via an oscilloscope for eye diagram analysis and measurements Figure 6 9 shows the GXB MMPX tab Figure 6 9 The GTB MMPX Tab ARET Test System 0 Configure Help About Systeminfa GPIO Flash Amphenol Molex GTB MMPX Power Monitor J Messages etectea XCVR 1 Project PLL lock locked Pattern sync synced Channel lock NOT locked Control Port GTB Transceivers 0 GTB Transceivers 1 GTB Transceivers 2 GTB Transceivers 3 Setting type 57 m Error control Detected errors 0 Inserted errors 0 Insert Error Clear Bit error rate 8 570492e 09 Loopback Tx Rx Stop Tx MBps 3125 0120 Rx MBps 3125 0116
19. 5 SW5 DIP Switch Settings Switch qe Function sein 1 S0 Determines S5GT CLK11 frequency Closed 2 1 Determines S5GT CLK11 frequency Open 3 550 Determines SSGT_CLK11 spectrum spread 0 Open 4 551 Determines S5GT CLK11 spectrum spread Open Note to Table 4 5 1 Truth tables for the SW5 setti 5150 00 25 MHz 01 100 MHz default 10 125 MHz 11 200 MHz SS1SS0Spread 00 center 25 01 down 0 5 10 down 0 75 11 no spread default Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide ngs February 2013 Altera Corporation Chapter 4 Development Board Setup Factory Default Switch Jumper Settings 6 Set DIP switch bank SW6 to match Table 4 6 and Figure 4 1 Table 4 6 SW6 DIP Switch Settings 4 5 Switch Board Label REFCLK_SEL_U32 Function Switch 1 has the following options OSC enables oscillator input m SMA enables SMA input Default Position OSC REFCLK_SEL_U33 Switch 2 has the following options m OSC enables oscillator input m SMA enables SMA input OSC REFCLK_SEL_U34 Switch 3 has the following options OSC enables oscillator input m SMA enables SMA input OSC REFCLK_SEL_U35 Switch 4 has the following options OSC enables oscillator input m SMA enables SMA input OSC 7 Set DIP switch bank S7 to match Table 4 7 and Figure 4 1 Table 4 7 S7 DIP Sw
20. BAAN Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes February 2013 11 Updates for production silicon release February 2012 1 0 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 1 Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bold Type with Inita Capital labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gd
21. D to the Factory Settings A 5 Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Contents Additional Information Document Revision History sse ke rt e tee ae edie e ERR e CN KR es doe Info 1 How to Contact Altera Info 1 Typographic Conventions cover ent UC aet es Info 1 February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide vi Contents Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide N DTE RYN 1 About This Kit The Altera Stratix V GT Transceiver Signal Integrity Development Kit is a complete design environment that includes both the hardware and software you need to develop Stratix V GT FPGA designs The one year license for the Quartus II software provides everything you need to begin developing custom Stratix V GT FPGA designs The following list describes what you can accomplish with the kit Kit Features Evaluate transceiver performance from 600 Mbps up to 12 5 Mbps Evaluate transceiver performance up to 28 Gbps for the GT channels Generate and check pseudo random binary sequence PRBS patterns Dynamically change differential outp
22. GT device is always the first device in the chain When set to 0 switch 57 6 MAX BYPASS includes the MAX II device in the chain when set to 1 the MAX II device is removed from the JTAG chain Qsys Memory Map The Osys memory map control shows the memory map of the Osys system on your board February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 6 6 Chapter 6 Board Test System Using the Board Test System The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I O components on your board You can write to the character LCD read DIP switch settings turn LEDs on or off and detect push button presses Figure 6 3 shows the GPIO tab Figure 6 3 The GPIO Tab Toara rest system NR ib Configure Help About PER SER EnA en d marec TEA System Info GPIO Flash r Character LCD Enter text stratis fsx Kit r User DIP switch 1 1 OFF AS glee 0 ON B B B B 2 E User LEDs Messages Detected the Flash GPIO Project The following sections describe the controls on the GPIO tab Character LCD The Character LCD controls allows you to display text strings on the character LCD on your board Type text in the text boxes and then click Display gt Ifyou exceed the 16 character display limit on either line a warning message appears Use
23. Il Software Your kit includes a license for the Development Kit Edition DKE of the Quartus II software Windows platform only For one year this license entitles you to most of the features of the Subscription Edition excluding the IP Base Suite gt 7 After the year your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus II software To continue using the Quartus II software you should download the free Quartus II Web edition or purchase a subscription to Quartus II software For more information refer to the Design Software page of the Altera website The Quartus II Development Kit Edition DKE software includes the following items m Quartus IL Software The Quartus II software including the Qsys system integration tool provides a comprehensive environment for network on a chip NoC design The Quartus II software integrates into nearly any design environment and provides interfaces to industry standard EDA tools m MegaCore IP Library A library that contains Altera IP MegaCore functions You can evaluate MegaCore functions by using the OpenCore Plus feature to do the following m Simulate behavior of a MegaCore function within your system m Verify functionality of your design and quickly and easily evaluate its size and speed m Generate time limited device programming files for designs that include MegaCore functions m Program a device and verify your design in
24. Integrity Development Kit Stratix V GT Edition User Guide 6 14 The Amphenol Tab Chapter 6 Board Test System Using the Board Test System The Amphenol tab allows you to run a x4 backplane loopback test through the Amphenol connector Figure 6 7 shows the Amphenol tab Figure 6 7 The Amphenol Tab ARET Test System Configure Help About x Power Monitor Messages Detected XCVR 1 Project System Info EPI SERA GAG SI GPIO Fash Amphenol Molex Status PLL lock locked Pattern sync synced Channel lock locked Control Port aggressor 1 aggressor 2 aggressor 3 Amphenol x4 Transceivers Setting aggressor 4 aggressor 5 aggressor 6 type 57 m Error control Detected errors 0 Inserted errors 0 Insert Error Bit error rate 1 666412 06 Loopback Tx Rx 1289 0806 1289 0806 Tx MBps Rx MBps Amphenol No external loopback is provided A loopback backplane can be purchased from The following sections describe the controls on the Amphenol tab Status m The Status control displays status information during the loopback test For details on this control refer to Status on page 6 11 Port The Port control allows you to specify the type of test to run on the Amphen
25. T development board includes integrated USB Blaster circuitry for FPGA programming However for the host computer and board to communicate you must install the USB Blaster driver on the host computer Installation instructions for the USB Blaster driver for your operating system are available on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide N DTE RYN 4 Development Board Setup The instructions in this chapter explain how to set up the Stratix V GT development board Setting Up the Board To prepare and apply power to the board perform the following steps 1 The Stratix V GT development board ships with its board switches preconfigured to support the design examples in the kit If you suspect your board might not be currently configured with the default settings follow the instructions in Factory Default Switch Jumper Settings on page 4 2 to return the board to its factory settings before proceeding 2 The development board ships with design examples stored in the flash memory device Verify the PGMSEL jumper J28 is set to the jump pins 2 3 position to load the design stored in the factory portion of flash memory Figure 4 1 shows the switch location on the Strat
26. Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide RYAN 101 Innovation Drive San Jose CA 95134 www altera com UG 01114 1 1 NA Feedback Subscribe 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks eb Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide N DTE RYN Contents Chapter 1 About This Kit Kit Features 1 sere ee ee REPE eh ai eee dh
27. atix V GT Edition page of the Altera website to determine if you have the latest kit software Using the Board Update Portal to Update User Designs The Board Update Portal allows you to write new designs to the user portion of flash memory Designs must be in the Nios Flash Programmer File flash format K Design files available from the Transceiver Signal Integrity Development Kit Stratix V GT Edition page include flash files You can also create flash files from your own custom design Refer to Preparing Design Files for Flash Programming on page 2 for information about preparing your own design for upload To upload a design over the network into the user portion of flash memory on your board perform the following steps 1 Perform the steps in Connecting to the Board Update Portal Web Page to access the Board Update Portal web page In the Hardware File Name field specify the flash file that you either downloaded from the Altera website or created on your own If there is a software component to the design specify it in the same manner using the Software File Name field otherwise leave the Software File Name field blank Click Upload The progress bar indicates the percent complete The file takes about 20 seconds to upload To configure the FPGA with the new design after the flash memory upload process is complete set the PGMSEL jumper J28 to the user position jump pins 1 2 and power cycle the
28. ce documentation refer to the Literature Stratix V Devices page To purchase devices from the eStore refer to the Devices page February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 2 2 Chapter 2 Getting Started References m For Stratix V GT OrCAD symbols refer to the Capture CIS Symbols page m For Nios II 32 bit embedded processor solutions refer to the Embedded Processing page Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide N D 2Ya 3 Software Installation This chapter explains how to install the following software m Quartus II Subscription Edition Software m Transceiver Signal Integrity Development Kit Stratix V GT Edition m USB Blaster driver Installing the Quartus Il Subscription Edition Software The Quartus II Subscription Edition Software provides the necessary tools used for developing hardware and software for Altera devices Included in the Quartus II Subscription Edition Software are the Quartus II software the Nios II EDS and the MegaCore IP Library The Quartus II software including Osys and the Nios II EDS are the primary FPGA development tools used to create the reference designs in this kit To install the Altera development tools perform the following steps 1 Download the Quartus II Subscription Edition Software from the Quartus II Subscription Edition Software
29. cy divide by 2 data pattern 10101010 m HF2 next highest frequency divide by 6 data pattern 111000111000 m HF3 second lowest frequency divide by 22 data pattern m LF lowest frequency divide by 33 data pattern Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 6 Board Test System 6 13 Using the Board Test System Le Settings HF1 HF2 HF3 LF are for transmit observation only and are not used in the receiver data detection circuitry Error Control This control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the received bit stream m Inserted errors Displays the number of errors inserted into the transmit data stream Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Loopback m TX and RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m Start This control initiates the loopback tests m Stop tThis control terminates the loopback tests m Tx MBps and Rx MBps Show the number of bytes of data analyzed per second February 2013 Altera Corporation Transceiver Signal
30. de eee ee i da e 1 1 Hardwate ec ARR Re aces a ceded eve babes bene 1 1 SOW are 2 beak avy das Dee See see bee ee Vio ete ES oe Werbe hs 1 2 Quartus II Software senori serti Ree bee E NEAR d ER 1 2 Transceiver Signal Integrity Development Kit Stratix V GT Edition Installer 1 2 Chapter 2 Getting Started MOU BEGIN Rebeca 2 1 Inspect the Board 5 2 5 wns ete eee e Pete S boe d ER EA Pee rie 2 1 2 M 2 1 Chapter 3 Software Installation Installing the Quartus II Subscription Edition Software 3 1 Licensing Considerations eee hen exer heh he e Ehre ee ek 3 1 Installing the Development Kit 3 3 Installing the USB Blaster Driver 3 4 Chapter 4 Development Board Setup Settine Up the Board inte oe er use peu E Lote ML 4 1 Factory Default Switch Jumper Settings 4 2 Chapter 5 Board Update Portal Connecting to the Board Update Portal Web Page 5 1 Using the Board Update Portal to Update User Designs
31. e Physical Address line 4 When licensing is complete Altera emails a license dat file to you Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus software to enable the software Te For complete licensing details refer to the Altera Software Installation and Licensing Manual Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 3 Software Installation 3 3 Installing the Development Kit Installing the Development Kit To install the Transceiver Signal Integrity Development Kit Stratix V GT Edition perform the following steps 1 Download the Transceiver Signal Integrity Development Kit Stratix V GT Edition installer from the Transceiver Signal Integrity Development Kit Stratix V GT Edition page of the Altera website Alternatively you can request a development kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website 2 Run the Transceiver Signal Integrity Development Kit Stratix V GT Edition installer 3 Follow the on screen instructions to complete the installation process Be sure that the installation directory you choose is in the same relative location to the Quartus II software installation The installation program creates the Transceiver Signal Integrity Development Kit Stratix V GT Edition directory structure shown in Figure 3 2 Figure 3 2 Transceiver Signal
32. ed bert eost pite Y a Reva vede die ete 6 19 AS DREADS De EE EEA TREES 6 19 Loopback me del gr 6 19 l ower Monitoring tbe b Ee e EU die ie BEES 6 20 The Clock Control eae ete SEEN P pepe EE A gau x A RE 6 21 Serial Port Registers ec e be e e RETE EEEE ede C EP ER PIG 6 22 tds ee bx bed das v a east aba ke ge apo se A ces odes 6 22 Target RrequenGy P LP 6 23 Cleat eieren hU es eats Ga oes 6 23 Set New Frequency 75s oce p E edet AS 6 23 Configuring the FPGA Using the Quartus 6 23 Appendix A Programming the Flash Memory Device CEI Flash Memory Map ee ien Cede bte eod ets A 1 Preparing Design Files for Flash Programming A 2 Creating Flash Files Using the Nios EDS A 2 Programming Flash Memory Using the Board Update A 2 Programming Flash Memory Using the Nios A 3 Restoring the Flash Device to the Factory Settings A 4 Restoring the MAX II CPL
33. eee aed oe E db ea C ea ace eles 6 8 Random Test ueber he te rh eA ad p rU desi 6 8 CRI Quety EX e E aes Fere d rex ies 6 8 Increment Test ee See Be Re eS RUPEE RP EE Nu Reece ES 6 8 Rp 6 8 February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide Contents BEraSeus exse odes Shae Toe Eds 6 8 Flash Memoty Map i ic gae hac dees dinida e E ees 6 8 The XEP SEP4T b 4 ete RV PR ESR ae bk Serb er PCR PASE 6 9 Status sews DUCERE RD Rp CERE 6 10 POPE 6 10 PMA chinese neds ieee ew ead ds ae ee ewe eS 6 10 Data eine V eed 6 10 Error Control i35 ce gd LADD OGD TAR Se RS 6 10 Loopback 6 10 The GXB SMA Tab dk NSE ASAD Rada 6 11 Status iow ek we teh 6 11 POPE 6 12 PMA Setting REDE DE Ry go rn ee bx d e beue ped 6 12
34. er Guide Chapter 6 Board Test System 6 9 Using the Board Test System The XFP SFP Tab The XFP SFP tab allows you to run an XFP or SFP optical loopback test You can also run the test using an electrical loopback test if you do not have an SFP or XFP module with optical loopback fibre available 57 To test the board using an optical module from the BTS if the optical module requires a divide by 64 REFCLK perform the following steps before powering on the board 1 Set SW6 1 8 1 to SMA and SW6 2 7 2 to OSC 2 Connect differential clock cables from SMAs J72 73 to J79 J80 Figure 6 5 shows the XFP SFP tab Figure 6 5 The XFP SFP Tab ARET Test System Configure Help About System into GPIO Flash 5 GXB SMA Molex GTB TMPX PLL lock locked Channel lock NOT locked Pattern sync synced Control r Port SFP PMA Setting C Power Monitor type Error control Detected errors 0 Inserted errors 0 Insert Error Clear Bit error rate 3 569788e 08 Messages Detected XCVR 2 Loopback TX Rx Start Tx MBps 1412 5225 Rx MBps 1412 5225 Project The following sections describe the controls on the XFP SFP tab February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide
35. ered on when running the demonstration application The application cannot run correctly unless the USB cable is attached and the board is on CAUTION Running the Board Test System To run the application navigate to the install dir gt kits stratixV GT 5sgtea7 siNexamplesNboard test system directory and run the BoardTestSystem exe application Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 6 Board Test System 6 3 Using the Board Test System 57 In Windows click Start gt All Programs gt Altera gt Transceiver Signal Integrity Development Kit Stratix V GT Edition lt version gt gt Board Test System to run the application A GUI appears displaying the application tab that corresponds to the design running in the FPGA The development board s flash memory ships preconfigured with the design that corresponds to the GPIO and Flash tabs 57 If you power up your board with the PGMSEL jumper J28 in the factory position jump pins 2 3 or if you load your own design into the FPGA with the Quartus II Programmer you receive a message prompting you to configure your board with a valid Board Test System design Refer to The Configure Menu for information about configuring your board Using the Board Test System This section describes each control in the Board Test System application The Configure Menu Use the Configure menu Figure 6 2 to
36. f file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets lt gt For example file name and lt project name pof file February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide Info 2 Additional Information Typographic Conventions Visual Cue Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a
37. formation control displays static information about your board Board Name Indicates the official name of the board given by the Board Test System Board P N Indicates the part number of the board Serial number Indicates the serial number of the board Factory test version Indicates the version of the Board Test System currently running on the board MAX II ver Indicates the version of MAX II code currently running on the board The MAX II code resides in the install dir NkitsNstratixVGT 5sgtea7 siNexamples directory Newer revisions of this code might be available on the Transceiver Signal Integrity Development Kit Stratix V GT Edition page of the Altera website MAC Indicates the MAC address of the board MAX II Registers The MAX II registers control allow you to view and change the current MAX II register values as described in Table 6 1 Changes to the register values with the GUI take effect immediately Table 6 1 MAX II Registers System Reset SRST Read Write Register Name Capability Description Write only Set to 0 to initiate an FPGA reconfiguration Page Select Override PS0 1 the value in PSS determines the page of flash memory to Page Select Switch PSS When set to 0 the value in PSR determines the page of Read Write flash memory to use for FPGA reconfiguration When set to use for FPGA reconfiguration Holds the current value of jumper J28 PGMSEL Read only 1 user i
38. hardware gt The OpenCore Plus hardware evaluation feature is an evaluation tool for prototyping only You must purchase a license to use a MegaCore function in production St For more information about OpenCore Plus refer to AN 320 OpenCore Plus Evaluation of Megafunctions Nios Embedded Design Suite EDS A full featured set of tools that allows you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs Transceiver Signal Integrity Development Kit Stratix V GT Edition Installer The license free Transceiver Signal Integrity Development Kit Stratix V GT Edition installer includes all the documentation and design examples for the kit Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 1 About This Kit 1 3 Kit Features 57 For information on installing the Development Kit Installer refer to Installing the Development Kit on page 3 3 February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 1 4 Chapter 1 About This Kit Kit Features Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide N DTE BAN 2 Getting Started The remaining chapters in this user guide lead you through the following board setup steps Inspecting the contents of the kit Installing the design a
39. ils read 0 90 V and 2 5 V respectively and will not come up to the proper levels This is due to the LTC2978 device trying to adjust these rails to their programed values which it cannot due to the switch position of SW2 The work around to this issue is to set switch SW2 in the close position at power up The Clock Control The Clock Control application allows you to set the four 51570 programmable oscillators to any frequency between 10 MHz and 945 MHz and select frequencies to 1400 MHz The oscillator drives a 2 to 6 buffer that drives a copy of the clock to all four edges of the FPGA The Clock Control application runs as a stand alone application ClockControl exe resides in the lt install dir gt kits stratixVGT_5sgtea7_si examples board_test_system directory On Windows click Start gt All Programs gt Altera gt Transceiver Signal Integrity Development Kit Stratix V GT Edition lt version gt gt Clock Control to start the application For more information about the Si570 and the Stratix V GT development board s clocking circuitry and clock input pins refer to the Transceiver Signal Integrity Development Kit Stratix V GT Edition Reference Manual February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 6 22 Chapter 6 Board Test System The Clock Control The Clock Control communicates with the MAX II device on the board through the
40. ios II EDS tools involved with reprogramming the user portions of the flash memory device The Stratix V GT development board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Board Update Portal design example and a default user configuration for running the Board Test System demonstration There are several other factory software files written to the CFI flash device to support the Board Update Portal These software files were created using the Nios II EDS just as the hardware design was created using the Quartus II software For more information about Altera development tools refer to the Design Software page of the Altera website CFI Flash Memory Map Table A 1 shows the default memory contents of the 1 Gb CFI flash device For the Board Update Portal to run correctly and update designs in the user memory this memory map must not be altered CAUTION Table A 1 Byte Address Flash Memory Map Block Description Size KB Address Range Unused 128 0x07FE 0000 0x07FF FFFF User software 24 320 0x0716 0000 0x07FD FFFF Factory software 8 192 0x0696 0000 0x0715 FFFF zipfs html web content 8 192 0x0616 0000 0x0695 FFFF User hardware 2 Unused 33 152 0x0410 0000 0x0615 FFFF User hardware 1 33 152 0x020A 0000 0x040F FFFF Factory hardware 33 152 0x0002 0000 0x0209 FFFF PFL option bits 32 0x0001 8000 0x0001 FFFF Board information 32
41. itch Settings Switch Board Label MSELO Function Switch 1 has the following m Closed Logic 0 m Open Logic 1 Default Position Closed MSEL1 Switch 2 has the following m Closed Logic 0 m Open Logic 1 Closed MSEL2 Switch 3 has the following m Closed Logic 0 m Open Logic 1 Open MSEL3 Switch 4 has the following m Closed Logic 0 m Open Logic 1 Closed MSEL4 Switch 5 has the following m Closed Logic 0 m Open Logic 1 Open February 2013 Altera Corporation MAX BYPASS Switch 6 has the following m Closed Logic 0 Includes the MAX II device in the JTAG chain m Open Logic 1 Removes the MAX II device in the JTAG chain Closed Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 4 6 Chapter 4 Development Board Setup Factory Default Switch Jumper Settings 8 Set jumper blocks J26 J28 to match Table 4 8 and Figure 4 1 Table 4 8 Jumper Settings Board Reference Description Shunt Position J26 Fan select Pins 1 2 select auto operation Installed J26 Fan select Pins 2 3 select fan on Not installed J28 PGMSEL logic 1 Pins 1 2 select user defined image Not Installed J28 PGMSEL logic 0 Pins 2 3 select factory image Installed 57 For more information about the FPGA board settings refer to the Transceiver Signal Integrity Development Kit Stra
42. ition Board P N 6X 43846R Serial number 5SGXSIO00001 Factory test version Test Software Version 1 MAX II ver 1 00 07 ED 1C 01 00 MAX II registers SRST JTAG chain 5SGTMC7K 2 3 81 5M 127012F3241221n71 I EPM E gt Qsys memory me cfi flash 0 0800 0000 OFFF FFFF d u 0000 006F FFFF onchip_memory 0 0000 1000 0000 1FFF scin 100000 0800 0000 0BFF led ot 0 0000 0040 0000 004F dps 0 x0000 0030 0000 003F 0x0000 0020 0000 002 Messages Detected the Flash GPIO Project Several designs are provided to test the major board features Each design provides data for one or more tabs in the application The Configure menu identifies the appropriate design to download to the FPGA for each tab February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 6 2 Chapter 6 Board Test System Preparing the Board After successful FPGA configuration the appropriate tab appears that allows you to exercise the related board features Highlights appear in the board picture around the corresponding components gt The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap II Embedded Logic Analyzer Because the Quartus II programmer uses most of the bandwidth of the JTAG bus other applications using the JTAG bus
43. ition User Guide 3 2 Chapter 3 Software Installation Installing the Quartus Il Subscription Edition Software 57 Your serial number is printed on the development kit box below the bottom bar code The number is 10 or 11 alphanumeric characters and does not contain hyphens Figure 3 1 shows 35150SPXXXX as an example serial number Figure 3 1 Locating Your Serial Number DK DSP 3SL150 YY LOT XXXXX 3S150SPXXXX 2 Consult the Activate Products table to determine how to proceed a Ifthe administrator listed for your product is someone other than you skip the remaining steps and contact your administrator to become a licensed user b Ifthe administrator listed for your product is you proceed to step 3 c Ifthe administrator listed for your product is Stocking activate the product making you the administrator and proceed to step 3 3 Use the Create New License page to license your product for a specific user you on specific computers The Manage Computers and Manage Users pages allow you to add users and computers not already present in the licensing system gt To license the Quartus II software you need your computer s network interface card NIC ID a number that uniquely identifies your computer On the computer you use to run the Quartus II software type ipconfig 11 command prompt to determine the NIC ID Your NIC ID is the 12 digit hexadecimal number on th
44. ix V GT development board Connect the 120 W 20 VDC 6 32 A power supply model LTE120E SW 3XX to the DC Power Jack J1 on the FPGA board and plug the cord into a power outlet A Use only the supplied power supply Power regulation circuitry on the board can be damaged by power supplies with greater voltage 3 Set the POWER switch SW1 to the on position When power is supplied to the board the blue LED D3 illuminates indicating that the board has power The MAX II device on the board contains among other things a parallel flash loader PFL megafunction When the board powers up the PFL reads a design from flash memory and configures the FPGA The PGMSEL jumper J28 controls which design to load When pins are in the 2 3 position the PFL loads the design from the factory portion of flash memory When pins are in the 1 2 position the PFL loads the design from the user portion of flash memory gt The kit includes a MAX II design which contains the MAX II PFL megafunction The design resides in the install dir gt kits stratixV GT_5sgtea7_si examples max2 directory When configuration is complete one of two LEDs illuminate D10 for FACTORY_IMAGE or D11 for USER_IMAGE signaling that the Stratix V GT device configured successfully If either configuration fails the red CONFIG_ERR LED D9 illuminates a For more information about the PFL megafunction refer to the Parallel Flash Loader Megafunction User Guide Februa
45. le of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 23 for more information 5 Click Add File and select install dir NkitsNstratixVGT 5sgtea7 siNfactory recovery Ns5gtea7 si bup sof 6 Turn on the Program Configure option for the added file 7 Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The FACTORY IMAGE LED D10 illuminates indicating that the flash device is ready for programming 8 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios Command Shell 9 In the Nios II command shell navigate to the install dir NkitsNstratixVGT 5sgtea7 siMfactory recovery directory or to the directory of the flash files you created in Creating Flash Files Using the Nios II EDS on page 2 and type the following Nios II EDS command nios2 flash programmer base 0x0 lt yourfile gt hw flash 10 After programming completes if you have a software file to program type the following Nios II EDS command nios2 flash programmer base 0x0 yourfile sw flash 11 Set the PGMSEL jumper J28 to the user position jump pins 1 2 and power cycle the board Programming the board is now complete St For more information about the nios2 flash programmer utility refer to the Nios II Flash Programmer User Guide February 2013 Altera Corporation Transceiver Signal In
46. ls and practices refer to the Embedded Software Development page of the Altera website Creating Flash Files Using the Nios EDS If you have an FPGA design developed using the Quartus II software and software developed using the Nios II EDS follow these instructions 1 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell 2 In the Nios command shell navigate to the directory where your design files reside and type the following Nios II EDS commands m For Quartus II sof files sof2flash input lt yourfile gt hw sof output lt yourfile gt hw flash offset 0x020A0000 pfl optionbit 0x00018000 programmingmode PS m For Nios II elf files elf2flash base 0x0 end 0x07FFFFFF reset 0x07160000 input yourfile sw elf output yourfile sw flash boot SOPC KIT NIOS2 components altera nios2 boot loader cfi srece The resulting flash files are ready for flash device programming If your design uses additional files such as image data or files used by the runtime program you must first convert the files to flash format and concatenate them into one flash file before using the Board Update Portal to upload them The Board Update Portal standard flash format conventionally uses either filename hw flash for hardware design files or filename sw flash for software design files Programming Flash Memory Using the Board Update Portal O
47. mage 2 factory image Page Select Register PSR Determines which of the up to eight 0 7 pages of flash Read Write memory to use for FPGA reconfiguration The flash memory ships with pages 0 and 1 preconfigured SRST Resets the system and reloads the FPGA with a design from flash memory based on the other MAX II register values Refer to Table 6 1 for more information PSO Sets the MAX II PSO register The following options are available m Use PSR Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration m Use PSS Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 6 Board Test System 6 5 Using the Board Test System m PSR Sets the MAX II PSR register The numerical values in the list corresponds to the page of flash memory to load during FPGA reconfiguration Refer to Table 6 1 for more information m PSS Displays the MAX II PSS register value Refer to Table 6 1 for the list of available options 57 Because the System Info tab requires that a specific design is running in the FPGA at a specific clock speed writing a 0 to SRST or changing the PSO value can cause the Board Test System to stop running JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain The Stratix V
48. nce you have the necessary flash files you can use the Board Update Portal to reprogram the flash memory Refer to Using the Board Update Portal to Update User Designs on page 5 2 for more information Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Appendix A Programming the Flash Memory Device A 3 Programming Flash Memory Using the Nios Il EDS If you have generated a sof that operates without a software design file you can still use the Board Update Portal to upload your design In this case leave the Software File Name field blank Programming Flash Memory Using the Nios EDS The Nios II EDS offers a nios2 flash programmer utility to program the flash memory directly To program the flash files or any compatible S Record File srec to the board using nios2 flash programmer perform the following steps 1 Set the PGMSEL jumper J28 to the factory position jump pins 2 3 to load the Board Update Portal design from flash memory on power up 2 Attach the USB Blaster cable and power up the board 3 Ifthe board has powered up and the LCD displays either Connecting or a valid IP address such as 152 198 231 75 proceed to step 8 If no output appears on the LCD or if the D10 for FACTORY IMAGE LED does not illuminate continue to step 4 to load the FPGA with a flash writing design 4 Launch the Quartus II Programmer to configure the FPGA with a sof capab
49. nd kit software Setting up powering up and verifying correct operation of the development board Configuring the Stratix V GT FPGA Running the Board Test System designs For complete information about the development board refer to the Transceiver Signal Integrity Development Kit Stratix V GT Edition Reference Manual Before You Begin Before using the kit or installing the software check the kit contents and inspect the board to verify that you received all of the items listed in Kit Features on page 1 1 If any of the items are missing contact Altera before you proceed Inspect the Board To inspect the board perform the following steps 1 Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment A Without proper anti static handling you can damage the board CAUTION Verify that all components are on the board and appear intact For proper Stratix V GT device cooling install the heatsink fan included with the kit using the provided heatsink fan installation tool For more information about power consumption and thermal modeling refer to AN 358 Thermal Management for FPGAs References Use the following links to check the Altera website for other related information For the latest board design files and reference designs refer to the Transceiver Signal Integrity Development Kit Stratix V GT Edition page For the Stratix V GT devi
50. ol port The following Amphenol port test is available m Amphenol x4 Transceivers Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide February 2013 Altera Corporation Chapter 6 Board Test System 6 15 Using the Board Test System PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface For details refer to PMA Setting on page 6 12 Data Type The Data type control specifies the type of data contained in the transactions For details refer to Data Type on page 6 12 Error Control This control displays data errors detected during analysis and allows you to insert errors For details refer to Error Control on page 6 13 Loopback m This control allows you control and analyze loopback performance For details refer to Loopback on page 6 13 February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 6 16 Chapter 6 Board Test System Using the Board Test System The Molex Tab The Molex tab allows you to run a x4 backplane loopback test through the Molex connector Figure 6 8 shows the Molex tab Figure 6 8 The Molex Tab 2519 Configure Help About System Info GPIO last i ERA 5 GKE SMG Amphenol Molex GTB MMPX e r Status PLL lock locked Channel lock locked Pattern sync synced
51. ortal Web Page This section provides instructions to connect to the Board Update Portal web page Before you proceed ensure that you have the following m APC with a connection to a working Ethernet port on a DHCP enabled network separate working Ethernet port connected to the same network for the board m The Ethernet and power cables that are included in the kit To connect to the Board Update Portal web page perform these steps 1 With the board powered down set the PGMSEL jumper J28 to the factory position jump pins 2 3 2 Attach the Ethernet cable from the board J29 to your LAN 3 Power up the board The board connects to the LAN s gateway router and obtains an IP address The LCD on the board displays the IP address 4 Launch a web browser on a PC that is connected to the same network and enter the IP address from the LCD into the browser address bar The Board Update Portal web page appears in the browser 57 You click Transceiver Signal Integrity Development Kit Stratix V GT Edition on the Board Update Portal web page to access the kit s home page for documentation updates and additional new designs February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 5 2 Chapter 5 Board Update Portal Using the Board Update Portal to Update User Designs Te You can also navigate directly to the Transceiver Signal Integrity Development Kit Str
52. ory address range Write The Write control writes the flash memory on your board To update the flash memory contents change values in the table and click Write The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents gt To prevent overwriting the dedicated portions of flash memory the application limits the writable flash memory address range to 0 08 0000 to Ox08FE FFFF which corresponds to address range 0x0000 0000 0x003FE FFF in the uppermost portion of the user software memory block as shown in Figure 6 1 on page 6 1 and Table A 1 on page A 1 Random Test Starts a random data pattern test to flash memory which is limited to a scratch page in the upper 128 K block CFI Query The CFI Query control updates the memory table displaying the CFI ROM table contents from the flash device Increment Test Starts an incrementing data pattern test to flash memory which is limited to a scratch page in the upper 128 K block Reset The Reset control executes the flash device s reset command and updates the memory table displayed on the Flash tab Erase Erases flash memory which is limited to a scratch page in the upper 128 K block Flash Memory Map Displays the flash memory map for the development board Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition Us
53. page of the Altera website Alternatively you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera website 2 Follow the on screen instructions to complete the installation process If you have difficulty installing the Quartus II software refer to the Altera Software Installation and Licensing Manual Licensing Considerations Purchasing this kit entitles you to a one year license for the Development Kit Edition DKE of the Quartus II software After the year your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus II software To continue using the Quartus II software you should download the free Quartus II Web edition or purchase a subscription to Quartus II software Before using the Quartus II software you must activate your license identify specific users and computers and obtain and install a license file If you already have a licensed version of the subscription edition you can use that license file with this kit If not you need to obtain and install a license file To begin go to the Self Service Licensing Center page of the Altera website log into or create your myAltera account and take the following actions 1 On the Activate Products page enter the serial number provided with your development kit in the License Activation Code box February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Ed
54. r DIP Switches The read only User DIP switches control displays the current positions of the switches in the user DIP switch bank SW4 Change the switches on the board to see the graphical display change accordingly Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 6 Board Test System 6 7 Using the Board Test System User LEDs The User LEDs control displays the current state of the user LEDs Toggle the LED buttons to turn the board LEDs on and off Push Button Switches The read only Push button switches control displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly The Flash Tab The Flash tab allows you to read and write flash memory on your board Figure 6 4 shows the Flash tab Figure 6 4 The Flash Tab ARET Test System Inl xl Configure Help About ene mphen mated TB TP NB SYN System Info Flash 2 Flash Start address Range 0 0000 0000 OxO7FF FFFF Pane Monito 00 oooo Read Write Random test Increment test Reset Erase adress 0 3 17 lt lt 0000 0000 89630089 0001 F94F0089 0004 0000 0010 FF4FFF4F FF4FFF4F FFAFFFAF FF4FFF4F 0000 0020 00520051 00010059 00040000 00000001 0000 0030 00000000 100170000 00850020 00080095 0000 0040 000 000 00010000 00020
55. ry 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 4 2 Chapter 4 Development Board Setup Factory Default Switch Jumper Settings Factory Default Switch Jumper Settings This section shows the factory switch settings for the Stratix V GT development board Figure 4 1 shows the switch locations and the default position of each switch on the top side of the board Figure 4 1 Switch Locations and Default Settings on the Board Top AUTO ON osc S7 SW4 User defined emm RUN D SMA a x 5 gt MAX BYPASSI SW3 1 VCC SW3 2 VCCRT_GXB SW3 3 VCCA_GXB SW3 4 1p5V SW7 1 2p5V SW7 2 VCCR_GTB SW3 SW7 SW74 VOOL_GTB ENABLE DISABLE Stratix V GT 51 S0 CLK SW5 o ON 0 1 100MHz 1 0 125MHz 1 1 200MHz 111234 50 51 550 551 SW2 1 open 0 9 SW2 1 close 1 0 SW2 2 open 2 5V SW2 2 close 3 0V close SW2 3 No Function ON SW2 4 No Function Sw2 1234 28 PGMSEL C WIR jupio uh JMP2 3 LOW To restore the switches to their factory default settings perform the following steps 1 Set the DIP switch bank SW2 to match Table 4 1 and Figure 4 1 Table 4 1 SW2 DIP Switch Settings Part 1 of 2 Default Position Board Lahel Function Switch Switch 1 has the following options 1 SW2 1 m Open VCCRT GXB select a
56. select the design you want to use Each design example tests different functionality that corresponds to one or more application tabs Figure 6 2 The Configure Menu Configure Help About Configure with Flash GPIO Design Configure with XCVR1 Design Configure with XCVR2 Design Exit Ctrl Q To configure the FPGA with a test system design perform the following steps 1 On the Configure menu click the configure command that corresponds to the functionality you wish to test 2 In the dialog box that appears click Configure to download the corresponding design s Raw Binary File rbf to the FPGA The download process usually takes less than a minute 3 When configuration finishes close the Quartus II Programmer if open The design begins running in the FPGA The corresponding GUI application tabs that interface with the design are now enabled The System Info Tab The System Info tab shows information about the board s current configuration Figure 6 1 on page 6 1 shows the System Info tab The tab displays the contents of the MAX II registers the JTAG chain the board s MAC address the flash memory map and other details stored on the board The following sections describe the controls on the System Info tab February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide Chapter 6 Board Test System Using the Board Test System Board Information The Board in
57. t 0 9 V Close m Close ON VCCRT GXB select at 1 0 V Switch 2 has the following options 2 SW2 2 m Open VCCA GXB select at 2 5 V Close m Close ON VCCA GXB select at 3 0 V Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Chapter 4 Development Board Setup Factory Default Switch Jumper Settings Table 4 1 SW2 DIP Switch Settings Part 2 of 2 4 3 Switch des Function Pm Switch 3 has the following options 3 SW2 3 m Open No function Open m Close ON No function Switch 4 has the following options 4 SW2 4 m Open No function Open m Close ON No function 2 Set DIP switch bank SW3 to match Table 4 2 and Figure 4 1 Table 4 2 SW3 Dip Switch Settings Switch Ped Function Switch 1 has the following options 1 SW3 1 VCC m ON S5GT_VCC is enabled ON m OFF S5GT_VCC is disabled Switch 2 has the following options 2 SW3 2 VCCRT GXB m ON VCCRT_GXB is enabled ON m OFF VCCRT_GXB is disabled Switch 3 has the following options 3 SW3 3 VCCA GXB ON position VCCA_GXB is enabled OFF m OFF position VCCA GXB is disabled Switch 4 has the following options 4 SW3 4 1p5V m ON position 1p5V is enabled ON m OFF position 1p5V is disabled 3 Set DIP switch bank SW7 to match Table 4 3 and Figure 4 1 Table 4 3 SW7 DIP Switch Settings Switch ria Function Switch 1
58. tall the free LTpowerPlay software and then connect your PC and the development board to a Linear Technology DC1613A USB to PMBus Controller Both the software and the controller interface are available from the Linear Technology www linear com website Figure 6 10 shows the LTpowerPlay GUI This application works in conjunction with two LTC2978 Power Monitor Controller devices located at U10 and U11 on the board These two devices are pre programmed at the factory to monitor and control specific voltage rails of this board The application can be used to monitor trim and sequence the specific voltage rails if necessary The operator does not need this application otherwise Figure 6 10 LTpowerPlay Contig VCORT_GXB 1 1V EG DT eee ey mc RS Lookup sa tn Ab paged Addressing WP General Contig Vokage Temperature Ting WatchdogFPGOCO Faut Responses Faut Sharing St i ration Kegisters 1978 Expand for Detail ro and Margining amp ONOFF CONF IG OPERATION ow 0xA4 Margtmnt ghignoreraules O Coxas Marg mmigh Output voltage VOUT MAX VOUT DV FAULT LIMIT VOUT DV WIEN A IMIT VOUT MARGIN VOUT COMMAND Timing On Sequence Ramp TON DEL AY ATSC TON FAULT LIMIT MW NOUT MIN LTC2978 PERCENT Telemetry Temperature MPA TEMPERATURE PEAK 17 2978 28
59. tegrity Development Kit Stratix V GT Edition User Guide A 4 Appendix A Programming the Flash Memory Device Restoring the Flash Device to the Factory Settings Restoring the Flash Device to the Factory Settings This section describes how to restore the original factory contents to the flash memory device on the development board Make sure you have the Nios II EDS installed and perform the following steps 1 10 11 12 13 Set the board switches to the factory default settings described in Factory Default Switch Jumper Settings on page 4 2 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 23 for more information Click Add File and select install dir gt kits stratixVGT_5sgtea7_si factory_recovery s5gtea7_si_bup sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The FACTORY_IMAGE LED D10 illuminates indicating that the flash device is ready for programming On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell In the Nios II command shell navigate to the install dir gt kits stratixVGT_5sgtea7_si factory_recovery directory and type the following command to run the restore script res
60. tix V GT Edition Reference Manual Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide N DTE RYN 5 Board Update Portal This kit ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board The design consists of a Nios embedded processor an Ethernet MAC and an HTML web server When you power up the board with the PGMSEL jumper J28 in the factory position jump pins 2 3 the Stratix V GT FPGA configures with the Board Update Portal design example The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network The web page allows you to upload new FPGA designs to the user portion of flash memory and provides kit specific links and design resources gt 7 After successfully updating the user flash memory you can load the user design from flash memory into the FPGA To do so set the PGMSEL jumper J28 to the user position jump pins 1 2 and power cycle the board The source code for the Board Update Portal design resides in the lt install dir gt kits stratixVGT_5sgtea7_si examples directory If the Board Update Portal is corrupted or deleted from the flash memory refer to Restoring the Flash Device to the Factory Settings on page A 4 to restore the board with its original factory contents Connecting to the Board Update P
61. to the Factory Settings This section describes how to restore the original factory contents to the MAX II CPLD on the development board Make sure you have the Nios II EDS installed and perform the following instructions 1 Set the board switches to the factory default settings described in Factory Default Switch Jumper Settings on page 4 2 57 Setting the switch 57 6 MAX BYPASS to open 1 includes the MAX II device in the JTAG chain Setting the switch 57 6 MAX BYPASS to closed 0 removes the Max II device from the JTAG chain Launch the Quartus II Programmer Click Auto Detect Click Add File and select install dir NkitsNstratixVGT 5sgtea7 siNfactory recovery max2 pof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the MAX II CPLD Configuration is complete when the progress bar reaches 100 ensure that you have the most up to date factory restore files and information about this product refer to the Transceiver Signal Integrity Development Kit Stratix V GT Edition page of the Altera website February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide A 6 Appendix A Programming the Flash Memory Device Restoring the MAX II CPLD to the Factory Settings Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide N DTE
62. tore sh Restoring the flash memory might take several minutes Follow any instructions that appear in the Nios II command shell After all flash programming completes cycle the POWER switch SW1 off then on Using the Quartus II Programmer click Add File and select install dir NkitsNstratixVGT 5sgtea7 _51 recoveryNs5gtea7 si bup sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The FACTORY IMAGE LED D10 illuminates indicating that the flash device is ready for programming Cycle the POWER switch SW1 off then on to load and run the restored factory design The restore script cannot restore the board s MAC address automatically In the Nios command shell type the following Nios II EDS command nios2 terminal and follow the instructions in the terminal window to generate a unique MAC address that you have the most up to date factory restore files and information about this product refer to the Transceiver Signal Integrity Development Kit Stratix V GT Edition page of the Altera website Transceiver Signal Integrity Development Kit February 2013 Altera Corporation Stratix V GT Edition User Guide Appendix A Programming the Flash Memory Device A 5 Restoring the MAX II CPLD to the Factory Settings Restoring the MAX II CPLD
63. ut voltage Vop pre emphasis and equalization settings to optimize transceiver performance for your channel Perform jitter analysis Verify physical medium attachment PMA compliance to PCI Express PCle Gbps Ethernet GbE CEI 6G Serial RapidIO high definition serial digital interface HD SDI and other major standards This section briefly describes the Transceiver Signal Integrity Development Kit Stratix V GT Edition contents The Transceiver Signal Integrity Development Kit Stratix V GT Edition includes the following hardware Stratix V GT development board A development platform that allows you to develop and prototype hardware designs running on the Stratix V GT FPGA T For detailed information about the board components and interfaces refer to the Transceiver Signal Integrity Development Kit Stratix V GT Edition Reference Manual Power supply and cables The kit includes the following items m Power supply and AC adapters for North America Japan Europe and the United Kingdom m USB type A to B cable m Ethernet cable February 2013 Altera Corporation Transceiver Signal Integrity Development Kit Stratix V GT Edition User Guide 1 2 Chapter 1 About This Kit Kit Features Software The software for this kit described in the following sections is available on the Altera website for immediate downloading You can also request to have Altera mail the software to you on DVDs Quartus
64. works in conjunction with the Set New Frequency control button Clear This control sets the 51570 programmable oscillator to a default frequency of 100 MHz The default frequency is unique to each oscillator For all four default oscillator frequencies refer to Board Overview in the Transceiver Signal Integrity Development Kit Stratix V GT Edition Reference Manual Set New Frequency The Set New Frequency control sets the 51570 programmable oscillator frequency to the value in the Target frequency control Frequency changes might take several milliseconds to take effect Altera recommends resetting the FPGA logic after changing frequencies When a frequency change is made the oscillator will always change back to its default value first and then to the programmed value Configuring the FPGA Using the Quartus Il Programmer You can use the Quartus II Programmer to configure the FPGA with a sof Before configuring the FPGA ensure that the Quartus II Programmer and the USB Blaster driver are installed on the host computer the USB cable is connected to the development board power to the board is on and no other applications that use the JTAG chain are running gt Ifyou connect an external USB Blaster download cable and power cycle the board the on board Blaster is disconnected and the 55 UNLOCK function Table 4 4 on page 4 4 does not allow JTAG access to the FPGA To successfully use the USB Blaster cable disconnect it

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