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External Memory PHY Interface (ALTMEMPHY) (nonAFI

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1. Command XE XNOP e XNOP mem_ras_n mem_cas_n mem_we_n mem_cs_n mem_addr 0000 00001 0000 4 yy 0000 yon X0000 mem ba 00 mem dq mem dqs The command interface is made up of the signals mem ras n mem cas n mem we n mem cs n mem cke and mem odt The waveform Figure 4 5 shows a NOP command followed by five back to back write commands 1 commands asserted either on the rising edge of ac_clk_2x The 1 2 is derived from either mem_clk_ 2x 0 write clk 2x 270 the inverted variations of those two clocks for 180 and 90 phase shifts This depends on the setting of the address and command clock in the ALTMEMPHY MegaWizard interface All address and command signals except for mem_cs_ns mem_cke and mem_odt signals remain asserted on the bus for two clock cycles allowing sufficient time for the signals to settle The mem_cs_n mem_cke and mem_odt signals are asserted during the second cycle of the address command phase By asserting the chip select signal in alternative cycles back to back read or write commands can b
2. 4 11 Chapter Info Additional Information Revision ElSIOEV REP REN HRA heady Esdr ps p VR vars Info 1 How to Contact Altera Info 2 Typographic Conventions seieseep e bey died seta RR ERE Peer dea y oa px Eb e Info 2 External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation 1 About this Megafunction JAN DTE RYA This user guide is only for legacy designs as it describes the specifications and functional descriptions of the ALTMEMPHY megafunctions that are common to non Altera PHY interface nonAFI variations This user guide also describes the implementation of the QDR and QDR II SRAM interfaces for legacy designs targeted for Arria GX Stratix II and Stratix II GX devices The ALTMEMPHY megafunction is an interface between a memory controller and memory devices and performs read and write operations to the memory The megafunction is available as a stand alone product or as an integrated product with Altera high performance memory controllers As a stand alone product use the ALTMEMPHY megafunction with either custom or third party controllers The ALTMEMPHY megafunction for DDR3 DDR2 and DDR SDRAM offers two different PHY to controller interfaces Altera PHY interface AFI and nonAFI The AFI is
3. 3 42 Handshake Mechanism Between Read Commands and Read Data 3 43 Handshake Mechanism Between Write Commands and Write Data 3 44 DDR2 DDR SDRAM Full Rate OA AR eh n Waid a nbn e 3 47 Handshake Mechanism Between Read Commands and Read Data 3 47 Handshake Mechanism Between Write Commands and Write Data 3 49 Chapter 4 Support for Arria GX HardCopy Il Stratix Il and Stratix Il GX Devices DDR SDRAM 2 4 1 January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide Half Rate Support eee dou eh Ree bee aes gee Qa ERE ERR quee d eX eres add p ee 4 1 pde ert 4 1 Clock and Reset Management 4 3 Write Datap th isses Re bod e Pde Pee Pier rs ad 4 8 Address and Command Datapath 4 9 Full Rate Support 554 ree ee RE ce hes hec a OE E err alee wes 4 11 Read Datapath c he Yes hb e s er PR VY 4 11 Clock and Reset Management 4 11 Write Datapathi cesses ue eek E erage eir qu 4 11 Address and Command Datapath
4. mem addr h _ 0000 0004 0008 0006 0010 0000 ctl mem odt h PHY Read Data Input ctl doing rd i PHY Command Output W DDR Command 2 PCH NOP NOP XPCH Pa mem_cs_n L mem addr _ 0000 0004 Yo008 Joooc 0010 Xodoo mem odt i j Memory Interface mem dq 00000 mem_dqs PHY Read Data Output i i 8c8fe30 0ap6ab i ctl_mem_rdata 23eafic823ebfic8 6 i X T Xi 114004038 14064648 i 0503db0 140c4b3 i ctl_mem_rdata_valid i i i 4 5 i 21 2 3 4 Notes to Figure 3 12 1 The DDR command shows the command comprised of the command signals ct 1_mem_ras_n_h ctl_mem_cas_n_h and ctl mem we n h seen at the ALTMEMPHY input There can be more than one clock cycle of no operation NOP between active ACT to RD depending on the value of tacp parameter of your memory d
5. mem addr mem Memory Interface mem dq mem dqs PHY Read Data Output ctl mem rdata 808bdae4ec55833a ctl mem rdata valid Notes to Figure 3 14 1 The DDR command shows the command comprised of the command signals 1 mem ras n h ctl mem cas n h and ctl mem we n h seenatthe ALTMEMPHY input There can be more than one clock cycle of NOP between ACT to RD depending on the value of tacp parameter of your memory device 2 DDR command shows the command comprised of the command signals ras n h mem cas n h and mem we n h seen at the memory interface There can be more than one clock cycle of NOP between ACT to RD depending on the value of the parameter of your memory device External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 49 Design Considerations Handshake Mechanism Between Write Commands and Write Data Figure 3 15 shows the write operation for the full rate controller The handshake mechanism remains similar to the half rate controller except for the following differences 1 versus 2T addressing As the burst size is fixed at four on the memory interface and also the address and command datapath is based on 1T addressing it takes two memory clock cycles to write data into the memory for each of the write c
6. PHY Write Data Output mem dq mem_dasft Notes to Figure 3 13 1 The DDR command shows the command comprised of the command signals ct 1_mem_ras_n_h ctl_mem_cas_n_h and ctl mem we n h seenatthe ALTMEMPHY input There can be more than one clock cycle of NOP between ACT to RD depending on the value Of tren parameter of your memory device 2 The DDR command shows the command comprised of the command signals ras n h mem cas n h and mem we n h seen at the memory interface Figure 3 13 shows the sequence of operations that happen during the write transactions The write operation is explained step by step below the inputs to the megafunction from the controller should be generated using phy clk gt The signals under the PHY command input label are the signals from the controller to the ALTMEMPHY megafunction and the signals under the PHY command output label are the signals coming out of the ALTMEMPHY megafunction and input to the memory device Some of the address and command signals generated by the controller are ctl mem h ctl mem cas nh January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide Chapter 3 Functional Description ALTMEMPHY nonAFI Design Considerations ctl mem ce nh ctl mem ras nh
7. rdata 1x 4n wr data 2n rd data 4n rd lt gt wr phy 1x resync clk 2x Data Capture and Resynchronization Data capture and resynchronization is the process of capturing the read data DQ with the DOS strobe and re synchronizing the captured data to an internal free running full rate clock supplied by the enhanced phase locked loop PLL The resynchronization clock is an intermediate clock whose phase shift is determined during the calibration stage Timing constraints ensure that the data resynchronization registers are placed close to the DQ pins to achieve maximum performance Timing constraints also further limit skew across the DQ pins The captured data rdata 2x pand rdata 2x n is synchronized to the resynchronization clock 1 2 see Figure 4 1 Data Demultiplexing Data demultiplexing is the process of SDR data into HDR data Data demultiplexing is required to bring the frequency of the resynchronized data down to the frequency of the system clock so that data from the external memory device can ultimately be brought into the FPGA DDR2 DDR SDRAM controller clock domain Before data capture the data is DDR and n bit wide After data capture the data is SDR and 2n bit wide After data demuxing the data is HDR of width 4n bits wide The system clock frequency is half the frequency of the memory clock Demultiplexing i
8. ddr_cs_n ddr_ras_n ddr_cas_n ddr_we_n local init done DDR Command P 200 clock cycles Note to Figure 3 5 1 1ocal init done only goes high when calibration has completed January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 8 Chapter 3 Functional Description ALTMEMPHY nonAFI Initialization Timing The following sequence corresponds with the numbered items in Figure 3 5 on page 3 7 1 Theclock enable signal CKE is asserted 200 us after coming out of reset 2 Thecontroller then waits 400 ns and then issues the first PCH command by setting the precharge pin the address bit a 10 ora 8 high The 400 ns is calculated by taking the number of clock cycles calculated by the wizard for the 200 us delay and dividing this by 500 If a small initialization time is selected for simulation purposes this delay is always at least 1 clock cycle 3 Two ELMR commands are issued to load extend mode registers 2 and 3 with zeros 4 An ELMR command is issued to extend mode register 1 to enable the internal DLL in the memory devices 5 An LMR command is issued to set the operating parameters of the memory such as CAS latency and burst length This LMR command is also used to reset the internal memory device DLL 6 A further PCH command places all the banks in their idle state 7 Two ARF commands must
9. Signal Name Type Width Description ctl mem be input LOCAL IF Optional byte enable signals for the write data to the DWIDTH x external memory The PHY converts the byte DWIDTH enables into memory DM signals If DM pins are not RATIO required MEM DM PINS Setto FALSE the DM logic is not generated and the DM pins are not instantiated ctl mem wdata input MEM IF The write data bus which has valid data in the same DWIDTH clock cycles that 1 wdata validis DWIDTH asserted RATIO ctl mem rdata valid output 1 Indicates when the cC1 mem rdata is valid ctl mem wps n input MEM 8 Write enable signal from the controller to the WIDTH memory QDR SRAM When this signal is asserted a write request is issued to the address presented on the 1 mem addr nh port ctl mem rps n input MEM IF CS Read enable signal from the controller to the WIDTH memory QDR SRAM When this signal is asserted a read request is issued to the address presented on the 1 mem addr 1 port ctl mem rdata output LOCAL IF Captured resynchronized and de multiplexed read DWIDTH data from the PHY to the controller ctl mem wdata valid input 1 Generates the DQ output enable Note to Table 3 14 1 Address and command and wdata rdata Table 3 15 Calibration Status Signals for QDR II QDR SRAM Note 1 Signal Name Type Width Description ctl_usr_mode_rdy output 1 Active high signal specifying the PHY has finishe
10. c1k and mem n pair connect to the ODR IL ODR II SRAM device s K and Kn ports 4 Memory interface D Q data bits select 36 which is the data bus width for x36 QDR II QDR II SRAM interfaces After generation for devices with F780 and F1152 packages that do not have x18 DQ groups necessary to fit the write data bus follow these steps to modify the lt variation_name gt _pin_assignments tcl file to change the assignments to use x9 groups 1 Remove the memory interface data pin group assignment of 18 for write data bus and DM pins in the Assignment Editor 2 Find the following assignments in the lt variation_name gt _pin_assignments tcl set instance assignment name MEMORY INTERFACE DATA PIN GROUP 18 to d_pin_name 0 17 from 5 4 pin 04 January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide 2 10 Chapter 2 Parameter Settings set instance assignment name MEMORY INTERFACE DATA PIN GROUP dm_pin_name 0 1 from 5 4 04 set instance assignment name MEMORY INTERFACE DATA PIN GROUP d_pin_name 18 35 from d pin name V 184 set instance assignment name MEMORY INTERFACE DATA PIN GROUP dm 2 3 from 5 4 pin 18M 3 Replace with the following assignment set instance assignment name MEMORY INTERFACE DATA PIN GROUP d pin 0 to pin name 0 8 set instan
11. ddr2hpcore example lop Ib cas n ddi2hpcore example top n ddiZhpcore example top Ib dm ddiZhpcore example top Ib clk to sdram ddi2hpcore example top Ib clk to sdram n ddr2hpcore example top tb clk ddr2hpcore example top tb clk ddiZhpcore example top 1b a delayed ddr2hpcore example top Ib ba delayed ddiZhpcore example top Ib cke delayed ddiZhpcore example top Ib odt delayed ddi2hpcore example top Ib cs delayed Jddi2hpcore example top tb ras delayed ddr2hpcore example top tb cas n delayed ddr2hpcore example lop n delayed ddi2hpcore example top Ib dm delayed ddi2hpcore example lop tb mem da Cen ddi2hpcore_example_top_tb mem_dgs WIN ucc Ne ea Em e i ddi2hpcore example top Ib zero ddr2hpcore example top tb test complete ddr2hpcore example lop tb test complete count ddr2hpcore example top ddi2hpcore example top tb pnf per byte ee ES SS a 3 ddi2hpeore_example_top_tb emd_bus E en aei nai s eie f el Ee E Memory Initialization 203us 200us due to parameter 00 u 0 ps to 281533876 ps Now 268 127 501 ps Delta 16 301950611 pue euj uoienuiis jeuonoun iqyuou L Ty uondisag jeuorunJ Chapter 3 Functional Description ALTMEMPHY nonAFI 3 29 Functional Simulation the ModelSim Wave
12. Test Logic _ mem_clk_n mem_odt mem_addr mem cs n mem_tas_n mem_cas_n mem dq mem_dqs mem dm IDE Capture Ex dataout dataout_h Local I F 4 ready 4 local init done 4 local ready 94 mem local addr E4 mem_local_col_addr 4 mem local cs addr mem local read req E mem_local_rdata 4 mem E Tak I CONTROL I F Input control doing rd CONTROL Output ctlust_mode_rdy ctLaddress ctLread_req ctl_write_req 4 94 4 ctL_burstbegin_sig PLLI F LE E vede J XLI ELI j ITA Bp We up dE A RR RR ER RSS MESSEN BI BR NBI m B E mm m mm m m m m mm nm 2 20 wooo 308 34 10 0022 0 CNN 1 DP CE iO C O C ee 0 1 1 JULI E NI MI M mm I T UTR mL DL ni m m mmo nm mp mm _ Wo mu om mm mu m nb mn Um ON 0 C 2 TE minm gum
13. mem DDR Command 2 mem addr mem cs n mem odt PHY Write Data Output mem dq 000000 mem_dqs Notes to Figure 3 15 1 The DDR command shows the command comprised of the command signals ct 1_mem_ras_n_h ctl_mem_cas_n_h and ctl mem we n h seen atthe ALTMEMPHY input There be more than one clock cycle of NOP between ACT to RD depending on the value of tacp parameter of your memory device 2 The DDR command shows the command comprised of the command signals nem ras n h mem cas n h and we n h seen at the memory interface For DDR SDRAM the write latency is fixed at one memory clock cycle but for DDR2 SDRAM this value changes with the read CAS latency As the controller is running at half the rate of the memory clock a latency change of one controller clock cycle is actually two memory clock cycles The ALTMEMPHY megafunction allows you to dynamically insert an extra memory clock of delay in the address and command path to compensate for this The insertion of delay is controlled by the CMD ADD 1T parameter and the ct1 add 1t latsignal If ADDR CMD ADD 17 is set to the External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 51 Design Considerations string EXT_SELECT an extra cycle of latency can be dynamically inserted on the add
14. 3 10 Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals Table 3 1 1 0 Interface for DDR2 and DDR SDRAM nonAFI Note 1 Part 2 of 2 Signal Name Type Width Description mem dqsn bidir MEM IF DWIDTH The memory bidirectional data strobe bus Not used in MEM IF DQ PER DOS Arria GX HardCopy Stratix Il and Stratix GX designs mem odt output MEM IF CS WIDTH The memory on die termination control signal mem ras n output 1 The memory row address strobe mem reset n output 1 The memory reset signal mem we n output 1 The memory write enable signal Votes to Table 3 1 1 Connected to 1 0 pads 2 Output is for memory device and input path is fed back to ALTMEMPHY megafunction for VT tracking Table 3 2 Clock and Reset Signals for DDR2 DDR SDRAM nonAFl Note 1 Part 1 of 2 Signal Name global reset n 1 Type input Width 1 Description The asynchronous reset input to the controller All other reset signals are derived from resynchronized versions of this This signal holds the complete ALTMEMPHY megafunction including the PLL in reset while low soft reset n 1 input The asynchronous reset input to reset controller for SOPC Builder use or to be controlled by other system reset logic This signal causes a complete reset of the PHY but not the PLL in the PHY In Arria GX Stratix II and Stratix I GX devices this signal also reset
15. 4 4 L Now 268127501 2 EE T 4 263858182 ps to 268129131 ps Now 268 127 501 ps Delta 16 301950611 pue jeuonoun iqyuou 5 jeuorun 8 Chapter 3 Functional Description ALTMEMPHY nonAFI 3 39 Additional Debug Signals Additional Debug Signals This section discusses the following debug signals m PLL and PLL Reconfiguration Signals m Calibration Status Interface m Additional Calibration Status Interface Signals PLL and PLL Reconfiguration Signals Before any design operates correctly all clock and reset signals must be stable and configured correctly Therefore you must ensure that the various PLL ports are visible in your simulation This is of increased values when simulating a DDR and DDR2 SDRAM high performance memory controller based design because of the PLL phase calibration stages that occur For full description of each signal refer to Phase Locked Loop ALTPLL Megafunction User Guide You must add the following ALTMEMPHY signals to your simulation seq pll select phasecounterselect seq pll inc dec n phaseupdown seq pll start reconfig configupdate pll reconfig busy pll phase done pll locked phs shft busy pll reconfig reset In Arria GX Stratix IL and Stratix GX designs where a separate altpll reconfig in
16. Figure 3 13 shows that the controller state machine asserts the ctl mem wdata valid signal to perform a write transaction The write data ctl mem wdata should be available at the same time when the signal is asserted high The ct1 mem wdata valid signal is asserted for five clock cycles phy c1k ten clock cycles mem 1 to transfer five data transfers The write data is only valid when the ct1 mem wdata validis asserted high and is held in the wdata registers until the write occurs In Figure 3 13 the write data bus ct1 mem wdata is of width 64 and each burst transfer is of the length four The 64 bit wide data is transferred to the memory as four 16 bit wide data as shown by mem dq The DOS clock is twice the frequency of the clock that clocks the ct 1_mem_wdata and the DQ data is transferred during both the edges of DOS External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 47 Design Considerations DDR2 DDR SDRAM Full Rate Controller The following section details the handshake read and handshake write function for the DDR2 DDR SDRAM full rate controller For more information about the timing diagrams of a DDR2 SDRAM High Performance controller refer to the Timing Diagrams chapter in the DDR and DDR2 SDRAM High Performance Controllers and ALTMEMPRHY IP User Guide Handshake Mechanism Between Read Comman
17. Maximum memory freque 400 1M x18 BL4 CL2 5 400Mhz JQDRI 1M x36 BL4 CL2 5 400Mhz Show Load Preset Selected memory preset GQDRII 512k x18 BL4 CL2 5 400Mhz Modify parameters Description SRAM 400MHz 9Mbit 18 bits wide CAS 2 5 3 Info The PLL will be generated with Memory clock frequency 200 0 MHz and 64 phase steps per cycle The text window at the bottom of the MegaWizard Plug In Manager displays information about the memory interface warnings for example if you are creating an interface above the maximum frequency supported and errors if you are trying to create something that is not supported The Finish button is disabled until you fix all the errors indicated in this window The following section describes the Memory Settings tab for QDR IL ODR SRAM interface in more detail Memory Settings In the Memory Settings tab you can choose the frequency of operation for the device and a particular memory device for your system Under General Settings you can choose the device family speed grade and clock information In the middle of the page left side you can filter the available memory device listed on the right side of the Memory Presets dialog box refer to Figure 2 1 If you cannot find the exact device that you are using choose a device that has the closest specifications then manually modify the parameters to match your actua
18. Altera Corporation NU Additional Information Revision History The table below displays the revision history for the chapters in this user guide Date and Document Version Changes Made Summary of Changes January 2010 m Removed AFI information and added AFI information references to v9 1 SP1 the External Memory Interface Handbook Moved the nonAFI information to Chapter 3 Functional Description ALTMEMPHY nonAFI June 2009 m Added support for DDR3 SDRAM unbuffered DIMM multirank v7 2 memory configurations on Stratix Ill and Stratix IV devices April 2009 Added DDR3 SDRAM without leveling v7 1 Added new signals gt aux scan clk reset n PLL reconfiguration signals March 2009 v7 0 Included Arria 1 GX information Updated generated files list Updated AFI information Moved information to appendix Added AFI timing diagrams for reads Updated calibration process to indicate multiple chip select calibration is supported by all devices Added DDR3 SDRAM Discrete Device and DDR2 DDR SDRAM Calibration section Added clock sharing information Changed pin_assignments tcl description Added section on dynamic OCT support November 2008 v6 0 Included HardCopy IV information Added Altera PHY interface AFI information Amended HDL source file names to remove lt device name gt Added x36 emulation information July 2008 v5 0 Include
19. Connects to the seriesterminationcontrol bus ofthe ALT OCT megafunction This port exists when you target Stratix IV and Stratix Ill devices only oct ctl rt value input 14 Specifies parallel termination value Connects to the Notes to Table 3 5 parallelterminationcontrol bus ofthe ALT OCT megafunction This port exists when you target Stratix IV and Stratix Ill devices only 1 These ports are available if you want to use user mode OCT calibration Otherwise they can be left unconnected 2 For more information on OCT see the ALT OCT Megafunction User Guide External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 13 ALTMEMPHY Signals Table 3 6 Interface to the Memory Controller for DDR2 and DDR SDRAM nonAFl Note 1 Part 1 of 3 Signal Name Type Width Description ctl add 1t ac lat input 1 When asserted one extra address and command clock cycle 1T of latency is inserted in the address and command path if the ADDR_CMD ADD 1T parameter is set to EXT SELECT see Handshake Mechanism Between Write Commands and Write Data on page 3 49 For DDR SDRAM the write latency is fixed at one memory clock cycle but for DDR2 SDRAM this value changes with the read CAS latency As the controller is running at half the rate of the memory clock a latency change of one controller clock cycle is t
20. DIMM packages This option is only available for DDR3 DDR2 and DDR SDRAM interfaces Maximum frequency You can filter the type of memory by the maximum operating frequency January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 2 4 Chapter 2 Parameter Settings Use the Preset Editor to Create a Custom Memory Preset Pick a device in the Memory Presets list that is closest or the same as the actual memory device that you are using Then click the Modify Parameters button to parameterize the following settings in the Preset Editor dialog box m Memory attributes These are the settings that determine your system s number of DQ DQS address and memory clock pins m Memory initialization options These settings are stored in the memory mode registers as part of the initialization process m Memory timing parameters These are the parameters that create and time constraint the PHY Even though the device you are using is listed in Memory Presets ensure that the settings in the Preset Editor dialog box are accurate as some parameters may have been updated in the memory device datasheets You can change the parameters with a white background to reflect your system You can also change the parameters with a gray background so the device parameters match the device you are using These parameters in gray background are characteristics of the chosen memory device a
21. Defines the width of D and Q data bus on each QDRII SRAM chip Address width 15 25 bits Sets the number of address bits 1 0 standard QDR 11 SRAM 1 5 V Selects the 1 0 standard to be applied to the memory interface HSTL Class pins QDR II SRAM 1 8 V Class or 1 5 V HSTL Class Note to Table 2 3 1 The range values depend on the actual memory device used External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 2 Parameter Settings Table 2 4 QDR II QDR II SRAM Initialization Options 2 1 Parameter Name Range Units Description Memory burst 4 beats Sets the memory burst length for the interface As the length QDR II QDR SRAM ALTMEMPHY megafunction only supports half rate designs only a memory burst length of four is supported which equates to a local burst length of one Memory latency 1 5 QDR Il Cycles Sets the memory latency Altera devices only support latency of setting SRAM or 2 5 2 5 for QDR 1 SRAM and 1 5 for QDR II SRAM QDR 1 QDR 1 SRAM SRAM with latency of 2 0 is not supported with Altera devices even though the ALTMEMPHY MegaWizard interface shows this as an option Table 2 5 QDR II QDR II SRAM Timing Parameter Settings Parameter Name Range Units Description tsa 200 500 ps Address setup time to K clock rise tsc 200 500 ps C
22. Ee ERR dnd ed me ved lie enn 3 26 Functional Memory Use esee epe een ee ere x eee e ace re ie RR Rata 3 26 Functional Simulation the ModelSim Wave and Transcript Window 3 27 Full Window Stage Identification 3 27 Initialization Stage cte HEURES Ede e bep 3 29 Write Training Data Stage 3 31 Read Calibration Phase ne EX a i Ae Eolas 3 33 Functional Memory UseStage eese ere eere reet er heh n ER 3 37 Additional Debug Signals eee he bee beret te bs ERE 3 39 PLL and PLL Reconfiguration Signals 3 39 Calibration Status Interface 2 3 40 Additional Calibration Status Interface 3 40 Design Considerations 3 41 Clocks and Reselt5 4e ees pedet uen oie irat beso teo edi fee ndi ctn teen 3 41 Calibration Process Requirements 3 41 Local Interface Requirements cese eemper ie ere eee ee Ree e ied non 3 42 DDR2 DDR SDRAM Half Rate Controller
23. Figure 3 4 DDR SDRAM Device Initialization Timing 2 3 j clk ddra ddr ba ddrcsn i ddrras n ddr cas n ddr_we_n i local init done DDR Command Key P L LMR 200 clock cycles The following sequence corresponds with the numbered items in Figure 3 4 1 A PCH command is sent to all banks by setting the precharge pin the address bit 10 8 high An ELMR command is issued to enable the internal delay locked loop DLL in the memory devices An ELMR command is an LMR command with the bank address bits set to address the extended mode register An LMR command sets the operating parameters of the memory such as CAS latency and burst length This LMR command also resets the internal memory device DLL The DDR SDRAM high performance controller allows 200 clock cycles to elapse after a DLL reset and before it issues the next command to the memory A further PCH command places all the banks in their idle state Two ARF commands must follow the PCH command The final LMR command programs the operating parameters without resetting the DLL After issuing the final LMR command the memory controller hands over control of the me
24. Output 2 ell ust mode je e p e e n e n ia ee c i e TNI AC JN 259312506 ps to 264194657 ps Now 268 127 501 ps Delta 16 301950611 pue jeuonoun iqyuou 5 jeuorun Chapter 3 Functional Description ALTMEMPHY nonAFI 3 37 Functional Simulation the ModelSim Wave and Transcript Window gt Until the completion of the calibration phase the local interface remains static and all transactions take place over the control interface Additional signals of interest are added to the wave view For simulation purposes the ALTMEMPHY megafunction allows calibration of a single DQ pin If you do not enable this option then the time required for the calibration phase of the simulation is multiplied by the number of DQ pins used in your actual memory controller instance To enable this option select Quick Calibration under Auto Calibration Simulation Options list at the Memory Settings tab in the Parameter Settings page Functional Memory Use Stage Once the calibration stage completes indicated by the signals local_init_done and ct1_usr_mode_rdy then the functional memory use stage begins The example driver which is generated by the MegaWizard Plug In Manager is clear text HDL in the language of your choice It can be used to test a custom controller and ALTMEMPHY megaf
25. User Guide pll reconfig read input 1 For more information refer to the Phase Locked Loop param ALTPLL RECONFIG User Guide pll reconfig input 1 For more information refer to the Phase Locked Loop ALTPLL RECONFIG User Guide pll reconfig input 4 For more information refer to the Phase Locked Loop counter type ALTPLL RECONFIG User Guide pll reconfig input 3 For more information refer to the Phase Locked Loop counter param ALTPLL RECONFIG User Guide pll reconfig data input 9 For more information refer to the Phase Locked Loop in ALTPLL RECONFIG User Guide pll reconfig soft input 1 The asynchronous reset input to the PLL reconfiguration reset en n block This reset causes a PLL reconfiguration block reset and holds the reset if the ALTMEMPHY megafunction in reset while the signal is low This port only exists in the DDR2 DDR SDRAM variation for Arria GX Stratix and Stratix Il GX devices pll reconfig busy output 1 For more information refer to the Phase Locked Loop ALTPLL RECONFIG User Guide pll reconfig data output 9 For more information refer to the Phase Locked Loop out ALTPLL RECONFIG User Guide pll reconfig clk output 1 Synchronous clock to use for any logic accessing the PLL reconfiguration interface pll reconfig output 1 Resynchronized reset to use for any logic accessing the PLL reconfiguration interface January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAF
26. and Transcript Window Initialization Stage The full window stage shows that the Memory initialization stage is dominated by the NOP command where tir is 200 ps The exact sequence of commands differs between the various external memory families refer to the respective the device datasheets for further information For this DDR2 SDRAM example the following sequence applies 1 2 3 9 10 11 12 Issue NOP commands for 200 us programmable via parameter Assert mem cke high Issue a PCH then wait for 400 ns after 400 ns is derived from dividing counter by 500 Issue an LMR command to ELMR register 2 0 Issue an LMR command to ELMR register 3 0 Issue an LMR command to ELMR register to enable the memory DLL and set Drive strength AL RTT DOS RDOS OE Issue an LMR command to MR register to reset DLL and set operating parameters Issue a PCH Issue an ARF Issue another ARF Issue an LMR command to MR register to set operating parameters Issue an LMR command to ELMR register to set default OCD and parameters 200 clock cycles after DLL reset the memory is initialized See Figure 3 7 on page 3 30 for the expected waveform view of the initialization phase directly following the NOP of 200 us Steps 2 to 9 are expanded to increase detail Initialization is complete by the second yellow cursor Additional signals are added to simplify debugging January 2010 Altera Corporation Ex
27. by using the following device resources m PLL m PLL reconfiguration m DLL PLL The ALTMEMPHY MegaWizard interface automatically generates an ALTPLL megafunction instance The ALTPLL megafunction is responsible for generating the different clock frequencies and relevant phases used within the ALTMEMPHY megafunction The minimum PHY requirement is to have 16 phases of the highest frequency clock The PLL uses With no compensation operation mode to minimize jitter You must choose a PLL and PLL input clock pin that are located on the same side of the memory interface to ensure minimal jitter Cascaded PLLs are not recommended for DDR2 DDR SDRAM interfaces as jitter can accumulate with the use of cascaded PLLs causing the memory output clock to violate the memory device jitter specification Also ensure that the input clock to the PLL is stable before the PLL locks If not you must perform a manual PLL reset and relock the PLL to ensure that the phase relationship between all PLL outputs are properly set gt If the design cascades PLLs the source upstream PLL should have low bandwidth setting the destination downstream PLL should have a high bandwidth setting Adjacent PLLs cascading is recommended to reduce clock jitters For more information about the VCO frequency range and the available phase shifts refer to the PLLs in Stratix II and Stratix II GX Devices chapter in the respective device family handbook Extern
28. counter and search for No 0 s followed by 1 s pattern Latency counter timeout If pattern found Timed out for both phases of resync clk 1x All DQS groups calibrated Align all DQS groups to worst case latency Calibration successful Calibration unsuccessful External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 3 QDR II QDR II SRAM Calibration Process During the QDR IL ODR II SRAM calibration the sequencer first writes all Os to address space 3 in the external memory followed by all 1s to address space 5 It then loads the scan chain for the first time to program the first setting for resync clk 1x The sequencer then starts reading 05 from address space 3 several times followed by a single read from address space 5 and starts the latency counter If a pattern of all 05 followed by all 1s is read before the latency counter reaches its time out value 31 clock cycles the latency value for that memory device is stored If all Os followed by all 1s is not found when reading back from memory and the latency count has reached the time out value the sequencer loads the scan chains a second time to invert the resync_clk_1x signal The sequencer then starts reading from address space 3 several times followed by a single read from address space 5 as before
29. drives ct1_be during calibration 1 is mandatory and has the same timing as local_be January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 14 Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals Table 3 6 Interface to the Memory Controller for DDR2 and DDR SDRAM nonAFl Note 1 Part 2 of 3 Signal Name ctl doing rd Type input Width 1 Description The active high signal from the controller specifying that a read command has been issued to the external RAM For more information see Handshake Mechanism Between Read Commands and Read Data on page 3 47 ctl init done ctl negedge en input input The memory controller drives this active high signal to specify that the controller has initialized the memory and the calibration process should begin This signal is used if ADDR CMD NEGEDGE ENIS setto EXT SELECT If true the address and command signals are output on the falling edge of the address and command clock 2x If false the address and command signals are output on the rising edge of the address and command clock When set 10 EXT SELECT the ctl negedge en top level input determines whether the edge is used ctl read req output The active high signal requesting a read command to the address on the ct1_address bus ctl ready input The controller ready signal
30. indicating DWIDTH 8 the byte enable flags local read req input 1 The active high signal requesting a read command to the address on the address bus local ready output 1 The controller ready signal which indicates that the currently asserted read or write request has been accepted The address of the request is sampled when both the ready and request signals are high local size input LOCAL The controller signal to indicate the size length of BURST LEN the burst transfer fixed at 1 for this version BITS local_wdata input LOCAL IF The write data from the user to the ALTMEMPHY DWIDTH megafunction local wdata req output 1 The controller request for write data not required when the controller has an Avalon MM interface local write req input 1 The active high signal specifying that a write command should be issued to the address on the ctl address signal local refresh req input 1 The ALTMEMPHY megafunction receives refresh requests from the local interface and passes them to the controller 1 refresh req when user mode ct1 mode output is high local burstbegin input 1 The ALTMEMPHY megafunction receives the burstbegin signal from the local interface and passes it to the controller ctl_burstbegin when in user mode ct1 usr mode output is high local rdata output LOCAL IF Whenctl usr mode is high this output passes DWIDTH through the read data from the controller to the local interface Otherwise
31. it is tied low local rdata valid output 1 When ctl usr mode is high this output passes through the read data valid signal ctl rdata valid from the controller to the local interface Otherwise it is driven low local init done output 1 When ctl usr mode is high this output passes through the controller s initialization done signal ctl init done from the controller to the local interface Otherwise it is driven low local_refresh_ack output 1 When ct1_usr_mode is high this output passes through the controller s refresh acknowledge signal ctl refresh ack from the controller to the local interface Otherwise it is driven low local autopch req input 1 User control for auto precharge to request the controller to issue an autoprecharge write or autoprecharge read command External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals 3 17 Table 3 7 Local Interface Signals for DDR2 and DDR SDRAM nonAF Part 2 of 2 Note 1 Signal Name local powerdn req Type input Width 1 Description User control to power down the memory device to request the controller to place the memory devices into a power down state as soon as it can without violating the relevant timing parameters and responds by asserting the local_powerdn_ack signal local self rfsh req input User control
32. of the self refresh feature to request that the controller place the memory devices into a self refresh state by asserting this signal local self rfsh ack output Self refresh request acknowledge signal This signal is asserted and deasserted in response to the local self rfsh req Signal from the user local powerdn ack Note to Table 3 7 1 Passed through PHY to the controller output Power down request acknowledge signal This signal is asserted and deasserted in response to the local powerdn req signal from the user Table 3 8 Datapath Interface for 0082 and DDR SDRAM nonAF Part 1 of 3 Note 1 Signal Name Type Width Description ctl mem addr 1 input MEM IF The row or column address that is sent to the ROWADDR _ external memory Output during the high half WIDTH period of the address and command clock and driven by the memory controller ctl mem addr 1 1 input MEM IF The row or column address that is sent to the ROWADDR _ external memory Output during the low half period WIDTH of the address and command clock and driven by the memory controller ctl mem ba h 1 input MEM IF The bank address that is sent to the external BANKADDR_ memory Output during the high half period of the WIDTH address and command clock and driven by the memory controller ctl mem ba 1 1 input MEM IF The bank address that is sent to the external BANKADDR_ memory Output durin
33. preset QDRIl 512k x18 BL4 CL2 5 400Mhz Parameter Categories Category All Parameters Memory Attributes Memory Initialization Options Memory Timing Parameters Shaded parameters represent the defining characteristics of this memory device Modifying any of the shaded parameters will result in the creation of a custom preset r Parameters Parameter Value Derate x18 timing for x36 emulation mode Enabled Output clock pairs from FPGA Memory depth expansion Memory interface D G data bits bits Memory vendor Maximum memory frequency MHz Memory burst length beats Memory latency setting 2 cycles Drive BWS N NVVS_N from FPGA DG bits per chip bits Address width bits Address setup time to K Clock Rise tSA ps Control setup time to K Clock Rise tSC Address hold time to Clock Rise Control hold time to Clock Rise ps 3 2 For Derate x18 timing for x36 emulation mode select Enabled This setting tells the report timing tcl script to use the derating factor for x36 emulation If you have modified the board such that the slew rate of the x36 emulated double loaded CO COn signal is comparable to a non emulated single loaded CO COn signal you can leave this option as Disabled as there is no slew rate degradation in your design 3 For Output clock pairs from FPGA select 1 Only one
34. process significantly The ALTMEMPHY megafunction only the center of data valid window and read latency The amount of internal RAM required to store calibration results therefore is significantly reduced compared to earlier versions The total calibration time is also reduced Functional Memory Use When training and calibration completes the ALTMEMPHY sequencer asserts ctrl usr mode rdy to the memory controller which is then copied to the local interface as the signal 1ocal init done Local interface read and write transactions can now occur In the example testbench the example driver now performs 16 writes followed by 16 reads to incremental address locations spanning column row and bank locations using LFSR pattern based on the address being written External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 27 Functional Simulation the ModelSim Wave and Transcript Window Functional Simulation the ModelSim Wave and Transcript Window To better understand the operation of the ALTMEMPHY megafunction and the memory controllers identify the various stages of operation the expected results and the behavior of the IP The following sections describe each of these stages in greater detail m Full Window Stage Identification on page 3 27 Initialization Stage on page 3 29 Write Training Data Stage on p
35. supported for all variations of ALTMEMPHY for DDR3 DDR2 and DDR SDRAM ALTMEMPHY for DDR3 SDRAM only support the AFI The AFI results in a simpler connection between the PHY and controller so Altera recommends that you use the AFI for new designs only use the nonAFI for legacy designs For information about using the external memory interfaces DDR3 DDR2 and DDR SDRAM with AFI and the ALTMEMPHY megafunction refer to Volume 3 Implementing Altera Memory Interface IP of the External Memory Interface Handbook For more information about the ALTMEMPHY megafunction features refer to Volume 3 Implementing Altera Memory Interface IP of the External Memory Interface Handbook For information about issues on the ALTMEMPHY megafunction in a particular Quartus II software version refer to the Quartus II Software Release Notes Juanuary 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 1 2 Chapter 1 About this Megafunction External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide Juanuary 2010 Altera Corporation RAA 2 Parameter Settings This section describes the memory preset settings for the ALTMEMPHY nonAFI megafunction with the QDR IL ODR II SRAM interfaces only For information about using the MegaWizard Plug In Manager or the SOPC Builder flow to implement the ALTMEMPHY megafunction refer to the Getting Started chapter in Vol
36. to meet the required memory write latency therefore this exact relationship is very important 57 Thectl mem dqs burst signal controls the DOS output enables of the DOS pins External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 45 Design Considerations Figure 3 13 Write Commands and Write Data Half Rate Controller phy clk PHY Command Input i i DDR Command Note 1 ACT WR i l __ JWR ctl mem 9003 0000 0004 0008 0006 0010 0000 0004 _ 0008 ctl mem cs n h ctl mem odt h PHY Write Data Input cti mem wdata valid 8774840 26692ac 9883a83fb8e6045a _ 5a369at ctl mem wdata cdb042dicc72adi13 Y YES Aa O N Lia 13 1563 4ccf5491 2016447 PHY Command Output i mem ok J DDR Command Note 2 XPCH _ __ mem addr 0000 j 0003 m 0004 0008 0006 0010 0000 mem cs n i i i mem_odt
37. which indicates that the currently asserted read or write request has been accepted The address of the request is sampled when both the ready and request signals are high ctl size ctl usr mode rdy output output LOCAL BURST LEN BITS 1 The output to the controller indicating the size length of the burst transfer fixed at 1 for this version The ALTMEMPHY sequencer logic drives this active high signal to specify the ALTMEMPHY has finished its calibration and is ready to accept user read or write requests ctl wdata output LOCAL IF DWIDTH The write data from the ALTMEMPHY to the controller The ALTMEMPHY sequencer logic drives ctl wdata during calibration ct1_wdata has the same timing as 1ocal wdata ctl wdata req input The controller request for write data not required when the controller has an Avalon MM interface The memory controller that the ALTMEMPHY sequencer uses during calibration drives ctl wdata req Same timing as local wdata req ctl write req output The active high signal specifying that a write command should be issued to the address on the ctl address signal The ALTMEMPHY sequencer logic drives 1 write req during calibration Same timing as 1ocal write req External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI ALTME
38. x18 Device MegaWizard Plug In Manager ALTMEMPHY 4 ALTMEMPHY About Documentation Mem ti General Settings Device family Stratix IIl M Speed grade 2 M PLL reference clock frequency 100 MHz 10000 ps Memory clock frequency 200 MHz 5000 ps Emulated Device Local interface clock frequency Half M 100 0 MHz Actual Device Local interface width 72 Show in Memory Presets List 34 Parameter Value Presets Memory type GDRII SRAM QDRIl 512k x18 BL4 CL2 5 400Mhz Memory vendor Other QDRIl 512k x36 BL4 CL2 5 400Mhz Maximum memory freque 400 GDRII 1M x18 BL4 CL2 5 400Mhz GDRII 1M x36 BL4 CL2 5 400Mhz Losd Preset Selected memory preset GDRII 512k x18 BL4 CL2 5 400Mhz Modify parameters Description SRAM 400MHz 9 18 bits wide CAS 2 5 3 Info The PLL will be generated with Memory clock frequency 200 0 MHz and 64 phase steps per cycle To indicate that you are interfacing with 36 bit read and 36 bit write data follow these steps 1 Onthe Memory Settings page click Modify Parameters to open the Preset Editor see Figure 2 4 External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide January 2010 Altera Corporation Chapter 2 Parameter Settings 2 9 Figure 2 4 Preset Editor Preset Editor Memory
39. 0107 wayyy 0102 Auenuer Figure 3 9 Read Calibration Phase 5 wave default File Edit View Insert Format Tools Window 144 4 8 3 _ 4 localrefresh_ack CONTROL Input doing rd CONTROL I F Output 2 NE Now 268127501 ps ir oo 00 o O o NN PEO DOR Wo rox 000000000 11748 20 Oi X E X X XY 202990990 ps to 203916282 ps Now 268 127 501 ps Delta 16 301950611 pue euj uoienuiis jeuonoun iqyuou 1W Uondiiosag jeuorun v Chapter 3 Functional Description ALTMEMPHY nonAFI 3 35 Functional Simulation the ModelSim Wave and Transcript Window This process continues until all 360 full rate or 720 half rate worth of phases are sampled and the available data window is measured The length of time between each read is determined by the PLL reconfiguration requirements and the compare and store operation of the sequencer which is device and configuration dependant The gap observed between the first and subsequent reads is greater as the sequencer must set the PLL into phase stepping mode Once a successful range of phases has been sampled the sequencer center aligns the PLL phase within this calibrated window This can be observed on the PLL reco
40. 10 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 14704 AHdIN3IALLTV Mowa euer 100107 wayyy 0102 Auenuer Figure 3 8 Writing Data Training Y wave default Je jf File Edit View Insert Format Tools Window Se Bw 1 mm RAT NU for 50 yo rr y local_tefresh_req local refresh 268127501 ps xd 3 202753199 ps to 203225846 ps Now 268 127 501 ps Delta 16 301950611 pue jeuonoun c iqyuou 1W Uondiiosag jeuorun Chapter 3 Functional Description ALTMEMPHY nonAFI 3 33 Functional Simulation the ModelSim Wave and Transcript Window Read Calibration Phase Figure 3 9 on page 3 34 shows that the read data calibration stage closely follows the write data stage The calibration repeatedly performs the following steps 1 Reads back the data pattern 2 Records pass fail 3 Increments the PLL phase step 360 number of phase steps 4 Repeats January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 14704 AHdIN3IALLTV Mowa euer 10
41. About this Megafunction Chapter 2 Parameter Settings Memory Settings ee es NOREEN SEG EERE qb due fep 2 2 Use the Preset Editor to Create a Custom Memory Preset 2 4 Creating an Emulated x36 QDR IL ODR II SRAM ALTMEMPHY Variation 2 7 Chapter 3 Functional Description ALTMEMPHY nonAFI QDR II ODR SRAM Calibration Process 3 1 PHY to Controller Interfaces iiec bel ree med ee d ac y doe e dene 3 4 Initialization ININE echt ence 3 5 DDR SDRAM Initialization Timing 3 5 DDR2 SDRAM Initialization Timing 3 7 ALTMEMPHY 2 94 1 3 bind eect eles kel oer aeter ie bietet et sai de 3 9 DDR2 and DDR SDRAM Signals 3 9 QDR H QDR H SRAM Signals cac a Cei 4 bac EN eade e dre 3 20 Understanding the Testbench 3 25 PLL Initialization and Lock e he 3 25 Memory Device Initialization 3 25 Interface Training and 3 25 Write exer UENIRE VIII MIRO dud od ease 3 26 Calibration coetu Eee d EE
42. Emulated x36 QDR 11 0 II SRAM ALTMEMPHY Variation on page 2 7 Output clock pairs 1 16 pairs Selects the number of differential clock pairs driven from the from FPGA FPGA to the memory More clock pairs reduce the loading of each output when interfacing with multiple memory devices Memory clock pins use the signal splitter feature in Stratix 111 and Stratix IV devices for differential signaling Memory depth 1 2 chips Picks the number of chip selects of memory supported This expansion option is for memory depth expansion Memory interface 8 288 bits Defines the width of external memory read and write data bus D Q data bits Multiply the number of devices with the number of DQ pins per device when you create width expanded memory interfaces Even though the GUI allows you to choose 288 bit DQ width the interface data width is limited by the number of pins on the device For best performance have the whole interface on one side of the device Memory vendor Others Displays the name of the memory vendor for all supported memory standards The ALTMEMPHY megafunction only has generic QDR II QDR II SRAM data sheet information listed under vendor as Other Maximum memory See the memory device MHz Defines the maximum frequency supported by the memory frequency data sheet Drive Yes or No Enables the use of the write select pins for write operations BWS_N NWS_N when set to Yes from FPGA DQ bits per chip 8 9 18 36 bits
43. External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide NO S SPAN 101 Innovation Drive Software Version 9 1 SP1 San Jose CA 95134 Document Version 7 3 www altera com Document Date January 2010 UG 01014 7 3 Copyright 2010 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other coun tries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warran ty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services LS EN ISO 9001 N DTE RYN Contents Chapter 1
44. M Part 1 of 2 Signal Name Type Width Description global reset n 1 input 1 The asynchronous reset input to the controller All other reset signals are derived from resynchronized versions of this This signal holds the complete ALTMEMPHY megafunction including the PLL in reset while low soft reset n 1 input 1 The asynchronous reset input to reset controller for SOPC Builder use or to be controlled by other system reset logic This signal causes a complete reset of the PHY but not the PLL in the PHY In Arria GX Stratix and Stratix I GX devices this signal also resets the PLL reconfiguration block on a falling edge detection phy_clk output 1 The ALTMEMPHY megafunction half rate clock provided to the user All user inputs and outputs to the ALTMEMPHY megafunction are synchronous to this clock in half rate designs However this clock is not used in full rate designs pll_ref_clk input 1 The reference clock input to PLL reset phy clk n 1 output 1 Asynchronous reset that is de asserted synchronously with respect to the associated phy clock clock domain Use this to reset any additional user logic on that clock domain January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 22 Table 3 12 Clock and Reset Signals for QDR II QDR SRAM Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals Part 2 of 2 S
45. MPHY Signals 3 15 Table 3 6 Interface to the Memory Controller for DDR2 and DDR SDRAM nonAFI Note 1 Part 3 of 3 Signal Name ctl refresh ack Type input Width 1 Description The active high valid signal from the controller acknowledging the refresh request The ALTMEMPHY sequencer logic uses ctl refresh ack during calibration ctl refresh req output The output to the controller requesting a refresh Same timing as 1ocal refresh req ctl burstbegin output The output to the controller indicating the start of a burst Only available for the Avalon MM interface ctl rdata input LOCAL IF DWIDTH The read data from the controller The ALTMEMPHY sequencer logic uses ct1_rdata during calibration ctl_rdata has the same timing as local rdata ctl rdata valid input The active high valid signal for the controller read data Asserted coincident with the read data on ctl rdata The controller drives ctl rdata validand has the same timing as local rdata valid ctl add 1t odt lat input When asserted one extra address and command clock cycle 1T of latency is inserted in the address and command ODT path if ODT ADD 1715 set to EXT SELECT see Handshake Mechanism Between Write Commands and Write Data on page 3 49 The timing of the mem oat signal can be controlled in the same way as mem but is independent of the address and command latency If the ODT ADD 1T
46. Output clock pairs from FPGA 1 Memory depth expansion 1 Memory interface D G data bits 36 Memory vendor Maximum memory frequency MHz Memory burst length beats Memory latency setting cycles Drive BYYS_N NVVS_N from FPGA DQ bits per chip bits Address width bits Address setup time to K Clock Rise 15 ps Control setup time to K Clock Rise tSC ps Address hold time to K Clock Rise tHA ps Control hold time to K Clock Rise tHC Table 2 3 through Table 2 5 describe the QDR IL ODR II SRAM parameters available for memory attributes initialization options and timing parameters The QDR SRAM devices have the same parameters as QDR II SRAM devices but their value ranges can differ Confirm that the value you have chosen is valid in the ALTMEMPHY MegaWizard interface January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide 2 6 Table 2 3 QDR II QDR Il SRAM Attribute Settings Chapter 2 Parameter Settings Parameter Name Range 7 Units Description De rate x18 timing Enabled or Disabled Allows the ALTMEMPHY megafunction to derate the timing for emulation x36 calculation when creating x36 QDR II QDR II SRAM mode interfaces by using two x18 DQS DQ groups For more information on x36 emulation refer to Creating an
47. R IL ODR II SRAM is delayed and is divided by two to generate half rate clock resync clk 1x Data is captured on the rising edges of the shifted CQ and shifted COn signals There is one clk 1 per DOS group QDR II QDR II SRAM devices can only have one DOS group per device which means that there is one 1 1 signal associated with each memory device This signal clocks the registers doing the full rate to half rate conversion It also clocks the front side of the read datapath clock crossing FIFO There is one FIFO per DOS group or memory device resync clk 1 signal be inverted or not inverted You can transfer data in the correct byte order with one of these options The main objective of calibration is to find out whether the resync clk 1 signal requires inversion which is done by loading the shift register see Figure 3 1 at most twice per QDR IL ODR SRAM device Each memory device is calibrated one after the other Figure 3 2 shows the ODR IL ODR II SRAM calibration flowchart Figure 3 2 QDR II QDR II SRAM Calibration Flowchart Write 0 s pattern to address 3 Calibration start y y Write 1 s pattern to address 5 y Setup resync_clk_1x phase associated with DQS group being calibrated Read 0 s pattern Read 1 s pattern Invert resync_clk_1x phase A Start latency
48. RSU can find one data valid window and not more than one the resynchronization clock is positioned at the center and the read latency output is then set to the read latency in phy cycles using that resynchronization clock phase If calibration is unsuccessful this signal remains at 0 rsu no dvw err Calibration failed due to no window found If the RSU sweeps the resynchronization clock across every phase and does not see any valid data at any phase position calibration fails and this output is set to 1 rsu grt one dvw err Calibration failed due to more than one valid window If the RSU sweeps the resynchronization clock across every phase and sees multiple data valid windows this indicates unexpected read data random bit errors or an incorrectly configured PLL which must be resolved Calibration has failed and this output is set to 1 rsu multiple valid latencies err Calibration failed due to more than two read latencies If the RSU sweeps the resynchronization clock across every phase and sees valid data at more than two different latencies calibration fails and this output is set to 1 QDR 1 008 II SRAM Signals This section describes the ALMEMPHY megafunction signals for QDR H QDR II SRAM Table 3 11 through Table 3 15 show the signals Signals with the prefix mem connect the PHY with the memory device signals with the prefix ct1_ connect the PHY with the control
49. The clock that controls the postamble logic the postamble clock is the negative edge of the resynchronization clock No additional clocks are required Figure 4 2 shows the relationship between the postamble clock and the resynchronization clock Figure 4 2 Relationship Between Postamble Clock and Resynchronization Clock Note 1 resync clk 2x postamble clk 90 shifted dq Data input to resync reg s ARST at postamble reg s Note to Figure 4 2 1 resync clk 2xis delayed further to allow for the I O element IOE to core transition time For more information about the postamble circuitry refer to the External Memory Interfaces chapter in the Stratix II Device Handbook Clock and Reset Management The clocking and reset block is responsible for clock generation reset management and phase shifting of clocks It also has control of clock network types that route the clocks January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 44 Chapter 4 Support for Arria GX HardCopy Il Stratix Il and Stratix II GX Devices DDR2 DDR SDRAM Clock Management The ability of the ALTMEMPHY megafunction to work out the optimum resynchronization clock phase during calibration and to track the system voltage and temperature VT variations Clock management is done by phase shifting the clocks relative to each other Clock management circuitry is implemented
50. ace during the initial calibration stage The ALTMEMPHY megafunction has four interfaces that all must be connected appropriately Figure 3 3 shows the four interfaces amp AsanSRAM the PHY for QDR II SRAM lacks most of the ct 1_ and local_ ports as you can use a driver that acts as a controller to generate read and write commands and data in the QDR IL ODR II SRAM PHY Figure 3 3 The Four ALTMEMPHY Megafunction Interfaces Addr amp Cmd Path Write path External Memory Read path Controller Ports named ctl_mem_ Ports named local_ User logic or example driver named ctl named mem_ Y Auto calibration ALTMEMPHY Clock amp reset management The four ALTMEMPHY interfaces from left to right are 1 The local interface is the interface between the user logic and the memory controller The signals between user logic and the controller traverse through the ALTMEMPHY megafunction This can either be an Avalon Memory Mapped slave interface or a Native interface All the ports on this interface have their names prefixed with local forexample local init done During the initial calibration period the auto calibration logic takes control of this interface and issues the write and read requests that the memory controller requires When the calibration process is com
51. age 3 31 Read Calibration Phase on page 3 33 Functional Memory Use Stage on page 3 37 Full Window Stage Identification Figure 3 6 on page 3 28 shows a standard appearance of an example testbench in the ModelSim Altera software The total simulation time around 270 us to 203 us is used for the memory initialization requirements and in this example 61 ps is used by the calibration routine to calibrate using just a single DO pin In general the PLL initialization phase has negligible impact on the overall simulation time For further information on simulating the PLL refer to Phase Locked Loop ALTPLL Megafunction User Guide January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 14704 AHdIN3IALLTV Mowa euer 100107 wayyy 0102 Auenuer Figure 3 6 Example Testbench 82 wave default Eie Edit View Insert Format Tools Window E l ddr2hpoore_example_top_tb cmd_bus_watcher_enabled 510 ddiZhpcore example top tb clk ddi2hpcore example lop tb clk n ddr2hpcore example top Ib reset n ddi2hpcore example top reset n ddiZhpcore example top tb a ddr2hpcore example top ddr2hpcore example top Ib cs n ddr2hpcore example Ib cke ddr2hpcore example top Ib odt ddr2hpcore example lop tb ras
52. al Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 4 Support for Arria GX HardCopy Il Stratix II and Stratix Il GX Devices DDR2 DDR SDRAM 4 5 Table 4 1 shows the clock outputs that Arria GX HardCopy II Stratix II and Stratix II GX devices use Table 4 1 DDR2 DDR SDRAM Clocking in Arria GX HardCopy Stratix Il and Stratix II GX Devices Part 1 of 2 Design Postscale Phase Clock Rate Clock Name Counter Degrees Clock Rate Network Type Notes Half rate phy clk 1x co 0 Half Rate Global The only clock that is made available on the user and interface of the ALTMEMPHY aux_half_rate_ megafunction This clock clk also feeds into a divider circuit to provide the PLL scan_clk signal for reconfiguration that must be lower than 100 MHz mem clk 2x C1 0 Full Rate Global This clock is for clocking DQS and as a reference and Clock for the memory devices aux full rate clk Full rate aux half rate C0 09 Half Rate Global The only clock that is clk made available on the user interface of the ALTMEMPHY megafunction This clock also feeds into a divider circuit to provide the PLL scan clk signal for reconfiguration that must be lower than 100 MHz phy clk 1 1 C1 0 Full Rate Global This clock is for clocking DQS and as a reference and clock for the memory devices mem_clk 2x and aux full rate clk Half rate wri
53. als Add the signals in Table 3 17 to your simulation to provide additional information about calibration status Table 3 17 Signals for Calibration Status Signal Description rsu codvw phase The ALTMEMPHY resynchronization setup unit RSU sweeps the phase of a Center of data valid window resynchronization clock across 360 full rate mode or 720 half rate mode of a memory clock cycle Data reads from the DIMM are performed for each phase position and a data valid window is located which is the set of resynchronization clock phase positions where data is successfully read The final resynchronization clock phase is set at the center of this range the center of the data valid window or CODVW This output is set to the current calculated value for the CODVW and represents how many phase steps were performed by the PLL to offset the resynchronization clock from the memory clock rsu read latency If the RSU can find one data valid window and not more than one then the Read latency at the center of the window resynchronization clock is positioned at the center and the rsu read latency output is then set to the read latency 1 cycles using that resynchronization clock phase If calibration is unsuccessful then this signal remains at 0 rsu no dvw err If the RSU sweeps the resynchronization clock across every phase and does Calibration failed due to no window found not see any valid data at any phase position t
54. and starts the latency counter again If all 05 followed by all 1s are read back from memory the latency value for that memory device is stored The training pattern must be read back correctly on this second iteration if it was not already read correctly on the first iteration If it is not read back correctly it indicates an underlying problem in the system The previous process is repeated until all memory devices are tested and a latency value obtained for each device The latency values found for the different devices are compared with each other If necessary they are aligned to the worst case latency or to the user requested deterministic latency value if this option is used which done by adjusting address pointers in order to add latency to some of the read datapath RAMs inside the until the latency associated with all of the memory devices is aligned to the worst case latency measured You cannot have a latency difference of more than two PHY clock cycles between all the QDR IL ODR II SRAM devices in non deterministic latency mode When calibration has finished the sequencer hands over control to the driver user logic and generates the p rdata out valid flag to indicate when read data is valid The sequencer also outputs the following signals upon completion of calibration p ready lndicates completion of the calibration process but does not mean calibration was successful This si
55. anuary 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 26 Chapter 3 Functional Description ALTMEMPHY nonAFI Understanding the Testbench Write Training Data A specific pattern of data is written to the memory so that each DQ pin may be calibrated The same pattern is written to every DQ pin The pattern takes the form 10101010 11111111 00000000 11111100 from the lowest address location to the highest address location left to right Once the memory interface is initialized a single write transaction is observed to the memory using the pattern above to write the same pattern to each DQ bit Calibration When the write training data process is completed the sequencer then repeatedly reads the training pattern back from the memory This action is performed on a per DQ pin basis and for all available phase steps supported by the PLL configuration The sequencer phase steps through 360 for a full rate controller and through 720 for a half rate controller For simulation purposes only calibration can be performed on just a single DO pin which greatly reduces simulation run time The sequencer stores a list of pass and fail training pattern results and when all phase comparisons have been made sets the optimum clock phase to be centered in the available window of results Simulation of the calibration cycle cannot be bypassed but setting it to single bit calibration speeds up the
56. ce assignment name MEMORY INTERFACE DATA PIN GROUP d pin 0 to dm_pin_name 0 set instance assignment name MEMORY INTERFACE DATA PIN GROUP d pin 18 to pin name 18 26 set instance assignment name MEMORY INTERFACE DATA PIN GROUP d pin 18 to 5 pin 2 set instance assignment name MEMORY INTERFACE DATA PIN GROUP d pin 9 to pin 9 17 set instance assignment name MEMORY INTERFACE DATA PIN GROUP d pin 9 to dm_pin_name 1 set instance assignment name MEMORY INTERFACE DATA PIN GROUP d pin 27 to pin 27 35 set instance assignment name MEMORY INTERFACE DATA PIN GROUP d pin 27 to 5 pin 3 4 Save the variation name assignments tcl file 18 18 18 9 9 9 9 9 9 9 9 toO tO tO from from from from from from from from The rest of the RTL implementation is similar to a regular QDR IL ODR II SRAM interface External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation 3 Functional Description ALTMEMPHY JN DTE RYAN nonAFI This chapter describes the ODR IL ODR II SRAM calibration process the typical PHY to Controller interfaces that are connected to the ALTMEMPHY variation and the signal name prefi
57. ck measures relative phase shifts between the internal clock s and those being fed back through a mimic path As a result the ALTMEMPHY megafunction can track VT effects on the FPGA and compensate for the effects The 1 2 clock is derived from either 1 2 when you choose 0 180 phase shift or write 2x when you choose 90 or 270 phase shift Votes to Table 4 1 1 In full rate designs a 1x clock may run at full rate clock rate 2 This clock should be of the same clock network clock as the resync_clk_2x clock PLL Reconfiguration The ALTMEMPHY MegaWizard interface automatically generates the PLL reconfiguration block by instantiating an ALTPLL_RECONFIG variation for Stratix II and Stratix II GX devices to match the generated ALTPLL megafunction instance The ALTPLL_RECONFIG megafunction varies the resynchronization clock phase and the measure clock phase External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 4 Support for Arria GX HardCopy Il Stratix II and Stratix Il GX Devices 4 7 DDR2 DDR SDRAM DLL A DLL instance is included in the generated ALTMEMPHY variation When using the DOS to capture the DQ read data the DLL center aligns the DOS strobe to the DO data The DLL settings depend on the interface clock frequency For more information refer to the External Memory Interfaces chapter in
58. ctl mem we nh ctl mem odt h As can be seen in the waveform Figure 3 13 the sequence of commands are PreCharge PCH ACT and NOP followed by a series of write commands 1 Thecontroller puts the five consecutive write commands with a starting address of 0 x with increments of four 0000 0004 0008 000c 0010 see the top of Figure 3 13 under the PHY Command Input label 2 The controller generates the following signals two clock cycles after ctl mem wdata valid and must supply the data ct1 mem wdata along with these two clock cycles Refer to Figure 3 13 under the PHY Write Data Input label 3 The ALTMEMPHY megafunction generates the write command at the memory interface after five to seven memory clock mem c1k cycles to accommodate the write delay In this example the address and commands are generated using the negative edge of the memory clock see Figure 3 14 under the PHY Command Output label 4 The address and commands are of 2T period and the chip select is of 1T period 5 The data mem dq at the memory interface is presented after two memory clock cycles of write latency The write latency is equal to the CAS latency 1 for DDR2 SDRAM only for DDR SDRAM it is always 1 For this example CAS latency is equal to three 6 The generation of DOS signals is controlled using the control mem wdata validsignal which is very important as the generation of the DOS signal is also dependent on the CAS latency parameter
59. d its calibration and is ready to accept user read or write requests This signal does not indicate that calibration was successful so you must check whether resynchronization_successful is high also resynchronisation_ output 1 Active high signal that shall be set to indicate that successful calibration of the read data resynchronization clock phase was successful ctl rlat output 5 Indicates the read latency of the interface in PHY clock cycles Note to Table 3 15 1 Calibration control or passed through from the user interface January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 24 Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals Table 3 16 shows the parameters that Table 3 11 through Table 3 15 refer to Table 3 16 Parameters Parameter Name DBG A WIDTH Description DQS DELAY CTL WIDTH DWIDTH RATIO The data width ratio from the local interface to the memory interface DWIDTH RATIO of 2 means full rate while RATIO of 4 means half rate LOCAL IF DWIDTH M M IF DWIDTH The data width at the memory interface MEM_IF_DWIDTH can have values that are The width of the local data bus must be quadrupled for half rate and doubled for full rate multiples of MEM IF M IF DQS WIDTH M IF ROWADDR WIDTH The row address width of the memor
60. d HardCopy 111 and Stratix IV information Updated to include changes in the Quartus II software version 8 0 Moved Appendix A to the end of Chapter 1 Updated all sections in Chapters 1 2 and 3 Added Chapters 4 5 6 and 7 January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide Info 2 Chapter Additional Information How to Contact Altera Date and Document Version December 2007 v4 1 Updated Figure A 4 Changes Made Summary of Changes December 2007 v4 0 Updated to include changes in the Quartus software version 7 2 June 2007 v3 0 Updated to include Arria GX and changes included in the Quartus software version 7 1 March 2007 v2 0 Updated to included Cyclone III information February 2007 v1 0 Initial release How to Contact Altera For the most up to date information about Altera products see the following table Contact Contact Wote 1 Method Address Technical support Website www altera com support Technical training Website www altera com training Email custrain altera com Altera literature services Email literature altera com Non technical support General Email nacomp altera com Software Licensing Email authorization altera com Note 1 You can also contact your local Altera sales office or sales representative Typographic Conve
61. d completes when the signal 11 locked is first asserted Typically this stage requires approximately 150 ns but can take longer if the PLL Option Hold locked output low for user entered number cycles after the PLL initializes is turned on The exact length of time required for p11 locked to become asserted depends on several factors including Device Type PLL Type and PLL Configuration pll locked is not included in the simulation default waveform view and must be added manually For more information refer to Phase Locked Loop ALTPLL Megafunction User Guide Memory Device Initialization Memory devices must be initialized before functional use The exact sequence is different for DDR2 and DDR SDRAM The memory controller sets the operating parameters of the memory based on the parameters you specify in the MegaWizard interface This parameter is fixed at generation time and is not dynamically editable via the local interface Interface Training and Calibration The sequencer element of the ALTMEMPHY megafunction performs path delay analysis to correctly set up the resynchronization DOS mode devices capture Non DOS Mode devices clocks and the data alignment settings The sequencer issues read and write commands to the memory controller over the ct1 interface for DDR and DDR2 SDRAM high performance memory controllers which is performed in the following two stages m Write training data m Calibration J
62. d signals in full rate designs or mem_cs_n mem_cke and mem_odt signals in half rate designs m 2T half rate The duration of the address and command is two memory clock cycles For half rate designs the ALTMEMPHY megafunction supports only a burst size of four which means the burst size on the local interface is always set to 1 The size of the data is 4n bits wide on the local side and is n bits wide on the memory side To transfer all the 4ri bits at the double data rate two memory clock cycles are required The new address and command can be issued to memory every two clock cycles This scheme applies to all address and command signals except for mem_cs_n mem_cke and mem odt signals in half rate mode Refer to Table 4 1 in PLL on page 4 4 to see the frequency relationship of mem clk 2x with the rest of the clocks Figure 4 5 shows a chip select signal mem cs which is active low and disables the command in the memory device All commands are masked when the chip select signal is inactive The mem cs nsignalis considered part of the command code January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 4 10 Chapter 4 Support for Arria GX HardCopy Il Stratix II and Stratix Il GX Devices DDR2 DDR SDRAM Figure 4 5 Arria GX HardCopy Il Stratix 11 and Stratix GX Address and Command Datapath PHY Command Outputs ac_clk_2x
63. ds and Read Data Figure 3 14 shows the read operation for a full rate controller The handshake mechanism remains similar to that of the half rate controller except for the following differences 1 1T versus 2T addressing As the burst size is fixed at four on the memory interface and also the address and command datapath is based on 1T addressing it takes two memory clock cycles to retrieve the data from the memory for each read command see Figure 3 14 The first memory cycle is the read command and the second memory cycle is the NOP command Because of this arrangement you see a NOP command between the read commands 2 Assertion of the chip select signal The chip select signal is asserted along with the read command because of the 1T addressing January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 48 Chapter 3 Functional Description ALTMEMPHY nonAFI Design Considerations Figure 3 14 Read Commands and Read Data Full Rate Controller phy clk PHY Command Input DDR command 1 ctl mem addr h cti mem cs n h ctl mem odt h PHY Read Data Input local_read_req ctl_doing_rd count_wr 0000 local_ready PHY Command Output mem_clk DDR command 2 NOP RD JuoP Ro JvoP no RD NOP mem cs n
64. e issued The address is incremented every other 1 2 cycle 7 The ac_clk_2x clock is derived from either mem 2x when you choose 0 or 180 phase shift or write_clk_2x when you choose 90 or 270 phase shift 7 The address and command clock can be 0 90 180 or 270 from the system clock External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 4 Support for Arria GX HardCopy Il Stratix Il and Stratix Il GX Devices 4 11 DDR2 DDR SDRAM Full Rate Support The following section discusses full rate support for Arria GX HardCopy II Stratix II and Stratix II GX devices Read Datapath The full rate datapath is similar to the half rate datapath The full rate datapath also consists of a RAM with the same width as the data input just like that of the half rate but the width on the data output of the RAM is half that of the half rate PHY The function of the RAM is to transfer the read data from the resynchronization clock domain to the system clock domain Postamble Protection The postamble protection is the same as the half rate support Clock and Reset Management For full rate clock and reset management refer to The PLL is configured exactly in the same way as in half rate designs The PLL information and restriction from half rate designs also applies 7 The phy_clk_1x clock is now full rate despite the 1x naming conv
65. ention You must choose a PLL and PLL input clock pin that are located on the same side of the memory interface to ensure minimal jitter Cascaded PLLs are not recommended for DDR2 DDR SDRAM interfaces as jitter can accumulate with the use of cascaded PLLs causing the memory output clock to violate the memory device jitter specification Also ensure that the input clock to the PLL is stable before the PLL locks If not you must perform a manual PLL reset and relock the PLL to ensure that the phase relationship between all PLL outputs are properly set The PLL restrictions in half rate designs also applies to full rate designs Write Datapath The write datapath is similar to the half rate PHY The IOE block is identical to the half rate PHY The latency of the write datapath in the full rate PHY is less than in the half rate PHY because the full rate PHY does not have the half rate to full rate conversion logic Address and Command Datapath The address and command datapath for full rate designs is similar to half rate designs except that the address and command signals are all asserted for one memory clock cycle only 1T signaling January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 4 12 Chapter 4 Support for Arria GX HardCopy Il Stratix Il and Stratix Il GX Devices DDR2 DDR SDRAM External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010
66. evice 2 The DDR command shows the command comprised of the command signals mem_ras_n_h mem cas h and mem we n h seen at the memory interface There be more than one clock cycle of NOP between active ACT to RD depending on the value of the trop parameter of your memory device 7 The signals under the PHY Command Input label are the signals from the controller to the ALTMEMPHY megafunction The signals under the PHY Command Output label are the signals coming out of the ALTMEMPHY megafunction and input to the memory device January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 44 Chapter 3 Functional Description ALTMEMPHY nonAFI Design Considerations Some of the address and command signals generated by the controller are ctl mem h ctl mem cas h ctl mem cs nh ctl mem ras n h ctl mem we n h ctl mem odt h Figure 3 12 shows the No Operation NOP command followed by a series of five read commands 1 Thecontroller issues five consecutive read commands with a starting address of 0x0 with increments of four 0000 0004 0008 000c 0010 see the top of Figure 3 12 under the PHY Command Input label 2 The ALTMEMPHY megafunction generates the read command at the memory interface after five to seven memory clock nem c1k cycles The address and commands are generated using the negative edge of the memory clock see Figure 3 12 unde
67. evices are expected to tie the 11 reconfig soft enshellto VCC to enable PLL reconfig soft resets January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide Figure 4 3 ALTMEMPHY Reset Management Block for Arria GX HardCopy 11 Stratix 11 and Stratix 11 GX Devices 8 1 14704 AHdIN3IALLTV Mowa euer 100107 gay 0102 Auenuer phy_clk T clk PLL clk div reset ams n r pll_reconfig_reset_ams_n reconfig DSETQ DSETQ eset clk_divider_reset_n set lk div reset ams n T 2080 CLR CLR pll_reconfig_reset_ams_n_r scancik i pll_locked ll reconfig reset n CRC Iu reset request n gt 4 reset master ams global pre clear system ps eee PLL clock Optional global reset n pll reset C gt reset request n i S te areset active HIGH edgedetectand phy out esetcounter 00 Ue enm eel pll_reconfig_soft_reset_en soft_reset_n p global_or_soft_reset_n phy internal reset PHY resets gt l Write Datapath The write datapath logic efficiently transfers data from the HDR memory controller to DDR SDRAM based memories The write datapath
68. follow the PCH command 8 A final LMR command is issued to program the operating parameters without resetting the DLL 9 200 clock cycles after step 5 two ELMR commands are issued to set the memory device off chip driver OCD impedance to the default setting After issuing the final ELMR command the memory controller hands over control of the memory to the ALTMEMPHY megafunction to allow it to carry out its calibration process When ALTMEMPHY megafunction has finished calibrating the memory controller asserts the local init done signal which shows that it has initialized the memory devices External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 9 ALTMEMPHY Signals ALTMEMPHY Signals This section describes the ALMEMPHY megafunction signals for the following interfaces m DDR2 DDR SDRAM signals m QDR II and QDR II SRAM signals DDR2 and DDR SDRAM Signals Table 3 1 through Table 3 10 show the signals for DDR2 and DDR SDRAM nonAFIs The signal lists include the following signal groups I O interface to the external memory device Clock and reset signals PLL reconfiguration signals External DLL signals User mode calibrated on chip termination OCT control signals Interface to the memory controller Local interface signals Datapath interface for the controller ALTMEMPHY megafunction calibratio
69. g the low half period of the WIDTH address and command clock and driven by the memory controller ctl mem be input LOCAL IF__ The optional byte enable signals for the write data DWIDTH 8 to the external memory The ALTMEMPHY megafunction converts the byte enables into memory mem dm signals If mem dm pins are not required dm pins set to FALSE the mem dm logic is not generated and the dm pins are not instantiated ctl mem cas n h 1 input 1 The column address strobe signal from the controller to the memory Output during the high half period of the address and command clock and driven by the memory controller January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 18 Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals Table 3 8 Datapath Interface for 0082 and DDR SDRAM nonAF Part 2 of 3 Note 1 Signal Name Type Width Description ctl mem cas n 1 1 input 1 The column address strobe signal from the controller to the memory Output during the low half period of the address and command clock and driven by the memory controller ctl mem cke h 1 input MEM IF CS Theclock enable signal from the controller to the WIDTH memory Output during the high half period of the address and command clock and driven by the memory controller ctl mem cke 1 1 input MEM IF CS Theclock enable signal fr
70. gnal is renamed as the 1 usr mode rdy signal at the ALTMEMPRHY top level file B p calibration successful lndicates calibration was successfully completed This port is renamed resynchronisation successful port at the ALTMEMPHY top level file p user defined latency ok lndicates that the read latency requested by the user was achievable when using deterministic latency This port is not instantiated at the top level of the file Currently this signal exists at the sequencer wrapper file level only B p detectedlatency Specifies the read latency achieved in phy c1k clock cycles This portis renamed ct1 rlat port at the ALTMEMPHY top level file January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 4 Chapter 3 Functional Description ALTMEMPHY nonAFI PHY to Controller Interfaces VT tracking is not required because the read strobe from the QDR IL ODR SRAM memory is continuous So all registers in the I O to the read RAM path are clocked using a clock that is derived from the QDR II QDR II SRAM read clock La For more information about the QDR II SRAM signals refer to QDR II QDR II SRAM Signals on page 3 20 PHY to Controller Interfaces The nonAFT s autocalibration logic relies on the services of the memory controller to perform its calibration writes reads and memory initialization so it must have control of the controller s local interf
71. hen calibration fails and this output is set to 1 External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 41 Design Considerations Table 3 17 Signals for Calibration Status Signal rsu grt err Calibration failed due to more than one valid window Description If the RSU sweeps the resynchronization clock across every phase and sees multiple data valid windows this is indicative of unexpected read data random bit errors or an incorrectly configured PLL which must be resolved Calibration has failed and this output is set to 1 rsu multiple valid latencies err Calibration failed due to more than two read latencies If the RSU sweeps the resynchronization clock across every phase and sees valid data at more than two different latencies then calibration fails and this output is set to 1 Design Considerations This section discusses the design considerations for nonAFI designs Clocks and Resets The ALTMEMPHY megafunction automatically generates a PLL instance but you must still provide the reference clock input 11 ref c1k witha clock of the frequency that you specified in the MegaWizard interface An active low global reset input is also provided which you can de assert asynchronously The clock and reset management logic synchronizes this
72. ignal Name reset request n 1 aux half rate clk Type output output Width 1 Description Directly connected to the locked output of the PLL and is intended for optional use either by automated tools such as SOPC Builder or could be manually ANDed with any other system level signals and combined with any edge detect logic as required and then fed back to the global reset ninput Reset request output that indicates when the PLL outputs are not locked Use this as a reset request input to any system level reset controller you may have This signal is always low while the PLL is locking but not locked and so any reset logic using it is advised to detect a reset request on a falling edge rather than by level detection A ofthe phy 1 signal that you can use in other parts of your design same as phy c1k port aux full rate clk Note to Table 3 2 output A of the mem 1 2x signal that you can use in other parts of your design 1 Refer to Figure 4 3 for the reset mechanism in Arria GX Stratix Il and Stratix 11 GX devices The ports listed in Table 3 5 only exist when you target Stratix III and Stratix IV devices You can leave them unconnected if you are not using user mode calibrated OCT For more information about Stratix III and Stratix IV ports refer to ALTMEMPHY Signals section in chapter 5 of the DDR and DDR2 SDRAM High Performance Controllers and ALTMEMPHY IP Use
73. l Megafunction User Guide 3 12 Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals Table 3 4 External DLL Signals DDR2 and DDR SDRAM nonAFI clk Signal Name Type Width Description dqs_delay_ctrl_ output 6 Allows sharing DLL in this ALTMEMPHY instance with another export ALTMEMPHY instance Connect the dqs delay ctrl export port on the ALTMEMPHY instance with a DLL to the dqs delay ctrl import port on the other ALTMEMPHY instance dqs delay ctrl input 6 Allows the use of DLL in another ALTMEMPHY instance in this import ALTMEMPHY instance Connect the delay ctrl export port on the ALTMEMPHY instance with a DLL to the dqs delay ctrl import port on the other ALTMEMPHY instance dll reference output 1 Reference clock to feed to an externally instantiated DLL This clock is typically from one of the PHY PLL outputs The ports listed in Table 3 5 only exist when you target Stratix III and Stratix IV devices You can leave them unconnected if you are not using user mode calibrated OCT For more information about Stratix III and Stratix IV ports refer to ALTMEMPHY Signals section in chapter 5 of the DDR and DDR2 SDRAM High Performance Controllers and ALTMEMPHY IP User Guide Table 3 5 User Mode Calibrated OCT Control Signals for DDR2 DDR SDRAM nonAFI Note 1 2 Signal Name Type Width Description oct ctl rs value input 14 Specifies serial termination value
74. l device by clicking Modify parameters next to the Selected memory preset field External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide January 2010 Altera Corporation Chapter 2 Parameter Settings 2 3 Table 2 1 describes the General Settings available on the Memory Settings page of the ALTMEMPHY MegaWizard interface Table 2 1 General Settings Parameter Name Device family Description Targets device family The device family selected here must match the device family selected on MegaWizard page 2a Speed grade Selects a particular speed grade of the device for example 2 3 or 4 for the Stratix device family PLL reference clock frequency Determines the clock frequency of the external input clock to the PLL Ensure that you use three decimal points if the frequency is not a round number for example 166 667 MHz or 100 MHz to avoid a functional simulation or a PLL locking issue Memory clock frequency Determines the memory interface clock frequency If you are operating a memory device below its maximum achievable frequency ensure that you enter the actual frequency of operation rather than the maximum frequency achievable by the memory device Also ensure that you use three decimal points if the frequency is not a round number for example 333 333 MHz or 400 MHz to avoid a functional simulation or a PLL locking issue Controller data rate Local interface clock f
75. l mem rdata output LOCAL IF_ Thectl mem rdata Signal is the captured DWIDTH resynchronized and demultiplexed read data from ctl mem rdata valid output 1 the ALTMEMPHY megafunction to the controller cti mem rdata valid signal Indicates when the ct1_mem_rdata is valid For more information see Handshake Mechanism Between Read Commands and Read Data on page 3 47 External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals 3 19 Table 3 8 Datapath Interface for 0082 and DDR SDRAM nonAF Part of 3 Note 1 Note to Table 3 8 Signal Name Type Width Description ctl mem wdata input MEM IF The write data bus which has valid data in the same DWIDTHx clock cycles that control wdata validis DWIDTH asserted see Handshake Mechanism Between RATIO Read Commands and Read Data on page 3 47 ctl mem wdata valid input 1 Generates the mem dq output enable When asserted the 1 mem rdata valid signal indicates that the coincident read data on ctl mem rdata valid ctl mem we n h 1 input 1 The write enable signal from the controller to the memory Output during the high half period of the address and command clock and driven by the memory controller ctl mem we n 1 1 input 1 The write enable signal from the controller to the memory Output during
76. ler Table 3 11 1 0 Interface to QDR 1 00 II SRAM Note 1 Part 1 of 2 Signal Name Type Width Description mem addr output MEM IF ROWADDR Memory address bus WIDTH mem clk output MEM IF CLK PAIR Memory clock positive edge clock K _ COUNT mem clk n output MEM IF CLK PAIR Memory clock positive edge clock K 180 offset _ COUNT from mem 1 External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 21 ALTMEMPHY Signals Table 3 11 1 0 Interface to QDR II QDR II SRAM Note 1 Part 2 of 2 Signal Name Type Width Description mem_d output MEM IF DWIDTH Memory data bus D input to QDR SRAM device mem_dm output MEM IF DM WIDTH Memory write select BWS input to QDR Il SRAM device mem dq input MEM IF DWIDTH Memory data bus Q output from QDR II SRAM device mem dqs input MEM IF DWIDTH Memory read clock high bits CQ MEM IF PER DOS mem dqsn input MEM IF DWIDTH Memory read clock low bits CQn MEM IF PER DOS mem doff n output 1 Memory DLL disable control mem rps n output MEM IF CS WIDTH Memory read enable signal mem wps n output MEM IF CS WIDTH Memory write enable signal Note to Table 3 11 1 Connected to WYSIWYGS pad atoms Table 3 12 Clock and Reset Signals for QDR II QDR II SRA
77. logic consists of m DQand DQ output enable logic m DOS and DOS output enable logic m Data mask DM logic X9 II xnens pue J X9 eny 10 Woddng p 1 1 INvuas Chapter 4 Support for Arria GX HardCopy Il Stratix Il and Stratix Il GX Devices 4 9 DDR2 DDR SDRAM The memory controller interface outputs 4n bit wide data ct 1_wdata 4n at half rate frequency Figure 4 4 shows that the HDR write data ct 1_wdata 4n is clocked by the half rate clock phy 1 1x and is converted into SDR which is represented by wdp wdata h and wdp_wdata_1 and clocked by the full rate clock write clk 2x The DQ IOEs convert 2 n SDR bits to n DDR bits Figure 4 4 DDR2 DDR SDRAM Write Datapath in Arria GX HardCopy Stratix and Stratix Il GX Devices Stratix Il IOE Write Datapath OE DQ n wdp wdata h ctl wdata 4n phy clk 1x ctl wdata write_clk_2x write_clk_2x Address and Command Datapath The address and command datapath is responsible for taking the address and command outputs from the controller and converting them from half rate clock to full rate clock Two types of addressing are possible m 1T full rate The duration of the address and command is a single memory clock cycle 1 2 Figure 4 5 This applies to all address and comman
78. mory to the ALTMEMPHY megafunction to allow it to carry out its calibration process When the ALTMEMPHY megafunction has finished calibrating the memory controller asserts the 1 1 init done signal which shows that it has initialized the memory devices External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 7 Initialization Timing DDR2 SDRAM Initialization Timing The DDR2 SDRAM high performance controller initializes the memory devices by issuing the following command sequence m NOP for 200 us programmable PCH ELMR register 2 ELMER register ELMR register 1 LMR PCH ARF ARF LMR ELMR register 1 ELMR register 1 Figure 3 5 shows a typical DDR2 SDRAM initialization timing sequence which is described below The length of time between the reset and the clock enable signal going high should be 200 us The value that you choose for the Memory initialization time at power up tINIt setting in the MegaWizard interface is only used for hardware that you generate The controller simulation model is created with a much shorter twr time to make simulation easier Figure 3 5 DDR2 SDRAM Device Initialization Timing ek HH HH ddr cke 4 ddr_a 2 3 3 4 15 6 ddr_ba
79. n status interface Additional calibration signals from the sequencer 27 Ports with the prefix connect the PHY with the memory device ports with the prefix ct1_ connect the PHY with the controller Ports with prefix ct 1_mem_ indicate the datapath for the controller ports with the prefix local_ indicate the signal to be connected with the example driver or user logic Le Signals with suffix _n are active low signals without suffix _n are active high Table 3 1 1 0 Interface for DDR2 and DDR SDRAM nonAFI Note 1 Part 1 of 2 Signal Name Type Width Description mem addr output MEM IF ROWADDR WIDTH The memory row and column address bus mem ba output MEM IF BANKADDR WIDTH The memory bank address bus mem cas n output 1 The memory column address strobe mem cke output MEM IF CS WIDTH The memory clock enable mem clk bidir MEM IF CLK PAIR COUNT memory clock positive edge clock 2 mem clk n bidir MEM IF CLK PAIR COUNT The memory clock negative edge clock 2 mem cs n output MEM IF CS WIDTH The memory chip select signal mem dm output MEM IF DM WIDTH The optional memory data mask bus mem dq bidir MEM IF DWIDTH The memory bidirectional data bus mem dqs bidir MEM IF DWIDTH The memory bidirectional data strobe bus MEM IF DQ PER DOS January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide
80. nd changing them creates a new custom memory preset If you click Save As at the bottom left of the page and save the new settings in the quartus install dir NquartusNcommon ip altera Naltnemphy MibN directory you can use this new memory preset in other Quartus II projects created in the same version of the software When you click Save the new memory preset appears at the bottom of the Memory Presets list in the Memory Settings tab If you save the new settings in a directory other than the default directory click Load Preset in the Memory Settings tab to load the settings into the Memory Presets list External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 2 Parameter Settings QDR Il QDR II SRAM Preset Editor Page Figure 2 2 shows the Preset Editor page for the ALTMEMPHY variation for QDR II QDR II SRAM interfaces Figure 2 2 Preset Editor for QDR II QDR Il SRAM Interfaces 2 5 gt Parameter Categories Preset Editor Memory preset 8M x36 BL4 333MHz Category All Parameters Memory Attributes Memory Initialization Options Memory Timing Parameters Shaded parameters represent the defining characteristics of this memory device Modifying any of the shaded parameters will result in the creation of a custom preset Parameters Parameter Value Derate x18 timing for x36 emulation mode Disabled
81. nd latency If the ADD 1T parameter is set to EXT SELECT an extra cycle of latency can be dynamically inserted on the ODT command outputs by asserting the ct1 add 1t odt lat input This allows separate run time control of the latency of the ODT signal If ADD 1T is set to TRUE the extra clock cycle of latency is always present If ODT ADD 1T is set to FALSE the extra latency is never added January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 52 Chapter 3 Functional Description ALTMEMPHY nonAFI Design Considerations External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation 4 Support for Arria GX HardCopy Il ANU p AN Stratix and Stratix GX Devices The following sections describe the ALTMEMPHY megafunction support for Arria GX Stratix II and Stratix II GX devices 7 HardCopy II ASIC device support is similar to that of the Stratix II FPGA family However some design considerations are specific to the HardCopy II device family The ALTMEMPHY megafunction does not natively support a memory interface that spans on multiple sides of the device in these device families because the memory interface pins that are connected to the DLL are only available on the top and bottom of the device In silicon you can route the DLL control settings from one side of the device to anothe
82. nds and read data for the controller in a DDR2 DDR SDRAM interface For more information about the timing diagrams of a DDR2 SDRAM High Performance controller refer to the Timing Diagrams chapter in the DDR and DDR2 SDRAM High Performance Controllers and ALTMEMPHY IP User Guide The behavior of ct 1_ signals is the same as local_ signals during calibration These signals switch to 1ocal signals after calibration External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 43 Design Considerations Handshake Mechanism Between Read Commands and Read Data The controller generates a signal cC1 doing rd tothe ALTMEMPHY megafunction which is asserted for one phy c1k cycle for every read command it issues If there are two read commands the signal ct1 doing is asserted for two phy 1 cycles This signal also enables the capture registers and generates the ctl mem rdata valid signal This signal should be issued at the same time the read command is sent to the ALTMEMPHY megafunction refer to Figure 3 12 Figure 3 12 Read Commands and Read Data Half Rate Controller phy PHY Command Input DDR Command 1 RD NOP PCH RD NOP ctl mem cs h
83. nfiguration bus as a burst of phase changes without any read accesses In the example this calibration is setting on the capture clock phase so you would in a functional simulation expect a phase of around 90 to be selected 48 phase steps were reported during the generation and a burst of 10 PLL reconfigurations can be observed 360 48 10 75 Refer to Figure 3 10 on page 3 36 In Arria GX Stratix II and Stratix III devices calibration is performed on the resynchronization clock January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 14704 AHdIN3IALLTV Mowa euer 100107 wayyy 0102 Auenuer Figure 3 10 Calibration Phase Setting the Optimum Phase 9 5 wave default File Edit View Insert Format Tools Window Ie gg hax es 241 amp amp Dems 5 1053 2 0 m omes x mem_cs_n mem ras n 4 mem we n E Command n mem ba EX mem das mem dm 10E Capture 4 ray 0 0000000 1 1 UU DB local_refresh_teq 4 local CONTROL Input 4 contral doing rd ctl init done e clL ready control_rdata 2 control_rdata_valid control doing rd 4 control_wdata_valid contral_dqs_burst CONTROL I F
84. ntions The following table shows the typographic conventions that this document uses Visual Cue Bold Type with Initial Capital Letters Indicates command names dialog box titles dialog box options and other GUI labels For example Save As dialog box For GUI elements capitalization matches the GUI bold type Indicates directory names project names disk drive names file names file name extensions dialog box options software utility names and other GUI labels For example qdesigns directory d drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicates document titles For example AN 519 Stratix IV Design Guidelines Italic type Indicates variables For example n 1 Variable names are enclosed in angle brackets For example file name and project name pof file External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter Additional Information Typographic Conventions Info 3 Visual Cue Initial Capital Letters Indicates keyboard keys and menu names For example Delete key and the Options menu Subheading Title Quotation marks indicate references to sections within a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example da
85. om the controller to the WIDTH memory Output during the low half period of the address and command clock and driven by the memory controller ctl mem cs n h 1 input MEM IF CS Thechip select signal from the controller to the WIDTH memory For half rate designs always tie ctl mem cs n hhigh as even with 2T addressing the chip select is only driven for the second clock cycle to allow an extra clock cycle of setup time for the other address and command signals Output during the high half period of the address and command clock and driven by the memory controller ctl mem cs n 1 1 input MEM IF CS Thechip select signal from the controller to the WIDTH memory Output during the low half period of the address and command clock and driven by the memory controller ctl mem burst input 1 Controls the DQS output enables of the DQS pins ctl mem h 1 input MEM IF CS Theon die termination signal from the controller to WIDTH the memory ctl mem 1 1 input MEM IF CS Theon die termination signal from the controller to WIDTH the memory ctl mem ras nh 1 input 1 The row address strobe signal from the controller to the memory Output during the high half period of the address and command clock and driven by the memory controller ctl mem ras n 1 1 input 1 The row address strobe signal from the controller to the memory Output during the low half period of the address and command clock and driven by the memory controller ct
86. ommands see Figure 3 15 The first memory cycle is the write command and the second memory cycle is the NOP command Because of this arrangement you see a NOP command between the write commands 2 Assertion of the chip select signal The chip select signal is asserted along with the write command because of the 1T addressing 3 To support full rate the controller must provide the 1 mem dqs burst signal In full rate mode the PHY allows separates control of the DO and DQS output enables to support incomplete bursts For example if the memory burst length is four and the local side burst length is two you may ask for a write of length one To support this the controller must be able to enable the DOS outputs for the full memory burst length two clock cycles four 005 edges while only enabling the DQ outputs for the number of cycles that you requested one clock cycle two beats of data January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 50 Chapter 3 Functional Description ALTMEMPHY nonAFI Design Considerations Figure 3 15 Write Commands and Write Data Full Rate Controller PHY Command Input DDR Command 1 ctl mem addr h ctl mem cs n h ctl mem odt h PHY Write Data Input ctl mem wdata valid local write req ctl mem dgs burst mem dgqs ctl mem wdata 808bdae4ec55833a PHY Command Output
87. ontrol setup time to K clock rise tua 200 500 ps Address hold time to K clock rise tuc 200 500 ps Control hold time after K clock rise tsp 200 500 ps D setup time to K clock rise tup 200 500 ps D hold time to K clock rise 200 500 5 Echo clock high to data valid couox 200 500 ps Echo clock high to data invalid 1 0 2 000 5 Echo clock high to inverted echo clock high 1 0 2 000 5 Echo clock high Note to Table 2 5 1 This parameter is available for QDR 11 SRAM interfaces only Creating an Emulated x36 QDR 11 0 Il SRAM ALTMEMPHY Variation From software implementation point of view creating a x36 emulated QDR IL ODR SRAM interface is exactly the same as implementing an interface with two x18 QDR II QDR II SRAM devices In the Memory Settings page of the ALTMEMPHY MegaWizard interface select a x18 QDR IL ODR II SRAM with the same timing specifications as x36 QDR II QDR II SRAM device see Figure 2 3 For more information about x36 emulation for QDR IL ODR II SRAM interfaces refer to the Exceptions for x36 Emulated QDR II and QDR SRAM Interfaces in Arria II GX Stratix III and Stratix IV Devices section in Volume 2 Device Pin and Board Layout Guidelines of the External Memory Interface Handbook January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 2 8 Chapter 2 Parameter Settings Figure 2 3 Select a
88. parameter is setto EXT SELECT an extra cycle of latency can be dynamically inserted on the ODT command outputs by asserting the ctl add 1t odt lat input which allows separate run time control of the latency of the ODT signal If ODT ADD 1T is set to TRUE the extra clock cycle of latency is always present If ADD 1Tissetto FALSE the extra latency is never added 1 rlat output READ LAT WIDTH Unused port that exists when you target Stratix IV and Stratix devices The default READ LAT WIDTH S set to 4 l self rfsh ack input l powerdn ack input autopch req output l powerdn req output c c etl c c l self rfsh req output Signal from the Altera high performance controller that is passed through the PHY Note to Table 3 6 1 January 2010 Altera Corporation Interface signals to the controller either through the sequencer or user interface External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide 3 16 Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals Table 3 7 Local Interface Signals for DDR2 and DDR SDRAM nonAF Part 1 of 2 Note 1 Signal Name Type Width Description local address input LOCAL IF The address corresponding to a write or read AWIDTH request local be input LOCAL IF Theinputto ALTMEMPHY megafunction
89. plete control is handed back to the user logic and normal operation occurs The ALTMEMPHY megafunction auto calibration logic does not require any further access to the memory controller when the initial autocalibration is complete External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 5 Initialization Timing 2 The ALTMEMPHY controller local interface is the interface between the ALTMEMPHY megafunction and the controller local interface All the port names on this interface are prefixed with ct1 forexample ctl init done This interface connects the ALTMEMPHY megafunction to the controller s local interface and is of the same type as the local interface either an Avalon MM interface or a native interface When the calibration process is complete this connection becomes a straight through connection and you have complete control of the memory controller 3 The ALTMEMPHY controller command interface is the interface between the controller and ALTMEMPHY AII the ports on this interface are prefixed with ctl mem forexample ctl mem rdata They are clocked by the phy c1k This interface contains the memory control and address signals from the controller to the memory The controller also sends write data to and receives read data from the external memory through this interface All the signals on this interface are clocked at
90. r Guide Table 3 13 User Mode Calibrated OCT Control Signals for QDR II QDR II SRAM Note 1 2 Signal Name oct ctl rs value Type input Width Description 14 Specifies serial termination value Connects to the seriesterminationcontrol bus ofthe ALT OCT megafunction This port exists when you target Stratix IV and Stratix Ill devices only oct ctl rt value input 14 Specifies parallel termination value Connects to the parallelterminationcontrol bus ofthe ALT OCT megafunction This port exists when you target Stratix IV and Stratix devices only Notes to Table 3 5 1 These ports are available if you want to use user mode OCT calibration Otherwise they can be left unconnected 2 For more information on OCT see the ALT OCT Megafunction User Guide Table 3 14 Datapath Interface for QDR II QDR II SRAM Note 1 Part 1 of 2 Signal Name Type Width Description ctl mem addr h input MEM IF Write address from the controller to the external ROWADDR WIDTH memory ctl mem addr 1 input MEM IF Read address from the controller to the external ROWADDR WIDTH memory External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals 3 23 Table 3 14 Datapath Interface for QDR II QDR II SRAM Note 1 Part 2 of 2
91. r side of the device via local routing To perform local routing you must register the DLL control settings and to minimize the arrival skew of the DLL control settings at the other side of the device However this method has not been characterized and its performance is unknown Therefore this implementation is discouraged DDR2 DDR SDRAM Arria GX HardCopy IL Stratix II and Stratix II GX devices support both full rate and half rate DDR2 DDR SDRAM PHYs Half Rate Support The following section discusses half rate support for DDR2 DDR SDRAM for Arria GX HardCopy II Stratix II and Stratix II GX devices Read Datapath The read datapath logic is responsible for capturing data sent by the memory device and subsequently aligning the data back to the system clock domain The following functions are performed by the read datapath 1 Data capture and resynchronization 2 Data demultiplexing 3 Data alignment January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide 4 2 Chapter 4 Support for Arria GX HardCopy Il Stratix Il and Stratix II GX Devices DDR2 DDR SDRAM Figure 4 1 shows the order of the functions performed by the read datapath along with the frequency at which the read data is handled Figure 4 1 DDR2 DDR SDRAM Read Datapath in Arria GX HardCopy Stratix and Stratix II GX Devices DDR SDR SDR HDR Data Demux and Alignment Data Capture IOE
92. r the PHY Command Output label 3 The address and commands are of 2T period and the chip select is of 1T period mem clk 4 The data 9 at the memory interface is presented after three memory clock cycles of read latency The read latency is equal to the CAS latency For this example CAS latency is equal to three By default the read data from the memory bypasses the controller and is sent directly to the user logic If your controller requires access to the read data after it has been captured but before it is sent to the user interface for example to perform error detection and correction connect the 1 mem rdata and ctl mem rdata valid outputs from the ALTMEMPHY megafunction to your controller The controller must delay both ct1 mem rdata and ctl mem rdata valid signals by the same amount Connect the read data and valid outputs of your controller to the ct1_rdata ctl rdata validinputs of the ALTMEMPHY megafunction which passes straight through to the local_rdata and local rdata valid signals Handshake Mechanism Between Write Commands and Write Data The controller provides a signal 1 mem wdata valid tothe ALTMEMPHY megafunction to tell it when to enable the dq and mem output enables It is the controller s responsibility to control the relative timing of the memory command signals for example mem cas mem we the control mem wdata valid or control mem dqs burst signals
93. requency This field s value depends on the memory clock frequency and controller data rate and whether or Selects the data rate for the memory controller Sets the frequency of the controller to equal to either the memory interface frequency full rate or half of the memory interface frequency half rate not you turn on the Enable Half Rate Bridge option Local interface width not you turn on the Enable Half Rate Bridge option This field s value depends on the memory clock frequency and controller data rate and whether or Table 2 2 describes the options available to filter the Memory Presets that are displayed This section is where you indicate that you are creating a datapath for QDR II ODR II SRAM Table 2 2 Memory Presets List Parameter Name Description Memory type You can filter the type of memory to display For the ALTMEMPHY megafunction with nonAFI select QDR 1 SRAM and QDR II SRAM Memory vendor You can filter the memory types by vendor JEDEC is also one of the options allowing you to choose the JEDEC specifications If your chosen vendor is not listed you can choose Other for QDR I QDR SRAM interfaces Then pick a device that has similar specifications to your chosen device and check the values of each parameter Make sure you change the each parameter value to match your device specifications Memory format You can filter the type of memory by format for example components or
94. reset to the appropriate clock domains inside the ALTMEMPHY megafunction A clock output which is half the memory clock frequency for a half rate controller and the same as the memory clock for a full rate controller is provided phy clkoraux half rate 1 all inputs and outputs of the ALTMEMPHY megafunction are synchronous to this clock An active low synchronous reset is also provided reset phy clk n This reset phy clk nsignalis synchronously de asserted with respect to the phy c1k clock domain and can reset any additional user logic on that clock domain In addition there is a full rate clock aux full rate clk output available to use anywhere else in your design This clock is derived from the mem c1k 2x PLL output signal Calibration Process Requirements As the autocalibration logic makes use of the controller to perform its calibration you should follow these guidelines at power up When the global reset global reset 15 released the clock management logic waits for the PLL to lock and then releases the reset to the rest of the logic including the controller As the PLL locked output is gated inside the PLL for approximately the first 10 000 cycles by this time the PLL locked output is stable of the PLL reference clock there is no activity at this time When the reset to the controller reset phy clk is released the controller begins its normal memory initialization sequence When complete the controller indicate
95. ress and command outputs by asserting the ct1 add 1t ac lat input This allows run time control of the address and command latency If ADDR CMD ADD 1T is set to the string value TRUE the extra clock cycle of latency is always present and if it is set to the string value FALSE the extra latency is never added 7 TheADDR CMD ADD 1T parameter value is set in variation name phy v file and is passed on to project directory N variation name alt mem phy v file For DDR2 SDRAM interfaces using unbuffered DIMMs or components the value of ADDR CMD ADD 1T should be TRUE for odd CAS latencies CL3 or CL5 and FALSE for even CAS latencies CLA For registered DIMMs the value of ADDR CMD ADD 1T should be FALSE for odd CAS latencies CL3 or CL5 and TRUE for even CAS latencies CLA see Table 3 18 For DDR SDRAM interfaces the write latency is fixed at one cycle You should use the settings for CAS latencies see Table 3 18 Table 3 18 shows the setting of ADDR CMD ADD 17 for different values of CAS latency and DIMM settings Table 3 18 ADDR CMS ADD 1T Settings Memory and CL DIMM Type ADDR CMD ADD 1T Unbuffered TRUE DDR2 SDRAM CL3 Registered FALSE Unbuffered FALSE DDR2 SDRAM CL4 Registered TRUE Unbuffered TRUE DDR2 SDRAM CL5 Registered FALSE Unbuffered FALSE DDR SDRAM Registered TRUE The timing of the ODT signal can be controlled in the same way but is independent of the address and comma
96. s achieved using a dual port memory with a 2n bit wide write port operating on the resynchronization clock SDR and a 4n bit wide read port operating on the PHY clock HDR The basic principle of operation is that data is written to the memory at the SDR rate and read from the memory at the HDR rate while incrementing the read and write address pointers As the SDR and HDR clocks are generated the read and write pointers are continuously incremented by the same PLL and the 4n bit wide read data follows the 2n bit wide write data with a constant latency External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide January 2010 Altera Corporation Chapter 4 Support for Arria GX HardCopy Il Stratix Il and Stratix Il GX Devices 4 3 DDR2 DDR SDRAM Read Data Alignment Data alignment is the process controlled by the sequencer to ensure the correct captured read data is present in the same half rate clock cycle at the output of the read data DPRAM Data alignment is implemented using either M4K or M512K memory blocks The bottom of Figure 4 2 shows the concatenation of the read data into valid HDR data Postamble Protection The ALTMEMPHY megafunction provides the DQS postamble logic The postamble clock is derived from the resynchronization clock and is the negative edge of the resynchronization clock The ALTMEMPHY megafunction calibrates the resynchronization clock such that it is in the center of the data valid window
97. s the PLL reconfiguration block on a falling edge detection phy_clk output The ALTMEMPHY megafunction half rate clock provided to the user All user inputs and outputs to the ALTMEMPHY megafunction are synchronous to this clock in half rate designs However this clock is not used in full rate designs pll_ref_clk input The reference clock input to PLL reset phy clk n 1 output Asynchronous reset that is de asserted synchronously with respect to the associated phy clock clock domain Use this to reset any additional user logic on that clock domain reset request n 1 output Directly connected to the locked output of the PLL and is intended for optional use either by automated tools such as SOPC Builder or could be manually ANDed with any other system level signals and combined with any edge detect logic as required and then fed back to the global reset ninput Reset request output that indicates when the PLL outputs are not locked Use this as a reset request input to any system level reset controller you may have This signal is always low while the PLL is locking but not locked and so any reset logic using it is advised to detect a reset request on a falling edge rather than by level detection aux half rate clk External Memory PHY Interface ALTMEMPHY Megafunction User Guide output copy ofthe phy 1 signal that you can use in other parts of yo
98. s to the ALTMEMPHY megafunction that it is ready to accept the calibration writes and reads by asserting the ct1 init doneand ctl ready signals in DDR3 DDR2 DDR SDRAM interfaces There are no such signals in QDR IL ODR II SRAM interfaces as the SRAM device does not need an initialization sequence other than initializing the memory DLL The auto calibration logic then issues a series of writes and reads to the external memory You do not have access to the memory controller during this period When the autocalibration logic completes January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 42 Chapter 3 Functional Description ALTMEMPHY nonAFI Design Considerations its calibration the ALTMEMPHY megafunction asserts the 1 usr mode rdy resynchronization successful local init done and local ready signals in DDR3 DDR2 DDR SDRAM interfaces or 1 mode rdy and resynchronization successful signals in QDR II QDR II SRAM interfaces You then have complete control of the memory controller For more information about calibration process refer to the Calibration section in the DDR and DDR2 SDRAM High Performance Controllers and ALTMEMPHY IP User Guide Local Interface Requirements The autocalibration logic makes use of the controller to perform its calibration so your controller must observe the following requirements The controller must have at least one Avalon MM sla
99. stance is required the following signals may be added to the simulation pll reconfig pll reconfig counter param pll reconfig counter type pll reconfig data in pll reconfig enable pll reconfig read param pll reconfig soft reset en n pll reconfig write param January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 40 Chapter 3 Functional Description ALTMEMPHY nonAFI Additional Debug Signals pll reconfig busy B pll reconfig clk pll reconfig data out pll reconfig reset 57 For full description of the signals listed and their required operation refer to the respective Device Handbooks or Pliase Locked Loop Reconfiguration ALTPLL RECONFIG Megafunction User Guide L gt The output clock order is fixed in the ALTMEMPHY seq 11 select anda mapping takes place to align with the required clock port used for each different device family Refer to variation name phy alt mem phy v hd file and refer to the section that starts with the following code NB This lookup table shall be different for CIII SIII The PLL phasecounterselect is 3 bits wide therefore hardcode the output to 3 bits Calibration Status Interface The following calibration signals provide information for ALTMEMPHY megafunction ctl cal success indicates calibration success m ctl cal fail indicates calibration failure Additional Calibration Status Interface Sign
100. ta1 tdi and input Active low signals are denoted by suffix n For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESTGN and logic function names for example TRI 1 2 3 and a b c and so on Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure January 2010 Altera Corporation Hu Bullets indicate a list of items when the sequence of the items is not important c The hand points to information that requires special attention A caution calls attention to a condition or possible situation that can damage or CAUTION destroy the product or your work A warning calls attention to a condition or possible situation that can cause you WARNING injury The angled arrow instructs you to press Enter The feet direct you to more information about a particular topic External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide
101. te clk 2x C2 909 Full Rate Global This clock is for clocking and full rate the data out of the DDR 1 0 DDIO pins advance of the DQS strobe or equivalent As a result its phase leads that ofthe mem 2x by 90 January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 4 6 Chapter 4 Support for Arria GX HardCopy Il Stratix Il and Stratix II GX Devices DDR2 DDR SDRAM Table 4 1 DDR2 DDR SDRAM Clocking in Arria GX HardCopy Stratix Il and Stratix II GX Devices Part 2 of 2 Design Rate Half rate and full rate Clock Name mem clk ext 2x Postscale Counter C3 Phase Degrees 0 Clock Rate Full Rate Clock Network Type Dedicated Notes This clock is only used if the memory clock generation uses dedicated output pins Applicable only in HardCopy Il or Stratix prototyping for HardCopy Il designs Half rate and full rate resync clk 2x C4 Calibrated Full Rate Regional Clocks the resynchronization registers after the capture registers Its phase is adjusted to the center of the data valid window across all the DQS clocked DDIO groups Half rate and full rate Half rate and full rate measure clk 2x ac clk 2x C5 Calibrated 90 180 270 Full Rate Full Rate Regional 2 Global This clock is for VT tracking This free running clo
102. ternal Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 14704 AHdIN3IALLTV Mowa euer uolyesodiog gay OLOZ Auenuer Figure 3 7 DDR2 SDRAM Simulation Initialization Phase wave default File Edit Insert Format Tools Window Uses Be esam 4 7006 5 4 clock_source 1 Test Logic 4 esl complete EA pnf_per_byte pnt DDR SDRAM I F B BA EX mem B EX addr mem_cas_n mem_we_n Command mem_local_wdata tmem_local_be mem_local_size local_wdata_req local_teftesh_teq s n 4 4 8 4 5 Cursor 3 2 en a ccc TRITT TUTTI 00800 n gt 200121383 ps to 203394388 ps Now 268 127 501 ps Delta 16 140950811 pue euj uoienuiis jeuonoun iqyuou 1W Uondiiosag jeuorun 0 amp Chapter 3 Functional Description ALTMEMPHY nonAFI 3 31 Functional Simulation the ModelSim Wave and Transcript Window Write Training Data Stage As shown in Figure 3 8 on page 3 32 following memory initialization the write data training stage is closely followed by the first read data calibration read sample January 20
103. the resynchronization clock phasing upwards tracking adjustment output 1 Active high signal that is pulsed to indicate that the mimic path tracking has adjusted the resynchronization clock phasing downwards External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 20 Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals Table 3 10 shows additional calibration status signal outputs from the sequencer You can either pull these signals out to the top level or observe them through the SignalTap II logic analyzer Table 3 10 Additional Calibration Status Signals nonAFI Signal rsu codvw phase Center of data valid window Description The ALTMEMPHY resynchronization setup unit RSU sweeps the phase of a resynchronization clock across 360 full rate designs or 720 half rate designs of a memory clock cycle Data reads from the DIMM are performed for each phase position and a data valid window is located which is the set of resynchronization clock phase positions where data is successfully read The final resynchronization clock phase is set at the center of this range the center of the data valid window CODVW This output is set to the current calculated value for the CODVW and represents how many phase steps were performed by the PLL to offset the resynchronization clock from the memory clock rsu read latency Read latency at the center of the window If the
104. the device handbook for your target device family Reset Management The reset management block is responsible for the following m Provides appropriately timed resets to the ALTMEMPHY megafunction datapaths and functional modules m Performs the reset sequencing required for different clock domains m Provides reset management of PLL and PLL reconfiguration functions m Manages any circuit specific reset sequencing Each reset is an asynchronous assert and synchronous de assert on the appropriate clock domain The reset management design uses a standard two register synchronizer to avoid metastability A unique reset metastability protection circuit for the clock divider circuit is required because the phy c1k domain reset metastability protection flipflops have fan in from the soft reset ninput and so these registers cannot be used Figure 4 3 shows the ALTMEMPHY reset management block for Arria GX HardCopy Stratix IL and Stratix GX devices The p11 ref 1 signal goes directly to the PLL eliminating the need for global clock network routing If you are using the p11 ref 1 signal to feed other parts of your design you must use global clock network for the signal If p11 reconfig soft reset enis held low the PLL reconfig is not reset during a soft reset which allows designs targeting HardCopy II devices to hold the PHY in reset while still accessing the PLL reconfig block However designs targeting Arria GX or Stratix II d
105. the low half period of the address and command clock and driven by the memory controller 1 The n and 1 stand for high and low They signify in which half of the clock cycle the data is output The n data is output when the corresponding clock for example 2x ishigh The 1 data is output when the 2x clock is low The signals with n and _1 allow you to select between 1T and 2T addressing For half rate designs 1T is where the address and command signals are driven for one clock 2T is where they are driven for 2 clocks For full rate designs ensure the same signal drives both h and 1 signals and 2T addressing is used Also when high performance controllers use ALTMEMPHY 2T addressing is used Table 3 9 Calibration Status Interface for DDR2 and DDR SDRAM nonAFI down January 2010 Altera Corporation Signal Name Type Width Description resynchronisation output 1 Active high signal that is set to indicate that successful calibration of the read data resynchronization clock phase was completed and successful postamble successful output 1 Active high signal that is set to indicate that read postamble calibration was completed tracking successful output 1 Active high signal that is set to indicate the completion of mimic path VT variation tracking operation tracking adjustment output 1 Active high signal that is pulsed to indicate that the up mimic path tracking has adjusted
106. the phy c1k rate The ALTMEMPHY megafunction converts between this clock and the memory interface clock 4 The fourth interface is between the ALTMEMPHY megafunction and the external memory devices and consists of the memory address command and data pins These must be connected directly to the external pins of your Altera FPGA Initialization Timing DDR SDRAM initialization timing is different to DDR2 SDRAM initialization timing DDR SDRAM Initialization Timing S e For DDR2 SDRAM initialization timing see DDR2 SDRAM Initialization Timing on page 3 7 The DDR SDRAM high performance controller initializes the SDRAM devices by issuing the following memory command sequence m NOP for 200 us programmable PCH Extended LMR ELMR LMR NOP for 200 clock cycles fixed PCH ARF ARF LMR Figure 3 4 on page 3 6 shows a typical initialization timing sequence The length of time between the reset and the first PCH command should be 200 us The value that you specify for the Memory initialization time at power up tINIt setting in the MegaWizard interface is only used for hardware that you generate The controller simulation model is created with a much shorter tj time to make simulation easier January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 3 6 Chapter 3 Functional Description ALTMEMPHY nonAFI Initialization Timing gt Do not set tINIT to zero
107. ume 3 Implementing Altera Memory Interface IP of the External Memory Interface Handbook The ALTMEMPHY Parameter Settings page in the ALTMEMPHY MegaWizard interface Figure 2 1 allows you to parameterize the following settings m Memory Settings m PHY Settings m Controller Interface Settings L The options for PHY Settings tab are editable if they apply to the Altera device that you have chosen for your interface Otherwise the options are disabled The options for Controller Interface Settings tab are disabled when you are creating an ALTMEMPHY nonAFI megafunction for QDR IL ODR II SRAM interface lt For more information about the PHY Settings and the Controller Interface Settings refer to the Parameter Settings chapter in Volume 3 Implementing Altera Memory Interface IP of the External Memory Interface Handbook January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide Chapter 2 Parameter Settings Figure 2 1 ALTMEMPHY Parameter Settings Page MegaWizard Plug In Manager ALTMEMPHY 4 ALTMEMPHY Device family Speed grade PLL reference clock frequency MHz 10000 ps Memory clock frequency END 1 MHz 5000 ps Local interface clock frequency E 100 0 MHz Local interface width Show in Memory Presets List Memory Presets E Parameter Value e Presets Memory type GDRI SRAM Memory vendor Other 512k x36 BL4 CL2 5 400Mhz
108. unction combination It performs a series of writes to the external memory followed by a series of reads to the same locations and compares the read and write data This comparison results in dynamic pass not fail per byte pnf per byte signals and a latched combined pass not fail pnf 1 pass 0 fail signal Each completed series of writes and reads is signaled via the test complete signal and then the test repeats The example testbench stops when either complete is asserted or when 200 000 mem c1k cycles after the time In Figure 3 11 on page 3 38 the series of writes followed by reads can be seen on both the local and memory interfaces together with the test complete signals As the data written to the memory is simply an LFSR pattern the example driver is able to generate expected read data from the memory to compare with that previously written to the same address The data on the read data bus should match that on the write data bus during the read process January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFl Megafunction User Guide 14704 AHdIN3IALLTV Mowa euer 100107 wayyy OLOZ Auenuer Figure 3 11 Functional Memory Use Stage v wave default Sees File Edit View Insert Format Tools Window Osuus esanti H hA xli 24i A QAI 4 clock source
109. ur design same as phy c1k port January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI ALTMEMPHY Signals 3 11 Table 3 2 Clock and Reset Signals for DDR2 DDR SDRAM nonAFl Note 1 Part 2 of 2 Signal Name aux full rate clk Type output Width 1 Description A of the mem 1 2x signal that you can use in other parts of your design Note to Table 3 2 1 Refer to Figure 4 3 for the reset mechanism in Arria GX Cyclone III Stratix II and Stratix II GX devices The ports in Table 3 3 exists for all DDR2 DDR SDRAM variations Table 3 3 PLL Reconfiguration Signals for DDR2 and DDR SDRAM nonAFI reset Signal Name Type Width Description pll_reconfig_ input 1 Allows access to the PLL reconfiguration block Hold this enable signal low in normal operation While the ALTMEMPHY is held in reset viathe soft_reset_n signal and the reset_request_n Signal is 1 it is safe to reconfigure the PLL To reconfigure the PLL set this signal to 1 and use the other p11 recon fig signals to access the PLL When finished reconfiguring set this signal to 0 and then set the soft_reset_n signal to 1 to bring the ALTMEMPHY out of reset For this signal to work the PLL RECONFIG PORTS EN parameter must be set to TRUE pll reconfig input 1 For more information refer to the Phase Locked Loop write param ALTPLL RECONFIG
110. ve interface or a native interface which the ALTMEMPHY megafunction can control during the initial calibration process For DDR3 SDRAM and QDR IL ODR II SRAM variations of the ALTMEMPHY megafunction only the Avalon MM local interface is supported When calibration is complete no further access to this interface is required by the ALTMEMPHY megafunction The memory burst length can be two four or eight for DDR SDRAM devices the memory burst length can be four or eight for DDR2 SDRAM devices DDR3 SDRAM burst lengths can be set at either four or eight when using the Altera high performance controller The QDR IL ODR II SRAM variations of the ALTMEMPHY megafunction only support burst length of four For a half rate controller the memory clock runs twice as fast as the clock provided to the local interface so data buses on the local interface are four times as wide as the memory data bus For a full rate controller the memory clock runs at the same speed as the clock provided to the local interface so the data buses on the local interface are two times as wide as the memory data bus Each read or write request on the local interface fits into a single memory read or write command on the memory interface simplifying the controller design 57 The ALTMEMPHY megafunction with the nonAFI does not support burst lengths of eight DDR2 DDR SDRAM Half Rate Controller The following sections describe the handshake mechanism between the read comma
111. wo memory clock cycles The ALTMEMPHY megafunction allows you to dynamically insert an extra memory clock of delay in the address and command path to compensate The insertion of delay is controlled by the ADDR CMD ADD 1T parameter and the ctl add 1t ac lat signal If ADDR CMD ADD 1715 set to the string EXT SELECT an extra cycle of latency can be dynamically inserted on the address and command outputs by asserting the 1 add 1t ac lat input which allows run time control of the address and command latency If ADDR_CMD ADD 1T iS set to the string value TRUE the extra clock cycle of latency is always present If it is set to the string value FALSE the extra latency is never added ctl add intermediate Input 1 When asserted an additional intermediate register or regs registers is included in the address and command path if the ADDR CMD ADD INTERMEDIATE REGS parameter is set to EXT SELECT For Stratix II and Cyclone III devices only to maintain the clock cycle relationship between address command and the write data You must include the address command phases where required ctl address output LOCAL IF The address corresponding to a write or read request The ALTMEMPHY sequencer logic drives ctl address during calibration ctl_address has the same timing as 1ocal address AWIDTH ctl be output LOCAL IF The output to the controller indicating the DWIDTH 8 byte enable flags The ALTMEMPHY sequencer logic
112. xes each module uses for nonAFI variations 57 Altera recommends that you use the AFI for new designs only use the nonAFI for existing designs QDR II QDR Il SRAM Calibration Process gt This section describes the calibration process for QDR II QDR II SRAM interfaces only For information about the calibration process for DDR2 and DDR SDRAM refer to the Calibration section in the DDR and DDR2 SDRAM High Performance Controllers ALTMEMPHY IP User Guide The calibration process of a QDR IL ODR II SRAM device is considerably simpler than that of a calibration process for a DDR2 DDR SDRAM device The calibration process involves selecting the right phase of the resynchronization clock to capture the read data at half rate Figure 3 1 shows the generation of the resynchronization clock which then clocks the HDR registers in the IOE During calibration the sequencer determines whether to use the half rate clock or the inverted half rate clock to capture the half rate data Figure 3 1 Resynchronization Clock in QDR II QDR II SRAM ALTMEMPHY Megafunction Input from Sequencer Shift Register Half Rate Data January 2010 Altera Corporation External Memory PHY Interface ALTMEMPHY nonAFI Megafunction User Guide 3 2 Chapter 3 Functional Description ALTMEMPHY nonAFI QDR II QDR II SRAM Calibration Process The clock CQ coming from the OD
113. y device The number of DQS pins in the interface M IF BANKADDR WIDTH M IF CS WIDTH The number of chip select pins in the interface The sequencer only calibrates one chip The bank address with the memory device not used in QDR II QDR II SRAM variations select pin EM IF DM WIDTH The number of mem dm pins on the memory interface M IF PER DQS The number of mem pins per mem dgqs pin M IF CLK PAIR COUNT The number of mem c1k mem pairs in the interface M M M R EAD LAT WIDTH The bus width for the ct 1_rlat signal used in QDR II QDR SRAM PHY that determines the read latency of your system External Memory PHY Interface ALTMEMPHY Megafunction User Guide January 2010 Altera Corporation Chapter 3 Functional Description ALTMEMPHY nonAFI 3 25 Understanding the Testbench Understanding the Testbench Before the user logic example driver can read or write to the local interface the external SDRAM must first be initialized and calibrated Following power up or a reset event the following stages of operation take place m PLL initialization and lock m Memory device initialization m Interface training and calibration m Write training data m Calibration m Functional memory use PLL Initialization and Lock PLL initialization and lock is the first activity that takes place an

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