10 Gig Ethernet MAC User Guide
Contents
1. Enable Receive Padding Remove When enabled Frames are provided on the Client H Boolean Interface without padding when disabled True g Frames are provided on the Client Interface with padding Enable CRC Forwarding When selected CRC MAC CONFIG Forward CRC Boolean is passed transparently from the Transmit Client False Interface to line and is preserved on the Received Client Interface MAC CONFIG Transmit IPG Integer Transmit Inter Packet Gap Defined in Bytes 12 Length the IPG between transmitted Frames Han Stratix II GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 Table 5 Testbuilder Simulation Control Testbuilder Panel Option Description Compile Database before e Simulation VHDL configuration options The option must be enabled at least once new Core database was generated When enabled the Core simulation database is refreshed with the Core after a EE the Testbuilder panel ignored Previous configuration used When selected starts the RTL simulation with all the options defined in When selected the options defined on the Testbuilder panel are saved Sana omon before the RTL simulation is performed Run Gate Level When selected the options defined on the Testbuilder panel are saved before the Gate level simulation is performed When running a simulation a set of waveforms is displayed error and information messages2. RN de device deg devi RN de zone den cn Package n Men pl Package en a Pastapa e ipii Package wio F n siepi Package miomo Peckege mip tem Pi Figure 4 Running Testbuilder Overview Important note The system variable QUARTUS_ROOTDIR should be set to the Quartus software installation directory so that the Altera libraries can be linked during RTL or Gate level simulations Testbuilder Options A single VHDL configuration file configures the Testbench e source package vhdl mtip_sim_pack vhd The file can be modified to implement different simulation scenarios To ease the configuration a graphical tool TestBuilder is provided that modifies the configuration file TestBuilder is a TCL TK extension written for the ModelSim Simulator which is fully integrated in the ModelSim framework MIB Stratix II GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 Core 2222 2 YCE Mon Frame Generation at clocks _ Configuration MAC CONFIG Transmit FIFO Section Empty Threshold 16 MAC CONFIG Transmit FIFO Section Full Threshold fi 6 MAC CONFIG Receive FIFO Section Empty Threshold fo MAC CONFIG Receive FIFO Section Full Threshold fi 6 MAC CONFIG Enable Auto Negotiation I i MAC CONFIG Ignore Pause Frames D MAC CONFIG Remove Frame Padding M i MAC CONFIG Foward CRE M Modelsim i Control SSeS EE EE E SSS S2S SS SSS SSS e E E E Run Ga
3. 1 408 544 7000 service 7 00 a m to 5 00 p m GMT 8 00 Pacific Time FTP site ftp altera com ftp altera com MorethanIP E Mail info morethanip com Internet www morethanip com Europe Muenchner Strasse 199 D 85757 Karlsfeld Germany Tel 49 0 8131 333939 0 FAX 49 0 8131 333939 1 7 00 a m to 5 00 p m GMT 8 00
4. Stratix II GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 Enable CRC Forwarding When selected CRC TB CRC FWD Boolean is passed transparently from the Transmit Client Interface to line and is preserved on the Faba Received Client Interface TB_IPG_LEN Integer Transmit Inter Packet Gap Defined in Bytes 12 the IPG between transmitted Frames 3 7 Design Implementation with Quartus Il Two TCL script quartus tc1 is provided in the design kit directory quartus which performs the following actions Create project Build database Set timing constraints Set I O Fast Register constraint on fast I O signals Run Quartus fitter Reports design timing and timing violations Pl OP OR ee Gor NS Generates VHO VHDL gate level netlist and SDO timing file used during Gate level simulation The TCL script can run from the Quartus II graphical interface or in batch mode e Graphical Mode 1 In Quartus Il TCL console Change to Quartus working directory cd lt Design Kit Root gt quartus 2 Run the design TCL script source quartus tcl 3 8 VQM Netlist Generation After you obtain a core license from Altera a VQM netlist of the Core can be generated with the Quartus II software The VQM netlist can be used to integrate the Core in a customer design To create the VQM netlist 1 Analyze and Synthesize the Core 2 Generate the VQM Netlist Han Stratix II GX Embedded Gigabit
5. from Altera the VQM netlist cannot be generated and an error message will appear You can disregard this message as it will not prevent you from running RTL simulation 3 9 Full Timing Gate Level Simulation The gate level verification is performed using Quartus Il VHDL output files Structural VHDL and SDF timing files in the directory quartus simulation To run the gate level simulation with Modelsim use as described in chapters 3 5 and following A gate level simulation when the Testbuilder simulation option Run Gate Level is used With a Modelsim PE or Modelsim AE run the script gate do do gate do 17 ral 4 Contact Altera Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 For the most up to date information about Altera products go to the Altera world wide web site at www altera com For technical support on this product go to www altera com mysupport For additional information about Altera products consult the sources shown below Information Type Technical support USA amp Canada www altera com mysupport All Other Locations www altera com mysupport 800 800 EPLD 3753 7 00 a m to 5 00 p m Pacific Time 1 408 544 8767 Pacific Time Product literature www altera com www altera com Altera literature services literature altera com literature altera com Non technical customer 800 767 3753
6. gap IGP used by the Ethernet Frame generator when generating frames to the RX PHY interface 12 TB_LENSTART Bytes Defines the payload length of the first frame generated by the Ethernet and FIFO models 100 TB_LENSTEP Bytes Frame payload length increment During simulation frames are generated starting from length of first frame incrementing with each frame generated TB_LENMAX Bytes Defines the payload maximum length used by the Ethernet Generator models This value specifies the wrap around for the frame length of generated frames l e if the frame length increment would exceed this value it wraps around to zero Can be used to test frame length error detection when set to any value larger than the MAC length configuration 1500 TB_ENA_PADDING Boolean If enabled RX PHY Generator model generated frames are padded to 64 octets in length normal mode If disabled no padding occurs and erroneous frames will be sent to the MAC RX True TB_ENA_VLAN Boolean If enabled all frames sent received will be VLAN type of frames False TB_STOPREAD Frames Inhibits the Testbench RX FIFO monitor reading the RX FIFO after this amount of frames has been sent to the RX Can be used to test Flow Control behaviour If more frames are received the FIFO will get filled When the threshold level is reached a Pause Frame will be generated by the MAC TX If set to 0 the RX FIF
7. set simulation options compile the complete design and run the simulation process To start Testbuilder in the Modelsim command window 1 Change to Modelsim working directory cd lt Design Kit Root gt simulation 2 Run the Modelsim macro do testbuilder do Han Stratix II GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 TestBuilder D tmp estrxii simulation ll x Number of Frames in RX path O loopback TX 5 Number of Frames in TX path 5 IPG in RX path bytes 12 Length of first frame 100 Frame length increment 1 Generated Frames Maximum Payload length 1500 Enable padding of frames in RX path by PHY Model WM Generate VLAN frame every frames 0 Stop RX FIFO read after frames 10 Restart RX FIFO read after clocks 10 Generate Frames with Errors on Transmit FIFO Interface I Testbench reacts on Pause Frames if not in loopback JW MAC CONFIG Transmit FIFO Section Empty Threshold 16 MAC CONFIG Transmit FIFO Section Full Threshold 16 MAC CONFIG Receive FIFO Section Empty Threshold 0 MAC CONFIG Receive FIFO Section Full Threshold 16 MAC CONFIG Enable Auto Negotiation I Compile database before simulation HDL I Run Gate Level Run Simulation only Configure and Start Simulation Fle Edt View Coole Semuiste Took Window Hep sasj sonrs emm AN on strenge RN on rn sic ToPo Debuggs NV er ethgenerato Nier steerget CET
8. 0 Dererge Fuer with Encs on Trane FIFO Intectsce T Tesbench reacts on Pause Frames H zl mlocpbeck E Testbench MAC CONFIG Receive NIFO Section Empty Tech 5 MAC CONFIG Receive FIFO Sexton Ful Threshold 16 Simulation Control ModelSim User Constraints na e Configuration VHDL Constraint VHDL MAC CONFIG Tranen FFD Section Ful Thesteld 16 Testbench Template Design FILES Quartus Figure 1 Design Flow Overview Han Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 3 2 Core Configuration Options The Core is fully configurable and a user friendly GUI is provided to simplify configuration To optimize the core for the intended application environment several options are available which can be modified before the actual database is generated as described before Mj etherPack File Select Documentation Help Altera Stratix Il Gx Y Core Module Options Maximum Frame Length 11522 1518 16000 Pause Frame Quanta 1000 0 65535 Enable Promiscuous Receive Mode IV Insert MAC Address on transmit TX FIFO 64 x 6 RX FIFO 64 x 6 r Block Diagram Coniguration Generate HDL Figure 2 MAC Core Configuration Panel Han Stratix II GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 Table 1 Core Configuration Options Option Description Technology T
9. Ethernet MAC PHY User s Guide Version 1 0 October 2005 X Quartus II D tmp estrxii quartus embedded_gige_mac_phy embedded_gige_mac_phy Compilation Report Flow Summary Fie Edit View Project Assignments Processing Tools Window Help osajsj s majo Dapre n Igglo rs b O O a Project Navigator Start Compilation col Ee EE Entity PA Analyze Current Eile o embedded_gige_mac_phy JE Compilation Report Clap E Start Analysis amp Synthesis Ctrl K Start Compilation amp Simulation Ctrl Shift K E SE Eeer Fa Start Timing Analyzer Ctrl Shift L E Start Simulation Olai a E SS SE Simulation Debug gt E simulation Report enema CEES see 9 Start PowerPlay Power Analyzer Ctri Shift P E start Software Build Ctr Q K Start SignalProbe Compilation Ctrl Shift 5 F gt Start UO Assignment Analysis Start Timing Analyzer Fast Timing Model Start Early Timing Estimate Start Timing Constraint Check Start Check amp Save All Netlist Changes Start Partition Merge Compile Current File Start Equation Writer Post fitting Start Test Bench Template Writer K Start EDA Synthesis Start EDA Physical Synthesis Figure 6 VQM Netlist Generation The VQM Netlist embedded_gige_mac_phy vam is created in the directory quartus atom_netlists Note Without the free license
10. Han Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 Stratix ll GX Embedded Gigabit Ethernet MAC PHY User s Guide Han Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 Contents 1 DESIGN KIT INSTALLA ION sasasnsnunnnnnnnnnnnunnnunununnnnnnnunnnunununununnnunnnunn nunun nnn nnn nn nnnm n nnmnnn nnmnnn nnmnnn 3 1 1 PLATFORM SPECIFIC JAVA RUNTIME INSTALLATION cccccccceeeeececccccsceseeeeececeeeeueeaueeeeeeeeeeeeanenensees 3 1 2 DESIGN KIT INSTALLATION cccccccccccccceeeeececcceseceseeeeesecceseuceaueessceseeuseaueaseseeeeeeaueuseeeeeseuaeaneaseeeness 3 2 DESIGN FE e UE 4 3 GENERATING THE MAC PHY CORE ccccsscccecesccccsssseeseeeeeseansessseeesuseouansuseseuueneeausesesuenaeanaass 5 Sch AV l NN ee ee 5 3 2 CORE CONFIGURATION OPTIONS cccccccccccceseecececececeseeeeeecceeesceaueeseceseeusuauaaeessceeeeuseaueueseeeseeananeess 6 3 3 DESIGN KT DATABASE ee edel geg Eed ageet 7 3 4 SIMULATION NWIBONMENT ttnn tn knnt annann Enn AA EAEE EE REAREA EEEE ARAA EE EEEE nanen Ennen ne 7 3 5 RUNNING SIMULATION USING MODELSIM SE 8 Wellesteen 8 TeStbuilder EC IEHIEHeegbeee geegent deed 9 3 6 RUNNING SIMULATION USING MODELSIM PE OR MODELSIM Ak 13 Ee TEE 13 SUMUMALIOM OPTIONS isanne aaen ea aeaaeae aiaa A SEEE E aAa E A U TAREA ell 13 3 7 DESIGN IMPLEMENTATION WITH QUARTUS l oo cecccccc cece eeeececeeeesce sees eeceeeeeesaea
11. O read is never paused TB_HOLDREAD RX FIFO clocks Number of clock cycles the RX FIFO should not be read after it has been stopped Only relevant if the previous configuration read stop was set to a non null value After this number of RX FIFO clock cycles the RX FIFO will be emptied again 10 TB_TX_FF_ERR Boolean Enable Transmit Error Generation the Core Transmit Interface When selected the transmit FIFO signal _tx_err is asserted with ff_tx_eop to signal an Error When disabled the FIFO error is signalled _tx_err is never setto l False TB_PAUSECONTROL Boolean If enabled true the Testbench will stop the RX PHY Frame generator if the MAC sends a True Han Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 Pause Frame This simulates a usual flow control chain correctly If disabled False Pause Frames sent by the MAC are ignored by the Testbench and the RX PHY Frame generator will never pause This can be used to test the MACs FIFO overflow behavior This option has no effect if loopback mode is enabled i e Frame generation in RX path is set 0 TB_TRIGGERXOFF Integer XOFF Pause Frame Generation Set the time for to generate a XOFF Frame with the Core command pin xoff_gen When set to 0 XOFF Frame generation is disabled TB_TRIGGERXON Integer XON Pause Frame Generation Set th
12. are issued in the Modelsim standard output 3 6 Running Simulation Using Modelsim PE or Modelsim AE Overview Modifying the file mt ip_sim_pack vhd located in the directory source package vhdl creates a custom simulation scenario The Core files and dependencies are available in the file comp do In Directory simulation the testbench file and simulation models files are liste in the file sim do The files comp do and sim do should be modified and adapted with the simulator command Once a scenario has been created the following steps should be followed 1 Change to the simulation directory 2 Compile the Core database e do comp do 3 Compile the Simulation database and run simulation e do sim do Simulation Options The simulation is controlled and is configured with a set of parameters set in the file mtip_sim_pack vhd Table 6 Simulation Options d If set to 0 a Serdes loopback test is performed with the Core pin loop_ena set to 1 Option Unit Description Default Sets the number of frames that are generated by the Ethernet frame Generator connected to the TB RXFRAMES Frames Receive PHY interface 5 Han Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 TB_TXFRAMES Frames Sets the number of frames that are generated by the frame Generator connected to the Core transmit FIFO interface TB_RXIPG Bytes Sets the inter packet
13. e time for to generate a XON Frame with the Core command pin xon_gen When set to 0 XON Frame generation is disabled Table 7 MAC Configuration Options Option Unit Description Default TX_FIFO_SE Integer Set the Transmit FIFO Section empty threshold to any value between 0 and 63 Maximum memory depth 16 TX_FIFO_SF Integer Set the Transmit FIFO Section full threshold to any value between 0 and 63 Maximum memory depth 16 RX_FIFO_SE Integer Set the Receive FIFO Section empty threshold to any value between 0 and 63 Maximum memory depth RX_FIFO_SF Integer Set the Receive FIFO Section full threshold to any value between 0 and 63 Maximum memory depth 16 TB_ENA_AUTONEG Boolean Enable Auto Negotiation When selected the Core performs auto negotiation to check the link with the Link Partner before simulation starts After simulation the Auto Negotiation is restarted with the Core signal an_enable set to 0 When disabled non Auto Negotiation is performed True TB_IGNORE_PAUSE Boolean Ignore Pause Frames When enabled received Pause Frames are ignored when disable Pause Frames are decoded False TB_PAD_ENA Boolean Enable Receive Padding Remove When enabled Frames are provided on the Client Interface without padding when disabled Frames are provided on the Client Interface with padding True Han
14. es the payload length of the first frame 100 generated by the Ethernet and FIFO models Unit Description Default ral Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 Frame length increment Bytes Frame payload length increment During simulation frames are generated starting from length of first frame incrementing with each frame generated Generated Frames max payload length Bytes Defines the payload maximum length used by the Ethernet Generator models This value specifies the wrap around for the frame length of generated frames l e if the frame length increment would exceed this value it wraps around to zero Can be used to test frame length error detection when set to any value larger than the MAC length configuration 1500 Enable Padding of Frames in RX Path Boolean If enabled RX PHY Generator model generated frames are padded to 64 octets in length normal mode If disabled no padding occurs and erroneous frames will be sent to the MAC RX True Enable VLAN frames for all tests Boolean If enabled all frames sent received will be VLAN type of frames False Stop RX FIFO read after Frames Inhibits the Testbench RX FIFO monitor reading the RX FIFO after this amount of frames has been sent to the RX Can be used to test Flow Control behaviour If more frames are received the FIFO will get filled When the thre
15. he Core is optimized for Altera Stratix II GX devices Maximum Frame Length Maximum Frame Length Defines a 14 Bit maximum frame length used by the MAC receive logic to check frames Pause Frame Quanta Receive Pause Quanta 16 Bit value sets in increment of 512 Ethernet bit times the pause quanta used in each Pause Frame sent to the remote Ethernet device Enable Promiscuous Receive Mode When selected all frames are received without Unicast address filtering Insert MAC Address on Transmit If select the MAC overwrites the source MAC address with the MAC set on the Core signal mac_adadr If disabled the source MAC address received from the transmit application transmitted is not modified by the MAC 3 3 Design Kit Database Table 2 Design Kit Directory Structure Directory Description models Ethernet Frame generator and monitor models Gene Contains the netist for Altera Stratix implementation and a script q to control the Altera Quartus design software sim lation Scripts to configure and execute RTL and Gate Level Simulation as well the Modelsim integrated TestBuilder source Encrypted VHDL design source files testbench and configuration files 3 4 Simulation Environment A complete testbench is provided File testbench vhd in directory source testbench vhdl which implements the Core together with a simulation control state machine and the following drivers and monito
16. me for Force Xoff Frame Generation integer to generate a XOFF Frame with the Core 0 at clocks 9 command pin xoff_gen When set to 0 XOFF Frame generation is disabled XON Pause Frame Generation Set the time for to Force Xon Frame Generation int g r generate a XON Frame with the Core command 0 at clocks H pin xon_gen When set to 0 XON Frame generation is disabled Table 4 MAC Configuration Options Option Unit Description Default f Set the Transmit FIFO Section empty threshold eee Integer to any value between 0 and 63 Maximum 16 pty memory depth Set the Transmit FIFO Section full threshold to MAC CONFIG Transmit FIFO Section Full Threshold Integer any value between 0 and 63 Maximum memory 16 depth Set the Receive FIFO Section empty threshold EE uaa Integer to any value between 0 and 63 Maximum 0 pty memory depth Set the Receive FIFO Section full threshold to MAC CONFIG Receive FIFO Section Full Threshold Integer any value between 0 and 63 Maximum memory 16 depth Enable Auto Negotiation When selected the Core performs auto negotiation to check the link with the Link Partner before simulation starts Ss RE E GER Boolean After simulation the Auto Negotiation is True g restarted with the Core signal an_enable set to 0 When disabled non Auto Negotiation is performed Ignore Pause Frames When enabled received Map Ek ie Pausa Boolean Pause Frames are ignored when disable False Pause Frames are decoded
17. n Stratix II GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 2 Design Flow The different steps of the Embedded Gigabit Ethernet MAC PHY Design are Core generation RTL Simulation Synthesis Implementation using Quartus II Gate Level Simulation Not available with Evaluation License The design kit provides scripts for ease of use fast design and verification implementation turn around The tools primarily supported are Simulation Modelsim Version 5 7a or higher Synthesis Altera Quartus II V5 1 or higher Implementation Altera Quartus II V5 1 or higher MIB 3 Generating the MAC PHY Core 3 1 Overview Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 After the Core configuration utility is installed start the utility and when the panel is available 1 Select the Core options on the panel 2 Press the Generate HDL button 3 4 A new window appears prompting you for a key Type LbNH sC79 and press Enter A new window appears which can be used to navigate through the file system to select an existing directory or create a new working directory After pressing the open button finally creates the database Macirum Frame Lengthy 1522 1 16000 Pause Frame Quarts 1000 vm 6656 T Enabse Promiscuous Receive Mode MorethanIP TestBuilder alaiz Fam g Generated Framer Maxmum Payload length 150
18. nvironment Version 1 2 x JRE1 2 or later To determine if and which Java version is installed on your system open a Shell and type java version If you get errors then the runtime is not installed If the version is lower than 1 3 x a newer package must be installed A platform specific package The runtime standard edition 1 3 JRE 1 3 is sufficient can be downloaded from the Sum Microsystems WEB site http java sun com j2se To install the runtime environment follow the instructions included in the download package e Windows platform Execute the self extracting archive e Solaris Linux Extract the package in a directory and add the bin directory to the PATH environment variable 1 2 Design Kit Installation A single executable Java delivery and configuration utility common to all platforms is provided ethpack jar The utility generates all the required design files as well as the required scripts for simulation and implementation After unzipping the distribution in any directory the Java application can be started immediately e Windows users 1 Double click on the ethpack jar file found in the distribution top directory e UNIX Solaris Linux users 1 Goto the installation directory gt cd lt installation directory gt 2 Execute the Java application gt java jar ethpack jar 1 Use the extract feature of your unzip tool Avoid using drag amp drop as it does not preserve the directory structure Ha
19. rs e GMII Ethernet Frame Generator Configurable Ethernet Gigabit Ethernet frame generator with GMII interface e GMIl Ethernet Frame Monitor Gigabit Ethernet frame monitor with GMII interface e Ethernet Frame Generator FIFO mode Configurable Ethernet frame generator simulating a user application connected to the MAC transmit FIFO interface e Ethernet Monitor FIFO mode Ethernet frame checker simulating a user application connected to the MAC receive FIFO interface e PCS 1000Base X PCS function that decodes encodes data from to the MAC PHY Core and controls the Auto Negotiation process within the testbench Han Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 mtip_sim_pack vhd Ee Testbench Unit Under Test uut Ethernet Fram Generator e COLE MA TX FIFO mode Ethernet ESCH Monitor A ae Set RX i FIFO mode 1 GMII p Ethernet Frame H Monitor PCS Model GMII K T Ethernet Frame Generator EE Testbench Control Figure 3 Testbench Setup Overview 3 5 Running Simulation Using Modelsim SE Overview To simplify the evaluation process and to allow designers to quickly generate custom simulation scenarios a graphical utility Testbuilder is provided Testbuilder operates as a Modelsim plug in which is used to
20. shold level is reached a Pause Frame will be generated by the MAC TX If set to 0 the RX FIFO read is never paused Restart RX FIFO read after RX FIFO clocks Number of clock cycles the RX FIFO should not be read after it has been stopped Only relevant if the previous configuration read stop was set to a non null value After this number of RX FIFO clock cycles the RX FIFO will be emptied again 10 Generate Frames with Errors on Transmit FIFO Interface Boolean Enable Transmit Error Generation the Core Transmit Interface When selected the transmit FIFO signal _tx_err is asserted with ff_tx_eop to signal an Error When disabled the FIFO error is signalled _tx_err is never set to 1 False Testbench reacts on Pause Frames Boolean If enabled true the Testbench will stop the RX PHY Frame generator if the MAC sends a Pause Frame This simulates a usual flow control chain correctly If disabled False Pause Frames sent by the MAC are ignored by the Testbench and the RX PHY Frame generator will never pause This can be used to test the MACs FIFO overflow behavior This option has no effect if loopback mode is enabled i e Frame generation in RX path is set 0 True ral Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 XOFF Pause Frame Generation Set the ti
21. te Level Run Simulation only Configure and Start Simulation Number of Frames in RX path O loopback TX P I Simulation Number of Frames in TX path 5 Control IPG in RX path bytes 12 ontro Length of first frame 100 Frame length increment fi be I I I I I I I I Generated Frames Maximum Payload length 1500 i Enable padding of frames in RX path by PHY Model V i Generate VLAN frame every frames E i I Stop Ax FIFO read after frames jo l Restart RX FIFO read after clocks fi 0 I I I I I I I I I I Generate Frames with Errors on Transmit FIFO Interface I Testbench reacts on Pause Frames if not in loopback V Force Xoff Frame Generation at clocks fo Compile database before simulation VHDL Iv Table 3 Figure 5 Testbuilder Panel Simulation Options Sets the number of frames that are generated by the Ethernet frame Generator connected to the Number of Frames in RX path Frames Receive PHY interface 5 If set to 0 a Serdes loopback test is performed with the Core pin loop_ena set to 1 Sets the number of frames that are generated by Number of Frames in TX path Frames _ the frame Generator connected to the Core 5 transmit FIFO interface Sets the inter packet gap IGP used by the IPG in RX path Bytes Ethernet Frame generator when generating 12 frames to the RX PHY interface Length of first frame Bytes Defin
22. ueuueseeeuaeaueeseeeeeeeeeaneneess 16 3 8 VQMNETLIST GENERATION 16 3 9 FULL TIMING GATE LEVEL SIMULATION ssssssssssenisnssssesuenrinnruetsnn tninn unnn nn nanntu nkuna nanna nn nannan nn nnna 17 4 CONTAC EE 18 Figure 1 Design Flow Overview ccccccccscesesceceeeeeeeaeeeeaaeeeeeeceaeeeeaaesaaeeseaeeesaaeseeaaesseaeeesaeeseaaeeseneeesaees 5 Figure 2 MAC Core Configuration Panel 6 Figure 3 Testbench Setup Ovenlew nn nnnn ennnen 8 Figure 4 Running Testbuilder Cverview nenene 9 Figure 5 Testbuilder Panel 10 Figure 6 VQM Netlist Generation 17 List of Tables Table 1 Core Configuration Options ccccceeecceeeceeeeeeeeeeeeeeeeeee cae eeeeaeseeeeeseaeeesaaeeeeaeeeeeeessaeeeeeeseneeee 7 Table 2 Design Kit Directory Gtruchure 7 Table 3 Simulation e te EE 10 Table A MAC Configuration Options 0 cceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeaaeseceeeceaeeesaaeeseaeeseeeescaeeesaeessaes 12 Table 5 Testbuilder Simulation Control 13 Table 6 ul R e EE 13 Table 7 MAC Configuration Options cccccceceeeceeeeeceeeeeeeeeeeeeeeeeeaeeeeaaeseeeeseaeeesaaeedeaeesseeeesiaeeesaeeseaes 15 Han Stratix Il GX Embedded Gigabit Ethernet MAC PHY User s Guide Version 1 0 October 2005 1 Design Kit Installation 1 1 Platform Specific JAVA Runtime Installation To be able to run the MAC Design Kit delivery and configuration tool a Java runtime must be present on the system The design kit needs the Java Runtime E
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