Detailed Datasheet
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1. L it operates by receiving M CLK2 from master device 2 Frequency Selection FS To adjust FRM by 70Hz the oscillation frequency should be as following OSCILLATION FREQUENCY fosc 430KHz fosc 21 5KHz In the slave mode it is connected to Vpp 64CH Common Driver For Dot Matrix LCD 12 3 Duty Selection DS1 DS2 It provides various duty selection according to DS1 DS2 DUTY 3 Data shift amp Phase Select Control 1 Phase Selection It is a circuit to shift data on synchronization or rising edge or falling edge of the CL2 according to PCLK2 PCLK2 PHASE SELECTION Data shift on rising edge of CL2 Data shift on falling edge of CL2 2 Data shift Direction Selection When M S is connected to VDD DIO1 and DIO2 terminal is only output When M S is connected to VSS it depends on the SHL DIO1 DIO2 DIRECTION OF DATA H C1 C64 C64 C1 L DIO1 C1 C64 DIO2 DIO2 C64 C1 DIO1 64CH Segment Driver For Dot Matrix LCD 13 CHAPTER 3 Driver IC Function Description KS0108 Driver IC 64 SEG graphic driver for dot matrix LCD Introduction The KS0108B is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems This device consists of the display RAM 64 bit data latch 64 bit drivers and decoder logics It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix liquid crystal driving signals corr2. DIO1 is external clock 5 This value is specified about current flowing through VEE Don t connect to Vicp V1 V5 A N eo 0 1 p On Resistance Rous Vop Vee 17V Vdiv Ci Load current 150uA 1500 64CH Common Driver For Dot Matrix LCD 8 Electrical Absolute Maximum Ratings KS0108B PARAMETER SYMBOL RATING NOTE 0 3 47 0 ei 4 1 Supply voltage Vpp 19 0 Vpp 0 3 4 Driver supply voltage 0 3 Vop 0 3 Vee 0 3 Vop 0 3 Notes 1 Based on Vss OV 2 Applies the same supply voltage to VEE VLep VDD VEE 9 Applies to M FRM CLK1 CLK2 CL RESETB ADC CS1B CS2B CS3 E R W RS and DBO DB7 4 Applies VOL V2L V3L and V5L Voltage level Vpp VO V1 V2z V3 V4z V5 Vee DC Electrical Characteristics KS0108B VDD 4 5 to 5 5V VSS 0V VDD VEE 8 17V Ta 30 to 85 O ITEM SYMBO CONDITION UNIT L E Operating voltage V 1 1 45 J55 v Vo 2 0 Von 2 Input Low voltage o f p m ale em prr Voltage Output Low Voltage Vo lu 1 6mA 04 nei GER oid ol li al E current 0 rer al iN a E RU Input Current Eme e ewm mp omi leakage current 7 5 kO 8 On Resistance Rons Vop Vee 15V T Vdiv Ci Load current 100uA Operating current looi During Display 0 1 mA 7 Ipp2 During Access 0 5 7 Access Cycle 1MHz Notes 1 CL FRM M RSTB CLK1 CLK2 2 CS1B CS2B CS3 E RW RS DB0 DB7
3. Notes 1 Based on Vss OV 2 Applies to input terminals and I O terminals at high impedance Except VOL V1L V4L and V5L 3 Applies to VOL V1L V4L and V5L 4 Voltage level Vppz VO V1z V2z V3z VAz V5 Vee DC Electrical Characteristics KS0107B VDD 4 5 to 5 5V VSS 0V VDD VEE 8 17V Ta 30 to 85 O ITEM SYMB CONDITION pa TYP MAX OL 45 Operating voltage I a Input voltage Via di 0700 EL UNIT NOT mz lt 3 x E N gt O N gt o lt u ws o D eo P current Cf 20pF 5 MIN 45 l a lonz 0 4mA Vo 0 4 lo 0 4mA ENS zd 315 50 450 1 5 O1 O1 Operating current Ippi Master mode 1 128 Dut lpp2 Master mode 1 128 Dut Supply Current IEE Master mode 1 128 Dut Operating fop1 Master mode External Dut Notes 1 Applies to input terminals FS DS1 DS2 CR SHL MS and PCLK2 and I O terminals DIO1 DIO2 M and CL2 in the input state 2 Applies to output terminals CLK1 CLK2 and FRM and I O terminals DIO1 DIO2 M and CL2 in the output state 3 This value is specified about current flowing through Vss Internal oscillation circuit Rf247kO cf 20pF Each terminals of DS1 DS2 FS SHL and MS is connected to Vpp and out is no load 4 This value is specified about current flowing through Vss Each terminals is DS1 DS2 FS SHL PCLK2 and CR is connected to Vpp MS is connected to Vss and CL2 M
4. The display on off flip flop can changes status by instruction The display data at all segment disappear while RSTB is low The status of the flip flop is output to DB5 by status read instruction The display on off flip flop synchronized by CL signal X Page Register X page register designates pages of the internal display data RAM Count function is not available An address is set by instruction Y address counter Y address counter designates address of the internal display data RAM An address is set by instruction and is increased by 1 automatically by read or write operations of display data Display Data RAM Display data RAM stores a display data for liquid crystal display To indicate on state dot matrix of liquid crystal display write datra1 The other way off state writes 0 Display data RAM address and segment output can be controlled by ADC signal ADC H gt Y address 0 S1 Y address 63 S64 ADC L gt Y address 0 S64 Yaddress 63 S1 ADC terminal connect the Vpn or Vss Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display Bit data DB lt 0 5 gt of the display start line set instruction is latched in display start line register Latched data is transferred to the Z address counter while FRM is high presetting the Z address counter It is used for scrolling of the liquid crystal display screen 64CH Segment Driver For Dot Mat
5. 3 DBO DB7 4 Except DBO DB7 5 DBO DB7 at high impedance 6 VO V1 V3 V3 V4 V5 7 1 64 duty FCLK 250KHZ Frame Frequency 70HKZ Output No Load 8 Vpp VEEg 13 5V VOL V2L Vppb 2 7 Vpp VEE V8L VEE 2 7 Voo VEE gt V5L 64CH Common Driver For Dot Matrix LCD 9 CHAPTER 2 Driver IC Function Description KS0107 Driver IC 64COM graphic driver for dot matrix LCD Introduction The KS0107B is an CD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems This device provides 64 shift registers and 64 output drivers It generates the timing signal to control the KS0108B 64 channel segment drover The KS0107B is fabricated by low power CMOS high voltage process technology and is composed of the liquid crystal display system in combination with the KS0108B 64 channel segment drover AC Characteristics VDD 4 5 5 5V Ta 30 C 85 O 1 Master mode MS Von PCLK2zVpp Cf 20pF Rf 47KQ SHL Vpp SHT Vss CHARACTERISTIC SYMBOL UNIT Data Setup Time ty 20 Data Hold Time itp 40 64CH Common Driver For Dot Matrix LCD 10 Data Delay Time ty bh b FRM Delay Time tor 2 Jes M Delay Time tom 2 2 CL2 Low Level Width two 85 h CL2 High Level Width twuc 85 CLK1 Low Level Width tw 700 j b CLK2 Low Level Width tws 700 CLK1 High Level Width twm 2100
6. operations of display data o o o 1 ACS AC4 AC3 AC2 ACI ACO 64CH Segment Driver For Dot Matrix LCD 20 3 Set Page X Address X address ACO AC2 of the display data RAM is set in the X address register Writing or reading to or from MPU is executed in this specified page until the next page is set 0 o j 1 o 1 1 1 J AC2 Aci ACO 4 Display Start Line Z Address Z address ACO AC5 of the display data RAM is set in the display start line register and displayed at the top of the screen When the display duty cycle is 1 64 or others 1 32 1 64 the data of total line number of LCD screen from the line specified by display start line instruction is displayed A Oo 1 1 ACS AC4 ac3 AC2 ACI ACO 5 Status Read 1 0 Busy o ON OFF RESET o o 0 0o e BUSY When BUSY is 1 the Chip is executing internal operation and no instructions are accepted When BUSY is 0 the Chip is ready to accept any instructions e ON OFF When ON OFF is 1 the display is on When ON OFF is 0 the display is off e RESET When RESET is 1 the system is being initialized In this condition no instructions except status read can be accepted When RESET is 0 initializing has finished and the system is in the usual operation condition 6 Write Display Data Writes data D0 D7 into the display data RAM After writing instruction Y address is increased by 1 a
7. CLK2 High Level Width twm 2100 n CLKt CLK2 Phase Difference t 700 j f CLK2 CLK1 Phase Difference tp 700 CLK1 CLK2 Rise Fall Time tate 150 Slave mode MS Vs55 twr ci 0 7 Vpp E He ts CL2 PLK2 Vpp DIO1SHL V pp DIO2 SHL V ss Input Data DIO1SHL V pp DIO2 SHL V ss Output Data CHARACTERISTICS SYMBOL M CL2 Low Level Width CL2 High Level Width CL2 Low Level Width CL2 High Level Width 50 Data Setup Time 00 Data Hold Time 00 TYP MAX NOTE U ne NEUEM ERE Pur i MN TYP Es je a see Soa a 450 EEE 100 p cc orse i Data Delay Time tp Output Data Hold Time 10 CL2 Rise Fall Time 1 Connect load CL 30pF 1 OUTPUT 30pF HH 64CH Common Driver For Dot Matrix LCD 11 FUNCTIONAL DESCRIPTION 1 RC Oscillator The RC Oscillator generates CL2 M FRM of the KS0107B and CLK1 CLK2 of the KS0107B by the oscillation resister R and capacitor C When selecting the master slave oscillation circuit is as following 1 Master Mode KS0107B KS0107B R C open open Extemal clock 2 Slave Mode KS0107B R C open open DD 2 Timing Generation circuit It generates CL2 M FRM CLK1 and CLK2 by the frequency from oscillation circuit 1 Selection of Master Slave M S When M S is H it generates CL2 M FRM CLK1 and CLK2 internally When M S is
8. User s Guide ATM12864D Liquid Crystal Display Module ATM12864D LCM Use s Guide Contents Chapter 1 Introduction to ATM12864D LCM Features Mechanical Specifications Temperature Characteristics External Dimensions Application Diagram Electro Optical characteristics Interface Pin Connections Electrical Absolute Maximum Rating KS0107B DC Electrical Characteristics KS0107B Electrical Absolute Maximum Rating KS0108B DC Electrical Characteristics KS0108B Chapter 2 Driver IC KS0107B Function Description Introduction 0 0 NN OO A A m rm NIN AC Characteristics Master Mode Slave Mode Functional Description RC Oscillator Timing Generation Circuit Data Shift amp Phase Select Control Chapter 3 Driver IC KS0108B Function Description Introduction Eo CAE b n LL SLE ob he lE c 0 N O AC Characteristics D Operating Principles amp Methods oO Display Control Instruction 64CH Common Driver For Dot Matrix LCD 2 CHAPTER 1 Introduction to ATM12864D LCM VT12864D is a dot matrix graphic LCD module which is fabricated by low power COMS technology It can display 128 64 dots size LCD panel using a 128 64 bit mapped Display Data RAM DDRAM It interfaces with an 8 bit microprocessor Features Display format 128 64 dots matrix graphic STN yellow green mode Easy interface with 8 bit MPU Low power consumption LED back light Viewing angle 6 O clock D
9. a RAM Data read from display data RAM to output register Reset The system can be initialized by setting RSTB terminal at low level when turning power on receiving instruction from MPU When RSTB becomes low following procedure is occurred 1 Display off 2 Display start line register become set by 0 Z address 0 While RSTB is low No instruction except status read can by accepted Therefore execute other instructions after making sure that DB4 clear RSTB and DB7 0 ready by status read instruction The conditions of power supply at initial power up are shown in table 1 Table 1 Power Supply Initial Conditions TEM SYMBOL MN TYP max UNT Reset Time ts 10 f lus Bam Du EN E Busy flag Busy flag indicates that KS0108B is operating or no operating When busy flag is high KS0108B is in internal operating When busy flag is low KS0108B can accept the data or instruction DB7indicates busy flag of the KS0108B E Busy Flag 4 1 Busy gt 1 feLgsT Busy lt 3 fcrg fer is CLK1 CLK2 Frequency 10 64CH Segment Driver For Dot Matrix LCD 18 Display On Off Flip Flop The display on off flip flop makes on off the liquid crystal display When flip flop is reset logical low selective voltage or non selective voltage appears on segment output terminals When flip flop is set logic high non selective voltage appears on segment output terminals regardless of display RAM data
10. esponding to stored data The KS0108B composed of the liquid crystal display system in combination with the KS0107B 64 common driver AC Characteristics V5524 5 5 5V Vss 0V Ta 30 C 85 0 10 Clock Timing CLK1 CLK2 Cycle Time tcy 25 20 us CLKi LOW Level Width tw 625 J CLK2 LOW Level Width tw 625 J CLKi HIGH Level Width tw 1875 CLK2 HIGH Level Width twiz 1875 J ns CLK1 CLK2 Phase Difference to 625 J CLK2 CLK1 Phase Difference tp 625 J Ai CURE Rie ine i LT CLK1 CLK2 Fall Time te 150 64CH Segment Driver For Dot Matrix LCD 14 O 20 Display Control Timing FRM Delay Time Li 2 F 2 img me Sig gt e i CL LOW Level Width tw 35 J CL HIGH Level Width tw 35 64CH Segment Driver For Dot Matrix LCD 15 30 MPU Interface pex ei ssi 5 1 25 ie 25 Ei E s 25 25 20 pe d i NEN i ke 4 er CES Address Set Up Time tasu 140 i Address Hold Time tay 10 Ee d EN EP i Fe per 2 Data Hold Time Write Data Hold Time Read tg gt te tan tasu E CSIBCS25 3 CS3 RS tosu DB0 DB7 MPU Write timing 64CH Segment Driver For Dot Matrix LCD 16 CSIB CS2B CS3 RS DB0 DB7 MPU Read timing OPERATING PRINCIPLES amp METHODS 1 O Buffer Input buffer co
11. ntrols the status between the enable and disable of chip Unless the CS1B to CS3 is in active mode Input or output of data and instruction does not execute Therefore internal state is not change But RSTB and ADC can operate regardless CS B CS3 2 Input register Input register is provided to interface with MPU which is different operating frequency Input register stores the data temporarily before writing it into display RAM When CS1B to CS3 are in the active mode R W and RS select the input register The data from MPU is written into input register Then writing it into display RAM Data latched for falling ofthe E signal and write automatically into the display data RAM by internal operation 3 Output register Output register stores the data temporarily from display data RAM when CS1B CS2B and CS3 are in active mode and R W and RS H stored data in display data RAM is latched in output register When CS1B to CS3 is in active mode and R W H RS L status data busy check can read out To read the contents of display data RAM twice access of read instruction is needed In first access data in display data RAM is latched into output register In second access MPU can read data which is latched That is to read the data in display data RAM it needs dummy read But status read is not needed dummy read 4 64CH Segment Driver For Dot Matrix LCD 17 L Instruction Status read busy check Data write from input register to display dat
12. on Driver For Dot Matrix LCD 6 Interface Pin Connections PIN SYMBOL I O DESCRIPTION TYPE Suppl Suppl Suppl Data input output pin of internal shift register DIO1 DIO2 Output Output Output Output Input Output Output Input VSS VDD mo Read or Write RW Description H Data appears at DB 7 0 and can be read by the CPU while E H CS1B L CS2B L and CS3 H L Display data DB 7 0 can be written at falling edge of E when CS1B L CS2B L and CS3 H Enable signal E Description H Read data in DB 7 0 appears while E High L Display data DB 7 0 is latched at falling edge of E Data bus 0 7 Bi directional data bus Chip selection When CS1 H CS2 L select IC1 When CS1 L CS2 H select IC2 Reset signal When RSTB L 10 ON OFF register becomes set by 0 display off 20 display start line register becomes set by 0 Z address 0 set display from line 0 30 After releasing reset this condition can be changed only by instruction ME VEE is connected by the same voltage Back light anode L Back light cathode i NO FEE En 8 9 s 10 aa ELTE 15 16 Elo i 20 UJ UJ UJ I mI 64CH Common Driver For Dot Matrix LCD 7 Electrical Absolute Maximum Ratings KS0107B PARAMETER SYMBOL RATING NT NOTE 0 3 47 0 Supply voltage Vpp 19 0 Vpp 0 3 4 Driver supply voltage 0 3 Vop 0 3 pe Vee 0 3 Vpp 0 3 3 4
13. riving method 1 64 duty 1 9 bias LCD driver IC KS0108B 2 KS0107B Connector Zebra Mechanical Specifications Dot Size W H 0 48 0 48 Dot Pitch W H 0 52 0 52 Module Size With B L 93 0 70 0 15 0 Temperature Characteristics PARAMETER SYMBOL RATING UNIT Operating temperature Topr 25 65 Storage temperature 30 70 64CH Common Driver For Dot Matrix LCD 3 Figure 1 External Dimensions MAX 15 0 9 8 0 3 9XP2 54 48 26 COx 1 0 ERI EE em ff ufo ts isf el Lust 20 sigNaL oBa os DBe 087 csi csel RES VEE A K NOTE 1 All units are mm 2 Tolerances unless otherwise specified 02 64CH Common Driver For Dot Matrix LCD 4 Figure 2 Application Diagram LCD panel COMI 128X64 COM64 SEG64 SEG65 SEG128 S1 S64 KS0108B Bottom view CONVERTOR KS0108B WEE Bottom view Note 1 64 duty 1 9 bias Vpp2 V12V22V3 VA2V 52M ee 64CH Common Driver For Dot Matrix LCD 5 Electro Optical characteristics TN Type Twisted Nematic ITEM ER UNIT CONDITION NOTE CR af eo ono ES eee ete ts REA 9 0 COINS wf 32 OSSI ETES Response Time rise Response Time fall Cr 6 lt 20 lt 6 2 0 0 20 0 3 Definition of contrast Cr 4 Definition of optical response ARPA On Off p OH Intensity 100 10 100 Set Point Driving Voltage Cr A B Negative P 1 Positive P 1 Time 64CH Comm
14. rix LCD 19 Display Control Instruction The display control instructions control the internal state of the KS0108B Instruction is received from MPU to KS0108B for the display control The following table shows various instructions Fo nan rini data DB 7 0 o PAR data from display data RAM to the data bus Read Display Date Writes data DB 7 0 into the DDRAM After writing d Hispa Write data instruction Y address is incriminated by 1 automatically Reads the internal status BUSY 0 Ready 1 In operation Status Read le is ON OFF 0 Display ON 1 Display OFF RESET 0 Normal 1 Reset Address Y Sets the Y address at Y address 0 63 the column address LL counter Indicates the Display Pen Display start line 0 63 Data RAM displayed at the top of the screen mu cu Address X Page 0 7 Sets the X address at mu cu 9 the X address register Controls the display ON or OFF The internal Display On off status and the DDRAM data is not affected 0 OFF 1 ON 1 Display On Off The display data appears when D is 1 and disappears when D is 0 Though the data is not on the screen with D 0 it remains in the display data RAM Therefore you can make it appear by changing D 0 into D 1 EATA scd Eos ve qr ee 2 Set Address Y Address Y address ACO AC5 of the display data RAM is set in the Y address counter An address is set by instruction and increased by 1 automatically by read or write
15. utomatically R W 1 o D7 D6 D5 D4 D3 D2 D1 DO 7 Read Display Data Reads data D0 D7 from the display data RAM After reading instruction Y address is increased by 1 automatically 1 1 D7 pe ps D4 D3 D2 D1 Do
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