PI2125 Evaluation Board User Guide
Contents
1. a solid output source such as a DC DC converter that supplies high current and can be connected very close to the evaluation board to reduce stray parasitic inductance Or use the prospective supply sources of the end application where the PI2125 will be used Stray parasitic inductance in the circuit can contribute to significant voltage transient conditions particularly when the internal MOSFET is turned off after a reverse current fault has been detected When a short is applied at the output of the power sources and the evaluation board input Vin a large reverse current is Picor Corporation e www picorpower com 7 3 sourced from the evaluation board output through the ORing internal MOSFET The reverse current in the MOSFET may reach over 60A in some conditions before the MOSFET is turned off Such high current conditions will store high energy even in a small parasitic element and can be represented as Y2Li2 A 1nH parasitic with 60A reverse current will generate 1 8uJ When the MOSFET is turned off the stored energy will be released and will produce a high negative voltage at the MOSFET source and high positive voltage at the MOSFET drain This event will create a high voltage difference across the drain and source of the MOSFET Apply a short at one of the inputs Vin1 or Vin2 when the evaluation board is configured with both SIP s SIP1 and SIP2 in master mode The short can be applied electronically using a MOSFET conn2. are available upon request Specifications are subject to change without notice ER TREE Asse SPESIE Vicor Corporation Picor Corporation 25 Frontage Road 51 Industrial Drive Andover MA 01810 North Smithfield RI 02896 USA USA Customer Service custserv vicorpower com Technical Support appsQvicorpower com Tel 800 735 6200 Fax 978 475 6715 Picor Corporation www picorpower com PI2125 EVAL2 User Guide Rev 1 1 4 09
3. 1 6 Appropriately sized interconnect cables 1 7 Safety glasses 1 8 PI2125 Product Data sheet Isolated PSS PA 12VH00mA s LA j ZA PI2125 EVAL2 T rA 9 2007 PS1 0 20V 15A saas nu Isolated PICOR ps4 F i A Vicor Subsidiary C3 El ectr onic 12V 100mA Cool ORing Load SIP2 25A if MS ch ded EI zm LT Figure 3 Layout configuration for typical redundant power application using PI2125 with both solutions configured in Master Mode Picor Corporation e www picorpower com PI2125 EVAL2 User Guide Rev 1 1 Page 4 of 11 Before initial power up follow these steps to configure the 4 0 Auxiliary Power Supply Vaux evaluation board for specific end application requi ts eres pata PP dor EE 4 1 The PI2125 ORing SiP has a separate input VO that 2 0 Undervoltage UV and Overvoltage OV provides power to the control circuitry and the internal gate driver An internal voltage regulator 2 1 Since SIP1 and SIP2 are return GND pin 11 VC clamps the VC voltage to 15 5 V typically referenced to Vin1 and Vin2 respectively UV and OV are disabled The UV pin is directly connected to the 4 2 Connect independent Auxiliary power sources to VC pin pin 10 and the OV pin is connected to the SIP Vaux inputs of the PI2125 EVAL2 Evaluation Board to return pin 11 supply power to the VC input The auxiliary power source return can be connected to either Rtn terminal or to Gnd terminal If the au
4. 25 EVAL2 User Guide Rev 1 1 Page 8 of 11 Figure 7a PI2125 EVAL2 layout top layer Scale 2 0 1 Figure 7c PI2125 EVAL2 layout mid layer 1 Scale 2 0 1 Picor Corporation e www picorpower com Figure 7b PI2125 EVAL2 layout mid layer 2 Scale 2 0 1 Figure 7d PI2125 EVAL2 layout Bottom layer Scale 2 0 1 PI2125 EVAL2 User Guide Rev 1 1 Page 9 of 11 1 550 1 400 1 300 0 150 0 900 0 800 0 550 0 400 0 300 0 150 0 000 Mechancial Drawing SIP1 Fiaden el AALAHHEE DR a 2822 Picor Corporation e www picorpower com PI2125 EVAL2 User Guide Rev 1 1 Page 10 of 11 170 Ad 1 450 1 100 0 050 0 889 0 811 0 650 0 250 0 100 0 000 1 800 Vicor s comprehensive line of power solutions includes high density AC DC amp DC DC modules and accessory components fully configurable AC DC amp DC DC power supplies and complete custom power systems Information furnished by Vicor is believed to be accurate and reliable However no responsibility is assumed by Vicor for its use No license is granted by implication or otherwise under any patent or patent rights of Vicor Vicor components are not designed to be used in applications such as life support systems wherein a failure or malfunction could result in injury or death All sales are subject to Vicor s Terms and Conditions of Sale which
5. A Vicor Subsidiary PI2125 EVAL2 Cool ORing Series PI2125 EVAL2 Full Function Active ORing Evaluation Board User Guide Contents Introduction PI2125 Product Description Evaluation Board Terminal Description Evaluation Board Schematic Bill of Materials Evaluation Board Configuration Test Procedure Thermal Images PCB Layouts Evaluation Board Mechanical Drawing The PI2125 EVAL2 Evaluation Board is intended to acquaint the user with the benefits and features of the Cool ORing PI2125 full function Active ORing solution It is not designed to be installed in end use equipment Please read this document before setting up the PI2125 EVAL2 Evaluation Board and refer to the PI2125 product datasheet for device specifications functional description and characteristics Introduction The PI2125 EVAL2 allows the user to test the basic principle and operational characteristics of an Active ORing function in a redundant power architecture while also experiencing the benefits and value of the PI2125 solution versus conventional Active ORing solutions The PI2125 EVAL2 evaluation board is configured to receive two independent power source inputs per a typical redundant power architecture through two Active ORing channels that are combined to form a redundant power output Each channel is capable of up to 12 A and is suitable for redundant bus voltages up to 12 V For high current Active ORing above 12 A the two chan
6. V or higher Keep PS3 output disabled off 5 5 Connect the positive terminal of PS4 power supply to Vaux2 Connect the ground terminal of this power supply to Rtn2 Set the power supply to 12 V or higher Keep PS4 output disabled off 5 6 Connect the electronic load to the output between Vout and Gnd Set the load current to 5 A 5 7 Enable turn on PS1 power supply output 5 8 Turn on the electronic load 5 9 Verify that the electronic load input voltage reading is one diode voltage drop below 12V 5 10 Enable turn on PS3 and PS4 power supplies output 5 11 Verify that the electronic load voltage reading Isolated PS3 12V 100mA PS1 0 20V 15A Isolated PS4 12V 100mA _Rds on A Vicor Subsidiary Cool ORing PS2 med de increases to a few millivolts below 12 V This verifies that the PI2125 internal MOSFET is in conduction mode 5 12 Verify that Vin2 is at O V This verifies that the PI2125 SIP2 internal FET is off 5 13 D2 should be on This is due to a reverse voltage fault condition caused by the bus voltage being high with respect to the input voltage Vin2 5 14 Enable turn on PS2 output 5 15 Verify that both PS1 and PS2 are sharing load current evenly by looking at the supply current 5 16 Disable turn off PS1 PS2 PS3 and PS4 outputs 5 17 Enable turn on PS2 output then Enable PS3 and PS4 outputs 5 18 Verify that the electronic load voltage reading is few milliv
7. ected between Vin and Gnd or simply a by connecting Vin to Gnd Then measure the response time between when the short is applied and the SIP internal MOSFET is disconnected or turned off An example for PI2125 response time to an input short circuit is shown in Figure 5 8 0 Internal MOSFET Rds on Measurement 8 1 The SIP1 internal MOSFET Rds on can be measured with a voltmeter between the S1 and D1 Kelvin connection The potential between S1 and D1 is the voltage drop across the internal MOSFET and Rds on Vs1 VD1 lin Where Vs1 Vp1 Voltage drop across the internal MOSFET lin Input current Note The value is temperature dependent and the Junction temperature increases directly proportional to power dissipation PI2125 EVAL2 User Guide Rev 1 1 Page 7 of 11 44 1 C i f j PI2125 P12125 25 C OLFM 25 3 C 25 C 200LFM Figure 6a PI2125 mounted on PI2125 EVAL2 lout 12 A Figure 6b PI2125 mounted on PI2125 EVAL2 lout 12 A TA 25 C Air Flow O LFM TA 25 C Air Flow 200 LFM O i P12125 176n Applied short at Vinl 5 2 2 Gane Vin 12 0V A178ns Load 10A VC 24V Reverse detection Voy fva reas Vin 2 0V Div 178ns A Ms Me Slave pin 5 0V div 20 0ns 2 50GS s GP 272v uy 85 6000ns M 1M points 2 Nov 2007 10 18 36 Figure 5 Plot of PI2125 response time to reverse current detection Picor Corporation www picorpower com PI21
8. f P51 power supply to Vin1 Connect the ground terminal of this power supply to Gnd Set the power supply to 12 V Keep PS1 output disabled off Connect the positive terminal of PS2 power supply to Vin2 Connect the ground terminal of this power supply to Gnd Set the power supply to 12 V Keep PS2 output disabled off Connect the positive terminal of PS3 power supply to Vaux1 Connect the ground terminal of this power supply to Rtn1 Set the power supply to 12 V Keep PS3 output disabled off Connect the positive terminal of PS4 power supply to Vaux2 Connect the ground terminal of this power supply to Rtn2 Set the power supply to 12 V Keep PS4 output disabled off Connect the electronic load between Vout and Gnd Set the load current to 10 A Enable Turn on PS2 PS3 and PS4 outputs and keep PS1 output disabled off Turn on the electronic load Verify that electronic load voltage drops to a diode drop below PS2 This verifies that the SIP2 internal FET is off due to the Master SIP1 not being on Enable turn on PS1 output Verify that the electronic load input voltage reading is a few millivolts below 3 3 V and PS1 and PS2 are sharing the load current evenly This verifies that both internal MOSFET s of SiP1 and SiP2 are in conduction mode 7 0 Input short circuit test before set up is completed consider the following 7 1 7 2 To emulate a real application the BUS supplies for this test should have
9. grammable via an external resistor divider Terminal Description Figure 1 shows a photo of the PI2125 EVAL2 evaluation board with two PI2125 used to form the two Active ORing channels The board is built with two identical Active ORing circuits with options and features that enable the user to fully explore the capabilities of the PI2125 Cool ORing solution si PI2125 EVAL2 ra 9 2007 PICOR A Vicor Subsidiary Cool ORing Terminals Rating Vin1 Vin2 Vaux1 Vin1 R2 102 see Vaux section Vaux2 Vin2 R4 102 see Vaux section SLI Vin1 SL2 Vin2 20V 12A 0 3V to 17 3V 40mA 0 3V to 17 3V 40mA 0 3V to 8 0V 10mA 0 3V to 8 0V 10mA Figure 1 PI2125 EVAL2 Evaluation Board 1 8 x 1 8 Vin1 Power Source Input 1 or bus input designed to accommodate up to 12A continuous current Vaux1 Auxiliary Input Voltage 1 to supply PI2125 SIP1 VC power If Vaux1 is referenced to Gnd Vaux1 should equal Vin1 plus 5 5 V or higher See details in the Auxiliary Power Supply Vaux section Rtn1 Vaux1 Return Connection Connected to Vin1 Gnd Vin amp Vout Return Connection Three Gnd connections are available and are connected to a common point the Ground plane Input supplies Vin1 amp Vin2 and the output load at Vout should all be connected to their respective local Gnd connection SL1 PI2125 SIP1 Slave Input Output pin For monitoring SIP1 slave pin When SIP1 is configured as the Master thi
10. lled 0603 RAR 109 TEE H KAL SiP1 SiP2 09 _ Picor Full Function 12 A EE 17 pins Cool ORing Solution Table 3 Complete PI2125 EVAL2 Evaluation Board Bill of Material Picor Corporation e www picorpower com PI2125 EVAL2 User Guide Rev 1 1 Page 3 of 11 Reference Designator Value Functional Description C162 1 uF VC Bypass Capacitor C3 22 uF Output Load Capacitor C4 C5 CO C7 Not installed Snubber to reduce voltage ringing when the device turns off D1 D2 LED To indicate a fault exist when it is on 11 33 Jumper To select between Master and Slave Modes J2 Jumper Connection between SL1 and SL2 Q1 Q2 NSBC114EPDXV6 T1 Fault level shift circuit R2 R5 10 KO LED Current Limiter R9 R8 10 KO Fault level shift gate bias resistor R3 R6 Not Installed BK Delay Timer Programmable Resistor RA R7 10 Q VC Bias Resistor SIP SiP2 PI2125 Cool ORing SiP Table 4 Component functional description Initial Test Set Up To test the PI2125 EVAL2 evaluation board it is necessary to Baseline Test Procedure PI2125 Refer to Figure 3 configure the jumpers J1 J2 and J3 first based on the 1 0 Recommended Equipment required board configuration 1 1 Two DC power supplies 0 20 V 15 A Failure to configure the jumper prior to the testing may 1 2 DC power supply 12 V 100 mA result in improper circuit behavior 1 3 DC electronic load 25 A minimum 1 4 Digital Multimeter 1 5 Oscilloscope
11. nels provided on the evaluation board can be paralleled in a master slave configuration and OR d with a second evaluation board Picor Corporation e www picorpower com Cool ORing Series PI2125 EVAL2 Evaluation Board featuring the Cool ORing PI2125 Full Function Active ORing Solution During operation the power devices and surrounding structures can be operated safely at high temperatures e Remove power and use caution when connecting and disconnecting test probes and interface lines to avoid inadvertent short circuits and contact with hot surfaces e When testing electronic products always use approved safety glasses Follow good laboratory practice and procedures The PI2125 EVAL2 evaluation board is designed with optimized PCB layout and component placement to represent a realistic high density final design for an embedded Active ORing solution for lt 12 Vbus applications requiring up to 12 A This evaluation board is intended as an easy and simple way to test the electrical and thermal performance of the PI2125 Full Function Active ORing solution Both dynamic and steady state testing of the PI2125 can be completed on the PI2125 EVAL2 evaluation board in addition to using the key features of the product Dynamic testing can be completed under a variety of system level fault conditions to check for response time to faults This document provides basic instructions for initial start up and configuration of the e
12. nimum voltage e a o dk ion un o px x aal Vauxmax Vaux maximum voltage VCclampMAx Maximum controller clamp voltage 16 0 V VCclampMiN Minimum controller 90 110 130 5 clamp voltage 14 0 V Blanking time ns ICmax Controller maximum bias current use 4 2 mA 4 4 3 For example if the minimum Vaux 22 V and the maximum Vaux 26 V Rbias Vauxmin V CdampMAX 22 V 16 V 1429 KO ICmax 4 2 mA use 1 43 KO 1 resistor PORbias Vauxmax VCdampMIN 28 V 14 0 VP 137 mW Rbias 1 43 KQ Picor Corporation e www picorpower com PI2125 EVAL2 User Guide Rev 1 1 Page 5 of 11 Note Minimize the resistor value for low Vaux voltage levels to avoid a voltage drop that may reduce the VC voltage lower than required to drive the gate of the internal MOSFET 5 0 Hook Up of the Evaluation Board 5 1 Verify that the jumpers J1 and J3 are installed for master mode across M and no Jumper on J2 5 2 Connect the positive terminal of PS1 power supply to Vin1 Connect the ground terminal of PS1 to its local Gnd Set the power supply to 12 V Keep PS1 output disabled off 5 3 Connect the positive terminal of PS2 power supply to Vin2 Connect the ground terminal of PS2 to its local Gnd Set the power supply to 12 V Keep PS2 output disabled off 5 4 Connect the positive terminal of PS3 power supply to Vaux1 Connect the ground terminal of this power supply to Rtn1 Set the power supply to 12
13. olts below 12 V This verifies that the PI2125 internal MOSFET is in conduction mode 5 19 D2 should be off This verifies that there is no fault condition 5 20 Verify that Vin is at 0 V This verifies that the PI2125 SIP1 internal FET is off 5 21 D1 should be on This is due to a reverse voltage fault condition caused by the bus voltage being high with respect to the input voltage Vin1 6 0 Slave Mode Slave Mode can be demonstrated in two setups either by using one PI2125 EVAL2 evaluation board as a single ORing function with both PI2125 effectively in parallel or two PI2125 EVAL2 evaluation boards to demonstrate a true redundant 20 A system The following test steps uses a single PI2125 EVAL2 in a slave mode application SW PI2125 EVAL2 rA 9 2007 Electronic Load SIP2 25A l 4C CX ED 0 20V 15A Qo gees Figure 4 Layout configuration for typical application SiP1 in Master Mode and SiP2 Slave Mode Picor Corporation e www picorpower com PI2125 EVAL2 User Guide Rev 1 1 Page 6 of 11 Note In this experiment SIP 1 is set in master mode and SIP2 in 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 6 10 6 11 slave mode As shown in figure 4 BK pin J1 of the master device will be connected to ground across M while the slaved device BK pin J3 is connected to VCC across S Place a jumper across J2 to connect slave pins together Connect the positive terminal o
14. renced to Vin1 and Vin2 Slave should be used only when Vin1 and Vin2 are connected to the same input source Table 2 PI2125 EVAL2 Evaluation Board jumpers description Picor Corporation e www picorpower com PI2125 EVAL2 User Guide Rev 1 1 Page 2 of 11 SIP1 PI2125 e Vin1 1 Vout Vout1 Vini O O Vout2 c C4 Sn L Un installed m Un installed o 22 uF Gnd 14 Gnd3 FT1O Gnd4 Vaux1 O OVaux1 Rtn1 Q ovVin1 SL1 MN J2 SL2 SL2 Vaux10 109 O VC1 SIP2 PI2125 Vin2 Fault Level Shift Circuit Vin2 O mo ma C7 Red LED vot Red LED Gnd C Un HE a Gnd 7 P2 4 R2 10K FT2O Vaux2 0 0 Vaux2 Fit VC1 O O Rtn2 Q o Vin2 Vaux20 O VC2 Figure 2 PI2125 EVAL2 Evaluation Board schematic Note SIP1 and SIP2 returns GND pins are referenced to Vin and Vin2 respectively Item C1 C2 1 uF Capacitor MLCC X5R 0603 1 yF To V 22 uF Capacitor MLCC X7R 1210 22 25 V c4 C5 C5 C7 Not installed 1206 D1 D2 D1 D2 0 0 j o 4 LED Super Red THIN 0603 Lite On Inc DULCE eue Turret Test point TURRET 1528 NG ORE SL1 SL2 Vaux1 Vaux2 Electronics 7 Gndi Gnd2 Gnd3 Gnda Turret Test point TURRET 1502 Vin1 Vin2 Vout1 Vout2 Keystone Electronics IRE Header Pins 0 1 pitch Header Pins 0 1 pitch 2 Q1 Q2 RTE 14EPDXV6 T1 Pre Biased NPN PNP SOT 563 2 ON Semi 2 R2 R5 R8 R9 10 KO fester 0 2 22 O 5 0603 E R3 R6 Not Insta
15. s pin functions as an output that drives slaved PI2125 devices When SIP1 is configured in Slave mode SL1 serves as an input SL1 is referenced to Vin1 SL2 PI2125 SIP2 Slave Input Output pin For monitoring SIP2 slave pin When SIP2 is configured as the Master this pin functions as an output that drives slaved PI2125 devices When SIP2 is configured in Slave mode SL2 serves as an input Vin2 Power Source Input 2 or bus input designed to accommodate up to 12 A continuous current Vaux2 Auxiliary Input Voltage 2 to supply SIP2 VC power If Vaux2 is referenced to Gnd Vaux2 should equal Vin2 plus 5 5 V or higher See details in the Auxiliary Power Supply Vaux section Rtn2 Vaux2 Return Connection Connected to Vin2 FT1 P12125 SIP1 Fault pin Monitors SIP1 fault conditions and level shifted to be referenced to the Gnd terminal FT2 PI2125 SIP2 Fault pin Monitors SIP2 fault conditions and level shifted to be referenced to the Gnd terminal Vout Table 1 PI2125 EVAL2 Evaluation Board Terminals Description Description Output SiP1 and SIP2 D pins connection connect to the load high side BK Jumpers Connect jumper across M for master mode and across S for slave mode Remove jumper to adjust reverse fault blanking time using Rbk Rbk is R3 for SIP1 and R6 for SIP2 shown in the schematic Figure 2 Slave Jumper Remove the jumper unless one of the PI2125 is configured in slave mode Since SIP1 and SIP2 returns are refe
16. valuation board Further information on the functionality of the PI2125 can be found in the PI2125 product datasheet PI2125 EVAL2 User Guide Rev 1 1 Page 1 of 11 Cool ORing PI2125 Product Description The Cool ORing PI2125 is a complete full function Active ORing solution with a high speed ORing MOSFET controller and a very low on state resistance MOSFET designed for use in redundant power system architectures The PI2125 Cool ORing solution is offered in an extremely small thermally enhanced 5 mm x 7 mm LGA package and can be used in low voltage x 12 Vbus high side Active ORing applications The PI2125 enables extremely low power loss with fast dynamic response to fault conditions critical for high availability systems A master slave feature allows the paralleling of PI2125 solutions for high current Active ORing requirements The PI2125 with its 5 5 mQ internal MOSFET provides very high efficiency and low power loss during steady state operation while achieving high speed turn off of the internal MOSFET during input power source fault conditions that cause reverse current flow The PI2125 provides an active low fault flag output to the system during excessive forward current light load reverse current over voltage under voltage and over temperature fault conditions A temperature sensing function indicates a fault if the maximum junction temperature exceeds 160 C The under voltage and over voltage thresholds are pro
17. xiliary power source 3 0 Blanking timer setup return is connected to the Rtn terminal make sure that the auxiliary power source return is floating at the source and will not cause a short circuit to the Vin supply when it is connected to the positive terminal of the Vin supply source The Vaux voltage should be 5 5 V higher than Vin to fully enhance the internal 3 1 The blanking timer provides noise filtering for typical switching power conversion that might cause premature reverse current detection by masking the reverse fault condition The shortest blanking time is 50 ns when the BK pin is connected to ground MOSFET Connecting an external resistor Rex reference designators R3 for SIP1 and R6 for SIP2 between the 4 3 10 O bias resistors Rbias reference designators R4 BK pin and ground will increase the blanking time and R7 are installed on the PI2125 EVAL2 between as shown in the following chart each Vaux input and VC pin of one of the PI2125 SiPs Where Rak lt 200 KQ 4 4 If Vaux is higher than the Clamp voltage 15 5 V typical the Rbias value has to be changed using the Note When BK is connected to VC for slave mode following equations operation then the blanking time will be 270ns typically 4 4 1 Select the value of Rbias using the following equation Vauxmin VCclampMAX ICmax Rbias 4 4 2 Calculate Rbias maximum power dissipation PdRbias Vauxmax VCciampMIN Rbias Where Vauxmin Vaux mi
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