EVBUM2163 - Interleaved PFC Stage Driven by the NCP1631
Contents
1. Rcs is the current sense resistor Pres are the losses across Rsense 0 2 of the maximum power generally gives a good trade off between noise immunity and efficiency Rocp is the resistor that placed between the CS pin and Rcs sets the maximum level of the input current total current absorbed by the two branches Remark Regarding the Compensation The compensation is computed to have a phase margin in the range of 60 The high frequency pole can be set at a lower frequency Practically Cp can be increased up to 4 times the proposed value without changing R and Cz to reduce the ripple on the Vcontrol pin and further improve the THD This is at the cost of a diminution of the phase margin that can drop as low as 30 Example 1 300 W Wide Mains Application We select a 120 kHz frequency clamp per branch The maximum output power being 300 W we estimate that the input power can be as high as around 325 W 92 efficiency at the lowest line conservative figure that offers some margin The power capability Pi gr is set 125 higher at 400 W The minimum input voltage being 90 Vig the brown out block is dimensioned so that the circuit starts operating when the line rms voltage exceeds 81 V and a brown out fault is detected when the line magnitude goes below 72 V The regulation level is set to 390 V Vout nom 390 V and the OVP level to 410 V Voutoyp 410 V A 100 uF bulk capacitor is implemented The cur2. Hoo ES Root Hoo Replacing Lo by its expression of Equation 55 it comes 5 5 AX 53 8 1012 L Chuk Keg fc Voutnom eq 56 187 Ro Cp C2 THOR DR ref EA Replacing Gg and Kar by their typical value 200 uS and 2 5 V respectively we can write the following equation that gives Cy m Viet Gea R eq 57 7646 2 1012 L Go Kgo fc Kaes Replacing R by this expression of Equation 36 the precedent equation simplifies _ 1 06 lt 10 5 P ES ok Ee Voutriom Cp eq 58 http onsemi com 13 NCP1631PFCGEVB Computing Rz The compensation zero being placed at f 4 it comes c 1 _ fe 2x R C 4 Finally from the above computations we can deduce the following equations to design the compensation network 1 06 10 5 P eq 59 eq 60 B ok geg Voutnoni Cz 15 Cp eq 61 2 Rz a Gh CU eq 62 In our application C 1 06 10 8 497 P 100 10 5 20 390 Practically we will use 68 nF capacitor that is a close standard value Cz 15 Cp 1020 nF eq 64 86 nF eq 63 In practice a 1 uF standard capacitor is selected Finally 2 ES Rz X105 20 91 8kQ eq 65 A 33 kQ resistor is implemented The compensation is computed to have a phase margin in the range of 60 The high frequency pole can be set at a lower frequency Practically Cp can be increased up to 4 times the proposed value without changing R
3. The process is illustrated by the following 300 W universal mains application Maximum output power 300 W The pfcOK signal enables the down stream converter when the PFC is ready Figure 2 Generic Application Schematic Semiconductor Components Industries LLC 2012 November 2012 Rev 2 ON Semiconductor hitp onsemi com EVAL BOARD USER S MANUAL Figure 1 Evaluation Board Photo Input voltage range from 90 Vi to 265 Vims Regulation output voltage 390 V The computations relevant to the power components are based on the assumption that the current is perfectly shared between the two branches This assumption is valid if the two coil inductances properly match 2 Vin Publication Order Number EVBUM2163 D NCP1631PFCGEVB Introduction The NCP1631 integrates a dual MOSFET driver for interleaved 2 phase PFC applications It drives the two branches in so called Frequency Clamped Critical conduction Mode FCCrM where each phase operates in Critical conduction Mode CrM in the most stressful conditions and in Discontinuous Conduction Mode DCM otherwise acting as a CrM controller with a frequency clamp given by the oscillator According to the conditions the PFC stage actually jumps from DCM to CrM and vice versa with no discontinuity in operation and without degradation of the current shape Furthermore the circuit incorporates protection features for a rugged operation t
4. Weidmuller PM 5 08 2 90 3 5 SW YES All products listed are Pb free http onsemi com 24 NCP1631PFCGEVB HEHHIBI G9Z WOW LAG DOA TAYO 9 dWO OBHQI1O44 PALOPATSO WW H3 2092 t H30vY3H D le IOrSNI SUMA T3 OT A Of co CI tu30v3H Zr o Z t An ma LI ucc DS HO o ow Bvw3loA ubru zefuwq We rte PROT wareg tu PA 06 andano o j30H uoranvo 25 Figure 13 Evaluation Board Schematic http onsemi com NCP1631PFCGEVB TEST PROCEDURE FOR THE NCP1631PFCGEVB EVALUATION BOARD The board contains high voltage hot live parts Brown out levels Be very cautious when manipulating or testing it Starts operation when the line voltage exceeds about 84 Vrms It is the responsibility of those who utilize the board to take all the precautions to avoid that themselves Stops operation when the line voltage drops below or other people are injured by electric hazards or 72 Vrms are victim of any other pains caused by the board The NCP1631 is to be supplied by an external power e Input Range 85 to 265 Vrms source ranging from 13 V to 20 Vdc e Output Voltage 390 Vdc e The board PCB offers the option where NCP1631 is self supplied For that some components are to be added see relevant application note Output Power Range 0 to 300 W 390 Vac Output Voltage The external i Vec voltage Daer from 13 to 20 V is to i b
5. http onsemi com 20 NCP1631PFCGEVB fosc nom is the oscillator frequency without frequency foldback fsw max is the nominal clamp frequency for each branch in the absence of frequency foldback that is fosc nom 2 fsw max min is the minimum clamp frequency for each branch resulting from frequency foldback Vout nom is the nominal output voltage of the PFC stage regulation level Vin rms LL is the lowest level of the line rms voltage Pin avg max is the maximum level of the average input power IL pk max is the maximum peak current absorbed by one branch of the interleaved PFC normal operation IL rms max is the maximum rms current drawn by one branch of the interleaved PFC normal operation Pon are the MOSFET conduction losses in one branch Rps on is the MOSFET on time resistor for one branch 8Vout pk pk is the output peak to peak ripple o is the line angular frequency w 23 x fiine fiine is the line frequency Cour is the bulk capacitor tyoLp up is the specified hold up time IC rms max is the rms current of the bulk capacitor Its given computation assumes a resistive load Vout min is the minimum level of the output voltage that is acceptable for the downstream converter Pin HL is the maximum level that can be virtually delivered by the PFC stage as allowed by the timing resistor selection For the sake of a welcome margin Pin HL should be select
6. out nom AM The capacitor rms current is given by assuming a resistive load eq 9 2 16 2 Pout Pout V 9 Vintms it Vout n C rms ms out nom Finally the following equation expresses the hold up time E Cpu Vou V out min thold up 2 P eq 10 out Where Vourgnin is the minimal bulk voltage necessary to the downstream converter to keep properly feeding the load The hold time being not considered here a 100 uF capacitor was chosen to satisfy the other above conditions The peak peak ripple is 25 V 43 of Kaal and the rms current is 1 4 A Oscillator Frequency Setting The NCP1631 clamps the maximum frequency of the PFC stage without power factor degradation This feature prevents the switching frequency from reaching excessive levels at light load As detailed in the NCP1631 data sheet the clamp frequency in each phase is actually half the oscillator one Hence Fsw max 4 z Fsw max 2 sw max pm eq 11 Where fsw max 1 is the frequency clamp for the first branch of the interleaved PFC and fgw max 2 that of the second one fsw max 1 and fsw max 2 being equal fsw max stands for the clamp frequency for any of the two phases fosc is the oscillator frequency In the absence of frequency foldback heavy load in general the oscillator swings at its nominal frequency foSC nom and each branch operates with a nominal clamp frequency fsw max nom
7. 13 Set the input voltage to 115 Vrms and apply it to Efficiency Voutlout Pin gt 96 the board 14 Abruptly apply the VCC voltage 15 V Check that the output voltage keeps below 424 V Test 2 6 Observe the input current using an oscilloscope Test 5 Frequency Foldback and a current probe The current is nearly 15 Set the output current to 0 07 A and the input sinusoidal voltage to 115 Vrms 7 Increase the input voltage to 230 Vrms 16 Connect a voltage probe to the test point DRV1 on 8 Verify that the board and a current probe to observe the input current Parameters 17 Set the trigger at the top of input current sinusoid Voltage measured between 370 V lt Vout lt and zoom in to see the DRV pulses Vour Ve m and GND 409 V dis e OUT a 18 Measure the switching frequency it should be PF gt 0 970 between 35 kHz and 50 kHz THD Total Harmonic Distortion 13 96 Efficiency Voutlout Pin gt 97 5 hitp onsemi com 27 NCP1631PFCGEVB 24 Feb 09 18 22 05 Tek Figure 17 ON Semiconductor and are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC ma
8. 242 Sec ze 64A eq 74 4 390 2 aal Selecting Rocp and Rcs If we neglect the input current ripple the Rcs losses are given by the following simplified equation 2 P Pros Ros Lo eq 75 in rms One can choose Rcs as a function of its relative impact on the PFC stage efficiency at low line and full power If is the relative percentage of the power that can be consumed by Rcs this criterion leads to 2 Pin avg max ek Pin avg max Res gum eq 76 Finally Vi rms min Res me eq 77 es Pin avg max And R lima OCP CS 210 uA Generally o 0 2 gives a good trade off between losses and noise immunity 0 2 of the power is lost in the Rcs at low line This criterion leads to the following Rcs value R eq 78 2 Ros 0 2 Ss 50 mQ eq 79 This selection results in the following Rocp resistor 6 4A SEA 80 Roce 50m zga L5kQ e 80 Zero Current Detection ZCD For each phase a winding taken off of the boost inductor gives the zero current detection ZCD information When the switch is on the ZCD pin voltage is equal to Vin V rcd SS N eq 81 Where V is the instantaneous ac line voltage and N the turns ratio ratio number of turns of the primary winding over the number of turns of the ZCD auxiliary winding When the switch is off the ZCD pin voltage is equal to ET CUR eq 82 The NCP1631 incorporates two ZCD comparators 1 A first one senses p
9. 560k 27k V REF 27k out nom 25V 388 V eq 43 Ripe Compensation The NCP1631 uses the brown out input voltage to provide some feed forward This allows the small signal transfer function of PFC stage to be independent of the ac line amplitude More specifically the bulk capacitor ESR being neglected Vout _ Ri Rout 1 53 8 1012 L ka 2 V o e eq 44 VREGUL BO Lu M Me out nl MENO QUEE Where Cour is the bulk capacitor Rout is the load equivalent resistance R is the pin3 external capacitor e Lis the PFC coil inductance Kgo is the brown out scale down factor Vout nom is the regulation level of the PFC output However PFC stages must exhibit a very low regulation bandwidth in the range of or lower than 20 Hz to yield high power factor ratios Hence sharp variations of the load generally result in excessive over and under shoots The NCP1631 limits over shoots by the Over Voltage Protection see OVP section To contain under shoots an internal comparator monitors the feed back Vpin2 and when Vpin2 is lower than 95 5 of its nominal value it connects a 220 uA current source to speed up the charge of the compensation capacitors Finally it is like if the comparator multiplied the error amplifier gain by about 10 Note 1 The implementation of this dynamic response enhancer together with the accurate and programmable over voltage protection guarantees a reduced spread of the
10. R1 e 80 due to temperature effects eq 7 1N4148 Poond IM rms Bps on 1 8 0 4 1 8 233W Q1 This computation is valid for one branch As there are two phases to consider the total MOSFETs conduction losses are actually twice 4 6 W Switching losses are hard to predict They are not computed here As a rule of the thumb we generally reserve a loss budget equal to that of the conduction ones One can anyway note that the NCP1631 limits this source of dissipation by clamping the switching frequency that can never exceed the oscillator one 120 kHz in each branch in our case To further improve the efficiency the MOSFET opening can be accelerated using the schematic of Figure 3 where the Q small npn transistor TO92 amplifies the MOSFET turn off gate current Figure 3 Q1 Speeds Up the MOSFET Turn Off The input bridge that rectifies the line voltage and the MOSFETS of the two branches share the same heat sink Based on above computations the total power to be dissipated is in the range of 6 5 4 6 4 6 16 W A 2 0 C W heat sink ref 437479 from AAVID THERMALLOY is implemented It limits the rise of the case temperature of the input bridge and MOSFETs applied to it to about 50 compared to the ambient temperature http onsemi com 3 NCP1631PFCGEVB Interleaved PFC requires two boost diodes one per branch No reverse recovery issues to worry about Simply they must meet the correct volta
11. and C to reduce the ripple on the Kaomget pin and further improve the THD The crossover frequency is unchanged This is just at the cost of a diminution of the phase margin that can drop as low as 30 More specifically Dm arc EA arctan fo eq 66 fz for Where e f is the frequency of the compensator zero 1 32 n R C fp1 is the frequency of the compensator high frequency pole Finally a 150 nF capacitor is selected for Cp leading to z 5H2 f 37 Hz Pm 76 28 48 http onsemi com 14 NCP1631PFCGEVB Current Sense Network Vaux2 n D2 Vom ViN lin EMI I Filter lcs locp 200 uA Ac line Ics lcs is proportional to the coil current In rush ec 8 di Izcp 20 ENT lt E Qu L irom ZCD block The CS block performs the over current protection and detects the in rush currents Figure 9 Current Sense Block The NCP1631 is designed to monitor a negative voltage proportional to the coil current Practically a current sense resistor Rcs of Figure 9 is inserted in the return path to generate a negative voltage proportional to the total current absorbed by the two branches The circuit incorporates an operational amplifier that sources the current necessary to maintain the CS pin voltage null refer to Figure 9 By inserting a resistor Rocp between the CS pin and Rcs we adjust the pin9 current as follows Res ll Rocp Jung z Voing 0 eq 67 Whi
12. permanently senses the total input current and prevents it from exceeding the preset current limit still maintaining the out of phase operation In rush Detection the NCP1631 prevents the power switches turn on for the large in rush currents sequence that occurs during the start up phase Under Voltage Protection this feature is mainly to prevent operation in case of a failure in the OVP monitoring network e g bad connection Brown Out Detection the circuit stops operating if the line magnitude is too low to protect the PFC stage from the excessive stress that could damage it in such conditions Thermal Shutdown the circuit stops pulsing when its junction temperature exceeds 150 C typically and resumes operation once it drops below about 100 C 50 C hysteresis Power Components Defining the oscillator frequency of the NCP1631 is a prerequisite step before dimensioning the PFC stage In the presented application we choose to clamp the switching frequency at around 120 kHz in each phase because this frequency is generally a good trade off when considering the following aspects A high switching frequency reduces the size of the storage elements In particular it is well known that the higher the switching frequency the lower the inductor core That is why one should set the switching frequency as high as possible On the other hand increasing the switching frequency has two major drawbacks 1 The switching rate
13. 012 eL kgo As a result of the feed forward the delivered power does not depend on the line magnitude but is the only function of the coil inductance of the input voltage sensing network used and dimensioned for the brown out detection and of R capacitor that is the timing resistor that is applied to pin3 Since Vagggur is clamped to 1 66 V the maximum power Pin yr that can be virtually delivered by the PFC stage is R9 1 66 z Ry eq 35 Pi eq 35 Ink 26 9 1012 L kgo 16 2 1012 L kgo eq 34 Hence R 4025 107 kgo L Pnu ea 36 For the sake of a welcome margin Pin HL should be selected about 25 higher than the expected maximal input power that is 125 x 325 W 400 W in the application of interest In our case e L 150 uH e Since Ri 7200 KQ and Rpo2 120 KQ k Rbo2 Es 1 de Root Deg 61 Hence 97 R 4025 105 er 150 10 5 400 16 2 KQ a2 A 18 kQ resistor is selected that leads to P LL T09 61 IHE 46 2101 150 10 4 496 W Feed back Network The NCP1631 embeds a trans conductance error amplifier that typically features a 200 uS trans conductance gain and a 20 uA maximum capability see Figure 8 The output voltage of the PFC stage is externally scaled down by a resistors divider and monitored by the feed back input pin2 The bias current is minimized less than 500 nA to allow the use of a high impedance feed back network The outp
14. 1 4 W 22 kW 196 SMD 1206 YES R16 R21 2 Axial resistor 1 4 W OW 196 through hole YES R18 1 Axial resistor 1 4 W 560 kW 0 01 through hole YES R23 1 Axial resistor 1 4 W 820 kw 0 01 through hole YES R24 1 Axial resistor 3 W 1 50 mW 0 01 through hole Vishay RLP3 0RO50 NO R25 R40 2 SMD resistor 1206 1 4 W 27 kW 0 01 SMD 1206 YES R31 R32 8 Axial resistor 1 4 W 1800 kW 196 through hole YES R38 R39 1 4W R44 R42 R43 R44 R33 1 SMD resistor 1206 1 4 W 18 kW 0 01 SMD 1206 YES R34 1 SMD resistor 1206 1 4 W 270 kW 0 01 SMD 1206 YES R36 1 SMD resistor 1206 1 4 W 33 kW 0 01 SMD 1206 YES R37 1 SMD resistor 1206 1 4 W 4 7 KW 0 01 SMD 1206 YES R45 1 SMD resistor 1206 1 4 W ow 0 01 SMD 1206 YES R46 1 SMD resistor 1206 1 4 W 120 kw 0 01 SMD 1206 YES R121 3 SMD resistor 1206 1 4 W 680 kW 0 01 SMD 1206 YES R122 R123 U1 1 Diode Bridge KBU6K General KBU6K NO Semiconductor U2 1 Interleaved PFC NCP1631 S016 ON NCP1631 NO controller SOIC 16 Semiconductor X1 X5 2 PFC coil 150 uH CME OF9120 NO X4 X6 2 MOSFET IPP50N250 550 V TO220 Infineon IPP50N250CP NO 2 TO220 isolators Bergquist 3223 07FR 43 YES 5 Board legs RICHCO TCBS 801 YES F1 1 Fuse 4A 250V Shurter 34 3123 YES Temporised X4 X6 2 MOSFET IPP50N250 550V TO220 Infineon IPP50N250CP NO CP VOUT 1 Connector Multi Contact 23 3200 22 YES GND 1 Connector Multi Contact 23 3200 21 YES J1 1 Connector Schurter GSF1 1201 31 YES J2 1 Connector 3
15. 6 YES 50V C25 1 Ceramic capacitor 1uF 1096 SMD 1206 YES 50V C28 1 Ceramic capacitor 220 nF 1096 SMD 1206 YES 50V C30 C33 2 Ceramic capacitor 100 nF 1096 SMD 1206 YES 50V C32 1 Electrolytic capacitor 100 uF 25V through hole YES C34 1 Ceramic capacitor 10 nF 1096 SMD 1206 YES 50V D6 D14 3 Diode D1N4148 through hole Philips 1N4148 YES D15 D3 1 LED 3mm 2 4V 2MA through hole Vishay TLLG4400 YES D4 D5 2 Boost diode MUR550 5A Axial ON MUR550APFG NO 500 V Semiconductor D16 1 Standard recovery diode 1N5406 3A Axial ON 1N5406G NO 600 V 600 V Semiconductor D21 1 Zener diode 18 V 18V through hole NXP BZX79 C18 NO All products listed are Pb free http onsemi com 23 Table 3 BILL OF MATERIAL Gs NCP1631PFCGEVB Substi Desig Toler Manufacturer Part tution nator Qty Description Value ance Footprint Manufacturer Number Allowed HS1 1 Heatsink 2 9 C W 2 9 C W AAVID 437479 NO THERMALLOY L4 1 DM Choke WI FI series 150 uH 5 A 20 through hole Wurth 7447076 NO 5A Electronics Q1 Q2 2 PNP transistor 2N2907 TO92 ON MPS2907AG NO Semiconductor R2 R6 2 Axial resistor 1 4 W 1kW 196 through hole YES R1 1 Axial resistor 1 4 W 1 8 kW 196 through hole YES R7 R17 2 Axial resistor 1 4 W 2 2W 1 through hole YES R11 R20 3 SMD resistor 1206 1 4 W 10 kW 196 SMD 1206 YES R14 R15 2 SMD resistor 1206
16. A 27k 2 1 4401 kQ eq 89 ovp1 For safety reason several resistors should be placed in series instead of a single Rn one In our application we choose a 1800 KQ 1800 kQ 820 KQ network The exact OVP level is then Dan Rovp2 v 1800k 1800 k 820k 27k out ovp Rovp2 REF 27k V 2 5V 412V eq 90 Remark As illustrated by Figure 11 another effective means to dimension the OVP sensing network is to select b Rovp2 Rgo Rovpi Rtoi Rovp where Roy is a part of the upper resistor of the OVP sensing network Note that v Bea Rio V outihom R REF fb2 M Doan Rovp2 v Rei Rovp Rez 4 out o ut ovp Rovp2 F Da REF Combining two precedent equations it comes Roy p Voutovp Vout nom Ripe i VREF In other words the OVP protection trips when the overshoot exceeds R ae VREF Ripa Conclusions This application note proposes a systematic approach for the eased design of an efficient 2 phase interleaved PFC More specifically this paper provides the key equations and design criteria necessary to dimension the PFC stage The practical implementation of a 300 W wide mains application illustrates the process For detailed information on the performance of a 300 W interleaved PFC designed according to the proposed method you can refer to NCP1631EVB D 3 This application note shows that the efficiency can remain as high as almost 95 at 90 Vims from 20 to 100 of th
17. NCP1631PFCGEVB Interleaved PFC Stage Driven by the NCP1631 Evaluation Board User s Manual Interleaved PFC is an emerging solution that becomes particularly popular in applications where a strict form factor has to be met like for instance in slim notebook adapters or in LCD TVs Interleaving consists in paralleling two small stages in lieu of a bigger one which may be more difficult to design Practically two 150 W PFC stages are combined to form our 300 W PFC pre regulator This approach has several merits like the ease of implementation the use of more but smaller components or a better heat distribution Also Interleaving extends the power range of Critical Conduction Mode CrM that is an efficient and cost effective technique no need for low t diodes Even as reported by NCP1631EVB D 3 when associated to the Frequency Clamped Critical conduction Mode FCCrM this technique yields particularly high efficiency levels about 95 over a large load range at 90 Vims in a 300 W application Furthermore if the two stages are operated out of phase the current ripple is significantly reduced In particular the input current looks like that of a Continuous Conduction Mode CCM one and the rms current within the bulk capacitor is dramatically reduced These characteristics are detailed in application note AND8355 1 This paper gives the main equations that are useful to design an interleaved PFC stage driven by the NCP1631
18. brown out pin Fe ed forward circuitry Vbo BO pin voltage Igo charges the timing capacitor for both phases elay 5 delay brown out dete ction Circuitry for Figure 6 Brown out Block hitp onsemi com 6 NCP1631PFCGEVB As sketched by Figure 6 the brown out block has two functions 1 Feed forward The brown out pin voltage is buffered to generate an internal current Igo proportional to the input voltage average value in conjunction with the pin3 resistor R This current is squared to form the current that charges the internal timing capacitors that control the on time in the two branches As a matter of fact the on time is inversely proportional to the square of the line magnitude This feed forward feature makes the transfer function and the power delivery independent of the ac line level 2 Detection of the line magnitude being too low A 7 uA current source lowers the BO pin voltage when a brown out condition is detected for hysteresis purpose as required by this function In traditional applications the sensed voltage dramatically varies depending on the PFC stage state Before operation the PFC stage is off and the input bridge acts as a peak detector refer to Figure 7 As a consequence the input voltage is approximately flat and nearly equates the ac line amplitude Vin 2 V inimi where Vin rms is the rms voltage of the line Hence the voltage applied to pin7 is R T bo2 V pin7 2 Vin r
19. ch leads to Ros Rocp Where Jin is the total current drawn by the two phases of the interleaved PFC stage The circuit compares Ics to an internal 210 uA current reference for a cycle by cycle current limitation Hence the maximum coil current is lcs loin eq 68 R lin max BC 210 uA eq 69 Finally the ratio Rocp Rcs sets the over current limit in accordance with the following equation Roce l in max Res 210 uA As we have two external components to set the current limit Rocp and Rcs the current sense resistor can be optimized to have the best trade off between losses and noise immunity e Maximum current drawn by the two branches As shown in 1 the following equations give the total current that is absorbed by the interleaved PFC eq 70 max V X lin max 2 IER L DE 2 J1 onem if Vin rms u Sten eq 71 in rms LL 4 Cas 2 f PET 2 2 max V t V t 2B Pin avg HR out nom if V TE EL Lus eq 72 lin max wee 4 2 TEA in rms LL 2 2 Where Vin rms LL is the lowest level of the line rms voltage Pin avg max i the maximum level of the input power Voutnom is the nominal level of the output voltage or the output regulation voltage In our case Vout nom 390 V 90s S 138 dee 2 2 2 2 http onsemi com 15 NCP1631PFCGEVB Hence Pis avg V limax 2 2 ve out nom eq 73 De 4 KS x v2 f Vra _ 325 390 zi liac
20. ck arrangement is possible as portrayed by Figure 9 The regulation and OVP blocks having the same reference voltage the resistance ratio R5 over Royt3 adjusts the OVP threshold More specifically e The bulk regulation voltage is Routt Rous R V _ _ out out out3 V eq 84 out nom Rout2 Rout3 REF The bulk OVP level is Routt Routo R Voto _ _ outi Ce out3 VREF eq 85 out2 The ratio OVP level over regulation level is V R ga ZA Ger eq 86 out nom out2 For instance Rout3 5 x Routz leads to Voutovp 105 X Vout nom As soon and as long as the circuit detects that the output voltage exceeds the OVP level the power switch is turned off to stop the power delivery http onsemi com 17 NCP1631PFCGEVB In our application the option that consists of two separate V sensing networks is chosen configuration of Figure 10 Like for the regulation network the impedance of the monitoring resistors must be 1 high enough to limit the losses that if excessive may not allow to comply with the stand by requirements to be met by most power supplies 2 low enough for a good noise immunity Again a bias current in the range of 100 uA generally gives a good trade off Hence Royo vllt 25kQ 87 ence ow2 T00 uA eq 87 In practice Rovp2 27 KQ was selected and as a consequence V out ovp 1 eq 88 Rovpt Rovp2 VREF In our application our 410 V target leads to
21. e applied The input a voltage range is from 85 V to 265 Vrms NCP1631 Figure 14 NCP1631GEVB Evaluation Board hitp onsemi com 26 NCP1631PFCGEVB NCP1631 Board High voltage probe Voltage source Input Socket 13 to 20 Vac Oscilloscope Power analyzer NOTE The resistive or active load must be Isolated current able to sustain 450 V Input Voltage probe 85 to 265 Vims including transients Figure 15 Test Setup Test 1 Test 3 OCP 1 Apply the input voltage 115 Vrms to the input 9 Set the input voltage to 90 Vrms and the output socket current to 0 8 A 2 Connect a load between the Vout GND 10 Gradually decrease the input voltage while terminals Set the output current Iout to 0 8 A observing the input current with the oscilloscope 3 Place a power analyser able to measure the input until the top of the sinusoid becomes flat as in the power Pin the power factor PF the total blue curve in Figure 16 harmonic distorsion THD 11 Measure the plateau it must be between 7 27 and 4 Apply the VCC voltage 15 Vdc 8 13 A 5 Verify that Test 4 OVP Parameters 12 Observe the output voltage with an oscilloscope Voltage measured between 370 V lt Vout lt Set the triggering level at about 200 V the trigger Vour Vout and GND 409 V position being set at 10 of the screen Program the scope to observ or 100 ms in single acquisition mode TAD Total Harmonic Distortion 13
22. e f is the frequency of the compensator zero _ 1 fe BRR Cp fp1 is the frequency of the compensator high frequency pole 1 CC 2n R2 prg 2 oz 5 181 Ro Cp Cz fot m fpo is the frequency of the origin pole foo http onsemi com 12 NCP1631PFCGEVB Vout nom e Busse 9 Viet Gea Place the zero and the high frequency pole We can obtain a 60 phase boost and hence a 60 phase margin by placing the compensation zero at f 4 and the high frequency pole at 4 x fc where fe is the selected crossover frequency From this it comes that fpi 4 f eq 48 Substitution of the fj and f expressions into Equation 48 leads to Cp Cz _ Cz eq 49 Cp Cz 16 Hence Cz 15 Cp eq 50 Place the pole at the origin to have the proper bandwidth Equation 44 instructs that the static gain of the PFC boost is E R9 Rout 53 8 1012 L kee Vout nom If fo is the desired crossover frequency the pole at the origin must be placed at the load that would set the boost converter pole at the selected compensation zero Hence Ska cl It il SE u eq 51 Go Or fo fi 7 eq 53 Go Rout a Cbulk fo This leads to fe oR eq 54 f po tw 53 8 1012 L Coutk kgo fc V outro This expression simplifies as follows 8 nm 53 8 1012 L eh kgo fo Voutnom eq 55 po 4 H Where kpo is scale down factor of the BO sensing network k
23. e load despite the relatively high switching frequency range that was selected 120 kHz nominal clamp frequency The following table summarizes the key equations useful to design a NCP1631 driven interleaved PFC Another table reports the results of these computations for our 300 W application of interest http onsemi com 18 NCP1631PFCGEVB References 1 Joel Turchi Characteristics of Interleaved PFC Stages Application Note AND8355 http www onsemi com pub Collateral AND8355 D PDF 2 Joel Turchi Designing a high efficiency 300 W wide mains interleaved PFC Application Note AND8354 http www onsemi com pub Collateral AND8354 D PDF Table 1 GENERAL EQUATIONS SUMMARY Coil Selection MOSFET Power Conduction Losses Components Bulk Capacitor loms max BO Upper Resistor Brown out Block BO Bottom Resistor BO Filtering Capacitor Oscillator Frequency No Frequency Foldback Clamp Frequency per Branch Fold Forward Power Threshold Minimum Frequency per Branch f sw max 3 Stephanie Conseil Performance of a 300 W wide mains interleaved PFC driven by the NCP1631 NCP1631EVB D http www onsemi com pub Collateral NCP 163 1EVB D PDF Vin ms K eds Vis rms Pin avg max Nout nem fosc nom Pin avg max V L gt li pk max 2 R img LL ERE Pi avg max 1 2 ic T 3 Nun melu 2 in avg max Vinrms LL Poutmax Ch
24. ed about 30 higher than the expected maximal input power that is Pa 180 Pin agas Pijrr is the input power level below which the circuit starts to reduce the switching frequency Frequency Fold back Rrr is the resistor to be placed between pin6 and ground to control the frequency fold back characteristic e Broin is the resistor that can be placed between the oscillator pin and ground to adjust a minimum frequency The moderate impact on the fosc nom value is not taken into account in the given fosc nom computation equation Rn and Ra are the feedback sensing resistors Royp1 and Royp are the OVP sensing resistors Vout ovp is the OVP output voltage Vrer is the internal 2 5 V voltage reference Rpo1 and Rpo2 are the Brown Out sensing resistors kpo is the brown out scaling down factor k Boo BO Root Hoo fpo is the frequency pole created by the BO pin external capacitor Cpo together with Brei and Rpo2 Itysr is the internal 7 uA internal current source used for hysteresis Vinavg boH is the averaged input voltage at which the circuit starts operation KCN P 2 Be in a traditional PFC stage Vin avg boL is the averaged input voltage below which the Brown out protection trips 2 2 nae T VBO th is the internal 1 V brown out voltage reference um in a traditional PFC stage Rz C and C are the compensation components f is the crossover frequency
25. ed use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 m R Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2163 D
26. ge rating Vout max margin and exhibit a low forward voltage drop Supposing a perfect current sharing the average diode current is the half of the load one l l Dto avg lLoap Pout 0 39 A D1 avg D2 avg 2 2 2 NM T ibo o So the losses are about lLoap Vr 2 per diode i e less than 500 mW per diode using MUR550 rectifiers For each phase the peak current seen by the diode will be the same as the corresponding inductor peak current Two axial MUR550 are selected 3 Bulk Capacitor Design The output capacitor is generally designed considering three factors 1 The maximum permissible low frequency ripple of the output voltage The input current and voltage being both sinusoidal PFC stages deliver a squared sinusoidal power that matches the load power demand in average only As a consequence the output voltage exhibits a low frequency ripple e g 100 Hz ripple in Europe or 120 Hz in USA that is inherent to the PFC function 2 The rms magnitude of the current flowing through the bulk capacitor Based on this computation one must estimate the maximal permissible ESR not to cause an excessive heating 3 The hold up time It can be specified that the power supply must provide the full power for a short mains interruption that is the so called hold up time The hold up time is generally in the range of 10 or 20 ms The output voltage ripple is given by Pout HUES 2 Fine Chuk V eae
27. given by _ fosc nom _ 26 10 8 fsw max nom 2 C eq 12 pin4 For instance a 220 pF capacitor leads to the following clamp frequency 26 10 6 220 1905 118 kHz fsw max nom eq 13 Frequency Fold back The NCP1631 features the frequency fold back function to improve the light load efficiency Practically the oscillator charge and discharge currents are not constant but proportional to power when the load drops below a programmable level as shown by Figure 4 http onsemi com 4 NCP1631PFCGEVB 150 140 130 120 110 100 90 fosc nom 118 kHz 80 70 60 fosc kHz 50 40 30 20 10 0 0 1 02 03 04 0 5 06 07 08 09 1 Vregul V Figure 4 Frequency Fold back Programming the Power Threshold for Frequency Foldback Pin6 of the NCP1631 pins out the signal Vgggur that is proportional to the power that is delivered The resistor Rrr placed between pin 6 and ground adjusts the pin6 current Ipp as follows _ VREGUL FF V E If e lt 105 2 FF lgp 105 pA otherwise As a matter of fact the clamp frequency is also an increasing function of More until it reaches a maximum value for Josc 105 uA fosc fosc nom If VRecuL Reg 105 pA REGUL fosc Rep 1050 fosc om H VngauL lt Rep 105 uA VREGUL Varies between 0 and 1 66 V Since the power that can be delivered is proporti
28. hing losses by turning the MOSFET back on when its drain voltage is at a minimum The value of Rzcp and Rzcp2 to accomplish this is best found experimentally Too high of a value could create a significant delay in detecting the ZCD event In this case the controller would operate in discontinuous conduction mode DCM and the power factor would suffer Conversely if the ZCD resistor is too low then the next driver pulse would start when the voltage is still high and switching efficiency would suffer Over Voltage Protection The NCP1631 dedicates one specific pin for the under voltage and over voltage protections The NCP1631 configuration allows the implementation of two separate feed back networks see Figure 11 One for regulation applied to pin 4 feed back input Another one for the OVP function Vout bulk voltage Vout bulk voltage Vout bulk voltage Rout1 Rovp Rout3 Rovp1 Rfb1 Rovp2 Rfb2 Figure 10 Configuration with Figure 11 Configuration with Two Figure 12 Another Configuration One Feed back Network for Separate Feed back Networks with Two Separate Feed back Both OVP and Regulation Networks The double feed back configuration offers some redundancy and hence an up graded safety level as it protects the PFC stage even if there is a failure of one of the two feed back arrangements However the regulation and the OVP function have the same reference voltage Vggr 2 5 V so that if wished one single feed ba
29. increasing the associated losses grow up In addition all parasitic capacitors charge at a higher frequency and generate more heat 2 EMI filtering is tougher the switching generates high EMI rays at the switching frequency and hitp onsemi com 2 NCP1631PFCGEVB close harmonic levels Most power supplies have to meet the CISPR22 standard that applies to frequencies above 150 kHz That is why SMPS designers often select Fsw 130 kHz so that the fundamental keeps below 150 kHz and then out of the regulation scope Often 65 kHz is also chosen to not to have to damp harmonic 2 too The oscillator frequency is the double of the clamp frequency in each phase The oscillator frequency is then set to approximately 240 kHz Basically Two 150 W FCCrM PFC stages are to be designed This chapter will not detail the dimensioning of the power components in very deep details since their computation is traditional However the main selection criteria and equations are reminded 1 Inductor Selection In CrM and in FCCrM assuming CrM operation at low line full load the maximum peak and rms inductor currents within one branch are P 2 sede eu 2 B _ 2 325 _ Ii x Ser in rms And Maer Se Jecke e 2 1A eq 2 Where Vin rms LL is the lowest line rms voltage Pinavg max is the maximum level of the input average power Kees 2 ae Vout nom is the nominal output voltage regulation le
30. inl that is to receive the ZCD voltage from branch 2 2 A second one monitors pin16 that receives the ZCD signal for branchl The ZCD comparators have a 0 5 V threshold rising with a 250 mV hysteresis Therefore N must be sized such that at least 0 5 V is obtained on the ZCD pin during the demagnetization in all operating conditions The voltage obtained on the ZCD pin is minimal in high line and at the top of the sinusoid leading to Vout v2 Vin rns HL i 0 5 hitp onsemi com 16 NCP1631PFCGEVB With Vin ms HL 265 V and Vout 390 V N must be lower than 30 A turns ratio of 10 was selected for this design A resistor Rzcp is to be added between the phase 1 ZCD winding and pin 16 for branch 1 and another one Rzcp2 between the phase 2 ZCD winding and pin1 for branch 2 Rzcp1 and Rzcp limit the current into or out of pins 1 and 16 This current is preferably set in the range of 2 mA sink and source In general the pins are the most stressed by the sink current obtained at high line Hence Rzcp and Rzcp2 must be selected high enough so that 2 Vin rms HL 2 265 gt S ES eq 83 Rzcp1 Rzcpe2 sach 2m 10 19 kQ mes A 22 kQ was selected However the value of this resistor and the small parasitic capacitance of the ZCD pin also determine when the ZCD winding information is detected and the next drive pulse begins Ideally the ZCD resistor will restart the drive at its valley This will minimize switc
31. is near zero leading to an extremely long discharge time and a very low frequency It is wise to prevent the frequency from dropping below 16 kHz to avoid audible noise issues A simple means consists of placing a resistor RFmin between the OSC pin and ground to force a minimum oscillator discharge current see Figure 5 http onsemi com 5 NCP1631PFCGEVB Oscillator Control Block Figure 5 Adjustment of the Minimum Frequency Assuming that the internal pp current is zero the oscillator period can be computed considering the 35 uA charge current the permanent leakage current generated by fosciminy _ RFmin and the 1 V swing across Cosc swing when the oscillator is clamping the switching frequency Doing this calculation we can deduce the minimum clamp frequency for each branch forced by Rrmin 1 eq 16 pr 2 2 Remin In our application Rfmin 270 KQ forces a minimum frequency of about 20 kHz Remark Ground pin6 to inhibit the frequency foldback If pin6 is grounded accidently or not the circuit operates with the nominal clamp frequency over the whole load range R nasci 02 In Rew 21 is Emin 143000 Brown out Circuitry The brown out terminal pin7 typically receives a portion of the PFC input voltage V As during the PFC operation Vyn is a rectified sinusoid a capacitor must integrate the ac line ripple so that a portion of the Vn average value is applied to the
32. kes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthoriz
33. m Resistor Rao 2 5 27 KQ Feedback 92 u Resistors Feedback Upper Resistor Rg 27k 339 d 4185 kQ oe Se OVP Resistors OVP Upper Resistor Rovpt 27k 229 1 4400 kQ hitp onsemi com 22 NCP1631PFCGEVB Table 2 Cp Capacitor of the E 1 06 10 494 86 nF Type2 Compensation 100 10 6 20 3902 n Loop Cz Capacitor of the Compensation E ES iid i 9e H xd f 0 uF Rz Resistor of the S Maximum Level of the Input Current lin max 4 o Current Limitation Current Sense Resistor 0 2 325 90 _ 325 SUE Over Current Resistor 50 103 64 _ Over Curent etter MET BILL OF MATERIALS Table 3 BILL OF MATERIALS Substi Desig Toler Manufacturer Part tution nator Qty Description Value ance Footprint Manufacturer Number Allowed CM1 1 CM Filter 4 A 2 6 8 mH 4A through hole EPCOS B82725 A2402 N1 NO 250V C2 1 Electrolytic capacitor 100 uF 450V through hole BC 2 22216E 11 NO Components C5 1 X2 capacitor 100 nF 275V through hole RIFA PHE840MB6100MB05R17 NO C6 1 X2 capacitor 1 uF 275 V through hole RIFA PHE840MD7100MD20RO6L2 NO C10 C16 2 Y capacitor 4 7 nF 275V through hole Murata DE1E3KX472MA5B NO C15 1 Ceramic capacitor 220 pF 5 SMD 1206 YES 50V C18 1 X2 capacitor 680 nF 275V through hole EPCOS B32923A2684M NO C20 1 Ceramic capacitor 150 nF 10 SMD 1206 YES 50V C22 C27 2 Ceramic capacitor 1 nF 10 SMD 120
34. ms Foi Foo After the PFC stage has started operation the input voltage becomes a rectified sinusoid and the voltage applied to pin7 is _ 2 2 Minis Ro piny S Root Rbo2 i e about 64 of the previous value Therefore in traditional applications the same line magnitude leads to a BO pin voltage that is 36 lower when the PFC is working That is why a large hysteresis is required Start of PFC operation Figure 7 Typical Input Voltage of a PFC Stage Computing Cho Rbo1 and Rpo2 of Figure 6 1 Define the line levels at which the circuit should detect a brown out and recover operation Our application being specified to operate from 90 Vrms it can make sense to select the following thresholds The system starts operating when the line voltage is above Vin rms bou 81 V 90 of 90 V The system detects a fault when the line voltage goes below Vin rms bor 72 V 80 of 90 V 1 Define the average input voltage when Vpin7 BO pin voltage crosses the BO thresholds Vpin7 rising and falling When the line voltage is below the BO threshold the internal current source Ipgysr 7 WA typically is activated to offer some hysteresis and the circuit recovers operation when eq 17 bo2 v B Lon Rbo2 8 M Rot Rbo2 MAVI boH Dron Pro HYST PORUM Where Vin avg boH is the average input voltage above which the circuit turns on and Vbo th is the BO internal threshold 1 V ty
35. nsation Characterized by the low bandwidth of their regulation loop PFC stages exhibit large over and under shoots when abrupt load or line transients occur e g at start up The NCP1631 dramatically narrows the output voltage range First the controller dedicates one pin to set an accurate Over Voltage Protection level and interrupts the power delivery as long as the output voltage exceeds this threshold Also the NCP1631 dynamic response enhancer drastically speeds up the regulation loop when the output voltage is 4 5 below its desired level As a matter of fact a PFC stage provides the downstream converter with a very narrow voltage range A pfcOK Signal The circuit detects when the PFC stage is in steady state or if on the contrary it is in a start up or fault condition In the first case the pfcOK pin pin15 is in high state and low otherwise This signal is to disable the downstream converter unless the bulk capacitor is charged and no fault is detected Finally the downstream converter can be optimally designed for the narrow voltage provided by the PFC stage in normal operation Safety Protections The NCP1631 permanently monitors the input and output voltages the input current and the die temperature to protect the system from possible over stresses and make the PFC stage extremely robust and reliable In addition to the aforementioned OVP protection one can list Maximum Current Limit the circuit
36. o2 7 60 225 nF eq 31 Se Bot Bee Ee Ze 7410 k 120k F0 In practice four 1 8 MQ resistors are placed in series for Rpo1 for a global 7 2 M resistor and we use a 120 kQ resistor for R55 and 220 nF capacitor for Cpo One should note that the NCP1631 brown out circuitry incorporates a 50 ms blanking delay to help meet hold up times requirement see data sheet Maximum Power Adjustment The instantaneous line current is the averaged value over the switching frequency of the total current absorbed by the two branches of the PFC stage It is given by the following formula Vin R VReGuL fes ES nO E 269 102 kgo V PS in rms http onsemi com 9 NCP1631PFCGEVB Where Ri VREGUL 26 9 102 Kao V s is the expression of the on time in each branch VreGuL is an internal signal linearly dependent of the output of the regulation block VCONTROL VREGUL varies between 0 and 1 66 V Tin t and Vin t are the instantaneous line current and voltage respectively Vin rms is the line rms voltage Lis the coil inductance kgo is scale down factor of the BO sensing network k Hoo BO Root Deg Multiplying Le by Vin one can deduce the instantaneous power R9 VnEGUL Vinel 26 9 1012 L kgo V 2 in rms D eq 33 And averaging the instantaneous power over the line period gives the following expression of the mean input power P 2 R Vagau in avg 26 9 1
37. ogether with some special circuitry to lower the power consumed by the PFC stage in no load conditions More generally the NCP1631 is ideal in systems where cost effectiveness reliability low stand by power and high power factor are the key parameters Fully Stable FCCrM and Out Of Phase Operation Unlike master slave controllers the NCP1631 utilizes an interactive phase approach where the two branches operate independently Hence the two phases necessarily operate in FCCIM preventing risks of undesired dead times or continuous conduction mode sequences In addition the circuit makes them interact so that they run out of phase The NCP1631 unique interleaving technique substantially maintains the wished 180 phase shift between the 2 branches in all conditions including start up fault or transient sequences Optimized Efficiency Over the Full Power Range The NCP1631 optimizes the efficiency of your PFC stage in the whole line load range Its clamp frequency is a major contributor at nominal load For medium and light load the clamp frequency linearly decays as a function of the power to maintain high efficiency levels even in very light load The power threshold under which frequency reduces is programmed by the resistor placed between pin 6 and ground To prevent any risk of regulation loss at no load the circuit further skips cycles when the error amplifier reaches its low clamp level Fast Line Load Transient Compe
38. onal to Vgggur the power threshold for frequency fold back is Rpp 105 uA 1 66 V eq 14 R a PH ver T5810 Pind HL Where Pin FF is the input power below which the frequency reduces Pin HL is the power highest level that can virtually be delivered by the PFC stage This value results from the timing resistor selection see the maximum power adjustment section and is generally set 25 or 30 higher than the application maximum power to offer some margin In our application a 4 7 kQ resistor is implemented on pin 6 Ref 4 7 KQ Hence the frequency folds back when the input power drops below the following Pin pr threshold 4 7 108 uer 1ggio Pihl 30 wn eq 15 In our application the maximum input power is 325 W It is recommended to design the PFC stage so that it can produce at least 25 more than the maximum power it targets In practice Pin HL 494 W has been selected As a matter of fact the frequency folds back when the input power goes below 30 x Pin HL that is about 147 W Forcing a Minimum Frequency The NCP1631 reduces the frequency down to virtually zero As detailed in the data sheet and shown by the simplified oscillator representation of Figure 5 the circuit lowers the frequency by diminishing the Ipp current When this current is near zero a 35 4A current source is still available for charging the oscillator capacitor but the discharge current
39. output voltage in all conditions included sharp line load transients http onsemi com 11 NCP1631PFCGEVB Hence in most applications it can be sufficient to place a low frequency pole that drastically limits the bandwidth However it is recommended to implement a type2 compensation as represented by the following figure GEA 200 uS VREGUL Figure 8 Regulation Trans conductance Error Amplifier Feed back and Compensation Network 1 The circuit disables this capability dynamic response enhancer until the PFC stage output voltage has reached its target level that is when the pfcOK signal of the block diagram is high This is because at the beginning of operation the pind compensation network must charge slowly and gradually for a soft start up The output to control transfer function brought by the type 2 compensator is V 1 sR C control zvz eq 45 Ro Cz p sh uc i6 C Wher R Vout nom 97 Vert Gea Gea being the gain of the trans conductance error amplifier OTA KA nom the output nominal voltage V regulation level and Vggr the OTA 2 5 V voltage reference Actually The NCP1631 PWM section does not directly use Vcontrol but VREGUL Taking into the 5 9 resistors divider that links Vcontrol and VREGUL it comes VREGUL _ 1 sR C eq 46 Vout HPH Cz p Ss Cz Cp 1 Size FG Hence we have 142 8 VREGUL _ 2n E eq 47 Vout S 14 S 21 foo 21 fot Where
40. pically Hence eq 18 Ro R S bo1 bo2 Visio 5 e sam Puoi liver http onsemi com 7 NCP1631PFCGEVB As long as the line is above the BO threshold the internal current source IgysrT zs 7 UA typically is off and the BO pin voltage is fso Vpin7 Kgo Vin avg 8 fu eq 19 Where Vin avg is the average input voltage fiine is the line frequency fpo is the sensing network pole frequency f Root Deg SE Tee Root Dees Cpo kgo is scale down factor of the BO sensing network k zs Hoo BO Root Hoo 4 2 80 3 fine of Equation 19 enables to take into account the BO pin voltage ripple first harmonic approximation A brown out fault is detected when the BO pin voltage goes below Vpo th BO internal threshold that is 1 V typically Hence the BO protection triggers when the average voltage goes below the Vis avg bor level expressed by the following equation The term Vsoqn V ar N fzo 3 fine Where Vin avg boL is the average input voltage below which the circuit turns off fgg is the sensing network pole frequency f Root t Deg BOT gs Root Poo Cp eq 20 and fije is the line frequency 2 Calculation From Equation 20 we can deduce the following expression of the brown out scale down factor R Veotth rae bo2 a th eq 21 BO Root Boo fso Vin avg bo 3f Ine Substitution of Equation 21 into Equation 18 lead
41. rent resistor is selected so that it does not consume more than about 0 2 of the maximum power PRsense 0 2 x Pin avg max http onsemi com 1 NCP1631PFCGEVB Table 2 90 390 2 90 320 390 120k 320 lL pk max e d 90 5 0A 140 uH Coil Selection 1 320 lj ims max F B 5 90 21A A 150 uH 6 Apk 2 5 Arms coil was selected Power MOSFET 1 S20 8 2 a 3 R ES DS on Components Conduction Losses 3 Roson 90 3x 390 300 M 8 8V out pk pk 1004 2x 60 390 20V fine 60 Hz 2 300 tHoLD uUP Bulk Capacitor Chuk 7 3002 3307 0 014 tig p up 8 16 2 325 809 UG wl max D xs 390 13A 115 65 1 19 Z 7450 kQ Root 7 10 6 1200 10 116kQ 65 10 120 kQ SD 19 BO Upper Resistor gt 7200 kQ BO Bottom Resistor bo2 Brown out Block Bote SE 7200 k 120 k e EE Cho Ss 7200 k 120 k 10 Pd ine BO Filtering Capacitor fine 60 Hz 120k Timing Resistor Pin3 Resistor R 4026 10 7200k 120k 150 u 400 16 2kQ 18 kQ gt Piy u 494 W Oscillator Frequency _ 52 106 _ No Frequency Foldback fosc nom 220 1072 236 kHz Clamp Frequency fosc nom Viel 7 B 118 khz Fold Forward Rer 4700 Q CX i 15810 Q l via 15810 Q i SS T id 2 1 m Minimum Frequency Kasel nep j amp 19 8 kHz er Branch g S i rU cde ay Dui p 2 270k 220p 022 RE k 143k Feedback Botto
42. s to eq 22 feo Vin avg boH ES m i 8 SI Root IHysT We can then deduce the following expression of Rpo1 f Vin avg boH DE E del eq 23 I R bo1 HYST Re using the above Rpo1 expression one can deduce Rpo2 from Equation 21 Drei D M bo2 Vin avg boL fao 1 Veoh 3 fine hitp onsemi com 8 eq 24 NCP1631PFCGEVB If as a rule of the thumb we will assume that fine e that is 6 Hz in the case of a 60 Hz line we obtain fine 10 V n V HH in avg boH in avg voL 3 fing m 4 Vin avg boH E 0 967 j KEN eq 25 ee luvsr Rbo2 Root E Root eq 26 Vin avg boL E fao a4 0 967 Vin aval boL 4 Veoth 3 fiine Noom As an example we will consider the traditional PFC stage where the average value of the input voltage is 36 lower when the circuit operates as illustrated by Figure 7 So if we select e The system starts operating when the line voltage is above V 81V wuel boH The system detects a fault when the line voltage goes below Vins bol 72V The corresponding average input voltage thresholds are Vin avg boH 2 Vin rms boH 2 81 eq 27 And 2 2 2 2 Vin avg boL Vin rms bo a 72 eq 28 We have then to solve 2 81 os EE 72 eq 29 Root CEN TES 7410 kQ 103 Rico E 120kQ eq 30 0 967 2 2 72 Du R 7410 k 120k Cis _ bo1 b
43. uk O V 8 2 Din gelt 3x V out nom Vout pk pk out nom 2 Poutmax Iuoup up V M Cpu 7 2 out min 2 16 2 nale Pout max on Vin rms LL C Vout nom Vout nom f Vin avg boH E DER i i e 2 out nom HYST Root Vin avg bol fso 1 Voth 3 fine Root Di bo Sr Bun Rbo2 fgo Le edu 52 10 6 Cosc C R 4026 10 kgo fosc nom _ foscinom _ 26 10 6 nom 2 Cosc f sw max Ree Iwer 15819 g Pin 1 Remin 114000 2 R Emin 2 Cosc 0 22 zb In R 143000 Fmin http onsemi com NCP1631PFCGEVB Table 1 GENERAL EQUATIONS SUMMARY Feedback Bottom Resistor Feedback Resistors outnom VREF Feedback Upper Resistor OVP Bottom Resistor OVP Resistors i OVP Upper Resistor outovp _ VREF Cp Capacitor of the 1 06 HL Type2 ti ype Compensation OL V out nom Loop C Capacitor of the 45 C Compensation Type2 Compensation p Rz Resistor of the Type2 Compensation n Cz f 2 2 Pin avg max Vout nom 1 in max Vin rms 4 V cuim V2 Vi mu Vout nom fV EE in rms LL 2 2 Maximum Level of the Input Current 2 2 Pin avg max Vout nom Current Limitation i Dip melt A 2 V meli Vout nom if V z negt 2 2 Rcs Vin rms LL Current Sense Resistor gt inavg max Rocp Fos ug ae 210 10 6
44. ut of the error amplifier is pinned out for external loop compensation pin5 http onsemi com 10 NCP1631PFCGEVB Computation of the Feed back Regulation External Components A resistor divider consisting of Ry and Rp2 of Figure 8 must provide pin2 with a voltage proportional to the PFC output voltage so that Vpin2 equates the internal reference voltage Vagr 2 5 V when the PFC output voltage is nominal In other words Ripe Riot Rips Voutnom VREF eq 38 Or Riot V Pio VREF Another constraint on the feed back resistors is the power it dissipates Rp1 and Rp2 being biased by the PFC output high voltage in the range of 390 V typically they can easily consume several hundreds of mW if their resistance is low Targeting a bias current in the range of 100 uA generally gives a good trade off between losses and noise immunity This criterion leads to out nom e eq 39 VREF R A pe 100 uA 25 kQ eq 40 In practice Rgp2 27 KQ was selected for our application Following Equation 39 Rp is given by V Riot Dro EZ E 1 eq 41 We target a 390 V regulation level hence 390 Re 27 KQ S20 1 4185KQ ea 42 Like for the input voltage sensing network several resistors should be placed in series instead of a single Rp1 resistor In our application we choose a 1800 kQ 1800 KQ 560 kQ network This selection together with Rjp2 27 KQ leads to Rit T Rez y _ 1800k 1800k
45. vel In our application Vin rms LL 90 V Vout nom 390 V Pinavg max 325 W assuming a 92 global efficiency that is a conservative value that offers some margin As aforementioned the frequency clamp for the two branches is set to about 120 kHz The inductor must be large enough so that Critical conduction Mode is obtained at low line full load where the conditions are the most severe This constraint leads to the equation below where Ssw max is the 120 kHz clamp frequency en Vout 2 iras bid Pi avg max i Vout nom Fsw max Vin rms LL L eq 3 In our application this leads to 902 390 2 90 825 390 120 108 Finally a 150 uH 6 Apk 2 5 Arms coil was selected 2 Power Semiconductors The bridge diode should be selected based on the peak current rating and the power dissipation given by 139 uH eq 4 eq 5 1 8 V 329265 18 Mer Gy 65 V _ 4 2 y Pin avg max bridge mo vf V P in rms LL Assuming a 1 V forward voltage per diode Vr 1 V the bridge approximately dissipates 6 5 W For each branch the MOSFET is selected based on the peak voltage stress Vout max margin and on the rms current flowing through it Jy rms ee V2 WVinems uL 29 EE Mlms 8 Vintrms LL 3 Voutnom 8 90 3 x 390 Using a 600 V 0 4 Q FET SPP11N60 will give bs conduction losses of assuming that Rps on increases by DEY R2 gt
Download Pdf Manuals
Related Search