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MSM6636/6636B User's Manual

1. 18 Pin Plastic DIP 18 Pin Plastic QFJ 24 Pin Plastic SOP CJ BER AV AVoo i O SID 275 E Bo 2 17 RES o BI eh E Bl B 3 Kelt E i 16 B 3 S INT GC Bl 4 rop Br ISITXD NC BO 5 IRXD Bos 5 app c SCLK AGND 6 DA AGNDIS RGE AGND Uc 7 PAD yc 7 man UC S M N M N 8 O njosco Ge DGND DGND 9 10 0SC1 As z 5 E 2 NC No Connection 2oOioo 2 MSM6636B 24 Pin Plastic SOP 30 Pin Plastic SSOP NC No Connection Refer to Chapter 9 for package dimension information MSM6636 6636B User s Manual Overview 1 4 Pin Description 1 MSM6636 Pin Name un 1 0 Function DIP QFJ SOP AVop 1 1 Analog power supply pin BO 2 2 O LAN BUS output BI 3 3 LAN BUS input Bl 4 H LAN BUS input BO 5 5 O LAN BUS output AGND 6 9 Analog ground pin U C 7 10 UART 0 clock synchronous serial 1 select pin M N 8 11 l MPC mode 0 normal mode 1 select pin DGND 9 12 Digital ground pin OSCT 10 13 O Crystal or ceramic resonator oscillation output OSCO 11 14 Crystal or ceramic resonator oscillation input AD e CN SCLK PAE 13 16 Serial clock input parity select pin RXD 14 20 l Serial data input pin TXD 15
2. Unit mm QFJ18 P R290 1 27 13 39 0 13 gt 12 45 0 08 gt a onn INDEX MARK Spherical surface 0 65 TYP 1 27 0 81MAX SEATING PLANE 0 180 Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating 251m Package weight g 0 50 TYP Rev No Last Revised 3 Nov 11 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times MSM6636 6636B User s Manual Package Outlines and Dimensions Unit mm SOP24 P 430 1 27 K 15 95 0 1 lt Q2 HAA AHA HAAS as s e EN r hutt Y le 2 05 0 3 INDEX MARK y FS Mirror finish x 1 27 x 0 99 TYP E 9 35 0 1 50258 E y0 10 j 1 23TYP 710 12 X SEATING PLANE Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating 251m Oki Electric Industry Co Ltd Package weight g 0 58 TYP Rev No Last Revised 5 Oct 13 1998
3. IFR Type 2 SOF Header DATA CRC EOD ID1 i IDn EOF Multiple responders send ID sequentially as in frame responses IDs are sent in sequence from the responder with the highest priority ID IFR Type 3 SOF Header DATA CRC EOD IFR DATA CRC EOF One selected responder returns multi byte data with CRC as IFR B Physical address or functional address of receive node The Y bit at the 1st byte A of 3 byte header determines whether an address is physical or functional The 2nd type B indicates the target address C Physical address of transmit node Indicates the physical address ID of transmit node D Data 0 to 8 bytes of arbitrary data to transmit is written Data can be increased decreased in byte units The maximum number of bytes is 8 including response E In frame response IFR Determined by the bit configuration of message type at the 1st byte A of header See the classification table of IFR types MSM6636 6636B User s Manual Communication Formats 2 2 PWM Bit Format Pulse Width Modulation at 41 6 kbps Typ i TP1 1 Inn TP2 Le Si 1 Dominant 1 n Passive TP3 4 i ra I Dominant S l o Passive l TP4 1 r Si Dominant SOF Passive TP5 ra gt I I Dominant i TP1 i p4 i EOD N i Passive i I Dominant EOP
4. a Transmission stop Node B iu Timing in Node A Break Transmission during Node B Transmission The following shows how the MSM6636 6636B operate when a break signal is received State at Break Reception Operation e Stops transmission operation judges the contention loss generated during communication mE e The break interrupt flag is set During transmission operation n e Even though an auto retransmission mode is set the frame that stopped the transmission by the break reception is canceled Therefore the retransmission operation is not carried out During transmission standby such e Retransmission standby is canceled Therefore the retransmission as bus busy in setting the auto operation is not carried out after break retransmission mode e The break interrupt flag is set e Stops the reception operation The message on response during reception is not stored in a reception uring reception operation register e The break interrupt flag is set During transmission standby e The break interrupt flag is set MSM6636 6636B User s Manual Function Details 5 10 Fault Tolerant Function The following shows a detection flow in the case that BUS and BUS are short circuited to Vpp and GND BUS s short circuit to GND BUS 48 us m BUSCH A 4 INT L 1 BUS s short INV ABN Clear pr
5. High order 2 bits communication type Low order 6 bits communication address 01 WR Register Write destination address 10 RD Register Read destination address AD X m RD N l9 Ae Db Y D d Dr E Pl XD START STOP P Even parity MSM6636 6636B User s Manual CPU Interfaces MPC Mode PIN CONNECTION CPU MSM6636 4 Vop SCLK PAE Parity Select SOUT gt RXD U C SIN TXD 7T A D INT lt INT MN CA TIT In MPC mode an MPC bit is added between the MSB bit D7 of serial data and the parity bit P indicating that this 8 bit data is address information if MPC 1 and that it is data itself if MPC 0 Therefore unlike normal mode A D pin control is unnecessary Connect the A D pin to GND Except for an MPC bit that is added to serial data everything including timing is the same as in normal mode In UART transmit receive is controlled by the shift clock with a 1 64 source oscillation frequency If UART is used set the baud rate at the CPU side SCLK PAE pin H selects parity yes L selects parity no RD Do X D1 KS X ps X pe Yor XmecY P TXD START STOP P Even parity MPC 1 address 0 data Note If an abnormality occurs at the host CPU serial interface part missing bit synchronization shift etc reset the MSM6636 from the CPU to initialize the interface circuit then st
6. Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times MSM6636 6636B User s Manual Package Outlines and Dimensions Unit mm SSOP30 P 56 0 65 K 9 7 0 1 AAA AAA AAA AAA alte O 3 ol e MIO INDEX MARK O 0313 0 05 Mirror finish 0 65 VARN 0 3 TYP 0 24 0 07 ao 0 07 0 130 3 E a Lo a evi s L o SEATING PLANE Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating 5um Oki Electric Industry Co Ltd Package weight g 0 19 TYP Rev No Last Revised 5 Dec 5 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mounting conditions reflow method temperature and times MSM6636 6636B User s Manual First Edition June 1995 Second Edition Jul
7. Passive l i I I Dominant TP1 i i D r x l D T E ed l TP1 24 us assive i TP2 7us P TP6 Y TP3 15 us I I Dominant TP4 2 81 us BRK i TP5 48 us Passive TP6 39 us I Chapter 3 INTERNAL REGISTER DETAILS MSM6636 6636B User s Manual Internal Register Details 3 3 1 INTERNAL REGISTER DETAILS Internal Address R W Contents Status at Reset 00H 0AH W Transmit register Undefined OBH 12H W Response register Undefined 13H 14H W Transmit status register 00H 15H 1FH R Receive register Undefined 20H R Receive data length register 00H 21H W Initialization read completion indication register 22H 24H RAN Interrupt request flag 00H 25H 27H RAN Interrupt enable flag 00H 28H W Sleep command register 00H 29H W Break command register 00H 2AH R W Mode setting register Undefined 2BH R W Physical address register Undefined 2CH 3AH R W Functional address register Undefined 3BH R W NAK register Undefined Transmit Register MSB LSB 00 H P2 P1 PO K Y Z1 ZU Communication Type Write priority and type of the message 0 1 03 0A MSB LSB RA7 RA6 RAS RA4 RA3 RA2 RA1 RAO Write physical address or functional address of receive node MSB LSB D7 D6 D5 D4 D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO Write arbitrary data for tr
8. The internal selectable frequency divider will realize J1850 specified transmission speed from various source oscillation such as CPU clock out or other oscillator Set the division ratio according to the source oscillation for use by referring to the table below D2 D1 and DO 1 1 1 are used for bus monitor For details see Section 8 Bus Monitor Function Source Oscillation Division Ratio D2 D1 DO 4 MHz 1 4 0 0 0 5 MHz 1 5 0 0 1 8 MHz 1 8 0 1 0 10 MHz 1 10 0 1 1 12 MHz 1 12 1 0 0 16 MHz 1 16 1 0 1 2MHz 1 2 1 1 0 Selecting NAK return yes no NAK This bit selects whether NAK register contents should be sent as a response or not when the MSM6636 6636B is not in response standby status and receives a response request in IFR type 3 0 Do not return NAK register value 1 Retum NAK register value Setting automatic retransmission function N1 NO N1 Selecting the function of retransmission in the case of non ACK 0 Retransmission twice 1 No retransmission This is a function that automatically retransmits when a response is not returned even though an IFR request was sent NO Selecting the function of retransmission in the case of being lost contention 0 Retransmission twice 1 No retransmission This is a function that automatically retransmits when lost in contention during simultaneous transmission MSM6636 6636B User s Manual Internal Register Details LAN BUS outpu
9. only switched to e Bus input is recovered BUS only switched to e Bus input is switched to the BUS only differential input of BUS and BUS At the bus idle status when BUS is short circuited to Vpp the input of LAN bus is switched to communicate normally by detecting the BUS s short circuit to V pp through the same flow as the case of the BUS s short circuit to GND as stated above When BUS returns to the normal status the inputs of both BUS and BUS are switched as reception inputs and the reception status of a normal LAN bus is given as before If BPV flag is then cleared all interrupt requests on LAN bus are cleared Chapter 6 APPLICATION EXAMPLE MSM6636 6636B User s Manual Application Example APPLICATION EXAMPLE Host CPU and J1850 Line Connection Example 1 Example of connection of host CPU and J1850 line with the MSM6636 is shown below Unit A TER AA A VEA EE ee er Host CPU MSM6636 ag e 2 I I I DVoo AVoo R es SOUT RXD 2 I B 1 We snp no 806 LDC INT INT m CLKOUT Osco B MANN E oPEN40SG 1 C R SCLK PAE BIC AN 6 N I L KJ U C Re 2D MN BO WAT i A D BZD RES TIT RES DGND AGND Rs l I i i i 3 777 Unit B A T le eee ye sere I I i Y I I i EL 4 METIRI el Rp Ro A Bus Bus The above connection example is when UART MPC and parity nol
10. An optimum system can be constructed by selecting an optimum host CPU number of ports A D converter yes no for the control target and combining it with the MSM6636B Insert a capacitor between the power supply and GND as a countermeasure for noise It is recommended that a small capacitance bypass capacitor and a large capacitance filter capacitor be connected in parallel Typical capacitors are as follows 0 01 to 0 22 uF Ceramic capacitor 10 to 100 uF Tantalum capacitor 6 2 C POWER ON Y Reset MSM6636 6636B Set mode Write to address 2AH Ze Set physical address Write to address 2BH Set functional address Write to addresses 2CH 3AH Set interrupt enable flag Write to addresses 25H 27H Set initialization completion command Write to address 21H Initialization completed MSM6636 6636B User s Manual Application Example Initialization Routine Example Set the RES pin to a low level to reset the device Set division ratio of source oscillation D2 to DO Select NAK return yes no NAK Set automatic retransmission function N1 NO This setting is kept until the device is powered down and is not reset by the RES pin input Set a physical address ID Write an inherent address on the network This setting is not reset by the RES pin input Set the function address register Up to 15 types of address values c
11. 1 1 1 1 OVerVieW neto a RR RR ete EE EE En 1 1 1 2 He tures Em 1 1 13 Pin Configuration EE 1 2 1 4 Bin Description es oil 1 3 LS se EE 1 4 2 COMMUNICATION FORMATS 2 1 2 1 A eege oer RRE een ed Ee e ODER PRU 2 1 2 30 PWM Bit Format nte iii ome eer ei 2 4 3 INTERNAL REGISTER DETAILS 3 1 3 1 Transmit Register oce Dez en tp ede chi esie Ie ie ede trt e cna 3 1 3 2 Response L see oe AAS ide AS le as 3 2 33 Transmit Status TE 3 2 3 4 Receive Register nai son Rinne E a Saletan nes 3 3 35 Receive Data Length Register ern mn ec e ires 3 5 3 6 Initialization Read Completion Indication Register sss sese esse eee 3 5 K Interrupt Request Bleser rege EBEN ge 3 5 3 8 Interrupt Enable Flag ME 3 7 3 9 Sleep Command AA eite eT Den P Tee Di EE Reb re EEN 3 7 3 10 Break Command Register iiiter e ERE ar e ete ip TED TATO RY ES TT Ke Tag 3 8 3 11 Mode Setting Register eicere EE E E EE EEE EEE EEEE E TOS EE TE Ehe 3 9 3 12 Physical Address UA eoret eee mte e pe rie ER e EE E rE Ea Ei 3 10 3 13 Functional Address Register eite eet eo ete eet eee rire Een 3 10 3 14 NAK Register eio Sete eb P rp dass 3 11 4 CPU INTERFACES 4 1 4 MSM6636 eee ute e e EENEG Hed 4 1 4 1 1 Clock Synchronous Serial Interface 4 2 4 1 2 UART Interface Start Stop Synchronization System 4 5 4 23 Eeler EE 4 8 4 24 Parallel Interface comics caia as 4 8 5 FUNCTION DETAILS 5 1 9 1 Arbitration PUNCH ONS ione O 5 1 527 Ad
12. 13 8 BUS MONITOR FUNCTION 8 1 9 PACKAGE OUTLINES AND DIMENSIONS 9 1 Contents 2 Chapter 1 OVERVIEW 1 1 1 1 2 MSM6636 6636B User s Manual Overview OVERVIEW Overview The MSM6636 6636B are transmission controllers for automotive LAN that conform to data communication protocol SAE J1850 These LSI devices can realize a data bus topology bus LAN system that employs the PWM bit encoding method 41 6 kbps In addition to a protocol control circuit the MSM6636 6636B have an oscillation circuit host CPU interface a transmit receive buffer and a bus receiver circuit thereby decreasing the load on the host CPU MSM6636 The host CPU is accessed through clock synchronous serial UART MSM6636B The host CPU is accessed through parallel interface Features Conforms to SAE J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE issued August 12 1991 CSMA CD carrier sense multiple access with collision detection Internal transmit buffer 1 frame and receive buffer 2 frames Bit encoding PWM pulse width modulation Transmission speed 41 6 kbps Multiaddress setting 1 type of physical addressing and 15 types of functional addressing Address filter function by multiaddressing broadcasting possible Automatic retransmission when lost in contention or in the case of non ACK Supports 3 types of in frame responses 1 Single byte response from a single recipient 2 Multibyte response from a single recipient wi
13. ALE RD gt RD WR gt WR Pxx CS Pxx RES INT INT J1850 Bus MSM6636 6636B User s Manual CPU Interfaces WRITE PROCEDURE 1 RN eg Apply a L level to the CS pin to enable parallel interface Apply a H level to the ALE pin Set address values to the ADO to AD7 pins Apply a L level to the ALE pin Set up the addresses at the fall of ALE Apply a L level to the WR pin Input date to the ADO to AD7 pins Apply a H level to the WR pin to write data Data writing ends at the rise of WR Apply a H level to the CS pin to terminate the use of parallel interface CS ADO 7 Address Data Figure 4 1 Write Timing READ PROCEDURE 1 SES eng Apply a L level to the CS pin to enable parallel interface Apply a H level to the ALE pin Set address values to the ADO to AD7 pins Apply a L level to the ALE pin Set up the addresses at the fall of ALE Apply a L level to the RD pin to read data Data reading starts at the fall of RD Apply a H level to the RD pin to end reading Data reading ends at the rise of RD Apply a H level to the CS pin to terminate the use of parallel interface CS ADO 7 Address Data ALE RD Figure 4 2 Read Timing MSM6636 6636B User s Manual CPU Interfaces WRITE PROCEDURE 2 Once address values have been
14. Data input to RXD is sampled at the rising edge of SCLK 4 8 bits of read data is sent from TXD output synchronizing to SCLK with LSB first Sample the read data at the rise of SCLK at the CPU side In MSM6636 data transmit and receive are simultaneous so in the case of continuous read set the RXD pin to H or L 5 Automatic increment of read destination address values operate every time one data reading ends This makes continuous data reading possible COMMUNICATION TYPE AND COMMUNICATION ADDRESS 7 6 5 4 3 2 1 0 Mt mo AS 4 as a2 at o High order 2 bits communication type Low order 6 bits communication address 01 WR Register Write destination address 10 RD Register Read destination address A SCLK v3 E En Q9 3 Ss RXD e wi E D2 X D3 x D4 X D5 X D6 Vo TXD Do p X D2 X ps bs X D5 X De Kor LA LM G ao X AL Notes 1 In the MSM6636 data is actually sampled at the A D pin at the rise of the final SCLK of 1 frame to determine whether data 1s address information or data itself Set up the A D pin before the final SCLK input 2 In the MSM6636 DO is output to the TXD pin when setting transmit data to the transmit register is completed D1 and later data are output synchronizing to the rise of SCLK For details see Section 7 4 AC Characteristics 3 In the MSM6636 RXD data is sampled at the rise
15. Hold Time SCLK High to A D High Low tan 8t ns Time Interval between SCLK Frames tuni 8t ns Time Interval between SCLK Frames taz 16to ns L t osco JU i tck w u lokaw i pt 1 SCLK L vtsasti Les i A RXD X 0 X Lem gt XD gt S O I tas 1 Lat AD X 1 X i SCLK I A tints 2 1 Final SCLK Rise of 1 Frame 1 Between Communication type WR and address setting frame and WR data frame Between one WR data frame and the next WR data frame during continuous WR 2 Between Communication type RD and address setting frame and RD data frame Between one RD data frame and the next RD data frame during continuous RD MSM6636 6636B User s Manual Electrical Characteristics e UART Don AVpp 5 V 10 Ta 40 to 125 C Parameter Symbol Min Typ Max Unit Setup Time A D High Low to STOP bit High tuas 0 ns Hold Time STOP bit Low to A D High Low uan 0 m ns Output Delay Time START bit Low toTXD High turo 48t0 50to 100 ns Time Interval between Write Frames 7 tints 0 ns Time Interval between Read Frames 7 lira 10to ns m to OSCO EE I luas I tun I i iT I A D KA EA I I 3 I I RXD X H Y STOP T A START A X I lura 1 15 M TXD J turo A START A ME STOP bit Termination 3 Between Communication type WR and address setting frame and WR
16. If BNG flag is then cleared all interrupt requests on LAN bus are cleared When the disable setting bit NBO of LAN BUS output is 0 the LAN BUSCH output is disabled when BNG flag is set and the LAN BUSCH output is enabled when BUS returns to the normal status MSM6636 6636B User s Manual Function Details BUS s short circuit to V pp BUS Bus A INT A 4 4 L 2 BNV flag is set BNV Tags set Clear processing of BNV flag Bus input is switched to BUS only BUS Ys short circuit to Vpp At a bus idle status when BUSCH is short circuited to Vpp the abnormality of LAN bus is not detected until messages are output on LAN bus until the status of LAN bus is changed because of no change at the status of LAN bus When the messages are output on LAN bus the interrupt request flag BNV is set from judging that BUS is short circuited after a fixed time Then the BUS input only is switched to the reception input At the bus idle status 1f BNV flag 1s cleared the abnormality of LAN bus is not detected until messages are again output on LAN bus When the disable setting bit NBO of the LAN BUS output is 0 the output drive of the LAN BUS output is disabled when BNV flag is set After a short circuit is detected when a frame of communication finishes the status of LAN bus returns to the bus idle status and
17. T T T T T T U U U U U U U U U U U U U U U U U U U U U U U U U U U U T T T T T T T T T a A a x EP 3 N N 1 N N N 1 1 1 1 1 1 N BE re TAR se G ss l l I l l l U l l U l l l l T TL 1T 1T 1 T 1T 1 T T T T 1 T E AE E E WD c Se sicui i m 1 3 CH E udo XI Se Hb i U U U I U U U l U l l l l l l aq 1 1 L l l 1 L l 1 1 1 1 1 E KA A Sa Sr ee EBs DEC OP UE IUD SE vro SEPIUS D lA ET AIAIT ER ed EE U U U U U I U U U U U U U U U U U l l U l l l U l l l U l l l l l l t t t t t t t t t t t t t t t t t l l U l l l U l l l U l l l l l l 0 A Xp e e het e 2 0 2 4 6 8 10 12 14 16 18 f MHz MSM6636 6636B User s Manual Electrical Characteristics 7 4 AC Characteristics 7 4 1 PWM Bit Timing DVpp AVpp 5 V 10 Ta 40 to 125 C Set at 41 6 kbps Transmit Receive Parameter Symbol f 7 Unit Min Typ Max Min Max Bit Length TP1 23 64 24 00 24 36 21 00 28 00 us 1 Dominant Width TP2 6 90 7 00 7 11 5 00 12 00 us 0 Dominant Width TP3 14 87 15 00 15 23 13 00 20 00 us SOF Dominant Width TP4 30 54 31 00 31 47 29 00 36 00 us SOF BRK Length TP5 47 28 48 00 48 72 45 00 52 00 us BRK Dominant Width TP6 38 42 39 00 39 59 37 00 44 00 us EOD Bit Length TP7 47 28 48 00 48 72 43 00 51 00 us EOF Bit Length TP8 70 92 72 00 69 00 76 00 us EOF IFS Bit Length TP9 94 56 96 00 86 00 us 0 Passive Width TP10 8 86
18. The bits to which a flag is not allocated will always read 0 MSM6636 6636B User s Manual Internal Register Details INTERRUPT CAUSE DETAILS LEN Exceeded 12 bytes maximum frame length of receive message ABN LAN bus was in dominant status for more than specified time 48 usec at 41 6 kbps Bl and BI both received a signal indicating passive status even though a signal indicating dominant status was output from BO and BO to both lines of BUS and BUS Local D P bus drive abnormality or LAN bus abnormality detected If one line is normal the communication is made by the normal line and the interrupt in D P flag does not occur OVER Received next message before host CPU completed receive message processing Overrun error CRC Error was detected during CRC check Received abnormal format message FORM 1 Received SOF during message receive 2 Detected EOD or EOF at location other than byte boundary INV Received signal in undefined bit format IFS Another node started transmission during IFS Even when IFS flag is set if the receive frame is normal receive operation is executed BUSY Lost in contention for all specified number of retransmissions NOACK Received no response for all specified number of retransmissions NRSP Type 3 IFR request message was received but return data was not in response register not in transmission standby sta
19. mode is used as the host CPU interface and when CLKOUT output of the host CPU is used as the clock for the MSM6636 An optimum system can be constructed by selecting an optimum host CPU number of ports A D converter yes no for the control target and combining it with the MSM6636 Insert a capacitor between the power supply and GND as a countermeasure for noise It is recommended that a small capacitance bypass capacitor and a large capacitance filter capacitor be connected in parallel Typical capacitors are as follows 0 01 to 0 22 uF Ceramic capacitor 10 to 100 uF Tantalum capacitor MSM6636 6636B User s Manual Application Example 2 Example of connection of host CPU and LAN bus with the MSM6636B is shown below Unit A id e TE EE E E 1 Host CPU MSM6636B NES adl T i DVoo AN Ge ADO 7 4 ADO 7 A N NE ALE BO ANM RD RD l WR WR Bl MA s Pxx 08 a n i ES INT INT BIS LAA I M CLKOUT OSCO Re FA DI i OPEN 0SC1 BO l 5ZD i RES RES DGND AGND Rs l I i er 777 Unit B ENEE ER yy ENEE EE II TTT T EE E ESA I EN I i e I I I E ER S I I Rp eeng a o Shop ee Ee a op Rall Ro l Le Bus Bus The adove connection example is when parallel interface is used as the host CPU intreface and when CLKOUT output of the host CPU is used as the clock for the MSM6636B
20. of SCLK MSM6636 6636B User s Manual CPU Interfaces MPC Mode PIN CONNECTION CPU MSM6636 4 SCLK SCLK PAE SOUT gt RXD ee SIN Le TXD U C A D INT L lt INT MN GA TIT In MPC mode an MPC bit is added after the MSB bit D7 of serial data indicating that this 8 bit data is address information if MPC 1 and that it is data itself if MPC 0 Therefore unlike normal mode A D pin control is unnecessary Connect the A D pin to Vpp or GND Except for adding an MPC bit to the serial data everything including timing is the same as in the normal mode SCLK T T d RXD po ES D2 X D3 X D4 X ps X De X or Ympc TXD po X pt X D2 X ps X o4 X os X os X or X MPC x MPC 1 address 0 data 4 1 2 UART Interface Start Stop Synchronization System MSM6636 6636B User s Manual CPU Interfaces Normal Mode PIN CONNECTION CPU MSM6636 Vop Pxx A D SCLK PAE 4 Parity Select SOUT gt RXD U C SIN TXD 7T e Mon INT INT M N A D pin input selects whether serial bus data is address or data information For control purposes connect the A D pin to the general purpose port Pxx output etc ofthe CPU In UART transmit receive is controlled by a shift clock with a 1 64 source oscillation frequency If
21. the BUS output again returns to an output enable status Therefore when the status of the short circuit continues note that the transistors mounted externally are driven during the top SOF signal dominant period per one communication frame In addition the abovementioned automatic return function is not operated and the output drive can be completely stopped by setting the disable setting bit NBO of the LAN bus output to 1 Note When BUS passive state is short circuited the overcurrent flows in the external bus drivers only during the SOF dominant period MSM6636 6636B User s Manual Function Details BUS s short circuit to GND BUS A Se eusc A HOM UU UL l l l l INT n RES ENG i A 4 E BPG flag is set BPG flag is set Bus input is switched to BUS only Bus input is switched to BUS only BUS s short circuit to GND Clear processing of BPG flag At bus idle status when BUS is short circuited to GND it is also detected and processed by the same way as the case of the BUS s short circuit to V an as stated above BUS s short circuit to Non A 4 BUS l INT t L l BUS s short INV ABN Clear processing Clear processing circuit to V an and BPV flags of INV BPV of BPV flag e Bus input is are set and ABN flags switched to e Bus input is e BPV flag is set BUS is normally BUS
22. y 3AH FID 15 Note The values of functional address registers 2CH to 3AH are undefined at reset Filtering is executed to the entire 1 to 15 area therefore be certain to set address values to the entire area even if not all the 15 types are used In this case set the same functional address values or invalid address values to areas not used Automatic Retransmission Function When a message cannot be transmitted because of being lost in contention when BUSY flag is set or communication errors when ABN D P FORM or INV flag is set and when a response is not normally returned even ifan in frame response request is sent when OVER CRC INV FORM ABN or LEN flag is set automatic retransmission is possible Automatic retransmission can be set for contention loss time and for non ACK time independently by setting the N1 NO bits of the mode setting register For example 1f transmission was not possible when retransmission twice was selected this means that the transmit operations were repeated a total of 3 times When no retransmission was selected if transmission was not possible in the first transmission attempt it notifies the CPU that transmission was not possible 2AH D2 D1 DO Nak N1 NO When lost in contention O Retransmission twice 1 No retransmission In the case of non ACK in IFR Retransmission twice 1 No retran
23. 21 O Serial data output pin TNT 16 22 O Interrupt output pin RES 17 23 Reset input pin DV an 18 24 Digital power supply pin 2 MSM6636B Pin Name A 1 0 Function SOP SSOP WR 1 1 Data write enable input pin RD 2 2 Data read enable input pin ALE 3 4 Address Latch enable input pin TNT 4 5 O Interrupt output pin RES 5 6 Reset input pin AVbp 6 7 Analog power supply pin BO 7 9 O LAN BUS output BI 8 10 l LAN BUS input Bl 9 11 I LAN BUS input BO 10 12 O LAN BUS output AGND 11 14 Analog ground pin DGND 12 15 Digital ground pin OSCT 13 16 O Crystal or ceramic resonator oscillation output OSCO 14 17 I Crystal or ceramic resonator oscillation input CS 15 19 Chip select input pin ADO 7 16 23 bin l O Address input data output pins DVop 24 30 Digital power supply pin MSM6636 6636B User s Manual Overview 1 5 Block Diagram 1 MSM6636 Buffer Register LAN Controller B Receive Receive S P PWM Degital Bus AER Register Buffer Converter Decoder Filter Receiver e
24. 6B 5 Indicates 30 pin SSOP package power dissipation for MSM6636B Power Dissipation Curve 18 pin DIP package for MSM6636 1000 850 T 500 Power dissipation Poop MW 40 25 125 150 Ambient temperature Ta C 24 pin SOP package for MSM6636 1000 910 1 4 500 Power dissipation Poor MW 40 25 125 150 Ambient temperature Ta C 18 pin QFJ package for MSM6636 Power dissipation Pors mW 1000 940 1 500 40 25 125 150 Ambient temperature Ta C MSM6636 6636B User s Manual Electrical Characteristics 24 pin SOP package for MSM6636B 30 pin SSOP package for MSM6636B L E d E 1000 1000 5 780 Y A 970 77 l i c c I S 500 7 3 5007 i Q o I 2 m I a 2 5 a i 2 5 o Oo a 40 25 125 150 o 40 25 125 150 Ambient temperature Ta C Ambient temperature Ta C MSM6636 6636B User s Manual Electrical Characteristics 7 2 7 3 Operation Range DGND AGND 0 V Parameter Symbol Condition Rated Value Unit Power Supply Voltage DV pp AVpp AV op DVop 4 5 to 5 5 V Operating Frequency fosc DVop AVpp 5 V 10 2to16 MHz Operating Temperature Ta 40 to 125 C 40 to 85 C for MSM6636B DC Characteristics 1 MSM6636 DVop AVp 5 V 10 DGND AGND 0 V Ta 40 to 125 C Parameter Symbol Condit
25. 9 00 9 14 4 00 15 00 us 40 to 85 C for the MSM6636B The sending timing in the above table does not include the delay of the bus drivers Dominant 4 Passive TP2 La Si U Dominant o Passive TP3 H 18 n I l TP1 l ha y ol bal TP10 Dominant SOF Passive TP4 ra gt gt TP5 Dominant EOD Passive L LAST BIT ER EOD i TP7 i EOF Dominant IFS Passive l LAST BIT E EOF EN IFS E i TP8 i i re gt l l TP9 i i i gt Dominant BRK Passive TP6 __ Fe gt I TP5 i ra gt MSM6636 6636B User s Manual Electrical Characteristics 7 4 2 CPU Interface Timing 1 MSM6636 Serial Interface Timing between CPUs Clock synchronous serial DVop AN 5 V 10 Ta 40 to 125 C Parameter Symbol Min Typ Max Unit OSCO source oscillation Pulse Cycle to 62 500 ns Period of SCLK Low lol w 8t ns Period of SCLK High Louw 8t ns Setup Time RXD High Low to SCLK High ters 4t ns Hold Time SCLK High to RXD High Low tenu 4t ns Output Delay Time SCLK High to TXD High Low tsro 4t 6t 100 ns Setup Time A D High Low to SCLK High tas 0 ns
26. C D7 pe ps bs D3 pz D1 po MSM6636 6636B User s Manual Internal Register Details 3 5 3 6 3 7 Receive Data Length Register MSB LSB 20 Rus RL2 RL1 RLO Receive Data Length Shows the byte length of receive data stored to the receive buffer excluding CRC indicates bits that are not provided They will always read 0 Initialization Read Completion Indication Register MSB LSB 21 Completion Command Shows the completion of initialization after reset by writing to register 21H Shows by writing to register 21H that CPU has read all receive data stored to the receive register Data to be written is not specified Interrupt Request Flag MSB LSB 22 LEN ABN D P over CRC FORM INV IFS Flags related to message abnormality etc MSB LSB 23 BUSY NOACK NRSP BRK RSP RCV TR Flagsrelated to message transmit receive status etc MSB LSB 24 PAR WAKRWAKO BPG BPV BNG BNV In MSM6636B this bit is Flags related to LAN bus line etc 1 indicates that a corresponding interrupt occurred Each bit is cleared by writing 0 to it All bits are automatically set to 0 at reset For details of how to clear see Section 5 4 CPU Interrupt Function page 5 3
27. FA2 FA1 FAO In the case of communication by functional addressing 15 types of address values in the above register are automatically filtered in sequence Even if 15 types are not used for functional addressing all 15 bytes are filtered Therefore set the functional address value in all address areas from the host CPU during initial setting For example write the same functional address value in unnecessary address areas 3 10 MSM6636 6636B User s Manual Internal Register Details 3 14 NAK Register 3B MSB LSB NA7 NA6 NAS NA4 NA3 NA2 NA1 NAO NAK Register When data with CRC is returned as IFR in IFR type 3 and when data was not set at the response register before response timing that is when data is not in transmission standby status because the write of response data has not been completed data of the NAK register is returned with CRC added If the NAK return function is used set the 3rd bit NAK of the mode setting register to 1 3 11 Chapter 4 CPU INTERFACES MSM6636 6636B User s Manual CPU Interfaces 4 CPUINTERFACES 4 1 MSM6636 Access to each internal register can be selected from 4 types of serial interfaces Data length is fixed to 8 bits LSB first Clock synchronous or UART can be selected and each has 2 types of modes normal mode to decide whether it is address value receive or data value receive according to the A D pin sta
28. FEUL6636B 05 OKI MSM6636 6636B User s Manual SAE J1850 Communication Protocol Conformed Transmission Controller for Automotive LAN Oki Electric Industry Co Ltd 5th EDITION ISSUE DATE August 2001 NOTICE 1 The information contained herein can change without notice owing to product and or technical improvements Before using the product please make sure that the information being referred to is up to date 2 The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product When planning to use the product please ensure that the external conditions are reflected in the actual circuit assembly and program designs 3 When designing your product please use our product below the specified maximum ratings and within the specified operating ranges including but not limited to operating voltage power dissipation and operating temperature 4 Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse neglect improper installation repair alteration or accident improper handling or unusual physical or electrical stress including but not limited to exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range 5 Neither indemnity against nor license of a third party s industrial and intellectual property r
29. Send the address of the write target register and communication type first then send the write data Since address values are automatically incremented it may be quicker to write to the registers that have consecutive addresses 1 Set 1 to the A D pin to send the write destination address and the communication type N AS to AO to SCLK with LSB first then send it to RXD input NP The data input to RXD is sampled at the rising edge of SCLK Set 0 to the A D pin to send write data Synchronize 8 bits of write data to the SCLK clock with LSB first then send it to RXD input Auto increment of the write destination address values occurs after each data write This makes continuous data writing quicker by eliminating some address selections Synchronize 8 bits of the register write code M1 MO 0 1 and the write destination address values MSM6636 6636B User s Manual CPU Interfaces READ PROCEDURE Send the address of the read target register and the communication type first then receive the read data Since address values are automatically incremented it is speedy to read data of the registers that have consecutive addresses 1 Set 1 to the A D pin to send the read destination address and the communication type 2 Synchronize 8 bits of the register read code M1 MO 1 0 and the read destination address values AS to A0 to SCLK with LSB first then send it to RXD input 3
30. UART is used set the baud rate at the CPU side Example If the source oscillation is 4 MHz the transmission speed is 4 MHz 64 62 5 kbps SCLK PAE pin H selects parity yes L selects parity no This is determined by the pin status immediately after RESET When changing a setting be certain to reset since setting cannot be changed during communication Parity is even parity WRITE PROCEDURE Send the address of the write target register and the communication type first then send the write data Since address values are automatically incremented it may be quicker to write data to registers that have consecutive addresses An example of a parity yes condition follows 1 Set 1 to the A D pin to send the write destination address and the communication type 2 Send start bit 0 and 8 bits of register write code M1 MO 0 1 and write destination address values AS to A0 to RXD input with LSB first When sending add even parity when parity yes is selected and stop bit 1 after the MSB bit 3 After detecting the edge of start bit 0 the MSM6636 generates a shift clock synchronizing data and samples data in the sequence of input to RXD 4 Set 0 to the A D pin to send write data 5 Send the start bit 8 bits of write data LSB first the parity bit and the stop bit to RXD input in this order 6 Auto increment of write destination address values occurs after each data write This make
31. Wo X 0 j Mode B gaihis pror Address Filter Function The MSM6636 6636B have physical addresses that are unique to each node and functional addresses that are set for each functional block Based on these address values the address filter function automatically judges whether data on the LAN bus becomes the receive target Set the physical address value to each node and set the functional address value for each functional block 15 types can be set from the host CPU side The MSM6636 6636B select either a physical address or functional address by the physical address functional address decision bit Y in a receive message and execute collating with each address value of the internal register If the same address is detected the MSM6636 6636B judge this as a message to their own node and enter receive operation Otherwise the MSM6636 6636B do not receive the message in that frame sor A B C DATA m EOF Selects address type by Y bit of 3 byte header A 0 functional address 1 physical address Address Filter Executes collating between listener address value of B and address value set to internal register Physical Address Functional Address MSM6636 6636B User s Manual Function Details 5 3 lt Physical Address gt lt Functional Address gt 8 bit x 1 8 bit x 15 Address Setting Register 2BH PID 01 2CH FID 01 2BH to 3AH y
32. Y Y 9 Address Register CRC Address ER Checker Filter CPU t Y A S K Status Register gt Receive Controller S Transmission Register Transmission Controller Y CRC Response Register Generator LAN Ki i Bus Crystal P S PWM puput af Clock Converter Encoder T Generator zoom MSM6636 2 MSM6636B Buffer Register LAN Controller LAN Bus Receive Receive S P PWM Digital Bus put Register Buffer Converter Decoder Filter Receiver o Y Y Address Register CRC Address S Checker Filter CPU d R 2 A Status Register Receive Controller i a Transmission Register Transmission Controller Y CRC Response Register Generator EAN i Bus Crystal P S PWM pupa z Clock Converter Encoder Ta Generator zo MSM6636B Chapter 2 COMMUNICATION FORMATS MSM6636 6636B User s Manual Communication Formats 2 COMMUNICATION FORMATS 2 1 Frame Format La 101 bits maximum gt I I SOF A B C D CRC EOD E EOF IFS r 3 byte header Data i Response SOF Start Of Frame CRC Cyclic Redundancy Check EOD End Of Data EOF End Of Frame IFS Inter Frame Separation Number of Bytes Contents A 1 Priority and message type B 1 Physical address or functional address of receiver node C 1 Physical address of transmitter node D Data E In frame response IFR The total sum of byte count of D E is O to 8 A Bit Configu
33. an be used Even if 15 types are not used for functional addressing all 15 bytes are filtered Therefore set the functional address value in all address areas from the host CPU during initial setting For example write the same functional address value in unnecessary address areas Set an interrupt enable flag See Section 3 8 Interrupt Enable Flag IE At reset all the flags are disabled for interrupt After reset be sure to set an initialization command The message reception response reception are enabled by writing in address 21H The data to be written is not specified Chapter 7 ELECTRICAL CHARACTERISTICS 7 ELECTRICAL CHARACTERISTICS 7 1 Absolute Maximum Ratings MSM6636 6636B User s Manual Electrical Characteristics DGND AGND 20V Parameter Symbol Condition Rated Value Unit Power Supply Voltage DVpp AVpp 0 3 to 47 0 V Input Voltage Vi AV DVop 0 3 to DVpp 0 3 V Output Voltage Vo AVoo DVpp 0 3 to DVpp 0 3 V Pane Ta 25 C 850 mW Bern Ta 25 C 940 mW Power Dissipation Poison Ta 25 C 910 mW Poison Ta 25 C 780 mW Passo Ta 25 C 970 mW Storage Temperature Tora 55 to 150 C 1 Indicates 18 pin DIP package power dissipation for MSM6636 2 Indicates 18 pin QFJ package power dissipation for MSM6636 3 Indicates 24 pin SOP package power dissipation for MSM6636 4 Indicates 24 pin SOP package power dissipation for MSM663
34. ansmitting Address 02H is empty which permits the write operation Receive Address Transmit Data 8 bytes The maximum number of bytes of transmit data that can be set depends upon the IFR type MSM6636 6636B User s Manual Internal Register Details 3 2 Response Register 3 3 MSB LSB 0B D7 D6 D5 D4 D3 D2 D1 DO 12 D7 D6 D5 D4 D3 D2 D1 DO Write arbitrary data for transmitting IFR Only applicable for IFR type 3 transmission Transmit Status Register MSB LSB 13 DL3 DL2 DL1 DLO IFR type 3 Response Data 8 bytes Data Length Write the total number of bytes of 3 byte header and data excluding CRC Data written to this register becomes the transmit start command MSB LSB E RL2 RL1 RLO Response Data Length Write the number of bytes of data that has been written to the response register used for IFR transmission Data written to this register becomes the response transmit standby command This standby state continues till the response request of IFR type 3 is received and is released after transmitting the response MSM6636 6636B User s Manual Internal Register Details 3 4 Receive Register Receive register configuration BUS f BUS GE ___ Receive Buffer J L Message normal receive RCV NZ Response normal receive RSP Rece
35. art communication again Even if the MSM6636 is reset an internal register like a physical address is not initialized therefore resetting 1s unnecessary See Status at Reset in Internal Register Details page 3 1 Normal abnormal of the host CPU interface part can be evaluated by sending an RD request for the physical address value and checking whether the set physical address value can be correctly read MSM6636 6636B User s Manual CPU Interfaces 4 2 MSM6636B The internal registers can be accessed through parallel interface This facilitates interfacing with a microcontroller that has an address multiplex type bus port 4 2 1 Parallel Interface The internal registers can be accessed through parallel interface by applying a L level to the CS pin After a L level is applied to the CS pin be sure to make address settings before reading or writing data Parallel interface allows the internal registers to be accessed asynchronously with the internal clock While accessing through the parallel interface avoid device operation where a L level is applied to the WR and RD pins simultaneously or the case that both of them are at a L level at the same time Applying a H level to the CS pin disables access though parallel interface In this case pins WR RD ALE and ADO to AD7 will be set to high impedance input PIN CONNECTION Host CPU MSM6636B ADO AD7 I 1 gt AD0 AD7 8 ALE
36. data frame Between one WR data frame and the next WR data frame during continuous WR 4 Between Communication type RD and address setting frame and RD data frame MSM6636 6636B User s Manual Electrical Characteristics 2 MSM6636B Parallel Interface Timing between CPUs DVop AVpp 5 V 10 Ta 40 to 85 C Parameter Symbol Condition Min Max Unit ALE Pulse Width taw 65 Address Setup Time tas 65 Address Hold Time Lu 5 CS Setup Time ios 50 RD Setup Time lude 20 Continuous Read Cycle Time tnpcv 160 RD Output Effective Delay Time teo 70 RD Output EE Delay Time Lon C 50 pF 50 s RD Pulse Width trow 75 RD Hold Time during Read lacsu 0 WR Setup Time twas 100 Continuous Write Cycle Time lucy 160 WR Pulse Width twrw 75 Data Setup Time tos 100 Data Hold Time ton 40 CS Hold Time during Write twos 50 e Parallel interface timing MSM6636 6636B User s Manual Electrical Characteristics ALE ADO 7 Address Data Output tro taoH gt L Loes Data Input tos to BA taow RD Read Timing ALE Le ADO 7 Address CS twrw WR Write Timing lwcsH MSM6636 6636B User s Manual Electrical Characteristics e Timing when address auto increment f
37. ddressing IFR Type Message Type 0000 Functional 2 Multiple IDs received from multiple responders 0001 Functional 1 Broadcast 0010 Functional 2 Multiple IDs received from multiple responders 0011 Functional 3 Data received from selected responders 0100 Physical 1 ID received from selected responders 0101 Physical 3 Data received from selected responders 0110 Physical 0 SAE reserve 0111 Physical 3 Data received from selected responders 1000 Functional 0 To multiple responders command status 1001 Functional 0 To multiple responders request 1010 Functional 0 1011 Functional 0 1100 Physical 0 1101 Physical 0 1110 Physical 0 1111 Physical 0 1 Broadcast The same data is transmitted to multiple responders selected by functional addressing Only the responder having an ID physical address with the highest priority can send an ID as IFR IFR is sent only once and other responder IFRs are stopped 2 SAE Reserve The MSM6636 6636B do not respond even if IFR is requested by this header because the response type is not defined MSM6636 6636B User s Manual Communication Formats IFR Type 0 SOF Header DATA CRC EOF Frame format when an in frame response is not requested IFR Type 1 SOF Header DATA crc eoo ID EOF Responder sends ID as an in frame response ID is 1 byte only Therefore the number of bytes for sending data is a maximum of 7 bytes
38. dress Filter Function E 5 1 5 3 Automatic Retransmission Function sess neret enne ESEE rE ea SE eR EZE Eeri enne 5 2 25 4 CPU Interr pt Functions sas aii ar 5 3 5 5 Receive Message Length Error Detection Function esse esse ee cese cee cneecaeecaeeeeeeeeeeeeeeeeeeseeeseenseeeseeseeesaes 5 3 5 6 Local Station Bus Driver Abnormal Detection Puncton nennen nennen 5 3 5 7 Communication Check Function between Specific Nodes A 5 3 5 8 Communication Check Function between Multiple Nodes sse 5 4 5 9 Break Function eee eben iine Rn eiecti 5 4 5 10 Fault Tolerant F nction miii Im REEL NO 5 5 Contents 1 MSM6636 6636B User s Manual Contents 6 APPLICATION EXAMPLE 6 1 6 1 Host CPU and J1850 Line Connection Example esses ener nnne enne nennen nennt 6 1 6 2 Initialization Routine Example s deg cot OOY tXo Taro enne nnne nennen enne terrent ente trennen nene nennen en 6 3 7 ELECTRICAL CHARACTERISTICS 7 1 Gali Absolute Maximiim Ratne M L 7 1 72 jQOperatomRange odere dia 7 3 1 3 JDG CharacteristiCsz ET 7 3 TA AC Char cteristies a rre PERRA ERE PEU EET ERE REESE tinta inet 7 5 TAL ZPWM BITS oras eps 7 5 TAQ CPU Interface Timing ep odds isa 7 6 TAS Wakeup Input Signal en eoe erp Rp e eer E Me rper EEES 7 11 7 4 4 Fault Tolerant Function Operation Conditions sees eren 7 12 TAS ResetInput Pulse Width eee eR PPP p Ee 7
39. e bus monitor mode is set as explained below all the messages on LAN can be received Using the bus monitor mode monitor equipment to analyze the messages on J1850 network can be easily designed 1 Bus Monitor Setting Method a Set the frequency division select code D2 D1 DO bits of the Mode Setting Register 2AH to 1 1 1 MSB LSB 2A D2 D1 DO PBO NBO NAK N1 NO Frequency division ratio setting D2 to DO b MSM6636 Apply 4 pulses to M N MSM6636B Apply 4 pulses to ALE pin when L level is input to CS pin The following figure shows the bus monitor setting timing of the MSM6636B c Resume the contents of D2 D1 DO to proper value that is depending on the applied oscillation frequency MSM6636B bus monitor setting timing a k wb 3 c l A i CS i E l 1 I 1 d T I 1 I 1 l 1 I I 1 I 1 ALE T T i T i WR i i r6 1 I l 1 I I Set the frequency division select Reset the frequency division select code to 1 1 1 code to the specified code MSM6636 6636B User s Manual Bus Monitor Function 2 Bus Monitor Using Method G 4 The received messages should be retrieved by the master CPU from the MSM6636 6636B using the CPU interface When the program uses interrupts please u
40. for each cause when set to 1 All bits are automatically set to 0 at reset Write is possible even for the bits to which a flag is not allocated but no interrupt will be generated Sleep Command Register 28 MSB LSB S7 S6 S5 S4 S3 S2 S1 EA Sleep Command The MSM6636 6636B enter sleep status by writing AAH to register 28H However if the MSM6636 6636B are processing a transfer they will enter sleep status after completing processing and after detecting IDLE bus status In sleep status oscillation stops and the MSM6636 6636B will be in output passive status After entering sleep status the value of register 28H 1s automatically set to 00H The value is automatically set to OOH at reset Sleep status has a low supply current mode that stops the oscillator circuit Do not make the device enter sleep status during message transmission Wake up conditions include 1 LAN bus status changes from passive to dominant 2 MSM6636 RXD terminal of CPU interface terminals changes MSM6636B Falling edge of CS terminal When detecting these conditions 1 and 2 the MSM6636 6636B enable oscillation circuit operation and at the same time notify WAKE UP completion to the CPU by sending an INT output in the case of WAKE UP interrupt enable Even if an abnormality occurs at one LAN bus V pp short circuit to GND or OPEN the MSM6636 6636B detect the change to dominant and WAKE UP occurs if
41. ication between multiple nodes with their respective functional addresses was normally made or not by sending messages with response type K Y Z1 Z0 0 0 0 0 or 0 0 1 0 physical address amp IFR type 2 How it is done 1s described below The multiple responders that normally received the message of the abovementioned response type send back ID sequentially as in frame responses in which case the IDs are sent back in sequence from the responder with the highest priority ID The returned IDs are then stored in the reception register in sequence from address 15H of the register When all the IDs have been stored the interrupt request flags TR and RSP are set The length of the received data is stored in the reception data length register address 20H Therefore by reading the reception data of the received data length from the reception register and checking the IDs returned the user can check whether the communication between multiple nodes was normally made Break Function The break function forcibly sets all nodes connected to LAN line to receive enable state By this function the break transmission node can quickly carry out the message transmission operation by a break transmission even during a bus busy state The break transmission is executed by writing 55H to the break command register 29H Data on bus Node A poko EE a EE o BRK EOD EOF FS SOF Le gt a
42. ight etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof 6 The products listed in this document are intended for use in general electronics equipment for commercial applications e g office automation communication equipment measurement equipment consumer electronics etc These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans Such applications include but are not limited to traffic and automotive equipment safety devices aerospace equipment nuclear power control medical equipment and life support systems 7 Certain products in this document may need government approval before they can be exported to particular countries The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these 8 No part of the contents contained herein may be reprinted or reproduced without our prior permission Copyright 2001 Oki Electric Industry Co Ltd MSM6636 6636B User s Manual Contents Contents 1 OVERVIEW
43. ion Application Min Typ Max Unit H Level Input Voltage Vi A DVppx0 8 DVop 0 3 V L Level Input Voltage Vi A DGND 0 3 DVpp x 0 2 V H Level Input Voltage Vio F DVip 2 0 DV 1 0 V L Level Input Voltage Vito F DGND 1 0 DGND 2 0 V Receiver Hysteresis Width Vu F 100 400 mV H Level Input Current lu V Vpp B 1 UA L Level Input Current lia V 0V B 1 UA H Level Input Current lus Vi Mon C 1 UA L Level Input Current llo V 0V C 100 UA H Level Input Current lus Vi Mon Bl SC 100 HA L Level Input Current lia V 0V BI 100 uA H Level Output Voltage Vout lo 400 yA D DV 0 4 V L Level Output Voltage Vou lo 3 2 mA D DGND 0 4 V H Level Output Voltage Vou lo 4 0 mA E DV 0 4 V L Level Output Voltage Vor lo 4 0 mA E DGND 04 V GND Offset Voltage Vorr 1 V Supply Current 1 los During sleep 50 UA f 16 MHz Supply Current 2 loo 10 mA no load A RES SCLK PAE RXD U C M N A D OSCO B SCLK PAE RXD U C M N A D C RES D TXD INT E BO BO F BI Bl MSM6636 6636B User s Manual Electrical Characteristics 2 MSM6636B DVpp AVpp 5 V 10 DGND AGND 0 V Ta 40 to 85 C Parameter Symbol Condition Application Min Typ Max Unit H Level Input Voltage Vie
44. ive Register is Read request d Internal Bus Line One frame of messages is stored in the receive register and one frame of messages in the receive buffer Transfer from the receive buffer to the receive register is implemented at the message response receive time Transfer to the receive register is not implemented if communication errors or overrun errors occur when receive operation is in progress Note Ifthe bus monitor mode is set to prepare a monitor tool a transfer to the receive register is performed even when errors described above occur See Section 8 Bus Monitor Function MSM6636 6636B User s Manual Internal Register Details When receiving header part and data part MSB LSB 15 H P2 P1 PO K Y Z1 ZU Communication Type Stores priority and type of the receive message MSB LSB 16 RA7 RA6 RAS RA4 RA3 RA2 RA1 RAO Receive Address Stores physical address or functional address of receive node MSB LSB 17 TA7 TAG TA5 TA4 TA3 TA2 TA1 TAO Transmit Address Stores physical address of transmit node MSB LSB 18 D7 D6 D5 D4 D3 D2 D1 DO 2 Receive Data 8 bytes 1F D7 D6 D5 D4 D3 D2 D1 DO When receiving response part MSB LSB 15 D7 De ps pa D3 pz D1 oo Response 8 bytes 1
45. ng ends at the rise of RD To read data from the areas with consecutive addresses repeat steps 5 to 6 Apply a H level to the CS pin to terminate the use of the parallel interface S Sch A ADO 7 Address ALE Repeat Figure 4 4 Read Timing 4 10 Chapter 5 FUNCTION DETAILS MSM6636 6636B User s Manual Function Details 5 FUNCTION DETAILS 5 1 5 2 Arbitration Function Multiple nodes are connected to the LAN bus so if multiple nodes start to transmit at the same time the MSM6636 6636B perform nondestructive collision detection and control priority using the arbitration function Only the node transmitting a message that has the highest priority can complete a transmission Priority is set so that the node outputting in dominant status is higher than the node outputting in passive status The MSM6636 6636B constantly monitor the LAN bus status even during transmission comparing the output data of local nodes and the LAN bus status If a local node is in passive status output but the dominant status is detected on the LAN bus the MSM6636 6636B judge this as a collision and immediately stop output This is how bus arbitration is performed we Arbitration Loss Transmit Node A Transmit Node B Transmit Node C s Arbitration Loss LAN Bus Dominant status output SOE E er
46. ocessing Clear processing circuit to GND and BNG flags of INV ABN of BNG flag e Bus input is are set and BNG flags switched to e Bus input is e BNG flag is set BUS returns to normal status BUS only switched to e Bus input is left Bus input is switched to the BUS only Switched to differential input of BUS BUS only and BUS At a bus idle status when BUS is short circuited to GND because a bus that changes its status is preferentially recognized as a normal bus it is first judged that BUS is short circuited to GND and only BUS is switched as the reception input If the BUS is short circuited to GND for more than 48 usec in transmission speed 41 6 kbps setting the dominant time error of the bus is detected and interrupt request flags ABN and INV are set As soon as these flags are set it is rejudged that BUS is short circuited to GND an interrupt request flag BNG is set and only BUS input is switched as the reception input Through the abovementioned flow BUS s short circuit to GND is detected and LAN bus input is switched so that normal communication can be carried out Then three interrupt request flags INV ABN and BNG are set When these flags are cleared the operation after that 1s just to set BNG flag Next when BUS returns to the normal status the inputs of both BUS and BUS are switched as reception inputs and the reception status of a normal LAN bus is given as before
47. ration of Priority and Message Type MSB LSB 7 6 5 4 3 2 1 0 H P3 P2 P1 PO K Y Zi ZO H 0 3 byte header MSM6636 6636B 1 1 byte header not applicable See Note below P2 to PO Priority setting bits Determines priority of message The smaller the priority value the higher the priority P2 P1 PO Priority 0 0 0 High 0 0 1 d I I 1 1 0 1 1 1 Low Note The 1 byte header mode is not selected even if 1 is set to H bit The 3 byte header mode is always selected In the MSM6636 6636B the H bit is not used for selective control of the number of header bytes However since 0 has priority over 1 the priority control depends on the bit value in the H bit that is the H bit can be used as P3 priority setting bit MSM6636 6636B User s Manual Communication Formats m DO D SO OD JO OD onm O Y Address type setting bit 0 Functional address is specified to address field B of receiver node Physical address is specified to address field B of receiver node K Z1 Z0 Sets response type The response type is set by a combination of K Z1 and ZO bits Message type and response type are determined by the lower 4 bits of the header byte A including the Y bit Classification is shown below The MSM6636 6636B identify each message type and makes an automatic response E A
48. rmal Detection Function If a passive status is received although a dominant status was output on LAN bus an interrupt request flag D P is set and this function notifies that the local station bus driver is abnormal In addition the message transmission or response transmission 1s discontinued at once Communication Check Function between Specific Nodes This function checks whether communication between specific nodes was normal or not by sending the response type K Y Z1 Z0 0 1 0 0 physical address amp IFR type 1 messages The specific node that normally received the message of the abovementioned response type sends back the physical address ID of the local station as an in frame response The node that sent the message does not store this returned response in a reception register and an interrupt request flag TR 1s set only when the value of a sent remote reception address was coincident with that of a received response At this time an interrupt request flag RSP is not set Therefore whether the communication is normal or not can be judged by checking only the TR flag which helps reduce the software load Also the setting of a read completion command address 21H is not required because the response received at this time is not stored in the reception register MSM6636 6636B User s Manual Function Details 5 8 5 9 Communication Check Function between Multiple Nodes This function checks whether commun
49. s continuous data writing quicker by eliminating some address selections MSM6636 6636B User s Manual CPU Interfaces READ PROCEDURE Send the address of the read target register and the read communication type set value 10 The MSM6636 automatically sends the specified read target data after a specified time The address auto increment function does not operate when reading in UART mode When reading from the MSM6636 address setting is required for each data item 1 Set 1 to the A D pin to send the read destination address and the communication type 2 Send start bit 0 and 8 bits of register read code M1 MO 1 0 and read destination responder address values A5 to A0 to RXD input with LSB first When sending add even parity when parity yes is selected and stop bit 1 after the MSB bit 3 After detecting the edge of start bit 0 the MSM6636 generates a shift clock synchronizing data and samples data in the sequence of input to RXD 4 Read target data is sent from TXD output in the sequence of start bit 8 bits of read data LSB first parity bit and stop bit after a specified time Receive in UART at the CPU side with the same baud rate The interval time from when the read request in UART came from the CPU to when data transmit starts takes 56 clocks of source oscillation COMMUNICATION TYPE AND COMMUNICATION ADDRESS 7 6 5 4 3 2 1 0 Mt mo AS Ad AS a2 at o
50. se the following registers IRQ and IE flags are mapped into the following registers IRQ Interrupt Request Flag MSB LSB 23 BUSY NRSP e MON BRK RSP RCV TR NOACK Transmit receive status of messages IE Interrupt Enable Flag MSB m LSB 26 BUSY hock NRSP 8 MON BRK RSP RCV TR Transmit receive status of messages Note When the bus monitor is not used the B MON interrupt request flag is fixed at 0 and the B MON interrupt enable flag is merely a read write enable flag Notes for Using Bus Monitor Bus Monitor mode operates as usual node Only the difference is that address filtering function is disabled to receive all messages Therefore if the message is addressed to the monitor node the node may make response to the message To avoid making response as described above and make the node work as monitoring only choose the unused address and set the address to the Address Setting Register Detailed Explanation for Bus Monitor When the MSM6636 6636B enter the bus monitor mode messages are sequentially stored in receive registers starting with the 3 byte header of a message that begins with SOF The difference from the normal receiving is that data is received together with CRC code Messages are stored in receive registers in the order of data CRC and response Therefore because a message is stored by one byte too much for CRC code the last byte is not s
51. set they will be automatically incremented after each data write It is therefore quicker to write to the registers consecutively 1 Apply a L level to the CS pin to enable parallel interface 2 Apply a H level to the ALE pin 3 Set address values to the ADO to AD7 pins 4 Apply a L level to the ALE pin Set up the addresses at the fall of ALE 5 Apply a L level to the WR pin 6 Input data though the ADO to AD7 pins 7 Apply a H level to the WR pin to write data Data writing ends at the rise of WR 8 To write data to the areas with consecutive addresses repeat steps 5 to 7 9 Apply a H level to the CS pin to terminate the use of parallel interface CS I I I I I I ADO 7 Address Data j Data eme I I I I ALE S WR i l h I I Repeat E M I I Figure 4 3 Write Timing READ PROCEDURE 2 Once address values have been set they will be automatically incremented after each data write It is therefore quicker to write to the registers consecutively Apply a L level to the CS pin to enable parallel interface Apply a H level to the ALE pin Set address values to the ADO to AD7 pins Apply a L level to the ALE pin Set up the addresses at the fall of ALE Apply a L level to the RD pin to read data Data reading starts at the fall of RD Apply a H level to the RD pin to end reading Data readi
52. smission MSM6636 6636B User s Manual Function Details 5 4 5 5 5 6 5 7 CPU Interrupt Function When transmit receive is completed or when various errors occur an interrupt can be requested to the host CPU by INT output low active Also interrupt enable disable can be set for each interrupt cause The host CPU can clear an interrupt request INT output H by writing 0 to the corresponding bit of an interrupt request flag in an interrupt process routine However the flag is not set by writing 1 in the interrupt request flag but the previous state is held Therefore other interrupts can be received during clearing operation by writing 0 to only the corresponding bits of the causes to be cleared and 1 to other bits An interrupt request is cleared when all bits set to interrupt enable status are cleared See below IN A Interrupt cause Interrupt cause Interrupt cause A generated A generated A cleared Interrupt cause Interrupt cause Interrupt cause A cleared B generated B cleared Receive Message Length Error Detection Function When a message length exceeds 12 bytes only the transmission and reception nodes of the message set an interrupt request flag LEN And then a reception message or reception response is not stored in reception register The message transmission or response transmission continues even if this flag is set Local Station Bus Driver Abno
53. t Detection Pulse Width toy 48 us LAN Bus to GND Short Circuit Detection Pulse Width tuc 48 us LAN Bus to V Short Circuit Detection Pulse Width tw 5 us 40 to 85 C for MSM6636B BUS j I I BUS l A Um MEE lea I try I BUS I I BUS TENE I I ba 1 tne l 7 12 MSM6636 6636B User s Manual Electrical Characteristics 7 4 5 Reset Input Pulse Width DVop AVp 5 V 10 Ta 40 to 125 C Parameter Symbol Min Typ Max Unit Reset Input Pulse Width tres 0 1 us 40 to 85 C for MSM6636B RES La ILRES I Note Make certain that as much time as the oscillation stable time determined by the crystal or ceramic resonator used and the parasitic capacitance generated by connection will be ensured as the tags time above when power is turned on The reset input pulse width given in the table above denotes the minimum pulse width when oscillation is stable in power on state 7 13 Chapter 8 BUS MONITOR FUNCTION MSM6636 6636B User s Manual Bus Monitor Function 8 BUS MONITOR FUNCTION In ordinal operation mode of MSM6636 6636B the message filtering function is based on physical or functional address Therefore the MSM6636 6636B treat only the message that is addressed to it and handle the message as a communication frame However when th
54. t disable PBO NBO When an abnormality occurs on LAN BUS its output external driving can be disabled PBO 0 LAN BUS output is enabled However when an abnormality is detected on LAN BUS 4 it is automatically disabled and when it becomes bus idle status it is automatically enabled Rh LAN BUS output is disabled regardless of the detection of LAN BUS abnormality It is recommended that this setting be made after checking that interrupt request flags BPG and BPV are set With PBO set to 1 the interrupt request flag BPG is always set during message transmission NB0 0 LAN BUS output is enabled However when an abnormality is detected on LAN BUS it is automatically disabled and when it becomes bus idle status it is automatically enabled LAN BUSCH output is disabled regardless of the detection of LAN BUSCH abnormality It is recommended that this setting be made after checking that interrupt request flags BNG and BNV are set With NBO set to 1 the interrupt request flag BNV is always set during message transmission 3 12 Physical Address Register 2B MSB LSB PA7 PAG PA5 PA4 PA3 PA2 PA1 PAO Physical Address Set the physical address ID of each node 3 13 Functional Address Register 2C 3A MSB LSB FA7 FA6 FAS FA4 FA3 FA2 FA1 FAO d Functional Address 15 bytes FA7 FA6 FAS FA4 FA3
55. th CRC code 3 Single byte response from multiple recipients ID response as ACK Error detection by cyclic redundancy check CRC Various communication error detections Dual wire bus abnormality detection by internal bus receiver and fault tolerant function Host CPU interface 1 MSM6636 Host CPU interface is accessed through serial interface with LSB first Serial 4 modes supported D Clock synchronous serial no parity 1 Normal mode 8 bit data 2 MPC mode 8 bit data MPC bit address data select bit 1 indicates address 0 indicates data UART parity yes no selectable 1 Normal mode 1 start bit 8 bit data parity 1 stop bit 2 MPC mode 1 start bit 8 bit data MPC bit parity 1 stop bit 2 MSM6636B Host CPU interface is accessed through parallel interface Sleep function Low power mode with oscillator stopped Ip Max lt 50 uA SLEEP WAKE UP control from host CPU WAKE UP via LAN bus Package 1 MSM6636 18 pin plastic DIP DIP 18 P 300 2 54 Product name MSM6636RS 18 pin plastic QFJ QFJ18 P R290 1 27 Product name MSM6636JS 24 pin plastic SOP SOP24 P 430 1 27 K Product name MSM6636GS K 2 MSM6636B 24 pin plastic SOP SOP24 P 430 1 27 K Product name MSM6636BGS K 30 pin plastic SSOP SSOP30 P 56 0 65 K Product name MSM6636BGS AK 1 1 MSM6636 6636B User s Manual Overview 1 3 Pin Configuration 1 MSM6636
56. the other bus is normal MSM6636 6636B User s Manual Internal Register Details Notes 1 In the case of wake up using ceramic oscillator the CPU interface cannot be used unless the specified oscillation stabilization time has elapsed Start access to the MSM6636 6636B considering the above time in an INT processing routine 2 When an oscillator is used and the wake up request has been received through LAN bus the interrupt flags except the WAKD interrupt flag may be set while the oscillation is unstable Be sure to 1gnore and clear all these flags after the oscillation has reached a stable point 3 10 Break Command Register 29 MSB LSB B7 B6 B5 B4 B3 B2 B1 BO BRK Transmit Command BRK is transmitted by writing 55H to register 22H However if the LAN bus is in communication a BRK transmission starts when the end of a PWM bit format is detected in the frame during communication A LAN bus can be set to idle status before the completing of a frame during communication by a BRK transmission The value of register 29H is automatically set to OOH after a BRK transmission and at reset For details see Section 5 9 Break Function page 5 4 MSM6636 6636B User s Manual Internal Register Details 3 11 Mode Setting Register 2A MSB LSB D2 D1 DO peo NBO NAK N1 NO Mode Setting Register Setting division ratio of source oscillation D2 to DO
57. tored in receive registers 15H to 1CH if the message is equal to the maximum frame length However the last byte is stored in the 3CH address in that case Therefore in this case read also the 3CH address though the address is not used for the normal communication In addition the bytes including CRC are stored in receive data length registers Therefore during the bus monitor mode check data referencing the above bytes when reading the received data Chapter 9 PACKAGE OUTLINES AND DIMENSIONS MSM6636 6636B User s Manual Package Outlines and Dimensions 9 PACKAGE OUTLINES AND DIMENSIONS Unit mm DIP18 P 300 2 54 22 6 0 2 E LI I LC Lt I N N S 3 LO H x i 7 62 INDEX MA LO x zn 1 gt o SEATING E L D L L y PLANE Q A o as x r9 Ek e Os 0 11 gt 54 0 46 00 150 0 25 20 05 1 14 TYP JL Z EE 9 0 08 6 90 25 Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating 5um Oki Electric Industry Co Ltd Package weight g 1 30 TYP Rev No Last Revised 2 Dec 11 1996 MSM6636 6636B User s Manual Package Outlines and Dimensions Oki Electric Industry Co Ltd
58. tus BRK Received break signal RSP Received response normally RCV Received message normally Message transmission ended normally TR If a response is not sent normally even though a response request was sent the interrupt in TR flag does not occur PAR Receive data parity error was detected during UART communication with CPU WAKR MSM6636 Wake up occurred during sleep due to change of RXD terminal state MSM6636B Wake up occurred during sleep due to change of CS terminal state WAKD Wake up occurred during sleep due to change of LAN bus status from passive to dominant BPG Short circuiting to GND detected at LAN bus side BPV Short circuiting to Vpp detected at LAN bus side BNG Short circuiting to GND detected at LAN bus side BNV Short circuiting to Vun detected at LAN bus side Only applies to the MSM6636 For details see Section 5 10 Fault Tolerant Functions MSM6636 6636B User s Manual Internal Register Details 3 8 3 9 Interrupt Enable Flag IE 25 26 27 MSB LSB LEN ABN D P over CRC FORM INV IFS Flags related to message abnormality etc MSB LSB BUSY NOACK NRSP BRK RSP RCV TR Flags related to message transmit receive status etc MSB LSB PAR WAKR WAKD BPG BPV BNG BNV In MSM6636B this bit is Flags related to LAN bus line etc An IE enables interrupt
59. tus and MPC mode to decide address data by MPC bit following 8 bit data When UART mode is selected even parity addition yes no can be selected by the SCLK PAE pin Type selection is set by the U C pin and the M N pin and is determined by the sampling result of the status of both pins immediately after clearing RESET Ifa communication type change is required be certain to perform RESET processing 1 Clock synchronous serial Normal mode 8 bit data MPC mode 8 bit data MPC bit 1 address O data select bit 2 UART start stop synchronization system Normal mode 1 start bit 8 bit data parity 1 stop bit MPC mode 1 start bit 8 bit data MPC bit parity 1 stop bit Selection of CPU interface type Type UART Clock Synchronous Serial Pin Process MPC Mode Normal Mode MPC Mode Normal Mode U C Pin L M N Pin L H L H Normal Mode PIN CONNECTION MSM6636 6636B User s Manual CPU Interfaces 4 1 1 Clock Synchronous Serial Interface CPU SCLK Pxx SOUT SIN INT MSM6636 ei SCLK PAE A D gt RAD TXD INT U C M N A D pin input selects whether serial bus data is address or data information For control purposes connect CPU general purpose port Pxx output to A D pin Supply serial clock for both transmit and receive to CPU CPU master MSM6636 slave communication WRITE PROCEDURE
60. unction is used Data Output Zu Read Timing ALE twas CS Sg l Se Write Timing 7 10 MSM6636 6636B User s Manual Electrical Characteristics 7 4 3 Wakeup Input Signal DVop AVpp 5 V 10 Ta 40 to 125 C Parameter Symbol Min Typ Max Unit LAN Bus Passive gt Dominant Change Pulse Width twp 7 us RXD Terminal Input Pulse Width for MSM6636 tun 300 ns CS Terminal Input Pulse Width for MSM6636B lun 400 ns Bus Receiver Stable Time tas 1 us 240 to 85 C for MSM6636B I I I I I I gt two re gt two te two m Bl we m BI Sc lei RXD Ka it Fa t I IWR ml WR rt CS Fa I WR I Note The above timing waveforms show the wakeup input signals from each sleep status 25 The stable time of the bus receiver is from just after wakeup to the restart of message transmission and reception However the clock oscillation source should use an external clock A clock is input even in the sleep status 7 11 MSM6636 6636B User s Manual Electrical Characteristics 7 4 4 Fault Tolerant Function Operation Conditions DVop AVpp 5 V 10 Ta 40 to 125 C set at 41 6 kbps Parameter Symbol Min Typ Max Unit LAN Bus to GND Short Circuit Detection Pulse Width tra 5 US LAN Bus to V p Short Circui
61. w A DVppx0 8 DVop 0 3 V L Level Input Voltage Vi A DGND 0 3 DV55x0 2 V H Level Input Voltage Vio E DVppx0 7 DVop 1 0 V L Level Input Voltage Vio E DGND 1 0 DGND x 0 3 V H Level Input Voltage Ving B 2 4 DVop 0 3 V L Level Input Voltage Vis B 0 3 0 8 V Receiver Hysteresis Width Vu E 100 400 mV H Level Input Current lu V Vpp B GC 1 uA L Level Input Current lia V 0V B T 1 uA H Level Input Current Jus V Voo RES 1 uA L Level Input Current lio V 0V RES 100 uA H Level Input Current lus Vi Mon Bl 100 uA L Level Input Current lia V 0V BI mE 100 uA H Level Output Voltage Vout lo 400 pA C ADO 7 DVpp 0 4 m V L Level Output Voltage Vou lo 3 2 mA C ADO 7 DGND 0 4 V H Level Output Voltage Von lo 4 0 mA D De 0 4 V L Level Output Voltage Vor lo 4 0 mA D DGND 04 V GND Offset Voltage Vorr 1 V Current Supply 1 los During sleep 1 50 uA f 16 MHz Current Supply 2 loo 2 10 mA no load A RES CS OSCO B ALE WR RD ADO 7 C INT D BO BO E BI Bl 1 Typ 0 2 uA when Vun 2 5 V f 2 16 MHz Ta 25 C 2 The variations in supply current at different frequencies at Vun 5 V Ta 25 C are shown below DYNAMIC SUPPLY CURRENT VS FREQUENCY Typ n T T T T T T T T
62. y 1998 Third Edition February 2000 Fourth Edition May 2000 Fifth Edition August 2001 2001 Oki Electric Industry Co Ltd FEUL6636B 05

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