EVBUM2256 - NB3N1900K Evaluation Board User's Manual
Contents
1. traces so as to eliminate via impedance and stub affects Board stand offs are installed Board Layout The NB3N1900K QFN 72 Evaluation Board provides ahigh bandwidth 50 62 controlled trace impedance environment 100 92 line to line differential and is implemented in four layers e All Layers are Constructed with FR4 Dielectric Material e The First Layer is the Primary Signal Layer Including All of the Differential Inputs and Outputs e The Second Layer is the Ground Plane It is Dedicated for the DUT Ground SMA Ground Plane e The Third Layer is Dedicated as the Power Plane A Portion of this 314 Layer is Designated for the Device VDD and VDDIO Power Planes e The Fourth Layer Contains Control Lines Power Supply Banana Jacks and Device Power Pin By pass Capacitors Layer Stack e LI Top Signal e 12 Device Ground and SMA Ground e 13 VDD VDDIO Separate Device Power Supplies e 14 Bottom Power Supply By pass Capacitors Control Pin Traces and Banana Jacks 4 LAYER STACK UP 0 001 0 0007 0 0007 ADJUST 0 0014 ADJUST 0 0014 ADJUST 7 0 0007 0 0007 0 001 PRIMARY SILK SCREEN PRIMARY SOLDER MASK PRIMARY SURFACE PLATING L1 TOP L2 GROUND PLANE L3 POWER PLANE L4 BOTTOM SECONDARY SURFACE PLATING SECONDARY SOLDER MASK SECONDARY SILK SCREEN Figure 2 NB3N1900KMNGEVB Evaluation Board Layer Stack Up Power Supplies Each VDD VDDIO and GND power supply has a separate side launch banana jack2. 1050 http onsemi com 6 NB3N1900KMNGEVB QUICK START LAB SET UP USER S GUIDE Pre Power Up 1 Connect power supply cables to VDD VDDIO and GND banana jacks do not turn power on yet 2 Connect a signal generator to the SMA connectors for the CLK_IN amp CLK_IN inputs 3 50 Q termination resistors are installed for a signal generator on the board Set appropriate input signal levels HCSL input VIL 0 V VIH 700 mV Frequency 100 00 or 133 33 MHz 4 Ensure the PWRGD PWRDNH pin is in the Low state before power up PWRDN There is a jumper on pin 6 to easily select between High and Low See Figure 7 5 The 10OM_133M and HBW_BYP_LBW pins need to be hardware selected with jumpers See Figures 3 and 6 6 Connect the DIF_n DIF_n outputs to the appropriate oscilloscope Signal Generator OUT OUTb gt o gt gt mI oO m Mm Figure 10 Typical Lab Test Set Up Power Up Sequence 1 Turn on power supply 3 3 V VDD amp VDDIO 2 Move PWRGD PWRDN jumper from Low to logic High PWRGD position 3 Turn on the Differential Clock Signal for the CLK IN inputs 4 Monitor DIF n DIF nf outputs on oscilloscope Table 2 POWER SUPPLY CONNECTIONS Device Pin Power Supplv Connector Power Supplv VDD VDDIO VCC 43 3 V Single Power Supply gt 43 3 V OV VDD VDDIO 3 3 V GND Figure 9 Power Supplv Connections Oscilloscope Optional Graphical User Interface There is a
3. Rp is installed 50 92 to GND on the short metal traces without SMA connectors and will use Hi Z probes Table 1 NB3N1900KMNGEVB OUTPUT LOAD AND TERMINATION VS OSCILLOSCOPE MEASUREMENT we e BA ee ae 1900K Long 1 5 Open DNI or 50 50 Q or Hi Z i ut Lanal E ey DFe DIF GS Figure 8 Differential Outputs Schematic Configuration Long OUT6 vs Short OUT7 Metal Traces HCSL Output Measurement HCSL outputs are typically terminated with 50 Q to ground Measuring HCSL outputs can be easily accomplished by NB3N1900K HCSL Outputs 50 2 Oscilloscope Head With Rpremoved from board connect the HCSL outputs through the SMA connectors to the 50 Q internal impedance of the oscilloscope sampling head NB3N1900K HCSL Outputs Use Hi Z Probe With Rp installed use a high impedance probe on the output s metal trace Holes for headers to connect to Hi Z probes are available but the header pins are not installed e Single ended Hi Z Probes or e Differential Hi Z Probe Misc Pins FB OUT amp FB_OUT External Termination of Feedback Pins FB_OUT amp FB_OUT have convenient test point anvils to monitor these pins with Hi Z probe NB3N1900K HCSL Since the FB_OUT amp FB_OUT pins do not drive transmission lines no SMAs the board layout has these pins loaded terminated at the DUT per datasheet 83 02 to GND is installed for the 100 92 board IREF Pin NB3N1900K HCSL The Rperresistor R9
4. located on bottom side This board is capable of measuring device IDD amp IDDIO separately Board Layer 2 SMA Ground Device GND 0 V GND Banana Jack negative power supply for DUTGND and SMAGND Exposed Pad EP The exposed pad footprint on the board is soldered to the exposed pad of the QFN 72 package and is electrically connected to GND power supply Board Layer 3 VDD and VDDIO Power Supplies VDD positive power supply for core and inputs VDD VDDA VDDR pins 1 8 VDDIO positive power supply for outputs VDDIO pins 21 31 45 58 68 VDD amp VDDIO have the power supply filtering per datasheet by the banana jacks All VDD VDDA VDDR VDDIO device pins have aQ 1 uF bypass capacitor installed on top side next to package pins http onsemi com NB3N1900KMNGEVB Control Pins e For a HIGH Level Put Jumper to High Each control pin can be managed manually with a H L e For a LOW Level Put Jumper to Low header H VDD L GND JN pe lb deager e Fora MID Level Put Jumper to both High and Low Tri Level Input Pins HBW_BYP_LBW SA_O and SA 1 this will Enable both Pull up and Pull down Resistors The three tri level input pins HBW BXPASS LBWH SAO and SA1 have selectable with jumper 4 7 KQ pull up to VDD and 4 7 kQ pull down to GND resistors No jumper defaults to open float HBW_BYP_LBW At J16 header there is a 4 7 KQ pull up to VDD and a 4 7 KQ pull down resistor to GND for manual
5. stand alone Graphical User Interface software package and user s manual that will interface with the DUT via the USB connector 1 Connect the USB port on the evaluation board to a USB port on the PC via cable 2 See the stand alone GUI instructions document 3 Allow Windows to install the necessary drivers for the eval board USB interface hardware 4 Start the GUI program http onsemi com 7 NB3N1900KMNGEVB Table 3 BILL OF MATERIALS FOR THE NB3N1900KMNGEVB HiQ Electronics NB3N1900KMNGEVB B1 1 PC Board Clock Fanout Board 38 C1005C0G1H020C 2 0 pF C0402 Digi Key 445 4863 1 ND C36 C44 TR3A106K010C2000 10 uF C1206 Digi Key 718 1300 1 ND C38 C40 Ka GRM155R61A105ME15D C0402 Digi Key 490 5409 1 ND C67 C68 4 C39 C41 18 0402ZD104KAT2A 100 nF C0402 Digi Key 478 1129 1 ND AVX C46 C54 C56 GC58 C60 C62 C65 C69 ma e e O a a ma FB3 FB4 2 BLMISAG6OISNID 6o JI L0402 Digi Key 490 1006 1 ND Murata H1 H2 H3 4 129 Hole in HOLE_0 240R0 12 H4 240 Round 9 PTH Pad 4 J1 J4 JB J7 1 142 0701 801 SMA Jack End SMA Jack End L J10 J11 J13 Launch aunch J14 J15 J17 961103 6404 AR Header 3 pin HDR_1X3_2P54 Johnson Components Digi key J502 ND J20 J22 J5 J8 J9 J12 J16 J18 J19 J21 J23 3M9448 ND w Digi Key J24 571 0500 Banana Jack con_571 0500 Mouser 164 6219 Deltron Thru Hole Red J25 571 0700 Banana Jack con_571 0500 Mouser 164 7170 Deltron Thr
6. 9 to GND is for the HCSL output part device Rper 475 Q is installed for the 100 92 board http onsemi com 5 NB3N1900KMNGEVB Graphical User Interface GUI USB amp I C SMBus Interface The NB3N1900K EVB has an on board I C SMBus interface circuitry located in the upper left section of the board This circuitry will interface with the software program and the device via the SDA and SCL input pins and can control all twelve of the OE_n pins PLL Mode and Frequency Select directly from the GUI SCL amp SDA The SMBus Clock SCL and Data SDA pins are exercised through the on board EC interface In order to enable the I C control of the DUT header jumpers J27 amp J28 must be shorted The I2C SMBus interface circuitry is powered separately from the USB type B connection and is isolated from device VDD and VDDIO The SDA and SCL pins can also be externally accessed by an off board programmer allowing other SMBus emulators to be used to program the DUT If used remove both jumpers J27 amp J28 Test point anvils TP33 amp TP34 are available for external control of the device with the use with mini grabber cables To receive the GUI software and GUI software manual please contact below ON Semiconductor Technical Support Email Chat www onsemi com support or Americas Voicemail 800 282 9855 Americas Direct 011 421 33 190 2910 EMEA 00421 33 790 2910 Japan Customer Focus Center 81 5817
7. GD PDN Figure 7 PWRGD PWRDN Pin Schematic Configuration http onsemi com 4 NB3N1900KMNGEVB Differential Clock Inputs and Outputs CLK IN amp CLK_IN Differential Clock Inputs The differential Clock input traces CLK_IN CLK_IN are equal length routed straight from the SMA connectors on the left side directly to the DUT there are no vias on metal traces CLK_IN amp CLK_IN have resistor pads R63 amp R64 to GND to terminate a signal generator if used 50 Q resistors are installed Remove these resistors if CLK_IN amp CLK_IN are driven by another IC device DIF _n and DIF _n Differential Outputs NB3NI900KMNGEVB were designed to measure the differential HCSL outputs with a 50 02 scope head or high impedance FET probe See Output Schematic in Figure 8 Six of the nineteen differential outputs are designed to have equal length metal traces from the device pins to the SMA connectors The other thirteen differential outputs have shortened metal traces do not have SMA connectors and can be observed with a high impedance probe on the metal pads provided Each DIF_n DIF_n output has a provision for Ci sad 2 pF capacitors are installed on all outputs Rs amp Rp pads are located close to the DUT Rs 33 Q is installed for the NB3N1900K NB3N1900K HCSL Outputs Rp can be uninstalled on the six output pair with long metal traces to SMA connectors Use 50 Q to GND of the oscilloscope head for Rp
8. LC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against al
9. NB3N1900KMNGEVB NB3N1900K Evaluation Board User s Manual ON Semiconductor Introduction The NB3NI900KMNGEVB evaluation boards were developed for the NB3N1900K HCSL devices This evaluation board was designed to provide a flexible and convenient platform to quickly evaluate characterize and verify the operation of the NB3N1900K devices This evaluation board manual contains http onsemi com EVAL BOARD USER S MANUAL e Information on the NB3N1900K Evaluation Board e Assembly Instructions This manual should be used in conjunction with the device e Test and Measurement Setup Procedures datasheet which contains full technical details on the device e Board Schematic and Bill of Materials specifications and operation ON SEM LOONDUCTOR Top View Bottom View Figure 1 NB3N1900KMNGEVB Evaluation Board Semiconductor Components Industries LLC 2014 1 Publication Order Number October 2014 Rev 1 EVBUM2256 D NB3N1900KMNGEVB BOARD FEATURES Single Board Design Layout e Accommodates the Electrical Characterization of the NB3N1900K HCSL Outputs e Incorporates On board I2 C SMBus Interface Circuitry Powered from a USB Connection Minimizing Cabling e Convenient and Compact Board Layout 3 3 V Power Supply Device Operation Differential Inputs Outputs Signals are Accessed via SMA Connectors or High Impedance Probes Other Board Features There are no vias on the high speed differential I O metal
10. control HBW_BYPASS_LBW J16 HBW LEW Figure 3 HBW_BYP_LBW Schematic Configuration SA_O amp SA_I At J21 and J23 headers there are 4 7 KQ pull ups to VDD and 4 7 KQ pull down resistors to GND for manual control 1 R61 2 Vi J21 2 DNI4 7K SAD 11 l SAQ H L b 3 RAS 1 MBD ngs o 1 2 1 l 4 7K J2 DNI4 7K i T ka e 7 SAT SA 1 SAL H L 1 RBI 2 ii 4 7K Figure 4 SA 0 amp SA 1 Schematic Configuration OE_n Pins Output Enable Disable Function All eight of the OE_n s can be controlled individually Four of the eight differential outputs can be controlled automatically by using the software GUI GUI control is manually using the convenient High Low OE_n jumpers accomplished via the USB See Figure 5 See Figure 5 http onsemi com 3 NB3N1900KMNGEVB OE IO5 a4 OE 5 Al oc ea OE 106 5 Po tha Oe OE 107 ki 40 DE TA Ai oc gg OE 1OB B fo 0EB OE 1OB T 48 OE 9 51 OE 108 certo Im For ELGE OE 1011 ee I oe 128 VDD GE 12 2 pem DELH 3 Figure 5 OE_n Pins Schematic Configuration LOOM _133M Frequency Selection J18 The 1OOM_133M frequency selection pin can be controlled manually with the High Low header jumper J18 H 100 MHz L 133 MHz 100M 133ME J18 100 133 Figure 6 100M 133M Pin Schematic Configuration PWRGD PWRDN2 J19 The PWRGD PWRDNH pin can be controlled manually with the High Low header jumper J19 H PWRGD L PWRDN PWRGD PWRON J19 P
11. l claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 ki l l Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2256 D
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13. u Hole Yellow J26 571 0100 Banana Jack con_571 0500 Mouser 164 6218 Deltron Thru Hole Black J27 J28 2 961102 6404 AR Header 2 pin HDR 1X2 2P54 Digi Kev 3M9447 ND J29 Digi Kev ED2994 ND On Shore Technologv Digi Kev 160 1435 1 ND Lite On LED1 1 M1 M8 M10 M9 4 M11 M13 M14 M17 4 PR1 PR6 LTST C190KGKT LED Green LED_0603 1808 Standoff 4 40 1 4 x 5 8 PMS 440 0025 PH Screw 4 40 x 0 25 PHP Digi Key S9337 ND Sullins USB B1SMHSW6 Conn USB B Con_USB_B_RA SMT Digi Key 1808K ND Keystone Digi Key H342 ND Building Fasteners No Part 4 Round Pads 060 with BERG 2X2 2P54 040 Hole w z http onsemi com 8 NB3N1900KMNGEVB Table 3 BILL OF MATERIALS FOR THE NB3N1900KMNGEVB continued R1 R2 R5 38 33 Q R0402 Digi Key jem Ta a o R6 R10 R11 R14 R18 R19 R22 R25 R27 R30 R31 R32 R34 R37 R39 R41 R43 R45 R48 R51 R53 R55 R58 R61 R65 R69 R72 R75 R77 R79 R83 R88 R92 R95 R97 49 9 Q R0402 Digi Key P49 9LCT N Panasonic 49 9 Q R0402 Digi Key P49 9LCT N Panasonic R0402 Digi Key 541 0 0JCT ND Vishay R3 R7 R16 R20 R23 R28 R33 R35 R4 R8 R17 R21 R24 R26 R29 R36 R38 R40 R42 R44 R47 R50 R52 R54 R57 R60 R62 R66 R71 R74 R76 R78 R82 R87 R90 R94 R96 R98 R9 R12 R13 R15 R46 R49 R56 R59 R70 R73 R80 R84 CRCW04020000Z0ED R63 R64 ERJ 3EKF49R9V 49 9 Q R0603 Digi Key P49 9HCT N Panaso
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