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EXC-1553PCI/Px User's Manual: Rev B

1. Figure 9 1 EXC 1553PCI Px Board Layout EXC 1553PCI Px User s Manual Board Layout page 9 LED Indicators page 9 B page page page 9 1 Board Layout BC RT BM A B BC BT BM A B A Oy pa 3 LD15 LD16 LD17 LD18 LD19 BDY afbY l CHANNEL 2 CHANNEL 3 mm O UOL u e Ji 2 WUUU CHANNEL 0 CHANNEL 1 l 0 opg l p o Y m Q H 6 85 174mm page 9 1 4 2 106 68 mm Chapter 9 Mechanical and Electrical Specifications 9 2 LED Indicators The EXC 1553PCI Px board contains 24 LEDs The LEDs indicate each channel s operational mode and bus activity The function of each LED is described below Channel No Channel Ready BC Mode Active RT Mode Active Monitor Mode Active Bus A Active Bus B Active Table 9 1 LED Indicators page 9 2 Excalibur Systems Chapter 9 9 3 9 3 1 9 3 2 Mechanical and Electrical Specifications Jumpers Rev B Board Channel x 1553 Coupling Mode Select Jumpers JP1 JP16 The board can be either direct or transformer coupled to the 1553 Bus Groups of four jumpers select the coupling mode for each channel Tabld 9 2 defines the jumper settings for all 16 jumpers Coupling Mode Jumper Settings JP2 4 6 8 10 12 14 16 JP1 3 5 7 9 11 13 15 Direct Coupled short 1 2 short 2 3 Transfer Coupled short 2 3 short 1 2 Ta
2. Figure 4 6 Word Count Error Table Addresses Register Value Word Count Offset FD H 3 Words FE H 2 Words FF H 1 Word 00 H No Error Injection 01H 1 Word 02 H 2 Words 03 H 3 Words Word Count Error Byte Values EXC 1553PCI Px User s Manual page 4 13 Chapter 4 4 12 page 4 14 Remote Terminal Operation Program Example RT Mode NOTE All values are in HEX unless otherwise stated BASIC Instruction 10 20 30 40 50 60 70 80 90 POKE POKE POKE POKE POKE POKE POKE POKE POKE amp H3FFF 02 amp H3FF2 xx amp H3201 1 amp H3204 1 amp H3222 00 amp H3223 08 amp H3228 00 amp H3229 amp H20 amp H3FF7 xx 100 POKE amp H3266 00 110 120 130 140 150 POKE POKE POKE POKE STOP amp H3FF3 00 amp H4xxx 1 amp H4yyy 2 amp H3FFC 1 Remarks Set the Configuration register to RT mode Set the Variable Amplitude register Enable RT 1 Enable RT 4 Set the Status word of RT 1 to 0800 Set the Status word of RT 4 to 2000 Set the Time Tag Resolution register Set the Mode Code Control register to Subaddress 0 amp 31 Set No global error injection Load block number 1 for data storage into look up table xxx Load block number 2 for data storage into look up table yyy Set the Start register to 1 to start RT mode Excalibur Systems Chapter 4 4 13 4 13 1 4 13 2 4 13 3 Remote Terminal Operation Control Register Defi
3. Mode Code Control Register EXC 1553PCI Px User s Manual page 6 27 Chapter 6 6 11 21 6 11 22 6 11 23 6 11 24 page 6 28 Bus Monitor Operation Broadcast Control Register Address 3FE8 H Write to the Broadcast Control register to select whether RT address 11111 RT 31 is interpreted as a valid RT address or as a Broadcast address Bit Description 01 07 0 00 1 Broadcast option is active RT 31 isa Broadcast Address 0 Broadcast option is inactive RT 31 is a Regular RT Broadcast Control Register Monitor Response Time Register Address 3E8E H The Monitor Response Time Register sets the maximum wait time until an RT s Status Response is considered valid by the Monitor The Monitor Response Time Register is measured in microseconds The default value of the register is 14 in not otherwise set by the user Boards Options Register Address 3E84 H The Module Options register is a 16 bit register in which the low 8 bits are reserved This register identifies the type of on module firmware Bit Description 10 15 Reserved 09 1 1760 08 1 1553 00 07 Reserved Board Options Register Firmware Revision Register Address 3E80 H The Firmware Revision register indicates the revision level of the on board firmware The value 0001 0010 would be read as revision level 1 2 Excalibur Systems Chapter 7 7 1 Concurrent Monitor Option Concurrent Monitor Option Chapter 7 des
4. gt ee a lt RT Status Word lt ime Figure 4 7 RT Response Time Definition Example Setting the RT Response Time Register To request a response time of 9 usec Write 32 to the RT Response Time register 32 x 0 155 5usec 4 usec 9 usec EXC 1553PCI Px User s Manual page 4 19 Chapter 4 4 13 15 4 13 16 page 4 20 Remote Terminal Operation Error Injection Register Address 3FF3 H The Error Injection Register is a global register that allows you to select the type of error to be injected in a transmitted message When the board receives a Start command issued by writing to the Start register the board reads this register To modify the Error Injection register issue a Stop command modify the register and then issue a Start command see Start Register page Bit Description 07 Data Word Sync Error Data Words Sent With Command Sync 06 Reserved Set to 0 05 Status Word Synchronization Error Status Word Sent With Data Sync 04 Reserved Set to 0 03 Reserved Set to 0 02 Non Contiguous Data Between First and Second Data Word 01 Reserved Set to 0 00 Reserved Set to 0 Error Injection Register Message Stack Pointer Address 3FF0 3FF1 H The Message Stack pointer indicates the Message Stack position After the entire message is received the Message Stack pointer is updated incremented by 6 This word is initialized to 3300 H and circulates in the Message Stack bet
5. Firmware Revision Loop Count Register 3FF6 H Register 3E80 H Bit Count 3FF5 H Reserved 3426 3E7F H Word Count Register 3FF4 H ai Ai Start 3424 H BC Response Time 3FF3 H Asynchronous Frame 3422 H Register Pointer Reserved 3FF2 H Asynchronous 3420 H Message Counter Stack Pointer 3FFo 3FFiH Active RT Table 32 3400 341FH Bytes Frame Time Register 3FEE 3FEFH nstruction and 0000 33FF H Message Block Area Figure 5 1 BC Concurrent RT Memory Map EXC 1553PCI Px User s Manual page 5 3 Chapter 5 BC Concurrent RT Operation 5 2 Instruction Stack Use the Instruction Stack to program the board The stack is divided into instruction blocks each containing four words The block contains control information that the user writes and status information that the board writes Figure 5 2 illustrates one instruction block Control and status information is stored in the memory in the Word following sequence Offset C Messo sae Wod remessas Gap Tne Comer 4 C memessage Geptine 2 C vessan o 15 81 7 0 High Byte Low Byte Figure 5 2 Instruction Block Structure BC Concurrent RT Mode page 5 4 Excalibur Systems Chapter 5 5 2 1 Message Status Word BC Concurrent RT Operation The Message Status word indicates the status of the message transfer This word is created by the board Do not confuse this word with the 1553 Status word see L553 RT Status Words page 4 7 The co
6. Interrupt Reset Register Software Reset Register Data Block Look Up Table Board Configuration Register Board ID Register Board Status Register Start Register Message Status Register Reserved Time Tag Resolution Register Reserved RT Response Time Register Error Injection Register Reserved Message Stack Pointer 700D 7FFF H 700C 700A 700B H 7008 7009 H 7007 H 7004 7006 H Status Response Register 3FEF H 7003 H Reserved 3E86 3FEE H 7002 H 3E84 H Firmware Revision Register 3E80 H Boards Option Register 7001 H 7000 H 4000 47FF H 1553 RT Vector Words 64 Bytes 3480 34BF H 1553 RT Bit Words 64 Bytes 3440 347F H 3FFF H 3FFE H 3FFD H RT Last Command Words 64 Bytes 3400 343F H Interrupt Condition Register 33FC H Message Stack 42 Blocks 3300 33FB H Word Count Error Table 32 Bytes 32E0 32FF H Mode Code Control 3266 H 1553 RT Status Words 64 Bytes 3220 325F H Active RT Table 32 Bytes 3200 321F H 1553 Data Blocks 200 Blocks 0000 31FF H 3FFC H 3FFB H 3FF8 H 3FF7 H 3FF5 3556 H 3FF4 H 3FF3 H 3FF2 H 3FF0 3FF1 H Figure 4 1 RT Memory Map EXC 1553PCI Px User s Manual page 4 3 Chapter 4 4 2 page 4 4 Remote Terminal Operation Data Block Look Up Table Address 4000 47FF H The received command word s RT Address T R Bit and Subaddress fields
7. The mailbox at address 40H contains the Interrupt Status Register O wan unon merpen merite 9c Reserved 0s 38 H OOOO o e dCi ah Subsystem ID Subsystem Vendor ID 2CH Cardbus CIS Pointer not used Os 28 H Base Address Register 3 Channel 2 1C H Base Address Register 2 Channel 1 18 H Base Address Register 0 PCI Configuration Space 10 H O est Heacortype 0 taere Timer H 31 24 23 16 15 08 07 00 Figure 2 3 PCI Configuration Space Header page 2 2 Excalibur Systems Chapter 2 2 3 2 3 1 2 3 2 PCI Architecture PCI Configuration Registers This section describes the registers contained in the PCI Space Header Vendor Identification Register VID Address 00 01 H Power up value 1405H Size 16 bits The Vendor Identification register contains the PCI Special Interest Group vendor identification number assigned to Excalibur Systems Device Identification Register DID Address 02 03 H Power up value 1103H Size 16 bits The Device Identification register contains the EXC 1553PCI Px device identification number EXC 1553PCI Px User s Manual page 2 3 Chapter 2 2 3 3 Power up value Size PCI Command Register PCICMD 0000 H 16 bits PCI Architecture Address 04 05 H The PCI Command register contains the PCI Command Bit 10 15 09 08 07 06 05 04 03 02 01 00 PCI Command Register page 2 4 Bit Name Reserved Fast Back
8. page 4 P1h the same status word is sent with the following conditions Message Error In case an error occurred in the previous message the Status Word Bit 10 will be sent with the Message Error bit set to 1 if the current message is of type Send Status or Send Last Command This will occur even if you set the Message Error bit to 0 If you set the Message Error bit to 1 it will always be sent set to 1 Busy Bit 03 The Busy bit is always sent as you defined it In the case of Transmit commands when Busy is set to 1 no data words will be transmitted by the RT following the transmission of the status word The MIL STD 1553B Format for the Status Word is as follows Bit Bit Name 11 15 RT Address 10 Message Error 09 Instrumentation 08 Service Request 05 07 Reserved 04 Broadcast 03 Busy 02 Subsystem Flag 01 Dynamic Bus 00 Terminal Flag 1553B Status Word EXC 1553PCI Px User s Manual page 4 7 Chapter 4 4 5 page 4 8 Remote Terminal Operation Message Stack The board generates a message stack in the dual port memory This stack contains information that can be used for post processing of RT messages The stack is divided into 42 blocks each containing three words The stack operates as a circular buffer The Message Stack Pointer points to the beginning of the next unused block Only active RT messages are stored Figure 4 5 illustrates one block Control and status information is stored in the memory
9. Interrupt Reset register at the beginning of a user written interrupt service routine data field don t care Software Reset Register Address 7000 H Write to the Software Reset register to reset the channel data field don t care The Board status the Board ID and Firmware revision registers are written by the board after the reset operation has been completed WARNING Reset erases all memory locations in the dual port RAM Board Configuration Register Address 3FFF H Before issuing a Start command to the board set the operating mode of the board via the Board Configuration register To modify the Board Configuration register issue a Stop command modify the register and then issue a Start command see Start Register page 6 23 Hex Operating Mode Value 08 BM Sequential Block 10 BM Sequential Link List 20 BM Look Up Table Board Configuration Register Values Monitor Mode EXC 1553PCI Px User s Manual page 6 21 Chapter 6 Bus Monitor Operation 6 11 9 Board ID Register Address 3FFE H The Board ID register contains a fixed value that can be read by your initialization routine to detect the presence of the board The one byte value of this register is 45 Hex ASCII value E 6 11 10 Board Status Register Address 3FFD H The Board Status register indicates the status of the board In addition this register indicates which options have been selected Do not modify this register Status b
10. T R bit and Subaddress are used as a pointer to the Data Block look up table memory NOTE When operating in Broadcast mode the Broadcast bits in the 1553 Status Words are not updated by the board s processor Excalibur Systems Chapter 4 4 11 4 11 1 Remote Terminal Operation Error Injection Features The board allows two types of error injection e Global for all RTs Per RT The global errors such as Sync and Non Contiguous data are described in page 4 Dal These errors are either ON or OFF for all RTs The ability to inject a 1553 Word Count error however can be set per RT Word Count Error Table Address 32E0 2FF H The Word Count Error is selected by writing to the Word Count Error table which contains 32 bytes one per remote terminal The first byte is for RT 0 the second to RT 1 and the last byte is for RT 31 The contents of each location controls the number of 1553 words 38 words in the message The variation is an offset relative to the 1553 command word s Word Count field The resulting message if an error is programmed must contain at least one data word Upon power up and software reset the board sets the Word Count Error Table to the default value 00 You must set the Word Count Error register before issuing a Start command to the board To modify the Word Count Error register issue a Stop command modify the register and then issue a Start command see Btart Register page 4 18
11. amp H3FF3 xx Set trigger word 1 high to xx 60 POKE amp H3FEB xx Set the Trigger Control register see Trigger Control page 6 16 70 POKE amp H3FEA 00 Set the Mode Code Control Register to 1s and Os see Mode Code Control Register pageb 27 80 POKE amp H3FE8 00 Set the Broadcast Control register to RT31 regular see Broadcast Control Register page 6 P8 90 POKE amp H3FFC 01 Start command NOTE Messages are read from memory starting from address 0000 Bus Monitor Sequential Link List Mode BASIC Instruction Remarks 10 POKE amp H3FFF amp H10 Set the Board Configuration register to Bus Monitor Link List mode see Board Configuration Register page B 21 20 POKE amp H3FEA 00 Set the Mode Code Control register to 1s and Os see Mode Code Control Register pageb 27 30 POKE amp H3FE8 01 Set the Broadcast Control Register to RT31 Broadcast see Board Configuration Register page 21 40 POKE amp H3FFC 01 Start command NOTE Messages are read from memory starting from address 0000 EXC 1553PCI Px User s Manual page 6 17 Chapter 6 6 11 6 11 1 page 6 18 Bus Monitor Operation Bus Monitor Look Up Table Mode BASIC Instruction Remarks 10 POKE amp H3FFF amp H20 Set the Board Configuration register to Bus Monitor Look Up Table mode 20 POKE amp H3FEA 00 Set the Mode Code Control register to 1s and Os see Mode Code Control Register pageb 27 30 POKE amp H3FE8 00 Set the Broadcast Control regi
12. H e Block 1 is located at location 0050 H e The location of the block is obtained by multiplying the block number by 50 H EXC 1553PCI Px User s Manual page 6 9 Chapter 6 Bus Monitor Operation 6 6 Look Up Table Mode Message Block Area Information is stored in the Byte memory in the following Offset sequence 78 See Appendix B for Message Formats 8 ess CoransWos e tie Tap wows CO mewo C message sauswod o Figure 6 7 Bus Monitor Message Block Look Up Table Mode page 6 10 Excalibur Systems Chapter 6 6 7 Bus Monitor Operation Message Status Word The Message Status word is identical for all Bus Monitor modes The Message Status word indicates the status of the message transfer This word is created by the board Do not confuse it with the 1553 Status word see L553 RT Status Words pagd 4 7 The contents of the Message Status word are described below NOTE A logic 1 indicates the occurrence of a status flag Bit Bit Name 15 End Of Message 14 Trigger Found 13 RT RT 12 Message Error Bit Set 11 RT Status Bit Set 10 Invalid Message 09 Reserved 08 Bus A B 07 Invalid Word Received 06 Word Count High 05 Word Count Low 04 Incorrect RT Address 03 Incorrect Sync Received 02 Non Contiguous Data 01 Response Time Error 00 Error Message Status Word EXC 1553PCI Px User s Manual Description Message transfer completed Trigger message was received and sto
13. Message Formats BC to RT Receive Data Data Data E Status i Next Command Word Word Word Word Command RT to BC Transmit Status Data Data Data Next Command Word Word Word Word Command RT to RT Receive Transmit A Status Data Data Data ig Status Next Command Command Word Word Word Word Word Command Mode w o Mode y Status Next Data Command Word Command Mode w Mode 7 Status Data 7 Next Data Command Word Word Command Transmit Mode w Mode Data Status Next Data Command Word Word Command Receive Broadcast Receive Data Data Data Next BC to RTs Command Word Word Word Command Broadcast Receive Transmit Status Data Data Data 2 Next RT to RTs Command Command Word Word Word Word Command Broadcast Mode _ Next Mode w o Command Command Data Broadcast Mode Data Next Mode Command Word Command w Data Figure 11 2 MIL STD 1553B Message Formats NOTE Response time Intermessage gap EXC 1553PCI Px User s Manual page 11 3 Appendix C Chapter 11 Internal Loopback Test Appendices The Internal Loopback Test is used to check the 1553 front end logic excluding transceivers and coupling transformers To initiate the Internal Loopback Test 1 Write ED H into the Board Configuration Register 2 Write 1 into the Start Register 3 Wait for 0 in the Start Register The results of this test are returned t
14. Options Select Register is used to select the bus to which Channels 1 and Channels 3 are connected On reset Channels 1 and Channels 3 are set to monitor their own buses NOTE Channels 0 and Channels 2 are always connected to their own 1553 buses in Monitor Mode independent of the state of this register OPTIONS SELECT REGISTER FOR CHANNEL 1 Bit Description 02 07 Don t care 01 Concurrent BM control bit only for EXC 1553PCI P2 P3 P4 configuration 1 Select Channel 1 as Concurrent BM of Channel 0 0 Select Channel 1 as Independent BM Channel 00 Don t care OPTIONS SELECT REGISTER FOR CHANNEL 3 Bit Description 02 07 Don t care 01 Concurrent BM control bit only for EXC 1553PCI P4 configuration 1 Select Channel 3 as Concurrent BM of Channel 2 0 Select Channel 3 as Independent BM Channel 00 Don t care Options Select Register Excalibur Systems Chapter 6 6 11 5 6 11 6 6 11 7 6 11 8 Bus Monitor Operation Global Software Reset Register Address 7002 H Write to the Global Software Reset register to reset all channels present on the card simultaneously data field don t care NOTE Global Software Reset erases all locations in dual port RAM Board status Board ID and Firmware Revision registers are written by the board after the reset operation is completed Interrupt Reset Register Address 7001 H To reset the Interrupt signal generated by the channel write to the
15. RTs data blocks 11 most significant bits of the 1553 command word Base RT T R Sub Look Up Data block Hex address address 1 bit address table address 5 bits 5 bits 2K x 8 of data block 4000 11111 1 Block Data Block 27B0 4000 00000 0 EE 7 o Block 3 OOFO 4000 00000 0 Block Block Data Block 2 Block 2 00A0 4000 00000 0 Block Block ee Block 1 0050 4000 00000 0 Block Block Ere Block 0 0000 Figure 6 6 Look Up Table Excalibur Systems Chapter 6 Bus Monitor Operation TO CREATE THE ADDRESS TO THE TABLE 1 Isolate the eleven most significant bits of the 1553 command word RT Address T R and Subaddress field and determine their hex value Example To allocate a data block for a 1553 receive message to RT 5 Subaddress 3 RT Address 5 T R 0 Rev Subaddress 3 0 0 1 0O 1 0 0 0 0 1 1 LSB Hex representation 143 2 Add the hex value of this part of the command word to the base address of the look up table 4000H 4000 H 143 H 4143 H 3 Write the Data Block number to this location Example POKE amp H4143 xx writes an 8 bit Block Number value to the look up table address amp H4143 Each data block beginning at address 0000 is 80 bytes long for up to 32 1553 data words The address of a block is obtained by multiplying its block number by 50 H THE BLOCK ADDRESSES ARE CALCULATED AS FOLLOWS e Block 0 is located at location 0000
16. Register 3FFD H Start Register 3FFC H Interrupt Condition Register 3FFBH Reserved Message Status Register 3FFA H Time Tag Resolution 3FF7 H Reserved 3FF6 H Boards Option Register End Buffer Pointer 3FF4 3FF5 H Reserved Next Message Pointer 3FF2 3FF3H Firmware Revision Register Message Block Spill Reserved 3FEB 3FF1 H Area Mode Code Control Register 3FEA H Message Block Area Broadcast Control Register 3FE8 H Figure 6 2 BM Sequential Link List Memory Map 3E90 3FE7 H 3E8E H 3E86 3F8D H 3E84 E 3E81 3E83 H 3E80 H 3400 3E7F H 0000 3DFF H Excalibur Systems Chapter 6 Bus Monitor Operation 6 3 Sequential Mode Message Block Area The Sequential Mode Message Block area is partitioned either into blocks of fixed length or into a link list of blocks of varying lengths The type of partitioning is determined by the Board Configuration register see Board Configuration Register page 6 21 For a description of the Time Tag function see ime Tag Word page 6 L2 6 3 1 Message Block Fixed Block Operation In Fixed Block operation the Message Block area is divided into 200 blocks of 80 bytes each The first block starts at address 0000 H the second at 0050 H the third at 00A0 H etc The Trigger option can be used only in Sequential mode with Fixed Block operation see page 6 3 Information is stored in the Word memory
17. Tag Options erik see lime Tag Options Register page 6 18 Provides ground reference for the digital signal connections page 9 7 Chapter 9 9 6 page 9 8 Power Requirements Mechanical and Electrical Specifications The EXC 1553PCI Px power requirements are listed in the following table EXC 1553PCI P1 EXC 1553PCI P2 EXC 1553PCI P3 EXC 1553PCI P4 5V 1 2A 2 2A TBD TBD Table 9 6 Power Requirements Excalibur Systems Chapter 10 Ordering Information 10 Ordering Information Chapter 10 explains how to indicate which options you want when ordering a EXC 1553PCI Px board The following suffixes must be added to the name of the board EXC 1553PCI Px to indicate the specific options The suffixes are added to EXC 1553PCI Px in the order in which they appear in the table Suffix Description M Concurrent Monitor option x Number of channels 1 4 E Ruggedized extended temperature operation 40 85 C 1760 MIL STD 1760 options ORDERING EXAMPLES PART NUMBER EXC 1553PCI P1 EXC 1553PCI P2 EXC 1553PCI PM3 EXC 1553PCI P4 E EXC 1553PCI P1 1760 EXC 1553PCI Px User s Manual DESCRIPTION Single Channel MIL STD 1553 interface board for PCI systems Supports BC RT BC Concurrent RT and BM modes Dual Channel MIL STD 1553 interface board for PCI systems Supports BC RT BC Concurrent RT and BM modes Three Channel MIL STD 1553 interface board for PCI systems Suppor
18. Time register is 155 nsec per bit measured as the dead time on the 1553 bus The minimum time is approximately 2 usec Set the BC Response Time register before issuing a Start command to the board To modify the BC Response Time register issue a Stop command maree the za gister and then issue a Start command see Start Register page f 5 21 Response RT Status Word Time Dead Time Last Command Data Word gt Figure 5 7 BC Response Time Definition Example Setting the BC Response Time Register To set up a BC response time of 14 usec Write 90 to the BC Response Time register 90 x 0 155 14 usec Stack Pointer Address 3FF0 3FF1 H The Stack pointer points to the Instruction stack The Instruction stack can reside anywhere between the locations 0000 H and 33FF H Set the Stack Pointer register before issuing a Start command to the board To modify the Stack Pointer register issue a Stop command modify the register and then issue a Start command see Start Register page 5 21 Excalibur Systems Chapter 5 5 7 17 5 7 18 5 7 19 BC Concurrent RT Operation Frame Time Register Address 3FEE 3FEF H The Frame Time Register contains the 16 bit Frame Time value for Continuous and n Times modes operation The value written to the Frame Time Register is multiplied by the value set in the Frame Time Resolution register pair described below The value set must equal the desired multi
19. are used to index the entries in the user programmed look up table Each entry in the table represents a data block number from 0 to 199 decimal Each block can contain up to 32 1553 Data Words 64 bytes Data Block 0 begins at address 0000 Data Block 1 begins at address 0040 H etc 11 most significant bits of the 1553 command word Base RT T R Sub Look up Data block Hex Address address 1 bit address table address 5 bits 5 bits 2K x 8 of data block 4000 11111 1 11111 Block Data Block 31C0 199 4000 00000 0 00001 Data Block 1 0040 4000 00000 0 00000 Data Block 0 0000 Figure 4 2 Data Block Look Up Table NOTE For RT to RT messages When the board is simulating both RTs in an RT to RT message transfer the simulated receiving RT s data block is not updated with the transmit data The data is transmitted over the 1553 bus TO CREATE THE ADDRESS TO THE TABLE 1 Isolate the eleven most significant bits of the 1553 command word RT Address T R and Subaddress field and determine their hex value Example To allocate a data block for a 1553 receive message to RT 5 Subaddress 3 RT Address T R 0 Rev Subaddress 3 5 0 o 1 0 1 0 0 0o 0 1 1 SB Hex representation 143 H Excalibur Systems Chapter 4 4 2 1 4 3 Remote Terminal Operation 2 Add the hex value of this part of the command word to the base address of the look up table 4000H 4000 H 143 H 4143 H 3 Write the
20. data block number to this location Example POKE amp H4143 01 allocates block 1 for the data of this message Read the 1553 data out by reading block 1 which starts at address 0040 H Each data block beginning at address 0000 is 64 bytes long for up to 32 1553 data words The address of a block is obtained by multiplying its block number by 64 40 H Data Storage The data words must be stored and or read in the following format in the data block 1553 Word N Last Location In Data Block 1553 Word 2 1553 Word 1 First Location In Data Block Figure 4 3 Data Storage Sequence Active RT Table Address 3200 321F H The 32 locations bytes of the Active RT table contain the list of active remote terminals To select an RT to be simulated set bit 00 in the Active Remote Terminal byte to logic 1 The first active RT byte relates to RT 0 the next to RT 1 and the last location relates to RT 81 RT 31 Active RT byte 32nd byte 321F H 1st byte 3200 H Figure 4 4 Active RT Table RT Mode EXC 1553PCI Px User s Manual page 4 5 Chapter 4 page 4 6 Bit Bit Name 04 07 0 03 Inactive Bus B 02 Inactive Bus A 01 Interrupt 00 Active Remote Terminal Operation Description 1 Bus B Inactive 0 Bus B Active If bit 00 is set to 1 and bit 03 is set to 0 the board will respond to all messages received over bus B for this RT and the board will generate interrupts if requested to do so If bit 03
21. don t care You must define the Trigger Mask registers when using the trigger function All bits in this register should be set to 1 except for those bits you want to be don t care in the incoming Command word or Message Status Word Using the 1553 Command Word Trigger Mask Registers After setting the Trigger Word register with a 1553 Command word write Os to the bits in the Trigger Mask register that you want to be don t care in the 1553 Command word trigger sjjisjiejnjiojojs z e s ajsjeji o RT Address Subaddress Word Count Field T R Field Field 1 Trigger on corresponding bit value in Trigger Word Register 0 Corresponding bit value in Trigger Word Register is Don t Care Using the Message Status Word Trigger Mask Registers After setting the Trigger Word register with a Message Status word write Os to the bits in the Trigger Mask register that you want to be don t care in the Message Status word trigger For an explanation of the see page 5 4 ssfre njiofefel7 e s 4 s3i2 i o Message Status Word Bits 15 0 1 Trigger on corresponding bit value in Trigger Word Register 0 Corresponding bit value in Trigger Word Register is Don t Care EXC 1553PCI Px User s Manual page 6 15 Chapter 6 6 9 3 6 9 4 page 6 16 Bus Monitor Operation Trigger Control Register Address 3FEB H The Trigger Control register is relevant only in Sequential Fixed Blo
22. error occurred e g Word Count Sync Error See other bits set for the exact error For example an RT to RT message which contains two receive messages Response time error occurred in the message even if no RT is active on the module Set to 0 At least one invalid 1553 word received i e bit count Manchester code parity RT transmitted too many words RT transmitted too few words Received 1553 Status word did not contain the correct RT address Sync of either the command or the data word s is incorrect Invalid gap between received 1553 words RT to RT message was received Error occurred The error type is defined in one of the other message status bit locations Message Status Word BC RT Concurrent Monitor NOTE The message contents are valid only after the Message Status Word has been written which is indicated by the End of Message bit being turned on page 7 4 Excalibur Systems Chapter 7 7 2 3 7 3 7 3 1 7 3 2 Concurrent Monitor Option 1553 Message Words The 1553 message words are stored in the sequence they appear on the bus i e 1553 Command words 1553 Status words 1553 Data words all according to the order of the specific type of message Control Register Definitions Next Message Pointer Address 3E90 H The Next Message pointer is a 16 bit pointer that indicates the address of the 1553 message about to be written The Next Message pointer register is update
23. in the Word following sequence Offset Message Status Word 4 Time Tag Value 2 1553 Command Word 0 15 8 7 0 High Byte Low Byte Figure 4 5 Message Stack Block Structure HOW THE BOARD UPDATES AN RT TO RT MESSAGE When an RT to RT message is received where the board is functioning as both RTs the Message stack is updated as follows Two message stack blocks are utilized 1 The 1553 Receive command word is written into the first message stack block 2 The RT RT bits in both message status words are set to 1 3 The board updates the Time Tag word in the second stack block and the second Message Status word The board updates only the RT to RT bit in the first Message Status word to Active status 4 The 1553 Transmit command word is written into the second stack block Excalibur Systems Chapter 4 4 5 1 Message Status Word Remote Terminal Operation The Message Status word indicates the status of the message transfer This word is created by the board Do not confuse this word with the 1553 Status word seel1553 RT Status Words page 4 7 The contents of the Message status word are described below NOTE A logic 1 indicates the occurrence of a status flag Bit Bit Name 15 End Of Message 14 Bus A B 11 13 Reserved 10 Tx Time Out 09 Reserved 08 Reserved 07 Invalid Word Received 06 Reserved 05 Word Count Error Receive Message 04 Broadcast Message 03 Incorrect Sync Received 02
24. is referred to as issuing a Start command Excalibur Systems Chapter 6 Bus Monitor Operation 6 1 Sequential Fixed Block Memory Map Global Software Reset Register Interrupt Reset Register Register Time Tag Resolution Message Counter Counter Trigger Trigger Word 1 Trigger Mask 1 Trigger Word 2 Trigger Mask 2 Trigger Control Register Mode Code Control Register Software Reset Register Board Configuration Register Broadcast Control Register 700C H 700A 700B H 7008 7009 H 7007 H 7004 7006 H 7003 H 7002 H 7001 H 7000 H 4000 6FFF H 3FFF H 3FFE H 3FFD H 3FFC H 3FFB H 3FFA H 3FF8 3FF9 H 3FF7 H 3FF6 H 3FF5 H 3FF4 H 3FF2 3FF3 H 3FF0 3FF1 H 3FEE 3FEF H 3FEC 3FED H 3FEB H 3FEA H 3FE8 H Reserved Monitor Response Time Reg Reserved Boards Option Register Reserved Firmware Revision Register Message Block Area 200 Blocks Figure 6 1 BM Sequential Fixed Block Memory Map EXC 1553PCI Px User s Manual 3E90 3FE7 H 3E8E H 3E86 3F8D H 3E84 E 3E81 3E83 H 3E80 H 0000 3EF7 H page 6 3 Chapter 6 6 2 page 6 4 Bus Monitor Operation Sequential Link List Memory Map Global Software Reset Interrupt Reset Register 7001 H Software Reset Register 7000 H Board Configuration 3FEF H Register Board ID Register 3FFE H Board Status
25. is set to 1 all messages over bus B for this RT will be ignored regardless of the settings of other bits in this register 1 Bus A Inactive 0 Bus A Active If bit 00 is set to 1 and bit 02 is set to 0 the board will respond to all messages received over bus A for this RT and the board will generate interrupts if requested to do so If bit 02 is set to 1 all messages over bus A for this RT will be ignored regardless of the settings of other bits in this register 1 Interrupt 0 No Interrupt If bit 01 is set to 1 the RT is active and the Interrupt Condition register is enabled this RT will generate an interrupt 1 Active 0 Inactive If bit 00 is set to 0 the RT is not active If it is set to 1 bits 01 02 and 03 are checked Active RT Byte Definition RT Mode Excalibur Systems Chapter 4 4 4 Remote Terminal Operation 1553 RT Status Words Address 3220 325F H These locations are reserved for the 32 1553 RT status words Load the desired status words into their respective locations in the block The first word relates to RT 0 the next word to RT 1 while the last word relates to RT 31 For each RT that is to be simulated all 16 bits of that RT must be defined in its status word In a non 1553B environment see Status Response Register page 4 bih the user defined status word is sent whenever the RT has to respond with a status word In a 1553B environment see Status Response Register
26. s Time Tag Counter data field don t care Immediately after the reset the counter will start to count from 0 NOTE The counter can also be reset from an external source see page 9 5 EXC 1553PCI Px User s Manual page 4 15 Chapter 4 4 13 4 4 13 5 4 13 6 4 13 7 page 4 16 Remote Terminal Operation Options Select Register Address 7003 1H Write to the Options Select register to select whether RT address 11111 RT 31 is interpreted as a valid RT address or as a Broadcast address Bit Description 01 07 0 00 1 Broadcast option is active RT 31 is a Broadcast Address No RT Status Word will be transmitted 0 Broadcast option is inactive RT 31 is a Regular RT Options Select Register Global Software Reset Register aadressi THAD Write to the Global Software Reset register to reset all channels present on the board simultaneously data field don t care NOTE Global Software Reset erases all locations in dual port RAM Board status Board ID and Firmware Revision are written by the board after the reset operation is completed Interrupt Reset Register Address 7001 H To reset the Interrupt signal generated by the channel write to the Interrupt Reset register at the beginning of a user written interrupt service routine data field don t care Software Reset Register Address 7000 H Write to the Software Reset register to reset the channel data field don t care The Boa
27. to Back Enable System Error Enable Address Stepping Support Parity Error Enable VGA Palette Snoop Enable Memory Write and Invalidate Enable Special Cycle Enable Bus Master Enable Memory Access Enable I O Access Enable Description Set to Os Always set to 0 Always set to 0 Always set to 1 Always set to 0 Always set to 0 Always set to 0 Always set to 0 Always set to 0 Always set to 1 Since the PCI Px board does not use I O space the value of this register is ignored Excalibur Systems Chapter 2 2 3 4 2 3 5 PCI Status Register PCISTS Power up value Size 0080 H 16 bits PCI Architecture Address 06 07 H The PCI Status register contains the PCI status information Bit 15 14 13 12 11 09 10 08 07 06 05 04 00 03 Bit Name Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort Device Select DEVSEL Timing Status Data Parity Reported Fast Back to Back Capable Reserved 66MHz capable Capability List enable Reserved PCI Status Register Revision Identification Register RID Power up value Size 01H 8 bits Description This bit is set whenever a parity error is detected It functions independently from the state of Command Register Bit 6 This bit may be cleared by writing a 1 to this location Not used Not use
28. with errors or messages with errors received over bus B etc see Trigger Word Registers page 6 14 The Trigger Mask Register defines which bits of the trigger word defined in the Trigger Word register are relevant and which can be ignored don t care The Trigger Mask registers must be defined when using the trigger function see Trigger Mask Registers page 6 L5 Set the Trigger Control Register to specify the following trigger conditions see rigger Control Register page 6 L6 Trigger source 1553 Command word or Message Status word Type of storage Store All Store Only or Store After e Active trigger word Trigger Word 1 and or 2 Set the registers Trigger Word Trigger Mask and Trigger Control before issuing a Start command to the board To modify these registers set the Initialize bit in the Start register to 10 H modify the Trigger Word Trigger Mask and Trigger Control registers then issue a Start command 01 H EXC 1553PCI Px User s Manual page 6 13 Chapter 6 6 9 1 page 6 14 Bus Monitor Operation Trigger Word Registers 1 and 2 Address 3FF2 3FEE H Use the Trigger Word register to define a particular 1553 Command word or a Message Status word as a trigger Load these locations illustrated below with the desired 1553 Command word or Message Status word which will be used as the trigger source You must also define the Trigger Mask Registers when using the trigg
29. 03 07 0 02 1 Loop Mode 0 One Shot Mode 01 0 00 1 Start Operation 0 Stop Start Register NOTE Itis also possible to start operation of the board by sending a low TTL pulse of 100 nsec minimum to the EXSTART xn pin see page D 5 EXC 1553PCI Px User s Manual page 5 21 Chapter 5 5 7 9 5 7 10 page 5 22 BC Concurrent RT Operation Interrupt Condition Register Address 3FFB H The Interrupt Condition register allows you to set interrupt triggers When a condition occurs that is enabled in this register an interrupt is generated A logic 1 enables the interrupt condition To determine which condition caused the interrupt check the Message Status register Set the Interrupt Condition register before issuing a Start command to the board To modify the Interrupt Condition register issue a Stop command modify the a ia and then issue a Start command see Start Register page 5 21 NOTE The interrupt will be sent at the end of the message for all interrupt conditions Bit Description 04 07 0 03 Message Error 02 End Of Frame 01 Message Complete 00 0 Interrupt Condition Register Message Status Register Address 3FFA H The Message Status register indicates the status of the current message being processed The definition of each status bit is given below Logic 1 indicates that the condition is activated Bit Bit Name Description 04 07 0 03 Message Error The message has been sent As a resu
30. 102 amp H23 amp H103 amp HOC amp H104 amp HOO amp H105 amp H08 amp H106 amp Hxx amp H107 amp Hxx amp H108 amp Hyy amp H109 amp Hyy amp H10a amp Hzz amp H10b amp Hzz amp H140 02 amp H141 00 amp H142 amp H23 EXC 1553PCI Px User s Manual Remarks Set the Configuration register to BC RT mode Set the Stack Pointer registers to 0000 stack now begins at address 0000 Set the Variable Amplitude register Pointer to first message Location of message is 0100 H Set the Intermessage Gap Time location Pointer to second message Location of message is 0140 H Set the Intermessage Gap Time location Set the Control word to Transmit command Bus A and no errors injected Set the command word to 0C23 Set the Status word to 0800 Set the Data word to xxxx Set the Data word to yyyy Set the Data word to zzzz Set the Control word to RT to RT command Bus B and no errors injected Set the first Receive command word to 3823H page 5 17 Chapter 5 5 7 5 7 1 5 7 2 page 5 18 BC Concurrent RT Operation BASIC Instruction Remarks 280 POKE amp H143 amp H38 290 POKE amp H144 amp H43 Set the second Transmit command word to 1C43H 300 POKE amp H145 amp H1C 310 POKE amp H3FEB 2 Set the Instruction Counter to 2 i e 2 messages 320 POKE amp H3FEC xx Set the Frame Time Resolution registers 330 POKE amp H3FED xx 340 POKE amp H3FEE xx Set the Fram
31. 15 JP16 Oo N N a SO CO Table 9 5 Channel Jumper Groups Rev C Example To set Channel 2 to transformer coupled short pins 1 and 2 of JP9 JP10 JP11 and JP12 Factory Default Jumper Settings The following are the factory preset default settings JP1 JP16 Pins 1 amp 2 Shorted Transformer Coupled mode Excalibur Systems Chapter 9 9 5 9 5 1 Mechanical and Electrical Specifications Connectors The EXC 1553PCI Px board contains all communication I O signals on one female high density DB 62 pin connector J1 P N HDL 62SLC PCB Mating connectors P N HDT 62 PD with plastic hoods are included The connectors pinouts and signals description are described below Connector J1 Pinout Figure 9 2 Connector J1 Pinout Connector Front View EXC 1553PCI Px User s Manual page 9 5 Chapter 9 Mechanical and Electrical Specifications 9 5 2 Connector J1 Pin Assignments BUSAL1 SHIELD BUSAH1 SHIELD Pause fae nto as fewer as eo fe Esmann 26 orerarGno 7 Bosne for K r euss 2 w CEE EI CEEA E COOMER se Eme me o oeme ss wc me fe EI me fafs ss E EI Ea EA ar pennen se E E E CI Ka CEE EE BUSAL2 BUSAH2 EXTCLK1 EXTGRSTin EXTGRST2n N C 42 DIGITAL GND N C Not Connected Z O Z O page 9 6 Excalibur Systems Chapter 9 9 5 3 EXC 1553PCI Px User s Manual Mechanical and Electrical Specific
32. 3FF6 H 3FF2 H 3FEB 3FF1 H 3FEA H 3FE8 H Reserved Monitor Response Time Reg Reserved Board Options Register Reserved Firmware Revision Register Reserved Message Block Area 128 Blocks Figure 6 5 BM Look Up Table Mode Memory Map 3E90 3FE7 H 3E8E H 3E86 3F8D H 3E84 H 3E81 3E83 H 3E80 H 2800 3E7F H 0000 27FF H page 6 7 Chapter 6 6 5 page 6 8 Bus Monitor Operation Look Up Table Mode In Look Up Table mode the board can store 128 unique messages by using a 2K x 8 Look up table in on board memory Each byte in the table is divided into a 7 bit block number and an Interrupt Select bit as described below Data Block numbers 0 127 decimal each consisting of 80 bytes are loaded into the table The first block starts at address 0 the second at 50 H etc Set the Interrupt Select bit to specify which messages will set the interrupt flag The Interrupt Condition register must also be programmed Bit Description 07 1 Interrupt Select Bit is Enabled 00 06 Block Numbers 0 127 Look Up Table Byte Structure When a 1553 message is received the Command word s RT address T R Bit and Subaddress fields are used as an 11 bit index to the Look up table This index is used to extract the Data block number from the Look up table For RT to RT messages all the information is stored in both the receiving and the transmitting
33. 7 3 0 0 1 18 2 0 1 0 19 1 0 1 1 20 1 0 0 21 1 1 0 1 22 2 1 1 0 23 3 Bit Count Register Excalibur Systems Chapter 5 5 7 14 BC Concurrent RT Operation Word Count Register Andress SEELE The Word Count register controls the number of 1553 data words 3 in the message and allows you to inject a Word Count error The error is an offset relative to the 1553 command word Word Count field This register is used by the board only for messages for which the Word Count Error bit is set in the Control word register see page 5 8 If the Word Count Error bit is not set a correct number of words are transmitted regardless of the contents of the Word Count register Set the Word Count register before issuing a Start command to the board To modify the Word Count register issue a Stop command modify the register and then issue a Start command see 5 21 page Register Value Word Count Offset FD H 3 Words FEH 2 Words FFH 1 Word 00 H No Error Injection 01H 1 Word 02 H 2 Words 03 H 3 Words Word Count Register Values EXC 1553PCI Px User s Manual page 5 25 Chapter 5 5 7 15 5 7 16 page 5 26 BC Concurrent RT Operation BC Response Time Register Address 3FF3 H The BC Response Time register sets the BC s Response Time window whose value determines the maximum wait time until an RT s Status Response is considered invalid by the BC The resolution of the BC Response
34. Broadcast Mode code 0 1 1 1 kip Message see Bkip Message page 5 P 1 0 0 0 mp and s SP Jump Command Minor Dperationlpage 5 Mino ame eure gt k Excalibur Systems Chapter 5 5 2 7 5 2 8 5 2 9 BC Concurrent RT Operation Halt Operation Normally set the Halt Operation bit to logic 0 before writing to the Start register In real time during BC execution y set this bit to logic 1 When operating on that particular message block s Control word the board will halt transfer operations until the bit is reset to logic 0 When the board detects that the Halt bit is set it sets the Wait For Continue bit in the Message Status register see page 5 18 Use the Wait For Continue bit to find out when the board has arrived at the halted instruction block When the board detects that you have reset the Halt bit Continue Mode the board will reset the Wait For Continue bit in the Message Status Register and continue BC operation The Halt operation can be implemented only in message blocks that have not as yet been executed by the board NOTE The Halt operation can be used in conjunction with the Jump command described below see Jump Command Operation page 5 b Skip Message Operation The Skip Message command allows you to skip a message defined in a certain message block All you have to do is modify the Command field in the Control word This lets you selectively send a message in the current f
35. C operation Restart by writing to the Instruction Count register and issuing a Start command Selects Even parity in 1553 Word 1 Halt stops BC transfer operation This bit must be reset to 0 to Run or Continue Transmits fewer or more word are indicated by th Word Count field see Word aa AER page 54 function is valid for BC to RT messages only Transmits invalid number of bits in 1553 words see page Transmits incorrect sync Data type Sync is transmitted in the Command word Transmits the first 1553 Data word with invalid Gap Time between Command and Data word For BC to RT Broadcast Receive and Mode Code with Data messages bit 08 selects the Parity Sync and Bit Count error injection placement 0 in Command word 1 in Data words For other error injection types or other message types this bit must be set 1 to enable error injection Selects active 1553 bus logic 1 selects bus A logic 0 selects bus B On error the BC will retry message transfer on alternate bus Note Auto retry must be selected This On error selects the number of retries before transferring the next message Bit 05 Bit 04 Description 0 0 No Retry 0 1 1 Retry 1 0 2 Retries 1 1 3 Retries 03 02 01 00 Description 0 0 0 0 Transmitcommand RT to BC 0 oO 0 1 Receive command BC to RT 0 0 1 0 RT to RT command 0 0 1 1 Mode code 0 1 0 0 Broadcast Receive command 0 1 0 1 Broadcast RT to RT command 0 1 1 0
36. EXC 1553PCI Px MIL STD 1553 Test and Simulation Board for PCI Systems User s Manual eZ XCALIBUS EXCALIBUR SYSTEMS 311 Meacham Avenue Elmont NY 11003 Tel 516 327 0000 Fax 516 327 4645 e mail excalibur mil 1553 com website www mil 1553 com Contents Contents EEE ee ee eee eee eee e Ee E 992 _ PAT Tye ney EXC 1553PCI Px User s Manual page i Contents 5 29 ump Command Opera 2 Q e Opera page ii Excalibur Systems Contents EXC 1553PCI Px User s Manual page iii Contents page iv 10 11 Appendix B Appendix C Appendix D Excalibur Systems Contents Figures Figure 11 1 Figure 11 2 EXC 1553PCI Px User s Manual page v Contents Base Address Registers Definition LED Indicators Jumper Settings Required to Select Coupling Mode Channel Jumper Groups Jumper Settings Required to Select Coupling Mode Rev C Channel Jumper Groups Rev C Power Requirements page vi Excalibur Systems Chapter 1 1 1 Introduction Introduction Chapter 1 provides an overview of the EXC 1553PCI Px avionics communication board The following topics are covered Overview page 1 1 Installation page 1 b 1553 Bus Connections page 1 4 Overview The EXC 1553PCI Px is an intelligent MIL STD 1553 interface board for PCI systems Available with up to four independent 1553 channels the EXC 1553PCI Px provides a complete solution for develop
37. Non Contiguous Data Receive Message 01 RT RT Message 00 Error Message Status Word EXC 1553PCI Px User s Manual Description Message transfer completed Bus on which the message was transferred 0 BusB 1 BusA Set to 0 Board acting as receiver in RT to RT message did not sense a transmitter status word in 14 usec Set to 0 Set to 0 At least one invalid 1553 word received i e bit count Manchester code parity Set to 0 Incorrect number of words received in the message Broadcast command word received Sync of either the command or the data word s is incorrect Invalid gap between received 1553 words RT to RT message received where board was simulating both RTs Error occurred The error type is defined in one of the other message status bit locations page 4 9 Chapter 4 4 5 2 4 5 3 page 4 10 Remote Terminal Operation Time Tag READ BY USER The Time Tag value is a 16 bit word that can be used to determine the time elapsed since the Start command was issued or the time between 1553 messages The Time Tag uses a 32 bit free running counter whose resolution is set by the Time Tag Resolution register This register has a resolution of 4 usec per bit The equation to determine the Time Tag resolution register value 1 x 4 usec Note that only the lower 16 bits of the counter are written to dual port RAM Example Register value 0 gt Counter s resolution 4 usec Regist
38. PERATE perform the following procedure after a power up or a software reset 1 Check the Board ID register test for value 45 H 2 Check the Board Status register test for Board Ready bit 1 The board is installed and ready when both registers contain the correct values as written above For software reset operations set these values to 0 immediately prior to writing to the software Board Reset register NOTE Throughout this manual writing a 1 to the Start register is referred to as issuing a Start command Excalibur Systems Chapter 5 BC Concurrent RT Operation 5 1 BC Concurrent RT Memory Map Figure b 1 below illustrates the BC Concurrent RT memory usage Reserved 7004 7FFF H Options Select Register 7003 M Global Software Reset Register 7002m Interrupt Reset Register JOON Software Reset Register ee Reserved 4000 6FFF H Board Configuration Frame Time Register Sper Resolution Register SFECSSFED H Board ID Register 3FFE H Instruction Counter 3FEA 3FEB H Board Status Register 3FFD H Minor Frame Time 3FE8 H Start Register 3FFC H Reserved 3FE7 H Interrupt Condition 3FFB H Minor Frame 3FE6 H Register Resolution Message Status 3FFA H Reserved 3E86 3FE5 H Register RT Response Time 3FF9 H Boards Option 3E84 H Register Register Reserved 3FF7 3FF8 H Reserved 3E81 3F83 H
39. RT Mode 1553 Command Word Excalibur Systems Chapter 5 5 2 5 BC Concurrent RT Operation Message Block The load the message block can be loaded anywhere in the Instruction Stack Message Block area see BC Concurrent RT Memory Map page 5 Bp Message blocks do not have to be stored in sequential locations in the memory since the Message Block pointers point to the message blocks in sequence Each block contains a 1553 message plus its Control word This Control word is written into the first word of each block The Control word instructs the board which type of message to transmit i e RT to RT Mode code Broadcast Error injection etc The size of the message block is variable and depends on the size of the message itself The descriptions of the various message block formats i e BC to RT RT to BC and RT to RT are illustrated in Message Block Formats page 5 L3 The description of each bit in the Control word follows EXC 1553PCI Px User s Manual page 5 7 Control Word BC Concurrent RT Operation NOTE Logic 1 enables the function 0 disables the function Bit Bit Name 15 Stop On Error 14 Even Parity 13 Halt Continue 12 Word Count Error 11 Bit Count Error 10 Incorrect Sync 09 Non Contiguo us Data 08 Error Placement Error Injection Enable 07 Bus A B 06 Auto Bus Switch 04 05 Auto Retry Code 00 03 Command Code BC RT Control Word Description Message error stops B
40. RT Operation In Continuous Loop mode the board will retransmit the message frame at a predetermined user programmable rate Use the Start Register and the Loop Count Register see page and page 5 23 to select Continuous Loop mode In Continuous Loop mode all messages relating to the active Stack pointer and Instruction counter are continuously looped until you halt the board s operation see Start Register page The Loop Time or Frame Time is a function of two control register pairs the Frame Time registers high and low and the Frame Time Resolution registers high and low The internal Frame Time counter is loaded when a Start command with the 16 bit value found in the Frame Time registers high and low is received The Frame Time counter is decremented every n x 155 nsec where nis the value of Frame Time Resolution registers high and low After all instructions are executed 1 frame the board waits until the internal Frame Time counter reaches 0 before transmitting the next frame NOTE Ifthe Frame Time is less than the time required to transmit all messages within 1 frame the subsequent frames will be transmitted with the minimum delay between them The minimum delay is approximately 20 usec measured as dead time on the bus To implement the desired Frame Time program the appropriate combinations of the two register pairs An example is described below Example Calculating Frame Time Given Frame Time of 500 msec i
41. Word 1 LSB Message Status Word Concurrent Monitor Message Block Structure page 7 2 Excalibur Systems Chapter 7 7 2 2 Message Status Word Concurrent Monitor Option The Message Status word indicates the status of the message transfer The module creates this word Do not confuse it with the 1553 Status word See L553 RT Status Words pagd 4 7 The contents of the Message Status word are shown below NOTE 1 Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Note that the Message Status word is different in RT Concurrent Monitor mode and BC RT Concurrent Monitor mode 2 A logic 1 indicates the occurrence of a status flag Bit Name End Of Message Bus A B Reserved Message Error Bit Set RT Status Bit Set TX Time Out Response Error Invalid Message RT Concurrent Monitor Invalid Word Received Reserved Word Count Error Incorrect RT Address Sync Error Non Contiguous Data RT2RT Message Error Description Message transfer completed Bus on which the message was transferred 1 BUS A Set to 0 Message Error bit bit 10 in the RT Status word was set A bit other than the Message Error bit in the RT Status word was set The Error bit is not set in conjunction with this bit The module acting as receiver in RT to RT message did not sense a transmitter status word Response time error occurred in the message even if no RT is ac
42. al mode 1553 Message blocks are stored in sequential locations in memory Sequential mode supports two types of operations Fixed Block operation 1553 messages are stored at fixed sequential blocks in the memory Sequential Fixed Block mode supports Trigger capability Link List operation 1553 messages are packed one after another in the memory separated by a header Look Up Table mode Each 1553 message is stored in a unique Message block In Look Up Table mode the board addresses the user programmable look up table when it receives a 1553 Command word The Command word s RT address T R bit and Subaddress fields make up the 11 bit pointer to a Look Up table with 2048 2K x 8 locations Use the Board Configuration register Board Configuration Register page to program the desired mode of operation EXC 1553PCI Px User s Manual page 6 1 Chapter 6 page 6 2 Bus Monitor Operation TO DETERMINE WHETHER THE BOARD IS INSTALLED AND READY TO OPERATE Perform the following procedure after a power up or a software reset 1 Check the Board ID register test for value 45 H 2 Check the Board Status register test for Board Ready bit 1 The board is installed and ready when both registers contain the correct values as written above For software reset operations set these values to 0 immediately prior to writing to the software Board Reset register NOTE Throughout this manual writing a 1 to the Start register
43. ame Time Register and Resolution Register page 5 28 The maximum value possible for the Minor Frame Time is 16 sec The example in Figure 5 4 shows a configuration of four minor frames in which Message A is sent in every frame Message B is sent in every other frame and Message C is sent once Each minor frame goes out at 10 msec 100Hz If each minor frame is 10 msec long Message A is sent every 10 msec Message B is sent every 20 msec and Message C is sent every 40 msec gt gt ee gt MINOR MINOR MINOR MINOR FRAME FRAME FRAME FRAME 1 2 3 4 A A A A B B Cc 10 msec 10 msec 10 msec 10 msec gt gt p lt lt lt lt Figure 5 4 Minor Frame Sequencing NOTE 1 The MINOR_FRAME message does not appear as a real message on the data bus 2 Frame Time should not exceed the total time of all the minor frames in the minor frame sequence see Frame Time Register page 5 27 Excalibur Systems Chapter 5 BC Concurrent RT Operation 5 2 11 Asynchronous Frame Operation During standard operation the board sets up a frame of messages and then sends them out synchronously over the bus Set up multiple frames of messages and select which one to send out Asynchronous Frame operation allows you to transmit a frame asynchronously meaning that in the middle of the transmission of the messages of a frame frame 1 Transmit another frame
44. ations Communication I O Signals Description of Connector Jl S gnal BUSAHI_1 BUSALO_1 BUSBHI_1 BUSBLO_1 BUSAHI_2 BUSALO 2 BUSBHI_2 BUSBLO 2 BUSAHI_3 BUSALO 3 BUSBHI_3 BUSBLO 3 BUSAHI_4 BUSALO 4 BUSBHI_4 BUSBLO_4 SHIELD case EXTGRSTxn EXSTARTxn EXTCLKx GND Description Channel 1 Bus A connection Channel 1 Bus B connection Channel 2 Bus A connection Channel 2 Bus B connection Channel 3 Bus A connection Channel 3 Bus B connection Channel 4 Bus A connection Channel 4 Bus B connection Provided for 1553 cables shield connection This signal is connected to the case of the computer Channel x External Time Tag Reset low active TTL input Provides an option to reset the Time Tag counter from an external source This signal can also be used for simultaneously resetting the Time Tag counter in a multiple channel application Apply a low TTL pulse of 100 nsec min With respect to the GND pin Note The reset takes affect only after the board is started in RT or BM mode External Start Low Active TTL input see Start Register page Channel x External Time Tag Clock TTL input Provides an option to drive the Time Tag Counter Clock from an external source for synchronizing in a multiple board application Connect a 250KHz or less clock with respect to the GND pin Note The external clock takes effect only after you activate the EXTCLK bit in the Time
45. ble 9 2 Jumper Settings Required to Select Coupling Mode Table 5 3 defines the jumper groups for each channel Channel Bus Jumper Group A JP1 JP2 B JP3 JP4 A JP5 JP6 B JP7 JP8 A JP9 JP10 B JP11 JP12 A JP13 JP14 3 B JP15 JP16 Oo N N a a SO OC Table 9 3 Channel Jumper Groups Example To set Channel 2 to transformer coupled short pins 1 and 2 of JP9 and JP11 and short pins 2 and 3 of JP10 and JP12 Factory Default Jumper Settings The following are the factory preset default settings JP1 3 5 7 9 11 13 15 Pins1 amp 2 Shorted Transformer Coupled mode JP2 4 6 8 10 12 14 16 Pins2 amp 3 Shorted Transformer Coupled mode EXC 1553PCI Px User s Manual page 9 3 Chapter 9 9 4 9 4 1 9 4 2 page 9 4 Mechanical and Electrical Specifications Jumpers Rev C Board Channel x 1553 Coupling Mode Select Jumpers Rev C The board can be either direct or transformer coupled to the 1553 Bus Groups of four jumpers select the coupling mode for each channel Table 5 4 defines the jumper settings for all 16 jumpers Coupling Mode Jumper Settings JP1 JP16 Direct Coupled short 2 3 Transfer Coupled short 1 2 Table 9 4 Jumper Settings Required to Select Coupling Mode Rev C Table 5 5 defines the jumper groups for each channel Channel Bus Jumper Group A JP1 JP2 B JP3 JP4 A JP5 JP6 B JP7 JP8 A JP9 JP10 B JP11 JP12 A JP13 JP14 3 B JP
46. ck area The value of this register varies from 3400 H end of Message Block area to 347E H end of Message Block Spill area Until the first buffer wrap around occurs this register contains 0000 H Excalibur Systems page 6 26 Chapter 6 6 11 18 Link List mode only 6 11 19 Look Up Table mode only 6 11 20 Bus Monitor Operation Next Message Pointer Address 3FF2 3FF3 H The Next Message pointer is a 16 bit pointer that indicates the address of the 1553 message about to be written The Next Message pointer register is updated at the end of each message storage operation It cycles from 0 H to 33FE H Last Block Register Address 3FF2 H Read the Last Block register to determine the Look Up Table block number of the current 1553 message This register is used to identify the location of the current 1553 message The Last Block register is updated at the end of each message reception Mode Code Control Register Address 3FEA H Set the Mode Code Control register to specify which 1553 Subaddress value indicates the reception of a 1553 Mode command Set the Mode Code Control register before issuing a Start command to the board To modify the Mode Code Control register issue a Stop command modify the register and then issue a Start command see Start Register page 6 23 Bit Description 02 07 0 00 01 Bit 01 BitOO Subaddresses Recognized as Mode Code 0 0 31 and 0 0 1 0 1 0 31 1 1 0 and 31
47. ck mode Set the Trigger Control register to specify the following trigger conditions Trigger source 1553 Command word or Message Status word Type of storage Store All Store Only or Store After e Active trigger word Trigger Word 1 and or 2 NOTE 1 Logic 1 enables the function 2 To use trigger s at least one of the bits Store All Store Only or Store After must be set Bit Description 07 Trigger Source 0 1553 Command Word 1 Message Status Word 05 06 Reserved 04 1 Store After 03 1 Store Only 02 1 Store All 01 1 Enable Trigger Word 2 00 1 Enable Trigger Word 1 Trigger Control Register Defining a Trigger Example Conditions e Define the Command word 0825 H as Trigger word 1 Receive Command for RT 1 Subaddress 1 and 5 words e Ignore the Word Count field e Use Trigger word 1 Disable Trigger word 2 Procedure 1 Set Trigger Word 1 register 0825 H 2 Set Trigger Mask 1 register FFEO H 3 Set Trigger Control register 09 H Excalibur Systems Chapter 6 Bus Monitor Operation 6 10 Program Examples BM Mode Bus Monitor Sequential Fixed Block Mode BASIC Instruction Remarks 10 POKE amp H3FFF 08 Set the Board Configuration register for Bus Monitor Sequential Fixed Block mode 20 POKE amp H3FFO xx Set trigger mask 1 low to xx 30 POKE amp H3FF1 xx Set trigger mask 1 high to xx 40 POKE amp H3FF2 xx Set trigger word 1 low to xx 50 POKE
48. cribes Concurrent Monitor operation an option available only on the EXC 1553PCI PMx module The following topics are covered Concurrent Monitor Memory Map page Message Block Area page Control Register Definitions page On the PMx module the Concurrent Monitor operates automatically when the module is started in either RT or BC RT modes This monitor is not available when the module is not running in one of the above modes It operates in sequential fixed block mode the 1553 Message blocks are stored in sequential locations in memory The storing of messages starts at the first block See Ordering Information page L0 1 for part number details Concurrent Monitor Memory Map Message Block Area 128 Blocks 4800 6FFF H Next Message Pointer 3E90 H Board Options Register 3E84 H Figure 7 1 Concurrent Monitor Memory Map EXC 1553PCI Px User s Manual page 7 1 Chapter 7 Concurrent Monitor Option 7 2 Message Block Area The Message Block area is divided into 128 blocks of 80 bytes each The first block starts at address 4800 H the second at 4850 H the third at 48A0 H etc Block 127 6FAO H Block 2 48A0 H Block 1 4850 H Block 0 4800 H 7 2 1 Message Block Structure Each message block occupies 40 words These 40 words include a message status word two time tag words and all the 1553 message words 1553 Data Word 1553 Data Word 1553 Command Word Time Tag Word 2 MSB Time Tag
49. cted frame that the user scheduled to send asynchronously Asynchronous Message Count Register Address 3420 H WRITE Write to the Asynchronous Message Count register to set how many messages to send when sending the asynchronous frame over the data bus The maximum number of messages allowed in a frame is determined by the amount of available space in the message stack area of the board and the size of the individual messages EXC 1553PCI Px User s Manual page 5 29 Chapter 6 Bus Monitor Operation Bus Monitor Operation Chapter 6 describes EXC 1553PCI Px operation in Bus Monitor mode The information in this chapter applies to all 1553 channels present on the board except where indicated otherwise All addresses referred to in this chapter are offset from the base address of the channel accessed see Base Address Registers page b 7 The following topics are covered equential Fixed Block Memory Map page 6 b equential Link List Memory Map page 6 4 equential Mode Message Block Area page 6 b ook Up Table Mode Memory Map page 6 7 ook Up Table Mode page 6 B ook Up Table Mode Message Block Area page 6 10 essage Status Word page ime Tag Word page 6 12 rigger Operation page 6 113 Program Examples BM Mode page 6 17 ontrol Register Definitions page al T E1 E1 2 ea we td S vn z 5 le o gej 5 t z o j o Fr t z B a mn Sequenti
50. d Not used This bit is set whenever this device aborts a cycle when addressed as a target This bit can be reset by writing a 1 to this location Set to 10 slow timing Not used Set to 1 Set to 0 Set to 1 Address 08 H The Revision Identification register contains the revision identification number of the EXC 1553PCI Px EXC 1553PCI Px User s Manual page 2 5 Chapter 2 2 3 6 2 3 7 2 3 8 2 3 9 2 3 10 page 2 6 PCI Architecture Class Code Register CLCD Address 09 0B H Power up value FF0000 H Size 24 bits The Class code Register value indicates that the EXC 1553PCI Px does not fit into any of the defined class codes Cache Line Size Register CALN Address 0C H Power up value 00H Size 8 bits Not used Latency Timer Register LAT Address 0D H Power up value 00H Size 8 bits Not used Header Type Register HDR Address 0E H Power up value 00H Size 8 bits The EXC 1553PCI Px is a single function PCI device Built In Self Test Register BIST Address OF H Power up value 00H Size 8 bits The Built In Self Test register is not implemented in the EXC 1553PCI Px Excalibur Systems Chapter 2 2 3 11 2 3 12 PCI Architecture Base Address Registers BADR Address 10 14 18 1C 20 24 H Power up value 00000000 H for each Size 32 bits The Base Address Registers are used by the system BIOS to determine the number size and base addresse
51. d at the end of each message storage operation It cycles from 4800 H to 6FFE H Module Options Register Address 3E84 H The Module Options register is a 16 bit register in which the low 8 bits are reserved This register identifies the type of on module firmware Bit Description 10 15 Reserved 09 1 1760 08 1 1553 00 07 Reserved Board Options Register EXC 1553PCI Px User s Manual page 7 5 Chapter 8 Switching Modes of Operation Switching Modes of Operation Many test applications utilizing the EXC 1553PCI Px simulate only one operation mode i e Bus Controller For these applications the information in this chapter is not relevant If your application requires simulation of more than one mode switch from one mode of operation to another i e between the Bus Controller and Remote Terminal modes TO SWITCH BETWEEN MODES OF OPERATION 1 Halt the operation of the board via the Start register 2 Modify the Configuration register to the desired mode 3 Set up the memory as required 4 Set the Start bit in the Start register EXC 1553PCI Px User s Manual page 8 1 Chapter 9 Mechanical and Electrical Specifications Mechanical and Electrical Specifications Chapter 9 describes the mechanical and electrical specifications of the EXC 1553PCI Px board The following topics are discussed
52. dress is determined by the BIOS at system start up WARNING You should wear a suitably grounded electrostatic discharge wrist strap whenever handling the Excalibur board and use all necessary antistatic precautionary measures To install the EXC 1553PCI Px 1 1553 devices may be connected to the 1553 bus either directly direct coupled or via a bus coupling stub transformer coupled Use jumpers JP1 16 to set the coupling mode to the 1553 bus es see page P a 2 Make certain the computer power source is disconnected Insert the EXC 1553PCI Px board into any PCI compatible slot 3 Attach the user constructed 1553 bus cable to the board and to the bus The cable may be connected to and disconnected from the board while power to the computer is turned on but not while the board is transmitting over the bus EXC 1553PCI Px User s Manual page 1 3 Chapter 1 1 3 page 1 4 Introduction 1553 Bus Connections For short distances the EXC 1553PCI Px may be coupled directly to another 1553 device To ensure data integrity you must make certain that the cable connecting the two devices is properly terminated with 78 Ohm resistors see Figure 1 1 1553 Device Direct Coupled EXC 1553PCI Px Direct Coupled Figure 1 1 Direct Coupled Connection One Bus Shown If operating in the more standard Transformer coupling mode use stub coupler devices which are available from Excalibur Systems Inc Two terminators are req
53. e Time registers 350 POKE amp H3FEF XX 360 POKE amp H3401 1 Enable RT 1 Use the Active RT s look up table to enable RTs Board will simulate enabled RTs 370 POKE amp H3FFC 1 Set the Start register to 1 Starts message transfers in One Shot mode 380 STOP Control Register Definitions Options Select Register Address 7003 H Write to the Options Select register to select whether RT address 11111 RT 31 is interpreted as a valid RT address or as a Broadcast address Bit Description 01 07 0 00 1 Broadcast option is active RT 31 is a Broadcast Address No RT Status word will be transmitted 0 Broadcast option is inactive RT 31 is a Regular RT Options Select Register Global Software Reset Register Address 7002 H Write to the Global Software Reset register to reset all channels present on the board simultaneously data field don t care NOTE Global Software Reset erases all locations in dual port RAM Board status Board ID and Firmware Revision registers are written by the board after the reset operation is completed Excalibur Systems Chapter 5 5 7 3 5 7 4 5 7 5 5 7 6 BC Concurrent RT Operation Interrupt Reset Register Address 7001 H To reset the Interrupt signal generated by the channel write to the Interrupt Reset register at the beginning of a user written interrupt service routine data field don t care Software Reset Register Address 7000 H Write t
54. e interrupts may be reset by writing to the relevant channel s Interrupt Reset Register 7001 H After the interrupt is reset by writing to the relevant Interrupt Reset Registers the bits in the Interrupt Status Register will automatically be reset Bit Description 31 4 Always set to 0 03 1 Interrupt from channel 3 02 1 Interrupt from channel 2 01 1 Interrupt from channel 1 00 1 Interrupt from channel 0 Interrupt Status Register Excalibur Systems Chapter 3 Bus Controller Operation 3 Bus Controller Operation In this manual the Bus Controller BC mode is included in BC Concurrent RT mode Refer to Chapter 5 BC Concurrent RT page for information regarding BC mode EXC 1553PCI Px User s Manual page 3 1 Chapter 3 Bus Controller Operation page 3 2 Excalibur Systems Chapter 4 Remote Terminal Operation Remote Terminal Operation Chapter 4 describes EXC 1553PCI Px operation in Remote Terminal RT mode The information in this chapter applies to all 1553 channels present on the board All addresses referred to in this chapter are offset from the base address of the channel accessed see Base Address Registers page p 7 The following topics are covered RT Memory Map page 4 b Data Block Look Up Table page 4 4 Active RT Table page 45 1553 RT Status Words page 4 7 essage Stack page 4 B RT Last Command Words page 4 1 553 RT BIT Words page 4 11 553 RT Vector Words page 4 11 ode Codes pa
55. er function see page 6 15 Define which trigger is active Trigger 1 Trigger 2 or both via the Trigger Control Register see page 6 L6 rigger Control Register Using the 1553 Command Word Trigger Word Registers Use a 1553 Command word as a trigger when you want to filter messages based on information found in the Command word For example if you want to filter messages from a particular RT or with a particular word count set the Trigger Word register with those parameters defined in the 1553 Command word sjjisjiejnjiojojs z e s ajsjeji o RT Address Subaddress Word Count Field T R Field Field Using the Message Status Word Trigger Word Registers Use a Message Status word as a trigger when you want to filter messages based on information found in the Message Status word Do not confuse the Message Status word with the 1553 Status word see page 4 7 For example if you want to filter messages transferred over bus A vs bus B or error messages set the Trigger Word register with those parameters defined in the Message Status word For an explanation of the see page a ea eA 6 ee eae ee Message Status Word Bits 15 0 Excalibur Systems Chapter 6 6 9 2 Bus Monitor Operation Trigger Mask Registers 1 and 2 Address 3FF0 3FEC H Set the Trigger Mask register to define which bits of the trigger word defined in the Trigger Word register are relevant and which can be ignored
56. er value 4 gt Counter s resolution 20 usec To reset the Time Tag counter to 0 any time write to the Time Tag Reset Register see Control Register Definitions page 4 55 When the first command of each message is received the value of the 16 lower bits of the Time Tag Counter register are written to dual port RAM NOTE 1 The counter s value can be read any time by reading the Time Tag Counter addresses see Control Register page 4 15 2 The counter can also be clocked and or reset from an external source see Connectors page p 5 Example How To Calculate Elapsed Time Time Tag Resolution register 03 initialized before Start command Time Tag values read during or after message transfers Low 40 H High 10 H Time elapsed since Start command Time Tag register value x Time Tag Resolution value 1 x 4 usec 1040 H x 03 1 x 4 usec 4160 Dec x 4 x 4 usec 66560 usec 66 56 msec 1553 Command Word The command word location contains the 1553 command word associated with the message Only active RT 1553 command words are stored Excalibur Systems Chapter 4 4 5 4 4 6 4 7 4 8 Remote Terminal Operation RT To RT Messages When the board is operating as both RTs in an RT to RT transfer e The board transmits both 1553 Status and Data words onto the bus e The board does not copy the Transmit data block into the Receiver data block area pointed to by t
57. etween 1553 messages The Time Tag uses a 32 bit free running counter whose resolution is fixed at 4 usec per bit Reset the Time Tag counter to 0 any time by writing to the Time Tag Reset register see Time Tag Reset Register page 5 19 The Time Tag counter s value is written to the dual port RAM during the reception of the first command of each message NOTE In addition to reading the Time Tag value in the message stack the user can also read the counter s value at any time in the Time Tag counter see Time Tag Counter page 6 19 Excalibur Systems Chapter 6 6 9 Bus Monitor Operation Trigger Operation Only Sequential Fixed Block mode supports triggers A trigger is a filter the user can set to tell the board when and how to store 1553 messages The board can be programmed to store messages in the following ways Store All Stores all 1553 messages without regard to triggers no triggers are active Store Only Stores only messages that meet the trigger condition Store After Stores only the trigger message and messages that come after the trigger message The user can define up to two triggers Each trigger is defined using two registers Trigger Word Register Trigger Mask Register Use the Trigger Word Register to define a particular 1553 Command word or a Message Status word as a trigger For example use the Message Status word as the trigger source to store all messages on bus A only messages
58. frame 2 and then return to continue transmitting the messages of the previous frame frame 1 To transmit an asynchronous frame you must write the number of messages in the asynchronous frame into the Asynchronous Message Count register place a pointer to the beginning of the asynchronous frame in the Asynchronous Frame Pointer register and then set the Asynchronous Start Flag register to a non zero value This will send out the asynchronous frame over the bus see Asynchronous Start Asynchronous EXC 1553PCI Px User s Manual page 5 11 Chapter 5 BC Concurrent RT Operation 5 3 Remote Terminal Simulation When the board is simulating both the Bus Controller and one or more Remote Terminals you must write the simulated Remote Terminal 1553 Status word and Data word s into the message block in the sequence in which they are to be transmitted over the 1553 bus see Message Block Formats page 5 113 To indicate to the board that Remote Terminals are to be simulated write to the 32 byte Active Remote Terminal table Each entry in the 32 byte table corresponds to a specific Remote Terminal The first byte is for RT 0 the second to RT 1 and the last byte is for RT 31 for a total of 32 locations A table entry value of 1 enables the Remote Terminal simulation by the board a value of 0 disables the simulation by the board RT 31 Active RT byte 341F H RT 30 Active RT byte RT 0 Active RT byte 3400 H Fi
59. ge 4 12 roadcast Mode page 4 12 rror Injection Features page 4 13 Program Example RT Mode page 4 14 ontrol Register Definitions page 4 15 The EXC 1553PCI Px can be configured to simulate up to 32 remote erminals The user selects which terminal s are operating active In addition errors can be injected into message responses er After receiving the Start command the board handles the transfer of all messages see page 4 15 Data associated with a particular RT subaddress combination is transferred via a 2K x 8 Look up table which points to one of 200 data blocks You load data blocks associated with transmit commands with 1553 data to transmit and read received 1553 data from data blocks associated with receive commands The board will respond properly to messages received with an intermessage gap of 4 usec The user chooses whether the remote terminal should transmit its 1553 status word at the end of a message even if the message contains invalid data words invalid as specified by MIL STD 1553 Use the Status Response register to activate or disable this feature See Control Register Definitions page 4 15 EXC 1553PCI Px User s Manual page 4 1 Chapter 4 page 4 2 Remote Terminal Operation The remote terminal transmits its 1553 status word in approximately 4 usec Use the RT Response Time register to increase the time it takes the remote terminal to transmit the 1553 status word Since most 1553 para
60. gure 5 5 Active RT Table BC Concurrent RT Mode Bit Description 01 07 0 00 1 Enabled 0 Disabled Active RT Byte Definition BC Concurrent RT Mode page 5 12 Excalibur Systems Chapter 5 5 4 BC Concurrent RT Operation Message Block Formats The Message block contains or will contain after response from an RT the entire 1553 message as it appears on the 1553 bus including Command word s Data word s and Status word s Examples of Message block formats follow Example No 1 Transmit Command Operating as BC Only Block before execution 1553 Transmit Command Control Word First Location In Block Block after execution 1553 Data Word From Transmitting Remote Terminal Not Simulated 1553 Data Word RT Status Word From Transmitting Remote Terminal Not Simulated 1553 Transmit Command Control Word First Location In Block EXC 1553PCI Px User s Manual page 5 13 Chapter 5 page 5 14 BC Concurrent RT Operation Example No 2 Receive Command Operating as Both BC and Receiving RT Block before execution RT Status Word Simulated By EXC 1553PCI Px Loaded by User 1553 Data Word 1553 Data Word Simulated By EXC 1553PCI Px Loaded by User 1553 Receive Command Control Word First Location In Block Block after execution RT Status Word 1553 Data Word 1553 Data Word 1553 Receive Command Control Word First Location In Block Excalibur Systems Chapter 5 5 5 BC C
61. he last location of the message indicating the length of the message The next message will start at the first location of the Message Block area 0000H The following figures illustrate the contents of the Message block For a description of the Time Tag function see ime Tag Word page 6 112 Information is stored in the memory Word in the following sequence Offset End Of File XXFF 1553 Data Word 1553 Data Word A ss Commended d me tegwost id re awed id Wessege tus od Message Header Address of Next Block 0 Figure 6 4 Bus Monitor Message Block Link List Operation Excalibur Systems Bus Monitor Operation Look Up Table Mode Memory Map Time Tag Options Time Tag Counter Word 1 Time Tag Counter Word 0 Time Tag Reset Register Reserved Options Select Global Software Reset Register Interrupt Reset Register Software Reset Register Data Block Look Up Table 2K x 8 Board Configuration Register Board ID Register Board Status Register Start Register Interrupt Condition Register Message Status Register Reserved Time Tag Resolution Reserved Last Block Register Reserved Mode Code Control Register Broadcast Control Register EXC 1553PCI Px User s Manual 700C H 700A 700B H 7008 7009 H 7007 H 7004 7006 H 7003 H 7002 H 7001 H 7000 H 4000 47FF H 3FFF H 3FFE H 3FFD H 3FFC H 3FFB H 3FFA H 3FF8 3F9 H 3FF7 H 3FF3
62. he look up table pointer RT Last Command Words Address 3400 343F H The Last command word locations are reserved for the 32 1553 Last command words The board writes to these locations at the end of each message transfer for active RTs only The first word is for RT 0 the next word is for RT 1 and the last word is for RT 31 These words are used for the implementation of the Transmit Last Command Word Mode code NOTE Only command words of valid messages containing no errors are recorded in this table 1553 RT BIT Words Address 3440 347F H The RT BIT word locations are reserved for the 32 1553 BIT words Load the desired BIT words into the corresponding locations in the block The first word is for RT 0 the next word is for RT 1 and the last word is for RT 31 These words are used to implement the Transmit BIT Word Mode code 1553 RT Vector Words Address 3480 34BF H The RT Vector Word locations are reserved for the 32 1553 Vector words Load the desired Vector words into the corresponding locations in the block The first word is for RT 0 the next word is for RT 1 and the last word is for RT 31 These words are used to implement the Transmit Vector word Mode code EXC 1553PCI Px User s Manual page 4 11 Chapter 4 4 9 4 10 page 4 12 Remote Terminal Operation Mode Codes The user can program the Subaddress code that will indicate that a Mode command has been received Either or both of the fo
63. in the following Offset sequence 1553 Data Word 1553 Data Word 8 1553 Command Word 6 Time Tag Word 1 4 Time Tag Word 0 2 Message Status Word 0 Figure 6 3 Bus Monitor Message Block Fixed Block Operation EXC 1553PCI Px User s Manual page 6 5 Chapter 6 6 3 2 page 6 6 Bus Monitor Operation Message Block Link List Operation In Link List operation the Message Block area is divided into a linked list of message blocks The length of each message block varies according to message size The first two locations in each block comprise the message header This header contains the address of the next Message Block header The header of the last 1553 block received contains XXFF End of File indicating that there are no more messages stored After a message is processed and stored in memory the header of the preceding message block is updated from XXFF to the address of the header in the block of the newly stored message The Link List method can store more data than Fixed Block operation Take special care with the last message in the Message Block area Since the buffer never wraps around in the middle of a message and a message may start at any address up to 3DFE H the final message in the buffer may extend past the end of the standard Message Block area into the Message Block Spill area The End Buffer pointer End page 6 B6 exists for this special case The End Buffer pointer points to the address after t
64. ing and testing 1553 interfaces and performing system simulation of the MIL STD 1553 bus All standard variations of the MIL STD 1553 protocol are handled by the board Each channel of the EXC 1553PCI Px contains 32k x 8 of dual port RAM for data blocks control registers and look up tables All data blocks and control registers are memory mapped and may be accessed in real time Each of the independent dual redundant 1553 channels may be programmed to operate in one of four modes of operation Bus Controller Remote Terminal Bus Controller Concurrent RT and Bus Monitor The EXC 1553PCI Px comes complete with menu driven software a C driver software library including source code 1553 adapter cables and couplers are an optional extra EXC 1553PCI Px User s Manual page 1 1 Chapter 1 EXC 1553PCI Px Board Features Up to four independent 1553 channels Features Per Channel Examples of user selectable parameters Operates as BC RT BC Concurrent RT or Triggerable Bus Monitor Handles 4usec intermessage gap times in all modes Real time operation Multiple protocol capability i e 1553A B F 16 Multiple RT simulation up to 32 remote terminals Introduction PCI half size board Programmable broadcast mode Multi mode triggerable Monitor Extensive interrupt features Error injection capability Word count 3 words Incorrect sync Incorrect RT address Non contiguous data Select whether an RT will
65. its are active if set to 1 Bit 07 06 05 04 03 02 01 00 Description 1 Board Type is EXC 1553PCI Px X Don t Care X Don t Care 1 Board Halted 0 Board Running 1 Self Test OK 1 Timers OK 1 RAM OK 1 Board Ready Board Status Register NOTE Board operation stops after you clear the Start bit in the Start page 6 22 Register Following this the board sets bit 04 Board Halted Certain registers may be modified only after the Board Halted bit has been set After receiving a subsequent Start command by writing to the Start register the board resets the Board Halted bit The condition of this bit after power up or software reset is logic 1 Excalibur Systems Chapter 6 6 11 11 Bus Monitor Operation Start Register Address BFFC H The Start Register controls the Start Halt operation of the board Refer to the Board Halted bit Data bit 04 in Board Status Register page which indicates when the board has been halted Set the Start Register to execute one of the functions described below Bit 06 07 05 04 03 01 02 00 Description 1 Stop On Trigger 0 Continue After Stop 1 Initialize Board 0 Stay in Monitor Mode 1 Clear Memory 0 Don t Clear Memory 1 Start Operation 0 Halt Start Register NOTE 1 The board tests Clear Memory bit 03 and Initialize Board bit 04 only when the Start Halt bit bit 00 0 Clear Memory clears the 1553 me
66. llowing codes can be used 11111 and 00000 You must program the Mode Code Control register as described in page 4 15 The board handles all dual redundant 1553B Mode codes The Word Count field is decoded according to MIL STD 1553B One of the Mode codes Synchronize with Data word is operated upon as a standard message transfer using the Data Block look up table When the board encounters the Synchronize with Data word Mode code the command word s RT Address T R bit and Subaddress fields are used as a pointer to the look up table The table entries that are addressed when the T R bit 0 and Subaddress 00000 or 11111 should contain a Data Block number 0 199 indicating where the Synchronize with Data Word s data word should be stored The data associated with mode codes Transmit Last Command Transmit Bit word and Transmit Vector word is set using the dedicated blocks in the on board memory described in and page 4 11 Broadcast Mode To operate the board in the broadcast environment select the appropriate bit setting as defined in Options Select Register page 4 When operating in Broadcast mode you must set the active RT look up table entry for RT 31 as Not Active The board reads the Options Select Register to determine whether the board is operating in Broadcast mode In Broadcast mode the board stores the received message in a 1553 data block area in the same way as standard message formats RT address
67. lt the Error bit has been set in the Message Status word 02 End Of Frame The last word of the last message in the frame has been sent 01 Message The last word of the message has been sent Complete 00 Wait For A message with the Halt bit set has been encountered Continue Reset the Halt bit in the Control word to continue Message Status Register NOTE Status bits are not reset by the board After reading them you must reset them Excalibur Systems Chapter 5 5 7 11 5 7 12 BC Concurrent RT Operation RT Response Time Register a ak The RT Response Time register sets the Remote Terminal s Response Time The resolution of the Response Time register is 155 nsec per bit measured as the dead time on the 1553 bus The minimum time is approximately 4 usec The value in the register is added to the minimum time The actual Response Time has a tolerance of 1 usec Set the Response Time register before issuing a Start command to the board To modify the Response Time register issue a Stop command modify the register and then issue a Start command see Register page 5 21 Last Command Data Word gt e gt lt RT Status Word ime Figure 5 6 RT Response Time Definition Example Setting the RT Response Time Register To request a response time of 9 usec Write 32 to the RT Response Time register 32 x 0 155 5usec 4 usec 9 usec Loop Count Register Address 3FF6 H The Loop Count register i
68. message status bit locations page 5 5 Chapter 5 5 2 2 5 2 3 5 2 4 page 5 6 BC Concurrent RT Operation Intermessage Gap Time The Intermessage Gap Time value is a 16 bit word that you write that allows you to insert a unique intermessage delay time between the current message and the next message The minimum Intermessage Gap Time is approximately 4 usec measured as dead time on the bus The value in the word is added to this minimum time The resolution of this word is 155 nsec per bit Intermessage Gap Time Counter The Intermessage Gap Time counter IGT_counter is a 16 bit word that you write that allows you to increase the Intermessage Gap Time by repeating the number of times the Intermessage Gap Time value is used For example if the counter is set to 0 then the gap time is not repeated and depends on the contents of the Intermessage Gap Time location If the gap time counter is 1 then the gap time is repeated once and equals the Intermessage Gap Time value x 2 etc NOTE To ensure maximum Intermessage Gap Time accuracy when using the IGT_counter use the largest possible value for the Intermessage Gap Time word and the smallest value for the IGT_counter for a given desired intermessage gap time Message Block Pointer The Message Block pointer is a 16 bit word that you write that points to the beginning of a 1553 message block o Instruction Stack Figure 5 3 Message Block Pointer BC Concurrent
69. meters such as response time status word content etc are user programmable the board can operate in various 1553 environments The board also allows you to enable or disable the 1553 Broadcast function If broadcasting is enabled RT address 31 11111 is reserved if broadcasting is disabled all 32 RT addresses are available see Options Select Register page 4 16 The 1553 Mode Code subaddress identifier see Mode Code Control page 4 22 can be programmed so that either 31 0 or both are used to indicate that the 1553 command word is a Mode code Perform the following procedure after a power up or a software reset To determine whether the board is installed and ready to operate 1 Check the Board ID register test for value 45 H 2 Check the Board Status register test for Board Ready bit 1 The board is installed and ready when both registers contain the correct values as written above For software reset operations set these values to 0 immediately prior to writing to the software Board Reset register NOTE Throughout this manual writing a 1 to the Start register is referred to as issuing a Start command Excalibur Systems Chapter 4 4 1 RT Memory Map Remote Terminal Operation Figure 4 1 illustrates the RT memory usage Reserved Time Tag Options Time Tag Counter Word 1 Time Tag Counter Word 0 Time Tag Reset Register Reserved Options Select Register Global Software Reset Register
70. ng 1 Self Test OK 1 Timers OK 1 RAM OK 1 Board Ready Board Status Register NOTE Board operation stops after you clear the Start bit in the Start Register Following this the board sets bit 04 Board Halted Certain registers may be modified only after the Board Halted bit has been set After receiving a subsequent Start command by writing to the Start register the board resets the Board Halted bit The condition of this bit after power up or software reset is logic 1 Excalibur Systems Chapter 5 5 7 8 BC Concurrent RT Operation Start Register Address BF FC H The Start register controls the Start Stop operation of the board Writing the appropriate bit bit 0 to the Start register starts the Bus Controller transfer operation When operating in Continuous Loop or n Times mode set the Start and Loop bits in the Start register The Loop and n Times number are selected via the Loop Count register In the One Shot and n Times modes the board resets the Start bit in the register after all messages have been transferred The board does not reset any bit while in Continuous Loop mode To halt the Loop operation between messages set bit 00 to 0 In order to halt the operation at the end of the entire frame set bit 02 to 0 bit 02 is not tested between message transfers Related data bit 04 in the Board Status register indicates when the board has been halted see tatus Register page 5 20 Bit Description
71. ng of the second 1553 message transfer operation To determine the arrival of the first 1553 message check the Message Status word of the first Message block The End of Message bit bit 15 in the Message Status word will be set Counter Trigger Register Address 3FF4 H Read the Counter Trigger register to determine when a specific message block number has been updated by the board Set the Counter Trigger register to a value that when equal to the Message counter will set a bit in the Message status register and set an interrupt if programmed in the Interrupt Condition register Set the Counter Trigger register before issuing a Start command to the board To modify the Counter Trigger register issue a Stop command modify the register then issue a Start command see Start Register page The user can also program the board to stop monitoring when the Counter Trigger value is equal to the Message Counter see the Stop Continue bit in the Start Register page 5 23 End Buffer Pointer Address 3FF4 3FF5 H The End Buffer pointer points to the address following the last word in the final message in the Message Block area The End Buffer pointer is updated each time a final message is written into the buffer Final messages that are longer than the remaining available space in the Message Block area do not wrap around to the start of the buffer They are spilled into the Message Block Spill area which is contiguous to the Message Blo
72. nitions Time Tag Options Register Address 700C H WRITE ONLY Set the Time Tag Options Register s 00 bit to select the current bank s Time Tag Counter Clock Source After power up or software reset the Time Tag Options Register s bit 00 is set to 0 i e Internal Clock Source For external Time Tag Clock eel Communication I O Signals E Conte ceal escription of Connector JI page Bit Description 01 07 Reserved 00 0 Internal Time Tag Clock 1 External Time Tag Clock Time Tag Options Register Time Tag Counter Address 7008 700B H READ ONLY Read the two 16 bit words of the Time Tag counter to determine the current free running 32 bit Time Tag counter value You may read the counter at any time The counter must be read in the following sequence 1 Read 7008 H 16 bit read only 2 Read 700A H 16 bit read only 7008 H contains the lo word 700A H contains the hi word The Time Tag resolution register sets the resolution of the counter Time Tag Resolution Register page 4 18 The counter is reset upon power up or software reset and stays reset until a Start command is issued When a Start command is issued the counter starts counting To re initialize to 0 write to the Time Tag Reset register When it reaches the value FFFFFFFF H the counter wraps around to 0 and continues counting Time Tag Reset Register Address 7007 H WRITE ONLY Write to the Time Tag Reset register to reset the channel
73. ntents of the Message status word are described below NOTE A logic 1 indicates occurrence of status flag Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit Name End Of Message Reserved Incorrect 1553 Bus Message Error Bit Set RT Status Bit Set Invalid Message Error Response Time Failure Reserved Invalid Word Received Word Count High Word Count Low Incorrect RT Address Incorrect Sync Received Non Contiguous Data Reserved Error Message Status Word EXC 1553PCI Px User s Manual Description Message transfer completed Set to 0 Remote Terminal response was not received on the active 1553 bus Message Error bit bit 10 in the RT Status word was set A bit was set in the RT Status word other than the Message Error bit The error bit is not set in conjunction with this bit A 1553 message level error occurred e g Word count incorrect sync details in the bits described below RT responded late see BC Response Time Register page 5 P6 Set to 0 At least one invalid 1553 word received e g bit count Manchester code parity RT transmitted too many words RT transmitted too few words 1553 Status word received did not contain the correct RT address Sync of either the status or data word s is incorrect Invalid gap between received 1553 words Set to 0 Error occurred The error type is defined in one of the other
74. o the Software Reset register to reset the channel data field don t care The Board status the Board ID and Firmware revision registers are written by the board after the reset operation has been completed WARNING Reset erases all memory locations in the dual port RAM Board Configuration Register Address 3FFF H Before issuing a Start command to the board set the operating mode of the board via the Board Configuration register To modify the Board Configuration register issue a Stop command modify the register and then issue a Start command see Start Register page 6 21 Hex Operating Mode Value 04 BC Concurrent RT Board Configuration Register Value BC RT Mode Board ID Register Address 3FFE H The Board ID register contains a fixed value that can be read by your initialization routine to detect the presence of the board The one byte value of this register is 45 Hex ASCII value E EXC 1553PCI Px User s Manual page 5 19 Chapter 5 5 7 7 page 5 20 BC Concurrent RT Operation Board Status Register Address BFFD H The Board Status register indicates the status of the board In addition this register indicates which options have been selected as described below Do not modify this register Status bits are active if set to 1 Bit 07 06 05 04 03 02 01 00 Description 1 Board Type is EXC 1553PCI Px X Don t Care X Don t Care 1 Board Halted 0 Board Runni
75. o the host in dual port RAM using the following structure beginning at address 0 struct LOOPBACK usint frame_val usint frame_status usint resp_ status usint early_val usint receive_data1 usint status_1 usint receive_data2 usint status_ 2 usint mc_status usint ttag_val_lo usint ttag_val_hi usint ttag_status usint prl lL_loopback page 11 4 Definition frame time counter status response time counter status first looped word test using command sync second looped word test using data sync mode code function test time tag status Address in Dual Port RAM 0 2 12 14 16 Status Value X not for user 8000H passed 8001H failed 8000H passed 8001H failed 6 LSB must be 15H 5555H 8000H passed else failed AAAAH 8000H passed else failed 8000H passed else failed 30D4H 2 0 8000H passed 8001H failed 8 LSB contain the CPU version Excalibur Systems Chapter 11 Appendix D External Loopback Test Appendices The External Loopback Test is used to check the 1553 transceivers transformers and associated bus cables NOTE The External Loopback Test requires a loopback cable to connect bus A to bus B To initiate the External Loopback test 1 Write FF H into the Board Configuration Register 2 Write 1 into the Start Register 3 Wait for 0 in the Start Register The results of this test are returned to the ho
76. oncurrent RT Operation Example No 3 RT to RT Command Operating as BC and Receiving RT Block before execution Receive RT Status Word Simulated By EXC 1553PCI Px Loaded By User Leave Empty For Data N Leave Empty For Data 1 Leave Empty For Transmit RT Status Word 1553 Transmit Command 1553 Receive Command Control Word First Location In Block Block after execution Receive RT Status Word 1553 Data Word From Transmitting Remote Terminal Not Simulated 1553 Data Word Transmit RT Status Word From Transmitting Remote Terminal Not Simulated 1553 Transmit Command 1553 Receive Command Control Word First Location In Block Continuous or One Shot Message Transfers The board can transfer all programmed messages once in a continuous loop or for n number of times In One Shot mode after receiving a Start command the board transfers all messages sets the Message Complete bit in the Message Status register issues an interrupt if programmed and waits for a new Start command Use the Start register see page to select One Shot mode In n Times mode load the Loop Count register with the number of times to transmit the messages frame and set the Loop and Start bits in the Start register Transmit 1 255 times see page 5 21 and page 5 B3 The time between frames is determined by the Frame Time register see page 5 27 EXC 1553PCI Px User s Manual page 5 15 Chapter 5 page 5 16 BC Concurrent
77. ondition enabled in this register occurs an interrupt is generated Logic 1 enables the interrupt condition Check the Message Status register to determine which condition caused the interrupt Set the Interrupt Condition register before issuing a Start command to the board To modify the Interrupt Condition register issue a Stop command modify the register then issue a Start command see 6 23 page 6 23 NOTE For all interrupt conditions the interrupt will be sent at the end of the message Bit Description 03 07 0 02 1 Counter Trigger Match Valid Only in Sequential Fixed Block Mode 01 1 Message Reception in Progress Valid in All Modes 00 1 Trigger Word Received Valid Only in Sequential Fixed Block Mode Interrupt Condition Register Excalibur Systems Chapter 6 6 11 13 6 11 14 Bus Monitor Operation Message Status Register Address 3FFA H The Message Status register indicates the status of the current message being processed Each status bit is described in the table below Logic 1 indicates that the condition is activated Bit Description 03 07 0 02 1 Counter Trigger Match 01 1 Message Reception In Progress 00 1 Trigger Word Received Busy Trigger word received is valid only In Sequential Fixed Block mode Busy is valid in Linked List and Look Up Table mode The busy bit is set when the board is processing a message It is set together with message reception in progress bu
78. ote Terminal Operation Interrupt Condition Register Address 33FC H The Interrupt Condition register allows you to enable an interrupt trigger The Message Complete bit works in conjunction with the Interrupt bit in the Active RT table When a message is received by an RT for which the Active RT interrupt bit is set the board will check the Message Complete bit If this bit is also set an interrupt will be generated Set the Interrupt Condition register before issuing a Start command to the board To modify the Interrupt Condition register issue a Stop command modify the register and then issue a Start command see Start Register page k 18 Bit Description 02 07 0 01 Message Complete 00 0 Interrupt Condition Register Mode Code Conirol Register Address 3266 H The Mode Code Control register allows you to specify which 1553 Subaddress value indicates the reception of a 1553 Mode command Set the Mode Code Control register before issuing a Start command to the board To modify the Mode Code Control register issue a Stop command apie the register then issue a Start command see page 1 18 Bit Description 02 07 0 00 01 Bit 01 Bit 00 Subaddresses Recognized as Mode Code 0 0 31 and 0 0 1 0 1 0 31 1 1 0 and 31 Mode Code Control Register Excalibur Systems Chapter 5 BC Concurrent RT Operation BC Concurrent RT Operation Chapter 5 describes EXC 1553PCI Px operation in Bus Controller Concurrent Remo
79. plication factor 1 see Calculating Frame Time page 5 16 Set the Frame Time register before issuing a Start command to the board To modify the Frame Time register issue a Stop command modify the register and then issue a Start command see page b 21 Frame Time Resolution Register Address 3FEC 3FED H The 16 bit Frame Time Resolution value represents the resolution of the Frame Time counter in increments of 155 nsec The high register contains the MSB the low register contains the LSB see also page 5 65 Set the Frame Time Resolution register before issuing a Start command to the board For an example of how to calculate Frame Time and Frame Time Resolution see page 5 16 To modify the Frame Time Resolution register issue a Stop command modify the register and then issue a Start command see Start Register page Instruction Counter Address 3FEB 3FEA H The Instruction Counter must be loaded with the number of instructions 1553 Messages to execute in the current frame The value must be greater than 0 before the user writes to the Start register to begin a transmission Set the Instruction counter to 1 for one message 2 for two messages etc The board updates the Instruction counter by decrementing the value and writing it back to memory at the end of each message transfer Set the Instruction Counter register before issuing a Start command to the board To modify the Instruction Counter register is
80. rame The skip takes place immediately and does not wait until the Intermessage Gap Time expires Jump Command Operation Modify the board s BC transfer cycle by setting the Jump command in the BC Control word The Jump command instructs the board to operate on a new instruction stack or new stack entry in the same stack This Control word is followed by a Stack Pointer word instead of the usual 1553 command word In addition the stack pointer is followed by an Instruction Count value The Jump command is tested after the board has tested the Halt Continue bit in the Control word The jump takes place immediately and does not wait until the Intermessage Gap Time expires EXC 1553PCI Px User s Manual page 5 9 Chapter 5 BC Concurrent RT Operation 5 2 10 page 5 10 The memory structure of the jump command is illustrated below Instruction Count Third Word Stack Pointer Second Word Control Word First Word Jump Command Memory Structure Minor Frame Operation The Minor Frame type of message is used in the following ways To function as a delay time message between groups of messages To produce a list of messages that will be sent out over the bus at different frequencies Minor frame time is defined as the time elapsed from the beginning of a minor frame to beginning of the next minor frame To set up minor frame operation you must begin each minor frame with a minor frame command see Minor Fr
81. rd status the Board ID Firmware revision are written by the board after the reset operation has been completed WARNING Reset erases all memory locations in the dual port RAM Excalibur Systems Chapter 4 4 13 8 4 13 9 4 13 10 Remote Terminal Operation Board Configuration Register Address 3FFF H Use the Board configuration register to set the operating mode of the board You must set the Board Configuration register before issuing a Start command to the board To modify the Board Configuration register issue a Stop command modify the register then issue a Start command see Start Register page Pers Hex Value Operating Mode 02 RT Mode Board Configuration Register Value RT Mode Board ID Register Address 3FFE H The Board ID register contains a fixed value that can be read by your initialization routine to detect the presence of the board The one byte value of this register is 45 Hex ASCII value E Board Status Register Address 3FFD H The Board Status register indicates the status of the board In addition this register indicates which options have been selected Do not modify this register Status bits are active if set to 1 Bit Description 07 1 Board Type is EXC 1553PCI Px 06 X Don t Care 05 X Don t Care 04 1 Board Halted 0 Board Running 03 1 Self Test OK 02 1 Timers OK 01 1 RAM OK 00 1 Board Ready Board Status Register NOTE Board operation stop
82. red This status is valid for Sequential Fixed Block mode with the following modes Store After mode the Trigger Found bit will be set only in the first Trigger message Store Only mode the Trigger Found bit will be set in every Trigger message See Trigger Operation page 6 13 RT to RT message was received Message Error bit bit 10 in the RT Status word was set A bit other than the Message Error bit in the RT Status word was set The Error Bit is not set in conjunction with this bit 1553 message level error occurred Word Count Incorrect Sync etc Examine the other bits in this table to determine which error occurred Set to 0 Bus on which the message was transferred 0 BusB 1 BusA At least one invalid 1553 word received i e bit count Manchester code parity RT transmitted too many words RT transmitted too few words Received 1553 Status word did not contain the correct RT address Sync of either the command or the data word s is incorrect Invalid gap between received 1553 words Response Time error occurred in the message Error occurred The error type is defined in one of the other message status bit locations page 6 11 Chapter 6 6 8 page 6 12 Bus Monitor Operation Time Tag Word In all Bus Monitor modes each incoming message is stored with a Time Tag value The Time Tag value is a 32 bit word used to determine the time elapsed since the Start command was issued or the time b
83. return a status word in the event a message containing a data word error is received by the RT Selectable broadcast mode Variable response time Variable transmit amplitude Select mode code subaddress 00000 11111 or both 1553A RT timing Define each bit in the 1553 Status word Each of the board s channels has four modes of operation Bus Controller BC mode Multiple Remote Terminal RT mode up to 32 RTs BC with Concurrent RT operation up to 32 RTs Triggerable Bus Monitor mode The EXC 1553PCI Px can be ordered with one to four installed channels See Ordering Information page 10 1 for the exact part numbers page 1 2 Excalibur Systems Chapter 1 1 2 1 2 1 1 2 2 Introduction Installation EXC 1553PCI Px installation includes installing the software for each system and installing the board Software Installation The standard software included with the EXC 1553PCI Px is for Windows operating systems Software compatible with other operating systems is available and can be downloaded from our website www mil 1553 com For information about installing the accompanying software drivers see ReadMe txt on the Galahad Software Tools diskettes that came with your board Board Installation Installation of the EXC 1553PCI Px board is similar to that of all PCI boards The EXC 1553PCI Px complies with the Plug and Play specification of the PCI standard and as such its absolute ad
84. s after you clear the Start bit in the Start Register Following this the board sets bit 04 Board Halted Certain registers may be modified only after the Board Halted bit has been set After receiving a subsequent Start command by writing to the Start register the board resets the Board Halted bit The condition of this bit after power up or software reset is logic 1 EXC 1553PCI Px User s Manual page 4 17 Chapter 4 4 13 11 4 13 12 4 13 13 page 4 18 Remote Terminal Operation Start Register Address 3FFC H The Start register controls the Start Stop operation of the board The user can Start then Stop the RT operation modify RT parameters example the Error Injection register or Response Time and then issue a new Start command in real time For more information about Bit 04 Board Halted Running in the Board Status Register see the note in Board Status Register Bit Description 01 07 0 00 1 Start Operation 0 Stop Start Register NOTE To start send a low TTL pulse of 100 nsec minimum to the EXSTARTxn pin see sae Ph Message Status Register Address 3FFB H The Message Status register indicates that a 1553 message has been received A logic 1 indicates active condition This bit is also set for messages with errors Bit Description 01 07 0 00 Message Complete Message Status Register NOTE After reading reset the Message Complete bit the board does not reset this bit Time Tag Resol
85. s of memory pages required by the board within host address space Five memory pages are required by the EXC 1553PCI Px one for the PCI Configuration Space Header and four for the 1553 channels Register Offset Size Function Base Address Register 0 10H 256 Byte PCI Configuration Space Header Base Address Register 1 14H 32 Kb MIL STD 1553 Channel 0 Base Address Register 2 18H 32 Kb MIL STD 1553 Channel 1 Base Address Register 3 1CH 32 Kb MIL STD 1553 Channel 2 Base Address Register 4 20H 32 Kb MIL STD 1553 Channel 3 Table 2 1 Base Address Registers Definition Each Base Address Register contains 32 bits Bit Description 04 31 Address of memory region with lower 4 bits removed 03 Always 0 memory is not prefetchable 01 02 Always 0 memory may be mapped anywhere 00 Always 0 indicates memory space Base Address Register Cardbus CIS Pointer Address 28 H Power up value 00000000 H Size 32 bits The Cardbus Pointer is not implemented on the EXC 1553PCI Px EXC 1553PCI Px User s Manual page 2 7 Chapter 2 PCI Architecture 2 3 13 Subsystem ID Address 2C H Power up value 0000 H Size 16 bits 2 3 14 Subvendor ID Address 2E H Power up value 0000 H Size 16 bits 2 3 15 Expansion ROM Base Address Register XROM Address 30 H Power up value 00000000 H Size 32 bits The Expansion ROM Space is not implemented on the EXC 1553PCI Px Address 34 3A H 2 3 16 Reserved Power up val
86. s required Method Select Frame Time Resolution of 3225 Dec 0C99 H Frame Time Resolution 3225 x 155 nsec 500 usec 5 msec Subsequently the Frame Time register value must be equal to 500 msec desired time 5 msec 1000 Dec 1 03E7 H Count 1 Before issuing the Start command set e Frame Time register low E7 H e Frame Time register high 03 e Frame Time Resolution register low 99 Hex e Frame Time Resolution register high 0C Excalibur Systems Chapter 5 5 5 1 Mode Codes BC Concurrent RT Operation The board handles all dual redundant 1553B Mode codes the Word Count field is decoded according to MIL STD 1553B The two Quad Redundant Mode codes Selected Transmitter Shutdown and Override Selected Transmitter Shutdown are not implemented by the board 5 6 Program Example BC Concurrent RT Mode NOTE All values are in HEX unless otherwise stated BASIC Instruction 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE POKE amp H3FFF 04 amp H3FF0 00 amp H3FF1 00 amp H3FF2 amp HFF amp H00 00 amp H H01 01 amp H02 xx amp H03 xx amp H08 amp H40 amp H09 01 amp HOA xx amp HOB xx amp H100 amp H80 amp H101 00 amp H
87. s used in conjunction with the Loop bit in the Start register If the Loop bit in the Start register is set then set the Loop Count register to specify the number of times the Message frame will be transmitted A value of zero is interpreted as a request for continuous looping Set the Loop Counter register before issuing a Start command to the board To modify the Loop Counter register issue a Stop command modify the register and then issue a Start command see Start Register page 5 21 Bit Value Description 00 07 0 Transmits in Continuous Loop 1 255 Sends Message Frame n times 1 255 as defined Loop Count Register EXC 1553PCI Px User s Manual page 5 23 Chapter 5 5 7 13 page 5 24 BC Concurrent RT Operation Bit Count Register Address BFF5 H The Bit Count Register sets the total number of bits in the 1553 word including Sync 3 and Parity 1 This register is used by the board only for messages for which the Bit Count Error bit is set in the Control Word of the Message Block see page 5 B If the Bit Count Error bit is not set a valid 20 bit word is transmitted regardless of the contents of the Bit Count Register Set the Bit Count Register before issuing a Start command to the board To modify the Bit Count Register issue a Stop command modify the register and then issue a Start command see page 5 21 Bit Description 03 07 0 00 02 Bit 02 Bit 01 Bit 00 No of 1553 bits sent per word 0 0 0 1
88. sing both registers is approximately 16 sec Example To generate a Minor Frame Time of 1 sec set the Minor Frame Time register to F424 H 62 500 Dec and set the Minor Frame Resolution register to 10 H 16 Dec The Minor Frame Time Resolution register must be set before issuing a Start command to the board To modify the Minor Frame Time Resolution register issue a Stop command modify the register and then issue a Start command see Start Register page J Board Options Register Address 3E84 H READ ONLY The Board Options Register is a 16 bit register in which the low 8 bits are reserved This register identifies the type of on board firmware Bit Description 10 15 Reserved 09 1 1760 08 1 1553 00 07 Reserved Board Options Register Excalibur Systems Chapter 5 5 7 23 5 7 24 5 7 25 5 7 26 BC Concurrent RT Operation Firmware Revision Register Address 3E80 H The Firmware Revision register indicates the revision level of the on board firmware The value 0001 0010 would be read as revision level 1 2 Asynchronous Start Flag Register Address 3424 H WRITE Write a 1 to the Asynchronous Start Flag register to indicate that it is now time to send a selected frame asynchronously The board will automatically reset this value to 0 when it sends the frame Asynchronous Frame Pointer Register Address 3422 H WRITE The Asynchronous Frame Pointer register points to the beginning of the sele
89. ssage blocks and all readable control registers The Initialize Board bit enables you to re initialize the board change the board s mode of operation modify the Board Configuration register and restart To switch Monitor modes you must stop and start the board Start Halt bit bit 00 and set the Initialize Board bit bit 04 After the specific function is completed the board sets the Initialize Board bit and the Start Halt bit to 0 The Stop On Trigger Continue bit bit 05 is used in Sequential Fixed Block mode only The Stop On Trigger Continue bit is tested when the Message counter equals the Message Counter Trigger If Stop On Trigger Continue bit 1 the board will stop storing 1553 messages Setting Stop On Trigger Continue bit 0 allows the board to continue monitoring operations You must first Continue set bit 05 1 before Halting the board setting bit 00 0 EXC 1553PCI Px User s Manual page 6 23 Chapter 6 6 11 12 page 6 24 Bus Monitor Operation 3 Bit 04 of the Board Status register is set if one of the following is true A Halt command is issued bit 00 is set to 0 An Initialize Board command is issued bit 04 is set to 1 4 It is also possible to start operation of the board by sending a low TTL pulse of 100 nsec minimum to the EXSTARTxn pin See page D5 Interrupt Condition Register Address 3FFB H Set the Interrupt Condition register to enable interrupt triggers When a c
90. st in dual port RAM using the following structure beginning at address 0 struct E LOOPBACK Definition conditions for passing E_loopback test TX bus RX bus Address in command or data sync Dual Port RAM Status Value usint frame_val 0 X not for user usint frame_status frame time counter status 2 8000H passed 8001H failed usint cmd_send 8 4 cmd_send 0 5555H TX A RX A 6 cmd_send 1 8000H passed command sync else failed 8 cmd_send 2 1234H TX A RX B cmd_send 3 8000H passed data sync else failed cmd_send 4 5555H TX B RX A E cmd_send 5 8000H passed command sync else failed 10 cmd_send 6 1234H TX B RX B 12 cmd_send 7 8000H passed data sync else failed usint ttag_val_lo 14 30D4H 2 usint ttag_val_hi 16 0 usint ttag_status time tag status 18 8000H passed 8001H failed E_loopback EXC 1553PCI Px User s Manual page 11 5 Chapter 11 Appendices The information contained in this document is believed to be accurate However no responsibility is assumed by Excalibur Systems Inc for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice June 2001 Rev B 1 page 11 6 Excalibur Systems
91. ster to RT31 Regular 40 POKE amp H4143 00 Set the Look Up Table so that Command words with Remote Terminal 5 Receive mode and Subaddress 3 point to Data Block 0 see able Mode page 6 b 50 POKE amp H4144 01 Set the Look Up Table so that Command words with Remote Terminal 5 Receive mode and Subaddress 4 point to Data Block 1 see Look Up able Mode page 6 b 60 POKE amp H3FFC 01 Start Command NOTE Messages are read from memory according to the address pointer derived from Command word see Look Up Table Model page 6 b Control Register Definitions Time Tag Options Register Address 700C H WRITE ONLY Set the Time Tag Options Register s 00 bit to select the current bank s Time Tag Counter Clock Source After power up or software reset the Time Tag Options Register s 00bit is set to 0 For external Time Tag Clock source see Communication I O Signals Description of Connector JI page Bit Description 01 07 Reserved 00 0 Internal Time Tag Clock 1 External Time Tag Clock Time Tag Options Register Excalibur Systems Chapter 6 6 11 2 6 11 3 Bus Monitor Operation Time Tag Counter Address 708 700B H READ ONLY Read the two 16 bit words of the Time Tag counter to determine the current free running 32 bit Time Tag counter value You may read the counter at any time THE COUNTER MUST BE READ IN THE FOLLOWING SEQUENCE 1 Read 7008 H 16 bit read only 2 Read 700A H 16 bi
92. sue a Stop command modify the register then issue a Start command see page 5 21 When in the Continuous Loop mode the Instruction Counter register cycles from the initial value down to 1 The low register 3FEA contains the MSB the high register 3FEB contains the LSB Therefore for an Instruction Counter less that 256 use the LSB only address 3FEB EXC 1553PCI Px User s Manual page 5 27 Chapter 5 5 7 20 5 7 21 5 7 22 page 5 28 BC Concurrent RT Operation Minor Frame Time Register Address 3FE8 H WRITE The 16 bit Minor Frame Time register is used to set the length of a single minor frame see page 5 10 The resolution of the Minor Frame Time register is 1 usec per bit The maximum value is approximately 65 msec which can be extended by the multiplier set in the Minor Frame Time Resolution register described below The Minor Frame Time register must be set before issuing a Start command to the board To modify the Minor Frame Time register issue a Stop command modify the register and then issue a Start command see page ort Minor Frame Resolution Register Address 3FE6 WRITE The Minor Frame Resolution is a multiplier of the Minor Frame Time described above The value written to the Minor Frame Resolution register allows the user to extend the Minor Frame Time beyond the 65 msec maximum in the Minor Frame Time register The maximum Minor Frame Resolution is 255 The maximum Minor Frame Time possible u
93. t read only 7008 H contains the lo word 700A H contains the hi word The resolution of the counter is 4 usec per bit The counter is reset upon power up or software reset and stays reset until a Start command is issued When a Start command is issued the counter starts counting To re initialize to 0 write to the Time Tag Reset register When it reaches the value FFFFFFFF H the counter wraps around to 0 and continues counting Time Tag Reset Register Address 7007 H WRITE ONLY Write to the Time Tag Reset register to reset the channel s Time Tag Counter data field don t care Immediately after the reset the counter will start to count from 0 NOTE The counter can also be reset from an external source see page 9 5 EXC 1553PCI Px User s Manual page 6 19 Chapter 6 6 11 4 page 6 20 Bus Monitor Operation Options Select Register Address 7003 H The Concurrent BM control bit of the Options Select Register is only relevant for users of the EXC 1553PCI P2 P3 and P4 boards The EXC 1553PCI Px provides that a second channel Channel 1 or Channel 3 may be set up to operate as Concurrent Monitors on the 1553 bus connected to Channels 0 and Channels 2 When configured in this way Channel 0 may operate as a BC and or RT while Channel 1 will concurrently monitor the Channel 0 1553 bus Similarly Channel 2 may operate as a BC and or RT while Channel 3 will concurrently monitor the Channel 2 1553 bus The
94. t is reset approximately 5 usec after the end of each message For consecutive messages with short intermessage gap times the busy bit may not be reset between messages Message Status Register NOTE Status bits are not reset by the board Reset them after reading them Time Tag Resolution Register Address 3FF7 H The 8 bit value in the Time Tag Resolution register represents the resolution of the Time Tag Counter in unites of 4 usec To determine the Time Tag Counter s resolution use the equation Time Tag Resolution register value 1 x 4 usec A value of 0 corresponds to a resolution of 4 microseconds a value of 1 corresponds to a resolution of 8 microseconds etc The user must set the Time Tag Resolution register before issuing a Start command to the board To modify the register issue a Stop command modify the register and then issue a Start command see Start Register page 6 23 EXC 1553PCI Px User s Manual page 6 25 Chapter 6 Bus Monitor Operation 6 11 15 Sequential Fixed Block mode only 6 11 16 Sequential Fixed Block mode only 6 11 17 Link List mode only Message Counter Register Address 3FF5 H Read the Message Counter register to determine the current Message Block number 0 199 The value is incremented by the board as each message is received The first counter increment to 1 which indicates that the first message has been received and stored occurs at the beginni
95. te Terminal mode The information in this chapter applies to all 1553 channels present on the board All addresses referred to in this chapter are offset from the base address of the channel accessed see page b 7 The following topics are covered page 5 b page 5 4 Remote Terminal Simulation page 5 12 essage Block Formats page 5 113 Continuous or One Shot Message Transfers page 5 15 Program Example BC Concurrent RT Mode page 5 17 Control Register Definitions page The EXC 1553PCI Px can simultaneously operate as the bus controller and up to 32 Remote Terminals The messages and the instruction stack are loaded as for BC operation In Concurrent RT mode load message blocks with the RT s 1553 Status and Data words for those Remote Terminals that you are actively simulating These words must be loaded into the appropriate locations in the message blocks in the sequence that the 1553 words appear on the 1558 bus Ss eS NOTE The requirement for loading the message blocks only applies to RTs that you are actively simulating For RTs that are not active not simulated by the board leave the corresponding locations blank in the associated 1553 message blocks The Remote Terminals simulated in BC Concurrent RT mode have a minimum response time of approximately 4 usec EXC 1553PCI Px User s Manual page 5 1 Chapter 5 page 5 2 BC Concurrent RT Operation TO DETERMINE WHETHER THE BOARD IS INSTALLED AND READY TO O
96. tive on the module 1553 message level error occurred e g Word Count Sync Error See other bits set for the exact error For example an RT to RT message which contains two receive messages At least one invalid 1553 word received i e bit count Manchester code parity Set to 0 Incorrect number of words received in the message Received 1553 Status word did not contain the correct RT address Sync of either the command or the data word s is incorrect Invalid gap between received 1553 words RT to RT message was received Error occurred The error type is defined in one of the other message status bit locations Message Status Word RT Concurrent Monitor EXC 1553PCI Px User s Manual page 7 3 Chapter 7 Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit Name End Of Message Bus A B Reserved Message Error Bit Set RT Status Bit Set Invalid Message Response Error Reserved Invalid Word Received Word Count High Word Count Low Incorrect RT Address Sync Error Non Contiguous Data RT2RT Message Error Concurrent Monitor Option Description Message transfer completed Bus on which the message was transferred 1 BUS A Set to 0 Message Error bit bit 10 in the RT Status word was set A bit other than the Message Error bit in the RT Status word was set The Error bit is not set in conjunction with this bit 1553 message level
97. ts BC RT BC Concurrent RT and BM modes with Concurrent Monitor option in RT and BC RT modes Four Channel MIL STD 1553 interface board for PCI systems Supports BC RT BC Concurrent RT and BM modes with extended temperature option 40 C 85 C Single Channel MIL STD 1553 interface board for PCI systems Supports BC RT BC Concurrent RT and BM modes with MIL STD 1760 option page 10 1 Chapter 11 Appendices 11 Appendices Chapter 11 contains appendices describing the Military Standard 1553B word Military Standard message formats and internal and external loop back tests The following topics are included page 11 P page 11 b page page EXC 1553PCI Px User s Manual page 11 1 Chapter 11 Appendices Appendix A MIL STD 1553B Word Formats sluofelnfolelelrfelsfelolel fol Bits 15 14 13 12 11 10 7 5 4 3 2 1 rm Li fels alsle rfefofwlnfele nfs nll Times 1 2 3 4 5 7 10 11 12 13 14 15 16 17 18 19 20 Command Word Sync RT Address TR SubAddress Mode Word Count Mode Code P Data Word 16 1 Sync lt Data gt P Status Word Sync RT Address Reserved P Message Error Instrumentation Service Request Broadcast Command Received Busy Subsystem Flag Dynamic Bus Control Acceptance Terminal Flag Figure 11 1 MIL STD 1553B Word Formats NOTE T R Transmit Receive P Parity page 11 2 Excalibur Systems Chapter 11 Appendices Appendix B MIL STD 1553B
98. ue 0000000000000000 H Size 64 bits 2 3 17 Interrupt Line Register INTLN Address 3C H Power up value OBH Size 8 bits The Interrupt Line register indicates the interrupt routing for the PCI Controller The value of this register is system architecture specific For x86 based PCs the values in this register correspond with the established interrupt numbers associated with the dual 8259 controllers used in those machines the values of 0 to F H correspond with the IRQ numbers 0 through 15 and the values from 10 H to FE H are reserved The value of 255 signifies either unknown or no connection for the system interrupt page 2 8 Excalibur Systems Chapter 2 2 3 18 2 3 19 2 3 20 PCI Architecture Interrupt Pin Register INTPIN Address 3D H Power up value 01H Size 8 bits Set to INTA Minimum Grant Register MINGNT Address Oe ED Power up value 00H Size 8 bits The Minimum Grant register is not implemented on the EXC 1553PCI Px Maximum Latency Register MAXLAT Address 3F H Power up value 00H Size 8 bits The Maximum Latency register is not implemented on the EXC 1553PCI Px EXC 1553PCI Px User s Manual page 2 9 Chapter 2 2 3 21 page 2 10 PCI Architecture Interrupt Status Register Address 40 H Power up value 00000000 H Size 32 bits Attribute Read only During an interrupt the Interrupt Status Register indicates which 1553 channels are interrupting Th
99. uired for each coupler which services a single bus e g BUS A see Figure f 2 For more information about couplers see our website www mil 1553 com To other 1553 device 1553 Device Transformer Coupled EXC 1553PCI Px Transformer Coupled s A s B s C Terminator Terminator Three Stub Coupler 78 Ohm 78 Ohm Figure 1 2 Transformer Coupled Connection One Bus Shown Excalibur Systems Chapter 2 2 1 PCI Architecture PCI Architecture Chapter 2 describes the PCI architecture The following topics are covered page PCI Configuration Space Header page 2 B PCI Configuration Registers page 2 B Memory Structure The EXC 1553PCI Px requests five memory blocks the first memory block is 256 bytes in size and contains a memory mapping of the PCI Configuration Space Header region The remaining four memory blocks are 32Kb each in size and contain dual port RAM for the 1553 channels For more detail on the memory block allocations see Registers page The EXC 1553PCI Px does not use any I O space EXC 1553PCI Px User s Manual page 2 1 Chapter 2 PCI Architecture 2 2 PCI Configuration Space Header The EXC 1553PCI Px includes a PCI Configuration Space Header as required by the PCI specification The registers contained in this header enable software to set up the Plug and Play operation of the board and set aside system resources
100. ution Register Address 3FF7 H The 8 bit value in the Time Tag Resolution register represents the resolution of the Time Tag Counter in units of 4 usec To determine the Time Tag Counter s Resolution use the following equation Time Tag Resolution register value 1 x 4 usec A value of 0 corresponds to a resolution of 4 microseconds a value of 1 corresponds to a resolution of 8 microseconds etc The user must set the Time Tag Resolution register before issuing a Start command to the board To modify the Time Tag Resolution register issue a Stop command modify the register and then issue a Start command see Start Register page 4 18 Excalibur Systems Chapter 4 Remote Terminal Operation 4 13 14 RT Response Time Register a ee The RT Response Time register sets the Response Time of the Remote Terminal The resolution of the Response Time register is 155 nsec per bit measured as the dead time on the 1553 bus The minimum time is approximately 4 usec which is achieved by writing a 0 to this register Any value above zero will result in a Response Time equal to 4 usec plus the contents of the register x 155 nsec The actual response time has a tolerance of 1 usec Set the Response Time register before issuing a Start command to the board To modify the Response Time register issue a Stop command modify the register and then issue a Start command see page t 18 UUO LIE Last Command Data Word
101. ween 3300 H to 33F6 H Excalibur Systems Chapter 4 4 13 17 4 13 18 4 13 19 Remote Terminal Operation Status Response Register Address 3FEF H The Status Response register is used to control the Status Response mode of operation After a Receive message the user can respond with a 1553 Status word even if an invalid 1553 Data word was received A 1553 environment can be selected which will affect some 1553 RT Status word bits see _L553 RT Status Words page 4 7 Set the Status Response register before issuing a Start command to the board To modify the Status Response register issue a Stop command modify the register and then issue a Start command see Start Register page 4 8 Bit Description 02 07 0 01 Environment 0 1553B 1 Non 1553B 00 On Error 0 Suppress Status 1 Send Status Status Response Register Address 3E84 H READ ONLY Board Options Register The Board Options Register is a 16 bit register in which the low 8 bits are reserved This register identifies the type of on board firmware Bit Description 10 15 Reserved 09 1 1760 08 1 1553 00 07 Reserved Board Options Register Firmware Revision Register Address 3E80 H The Firmware Revision register indicates the revision level of the on board firmware The value 0001 0010 would be read as revision level 1 2 EXC 1553PCI Px User s Manual page 4 21 Chapter 4 4 13 20 4 13 21 page 4 22 Rem

EXC-1553PCI/Px User's Manual: Rev B

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