PCI - AER Adapter board User Manual
Contents
1. 12 Figure 12 LED layout on External BOSA patatas ori Oi Raros 13 Figure 13 Bit description of STATUS REGISTER AT 16 Figure 14 Bit description of CONFIGUARTION REGISTER Al ii 18 Figure 15 Bit description of CONFIGUARTION REGISTER BI 19 Figure 16 Bit description of CONFIGUARTION REGISTER Cl iii 20 Figure 1 7 Release register Of EEN 21 Figure 18 Bit description of CONFIGUARTION REGISTER A7 23 Figure 19 Release register of PPGA2 Ee Bee 24 Figure 20 Multi sender AER transaction Specification i 25 Figure 21 Multi sender AER Time Specification corno ncnonn naciones 25 Figure 22 AER transaction Specific rias 27 Figure 23 Top view of AER connector used on external board 28 Figure 24 Top view of AER standard converter 29 10 11 04 PCI AER Adapter board 17 15 USER MANUAL Warning Be careful that PCI BUS of PC have 3 3V power supply line The PCI AER use 3 3 Volt for Xilinx FPGA and don t have voltage regulator inside Connection cable between PCI AER and External Board is fragile Be careful when manipulate it The PCI AER board is an ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 volts which readily accumulate on the human body and on test equipment can discharge without detection Therefore proper ESD precautions are recommended to avoid any loss of functionality 10 11 042. IN and AER OUT addresses thus allowing for example the definition of a connection matrix between neurons on different chips Senders and Receivers On the basis of the input LABEL placed on AER bus as input to the Mapper it possible to send a spike in output for one or many neurons of the receiver chip The MAPPER can operate in three modes 1 Pass thru mode the AER IN address is simply replicated on the AER OUT 2 One to one mode the AER IN address is used as a pointer into a look up table and the retrieved content will be the target address on the AER OUT 3 One to many mode the AER IN address must generate multiple events to be dispatched to different targets this is achieved by a sequence of look up table addressing a readings Since the time each event takes to be put on the bus is shorter than the spike typical time width usual not too large sequences of output events generated by a single AER IN event are to be considered as essentially simultaneous from the point of view of the recipient chips PCI AER ADAPTER BOARD NO tege FPGA 1 Cable Buffer lt Seq Ack A Seq Req gt MONITOR SEQUENCER PCI to Local Bus 32 H Interface AMCC 55920 PCI Bus MAPPER IN Local Bus 2M Word Figure 7 Mapper blocks highlighted 10 11 04 AER PCI adapter board 17 15
3. Layout of PCI AER board From Sender Chips Cable Driver 68 Pin Cable connector Sequencer Connector To Receiver Chips Status LED External Power Supply Figure 11 Layout of Adapter Cable board External board At the moment the Sequencer connector is not used 17 15 AMCC EEPROM configuration 10 11 04 AER PCI adapter board 17 15 External Board Led description The external board have five LED three yellow and four red Near 68 pin connector there is Power ON LED After there are FIFO Full alert LED The yellow LED are used to indicate status of primary block of PCI AER Board Monitor Mapper and Sequencer If LED is lighted associate block is active Power ON Mapper FIFO Full Monitor FIFO Full Sequencer FIFO Full Monitor enabled Mapper enabled Sequencer enabled Yellow LED Figure 12 LED layout on External Board 10 11 04 AER PCI adapter board 17 15 PCI Configuration Space for PCI AER Adapter Board At present the PCI SIG PCI Special Interest Group has not assigned the IDs necessary for the identification of the PCI AER board Therefore for the moment we use the numbers provided by AMCC VENDOR ID Value 10E8h PCI Offset 00h 01h DEVICE ID Value 5920h PCI Offset 02h 03h Base Address Register and Memory Region The PCI AER board uses 4 different memory location All the registers of the board are located in the memory space no resources are located i
4. Offset 00h Read only Bit 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XXXXXXXXXXXXXXX Not Used Z MonFE Not Used MonFH Not Used MonFF MapStsFFInt SeqFE SeqStsFHInt SeqFH SeqStsFEInt SeqFF MonStsFFInt MapFE MonStsFHInt MapFF Figure 13 Bit description of STATUS REGISTER Al On the MAPPER FIFO we don t have FH because the MAPPER FIFO is filled and flushed automatically by MAPPER IN and MAPPER OUT state machine From software is only possible to reset this FIFO For more information about behaviour of FIFOs flags signals refer to IDT7205 FIFO data sheet 10 11 04 AER PCI adapter board 17 15 MON HF Int MonStsFHInt bit is high when a FIFO HALF FULL interrupt is generated by the Monitor The FIFO HALF FULL interrupt is generated when MONITOR FIFO becomes half full This interrupt is useful to handle emptying of FIFO by the data block and not word by word MON FF Int MonStsFFInt bit is high when an FIFO FULL interrupt is generated by the Monitor The FIFO FULL interrupt indicates a probably error condition because when MONITOR FIFO is full further incoming spikes are lost SEQ FE Int SeqStsFEInt bit is high when an FIFO EMPTY interrupt is generated by the Sequencer The SEQUENCER FIFO EMPTY interrupt is generated when SEQUENCER FIFO becomes empty This is a probably error condition because the data flow from sequencer can
5. The MAPPER includes four blocks distributed on both FPGA Figure 7 Mapper In FIFO Mapper Out MMU and SRAM MAPPER IN Handles the flux of spikes at the ARBITER output of the sender chips and forward them to the MAPPER FIFO The MAPPER IN generates an ACK signal to reply to a REQ signal from the ARBITER and complete an AER transaction thus allowing to emulate the presence of a receiver chip this is useful if one wants to test a sender chip in the absence of a receiver chip FIFO Is used in the modes one to one and one to many and it is needed for the second one If a one to many mapping between the AER IN and AER OUT addresses the MAPPER in fact must then sequentially scan the axon look up table and generate an AER transaction at each step at the risk of missing an incoming event were it not for the FIFO In this architecture the Sender BUS is completely decoupled from the Receiver BUS If the event flux from the MAPPER in causes the saturation of the FIFO an error flag arises for the MAPPER in registers MAPPER OUT Takes the spike address from the FIFO and performs the sequence of steps needed to generate the appropriate AER OUT events In one to one mode it manages the address from the FIFO as a pointer to a look up table word containing the address of a receiving neuron in one to many mode the address from the FIFO is the start pointer for the look up table scan stopped when the MAPPER out
6. be discontinued SEQ HF Int SeqStsFHInt bit is high when an FIFO HALF FULL interrupt is generated by the Sequencer The SEQUENCER FIFO HALF FULL interrupt is generated when the number of the words on FIFO becomes less than one half of the total memory of the device This is useful to maintain constant data flow from SEQUENCER MAP FF Int MapStsFFInt bit is high when an FIFO FULL interrupt is generated by the Mapper The FIFO FULL interrupt is generated when MAPPER FIFO become full This is probably an error condition because it indicates that the data flow from MAPPER IN to MAPPER OUT has stopped with consequent spike loss The interrupt flags can be cleared through a write operation at Status Register AI address The value written at this address will be used as a MASK to select which Interrupt Flags to clear The value is not stored If a bit bit 8 to bit 12 in the written value is 1 and the corresponding Interrupt Flag is active the flag will be cleared otherwise the flags do not change Configuration Register Al EnMON Enable Monitor starts the MONITOR This read write bit starts or stops the AER transaction acquisition If 1 the MONITOR is stopped MonChSel 3 0 masks the input channels of the Monitor For each channel it is possible to enable or disable the AER transactions management If the bit of a channel is 0 the transactions for that channel are managed by the Monitor and stored in the FIFO if 1 the Monitor ignores that c
7. generate a relative time delay expressed in AER clock cycles or else an absolute time delay on the basis of the TIME counter value word format in Figure 5 The transactions generated by the SEQUENCER can be presented on one of the channel thus implementing the mentioned emulation of a virtual AER chip possibly coexisting with real chips 17 16 15 0 Comando Dato Figure 5 Sequencer FIFO word format The flux of the FIFO is one way the input comes from the PCI BUS and the SEQUENCER block on FPGA1 decodes the data on FIFO and producing and AER transaction or a delay according to the commands in Table 4 The FIFO is asynchronous Cypress or IDT with a maximum storage of 64Kx9Bit In Figure 6 there is a typical sequence of commands with the format inside the FIFO The HOST manages the data formatting and any error Bit 171615 0 di 26FE amp Generate spike with LABEL 26FE Hex 01 F433 Generate spike with LABEL F433 Hex 10 0020 la Wait 32 cycle of AER CLOCK before continue o1 3344 ke Generate spike with LABEL 3344 Hex DI AD22 kg Generate spike with LABEL AD22 Hex E 0001 Wait for TIME equal to 00010000 befor continue 2 Word kx 0000 75E2 d Generate spike with LABEL 75E2 Hex Figure 6 Example of commands in the Sequencer FIFO 10 11 04 AER PCI adapter board 17 15 MAPPER The MAPPER implements the mapping between AER
8. too The two most significant bits of the output address determine the channel hosting the new AER transaction given the AER DEMUX configuration see Table 13 10 11 04 AER PCI adapter board 17 15 Description of the Cable Adapter board blocks The Cable Adapter board decouples electrically the system under test from the PCI AER board and the cable This solution assures the integrity of the signals also with long cables The power supply can be 5V or 3 3V The External Board can be powered directly from PCI AER board 5Volt or through external power supply The External Board have a voltage regulator inside The different power supply source is provided for neuromorphic chips with different power supply EXTERNAL BOARD Seq Ack KE Sequencer Seq Req p Connector LABEL 16 gt Se ender y lt t 9 Sender 2 co A Connector 4xREQ e 37 pu Ei Sender 3 DI Ke Connector CH _4xACK lt gt 2 OS Sender 4 an p Connector e E E 2 LABEL 16 uz P Receiverl Connector a 0 19 Receiver 2 3 O Connector Ki 4x REQ SW p Receiver 3 Connector 4x ACK LS Receiver 4 lt Connector Figure 9 Blocks of Cable Adapter board 10 11 04 AER PCI adapter board PCI AER system Board Layout Sequencer FIFO Monitor FIFO Mapper FIFO Cable driver XNNIX 5S 6766N 0d Tu LOPD 68 Pin Cable DINO Connector i Ed AI TALA FPGA EPROM Configuration AMCC s5920 PCI Interface Figure 10
9. used CfgMapperOut 0 Not used CfgMapperOut 1 Not used AEROutCfg 0 Not used AEROutCfg 1 Not used MapperOutEN Not used KwAdAER Not used Not used Not used Not used Figure 19 CONFIGUARTION REGISTER A2 bit description AEROutCfg 1 0 AER Out Configuration FPGA2 are the read write bits that set the output configuration for the receiver chip All the configurations are in Table 13 10 11 04 AER PCI adapter board 17 15 AEROutCfg 1 0 Addr Bit Handshake oo Disabled Not Used Receiver Chips 2 Receiver Chips 4 Receiver Chips Table 13 AER OUT Configurations MapperEn if 0 Mapper OUT take spike from FIFO Mapper and generate AER transaction un Output stage of PCI AER board KwAdAER selects the output configuration of the PCI AER board Is possible to choose if use Point to Point implementation of AER or Multi Sender AER implementation If bit is 1 output will be set to use Point to Point AER otherwise Multi Sender AER is used Release Register FPGA2 This register stores the release of the FPGA2 firmware and is read only Its value is fixed at hardware level The information is stored in the lower 16 bits of registers the less significant 8 bits store the Revision number and the other bits store the Version number The higher 16 bit are irrelevant Release Register FPGA2 16 15 14 1
10. 0 and if MAPPER Out goes through recovery state start flashing LED If 1 no special action EnAntiMeta if 0 the incoming spike will not synchronized if 1 the incoming spikes pass thru a double level synchronization block 10 11 04 AER PCI adapter board 17 15 Release Register FPGA1 This register stores the release of the FPGA1 firmware and is read only Its value is fixed at hardware level The information is stored in the lower 16 bits of registers the less significant 8 bits store the Revision number and the other bits store the Version number The higher 16 bit are irrelevant Memory space Release Register FPGA1 Base Address BA1 Offset 20h Read only 31 XXXXXXXXXXXXXXX After Reset yxXXXXXXXXXXXXX Version Figure 17 FPGAI release register 10 11 04 AER PCI adapter board 17 15 FPGA2 register set Status Register A2 MMU Busy Memory Manager Unit Busy FPGA 2 It s read only bits This bit is active low and is 1 only when the MAPPER OUT is disabled and State machine of MAPPER OUT is on idle status This means that MAPPER OUT have completed last access to the SRAM after having been disabled In all others cases is 0 Remember the SRAM is accessible by PCI only when the MAPPER OUT is disabled and have finished his last access Therefore before to write or to read the SRAM is needed to check this bit to be sure of the s
11. 3 12 11 10 9 8 7 6 5 4 3 2 1 0 XXXXXXXXXXXXXXX After Reset yxxXXXXXXXXXXXX Version Figure 20 FPGA2 release register 10 11 04 AER PCI adapter board 17 15 Appendix A AER specification Multi sender implementation of AER Figure 21 Multi sender AER transaction Specification The Sender Chip begin transaction and assert Req Active low signal The Receiver chip assert Ack signal This mean that Sender Chip can put address of spiking neuron on the bus 3 The Sender Chip put address on the bus 4 The Sender Chip drive address bus while Ack signal is active low When Receiver Chip is ready set Ack signal and free Sender Chip 5 The Sender Chip free Address bus and new transaction can begin Ne pa Wy ESS peal I WES Req Ack AER Address Time PAUMBOONI De Figure 22 Multi sender AER Time Specification 10 11 04 AER PCI adapter board 17 15 PAUMBOO bes On Table 14 and Figure 22 we can see typical time for AER transaction T1 Latency time of Receiver has T2 _ Ack fall to Req rise delay 0__ 175 ns D AckWidth 225 ns T4 _ Ack Rise to Req fall delay JO ns T5 Ack Rise to Ack fall delay 100 nS T6 Label valid from Ack fall O 75 ns T7 BusHEZ from Ackrise Io 100 jas Table 14 AER Transaction timing 10 11 04
12. AER PCI adapter board 17 15 Overview Figure 1 illustrates the main components of the system The system includes two boards the PCI AER Board is the PCI interface placed in the host computer and the Cable Adapter Board is an external board connected via a flat cable 68 pin to the PCI AER board and directly connected to the AER bus This configuration simplifies the placing and the interfacing of the system to test allowing a friendly management of the connections The board in the host includes all the working components of the system PCI AER and the buffers driving the internal communication by local buses The external board manages the signal transmission from the chips to the cable connecting the Cable Adapter Board to the PCI AER board It includes 9 AER connectors for chips connection The PCI AER board has four main components The ARBITER implements arbitration of events coming from different up to four sender chips The MONITOR allows to tap the transactions on the AER bus to attach time information to them and to forward the joint information to a PC via PCI Its available modes of operation allow acquiring every event from the AER bus or selecting events associated with a chosen subpopulation of neurons on the chips The MAPPER essentially implements the connectivity pattern between up to four sender chips and up to four receiver chips The SEQUENCER can be connected directly to the AER bus to emulate a neural chi
13. AER PCI adapter board 17 15 Point to point implementation of AER This implementation of AER use only one sender and one receiver chip at the time IAO WO fje Req Ack Address Figure 23 AER transaction Specification Sender chip put valid address of spiking neuron on the bus Sender chip set REQ signal Receiver recognize REQ signal form sender and set ACK signal Sender chip free the BUS and reset REQ signal Receiver terminate AER transaction and reset ACK signal a E fg 10 11 04 AER PCI adapter board 17 15 Appendix B PCI AER board standard pin connection On the Table 15 and Figure 24 we can see pin number and short description of AER connector used on external board 6 AES _ AER address BIT 5 signal 8 _ AE7 AER address BIT 7 signal 9 LAPS _ AER address BIT 8 signal Table 15 AER Connector pin description Figure 24 Top view of AER connector used on external board 10 11 04 AER PCI adapter board 17 15 Appendix C PCI AER Accessories AER standard converter The PCI AER Board accept in input Multi Sender AER implementation only Therefore this small PCB is needed to connect Point to Point AER chip to the PCI AER board The AER Adapter can be configured both Multi Sender to Point to Point and viceversa through few PCB jumper At the moment we use AER Adapter only to transform Point to Point devices on Multi Sender devices The Adapter need 5V
14. ENEE a Oo 10 Description of the Cable Adapter board block 11 PCI AER system Board Layout iii A ii A a iia 12 External Board Led descripta e le ia da andes 13 PCI CONFIGURATION SPACE FOR PCI AER ADAPTER BOARD 14 Base Address Register and Memory Region 14 Base Address U S 3020 REO cradle alinea 14 Base Address 1 Registers of PCI AER Dorada aa 15 Base Address 2 Access to the FIFOn ecra kanna a a cirie 15 Base Address 3 Access to MAPPER SRAM occccnncccnnnnniccnnnnnonocnnonnnocnnnnnaconnnnnnrrcnnonnrcccnonaniccnnnns 15 REGISTER ARCHITECTURE OF PCI AER BOARD cccccccseececeeeceeeeeeeeuseeseeeeenseeseaes 16 ERGA TESIS di A as 16 Status Register AW a LO ee Ea 16 Configuration Register a a 17 Configuration Register Bl ai O eekleg 19 Configuration Register Cl a a da cs 20 Release Register FPGA EE 21 A O a lineare 22 APLIKA A eege gebeten ee 22 Configuration Register AZ A ela allea 23 10 11 04 AER PCI adapter board 17 15 Release Register EE 24 APPENDICA ee 25 AER Ee ee 25 Multi sender implementation of AER cccsssccccssssnccccesssnccecessenccecessenaessessencescessanacesessenaeess 25 Point to point implementation of AER curricolari 27 APPENDIX IB ocur 28 PCI AER board standard pin CopnnectHon cnn no nn ncnnaness 28 APPENDIX Cossio ria 29 Ne EE 29 AER Staidard CON VE iii A SEENEN 29 10 11 04 AER PCI adapter board 17 15 Table Index Table 1 Allow
15. PCI AER Adapter board User Manual Dante V Istituto Superiore di Sanita Rome Italy 2002 2003 Rel 1 1 5 November 2004 FPGA 1 rel 4202 FPGA2 rel 4203 Release history Release 1 0 of this document refers to implementation Beta 1 of both FPGA Therefore the release register for FPGA1 has value 4201h and release register for FPGA1 has value 4201H Release 1 1 of this document was updated during my visit at INI and refer to the solution of some bugs signalled on the Adrian Issue doc document Some corrections on FPGA2 s State Machine has been necessary The new value for FPGA Release register are 4201 for FPGA1 and 4203 for FPGA2 IN Release doc document are reported the modification bring to the PCI AER board and FPGA configuration For Software change see the Adrian M Whatley Software and Drivers documentation 10 11 04 AER PCI adapter board 17 15 Release SO ilaele I Table Index A A GER EAE IV Fioute A a a aa IV WARNING a cscs enc cee EE 1 ORKE DTA TAN ssi ct E A E A TE AAE 2 Description of the main PCI AER board blocks 3 A see A A niro MATL ene ele rio ANS 4 PIERCE OC EEN 4 TIME COUDE ai A Gb allen rale iii ia 4 ARBITER uta i nt hee 4 MONTO Rita la rina a nni poli donne dale lil ilo ade cd a i 5 ANA elisa ili 6 IVIAIPPE RGA coches teksts ta icon ate ek Mest tales ets tie een ENER 8 MAPPER IN EE 9 A ii ie ni 9 MAPPERSOUT arca da lar cata had EE 9 MMU and SRAM architecture ieri 9 AER DEMUX lt o da es
16. XXXXXXXXX 1 o Not Used a DS EnInt_HF Mon SMDEbug EnInt_FF Mon EnAntiMeta EnInt_EF_SEQ Not Used EnInt_HF_SEQ Not Used EnInt_FF MAP Not Used Not Used Not Used Not Used Not Used Not Used After Reset XXXXC01Fh 1 1 E o E Figure 16 CONFIGUARTION REGISTER C1 bit description MonFHInt if 0 enables the generation of the interrupt when the FIFO of the Monitor is half full This feature is implemented to communicate to the driver that the Monitor FIFO becomes half full MonFFInt if 0 enables the generation of the interrupt when the FIFO of the Monitor is full This state can generate an error condition because we can loose data SeqHFInt if 0 enables the generation of the interrupt when the FIFO of the Sequencer is half empty This feature is implemented to communicate to the driver and or the software that it s possible to transfer new data to the FIFO at least half FIFO SeqEFInt if 0 enables the generation of the interrupt when the FIFO of the Sequencer is empty This information can be managed by the driver as an error condition or as the availability of the FIFO for new data MapFFInt if 0 enables the generation of the interrupt when the FIFO of the Mapper is full This information must be managed by the driver as an error condition because in this case the further incoming spikes are lost SMDebug If
17. e PCI PCI AER ADAPTER BOARD u E pe Seg Ack Seq Req gt 64Kx18bit Up to Async FIFO SEQUENCER PCI to Local Bus Interface AMCC S5920 nie Input 7 MUX di Local Bus PGI Bus lt Label 16 Cable to External Board Figure 4 Sequencer blocks highlighted The SEQUENCER on current version of the board can t be used without ARBITER and MAPPER In all cases the spike must pass through the ARBITER and MAPPER The SEQUENCER connector on EXTERNAL board is not used So the spikes can out from the board only through the RECEIVER connectors 1 4 The SEQUENCER is handled exactly like a chip So you must take an input channel to use SEQUENCER Practically you can use only 3 chips when SEQUENCER is active If SEQUENCER is inactive all channels are available for chips 10 11 04 AER PCI adapter board 17 15 The data structure of the FIFO and the SEQUENCER commands are illustrated in Table 4 Bitl7 16 Bit 15 0 End of sequence 00____ Reserved AER cycle Event address label Delay AER CLOCK cycle Wait TIME 11 TIME for resuming execution 2 words in sequence Table 4 Allowed SEQUENCER commands The SEQUENCER checks the FIFO state and if the latter is not empty reads its content Then depending on the two most significant bits it can either generate a transaction on the AER bus a spike or it can
18. ecause AER clock drives the TIME Counter the maximum duration of a measurement depend on which AER clock is selected See Table 1 AER Clock Approximate duration 1 hour 10 minutes 11 hours 55 minutes 59 hours 39 minutes 100us 119 hours 18 minutes Table 1 Maximum duration of measurement ARBITER The PCI AER board can simultaneously manage up to four chips In the worst case four chips will therefore compete for the bus and the ARBITER will be in charge of handling the arbitration of the accesses in compliance with the Multi sender AER standard see appendix A The ARBITER can operate in three configurations In the first only one sender chip is assumed with the associated 16 bit address The second configuration can handle two sender chips with a 15 bit address each so that each chip can address 32768 neurons The third configuration allows for four chips with a 14 bit address each 16384 addressable neurons In the second and the third case the ARBITER uses the two most significant bits to signal which AER channel one of the available connectors carried the spike Label width N Sender Chips 1 Sender Chips Table 2 Allowed ARBITER configurations 10 11 04 AER PCI adapter board 17 15 MONITOR The MONITOR taps any AER transaction on the ARBITER output It takes the TIME value when the transaction is detected and stores the time label and the address in the FIFO Each event is stored in the FIFO as three succe
19. ed ARBITER CONAN tee ain cde coda eege 4 Table 2 Word identification in the MONITOR FIFO i 5 Table 3 Allowed SEQUENCER commands ia 7 Table 4 Pointer Table commands on one to many mode 9 Table S Board Ee EEN 14 Table 6 Registesr list of S5920 Base Address LN avian dis on Gab tari teh id 14 Table 7 Registers list of the PCI AER board Base Address 1 15 Table 8 Configurations for the input channel of the Sequencer 18 Table 9 Configurations of the CLOCK AER Treguencn 19 Table 10 Configurations for the ARBITER as S SEENEN 19 Table 11 Mapper Out configuration xs asilo EE 23 Table 12 Configurations for AER Ollas ds A ia cs 24 Table 13 AER Transaction E EE 26 Table 14 AER Connector pin description etd ee ees 28 Figure Index Figure 1 Illustration of the PCI AER system architecture to test neuromorphic chip by AER bus 2 Figure 2 Blocks scheme of the PCI AER Dodd natal 3 Figure 3 Monitor and Arbiter highlighted AA 5 Fig re 4 Sequencer le EE 6 Figure 3 SEQUENCER FIFO word dom is 7 Figure 6 sequence of commands in the Sequencer FIFO ssecsessssessesasernscesssncvesnneeerscerenaters 7 Figure 7 Block diagram of MAPRE Rain aa aaa 8 Figure 8 SRAM architectures 2 ri ERE 10 Figure 9 Blocks of Cable Adapter board si sce e dee Eed Ree 11 Figure 10 Layoutot PCI AER De e 12 Figure 11 Layout of Adapter Cable board external board
20. er will send the spike information The selected transmission channel is disconnected from the external AER channels All the configurations for these bits are in Table 9 SeqChSel 1 0 Channel 0 Sequencer connected to 0 channel of the Arbiter Channel 1 Sequencer connected to 1 channel of the Arbiter Channel 2 Sequencer connected to 2 channel of the Arbiter Channel 3 Sequencer connected to 3 channel of the Arbiter Table 9 Configurations for the input channel of the Sequencer SeqFMR Sequencer FIFO Master Reset is a red write bit that resets the FIFO of the Sequencer SeqFRT Sequencer FIFO ReTrasmit is the RETRASMIT signal of the Sequencer FIFO This read write bit is for future expansion of the board it is not used in the current version and is usually fixed to 1 For a deeper explanation of the functions of this bit it is necessary to read the FIFO datasheet in the section concern the RT signal EnMapperIN Enable Mapper IN FPGA1 is a read write bit to enable the MAPPER in module if 0 then the transmission of an ACK signal to the REQ signal from the ARBITER to complete an AER transaction MapFMR Mapper FIFO Master Reset if 0 resets the Mapper FIFO 10 11 04 AER PCI adapter board 17 15 Configuration Register B1 EnTIME Enable TIME counter is a read write bit that enables disables the TIME counter If bit is 0 TIME Counter is enabled RstTIME Reset TIME counter is a read write bit that if 0 the value of
21. find an END label The look up table data structure is illustrated in and details in MMU and SRAM architecture section MMU and SRAM architecture The memory management unit handles the SRAM accesses The SRAM can be written and read from the PCI but it is usually accessed by the MAPPER OUT since it hosts the look up table The MMU manages the access conflicts and configures the data paths for each type of access Is possible access to the SRAM from PCI only if MAPPER OUT is disable see Configuration Register A2 If you try to access the SRAM when MAPPER OUT is enabled no errors are generated but in case of writing access the data are lost In reading access the data value is unpredictable The SRAM amounts to 2 MWords organized in four 512 KWords banks The first one has a 24 bit word the others have a 16 bit word see Figure 8 This architecture is needed to use the SRAM in the implementation of two different tables the Pointer Table and the Spike Table The Pointer Table takes up the first 64KW of SRAM and contains a table of 21Bit pointers addressed to a location inside the Spike Table Pointer Table Bit 23 22 Bit 20 0 Pnt Start Table 100 NotUsed Pointer to start word on the Spike Table 21 bit Not Used Direct Spike Generation Direct Spike generation only Bit 15 0 is used Table 5 Pointer Table commands on one to many mode The Pointer Table works as a look up table the AER Label coming from the worki
22. gister bits are read only MON FE MonFE bit Monitor FIFO EMPTY flag is an active low bit It is high when at least a word is in the MONITOR FIFO FIFO not empty MON FH MonFH bit Monitor FIFO HALF FULL flag is an active low bit It is set to low after half of the FIFO memory is filled and will remain set until the number of data on MONITOR FIFO is more than or equal to one half of the total memory of the device 4096 word in our case MON FF MonFF bit Monitor FIFO FULL flag is an active low bit It is low when the MONITOR FIFO is full Otherwise is high SEQ FE SeqFE bit Sequencer FIFO Empty flag is active low The bit is high when at least a word is in the SEQUENCER FIFO FIFO not empty SEQ FH SeqFH bit Sequencer FIFO Half Full flag is an active low bit It is set to low after half of the FIFO memory is filled and will remain set until the number of data on SEQUENCER FIFO is more than or equal to one half of the total memory of the device 4096 word in our case SEQ FF SeqFF bit Sequencer FIFO Full flag is an active low bit It is low when the MONITOR FIFO is full Otherwise is high MAP FF MapFF bit Mapper FIFO Full flag is an active low bit The bit will set to low when the MAPPER FIFO is full Otherwise is high MAP FE MapFE bit Mapper FIFO Empty flag is an active low bit The bit will set to low when the MAPPER FIFO is empty Otherwise is high Memory space Base Adiress PAI Status Register Al
23. hannel This feature allows to save space in the FIFO EnTIMEL bl if 0 allows to save the spike address with the relative TIME label rather that only the spike address MonFMR Monitor FIFO Master Reset resets the Monitor FIFO Usually it is 1 to disable the reset condition but if we need to reset the FIFO it must be 0 for at least 10ms MonFRT Monitor FIFO ReTrasmit is the RETRASMIT signal of the Monitor FIFO This read write bit is for future expansion of the board it is not used in the current version and is usually fixed to 1 For a deeper explanation of the functions of this bit it is necessary to read the FIFO datasheet in the section concern the RT signal 10 11 04 AER PCI adapter board 17 15 Base Address BAI Offset 04h Read Write Memory space Configuration Register A1 Bit 31 16 15 14 13 2 11 10 9 8 7 6 5 4 3 2 1 0 XXXXXXXXXXXXXXX After Reset XXXXB781h 1 0 1 1 0 1 11 1 0 0 0 0 0 0 I Not Used EnMon MapFMR En_Mon_Ch 1 EnMapIN En_Mon_Ch 2 SeqFRT En_Mon_Ch 3 SeqFMR En_Mon_Ch 4 SeqChSel 1 EN_TIMELbl SeqChSel 0 MonFMR EnSeq MonFRT Figure 14 Bit description of CONFIGUARTION REGISTER Al EnSEQ Enable Sequencer is a read write bit that enables the Sequencer function SeqChSel 1 0 Sequencer Channel Select are read write bits that select the Arbiter channel where the Sequenc
24. ister Cl FPGAI SIGG ENI DO A Not impl i s Not _ i sd Not imp raid ars iN Release Register 1 _ RO 20H Release Register of FPFGAI FPGAI o A y Noti o Not ipl _ licei iene AA Status Register A2 RO 30H_ StatusRegister A2 ________ FPGA2 _ eo dl EEA dl Release Register 2 _ RO 3CH Release Register of FPGA2____ FPGA2_ Table 8 Registers list of the PCI AER board Base Address 1 Base Address 2 Access to the FIFO Through this Base Address it is possible to access the Monitor FIFO and the Sequencer FIFO As the information flux in the FIFOs is one way the PCI accesses the Monitor FIFO only in reading mode and the Sequencer FIFO in writing mode Therefore the contemporary access to both FIFO through the same base address does not generate conflicts The maximum storage capacity of the FIFO used is 64K x 18Bit access by 32 bits words Base Address 3 Access to MAPPER SRAM Through this Base Address it is possible to access to the MAPPER SRAM The storage width is 2MW the first 512K W are 24bit and the other 1 5MW are 16 bit Only the single access is possible no burst mode accesses is allowed The SRAM access from PCI is denied if the MAPPER OUT is active See Configuration Register A2 section 10 11 04 AER PCI adapter board 17 15 Register architecture of PCI AER board FPGA1 register set Status Register Al The bit configuration of the Status Register Al is in Figure 13 The re
25. n I O space BADDR 0 128 Byte S5920 PCI Register 0 BADDR 1 128 Byte BADDR 2 Up to 64 KDW 32Bit _ FIFO Area BADDR 3 2 MDW 32Bit SRAM Area Table 6 Board Memory Space Base Address 0 S5920 Register The registers of S5920 accessible from PCI and necessary for the right configuration of the board Operation Register are located in this region of Memory space The S5920 works as Pass Thru in Active Mode for the board control Therefore we don t need to consider the registers relating to the other modalities of S5920 Add Offset Description o y O Outgoing Mailbox Register Incoming Mailbox Register PTCR___ 60h____ Pass Thru Configuration Register Used Table 7 Registers list of S5920 Base Address 0 During the test stage it is necessary a certain number of wait states for the routing ottimization of FPGAs Then it will be possible to decrease the waiting time This setting depends from FPGA family Because SRAM is 70nS we need of 2 wait states for the PCI access 10 11 04 AER PCI adapter board 17 15 Base Address 1 Registers of PCI AER board The registers from 00H to 2CH are 16 bits and from 30H to 3CH are 24 bits In Table 8 there is the list of the PCI AER board register po _ Offset Description Implemented on Status Register AI RO Jun Status Register AL FPGAI Configuration Reg BI RW 08H Configuration Register BI FPGAI Configuration Reg Cl RW OCH Configuration Reg
26. ng AER entry is a pointer to a first word of an Spike Table location containing an other table of AER Labels 10 11 04 AER PCI adapter board 17 15 representing the addresses of the receiving neurones The look up table scan ends when the END LABEL is reached Because the END LABEL is represented by the value FFFF Hex the maximum number of receiver neurons is 2 1 In one to many mode is also possible generate directly a spike without scan Spike Table Using direct spike generation save time in terms of clock cycle Is enough set the two higher bit of Pointer Table to 11 see Table 5 SRAM Pointer and Spike Table 2Mword Pointer Table word structure Comm bit Pointer Address 0000008 E 00 Pointer 010000H Bit 23 22 Bit 20 0 AER LABEL IN 00 Pointer 010100H 16 00 Pointer 0D0A02H Pointer Table 11 AER Label xx0022H Word width 24Bit i O Only First 64KW 00 Pointer 010C02H OOFFFFH 00 Pointer 1C0000H 010000H d AER Label l AER Label END rF 010100H d AER Label AER Label Spike Table 4 i S Word width 16Bit i y AER Label END crrru 010C02H ODOA02H 1C0000H Free SRAM location 1FFFFFH Free SRAM location Figure 8 Mapper SRAM architecture AER DEMUX It is the ARBITER counterpart on the output side It can be configured in such a way to handle 1 to 4 receiver chips
27. olt power supply Standard AER Connector Not Used 5Volt for Devices GND 5Volt Standard AER Connector 5Volt for Devices Not Used Pinl Figure 25 Top view of AER standard converter Input and output connectors are conform to the PCI AER standard connector See Appendix B 10 11 04 AER PCI adapter board References MindShare Inc Tom Shaley Don Anderson PCI System Architecture Addison Wesley Publishing Company 1995 ISBN 0 201 40993 3 PCI PRODUCTS DATA BOOK Applied Micro Circuits Corporation 6290 Sequence Drive San Diego CA 92121 4358 http www amcc com The Linux driver for the Rome PCI AER board Adrian M Whatley Institute of Neuroinformatics University amp ETH Zurich 17 15
28. p i e allowing the communication of a pre determined flux of spikes from a simulation to subpopulations of neurons on the chips to code the structure of external stimuli PCI AER board Chip 0 or Sender Chips Sequencer Ki es DN D D D D D D D D Bi D he D D D Label Req Ack Receiver Chips Figure 1 Illustration of the PCI AER system architecture to test neuromorphic chip by AER bus 10 11 04 AER PCI adapter board 17 15 Description of the main PCI AER board blocks Figure 2 illustrates the logic plan of the PCI AER board for the interface with AER bus The highlighted parts contain the blocks in each one of the two FPGA XILINX Figure 2 Blocks scheme of the PCI AER board 10 11 04 AER PCI adapter board 17 15 Block description AER CLOCK The AER CLOCK provides timing for all events on the AER bus it provides a time base for the time label attached by the MONITOR to each spike the SEQUENCER uses it to establish the time sequence of events put on the AER bus The CLOCK period can be configured to assume one of the values 1 10 50 100us TIME Counter Time is a 32 bit counter which once started provides the absolute time elapsed since a reference start time for each transaction on the AER bus The 32 bit label is attached to each spike tapped by the MONITOR and is stored in the FIFO along with the address The SEQUENCER uses TIME to implement delays between spikes B
29. ssive words The FIFO word is 18 bits the two highest bits state the type of the information stored in the other 16 bits The data structure is illustrated in Table 3 the address is 16 bits and the time label is 32 bits because it is compound by the TIME high and the TIME low word This structure allows in particular to recover from any loss of synchrony in a FIFO reading operation Bitl7 16 Bit 15 0 AER Address 00 Event address label TIME HI TIME high TH TIME LO TIME low TL Control Error Error or Control code Table 3 Word identification in the MONITOR FIFO PCI AER ADAPTER BOARD Stau VE FRGA i AER Clock TIME 32 Bit Counter 64Kx18bit MONITOR Up to Async FIFO Seq Ack Seq Req pi p PCI to Local Bus f 3 5 Interface Y AMCC 5920 Label 16 O t gt MAPPER IN e 20 4 x Req rine 2 20 KE El eS O II Ge FRGA 2 S Lobel l 15 Si 3 3 L 4 x Ack Figure 3 Monitor and Arbiter blocks highlighted 10 11 04 AER PCI adapter board 17 15 SEQUENCER It allows the software generation of AER transactions thereby allowing for example the emulation of a virtuall AER compliant chip communicating with real chips The SEQUENCER module highlighted in figure includes a FIFO the SEQUENCER block that reads the FIFO and executes the commands and an interface with the system to test The FIFO decouples the Sequencer block from th
30. the TIME counter is forced to 0 emory space ase Address BA1 ffset 08h Read Write Configuration Register B1 Bit 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XXXXXXXXXXXXXXX ECKE KAS EA rh ck After Reset xxxXXXXXXXXXXXX Not Used Not Used Not Used Not Used Not Used EnTIME RstTIME AERCIKCfg 0 AERCIKCfg 1 ArbCfg 0 Not Used ArbCfg 1 En Map _Ch 4 En Map _Ch 1 En Map ChO KK Le En Map ChO Figure 15 Bit description of CONFIGUARTION REGISTER BI AERCIKCfg 1 0 AER Clock Configuration are a read write bits that select the CLOCK frequency used in the AER management as illustrated in Table 10 AERCIkCfg 1 0 Clock Period us E 100uS Table 10 AER CLOCK frequency configurations ARBCFG 1 0 Arbiter Configuration are read write bits to set the operation mode of the Arbiter All the configurations are in Table 11 ARBCFG 1 0 Label width N Reg N Ack 00 Disabled Not Used 1 Sender Chips 2 Sender Chips 4 Sender Chips Table 11 ARBITER Configurations En Map _Ch 4 1 mask the input channels of the Mapper If a bit is 0 the corresponding channel is managed by the Mapper otherwise it is ignored 10 11 04 AER PCI adapter board 17 15 Configuration Register C1 Memory space Configuration Register C1 Base Address BA1 Offset 0Ch Read Write 16 15 14 13 12 11 10 XXXXXX
31. uccess of operation emory space ase Address BAL Status Register A2 ffset 30h Read only 23 22 21 20 19 18 17 16 Come SR Not used Not used Not used Not used Not used Not used Not used Not used Bit 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 o o Jo o o o o o o Jo fo fo fo Not used MMU Busy Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Figure 18 Statur REGISTER A2 bit description 10 11 04 AER PCI adapter board 17 15 Configuration Register A2 CfgMapperOut 1 0 Configuration Mapper OUT FPGA 2 are read write bits to configure the del MapperOut mode See Table 12 Geier 0 Gi sed The incoming Spike address is put directly on output without change r fs The incoming spike address is converted and put on the output I One to many Mode Send incoming spike to many different neuron address on the output Table 12 MAPPER OUT configurations emory space ase Address BAI ffset 34h Read Write Configuration Register A2 23 22 21 20 19 18 17 16 Come plete Tafel Not used Not used Not used Not used Not used Not used Not used Not used Bit 45 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o o Jo o o o o o o i o ifo i Not
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