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Lexicon 960L & Larc2 Service Manual Covers

Contents

1. L z v 8 9 8 5 8 9 68 22 00 2 62551090 20 9 3900 66 00 WO3 Na OLO3NNOO SNA Ol 8820 HW G8 WHOS ad NARRA NunISZ lt E dnSAzi 0 10 VW su 3406 L 0902 783 EES 4 p HT on EES 50867 TSInWIW 50901 E Ps pem sem HT PT T NU NUNISE aS 12525 E ON i BY AU SEE XTW a JG Sn8Ol 57801 LL ON CATIONS ON 39007 50801 78 14007 50801 SEGGV 50
2. 5 2 t v S 9 4 8 8 61 652 Wd asngsi eere a 60661 090 a 8 asa azis 66 27 1 s XN HME 57 844 06 10 WW ON 5 511192 YOLOANNOO XIN y 6 306 6 308 f y I 6 309 1307 or 6 306 QN 4 6302 ane or 6 301 HENIN NOISIASH ESSRON 133HS Be 55 oven DEVI vig 908 a 400718 1081400 LNAWNOOA ON 1918 ane veer am OI 56 IE 905 99 Wad Agus VSL vas lar w 9918 ON ras gt O Va gt 1908 lt Sd lt gt 90 5 WCW 918 TET WT lt zi gt 2085 1806 EH ON 918 ON 505 YSL odis 8 paa Sw Y os lt 501 V3O oy NYSE YS Hue a gt E
3. 5 2 9 8 1 6850 3AYN 314 S 9 B oper 3000 azis 6650 NOLOSNNOO OI 5 50 1096 08 S3v W3HOS AMO 519 08847 06 10 WW U 0 91 gauvdsv V AZ 8 ENSA TINT 51801 FEA TE 152551 11452 1XIZEZSU NIE Lan e 57155 5414 S3uvdsv EMESA NU 1801 Nis E CEEI SR 750 50801 75 SEEM SNOL s 50801 INI SO 524 Ls ONTO ON am 00989 50801 84009 50801 vey AG SIN 50801 18049 51801 98001 50801 SHY 50801 SG 51801 g 51801 50801 75 NOV 51801 Snaor 23007 S 8O THOOY 50801 mav 50801 ame 1800990 TOV 50801 50801 TN 880 50801 23190 57801 VIVO 51801 50801 51801 EIS viva 5180 78 51801 SNEON
4. 8 2 r 9 4 8 9 1938 92691 6618 ansa WYN a jz 69221090 a 1 8199 108102 340930 mes xi Ene 66 08 1096 WHOS STVAOUddY Sls 06 10 WW 30 ar uooixe eoe ang 10 28 dWvs 2N OE 2218 1 mapa 12192 E A SNe Iva dNVS 0290 37459 INL gc VO anys eL 9 Z LIO 490 22 Ed om Wren VSN IXINL Bs 630 490 8 NIE Rov dsa Ong 957 NIS MS zu LHS OPH iav d 490 6 I ddA H Of 30 959 ze LA Quay esa 33343189 1 1 1008 460 1 9 bH 4n per 9291 toic sane XO XI So dnm 5 22107957 450 sJ BE o lt ON SV
5. n 5 9 4 8 6 05 GENS souci 66 8 9 ange i MO a 535 29 5 u usannn 68648 7 GOL 66215 HMU NIV W3H9S S vAOUdav 08 10 WW uoo y 19 Y nu ua od 8104 eI lt Eod 68 9 VS OZ3ld go Ven aod Leur Luv 21 T SELO T velo E I r o 3 3SN3SAZL T 5 cord 7909 i wel 1 8 19 Le dN 2115 Or 8104 mne d u sav 5792 7762 m MOILSAOL a 1 4 eo W3143ANOO QV 23 02 SSA dacezi lt BA x Lil Ww gen 4 sr sano rono f ar ZH ono eana 5 I 2 asyo Lede n eol Y 104 wee 9 sup 21 Teo uw 2104 uu oen 55 L
6. L 2 5 9 8 ISHS veevcei 66 00 Wd qanssi 8 ANNU gov 67 5 090 g 99 8 325 66626 WO3 8 SHO HO 1nd1no 662 1096 08 10 WaHOS SUADUEV 06 10 VW NWO v 1OVNINOO oF p Inna m x vivo lg ero sm L Lay 180 899 Y 1 ana 032 wal gt 5 gg onl auno tonl j uno vivos gt Ives una oos bos uno SON resi uno lon 51 rz 808 Y anc 8 69 501 evo 1 1 999 zed eo 329 Loven Y w fanov ano TSE ros aras vivqolx sarl 199 890 Nd Ll 5 ANALNO HO 5 aran romoj i 10952 E adost Se NOR oneal yz 0029 1020
7. J6 J5 24 J3 C6 FB2 3 2 07 FB1 20 5 5 5 5 75171180 5 34815 8 ZE 2 R33 N LE EGE 872 2 ees 387 EAIA 2 5 RTRS 8179 aise reer de z dez 15 xy 23 2 5 Sa sess 85 8 5 KS EEK E S Ek 5 5 62 1 ELS Jota R61JC64J C77 R33 nai 24 5 gg 5 CI M 880 x S Ws s 585966378 5 3 ej OX o 155 58886 192 57 R14 5001 ES IR13 2 RIZ 9 gE 2 5 88 5 E a o COCO Og 2 lt 5 59888 is 5 zi ii 20 2 2 33 g
8. 6 ON 4 lead xr z 08181981 2 Savas 091041 2 5 a 40 HXH 8 OBLSTVSL 99 08100 Tel 6 za 150 2 ga weansa t T zn 0 4 3JOINO SS3NIHOISG H3183ANI 0 levi 18384 opi goi lt E ANI Q97 Y canes O91 280 ___________ 57907 ze qve 40 089 sen 1SVHINOO 1 T OT Kw S E n 5019621 5 NA 0 AN arr Seo d 7 00212000 003 0 7 Ta 051 1X3 INVA QOHO AONO t W3LN ANI QOH 127 h 10 1Z2166 Z 60 00 10166 334 28 SNOISIA3NI Lexicon 9 63
9. L 2 S 9 8 5 8 s son ases U TEE Wd qanssi 2 695 090 L ne Ma 5 3000 azis 68048 AC amomo WVUS Z 09 7 68098 1 1096 08 W3HOS amc SIAOUdeY 0610 WW quoaqag u 02 ON 0 1 1 22 lo zlv va zz ezn ON D 9 Sp 222 5 39 ave 155 ENVES 8801 QN Tl MW uyay aa vil spo v NE o Z 8309 ZZ 22 eO LAN CZ e gl lL Ww 8 17201 26 Pi wp 22 isa VEOLOLAD een lt EL ZIN 087 QNO 1 i pisuz t eae 8010 _ bvd ANI Ne ZINZ 2 4 Daysha SINOV ZZ 72 5 2 2 NEAL 22 O 1 7 01409 22 86 8 MZ 88060200 Er 22 8 2070 42 880025 22 Ton 0 S tale VIVO 02 xoroz 22 E EVIVO ZZ ron CALLE 77 5 VIVO 22 ae HOV ZZ sont BENE 22 E 6 04190 22 z7 62
10. 2 S 9 L D 6689 Nd 68661 080 8 a a N38ADN aqoo 325 amp ZOUYT 3313W N3HOS zu STVAOUddY 06 10 VW auodq38 Uuooixe o89 za w t 9 20 A say 50 19 2 OH A TA 9 089 ai Ee eza R 039 98 L 0 zza eia sia 8408 os T 219 Y H NN oz 4 I I Hor a RTT MES ON n TZ yO 3380 SYOLYNOISIO 18916 mE Ww GNNOYD y GNNOYD yy 001 xavod sew T v Er We P 0 SUOLIOVdYO CALVOIONI 88811116 xum 83018 538 ISIMYIHLO Z T Gi oly nwo r N hi TA BA A ON r N 80 sq za en Gas E ki 8198 Gg I oia 10 va ra GP 2109 ajo 810 32 1
11. 2 B 9 5 8 e 9 me 66 001 Nd conss UH SWNT MO i esccioo 8 28 ag 3000 azis 66 90 SuaJ4ng OSIN 66 801 HMM 1096 88 S3v W3H9S PM avc STWAOuddY OELLO VN 00519 Vd u ON 199 PA dp K sn 4 8 5 9 AS YCOHAVL sn uy p 5 X190 74 8n 2 VSL E a coy xi 5 INOC NSFVEOHAYL in EMO A 52 NH og 9 se 9 wH wH w oa SO SONE SOR SON lo zly va 50801 E du 10 400 9 47 8001 51801 5180 50801 ON ON AS PYCOHAPL ww dir oii Li v 00 066 DOH 20 3 2 5 9 9 37
12. Figure 1 1 LARC2 Block Diagram 56 TXD2 Channel 2 USB IrDA Not Used UDC RXD 2 not used Channel 1 RXD 1 1 53 y Channel 3 RS422 RS232 Host Debug LD 7 0 TXDC Channel 4 LCD 4 640 x 240 lt 7 RXD C M not used SA 1100 CPU 10 PCMCIA 2 Inverter optional Address 25 0 23 5 Data 31 0 m Buffers PCMCIA 1 8 MB FLASH on board EN 11 8 MByt Boot FLASH 52 DRAM FPGA Keyboard ee Meter Bridge 12 Keypad Backlight 8 8 10 Bit A D 10 Bit A D Keypad 8 Touch Controls 8 Wipers Ext In 2 VDC 5 3 3 Motor Drivers JoyStick 5 VDC Supply 42V In XIII 7 39 960L Multi Channel Digital Effects System Service Manual Central Processor sheet 1 The system central processor is a highly integrated microprocessor that incorporates a 32 bit StrongARM RISC processor core system support logic multiple communication channels an LCD controller PCMCIA controller and general purpose ports Processor Summary 08 sheet 1 The SA 1100 Microprocessor is a general purpose 32 bit RISC microprocessor with the following features 16 Kbyte instruction cache 8 Kbyte write back dat
13. L 2 r 5 9 2 8 N 01 199 Nd Gans 8 seo 4 e eros 2 a 325 66 626 W93 ZHO LNALNO 68 200 7096 8 1nov Oud 06210 VN 0051 d v 51 1388 weg lt Wars 4 1ndlno T er dN330 170 91 n x ze MOI oor ovg lt ros LEE be LI VINOS zza ras 2 7395 mo ors 4301 HENIN 6961 0908 2 0018 101109 lt rog zas EEN BAY uy 8 TED 20 9020 GSN SHOLVNOISSC 1391 2 GSTWISNILON HLIM SIN3NOdOO 9 aeo 133HS S310N30 KXXX s ONnOuO avnoso IE amoa T 85880280 soww wien 6 38v SHO1IOVdVO 3SIW 3H1O 563180 AN 38V 540151534 O3LVOIONI SSIINN Z MOW SYOLSIS3Y GALVOIONI SSTINN L S310N PA Tiss ove r
14. 5 L 4 v 9 9 4 8 5 8 66 8 9 qanssi 3 61661 090 NS MO 20 azis 6668 1 7101409 ZONV1 8823 ZONV1 O8 NIV WHOS ava STVAOUddY 08210 YW u 02 gt 1OVS1NOO levi ev ms P a 10d 55 TSE SS NINT 12d bom a Lr 3 ay MADin zv v 02 Qd 74 099 19d 6d9 Fes EB lovi NOTINOO va DR NI 33S 79d levi EE ra Viva 254 NNO 110254 57 1135 ev vs NO 110 031150 41 ATNO 83111404 38 OL SI 198 v vs 2 SILON zY vs sid vs advs OOS vs 80 45 1d vs 9d vs mete Vodi 907915 LOL id YS a NE ND JUNI OX 8 Teeiv carz oond 201 19 0008 avos 1 310N 335 na 00 208000 093 3d 198 008 RSS ni NOS 14884 103NNOOSIQ v ara ur OODLE 29 Qe 0 V 0012000 003 pesin kes is
15. 2 v S 9 4 y 20 1536 E 66 20 62661090 20 38WAN 3909 325 6620 NO3 ayo 68 0001 wg S3OV3S31NI 310 34 1096 G8 X79 W3HOS sul 08 10 VW quoJda3a uoorxe AVO uoonx ON 08151404 66Av8 m 6 26254 5 ond Jor cin 18397 1 OBIS WSL lt pir EET 1 z au vor 6 gnsa 30v sin f 16 284 2 09 307 Y y 301 54 HANAN NOSAN ZNAN 13388 5 es ansnzi 6ZEE1 090 2400 18 TOYLNOO 4001 z sea 1 xv 08151981 a s 9 aieiai 5 Wy bvm gt jor TM Za say L 10 SIN ZEY 20 254 E 1 193 8184 010 190 03801 SHOLVNOIS3Q 15719 133HS SALONI DONO S E ONnONO A QNDONO ZZ T 9550 T vua y w SUOLIOVEVO O31VOIONI 8831 0 TINO lt leol AOE ee 2 2 ead 9 580151534 O31VOIONI 3SIMMSHIO SSIINN 2 pin ay 154 509 1no MOWI 3501953 SSITNN 1 H S310N M
16. 2 r 5 9 4 8 8 1301 V 866881 6567 Wd 314 66661090 g us 3000 696 W93 aoa ZHO HO QV 9 7096 08 NIV N3HOS stvaouddy Nr 06 10 VW NYO uooixe sis l ries v RM m T 1 1 519 say 19001 810 7199 Nue yero LLL D 5 ET 6H ou 8 L 20 xcov 2 2 307 we akay sas s ide z 1 02 n 1301 SANAN NOSARE TENAN 1338 oes 9651 0904 400718 1 eos sss AGO gr 158 on amp zn nu sr 9z g3 SHOLVNOIS3C 18811 HIM CSV SIN3NOdIOO 9 DON Tuo193sniaaWnN 133Hs sa10N30 XXX s uiv MT 2 52 aNnouo ANNOYS TIOS ype 866 0 F DOWNY RU v m 1 p p SHOLIOVEYO O3 YOIONI 88318116 level SOT oT En 9 8 BEV 58015634 21 3SIWa3H1O 86211012 m 3019 53 031 88318011 NOMS
17. 5 1 z 8 1 309 13865 97 8 9 1 8 48059 e WYN SUS cou alt 6 1 090 8 9 99 3 x3ewnN saoo 656 WO3 axis 3NY Ova 66 617 1096 08 NIV W3H9S gt HMM aui 380 np 08210 WW quoAqag NYO uoonx ON 0 LOVYINOO 25 ON TENZA ON 2 UVES 169 Tn TV 5080 ley s 3 ON 1221 puse 0EV CA 18126054 ONT 52 ON 805 FERS ON zl AZ ON 725 XVn ON nz TSV 51601 o a N XL OW 150 80801 979 soso 807 766 ise GERM SGOT 55 50801 ON LL s mm TENGE ON 5 7095180 2 ON 88101 57801 Yr E 25 29005 8 Saday SHEL 50901 220 9300 SEO 50801 93099 sngor E I Te 58801 12 5280 200 50801 2901051801 NTO lors 50401 18009 50801 0 1400 sngo 0800 51801 eaey saoi 027 Ag 1vivd 51801 5180 uir SVivd Sngol ouo 51801 9 Snagi VIVO 51801 2171 51801 NEE Vnd 5001 0 4 1 0 50801 E EES Si 3 1 L 80815 INL Siv 11055 ON Yi 20838
18. 2 r 5 9 4 8 8 i 66 8 9 Wrd ea 61551090 8 gt 8 3goo azis 8888 H9 5031 6626 NI zu 1 NIV WIHOS 39 STWAOUddY 06 10 VW 8 uoorxe NNI L 19 031 o T L 1 099 x 0 09 09 Os or qz do 8 leviz ewro vore MOSS Fn ear 9 2945 0748 amp x x a MOS lt 8648 2645 leds 0645 eae 2088 745 NE NT Ne SJ SJ SJ e lt a core THORS TEY du Ss elds Ns Ns OS lt 10422166 YOO 2 2048 1048 0045 99510166 X00 G3ONVHO ES een NOLLehiOSad SNOISA3N
19. 2401 133 5 V N 66 2 11 9305 IIIS LON 00 2 080 g seu 20 0350 ASSY DON Agu ON 325 66 62 6 HSN za OAM 66 6 11 wirt V OSH 1450 OMG ASSY swwoudcv o BI E 581 9 9 Shean 310301 213 1 138 0 2 031412355 35 3 10 SS3 TNn 4 2 JO Z IHS SH 1450 OMG ASSY 27271 080 4 30 IHS OSH 11450 ASSY 0 1 080 4 011319534 8 000 319018 10 1 09 00 6 8 00 8 8 NO NMOHS SY 91 13 5 9 LSM 518 304 2 133HS 335 71 00 82 1 00 02 00 62 2 8N 00 91 2 V Wad SALON 00 61 000 003 3d 6 aov 00 1660009 023 040 504 1234402 00 112000 003 N3d 0 f SNOISIASY 5914 581 9 v 1 133 5 335 5014 2 935 001 qva NMOHS SV 021 30 53903 OL L33Sv9 021 30 30V4 1 4 OL 51 41415 3AIS3HQV 431 30 53903 E 5914 81 300301
20. L 2 v S 9 2 8 1 13388 Wd _ qanssi 8 anwan 656100 g pa 3000 azis 6667 W93 SHO LNANI 8884 HMH 1096 08 NIV W3HOS aia STVAOUddY 08210 WW 00019 ird MYO ON L AOVYLNOO A 8 1 sen JA suy gwr 1 by e M MAN s 2113 PS 6v9 001 108 ve 69 9n kod 58 anga 3 713534 ANOS or 28 onl EUR kad i pron NND legis a sas xcu Ed e P 5 vivos F 945 Sav EI m PA sav INOOA leors 1 0831 8r a 080 T MES 2 950 Tape suma fr juss gj oz a 68683 sur su 9 983 3 184 89 VA9 m 1 ui 30 900 810 900 OLIY verg 6914 90M yy or SHO 192 ven z T 3 p w 0899 g 660 gig Y a Ne Wo3 0082 005 2 10 12000 093 0300Y 2 00977 SONVIVE 5 333308 LNANI P In 00
21. 2 9 8 8 1 30 13995 2 Wd canes 9 seo erro g 99 8 x38WnN scoo 329 68606 W93 f HOSHO ANY 8 via 66121 1 081 WHOS ir oNov asa 06 10 vW 59074 Posl v NON yeu gr EEI anh ai 5 gr 804 vivo 4 sul Lamy 53 983 955 nano 1 gren 1 i 10832 3408 ados ay 4 ondaj 2 ww 4 arp uno ST lt Wars 3802 90 any x 7 nuno bas Atle f yi ura DDT ovg lt 708 gr uno S 4 09 2 9 esglay vas g any any 080 508 seo 1 1 90 9183 31 eas Y Trois varv vere van VAS P 9n Hk ea WLT ros Seu LS as 310 hg a lt 9 artes 4 280 552 Y ANdLNO 5 1 genu w z oz maiz an EL gt w os 8084 gr uno Ez lt 09 uno vivas ras l uno ON lt uno
22. EBI En gu 8 RK 185 13 181 Ried P2 BOTTOM SIDE CO gt gt cm 1 rad Cac ua QO caa 25 aco ao SHEET 2 OF 2 SCALE N A Lexicon REV 5 SHEET 1 OF 2 PC BD MAIN LARC2 COMPONENT LAYOUT SCALE N A Ouro er for mm m Ls ems RESET s gt 229 13 914 vin gt z a TY on A a Eg
23. M L HEX 5 5 VALUE B BINARY CONVERSION B C0000000 1100 0000 0000 0000 0000 0000 0000 0000 C0000004 1100 0000 0000 0000 0000 0000 0000 0100 C0000008 1100 0000 0000 0000 0000 0000 0000 1000 C0000010 1100 0000 0000 0000 0000 0000 0001 0000 C0000020 1100 0000 0000 0000 0000 0000 0010 0000 C0000040 1100 0000 0000 0000 0000 0000 0100 0000 C0000080 1100 0000 0000 0000 0000 0000 1000 0000 C0000100 1100 0000 0000 0000 0000 0001 0000 0000 C0000200 1100 0000 0000 0000 0000 0010 0000 0000 C0000400 1100 0000 0000 0000 0000 0100 0000 0000 C0000800 1100 0000 0000 0000 0000 1000 0000 0000 C0001000 1100 0000 0000 0000 0001 0000 0000 0000 C0002000 1100 0000 0000 0000 0010 0000 0000 0000 C0004000 1100 0000 0000 0000 0100 0000 0000 0000 C0008000 1100 0000 0000 0000 1000 0000 0000 0000 C0010000 1100 0000 0000 0001 0000 0000 0000 0000 C0020000 1100 0000 0000 0010 0000 0000 0000 0000 C0040000 1100 0000 0000 0100 0000 0000 0000 0000 C0080000 1100 0000 0000 1000 0000 0000 0000 0000 C0100000 1100 0000 0001 0000 0000 0000 0000 0000 C0200000 1100 0000 0010 0000 0000 0000 0000 0000 C0400000 1100 0000 0100 0000 0000 0000 0000 0000 C0800000 1100 0000 1000 0000 0000 0000 0000 0000 C1000000 1100 0001 0000 0000 0000 0000 0000 0000 C2000000 1100 0010 0000 0000 0000 0000 0000 0000 When a DRAM Address Bus failure is encountered the test will stop an
24. Lexicon CIE 1395 398 66 2 11 Wd ONIMVY 3W3S LON 00 NOLVONddY 071 080 g eun 9 0350 ASSV DGN ON WOS 325 66 62 6 EN ZOWVI OAM 66 91 6 vvu V OSH 1450 OMG ASSY swAoUddv ips OE SUL STIONV SAID 20 2 091 SIHONI SHY g 640 1 200 6091 6060 5 408 303553915 LON 5300 AINO 3ON3333439 UOJ SI NILSN YSEWAN 1 SALON 0 6 8 M 00 61 000 093 Yad 00 6 8 00 82 4 EN Y oo 1 co00 093 q 00 8 8 00 92 2 NV 1 6 3 00 1 00 82 2 00 1120004 093 Yad 00 1 6 oo 1i z C ao 2s sisva 29 40530 5 5 2 313 61 134 Qvov 03112345 3SIWi3HIO 5531 01 91 2 1 7 91 1 XONddv 2 11 021 371979 Q 5214 334 4 SN31 9 021 N33ML38 L HOV 8 9 4245 02 lt 71 02 81 OL 37890 SFL 620 XMS 915 180 AVO4 86101 02 L 091 LMS 572 1 024 91 L 390148 YILIN ATAO 172 1 lt 0 CL L 001 SNIT 0891 6012 yl L VH3OOAM 001 13
25. L v S 9 8 Y 306 13395 EEL 86720 93051 3M 6677001 621 090 8 99 38WAN azis 69720 W93 68 70 01 06 10 VW Y04038 MYO u o9 ON 1999 193 quis f w suy N gl 5 gen pos 68 oT se ia y o BG I L ESO um EOF 1 Wires Ed 250 20 4 Na y S 14 seuva 000971 PA 1 6 seuva en Y o lt Eod ites 1843 Ie saa f mn ovo on sC 60 920 6 en ET PA VAS 2 say Leur in ON 101 89 en 9018 s en ON 8 6 en s lt S3uvds esu Wed wos 00 466 9 L Hinv OH Lexicon
26. 9 2 9 1 S 8 26062 eerie Wrd o3ngs 1 69215090 g S 29 000 azis 66 0 8 Ar SNEIXaT 66 01 8 096 G8 A WHOS TEE 06 10 VW U O0 ON Y LOVEINOD PA PA cvs 0532 9 sos aaa Eve aaro EYSH eH 55109 5101 51801 Dom IHSN DO XNL 9V TIN Oq gt BSH Suv N YN g OHSS 010838 n yOu XIN 9035 LXINL 20535 1XINL 0835 PINL TESST SEY O48 ETE EY 80538 XINL 37 SOESS AL 60839 ON Lev HOYAS 031 00835 OAL L s 10835 BESET 807 2359259 lt 19891 Zev 20435 1 N 90 50855 Sev 10838 0081 5 90335 ON zg Sn ev 6 8 02 5180 IIVO SNEOI Lig Sho SnEOI 918 VIVO 50801 sig 57801 81801 INGOV 51801 51801 0 18001 SSO N SAGO pen 10850801 1 16050801 SABOL 2 SMSO 51 SV x N ON ON Ev bas m i
27. 2 S 9 1 8 3 6 406 1558 655 66 8 9 ANY mo 21 61551560 Sol 8 aay 3909 azis 666 5 1 9 asio3uo 8490 SSVdA8 ATddnS cecus yd 2 W3HOS 39 S WAOUddV T 06 10 WW P cri SIT u ON V 2 carl saj 660 21 sul wl sal wl SOT HOT T adi NO steal 1 21 9 zano f w orn I I I I sen Sev SV SZIV Sav sav ON eno 201 oT POT il oe 2 983 sa4 al al al al alts al zl suy E WOT LE HoT on ala 20 w 983 SvAS 9 Eee 4 19 08100 9 H 62 Suv mw a E ON W Pho n y t ZOT 107 HIP 647 sq t s ar WLLENT TD 684 asses F 10 10122166 2 quee 00510166 CHONYHO SNOISIA3Y 2 S 9 4 8 Lexicon
28. 66 6 01 66 8 01 H9 E rud 10800168 SNOISIA3H L 2 2 5 9 65 Your Notes Lexicon 140 133HS VIN 31 25 s 10497 IN3NOdNOO 1096 188 08 24 UOS IX 1 vir sa or 6r er 17 8183 28 18 1 eu 5 sir Jz m 3 294 25 198 1 281 19 t T zov 1 2 1 18 810 812 or bid 8 198 1g zov 19v 1 E B 4 BB 8 Oo O 28458 198 29 88 19 29495 198 5 298 E 198 19 9 67 130 T 133 5 Y N 31 25 1 1N3NOdNOO 11096 148 0 1 Q8 2d Took of 240 140 91 s1 er lor 6 17 or ov
29. N N N N ON N Lexicon REFERENCE C4 8 13 17 2O C6 10 15 19 22 C1 C2 3 5 7 9 11 12 14 C16 18 21 23 R19 22 25 R2 4 27 30 R5 R1 16 R26 28 29 31 32 R6 14 15 R13 R10 R18 20 21 23 24 R17 7 9 11 R12 C13 16 C8 20 C22 23 C26 C9 12 14 17 C48 51 C35 C41 44 C10 11 15 18 C1 7 19 21 24 25 C27 34 36 40 45 47 C49 50 FB13 16 FB3 4 FB1 2 5 12 FB14 15 17 18 L1 D2 8 D9 10 03 4 05 6 8 3 960L Multi Channel Digital Effects System Service Manual PART NO 340 11573 340 12111 345 12038 350 14373 375 12110 390 12978 390 12979 430 10419 440 13906 500 05855 510 03550 510 08634 510 09790 DESCRIPTION QTY ICSM LIN NJM4580 DUALOPAMP SOP 1 ICSM LIN MC12148 VCO LPWR SOIC 1 ICSM INTER 75ALS180 DR RC SOIC 3 ICSM CPLD 960L I O CLK V1 10 ICSM OPTO ISOL HCPL0601 SOIC CRYSTAL OSC 22 5792MHz 10PPM CRYSTAL OSC 24 576MHz 10PPM LEDSM INNER LENS RED FUSESM 75A RESETTABLE 18X 13 CONN EURO C ROW a b c MALE RA CONN DSUB 9FC PCRA 4 40THD INS CONN BNC 1FC MB PCRA GLD CONN DIN 5FC 2180DEG PCRA OO OO N PS IN O AND AND A S 510 12326 CONN BNC PCRA SELF TERM 75 527 12974 CONN DSUB JSCKT 4 40 187X 25 620 12915 LUG SOLDER 52IDX 7OD FL 25TAB 641 09699 SCRW TAP AB 2X5 16 PNH PH ZN 643 04942 NUT 1 2 28 HEX BRASS NI 644 04943 WSHR INT STAR 1 2 702 13973 PANEL I O CLK 960L AIN BD ASSY 960L 202 09794 RESSM RO 0 OHM 0805 10 202 09873 RESSM RO 5 1 10W 10
30. J 8513 44 10302 100 or 9 SO _ OCTET gp j8Y 09882 111005 70 2 oq 7 gold SUN THSH HET w NI 3102 anne a 182 hisa 902 zz PX31 2 NZ jane a 592 85 N 202166 8903442 W ENTM NAE zz W 10822 99 2 eee Pel 088 gt YS TANG 031 08845 px lt gt ALSS 18 02407 JA 022 ord NW 0845 712302 5 08 levi gt 59337 INIGS 2801 BNI9S2S3 1035 BOl ZN 338 PALOL OA 80 6 dWOGV DIS 07808 A dE 82018211 170 5 92 __ 00996409109 ne 10181114 011008 011005 W 88 Tid Eos 157 NE ming OMOSAS 100 MIN NYH NI ZXOWNI 1 ON no oW OWN T disi na HE N SSA mas onside Gan Tid THO P 199 TIVI pA 984 ITIN svox 5
31. OIL sngor 9 aasa SAS iod LY DIO XINL solu H 08 T zT eWay uod T 2 60M aW DICES XAL gp n TL EXT Qv cv 33 ur 297 L cix ww LEW Sey TRI Ler Sev Sev 40835 yey ESA 80438 L E E lev LEY Oey er ier 10839 Ea 80 gr Low ZONAS ZXIN1 SV Ea vov 7033 ZXINL SCV 90435 ZXINL t ra e 00 02 57801 fou Evva 50801 2 Biv VIVO Sn8O p gt 1 1 0 2 sw 14009 50801 YIN sngor t Liv 508012 oiv OW 18009 5080 5200 6v 6V Ot_SN8OI 508022 car Es Ly TSV 80801 E EJ 9v 538 45 Y vv T gauvdsv awa v zv w n sas wm ba Y 1 Y 10 06216 300 CHONVHO 00 0Z0166 00210166 00 822066 1 3 223 L 2 5 9 4 Lexicon 9 11
32. QN Hinv UMIIHI 53 1 2 6 r S 9 1 Lexicon 2 r 5 9 4 8 8 1 01 66 101 ganssi 8 SWNT a e erro g 99 usawnn azis 66 62 06 WO3 3M Od 8821 HMM 08 LNOV 28 2N 1 06 10 WW auodaaa 9 7583 283 12 QNO Waal xwawoe UOOIXO ON Tense PE 1 1 5 Bonswa 90 7 V n anor 081 ol anor L NAT 14 1 4 4 SOOT 820 HOT QNO 3svo ea ZOPNE vast sa t T 227 300014 OSI os L 0814 410014 902318 820 2018 F San yt T EE egi sia m Ed SA 88 wiem inoa NA 1noAeasvo 10 8 iid oe s 4 revs 1 19 7 4 iH su ad E asl 41 82 8A 2 i 9 al 298 208 501 2
33. puc uacua cu 9003 0000 RSRR Reset controller software reset 9003 0004 RCSR Reset controller status register 9003 0008 TUCR Reserved for test 9004 0000 GPIO level register 7 52 Lexicon 23 Meter Bridge Module The meter bridge circuitry is represented on schematic 060 13389 The module connects to the main board via J4 main board sheet 7 The meter bridge consists of 24 LEDs in a three row by eight column matrix The LEDs are divided into two groups each controlled by an 8 bit register U1 U2 sheet 1 Software writes a sequence of bit patterns to activate the groups one at a time turning on the LEDs in that group AA RD FD FD FD 703 AZ GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN MD DN IM IE 20783208 2 GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN RR 25 ING 207 202 207 202 Group B1 Group B2 Group GroupB4 GroupA1 GroupA2 GroupA3 Group 4 Figure 7 1 Meter Bridge 7 53 Chapter 8 Parts List Lexicon PART NO DESCRIPTION QTY REFERENCE CHASSIS MECHANICAL 530 02488 TIE CABLE NYL 14 X5 5 8 8 540 14303 GROMMET STRIP SER 037 GAP NYL 4 SUPPORT CENTER 600 13984 CARD GUIDE 1 16PCB 4 L 3 MTG 10 630 14304 WSHR FL 170IDX 375ODX 093 RUB 2 PWR SUP CHASSIS 630 14358 WSHR FL 6CLX1 4ODX1 16 NYL 1 STOP TO STOP SUPP 630 14514 WSHR FL 6CLX1 4ODX1 32 BLKNYL 2 FRONT PANEL 640 01711 SCRW 6 32X1
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35. 66 2 21 93155 31 25 LON 00 Nouvordav 8661 080 NO 0360 1859 DGN E on owo ON azis 8 0 1 cayo 1096 SISSvHO wo ae 1 ASSV q J OREN 314 135 939345 3SWS3HI0 SS3TNQ S81 NI 01 8 3NDYOL SY3A09 Z X 5919 S3NMO OL 110100 2 SENI 01 8 14405 Y3MOd WONJ 5318 2 0333 Sold 2 INDOL 170170 91815 I3AWONO 69 5214 SISSVHO P 1848 N33MI38 81431 P N3A00 804 133 5 NO Sz Wall 3505 5360 418405 N3MOd 318019 5333 02 9 805 583805 OLN 26 9 ISN 5214 2 581 01 8 3nbWoL SN OS 0158 OZ Wil ONY 2 405 30 3015 NO LIMO 531430 02 SIW 2 Sold 405 MMd 40 401 NOUS 583305 3AOWGM 69 no 1 20 S81 NI 01 8 3nouoL ASSY AINO T1ISIG 804 5214 9 02 5014 2 SENI 08 62 1 5014 9 62 9 DN SENI Z S ri eu N 9 5014 8 62 5 SS 22 69 QNVO 1 NO NNOD IGIN OL 8n SALON 00 1 6 00 61 6 18 00 51 6 00 8 6 ASSY ANO 03 2 00 00 1 8 no3 oo sz a 1 00 1c 8 00 41 8 ssvMQNvH OLN dns Ad 35 34 00 8 Wa 00 0 00 81 wo on z v wv 10 00 611000
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47. 28 13939 VSI are zou we 29 NO 4405 28 TIKE 0091 lt 900 600 rola zf 984 14 9210 1380 8 1 30 4 15512 E 2 00 713535 Died G3TWISNIION3BY HLM SINSNOdINOO 9 Ed lt Sy Ds berl or foa gt SGS 9105 sOo1O3Sni3gwnN 133HS saLoNaa g ar 885 ELAS YSI 6Y DNI VS w pas 214 pazi ANNOYS ONnOMO CNnOuD QNnOMD yy f oars YSI 205 51 E 00 9d raz SISSVHO 7 SOWNV WIIG v IOVI z5 HS _ wg A 12 98 5 A a NaN GALVOIONI SSIMUSHLO 888180 vaste Ed E OO gt 8 JYV 01955 GALVOIONI SSIINNZ S ES VSL x Jed MOLL 530181534 1 2 0 SSIINN Taw 606 X EDIT s 522 E Ed EV 58 zy A T Tee 32 AC Dd 880 ws Wy Dd 628 627 828 Sv pasl SEE w 1 E 159 8301 18 Ova e S ud uy bor am ES E as 20854 gt cor e
48. W9 1054409 SNEIXa1 SNOISA38 Lexicon 9 55 2 v 5 9 4 8 8 or 99 13 5 912 6065 Wd gans e 3NN 313 6961 090 5 a uaawon 375 SHOLIOVdVO SSVdA8 7096 N3HOS 81 0844 06 10 WW Uuoorxe Wud u 09 ON LOvaLLNOD Sa Sa ONY old T zo 6515 ANON Nh e TOON ATddNS YAMOd YOLVISNVYL T3A31 NA SuO1IOVdVO SSVdAg owed oe sayl swt sov L 620 HOT WFP Som mer wl L ml EN 69 9691 IT t a say L 2021 ROT T 4 Sav suy L 8484 suy 8084 8064 surb sul 189 BIT mI 29 WoT Ec sev sev L zl 5 sav L wl ml suy L 6017 907 199 027 6001 1071 L al aL EU ul SOT SOT T Tof t pd i dd Ee
49. 3415 401 v e dj 20 220 120 020 619 810 Lid 614 19 210 114 014 64 4 94 sa 9 77 2202 133 5 VIN 371925 1 A3U LNINOdWOD 2 0 1 H313N 09 Od 3015 WOLLOd 90 B FTH 9 70 rm m oz 1 in er I Lexicon Your Notes 9 79 Your Notes Lexicon gt 0 1 OL 866 1 080 ES oN MOS 1096 SISSVHO CEPR EI ASSY 3uvas 39018 1031NO9 13 0509 15 51 4 N03 133 5 33S L 0350 LON 0350 LON INYA QNVH OL INYA 93073 OL 09 OL 927 XN OL WALI 531 318 2 30 NOI1VTIVISNI ONY 00 8 6 oo ci 6 W 00 51 6 00 8 6 NY 00 15 8 00 82 8 W 00 16 8 00 5 8 1 mra 00 06 84 00 8t wo SNOISIA3H JEYO AlddNS H3MOd 804 0 335 331
50. zevi zeal 263 sr k od Ie orr SRCE 262 er iv 18 12 2 zey zesg 262 Lexicon 130 1 133 5 1 IN3NOdWO2 1096 12 0 ar 16 52 PS1 R30 C17 783 oe er O 8231 R21 220 ead FS 64FS 128 5 25675 RIS is 9 69 cri REV SHEET 1 OF1 con 960L LAYOUT SCALE J9 J8
51. Card One Spare IO Card slot Storage Media Hard Disk 3 5 Floppy Disk Drive CD ROM Drive Reverb Card Configurations 48K Stereo Machines Four 2in x 5out Machines Two 5in x 5out Machines Two 96K Stereo Machines Two 2in x 5out Machines One 5in x 5out Machines One Internal Hard Disk Storage Factory Programs 240 User Registers 1000 Removable 3 5 Floppy Disk Storage User Registers 100 Power Requirements 100 120 220 240 VAC 50 60Hz 300W max some mainframes will have a mains voltage selection switch if there is no selector switch it will operate on mains voltages from 100 240 VAC Connector 3 pin IEC Dimensions Rack Units 40 Size 19 0 L x 7 0 W x 17 4 483mm x 178mm x 442mm Weight 35 Ibs Regulatory Approvals FCC Class A CE EN55103 1 EN55103 2 UL UL1419 cUL C22 2 TUV EN60065 Environment Operating 10 to 40 C Storage 30 to 70 C Humidity 95 max non condensing LARC2 User Interface Display Type Passive Matrix LCD Resolution 640x240 Colors 256 Backlight Fluorescent Contrast HW controlled rear panel Brightness SW controlled LED Meter Bridge Configuration 8 channels x 3 levels Levels 60dBFS Signal Lexicon 3 3 960L Multi Channel Digital Effects System Service Manual 6dBFS 0 5dBFS Overload Control Surface Faders 8 60mm throw motorized touch sensitive Joystick Two axis Dedicated Function Keys 29 12 backlit Soft Buttons 8 Connectors 960L 9 pin
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57. S H3NMO 14 X08 320 14 ONY NOLVIN3RIO 310N LINN NO 51435 WvOJ Ind 9 312 350 LINN 30 3015 NO ONY 35345 8 3dvl 0104 9V8 LINN LINN 30 401 OL OVE W3S lV3H 39uv1 NI 9V8 TIVAS NI 1334 u3dWng 104 OVE Q30Y1d 201 NO SNL 383TWAS 3ZIS JO 33940 NI G3xOVIS 38 01 NO 031319395 SWIL Y3HLO ONY 33nivsaln KINO 808 1 2204 NO 3001 220 303543405 LON OQ ONY ANO 3ON3N3J34 03 NMOHS liva 00 8280008 003 AINO 1190 03 338 00 oo c c 00 22200 003 u3d SION 38 38 N d 1334 Oo c c 00 2 0409 03 SNOISIA3N 2 00 81 6 Mn W 00 91 6 00 8 6 NY 5310 91991 0614 OVE NI 335 0409 N3MOd Oo 06171 05 ova NI 1096 08 00 1 9 v 1334 9820 0644 Ova avo 09 90 ova INVAN 9v8 NI 335 5 3 0 2 9 5305 H109 NO AINA 30 1NOBJ 3HL 3903 3QlSNI 1HOIVMIS JHL HUM SIN3SNI 183130 5014 25671 06 A33SNI WvOJ Lexicon 2 30 13395
58. TMIX 2 port 10 to TMIX 1 port 11 through the AES card TMIX 2 port 11 to TMIX 1 port 1 through the AES card Note that the data is shifted 1 bit to the right when it passes through the AES card its loopback mode so data is reported as 2AAAAA for tests which use it Parameters CardlD This number selects which reverb card to test Legal values are 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Devices 0 TMIX 1 6 13 960L Multi Channel Digital Effects System Service Manual 1 TMIX 2 2 TMIX 3 Lexichip3 1 4 Lexichip3 2 5 Lexichip3 3 6 Lexichip3 4 Device Port Assignments TMIX 1 DevicelD 0 Interfaces with the IO backplane Typically used for inputs 0 TMIX 1 SERDO 1 TMIX 1 SERD1 2 1 SERD2 3 TMIX_1_SERD3 10 TMIX 1 SERD10 11 TMIX 1 SERD11 TMIX 2 DevicelD 1 Interfaces with the IO backplane Typically used for outputs 0 2 SERDO 1 TMIX 2 SERD1 2 2 SERD2 3 2_SERD3 4 2 SERDA 5 2_SERD5 6 2_SERD6 7 2_SERD7 8 2_SERD8 9 2_SERD9 10 2 SERD10 11 TMIX 2 SERD11 TMix 3 DevicelD 2 O LEXI 1 SER
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77. ENTER keys while powering on the LARC2 by connecting the barrel end of the external power supply cord to the connector labeled POWER on the LARC2 rear panel Release the PROGRAM ENTER keys when the chase pattern appears on the Meter Board and Keypad LED s NOTE When the PROGRAM ENTER keys are used to enter the Interactive Diagnostics the 8 RED LED will be lit to indicate that a keystuck error has occurred This is because the PROGRAM ENTER keys were being held during the Power On Diagnostic Tests This behavior is normal and is not a fault with the LARC2 Press the PROGRAM MACHINE keys simultaneously to execute the Repetitive Test NOTE During the Repetitive Test the Meter Board and Keypad LED s are lit sequentially one LED at a time The following diagnostic tests are executed in the sequence shown in the table below TEST DESCRIPTION LCD Display Eight different screens are displayed on the LCD Display Fader Motor The same test that is used during Test Interactive Diagnostics Memory Test The same test that is used during Interactive Diagnostics Diagnostics Suite This Diagnostic Suite was designed to help reduce the test time during the Manufacturing Test process by automatically executing all of the Interactive Diagnostics one test after the other in the order listed below Self Test LCD Test KEY Test LED Test Joystick Test Fader Motor Test Lexicon Te
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79. REM History 03 13 2000 Created REM REM MATT REM cd midi MidiTest rem cd Reverbcardtests rem SerialAudioTest 0 rem z80dpramtest 0 0 rem tmixHostPortTest 0 0 rem z80waittest 0 0 rem tmixdspramtest 0 0 rem cd Reverbcardtools SerialAudioTool 0 0 0 0 555555 LexichipAdfTool 0 0 0 55AAFF LexichipAdfTest 0 0 LARC2 DIAGNOSTICS There are two categories of diagnostics that exist in the LARC2 software 1 Power On Diagnostics and 2 Interactive Diagnostics The Power On Diagnostics are executed automatically when the 2 is first powered on The Interactive Diagnostics are used to perform functional tests that are not performed during the Power On Diagnostics and also for troubleshooting purposes There two ways that Interactive Diagnostics menu mode can be invoked they are as follows 1 Byinstalling a RS 422 Wraparound Plug in the HOST connector then powering on the unit 2 By pressing and holding PROGRAM ENTER keys while powering on the unit NOTE Hold the PROGRAM ENTER keys until a chase pattern appears on the LARC2 Main board Meter board LED s after approximately 8 seconds When the chase pattern appears release the 6 24 Lexicon PROGRAM ENTER keys NOTE There are two other modes that can also be entered during the Power On Diagnostics they are as follows 1 To enter the Option Board Menu mode press a
80. The functional diagnostics are used to verify the performance of the digital circuitry of the 960L The functional diagnostics test the following 1 MIDI port 2 Serial 2 Port 3 Reverb Card which includes 56301 to Dual Port Ram Z80 to Dual Port Ram Z80 to DRAM Z80 to SRAM Lexichip3 WCS Writeable Control Storage Lexichip3 ADF Audio Data File TMIX Serial Audio all the Octal Audio Data lines 6 1 960L Multi Channel Digital Effects System Service Manual 4 O Cage Cards The functional diagnostics test the hardware on the 960L that do not process audio as well as the audio processing circuitry The non audio processing sections include the MIDI clock ports and serial communication on 960L The audio processing is verified with functional diagnostics and a dry audio processing algorithm available in the normal operating mode called 8 In 8 Out Diagnostic testing is performed on the 960L prior to burn in The troubleshooting diagnostics are those tests that are available to assist a technician either in house or in another part of the world to debug a 960L to the component level 960L Diagnostic User Interface The primary user interface for the 960L diagnostics is the LARC2 The secondary user interface for the diagnostics are the LED s on the Reverb card which indicate Reverb functionality Lastly a computer monitor can be connected to the NLX motherboard video port in order to change BI
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86. 960L Multi Channel Digital Effects System Service Manual LexichipDramTest 0 1 1 Z80SramTest 0 0 Z80SramTest 0 1 z80waittest 0 0 0 z80waittest 0 0 1 z80waittest 0 1 0 z80waittest 0 1 1 TMIXHostPortTest 0 0 TMIXHostPortTest 0 1 TMIXHostPortTest 0 2 TMIXDspRamrTest 0 0 TMIXDspRamrTest 0 1 TMIXDspRamrTest 0 2 TMIXPingPongRamrTest 0 0 TMIXPingPongRamTest 0 1 TMIXPingPongRamrTest 0 2 SerialAudioTest 0 cd cd 5 lOClockBdTest 0 IOAInBdTest 0 IOAOutBdTest 0 IOAESBdTest 0 cd REM Script 2 REM REM 9601 Diagnostics Test Script REM REM COPYRIGHT C 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 2 htm REM REM Description This document is a script file that runs all available tests REM REM History 03 13 2000 rjs Created REM 05 17 2000 clc modified to run the MIDI REM and Serial Tests REM MLL REM cd Midi MidiTest cd Serial REM serialtest 1 serialtest 2 Script 3 REM 6 20 Lexicon REM MMA REM 960L Diagnostics Test Script REM REM COPYRIGHT C 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 3 htm REM REM Description This
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91. 92 95 98 101 104 105 960L Multi Channel Digital Effects System Service Manual PART NO 203 12895 240 11827 240 12136 240 13216 240 13217 240 13803 240 13913 241 09366 241 11799 245 09869 245 09875 245 09876 245 10544 245 10976 245 11625 245 12485 270 00779 270 06671 270 09799 270 12323 270 13802 270 13927 300 10509 300 10563 300 11599 300 14286 310 10422 310 10566 330 10535 330 12073 330 13905 330 13924 330 13925 330 14372 340 11045 340 11559 340 11631 340 12062 340 13806 340 13912 340 13926 340 14356 345 12038 350 13910 350 13928 350 13949 8 12 DESCRIPTION RESSM RO 1 1 10W 143 OHM CAPSM ELEC 10uF 16V 20 CAPSM ELEC 33uF 10V 20 CAPSM ELEC 22uF 16V 20 CAPSM ELEC 47uF 16V 20 CAP ELEC 560uF 35V RAD LOW ESR CAPSM ELEC 470uF 16V 20 CAPSM TANT 10uF 25V 20 CAPSM TANT A 7uF 6 3V 2096 CAPSM CER 001uF 50V Z5U 20 CAPSM CER 1uF 50V Z5U 20 CAPSM CER 01uF 50V Z5U 2096 5 220 50 5 CAPSM CER 47pF 50V COG 5 CAPSM CER 33pF 50V COG 5 CAPSM CER 1uF 25V Z5U 20 FERRITE BEAD FERRITE CHOKE 2 5 TURN FERRITESM CHIP 600 OHM 1206 FERRITESM CHIP 750 OHM 0805 INDUCTORSM 24uH 20 2 74A FERRITESM CHIP T EMI 1000pF DIODESM 1N914 SOT23 DIODESM DUAL SERIES GP SOT23 DIODESM GP 1N4002 MELF DIODESM SCHOTTKY 1A SMB TRANSISTORSM 2N4403 SOT23 TRANSISTORSM 2N4401 SOT23 ICSM DIGITAL 74AC273 SOIC ICSM DIGITAL 74ALS38 SOIC ICSM DIGITAL 74LVC16244 TSSOP IC
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93. Key Test This test is used to verify the operation of the Fader Touch circuitry for each of the 8 faders and the 45 keys on the Main Board keypad When the test is executed the 8 faders are tested first followed by the 45 keys During the test the names of the keys pressed are sent to the LCD display and also to the Debug Port 6 35 960L Multi Channel Digital Effects System Service Manual NOTE Pressing the Lexicon key will exit the test Be sure the Lexicon key is the last key pressed when testing the keys The Lexicon key can also be used to bypass the Fader Touch tests if necessary NOTE If a fader is touched when the test is executed an error message is sent to the LCD display and also to the Debug Port as shown in the example below A fader is being touched Press or Enter on debug port key to acknowledge Press key the LARC2 or press ENTER on the Debug Terminal to continue NOTE If the Key Test is exited prior to testing all of the keys an error message is sent to the LCD display and also to the Debug Port reporting the names of keys that were not pressed An example of the error message displayed when the JOYSTICK and FINE ADJ were not pressed is shown below Failure on key JOYSTICK Failure on key FINE ADJUST Press or Enter on debug port key to acknowledge Press the key on the LARC2 or press ENTER on the Debug Terminal to continue LED Test This
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98. 1 Audio Output and the distortion analyzer Apply a 997Hz sinewave 24dBu Set the distortion analyzer for a OdB reference Enable the Audio Band Pass filters on the distortion analyzer Lower the input by 60dB to 36dBu Verify the THD N at the 1 output to be 110 Repeat the test for the remaining Input Outputs 2 8 9 O gt Q N Analog In to Digital Out Dynamic Range Test 1 Connect a balanced XLR audio cable between the low distortion oscillator and the 960L 1 Audio Input Connect a balanced XLR audio cable between the 960L 1 2 AES Output and the digital distortion analyzer Apply a 997Hz sinewave 24dBu Set the distortion analyzer for a 0dB reference Lower the input by 60 dB to 36dBu Verify the THD N level at the 1 2 AES Output to be lt 110 dBFS Move the audio input cable to the 2 Input and repeat the test Repeat the test for the remaining Input Outputs pairs 3 4 5 6 and 7 8 Digital Analog Out Dynamic Range Test Note Change the Clock Source and Inputs to AES see Audio Functional Tests Setup 4 8 OONOARWN Lexicon Connect a balanced XLR audio cable between the digital function generator and the 960L 1 2 AES Input Connect a balanced XLR audio cable between the 960L 1 Audio Output and the distortion analyzer Apply 997Hz sinewave 0 1 dBFS Set the distortion analyzer for a OdB reference Enable the Audio Band Pas
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101. Executes the entire set of diagnostic tests 6 3 960L Multi Channel Digital Effects System Service Manual Script 2 Executes the MIDI Test and Serial Port 2 Test Script 3 Executes the 56310 and Z80 to the DPRAM Dual Port RAM Tests Script 4 Executes the Lexichip3 Tests Script 5 Executes the Z80 to SRAM and Z80 Wait Tests Script 6 Executes the TMIX Memory Tests Script 7 Executes the Serial Audio Tests the Octal data lines Script 8 Executes the Card Cage Tests Script 9 Executes the MIDI Test A full list of each script is included later in this chapter A LISTING of RESIDENT SCRIPTS Custom Scripts Using a text editor custom scripts can be made and run from the floppy drive In order to perform this use a computer and type the diagnostic tests to be executed using a text editor following the syntax as outlined in the test description sections Save the custom script with a file name Prior to powering on the 906L connect a PS 2 compatible keyboard into the PS 2 keyboard connection on the rear of the LARC2 Power on the 960L and enter the diagnostic mode This is performed by pressing together and holding for 2 seconds the PROGRAM and MACHINE buttons on the LARC2 immediately after powering on the 960L The LARC2 will display Requesting Menu Mode from 960L See the previous section 960L Diagnostic User Interface for more information The floppy containing the custom script can be inserted into the floppy drive of the
102. IOBP AS Control Bus AS On IOBP PWROK Power OK Pulldn ALL MUTE Panic Mute OD OC Pullup IOBP DS XCVR EN On IOBP IOBP INT Interrupt OD OC Pullup 12V From NLX Supply 5V From NLX Supply 12V From NLX Backplane GROUND From NLX Supply MIDI TX From NLX IO Panel MIDI_RX From NLX IO Panel O RS232 TX1 From NLX IO Panel RS232 TX2 From NLX IO Panel RS232 RX1 From NLX IO Panel RS232 RX2 From NLX IO Panel Table 2 1 IO Backplane Signal List Decoder U1 provide slot addressability by decoding the system control bus address signals ADDR11 9 Each slot is allocated a 512 byte address space The address map is as follows 7 6 Slot 1 top 0x000 0x1FF Slot 2 0x200 0x3FF Slot 3 0x400 0x5FF Slot 4 0x600 0x7FF Slot 5 bottom 0x800 0x9FF Table 2 1 Slot Address Map Lexicon At startup the system software polls each slot to detect the presence of an IO card When no card is present in a slot a default DATA bus value of 0xFF is provided by pullup resistors R11 R14 and R24 R28 to signify this condition Clock Terminations Passive termination networks R40 R41 R45 R38 R39 R44 R36 R37 R43 R33 R34 R42 R2 R3 R1 are used on the local clock signals IOBUS_256FS IOBUS_128FS IOBUS_64FS and IOBUS_FS to manage signal reflections and levels Currently none of these local FS related clocks are used by any IO card Sheet 2 Power Power is provided to the IO card i
103. N ONDARY Connect a balanced XLR audio cable between the low distortion oscillator and the 960L 1 Audio Input Connect a balanced XLR audio cable between the 960L 1 2 AES Output and the digital distortion analyzer Apply a 997Hz sinewave 10 94 VRMS Set the distortion analyzer to measure THD N Enable the Audio Band Pass filter on the distortion analyzer Verify the output THD N on the Analyzer is lt 94 dBFS Move the audio input cable to the 2 Input and repeat the test Repeat the test for the remaining Input Outputs pairs 3 4 5 6 and 7 8 Digital In to Analog Out THD N Test Note Change the Clock Source and Inputs to AES see Audio Functional Tests Setup 1 N Connect balanced XLR audio cable between the digital function generator and the 9601 1 2 AES Input Connect a balanced XLR audio cable between the 960L 1 Audio Output and the distortion analyzer Apply a 997Hz sinewave 1 dBFS Set the distortion analyzer to measure THD N Enable the Audio Band Pass filter on the distortion analyzer Verify the output THD N on the Analyzer is lt 94 dBFS Move the audio output cable to the 2 Output and repeat the test Repeat the test for the remaining Input Outputs pairs 3 4 5 6 and 7 8 4 7 960L Multi Channel Digital Effects System Service Manual Crosstalk Tests Analog In to Digital Out Crosstalk Test 1 Connect a balanced XLR audio cable between the low distortion oscillator and
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106. OXFFFFFF OXAAAAAA and 0x555555 tested An address test is also run that writes each address value into its associated memory location address 29 has the value 29 written into it address 30 has the value 30 written into it etc This test confirms that the 56301 can access all of the Dual Port RAM Parameters This number selects which reverb card to test Legal values are 0 1 since only two reverb cards will be supported If only one card is present use the number 0 TMixld This specifies which TMIX on the card to test Legal Values are 0 1 and 2 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running 6 12 Lexicon TMIX Ping Pong RAM Test The syntax for the TMIX Ping Pong RAM Test is TMixPingPongRamTest Cardld TMixID NumRepeats This tests a TMix s Ping Pong RAM In addition to testing the TMIX memory itself this test also checks the 56301 s ability to access the Ping Pong RAM a chip The test begins by filling the memory space under test with a specific data value then reading back the contents of each memory location confirming the data contained therein is correct Values of 0 OXFFFFFF and 0x555555 are tested address test is also run that writes each address value into its associated memory lo
107. This is useful for quickly checking the operation of the Faders and A D converters circuitry but the Fader Motor Test performs more accurate testing at higher resolution The Interactive Diagnostics menu is displayed on the LCD display after approximately 8 seconds as shown in the example below Voltage raw 00000305 mvolts 11312 BootRom diag file built Apr 11 2000 pp version z47 BootRom Version 0 13 16 08 02 For test Press or on the DeBug port enter Self Test _ PROGRAM REGISTER s LCD Test _ PROGRAM STORE o Press ENTER to change pattern Enter Key Test _ PROGRAM EDIT k LED Test _ PROGRAM CONTROL e Press to advance Press ENTER to stop Enter JoyStick Test _ PROGRAM JOYSTICE Move joystick completely around the edges TWICE Hold CONTROL to see data Press ENTER to stop Enter Fader Motor Test PROGRAM FINE ADJ f LEXICON Test _ PROGRAM LEXICON LA Memory Test _ PROGRAM MUTE ALL m Repetitive Test PROGRAM MACHINE Hold LEXICON quit Enter Diagnostics Suite d To exit _ ALL MUTE PLR 6 33 960L Multi Channel Digital Effects System Service Manual NOTE The top line of the Interactive Diagnostics menu displays the voltage test readings raw value and its conversion to millivolts line 2 displays the date
108. not slide ICs or boards over any surface Insert ICs with the proper orientation and watch for bent pins on ICs Use anti static containers for handling and transport To make a plastic laminated workbench anti static wash with a solution of Lux liquid detergent and allow to dry without rinsing s Lexicon Table of Contents 960L Multi Channel Digital Effects System Service Manual ha pter 6 Troubleshooting Lexicon 960L Multi Channel Digital Effects System Service Manual Lexicon Chapter 1 Reference Documents Required Equipment Reference Documents 960L Owner s Manual Lexicon P N 070 14353 or latest revision Software Release Notice 960L Lexicon P N 070 14354 or latest revision Required Equipment Tools The following is a minimum suggested technician s tool kit required for performing disassembly assembly and repairs Clean antistatic well lit work area e 1 1 Phillips tip screwdriver e 1 2 Phillips tip screwdriver e Small pair chain nose pliers e Solder 63 37 Tin Lead Alloy composition low residue no clean solder e Magnification glasses and lamps e SMT Soldering Desoldering bench top repair station Test Equipment The following is a minimum suggested equipment list required for performing the proof of performance and diagnostic tests Digital Multi Meter DMM e Amplifier with speakers or headphones e Cables dependent on your signa
109. the receiver is wired as an inverting stage such that when the difference between RX1 and RX1 is positive i e marking 5232 RXD1 is low in accordance with 65232 conventions With no external connection to J9 R28 and R29 bias the differential pair in the marking positive state overriding the default biasing of the receiver input The RS232 RXD1 logic level is fed directly to the COM1 RS232 line receiver on the motherboard Although the line receiver normally expects wide range bipolar RS232 levels its input threshold is essentially TTL and it operates properly when driven locally with conventional unipolar logic levels Similarly REMOTE 2 communication is based on the COM2 RS232 port on the NLX motherboard COM2 is implemented as a 10 pin header on the NLX motherboard connected by ribbon cable to IO backplane 7 CPLD Logic U2 Xilinx XC9572 sheet 2 is a Complex Programmable Logic Device which is custom programmed to perform several different functions Unlike the FPGAs on other modules the internal logic of the CPLD is permanently programmed so no configuration needs to be loaded each time power is applied The CPLD 7 8 Lexicon forms most of the interface between the I O backplane control data and clock buses and the on board clock generating circuitry Pin Name Host Interfacse 42 RESET 33 ALL_MUTE 39 CS 37 DS 35 WR RD 34 0 D7 D6 9 D5 11 D4 12 D3 13 D2 14 D1 18 D0 Clocks 28 BNC_WCLK 40
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112. 038 01 03 9 13 14 30 32 044 50 039 02 037 010 12 041 43 47 49 034 D1 8 BRKTS TO RVB BD 2EA NLX CPU TO BRKT RETAINER CLIPS TO PCB 2PLCS PLUG IN FAN CONN TO J1 J20 21 J1 2 BRACKET MTG J1 J15 J12 13 8 9 960L Multi Channel Digital Effects System Service Manual LARC2 CHASSIS MECHANICAL MAIN HSG ASSY LARC2 PART NO 120 14515 270 14401 453 14226 453 14228 530 02489 550 14035 550 14230 630 12533 640 01716 641 01715 644 06347 700 14208 700 14211 701 14447 701 14517 720 14223 740 09538 740 13573 740 14200 740 14349 DESCRIPTION ADHESIVE GLUE HOT MELT GP FERRITE FLAT CABLE 8X1 2 HW KEYPAD MAIN LARC2 KEYPAD SIDE LARC2 TIE CABLE NYL 1 X4 KNOB SLIDE TANG SATIN BLK LN KNOB JOYSTICK LARC2 WSHR FL 120IDX 250DX 062 RUB SCRW 6 32X3 8 PNH PH ZN SCRW TAP AB 6X3 8 PNH PH ZN WSHR FL 195IDX 437ODX 030THK HOUSING TOP LARC2 HOUSING BOTTOM LARC2 CLIP 78LX 28WX 26H 100 156 CLIP 78LX 28WX 29H 100 156 PAD FOOT LARC2 LABEL S N CHASSIS PRINTED LABEL MFR ID 9X 25 SILVER LABEL WARN APP PRO 5 75X 98 LABEL WINDOWS CE LARC2 JOYSTICK ASSY LARC2 200 13939 641 01703 680 14239 701 14215 720 07297 POT STICK CTLR 10K 38MM SQ SCRW TAP AB 4X1 4 PNH PH ZN CABLE 059 SCKT ST amp T 3C 3 5 L BRACKET JOYSTICK LARC2 TAPE COPPER 1 2 W DSPLY HSG ASSY LARC2 380 13931 640 01716 640 14037 641 01715 680 14235 680 14238 7700 14212 7700 14213 1701 14447 1703 14207 1703 14
113. 0x0015 BD 0x0015 Address 0x3c400000 GD 0x0016 BD 0x0016 Address 0x3c800000 GD 0x0017 BD 0x0017 6 45 960L Multi Channel Digital Effects System Service Manual This portion of the test verifies that all of the data lines on the PCMCIA Flash Memory card are functioning properly The data lines are tested by writing reading a walking 1 s pattern into the first memory location Writing 0x0001 Writing 0x0002 Writing 0x0004 Writing 0x0008 Writing 0x0010 Writing 0x0020 Writing 0x0040 Writing 0x0080 Writing 0x0100 Writing 0x0200 Writing 0x0400 Writing 0x0800 Writing 0x1000 Writing 0x2000 Writing 0x4000 Writing 0x8000 Reading 0x0001 Reading 0x0002 Reading 0x0004 Reading 0x0008 Reading 0x0010 Reading 0x0020 Reading 0x0040 Reading 0x0080 Reading 0x0100 Reading 0x0200 Reading 0x0400 Reading 0x0800 Reading 0x1000 Reading 0x2000 Reading 0x4000 Reading 0x8000 All okay Press Enter Program Flash Data Checking When the Program Flash memory is programmed during the Program App routine the data written to the Program Flash memory is verified by performing a byte by byte comparison of the data written to the Program Flash memory and the downloaded data that is currently in the DRAM memory In the event that a failure has occurred the data sent data received and failed address information is displayed as shown in the example below Ok be patient Programming block 28 0 Checking data Error GD 6e617645 B
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115. 1 YN lt 501 02 06187114 NI ZXOW NI evz no ON NL OW ON W az 90151 1148 lt 1146 2 wn OONISL Tide SINI 12 0 2 Dno ux jea ONO m i noosa Sere DE ea 5 XWav e di HN E oz S Va oi axz 9 SL pe UR H Of N 5 Wold e axi xnav H LIVI invad SE oe 6 VX vole g axo xwav o awoav 610 ve me INYA C 621703 9 Ebr KES OLIO 05100 SOY INVIO Sc L LAYO a 6102 Lc ox 9 HAVHO X Fala 67 n Nf or 8 1 sag Q SZ ERA vd vd El yl 880 wed ZL oyy ax LZ Olvd Ava 2 9L V 0 02 ZV METANET 77 OAV 0067 668201 SAL NY os 00 90266 2 68711 mx AC Ar viia iW Ed 10820166 400 G3ONVHO UDOT loiva SNOISA38 2 6 14 g 9 8
116. 102166 NOH 20 aavan SNOISIA3H L 5 9 4 8 Lexicon 5 2 9 9 4 8 1 dO v 18865 reser E 68649 Wd 090 8 ou 3009 32 88649 2 SHO HO 1 71096 NIV N3HOS n 06 10 WW AV 23 v wad 4 L 9 9283 21 1001 sin 7 ogy s T T Hk 1 185 00 M AUT 9114 NYS 340089 179 79 a 4 8H9 z 0889 Ne Y 11 leot mea ANOS 91 183 8 woe anog 6 ey legis gt SDON SC tears aE pr 8 99 DOTY Fa Te 89 wl em levis sr j vas SUR SOT 950 YWOOA 1 1 ch 2 1 ba acs 77 fana nume r joss 9 re SES Sa La 1 2 ral F 520 0183 3 3 su
117. 11575 350 13921 350 14377 355 13831 500 05855 510 11086 520 00941 641 11466 702 13976 DESCRIPTION CAPSM CER 33pF 50V COG 5 CAPSM CER 1uF 25V Z5U 20 FERRITE CHOKE 2 5 TURN FERRITESM CHIP 600 OHM 1206 FERRITESM CHIP 600 OHM 0805 DIODESM GP 1N4002 MELF QTY 8 82 2 8 16 7 ICSM LIN NJM4580 DUALOPAMP SOP 20 ICSM LIN 7805 5V REG TO263 ICSM FPGA XCS05 3 10X10 PLCC IC SPROM 960L AIN V2 ICSM ADC AKM5393 24b 96kHz SOP CONN EURO C ROW at b c MALE RA CONN XLR 3FC PCRA LATCH SMALL IC SCKT 8 PIN LO PRO TIN SCRW TAP 4X3 8 PNH PH BZ TRI PANEL I O AIN 960L AOUT BD ASSY 960L 202 09794 202 09795 202 09873 202 09899 202 09899 202 10946 203 10896 203 11697 203 11743 203 11890 203 11980 203 12370 203 12371 RESSM RO 0 OHM 0805 RESSM RO 5 1 10W 2 2K OHM RESSM RO 5 1 10W 10K OHM RESSM RO 5 1 10W 47 OHM RESSM RO 5 1 10W 47 OHM RESSM RO 5 1 10W 3 3K OHM RESSM RO 1 1 10W 1 00K OHM RESSM RO 1 1 10W 909 OHM RESSM RO 1 1 10W 100K OHM RESSM RO 1 1 10W 232 OHM RESSM THIN 1 1 10W 10 0K OHM RESSM RO 1 1 10W 280 OHM RESSM THIN 1 1 10W 2 74K OHM c gt gt O 24 16 02 17 00 02 17 00 Lexicon REFERENCE C59 60 63 64 67 68 C71 72 BC1A H BC2 8 27 9 11 12 15 16 19 20 23 24 26 34 37 38 41 42 45 46 49 XLR 42 9 PANEL R13 R20 21 46 87 152 153 R1 3 12 17 R7 11 14 R7 11 14 154 R4 6 15 16 R18 R
118. 33333333 99999999 66666666 During the test the DRAM data lines SA DO SA 031 are tested using the data patterns listed in the table below Refer to the table below for the hex to binary conversion of the data patterns M L HEX S S VALUE B BINARY CONVERSION B 00000000 0000 0000 0000 0000 0000 0000 0000 0000 6 26 FFFFFFFF 1111 1111 1111 1111 1111 1111 1111 1111 AAAAAAAA 1010 1010 1010 1010 1010 1010 1010 1010 55555555 0101 0101 0101 0101 0101 0101 0101 0101 1100 1100 1100 1100 1100 1100 1100 1100 33333333 0011 0011 0011 0011 0011 0011 0011 0011 99999999 1001 1001 1001 1001 1001 1001 1001 1001 66666666 0110 0110 0110 0110 0110 0110 0110 0110 When DRAM Data received is sent to the Debug Port Memory Test DRAM Address Bus Lexicon Bus failure is encountered the test will stop and loop continuously at the failed address location The address where the error occurred along with the data sent and the data During this operation the DRAM Address Bus is tested by first writing the current address into 25 memory locations of the DRAM using 32 bit words then the same memory locations are read to verify the data written in these locations is correct During the test DRAM address lines BMA10 BMA21 are tested using the addresses listed in the table below Refer to the table below for the hex to binary conversion of the data patterns
119. 686401 Wd EHO 001068 YOO 2 66 2 8 6618 Wd Wd 66 18 661801 CHONVHO 1 IV M NOILAIHOS3O 2 r 9 9 4 8 6 30 13385 v eeocci 68000 Wr 60261090 a ase MO 29 3000 azis 6621 H9 ME C SNR 87 888 06 10 WW u 09 ON 064 5 sayl sz 907 989916 89 Sa L 521 IP BOT ZIP GO 407 EIP Su T 1 eso I 29 1 169 Qe AA we 4L er wy I E
120. 69 4 OL 748 0 NZ SA3S Hd HNd 1 0 9 MNOS 66690 099 62 ASSVENS SISSVHO OS6 1 0S4 789 1888 1804405 4 OL NV NZ Hd v 1 1 26 9 MYDS G 9 0 0v9 ZZ 0 4 SANG 691 082 9 SISSWHO OL 43409 ZZ Hd HNd 1 06 9 25 0 70 099 03 IANG 681 051 799 7 SISSVHO OL LING 4405 9084 08 33S INYA OH 16661 08 759 9 SISSVHO OL 3lvld AlddNS Md 06661 08 799 8 SISSVHO OL 31914 55392 1 04405 305 IN SMOQNIM 1381 891 094 9 8 SISSVHO OL 405 MMd ZZ NZ Hd HNd 8 CXZe 9 MNOS 91 10 09 202 SISSVHO di JA 1381 681 092 729 ANG QNVH OL 318148 NZ Hd Hd 1XZ 9 MNOS 11 10 099 61 SISSVHO SISSVHO N S 13881 86560 0 719 T3Nvd 14043 Z 26 1 X 00 v L 129914 HSM 16 1 079 81 AWD MALS 6071 0044 709 1804405 4015 OL 4015 91 1 X GO 9 1 109914 HSM 881 079 7 1 13404405 3AVH3 901 004 66 SISSVHO 01 405 Md X318019 334 660 X GO SLE X GI OLU 14 SHSM 081 089 91 JAG QNVH 114 68661 201 786 XNYIB O I 2 661 201 7 6 3992 0 1 01 OLN Lv 804 91 1 3009 QNVO 861 009 14033 IJjNvd 6S6e1 204 796 W31N39 04405 d 9 LEO 415 I3AWONO 6069 09 JAYO Sd Z 48 6 AN IAYO 88920 06 0350 0532 NNOO M 84096 20 01 ASSY
121. 809 FINS Og Lon Od svi t Uo TEINS 854 T TAINS Dj Loll Lore lt eon Si OX Od WX Da 4 leon TANT GOI goy THINS 104 TOY Ba Ria feo e TINT BOI ee TINS Dd NAS EN Dd saw OWOSSO e anp 800 gt leon OV EDT iod TZ Dd a uon lt uon TUN Od TIN pg gt 180 1 Lor lt lt gt 80 1 80098048 gt uod xn TINT BOE ON od 4 SUY Od lt gt leon IND 8 TOV EO Tu Dd mE Lore SO lt on 2 809 OY Od xz ow sae m uon 185 seu eni eed 96H Da cU 888 7 888 164 lt 07804 Lon 867207 Y 66 27 01 Ule c 00020166 582 07 Wd 88 07 00 2 0186 2 88018 88118 Wd GILL 6880 ra inns 0982086 400 12 30 2 v S 9 1 Lexicon
122. 83494597 lewis 0 50801 Que least 0 1 1 4 5780 10 0 35 ZXINL leom LANES LXINL a DOT Wee 5000 00 902166 pz N 10620166 490 inv 20 SNOISIA38 L 2 9 4 9 53 169 0002 9 1 2 5 9 4 8 9 3054 18843 912 6966 66118 aasa 2 69551 090 d 6618 0801 120001 azs 680H9 AT e E 2 I p 8880 3OV3831NI Sn8IX31 6600 8 AMY Em x 109608 SAU N3HOS re HA wl il SOY lt 82484 n 06 10 WW 1919 JYO u 02 ON LOWAINOS Stui333n8 TWNOIS 1031409 Y3LSYW Sn8lX31 Lam emn Boaroiwm 4 274 T lt TOT 5 9 TINT SEO EI OS did 05 433
123. 960L at any time After the diagnostics have been entered using the keyboard connected to the LARC2 type the command Script space a Vilename Where filename is the name of the custom script that has been created show the 960L the path to the custom script where the script is located so it can find the script This assumes the custom is in the root drive on the floppy Don t forget to put a space between the command script and the filename 960L Setup for Functional Diagnostic Tests MIDI Test To pass the MIDI test connect a 5 Pin DIN to 5 Pin DIN cable MIDI cable from the MIDI In connector to the MIDI Out connector on the Clock card In addition there are two methods to verify that the MIDI THRU connector is functioning The first method is to connect a 5 Pin DIN to BNC cable from the MIDI THRU connector on the Clock card to the input of a dual channel oscilloscope and observe the MIDI data when executing the test Second connect the MIDI THRU port to a MIDI reader such as a PC running a MIDI terminal program and observe the MIDI data CO 00 CO 00 is the MIDI data that is sent in the MIDI diagnostic test Serial Port 2 Test To pass the serial port 2 test connect a D9 male connector that is wired as specified later in this chapter to the REMOTE 2 connector on the I O Clock Card The REMOTE 1 connector is tested by communicating with a LARC2 960L Power On Diagnostic Descriptions The 960L power on diagnost
124. 9DO800 9DOFFF 22 2 9C000 SOCFFFF y 84000 9BFFFF 2 83C400 83FFFF 2 20 2 83A400 S83BFFF 2 2 2 830400 839FFF 2 80000 837FFF e s 5301800 3019FF IOBUS SLOT 5 0 30000 300FFF 01000 2FFFFF 1 0 S0oFFFF intemal Decodes 280 Memory 7 37 960L Multi Channel Digital Effects System Service Manual same for both Z80s 0 7FE 2K Dual Port SRAM 7FF Motherboard interrupt mailbox 7 38 Lexicon Larc2 This section describes the theory of operation of the LARC2 main board and related modules Refer to Lexicon schematic 060 13379 General Description The LARC2 is the remote control unit for the Lexicon 960L Digital Effects System LARC2 provides easy access to all of the 960L functions and parameters A thin cable provides a direct link with the mainframe from up to 50 feet away or up to 1000 feet with an external12VDC power supply The LARC2 system board contains the following standard components Intel SA 1100 Processor 64KBytes Boot ROM 8 Mbytes of Flash 16 Mbytes of EDO DRAM Control for 8 motorized faders Control for an 640 x 240 LCD display Keypad and serial interfaces Diagnostic LEDs
125. As a minimum the remaining address bits must be low but they could well be shorted This test also confirms that the chip select read and write lines to from the Z80 are making it to the DPRAM Parameters This number selects which reverb card to test Legal values are 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 28014 This specifies which 280 the to test Legal Values 0 1 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Notes This test explicitly does NOT make use of the interrupt command lines INTL INTR tis assumed that the DPRAM Test which accesses the DPRAM from the 56301 side passes Z80 DPRAM Test The syntax for the 780 DPRAM Test is Z80Dpram Test Z80ID NumRepeats Tests a Dual Port RAM via a Z80 This test confirms that the Z80 can access most memory locations in the DPRAM The special command trigger addresses OxO3FE Ox03FF 0x07FE and OxO7FF in Rev 1 and higher cards are not checked by this test This test basically confirms that programs can safely be loaded into the DPRAM for the Z80 to run This command loads a small piece of code into the dual port RAM DPRAM which writes a data value into a memory location then halts To
126. CAPSM CER 1000pF 50V COG 5 16 119 120 122 123 129 130 132 133 139 140 142 143 149 150 152 153 245 10544 CAPSM CER 220pF 50V COG 5 24 94 95 97 98 100 101 103 104 106 107 109 110 112 113 115 116 121 126 131 136 141 146 151 156 245 10562 CAPSM CER 150pF 50V COG 10 22 1 4 7 8 16 19 182 183 185 186 188 189 191 192 194 195 197 198 200 201 203 204 245 11593 CAPSM CER 4700pF 50V COG 5 16 117 118 124 125 127 128 134 135 137 138 144 145 147 148 154 155 245 12485 CAPSM CER 1uF 25V Z5U 20 85 BC1A H BC2 BC14 33 C5 6 9 10 30 32 34 C36 38 40 42 44 45 C46 48 49 51 52 54 C55 57 58 60 61 63 C64 66 67 69 72 75 C78 81 84 87 90 270 00779 FERRITE BEAD 16 FB37 52 270 06671 FERRITE CHOKE 2 5 TURN 4 m02 17 00 FB1 4 270 06671 FERRITE CHOKE 2 5 TURN 6 02 17 00 1 4 53 54 8 6 270 09799 270 11545 300 10509 300 11599 300 14286 310 10422 310 10510 310 10565 310 10566 330 12143 340 11559 340 11573 340 11575 340 12936 340 13911 350 13921 350 14378 355 13987 410 11639 500 05855 510 10881 520 00941 620 12428 641 11466 702 13978 DESCRIPTION FERRITESM CHIP 600 OHM 1206 FERRITESM CHIP 600 OHM 0805 DIODESM 1N914 SOT23 DIODESM GP 1N4002 MELF DIODESM SCHOTTKY 1A SMB TRANSISTORSM 2N4403 SOT23 TRANSISTORSM 2N3904 SOT23 TRANSISTORSM 2N3906 SOT23 TRANSISTORSM 2N4401 SOT23 ICSM DIGITAL 74ACT244 SSOP ICSM LIN LM317M ADJ REG DPAK ICSM LIN NJM4580 DUALOPAMP SOP ICSM L
127. DPRAM that triggers the INTL line going low must be functional for the test to pass Parameters This number selects which reverb card to test Legal values 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 28014 This specifies which DPRAM associated with particular 280 the to test Legal Values 0 1 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running 6 7 960L Multi Channel Digital Effects System Service Manual Notes The following tests must pass before using this test 56301DpramTest Z80BootTest Z80DpramTest Z80 Tests Z80 Boot Test The syntax for the 280 Boot Test is Z80BootTest Cardid Z80ID NumRepeats This tests the Z80 s ability to execute code from the DPRAM This command resets the Z80 loads a small piece of code into the dual port RAM then checks to see if the 280 program ran The program first disables the interrupts then writes the number OxAA to address 0x000C in the DPRAM Finally the Z80 halts The diagnostic program then reads the contents of address 0 000 and confirms that it is OXAA This test confirms that the Z80 data bus between to the DPRAM is in tack and that at least the first 4 bits of the address bus are good as well
128. IN Output to Lexichip3 port 0 1 LEXI 2 SER IN Output to Lexichip3 port 0 2 LEXI 3 SER IN Output to Lexichip3 port 0 3 LEXI 4 SER IN Output to Lexichip3 port O 4 LEXI 1 SER OUT Input from Lexichip3 port 0 5 LEXI 2 SER OUT Input from Lexichip3 port 0 6 LEXI 3 SER OUT Input from Lexichip3 port 0 7 LEXI 4 SER OUT Input from Lexichip3 port 0 Lexichip3 1 DevicelD 3 0 Input LEXI 1 SER IN from TMIX 3 port 0 0 Output LEXI 1 SER OUT to TMIX 3 port 4 1 Input LEXI2 TO LEXI1 SER from Lexichip3 2 port 1 1 Output LEXI1 TO LEXI2 SER to Lexichip3 2 port 1 Lexichip3 2 DevicelD 4 0 Input LEXI 2 SER from 3 port 1 0 Output LEXI 2 SER OUT to TMIX port 5 1 Input LEXI1 TO LEXI2 SER from Lexichip3 1 port 1 1 Output LEXI2 TO LEXI1 SER to Lexichip3 1 port 1 6 14 Lexicon Lexichip 3 DevicelD 5 0 Input LEXI 3 SER IN from TMIX port 2 0 Output LEXI 3 SER OUT to TMIX 3 port 6 1 Input TO LEXI3 SER from Lexichip3 4 port 1 1 Output LEXI3 TO SER to Lexichip3 4 port 1 Lexichip3 4 DevicelD 6 0 Input LEXI 4 SER IN from TMIX 3 port 3 0 Output LEXI 4 SER OUT to TMIX port 7 1 Input LEXI3 TO LEXIA SER from Lexichip3 3 port 1 1 Output LEXIA TO LEXI3 SER to Lexichip3 3 port 1 Notes Itis assumed that the following tests pass DPRAM Test Z80BootTest Z80DpramTest LexichipWCSTest card Tests The following
129. KEEP AWAY FROM LIVE CIRCUITS Operating personnel must not remove instrument covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them DO NOT SERVICE OR ADJUST ALONE Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification to the instrument DANGEROUS PROCEDURE WARNINGS Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the must be followed Dangerous voltages capable of causing death are pres ent in this instrument Use extreme caution when han dling testing and adjusting CAUTION Notch ICs inserted backwards will be destroyed Incorrect insertion of ICs is also likely to Pin P 4 cause damage to the board General definitions of safety symbols used on equipment or in manuals CAUTION SAFETY SYMBOLS instruction manual symbol the product will be marked with this symbol when it is necessary fo
130. L awos 0017 nea 1105 ION 00 0 80991 080 a m WOS4 325 00 06 Tou 1096 SS3NuVH 318VO Sd 18 355 NO 0380 ASSY DGN 1096 TOFS 88750 055 31 3180 ISN S NNOO 30 135 3HVdS 0104 98750 055 318 2 ISN SYOLOSNNOD G3SNNN Z MOVE ONY 0103 3NMO OL SNOISIAZY n 5014 Z S310H IN3A NAHL ONIdOOT 8 114405 OL 2 NMOHS SV 553 109 921 XN OL 43 11 2 H19N31 338 21 H19N31 0314405 INYO AddOl3 OL 6r 0 1 OL 09 OL 1 338 XOHddv H19N31 03114405 YOONSA 9 85 e b n HL 66 2 11 We ganss 9NIMVHO 3190 LON 00 NOILVOMddl 2 I Cv1 080 eeu wo NO 0350 ASSY XIN A3 ON ON 953 3215 66 62 6 ZONY OSH sS mr V ASSV 5 E
131. NI 032914 ONY dOL NO 33TWAS HIM 3715 30 N3QHO Q330VlS 38 01 3V NOS NO 031319395 SWIL 10 33nivW3lll 020 1 0204 303543405 LON OO ONY AINO 3 383434 303 NMOHS SN3BWDN 18 4 00 6 8 Mr oo gz L 090 1000 003 00 8 8 02 0 OL 314433 00 00 c c oo c c 00 522000 003 Yad 00 NY S3ION 35 34 S N d 9 8 OHO 401140530 SNOISIASH 000 20 1 0128 8260 0890 318 2 06 313333 do 5 58 2 11 TIVOS 108 00 2 271 080 8 09 NO 0380 ASSY DON on oma azis 66 1 1 HSN 2 1 DANK ta sos 53 LN3WdIH aor 1 13 03130395 5531 Lievi oezf 261 081 LY3SNI AVO3 202 1 0840 138 1 01 ova 3 1 1331 1 5 WvO4 0 1991 0611 Ove 09 90 054 Lexicon Your Notes 9 95 Lexicon Inc 3 Oak Park Bedford MA 01730 1441 Tel 781 280 0300 Customer Service Fax 781 280 0499 Email Lexicon Part No 070 14826 Rev 0 Printed in U S A
132. On Diagnostic tests PCMCIA Card Detection During this operation the Power On Diagnostics checks for presence of a PCMCIA Card installed on the Option Board if a PCMCIA card has been detected a flag is set e Voltage Test During this operation a voltage test is performed to verify the 12V Power Supply is operating between 10 13 volts by reading the A D Converter value of the 12VSENSE signal NOTE If a PCMCIA Card was detected during the PCMCIA Card Detection routine above the card is now initialized and the card type is also detected Ifthe Option Board and PCMCIA Card were present the LARC2 will now enter the Option Board Menu as shown in the example below Refer to the Option Board Menu section of this document for more information NOTE The top line of the Interactive Diagnostics menu displays the date and time of the Boot ROM build and line 2 displays the Boot ROM version the actual text may vary LARCZ Menu file built 11 2000 14 52 36 Bootrom Version 0 13 11 Display Register X Download via 2 Set Register F Flash Operations 3 Dump Memory K Keyboard Echo 3 Set Memory D Interactive Diagnostics 5 Erase FLASH I Enable Interrupts 7 Display Ethernet Information L Loop on read 8 Set Up Ethernet Information 5 Diagnostics Suite 9 Download Image Via Ethernet ESHELL 21 zModem Download Load from PCMCIA Flash 0 Option Board Test B Boot 8 90000000
133. PLATE ACCESS 960L 1 701 14308 BRACKET SUPPORT STOP FP 960L 1 701 14309 STOP FP 960L 1 702 13959 PANEL FRONT 960L 1 702 13972 PANEL I O BLANK 960L 1 702 13983 PLATE MTG HARD DRIVE 960L 1 720 14404 GASKET CONDFOAM 2X 04X8 4 PSA 6 UNDER PANELS 8 1 960L Multi Channel Digital Effects System Service Manual PART DESCRIPTION QTY EFFalNACT 720 14405 AIR FILTER 4 3X3 5X 188 GRAY 1 740 09538 LABEL S N CHASSIS PRINTED 1 740 13573 LABEL MFR ID 9X 25 SILVER 1 740 14348 LABEL WINDOWS NT 960L 1 750 13356 HD DRIVE PROGRAMMED 960L 1 750 13390 PWR SUP 3 3V 5V 12V 300W 1 750 13392 DRIVE CD IDE 32X 85MS BLK 1 750 13393 DRIVE FLOPPY 3 5 1 44MB BLK 1 750 13950 CHASSIS SUBASSY 960L 1 750 14031 ASSY PCI AUDIO MIDI 1 202 09794 RESSM RO 0 OHM 0805 7 202 09871 RESSM RO 5 1 10W 1K OHM 12 202 09872 RESSM RO 5 1 10W 33 OHM 60 202 09873 RESSM RO 5 1 10W 10K OHM 33 202 10559 RESSM RO 5 1 10W 100 OHM 3 202 10597 RESSM RO 5 1 10W 180 OHM 3 202 10598 RESSM RO 5 1 10W 330 OHM 1 202 12836 RESSM RO 5 1 10W 2 7K OHM2 3 240 13216 CAPSM ELEC 22uF 16V 20 37 245 09291 CAPSM CER 470pF 50V COG 5 4 245 12485 CAPSM CER 1uF 25V Z5U 20 63 500 13944 CONN EDGE 2X60C 050 VERT PCI 8 500 13946 CONN EDGE 2X170C 1MM VERT NLX 1 510 01480 CONN POST 156X045 HDR 3MCG LOK 1 510 13903 CONNSM HDR 059 6P SHRD POL 1 510 13935 CONNSM HDR 059 3P SHRD POL 1 510 13940 CONN HDR 4 2MM 2X10C POL LATCH 1 510 13941 CONN POST 100 HDR 2X17MCG LP 1 510 13942
134. R166 168 172 173 R177 180 182 184 R186 190 192 194 202 09899 RESSM RO 5 1 10W 47 OHM 34 R59 62 113 115 R117 127 132 134 139 R144 147 158 183 202 10557 RESSM RO 5 1 10W 4 7K OHM 9 R40 170 171 174 176 R178 179 185 202 10559 RESSM RO 5 1 10W 100 OHM 4 R70 82 93 104 202 10569 RESSM RO 5 1 10W 10 OHM 4 R64 81 88 103 202 10947 RESSM RO 5 1 10W 680K OHM 1 R165 202 10948 RESSM RO 5 1 10W 390 OHM 1 RQ 202 11073 RESSM RO 5 1 4W 270 OHM 8 R1 8 203 10575 RESSM RO 1 1 10W 523 OHM 1 R11 203 11077 RESSM RO 1 1 10W 237 OHM 1 R10 240 11827 CAPSM ELEC 10uF 16V 20 5 19 22 23 26 27 240 12136 CAPSM ELEC 33uF 10V 20 7 3 5 6 9 10 21 29 245 09876 CAPSM CER 01uF 50V Z5U 20 4 34 45 56 67 245 10976 CAPSM CER 47pF 50V COG 5 2 114 115 245 12460 CAPSM CER 056uF 50V X7R 20 1 122 245 12485 CAPSM CER 1uF 25V Z5U 20 133 1 2 4 7 8 11 18 20 24 25 28 30 33 35 44 46 55 57 66 68 113 116 121 123 152 8 8 PART DESCRIPTION QTY EFFalNACT 300 11599 DIODESM GP 1N4002 MELF 2 330 09893 ICSM DIGITAL 74ACT157 SOIC 1 330 11990 ICSM LEXICHIP3B 100PIN PQFP 4 330 12321 ICSM DIGITAL 74VHCT08 TSSOP 1 330 12461 ICSM DIGITAL 74FCT2244AT QSOP 15 330 14247 ICSM DIGITAL 74VHCT245 SOIC 340 11559 ICSM LIN LM317M ADJ REG DPAK 340 12119 ICSM LIN TL7705 5V MON SOIC 346 12072 ICSM SS SWITCH QS3245 QSOP 350 12637 ICSM DRAM 1MX16 70NS SOJ 350 14248 ICSM SRAM 128KX8 70NS SOIC 350 14287 ICSM SRAM 2PORT 2KX8 55NS PLCC 350 14364 ICSM R
135. REFERENCE J7 8 11 18 J1 4 J20 U41 U12 REAR PANEL FADER BRKT MTG 3 KEYSTONE TO PCB 2 RP TO KEYSTONES 2 STRAIN RELIEF 1 BRACKET TO FADERS SOLDER GRN YEL BLK WIRES TO FADERS BEFORE ASSY TO BRKT PCB TO REAR PANEL R1 6 7 11 12 16 R21 22 R8 10 13 15 R2 5 17 20 C1 3 2 4 01 8 01 2 D3 6 9 12 15 18 D21 24 D1 4 7 10 13 16 D19 22 D2 5 8 11 14 17 D20 23 J1 INVERTER 8 13 960L Multi Channel Digital Effects System Service Manual OPT BD ASSY LARC2 PART NO 202 09873 202 10559 202 10586 240 11827 245 12485 330 13923 330 14314 345 13140 350 14046 500 05930 500 13907 510 09773 510 09985 510 14172 640 01706 643 01733 SHIP MAT L PACKAGING MISCELLANEOUS 270 14402 680 03525 730 04346 730 09509 730 14316 730 14317 730 14326 730 14327 730 14347 740 07693 DESCRIPTION QTY RESSM RO 5 1 10W 10K OHM 9 RESSM RO 5 1 10W 100 OHM 3 RESSM RO 5 1 4W 100 OHM 1 CAPSM ELEC 10uF 16V 20 4 CAPSM CER 1uF 25V Z5U 20 17 ICSM DIGITAL 74LVC32A TSSOP 1 ICSM DIGITAL 74LVC125A SOIC 1 ICSM INTER RS232 XCVR 5V SOIC 2 ICSM GAL 22V10 LARC2 OPT V1 00 1 CONN EURO C ROW a b c FEM RA 1 CONN EURO C 96P abc RECP VERT 1 CONN MEM CARD PC 68PIN 1 CONN MEM CARD 68 PIN EJECTOR 1 CONN DSUB 9MC PCRA 4 40SCRW 1 5 4 40 3 8 7 4 NUT 4 40 HEX SMALL ZN 4 FERRITE RND CABLE 8X1 6 SNAP 1 50 LARC 1 CARD WARRANTY LEXICON 8 5X11 1 CARD REGISTRATION GENERAL 1 CERTIFICATE CE 960L LA
136. THIS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 7 htm REM REM Description This document is a script file that tests the MIDI Port REM REM History 03 13 2000 Created REM 05 17 2000 clc modified to run the Serial Audio Test Reverbcardtests SerialAudioTest 0 Script 8 REM 9601 Diagnostics Test Script REM REM COPYRIGHT C 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 8 htm REM REM Description This document is a script file that tests the MIDI Port REM REM History 03 13 2000 lt Created REM 05 17 2000 clc modified to run the IO card Tests REM 6 23 960L Multi Channel Digital Effects System Service Manual cd IOTools lOClockBdTest 0 IOAInBdTest 0 IOAOutBdTest 0 IOAESBdTest 0 REM Script 9 REM REM MALL REM 9601 Diagnostics Test Script REM REM COPYRIGHT C 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 9 htm REM REM Description This document is a script file that tests the MIDI Port REM
137. TMIX HWEN It also generates the sample bus data transceiver control signals SAMP RD SAMP The TMIX HRDY signal is used to extend 56301 data transfer cycles as required by the T MIX chips This signal is qualified with the CTRL_SEL chip select in this GAL to create the TRANS signal to the 56301 When the signal is high and CTRL_SEL is low TRANS is high and the data transfer cycle is extended The 56301 Decode GAL U17 generates the chip selects for the T MIX DSP ports TMIXn DSP CS andit creates the dual port RAM chip selects read strobes and write strobes DP RAMn CS DP RAM RAM WRYJ The Tmix Chip Select GAL 016 generates the T MIX control port chip selects TMIXn 5 the Boot PROM chip select BOOT SEL and the T MIX DSP port interface clock TMIX DCLK The Boot PROM U18 is used by the 56301 to get its start up configuration This information consists of the 56301 clock PLL multiplier value which is used to multiply the 6 MHz clock to 80 MHz and the PCI subvendor that is passed to the host Pentium processor as part of the start up process The DSP Interrupt Buffer U3 is tri stated at start up to allow the resistors R36 39 to drive the dual function interrupt mode signals to the 56301 When the 56301 senses the rising edge of the DSP RESET signal it samples the IRQA IRQB IRQC and IRQD signals to determine the boot m
138. U1 the selected 8 channels of high speed data are converted to eight individual I2S streams each carrying complement and true data as previously described one for each D A converter At double speed sampling rates 88 2 96Khz each high speed channel can carry 4 audio samples during each word clock period so a pair can carry all 8 samples Within a pair samples from odd numbered input channels lefts are split off and carried by one member of the pair 5000 8 10 even numbered ones rights by the other SDO 1 9 11 This division is the same at single speed rates and so is the bit rate However only the last four octal time slots in each octal signal are used to derive the eight individual 125 audio streams In both single and double speed modes two high speed octal channels are necessary to carry 8 samples WCKI IOBUS WCLK SDO0 24 001 3 5 1250 2 4 6 50 inverted 125 data 50 Non inv data 1251 3 5 7 50 inverted 125 data S0 data TMIX_WCKI IOBUS WCLK 5000 2 4 5001 3 5 125 Ch1 3 5 7 125 Ch2 4 6 8 channel number data type Pin Descriptions Pin Name Type Description Host Interfacse 7 24 40 PWROK 56 RESET 82 ALL_MUTE 50 CS 47 DS 48 WR RD 66 0 65 1 67 D7 68 D6 69 D5 70 D4 79 D3 77 D2 80 D1 81 D0 Clocks 13 51 2 78 WCKI 29 IOBUS_WCLK 35 IOBUS_64FS 57 IOBUS_256FS 8 125 FS 37 125 64FS 23 125 256FS Pin Name Serial Au
139. also interrupt the DSP cards by asserting the IOBUS INT signal The ALL signal is provided to allow for a hardware assisted system wide mute Pullup resistors R28 R32 are provided to establish a default undriven signal level for signals PWR IOBUS INT IOBUS 05 IOBUS AS ALL MUTE respectively IO Backplane Slot Connectors The IO backplane bus is comprised of the system control bus serial audio clocks serial audio data in octal format MIDI pass thru connections RS232 pass thru connections Each IO card plugs into 96 pin EURO style connectors J1 J5 Slot Addressing TMIX1 SERD 3 0 1 0 AIN 3 2 DIN Pullup TMIX1 SERD 11 10 Expansion Pullup TMIX2 SERD 3 0 5 4 AOUT 7 6 DOUT Pullup 2 SERD 11 8 Expansion Pullup WCKI TMIX 512fs clk Active TMIX_CKI 2 TMIX 256fs clock 9 Active TMIX CKI TMIX wc clk Active WCLK Master WCLK Active 256FS Master 256FS O Active 128FS Master 128FS O Active 64FS Master 64FS Active SLOT WCLK System WC 3st Active SLOT SEL One unique sel per slot IOBP_ADDR 8 0 Control Bus Addr IOBP DATA 7 0 Control Bus Data IO RESET Master Reset Pullup Preview WCK INT Preview Word Clock INT 3st Active RD Control Bus Read IOBP WR Control Bus Write
140. and time of the Boot ROM build and line 3 displays the Boot ROM and Application version the actual text may vary The Interactive Diagnostic tests are executed from the Interactive Diagnostics menu by pressing two keys simultaneously For example pressing the PROGRAM REGISTER keys would execute the Self Test The key combinations used to execute the Interactive Diagnostic tests are listed in the table below TEST NAME KEY COMBINATION Self Test PROGRAM REGISTER LCD Test PROGRAM STORE KEY Test PROGRAM EDIT LED Test PROGRAM CONTROL Joystick Test PROGRAM JOYSTICK Fader Motor Test PROGRAM FINE ADJ LEXICON Test PROGRAM LEXICON Memory Test PROGRAM MUTE ALL Repetitive Test PROGRAM MACHINE Diagnostics Suite PROGRAM BANK To exit MUTE ALL MUTE MACH IMPORTANT Always follow the instructions which appear on the LARC2 LCD display or Debug Terminal when performing any of the Interactive Diagnostic tests Self Test NOTE These are the same tests that are executed during the Power On Diagnostics Prior to the execution of the Power On Self Tests the Realtime Clock is tested This test verifies the operation of the 32 768kHz crystal on the SA 1100 TEST 1 Motor Waveform Registers Test This test writes to control registers in SA 1100 then verifies the value written can be read TEST 2 Motor Control Registers Test This test writes to control registers in SA
141. anu lZ leer S3HONI SNOISN3MIQ 313 61 138 03140345 3SIMH3HIO SS3INn O Z IHS OSH NIVW OMG ASSY ISM SLUVd 303 c 133 5 33S 1 SALON 00 52 0004 023 N3d Z LHS 00 61 000 023 Yad 00 6 8 mr 00 e2 z 2 31310 0169 0 00 8 8 v 00 1c 000f 093 834 62 2 4 00 1120004 093 00 1 00 sz z 00 1 00 81 2 NY lt 24 2 1 080 H Z JO IHS OSH OMG ASSY 151 080 NOlLdl2S3Q 200 310018 lOMINOO IN3AnOOQ SNOISIA34 1HS NO 113 33S 08 NIVW 51015 NYHL 5318 2 0334 5214 2 6 2 5018 6 5014 v 87 9 8 NOLIVIN3IHO 310N B 581 9 9 3NDYOL 6 43 777 5014 SB1 NI 9 7 6 NOIDEN lt Lexicon 2 306 133 5 1 1 68 2 11 9305 9NIMVHO 31 25 LON 00 NOILYONddY 5 L cv1 080 su mo 20 G3sn ASSY DGN 2 325 66 62 6 8N Lr 5 TOUT OSH NM a w nn V ASSV 310 S VAONddv 2 1 Qr xk O V iS3TON
142. be opened by qualified service personnel Removing covers will expose you to hazardous voltages This trangia which appears on your 9 This triangle which appears on your u i bn CAUTION component alerts you to important ence of uningulated dangerous volt insi intenance instruc age inside the enclosure voltage operating and maintenance instru that may be sufficient to constitute a tions in this accompanying litera ture tisk of shock Notice This equipment generates and uses radio frequency energy and if not installed and used properly that is in strict accordance with the manufacturer s instructions may cause interference to radio and television reception t has been type tested and found to comply with the limits fora Class B computing device in accordance with the specifications in Subpart J of Part 15 of FCC Rules which are designated to provide reasonable protection against such interference in a residential installation However there is no guaraniee that interference will not occur in a particular installation If this equipment does cause interference to radio or television reception which can be determined by turning the equipment OFF and ON the user is encouraged to try to correct the interference by one or more of the following measures Reorient the receiving antenna Relocate the computer with respect to the receiver Move the computer away from the receiver Plug the computer into a dif
143. by R18 and optically coupled by U11 0601 which converts it to 5V logic level MIDI RXD high marking low spacing Midi input is echoed directly without decoding delay to J5 MIDI THRU via inverter U12 and current driver transistor Q2 2N3904 with R23 and R24 providing current limiting MIDI RXD connects to the IO backplane which in turn feeds it to the midi adapter which contains the asynchronous serial receiver that interfaces the serial data to the NLX motherboard Midi transmission originates on the midi adapter and arrives on the IO backplane as logic level MIDI TXD high marking Inverter 012 and transistor Q1 drive J4 MIDI OUTPUT with R20 and R21 providing current limiting Ttl Wordclock Interface An external TTL level wordclock rate squarewave applied to BNC connector J6 or J7 can be used as a reference for synchronizing the internal sample rate The input automatically configures itself as either a 75 ohm termination or as a high impedance bridging loop Each connector contains an internally switched 75 ohm terminating resistor which disconnects when an external mating BNC connector is present With just one BNC cable connected the resistor in the other connector terminates the line With two BNC cables 7 7 960L Multi Channel Digital Effects System Service Manual connected both resistors get disconnected and the input becomes a bridging high impedance loop allowing the line to be chained to other equipment and
144. card involves local filtering and regulation of supplies from the backplane as well as the production of boosted voltages for special purposes The main 5VD from the backplane is used by the fpga and the digital sections of the D A converters The 12V supplies from the backplane 12VSUP 12VSUP are filtered by FB4 FB1 and associated capacitors to supply 12V to the analog op amps 12VSUP also supplies U3 through a string of 5 dropping diodes to provide regulated 5VA for the D A converters which consume 8 x 15 120mA maximum Diodes D8 D9 prevent large differences from existing between the 5V pins of the converters U4 develops regulated 6 6V from 12VSUP through 3 shared dropping diodes This voltage supplies U5 which is the switching device for the VCC charge pump U5 switches at 6425 in the range of 3 6MHz driving a low impedance square wave into circuitry consisting of schottky diodes and associated capacitors This boosts the 12V to create supplies of around 18V which vary some with load due to the impedance exhibited by the switch and diodes Dropping diodes in series with regulators 03 U4 reduce their operating voltage resulting in cooler operation 7 26 Lexicon Bias voltage VB is derived from both 12VSUP by switching transistors 01 02 and associated diodes and capacitors An ac coupled two phase clock at wordclock rate drives the transistors with non overlapping on times creating a 24V squarewave to augme
145. considered a hazardous substance should be disposed of in accordance with any local national or international laws or guidelines Power Supplies Various manufacturer s power supplies have been specified for the 960L There are some slight mechanical differences in some of these power supplies Some units will have a power supply with a voltage setting switch as noted above Some units will have a power supply that does not have a voltage selection switch and the AC voltage input will be automatically sensed by the supply Always be sure to inspect the rear panel of the 960L for indication of proper AC voltage setup and in case of the need to switch for the appropriate AC input voltage Symptoms of possible power supply failures 1 The fan mounted on the processor of the Main PC card and the fan mounted on the right side of the chassis are spinning in slow motion or not spinning at all 2 The Larc2 is indicating not seeing the 960L mainframe If supply problems are suspected please test for proper voltage reading with a DMM meter as described in the Troubleshooting section of this service manual Larc2 Meter Display LED Handling Due to the special storage and handling procedures required for these dry packed moisture sensitive devices and the sensitivity to temperature Lexicon recommends that the Meter Board Assembly be replaced in its entirety when service of the LEDs is required Spare modules can be obtained from the factory Lexicon
146. currents OUTL and OUTR are connected out of phase as described above The combined currents OUTL and are fed to one summing node of dual op amp U14 OPA2134 through ferrite FB22 with their counterparts similarly fed to the other summing node The non inverting inputs of U14 are biased at about 2 7V by the FILTR pin of 06 which sets the dc compliance voltage into which the D A current sources are designed to operate 014 acts as a current to voltage converter converter producing a differential voltage from the combined differential D A currents Each current output pin of 06 sinks a bias of 1mA and delivers full scale signal current of 0 75 around that bias point 25 to 1 75 mA The output voltage at U14 1 is determined by feedback resistor R92 6 49k balancing the net current into the summing node The full scale ac signal voltage developed at U14 1 due to OUTL would be 0 75mA 6 49k 4 9V it becomes 9 8 when the equal contribution of OUTR is added A separate dc feedback scheme is used to eliminate dc bias from the outputs of U14 The feedback loop is formed by R49 R48 Q4 R47 R51 and ancillary components Q4 supplies bias currents into the summing nodes through R47 and R51 while Q3 senses the sum of the outputs of U14 through R49 and R88 The combination of Q3 and Q4 has high current gain and Q3 requires a negligible base current lt 1uA when the loop is nulled R48 supplies a bias which
147. from the supply under the overload condition The fuse maintains the high resistance state as long as it dissipates about 0 8W or about 66mA at 12V which is the short circuit condition The trip time is typically 0 2 seconds at 8 Amps which is a severe overload Smaller overloads can take many seconds to trip Resetting occurs when the load is removed and the fuse cools returning to the low resistance state When PS1 is tripped the voltage across it is sufficient to supply current through R16 to illuminate LED D3 D3 glows as an indication that the fuse has tripped visible through the ventilation slits in the bottom rear cover 7 49 960L Multi Channel Digital Effects System Service Manual LCD Backlight sheet 7 The backlight built into the color LCD module is based on a Cold Cathode Fluorescent Lamp CCFL which requires high voltage ac to operate This voltage is generated by the inverter module mounted in the LCD display housing The inverter is rated to produce an output of 900VACrms from for an input voltage of 5 to 12 VDC Regulator U4 LM2941 supplies this input voltage and protects the inverter by going into regulation if the input is too high due to misconnection U4 is a low dropout type and normally delivers nearly full voltage to the inverter with only around 1 2 volt across the regulator itself On off and brightness of the LCD backlight is determined by the control characteristics of the inverter module from control lines co
148. is determined by the octal select field in the AIN control register see register description for details TMIX Octal data Drives TMIX1 Octal 11 Tristate control is determined by the octal select field in the AIN control register see register description for details CONVERTER RESET 0 resets AD conveters 1 normal operation DFS1 0 determines AD sample rate 1x vs 2x See AIN control register description for details MODE Serial download interface mode signal Nomimally zero for loading from external SPROM FPGA Program 0 causes the FPGA to reload its program from the external SPROM CCLK Serial PROM clock signal FPGA DONE Asserted when FPGA program cycle has completed FPGA serial download initialization signal FPGA configuration data from SPROM JTAG Interface Not used JTAG Interface Not used 7 19 960L Multi Channel Digital Effects System Service Manual Power Supply Power conditioning for the Analog Input card involves local filtering and regulation of supplies from the backplane The main 5VD from the backplane is used by the fpga and the digital sections of the A D converters The 12V supplies from the backplane 12VSUP 12VSUP are filtered by FB1 FB2 and associated capacitors to supply 12V to the analog op amps 12VSUP also supplies U3 through a string of 5 dropping diodes to provide regulated 5VA for the A D converters which consume 4 130 520 maximum Diodes D7 D8 prevent large differe
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150. ld 80991 000 5 ASSY 8 08 GAN ld 8101 60 6 ASSY 08 S3V ld 1091 60 8 ASSY AINO 151910 NO Q3sn LON ASSY Gg INO 90WNY Id 9109 6201 ASSY AINO TWII9IG NO 0350 LON 1 ASSY 08 NI OOWNY ld 61091 60 29 L ASSY 08 x10 id 91091 020 5 00 1 8 00 82 8 00 9010009 003 834 AERE A 00 10000 023 E EC ES ASSY 08 XIN id 61071 60 oo zeoo0f 003 ia 9 6 cov oo sortoof ASSY 1d8 0 1 id lOvri ccO vor f hom oS GC ASSY XIN d 21091 020 OL AID 00 dere Ent o 0350 3H3HM AD 14119530 ON 9 83 3o 13365 swa 430551 21 25 LON 00 2 666 1 080 8 0 NO 03501 ASSY DGN nc ON OMO _WOS4 325 HSIN 1096 1096 20691 0910 IN3WdIHS OMG ASSY su 7777 IX al J 2 66661 T34 039345 5 3 10 5531 0 08691 062 5 OL 138 1 0 Gav 54 14 35013 30 Y3NYOD NI 32 14 8 G3NOIHSND 9 1 35 4135 335 0502 N3MOd 3lViMdONddV Ind 30 3015 1431 NO 510815 WvO3 33 138 39914 WAS 1V3H OV
151. locations of the DRAM above the memory locations where the Boot ROM was copied from C0008000h to C8000000h The test first writes 55555555 hex into these memory locations of the DRAM then the same memory locations are read to verify the data written in these locations is correct This write read sequence is also performed using the hex values FFFFFFFF and a Walking 1 s pattern Refer to the table below for the hex to binary conversion of the data patterns M L HEX S S VALUE B BINARY CONVERSION B 55555555 0101 0101 0101 0101 0101 0101 0101 0101 FFFFFFFF 1111 1111 1111 1111 1111 1111 1111 1111 1 0000 0000 0000 0000 0000 0000 0000 0001 2 0000 0000 0000 0000 0000 0000 0000 0010 4 0000 0000 0000 0000 0000 0000 0000 0100 8 0000 0000 0000 0000 0000 0000 0000 1000 10 0000 0000 0000 0000 0000 0000 0001 0000 20 0000 0000 0000 0000 0000 0000 0010 0000 40 0000 0000 0000 0000 0000 0000 0100 0000 80 0000 0000 0000 0000 0000 0000 1000 0000 100 0000 0000 0000 0000 0000 0001 0000 0000 200 0000 0000 0000 0000 0000 0010 0000 0000 400 0000 0000 0000 0000 0000 0100 0000 0000 800 0000 0000 0000 0000 0000 1000 0000 0000 1000 0000 0000 0000 0000 0001 0000 0000 0000 2000 0000 0000 0000 0000 0010 0000 0000 0000 4000 0000 0000 0000 0000 0100 0000 0000 0000 8000 0000 0000 0000 0000 1000 0000 0000 0000 10000 0000 0000 0000 0001 0000 0000 0000 0000 20000 0000 0000 0000 0010 0000 0000 0000 0000 40000 0000 0
152. mu 3 2s Elo RT3 R81 5 5 E 2 2 863 lt jas 3 8 R62 o mos f 8 elus 218 les gt Lexicon 230 13395 VIN 31925 2 1 1 LNG 1096 GAY NOdNOD 48 24 9 73 UOII XA 3015 401 U d EDEN TAMEN 2d F DA 29 OIO 5 BEEE ml age ven zen oen E R R2T 8151 670 ot 1 oe ID oor IE 2 arn 62n os 08 12 VIN ein Is os 10 15 pen em m m RS 62 5 LYN irn 08 Dr 6 Ir 0 001 I m ve 22 een 20 e2n oan 610 LIN 910 ENTETTT Wc cep de Seen
153. oh TXOLSZIOX 894 094 10 1ZZ166 2 WOHdS vod 00310166 X00 G39NVHO SNOISIA38I 2 r 5 9 4 8 Lexicon L B B 9 1 8 5 3 mer gus 2 68 19 Wd 611 090 4 8 a 3000 37 NNOO 844418 68 209 ZOXY NIVW N3H9S 3lva SVAOHddv 10304 zu WOR Ui 08210 VW 4038 RAE hs sa wu Wy dy T1300 Od ezn ud 2 97 8d YS 60 VS p 5218 xo 88 Hg vs 075 220 LS d VS F3 vg ES x 74
154. on the remaining Input Outputs pairs 3 4 5 6 and 7 8 Digital In To Analog Out Frequency Response Test Note Change the Clock Source and Inputs to AES see Audio Functional Tests Setup 1 Disable all Filters on the distortion analyzer 2 Connect a balanced XLR audio cable between the digital function generator and the 960L 1 2 AES Input 3 Connect a balanced XLR audio cable between the 960L 1 Audio Output and the distortion analyzer 4 Apply a 1kHz sinewave 0 1 dBFS 5 Set the Analyzer for OdB reference 1khz 6 Sweep the oscillator from 20Hz to 20kHz and verify the level is 1dBr throughout the sweep 7 Move the audio output cable to the 2 Output and repeat the test 8 Repeat the test for the remaining Input Outputs pairs 3 4 5 6 and 7 8 THD N Measurement Analog In to Analog Out THD N Test Note Change the Clock Source to Internal and Inputs to Analog see Audio Functional Tests Setup 1 NO MB N Connect a balanced XLR audio cable between the low distortion oscillator and the 960L 1 Audio Input Connect a balanced XLR audio cable between the 960L 1 Audio Output and the distortion analyzer Apply a 997Hz sinewave 9 75 VRMS Set the distortion analyzer to measure THD N Enable the Audio Band Pass filter on the distortion analyzer Verify the output THD N on the Analyzer is lt 0 002 Repeat the rest for the remaining Input Outputs 2 8 Analog In to Digital Out THD N Test 1
155. only as recommended by the manufacturer Servicing Do notattempt any service beyondthat described in the operating instructions Flefer all other service needs to qualified service personnel Safety Suggestions Damage requiring service The unit should be serviced by qualified service personnel when the power supply cord or the plug has been damaged objects have fallen or liquid has been spilled into the unit the unit has been exposed to rain the unit does not appear to operate normally or exhibits a marked change in performance the unit has been dropped or the enclosure damaged Outdoor Antenna Grounding If an outside antenna is connected to the receiver be sure the antenna system is grounded so as to provide some protection against voltage surges and built up static charges Section 810 of the Na tional Electrical Code ANSI NFPA No 70 1984 provides information with respect to proper grounding of the mast and supporting structure grounding of the lead in wire to an antenna discharge unit size of grounding conductors loca tion of antenna discharge unit connection to grounding electrodes and requirements for the grounding electrode See figure below Power Lines An outside antenna should be located away from power lines Antenna Lead in Wire Ground Clamp Antenna Discharge Unit NEC Section 810 20 Electric Service Equipment __ Grounding Conducto
156. pellets When a key is pressed its pellet makes a connection between the two halves of a corresponding gold plated finger pattern on the main pc board The patterns are organized for scanning as 5 rows by 8 columns Under software control the array is scanned by setting one of the row drive lines 4 0 to a high level Each driveline connects to the switch matrix SROW 4 0 through a corresponding diode and resistor D9 D13 R51 R55 If a keypad Switch connected to the driven row is pressed it connects its row and column forcing the corresponding bit of the column byte SCOL 7 0 high Un driven column bits remain at a low level due to 1K pull down resistors A read instruction issued by the CPU asserts the ENA KBD strobe enabling two 4 bit sections of buffer 024 74LVC 16244 to drive the bidirectional 8 bit LB D 7 0 bus of FPGA U18 018 in turn places the byte the CPU data bus SA 0 7 0 where it is read by the software The diodes on the row drivelines prevent multiple simultaneous switch closures from short circuiting the RD KBD outputs of U18 Note that in this scanning circuit two simultaneous switch closures can always be sensed properly however this is not true for every combination of 3 or more switch closures because two closures on the same column unavoidably cross connects two rows with the result that the other switches on those rows become indistinguishable The SA 1100 scans the keypad matrix using 5 address li
157. perform the previous set up procedure substituting the indicated sample rate in step 5 4 5 960L Multi Channel Digital Effects System Service Manual Gain Tests Analog In to Analog Out Audio Gain Test 1 Connect a balanced XLR audio cable between the low distortion oscillator and the 960L 1 Audio Input Connect a balanced XLR audio cable between the 960L 1 Audio Output and the distortion analyzer Apply a 1kHz sinewave 9 75 VRMS Verify the output level to be 10 VRMS 1 5 Repeat the test on the remaining Input Outputs 2 8 Analog Digital Out Audio Gain Test 1 Connect a balanced XLR audio cable between the low distortion oscillator and the 960L 1 Audio Input Connect a balanced XLR audio cable between the 960L 1 2 AES Output and the digital distortion analyzer Apply a 1kHz sinewave 10 94 VRMS Verify the output level to be 1 dBFS 1dBFS Move the audio input cable to the 2 Input and repeat the test Repeat the test on the remaining Input Outputs pairs 3 4 5 6 and 7 8 Digital Input to Analog Output Gain Test Note Change the Clock Source and Inputs to AES see Audio Functional Tests Setup 1 Connect a balanced XLR audio cable between the digital function generator and the 960L 1 2 AES Input Connect a balanced XLR audio cable between the 960L 1 Audio Output and the distortion analyzer Apply a 1kHz sinewave 1 dBFS Verify the output level to
158. populated as the current NLX motherboard no longer supports ISA By convention the primary IDE interface is connected to the hard drive and the secondary interface is connected to the CDROM drive The 960L 3 5 HD floppy drive is connected to the floppy drive connector 47 The actual hardware that supports all of these interfaces resides on the NLX motherboard itself Miscellaneous Connectors Sheet 6 Much of the circuitry on this page is not populated It was originally included for experimental or future use This includes components J18 J16 U2 U1 J17 J25 J19 J23 J24 and the resistors and capacitors associated with them The only functionality which is in use are power on and reset circuits J20 connects the front panel standby power switch and LED to the NLX backplane This switch is a momentary type which signals the NL X motherboard to either turn on or turn of the power by pulsing the SOFT ON OFF control signal The NLX motherboard lights the power on LED accordingly A standard PC hard reset signal is provided A momentary switch on the inside of the 960L chassis behind the front panel connects to the NLX backplane via J21 IOBUS amp Power Connectors Sheet 7 The NLX backplane and the IO backplanes are connected by two 40 pin ribbon cables which connect to J14 and J15 This interface is comprised of an 8 bit non multiplexed address and data system control bus and serial audio data and clock signals The cards in t
159. reference capacitor The terminal from channel 1 TOUCH1 is coupled to comparator U28 by capacitor C118 and current limiting resistor R103 The dual diodes of D22 are normally back biased D22 protects the touch circuitry by diverting high voltage triboelectric charge static either to ground or into C120 C199 biased at 5V by R87 In normal operation D22 and R103 can be ignored The other comparator input is connected to a discrete 33pF capacitor C119 and both comparator inputs are driven through individual 39 2K resistors R104 R105 by a bridge excitation waveform The excitation is produced from TCH_CLK a 3 3V 125kHz squarewave buffered by emitter follower Q8 Relative to the period of the squarewave the time constants of the bridge are long enough that the comparator inputs are quasi triangular The relative amplitudes of the triangles depend on the relative capacitances at the two inputs When the knob is not touched its capacitance is smaller than 33pF and the corresponding triangle at U28 3 is larger than that developed at U28 2 At the positive peak of the triangle the comparison will be positive and the output of U28 will therefore be high At that point the high level is latched by the squarewave into U35 which drives TCH_DET1 from its inverting output In the untouched state is constantly low When the knob is touched the capacitance becomes greater than 33pF and the result of the compariso
160. several system clocks that are distributed to the backplane This clock tree along with the action of the VCO ensures continuous coherent clocking within the system The PFD operates at the single speed wordclock rate in both single and double speed modes i e 48kHz at both 48 and 96kHz The VCO frequency is always divided by 512 to form one input to the PFD The other PFD input is derived from the chosen reference source conditioned by other logic within U2 to be at the single speed wordclock rate For internal crystal operation a multiplexer within U2 selects the input from one crystal and divides it by 512 to become 48kHz or 44 1kHz for U3 04 respectively External wordclock sources BNC e g get 7 11 960L Multi Channel Digital Effects System Service Manual divided by two if necessary to form single speed wordclock from double speed input A final multiplexer chooses the reference source to be applied to the PFD logic When neither crystal oscillator is in use they both get disabled under software control by bringing XTAL EN low Multiplexing and other configuration of the logic within U2 is established according to the value written to the internal control register by software PLL Detailed Description To ensure a high degree of VCO stability and constant loop gain 5Vdc for the PLL 5VA is supplied by a dedicated regulator U7 78L05 regulated from 12V Diodes D5 D6 prevent large differences from existing between the 5
161. signal All four Lexichips receive the 12MHZ clock signal and multiply this clock to 50MHz for internal use using an on board PLL The PLL filter for Lexichip 1 is comprised of R93 R94 and C56 The PLL supply voltage is filtered by R88 C54 and C22 The DRAM is used by Lexichip to store audio samples for processing The 21 DATA bus has resistors R65 91 which drive the bus at start up since all other data bus drivers are tri stated at this point Lexichip 1 and 2 sample the data bus on the rising edge of DBRD RSTO to determine the mode in which they are to be configured The Z80 Lexichip Clock GAL U35 generates the 12MHZ Lexichip clock and the clocks for the Lexichip s 280 interfaces ZCLKn well as the clock for both Z80s 780 This description of this page also applies to Lexichip 2 3 and 4 and their associated DRAMs which are shown on sheets 10 12 and 13 Bus Connector sheet 14 The Reverb Card passes commands and status between the host Pentium processor and the Bus peripheral cards through the bus connector P2 Bus Control sheet 15 The I O Bus interface is controlled by the 56301 through the circuitry shown on sheet 15 The Lexibus Control GAL U20 is configured as a counter that is used by the Lexibus Strobe GAL U23 to create Bus data transfer cycles The I O Bus control signals consist of an address strobe IO AS data strobe IO DS and read write qualifier IO WR T
162. the fifth RLY controls the mute relays as already described IOBUS RESET PWROK not used When low ALL forces zeroes on all 125 data lines 1250 7 Register Descriptions ADDR NAME Access Default Description Value 0x00 IDREG 7 0 RO Ox21 Board ID register IDREG 7 4 RO 2 Type 2 AOUT IDREG 3 0 RO 1 PCB Revision number 0x01 CTLREG 7 0 CTLREG 7 RW NA Reserved CTLREG 6 5 RW 0X3 Octal Select selects which IOBUS octal pairs are rec d by AOUT FPGA 00 AOUT octals rec d TMIX2 SERDO TMIX2 SERD1 01 AOUT octals rec d from TMIX2_SERD8 TMIX2_SERD9 10 AOUT octals rec d from TMIX2 SERD10 TMIX2 SERD11 11 AOUT input octals set to zero CTLREG 4 RW 0 DEEMPHASIS Active High When asserted hardware de emphasis is enabled CTLREG 3 RW 0 RELAY_MUTE Active Low When asserted All D A output relays are in the mute state CTLREG 2 RW 0 DAC_RESET Active Low When asserted all DACs are in reset state Software must assert then negate CTLREG 2 to complete a soft reset sequence CTLREG 1 RW 0 DAMUTE Active High When asserted DAMUTE enables the built in D A soft mute capability Refer to the AD1853 spec for details CTLREG 0 RW 0 96K EN Active high When asserted D A s operate in double speed mode 88 2 or 96K Clock Interface The following onboard digital audio clocks are derived from bus clocks TMIX and TMIX WCKI 125 FS I28 64FS and 125 256FS The bus clocks TMIX CKI 2 IOBU
163. to an AES input The sequence is described in section 7 of this document AES card Memory Map 7 29 960L Multi Channel Digital Effects System Service Manual Crystal AES TX 2 Crystal AES RX 4 Crystal AES RX 1 Crystal AES TX global chip select used for synchronized TX reset 00 Board I D register read only hardwired to 33 FPGA Control Register MELLE Number output table output table output table output table 0 Local loopback mode for test only High 0 Lock Register ass Number 7 2 notused j 6 fntused xa 5 ____4 Lexicon xa 3 7 07757 2 ootused Enter word clock seek mode see following discussion HEN Drive clocks to Crystal receivers see following discussion Locking to the AES Input Word Clock The procedure to derive the system word clock from an AES input stream is as follows 1 Set bit 0 of the Lock Register low and bit 1 high to enter seek mode 2 Program the selected Crystal AES receiver to be in master mode by setting bit 1 of the receiver s Control Register 2 high Bit 2 of the Interrupt Enable register of all of the Crystal receivers should also be set high Wait at least 10 mSec Set bit 1 of the Lock Register low to exit seek mode Program the selected Crystal AES receiver to be in slave mode by setting 1 of the receiver s Control Register
164. verify the voltage is 5VDC 25VDC Audio Functional Tests Setup 1 2 3 14 Power on the 960L with the main power switch and wait for the Power on diagnostics cycle to finish On the Larc2 press the Control Button The Control Mode screen will appear at this time Press the 1 button to set the clock source to Internal Note for any Digital In tests you will need to return to this screen and select Source 3 AES EBU Press the Right arrow button to jump to the Rate page Press the 2 button to select a 48kHz sample rate Press the Soft button labeled CONFIG under the display Press the 4 button This will highlight the 1 8in 8out setup for Diagnostics Press the Edit button the screen will then display the Edit Mode page Press the Soft button labeled Algorithm the display will then read Algorithms Options Enabled Press the Soft button labeled Select a small box will open with 1 OctalThru stated Press the 1 button then the Enter button this will load the Diagnostic 1 8in 8out setup Press Control and then the gt key to highlight Inputs Press the key to toggle the state to AN Analog Note for any Digital In tests you will need to return to this screen and toggle the state to AES Digital Set the distortion analyzer to measure VRMS Note The following tests should also be performed at the 44 1kHz and 96kHz sample rates Prior to performing the following tests at each sample rate you must
165. voltage linear regulator U3 LM3940 The 2V logic supply is derived from the 5V by adjustable linear regulator U7 LM317 set to 2V by R34 R35 Register Summary The following is a full map of the physical address space all addresses in hex Address 7 Symbo Name 00000000 0001FFFF Bootflash 0800 0000 087 FFFF 7 Programflash alternate 7 50 Lexicon 1000 0702 PS 2STAT PS 2 Status Register m awasi 1800 0000 1800 0002 CS3REG CS3 Register 2000 0000 2000 _ PCMClAsocketil Ospace 2800 0000 2800 FFFF 7 PCMCIA socket 1 attribute space 2 00 0000 200 7 PCMClAsocket memory space 3000 0000 3000 _ PCMClAsocket2l Ospace 3800 0000 3800 FFFF PCMCIA socket 2 attribute space 3 00 0000 3C00 FFFF PCMCIA socket 2 Memory space Lo Ee U a d c 7 E ad ee Lx 2111 a Oe p 8004 0060 HSCR0 HSSP control register 0 8004 0064 HSCR1 HSSP control register 1 7 51 960L Multi Channel Digital Effects System Service Manual 8004 006C HSDR HSSP data register 8004 0070 HSSR0 HSSP status register 0 8004 0078 HSSR1 HSSP status register 1 j er ce 45 2 e p 9000 0000 9000 0004 9000 0008 9000 000 9000 0010 9000 0014 9000 0018 9000 001 pp asa ces
166. word clock Rising edge denotes start of octal frame Input frequency is 44 1Khz or 48Khz Not used Not used Not used AD Frame Sync falling edge denotes start of frame Locally generated AD bit clock falling edge denotes start of bit period Locally generated AD MCLK signal Locally generated Does not actually scale with sample rate Nominal output frequency is XXXX 44 1 88 2Khz or XXXX 48 96Khz Description I2S audio data for channel 1 I2S audio data for channel 2 125 audio data for channel 3 I2S audio data for channel 4 125 audio data for channel 5 I2S audio data for channel 6 I2S audio data for channel 7 I2S audio data for channel 8 TMIX Octal data Received from TMIX2 Octal 0 Octal selection is determined by the octal select field in the FPGA control register see register description for details TMIX Octal data Received from TMIX2 Octal 1 Octal selection is determined by the octal select field in the FPGA control register see register description for details 7 25 960L Multi Channel Digital Effects System Service Manual 7 SDO2 INPUT TMIX Octal data Received from TMIX2 Octal 8 Octal selection is determined by the octal select field in the FPGA control register see register description for details 84 003 Octal data Received from 2 Octal 9 Octal selection is determined by the octal select field in the FPGA control register see register description for details 9 SDO4 INPUT
167. 0 Writing to 0x3c000200 Writing to 0x3c000400 Writing to 0x3c000800 Writing to 0x3c001000 Writing to 0x3c002000 Writing to 0x3c004000 Writing to 0x3c008000 Writing to 0x3c010000 Writing to 0x3c020000 Writing to 0x3c040000 Writing to 0x3c080000 Writing to 0x3c100000 Writing to 0x3c200000 Writing to 0x3c400000 Writing to 0x3c800000 Reading from Flash PCcard Lexicon This portion of the test reads each value and compares it to what was written If any errors are detected the failure results are reported and the test then waits for acknowledgement of the error Address 0x3c000000 GD 0x0000 BD 0x0000 Address 0x3c000002 GD 0x0001 BD 0x0001 Address 0x3c000004 GD 0x0002 BD 0x0002 Address 0x3c000008 GD 0x0003 BD 0x0003 Address 0x3c000010 GD 0x0004 BD 0x0004 Address 0x3c000020 GD 0x0005 BD 0x0005 Address 0x3c000040 GD 0x0006 BD 0x0006 Address 0x3c000080 GD 0x0007 BD 0x0007 Address 0x3c000100 GD 0x0008 BD 0x0008 Address 0x3c000200 GD 0x0009 BD 0x0009 Address 0x3c000400 GD 0x000a BD 0x000a Address 0x3c000800 GD 0x000b BD 0x000b Address 0x3c001000 GD 0x000c BD 0x000c Address 0x3c002000 GD 0x000d BD 0x000d Address 0x3c004000 GD 0x000e BD 0x000e Address 0x3c008000 GD 0x000f BD 0x000f Address 0x3c010000 GD 0x0010 BD 0x0010 Address 0x3c020000 GD 0x0011 BD 0x0011 Address 0x3c040000 GD 0x0012 BD 0x0012 Address 0x3c080000 GD 0x0013 BD 0x0013 Address 0x3c100000 GD 0x0014 BD 0x0014 Address 0x3c200000 GD
168. 00 828000 093 3d 00 50 0004 093 00 2 0004003 DFO 5 40 SNOUISOd 100 40000003 OL 00 2c000f003 534 aav 00 012000 003 3d P iv 003 wad 69 2530 SNOISIA33 LWOO XIN 01 SISSVHO 5 01 2 8014 9 1 1HS 335 2102 XIN OL 9n SISSWHO 30 SQNVMOL QN3 43873 318443597 09 5214 0 5214 1 581 4 5 300401 Lexicon 40 tts 3NON 68 2 24 93055 9NWW30 77 25 LON 00 Nouvoriddv 8662 080 sa E No 0350 IH ON ON azis 66 21 1096 1096 SISSVHO ws pn mm Sd XIN I3MOVHG 9961 1004 GG cr Du di 4015 60691 101 YG 56 96661 di 4015 1804405 1 0 8 80691 101 S zii aides SSN 334 fid XIN 1509915 LOSPL LOL tg L SS300V 3114 98681 101 716 NOISNVdX3 3ivid S86 1 104 706 y 510 09 1509915 0 8 69681 10 1304405 89661 101 78 24 20 15 2 MOL
169. 000 0000 0100 0000 0000 0000 0000 80000 0000 0000 0000 1000 0000 0000 0000 0000 100000 0000 0000 0001 0000 0000 0000 0000 0000 200000 0000 0000 0010 0000 0000 0000 0000 0000 400000 0000 0000 0100 0000 0000 0000 0000 0000 800000 0000 0000 1000 0000 0000 0000 0000 0000 1000000 0000 0001 0000 0000 0000 0000 0000 0000 2000000 0000 0010 0000 0000 0000 0000 0000 0000 4000000 0000 0100 0000 0000 0000 0000 0000 0000 8000000 0000 1000 0000 0000 0000 0000 0000 0000 10000000 0001 0000 0000 0000 0000 0000 0000 0000 20000000 0010 0000 0000 0000 0000 0000 0000 0000 40000000 0100 0000 0000 0000 0000 0000 0000 0000 80000000 1000 0000 0000 0000 0000 0000 0000 0000 When a Memory Test failure is encountered the test will stop and loop continuously at the failed address location The address where the error occurred along with the data sent and the data received is sent to the LCD display and also to the Debug Port NOTE The Memory Test will run for approximately 2 minutes The LARC2 will return to the Interactive Diagnostics menu when the Memory Test is complete Repetitive Test This test was designed to exercise the LARC2 hardware during the Burn In cycle of the Manufacturing Test process Refer to the following instructions for the execution of the Repetitive Test 6 40 Lexicon Press amp hold down the PROGRAM
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171. 02 09871 202 09872 202 09873 202 09874 202 09899 202 10557 202 10559 202 10571 202 10586 202 10597 202 10836 202 10892 202 11041 202 13904 203 10894 203 10895 203 11077 203 12841 ADHESIVE SILICONE RTV CLEAR ADHESIVE EPOXY 5 MIN POT SLD MOTOR 10K 60MMTRAV POT RTY 10KB KNURL 6MMX15MML RESSM RO 0 OHM 0805 RESSM RO 5 1 10W 1K OHM RESSM RO 5 1 10W 33 OHM RESSM RO 5 1 10W 10K OHM RESSM RO 5 1 10W 2 2M OHM RESSM RO 5 1 10W 47 OHM RESSM RO 5 1 10W 4 7K OHM RESSM RO 5 1 10W 100 OHM RESSM RO 5 1 10W 100K OHM RESSM RO 5 1 4W 100 OHM RESSM RO 5 1 10W 180 OHM RESSM RO 5 1 4W 1K OHM RESSM RO 5 1 10W 2K OHM RESSM RO 5 1 10W 680 OHM RESSM RO 5 1 10W 220K OHM RESSM RO 1 1 10W 340 OHM RESSM RO 1 1 10W 681 OHM RESSM RO 1 1 10W 237 OHM RESSM RO 1 1 10W 39 2K OHM QTY NL 0 050 0 042 8 1 5 30 5 cA P EFFalNACT 06 14 00m Lexicon REFERENCE LCD TO MAIN BD J1 FFC CABLES TO BRKT 2 5 PC 1 1 PC CABLE TO METER BD CONN TO INVERTER FFC CABLES TO BRKT C14 15 XDUCER R139 146 R136 R3 45 129 132 W1 R11 13 15 19 31 33 R36 44 62 63 70 71 74 77 80 106 113 R128 131 137 R51 55 R1 10 12 20 21 37 38 R42 43 47 50 57 61 R64 69 72 73 75 76 83 84 90 91 96 97 102 103 138 R114 R4 5 R6 9 18 R119 R87 R22 25 40 41 56 R39 R16 R115 117 122 127 R130 133 135 R81 82 85 86 88 89
172. 021 14507 PL SHIP NLX CPU BD TESTED 960L 021 14508 PL SHIP NLX EXT BD TESTED 960L 021 14509 PL SHIP I O EXT BD TESTED 960L 8 15 Chapter 9 Schematics and Drawings Schematics 060 13309 SCHEM NLX BPL 960L 060 13319 SCHEM I O BPL 960L 060 13329 5 BD 960L 060 13339 SCHEM AIN BD 960L 060 13349 SCHEM AOUT BD 960L 060 13359 SCHEM AES BD 960L 060 13369 SCHEM RVB BD 960L 060 13379 SCHEM MAIN BD LARC2 060 13389 SCHEM METER BD LARC2 Drawings COMPONENT LAYOUT PC BD NLX BPL 960L COMPONENT LAYOUT PC BD I O 960L COMPONENT LAYOUT I O CLK 960L COMPONENT LAYOUT PC BD AIN 960L COMPONENT LAYOUT PC BD AOUT 960L COMPONENT LAYOUT PC BD AES 960L COMPONENT LAYOUT PC BD RVB 960L COMPONENT LAYOUT PC BD MAIN LARC2 080 13998 ASSY DWG CHASSIS 960L 080 13999 ASSY DWG SHIPMENT 960L 080 14403 ASSY DWG PS CABLE HARNESS 960L 080 14231 ASSY DWG MAIN HSG LARC2 080 14232 ASSY DWG DSPLY HSG LARC2 SHARP 080 14233 ASSY DWG JOYSTICK LARC2 080 14234 ASSY DWG MECH MAIN BD LARC2 080 14242 55 DWG DSPLY HSG LARC2 KYO 080 14243 ASSY DWG SHIPMENT LARC2 Lexicon 9 1 Your Notes Lexicon 9 3
173. 1 J6 is a standard NLX riser card connector This interface contains the signal interconnect for the following functions PCI Bus The 960L support up to 4 PCI slots ISA Bus not supported by 960L Primary Hard Drive and Secondary IDE Interfaces Floppy Interface Power supply management and control PCI Interface Sheets 2 3 4 Sheet 3 contains the series termination resistors for various PCI signals This sheet also contains the pullups for the slot specific signals e g GNT IRT Sheet 4 and 5 are the PCI slot connectors The 960L support the 5V PCI v2 2 standard Slot addressing and identification are accomplished through standard PCI bus algorithms In PCI parlance Slot 0 IDSELO is the topmost PCI slot in the 960L and Slot 3 IDSEL3 is the bottommost slot This is significant in that not all NLX motherboards support four 4 PCI slots From a mechanical standpoint i e least mechanical keep out constraints the top slots are the most valuable in that the PCB in these slots can support more surface area i e more real estate more functionality per slot and the least significant slots i e Slot 0 1 are supported first by NLX motherboards For a detailed understanding please refer to the PCI Specifications V2 2 IO Connectors Sheet 5 Sheet 5 contains the ISA interface J5 primary J9 and secondary J8 IDE and floppy drive J7 interface connectors The ISA bus connector is not
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175. 100dB A A Performance Freq Response 48K 20Hz 20Khz 1db Freq Response 96K 20Hz 40Khz 1db Dyn Range gt 107 dB 20 20 2 THD lt 002 Digital Audio IO Connectors Four Male XLR Outputs Four Female XLR Inputs Format AES EBU Word Size 24 bits Sample Rates Internal 44 1 48 88 2 96KHz Accuracy within x10ppm External 44 1 48 88 2 96KHz Lock Range 1 Group Delays milliseconds Lexicon 3 1 960L Multi Channel Digital Effects System Service Manual 44 1 48 88 2 96 Khz Khz Khz Khz 144 133 081 0 74 A D 2 42 2 23 1 80 1 66 D A 1 54 1 42 1 35 1 25 D D 0 54 0 50 0 36 0 33 Synchronization TTL Word Clock Input 75 Ohm self terminating loopthru TTL Word Clock Output Low Z BNC Falling edge marks start of frame Clock Jitter Intrinsic Exceeds AES3 Amendment 1 Jitter Gain Exceeds AES3 Amendment 1 Control Interfaces LARC2 Ports 2 MIDI In Out Thru supports program change Algorithms Ambience 48K Stereo amp Surround Chamber 48K Stereo amp Surround Plate 48K Stereo amp Surround Reverse 48K Stereo amp Surround Random Hall 48 96K Stereo amp 48K Surround Ambient Chamber 48K Surround Standard Hardware Configuration DSP CPU Card Compartment One System CPU Card One Reverb DSP Card Two Spare DSP card slots One MIDI Card IO Card Compartment One Analog Input Card One Analog Output Card One AES EBU Digital Card One
176. 104 usni 185899 738 5 Dd TROT EOE Da fon Lari Mu 5 Od m rs aa TEE a n E OOV od ee T i Lon Lam lt d Tay fod Lan sas aod Gd sous pa c Lar TOV 804 TOV 54 adl Tiyaq son g gt us avg c e 74015 404 14618 104 O WWSO TOV Da 404 1 uon rs uam 8808 e SOY 04 vu Dd lant ww c rasa aod Mn Teka pa lt 8001 AA vu ate Tay od psl Lam m 12 04 0647 joa 90 899 Ldbg OIOV Od 19 ore 18 4 TOWED ee Ha u T Usi lt Y Y Od ZQ trav Da n Uu 404 104 n nr ver Lil pam THOSE BOI 3306 DY Da o SHOW 804 se eeu 8109 109 w gt gon Lor M Ta uon 809 70033709 024 809 Tod lt ju e TGV GOI iod leon TOIT EOI TORE 104 gt V 09 lt gt 9 kor m TINO
177. 1100 then verifies the value written can be read TEST 3 A D Control Registers Test This test writes to control registers in SA 1100 then verifies the value written can be read TEST 4 A D Self Test This test reads the MIN MID and MAX values based on the reference voltage of the A D converter TEST 5 Not Used TEST 6 External PS 2 Keyboard Test This test initializes the External Keyboard and tests for the presence of a keyboard connected to the AUX port of the LARC2 by sending 8 characters out the port and monitors any data that is received The data received is then compared to what was sent 6 34 Lexicon NOTE This test requires an External Keyboard connected to the AUX port Otherwise the test will fail when an External Keyboard is not present Diagnostic error messages are also sent to the Debug Port to indicate when a failure has occurred as shown in the example below ERR KB01 TXRDY 0 should be 1 GPIO fffc7ec ERR KB02 IBFULL 1 should be 0 Stat 12 fffc7ec ERR KB03 Keyboard Timeout TEST 7 Host Port Loop Back Test This test checks for the presence of a Loop Back Plug connected to the HOST port of the LARC2 by sending 8 characters out the port and monitors any data that is received The data received is then compared to what was sent NOTE This test requires a Female RS 422 Wraparound Plug installed in the HOST port Otherwise the test will fail when the Loop Back Plug is not pr
178. 12V to the PLL active filter op amp 12VSUP also supplies the REMOTE connectors through fuses as described previously 7 14 Lexicon Analog Input card The Analog Input card consists of eight channels of A D conversion and associated input circuitry sheets 1 4 bus interface foga and connector sheets 5 6 and on board power conditioning sheet 7 This card is plugged into the IO backplane which is accessed from the rear of the 960L chassis The following system block diagram highlights its place within the 960L system Overview The Analog Input card is based on the AK5393 delta sigma A D converter which accepts 2 channels of analog input and produces a pair of 24 bit digital audio samples at nominal rates up to 96kHz Four converters provide the 8 channels of A D conversion High impedance differential inputs accept balanced or unbalanced signals at 24dBu maximum level on XLR connectors Additional circuitry supplies the conditioning necessary to drive the differential 5Vp p A D input The design supports nominal sample rates of 44 1 48 in single speed mode and 88 2 96kHz in double speed mode The following detailed circuit description applies to channel 1 sheet 1 The seven other channels are similar Input Buffer Signals at pins 2 and 3 of input XLR connector J2 are ac coupled by C83 and C85 and attenuated by voltage dividers R130 R129 and R132 R131 respectively Differential input impedance is gt 50kohms common mode
179. 138 1 8 560 0 91 WOLLOG OSH 2 1004 201 001 ONISNOH LL 1 004 401 ONISnOH 80071 00 08 OL 331H3AN 338 8 99 96 9SH 9SH IYO 822 089 Q8 OL 097 338 0103 4 5 ANSXO8L O44 37189 LETY 1 089 m Q8 NIV OL 08 X313 84 NNS XO0Z O44 31872 GCZv 1 089 01 401 OL NIVW 401 OL ASSY 5 8 NZ Hd HNd 8 X9 MYOS 81 10 199 6 OL 401 0 9SH OL 9SH Alasa 9 HNd 8 e Xc 9 MYOS 9110 079 8 XOLSAOP BONY 0677 095 00 52 0004 093 Yad 4303 8 ONVL 30115 80NM 6 0 1 056 9 00 6 8 Mr 00 82 1 96 a A 2068 5 00 8 8 N 960 00 1 0 0 003 L OvdA3 92771 lt 5 1 62 2 snau aov ASSY Q8 ld 20071 20 1 00 1 oo sz z 8N 00 112000 093 Yad ASSY 9SH ld 5071 6560 56 00 1 00 91 2 9 62 aav ASSY MOlLSAOP ld 920 1 220 1 0350 3H3HM 40530 9 87 1 080 2 30 IHS 9SH 1950 ASSY Z 30 IHS 95 1950 OMG ASSY Zez 1 080 NOlLdIM2S3Q 9018 1O8MINOO v 1130 NO NMOHS 540 5 AlddV ISM 184 303 2 133 335 00 61000 093 Yad 6
180. 2 low 6 Set bit 0 of the Lock Register high to drive clocks to the Crystal receivers The system is now locked the selected AES stream If the cable is disconnected or the sample rate is out of range then this procedure will need to be repeated to reestablish lock Software should monitor the loss of lock status in the selected AES receiver to detect loss of AES signal and should also monitor slipped sample to detect an input stream that is out of the accepted sample rate range 7 Global TX Reset Chip Select OV ds o This address is decoded as a simultaneous chip select for all four Crystal AES transmitters This location should be used to reset all four devices within the same word clock period This technique will ensure that the AES transmitters NRZI streams are aligned properly Octal Select Register Register Bit Active State Number 7 Notued 6 Noued 5 2 Notued amp 1 amp 11 amp 3 Input octal group select encoded bit 1 See following table 0 Input octal group select encoded bit O See following table 0 Tmi 20ctals2 amp 3 O 7 31 960L Multi Channel Digital Effects System Service Manual Local Loopback Mode When the local loopback mode bit is set in the FPGA control register the AES inputs are looped through the FPGA and back to the AES outputs Also the octal data received from the Reverb card is looped back to the Reverb card by the FPGA as follows
181. 221 720 0 8 10 DC AC INV 2W OUT W DIMMING SCRW 6 32X3 8 PNH PH ZN SCRW 0 80X1 4 PNH PH ZN SCRW TAP AB 6X3 8 PNH PH ZN CABLE FFC 20CX 5MM 7 5 CABLE HSG HSG 5C 6C 8 5 HOUSING DSPLY FRONT LARC2 HOUSING DSPLY REAR LARC2 CLIP 78LX 28WX 26H 100 156 LENS LCD LARC2 OVLY METER BRIDGE LARC2 SPCR PVC 6 8X3 0X 02 BLK ADH QTY 1 135 1 k N BA a ma Aa EFFmINACT 04 27 00 04 27 00 07 26 00 HOLDER INVERTER amp DISPLAY CABLE DSPLY HSG TO MN HSG MAIN BD TO TOP DSPLY HSG TO MAIN HSG ON INSIDE OF UPPER MAIN HSG FERRITE MTG FERRITE MTG HSG BOTTOM REAR PANEL REAR PANEL HSG BOTTOM MAIN BD U8 BRACKET TO POT HSG REAR TO FRONT INVERTER TO METER BD LCDBRKT TO DSPLY HSG TO METER BD J1 TO INVERTER DISPLAY LARC2 SHARP KYOCERA SHARP 430 13934 680 14236 680 14240 701 14216 720 10158 720 14224 DESCRIPTION DISP LCD 640X240DOTS COLOR CABLE FFC 20CX 5MM 12 5 FOLD CABLE CONN HSG 2C 2 5 BRACKET LCD SHARP LARC2 TAPE FOAM DBL STK 5WX 025THK GASKET LCD SHARP LARC2 KYOCERA 430 14034 680 14237 1701 14217 720 18 720 5 DISP LCD 640X240DOTS COLOR CABLE FFC 18CX 5MM 5 7 FOLD BRACKET LCD KYOCERA LARC2 TAPE FOAM DBL STK 5WX 025THK GASKET LCD KYOCERA LARC2 MAIN BD SUBASSY LARC2 120 02023 120 09619 200 13938 200 14153 202 09794 2
182. 228 I 0z208 T 6198 E al E E salu ai Iv lll akal ake 819 sz sav SU 3000 4805 il L l TT 1 xl HH mms 1 0208 6108 9987 5108 708 MOT 609 i ie 201 818615 Y 1 784 ZOOPNL 9 d 5 sa I sol teoa 2208 I eT Suy 0082 1 Wr 200112000 3d OSOOOA AB T 999 0054 Nanya mon en exo eaa snl sal al rl wl wl wl sur Loew Le Low Lem Low Leen Lour BET 808 T Z8098 T LE08T 40 08 T 6208 T 8208 T 912081 9208 T 2a Taoa T3108 Poroa Wed Wa 00 01 1000 wad 9050 9 e Gr 1 102165 Ma3xO3HO 20 2 v 5 9 4 8 9 31 02 01 0002 9 2 9 9 8 9 30 13365 ees Wd qnss ANN 214 69661 090 8 20 aaoo azis 6840 ZL ST3NNVHO 6680
183. 3 and 4 are the other receivers and transmitters The description of sheet 1 also applies to sheets 2 3 and 4 Digital audio is received through an XLR connector J3 This differential pair is transformer coupled by TX2 and terminated by R38 before being presented to the Crystal CS8413 digital audio receiver U6 The device has a microprocessor interface and internal registers that are used to configure the device and to monitor the status of incoming digital audio stream Digital audio is transmitted by the Crystal CS8403A digital audio transmitter U10 This device also has a microprocessor interface and internal registers that are used to configure the device The differential output from this device is transformer coupled through TX10 and transmitted through an XLR connector J7 FPGA sheet 5 The primary function of the AES FPGA U2 is to convert octal format serial audio to 125 format in the following manner The Crystal receivers pass 125 audio to the AES FPGA that packs the eight samples into octal serial streams that interface to the Reverb Card via the I O Bus The Crystal transmitters receive 125 audio from the FPGA These 125 streams are unpacked from octal serial streams that are sent from the Reverb Card The FPGA also contains control and status registers to set up and monitor the card s operation These registers are described in sections 5 10 of this document At start up the FPGA clocks in its configuration program from a se
184. 4 FH PH ZN 8 640 01716 SCRW 6 32X3 8 PNH PH ZN 28 640 02704 SCRW 6 32X1 4 PNH PH BLK 22 640 03675 SCRW 6 32X1 1 4 PNH PH ZN 4 FAN ASSY 640 04339 SCRW 4 40X1 4 PNH PH SEMS ZN 15 NLX BPL TO CTR SUPP 640 10498 SCRW M3X6MM PNH PH BZ 18 PS BRKT TO PS 640 13996 SCRW 10 32X1 2 FH PH BZ 6 641 01703 SCRW TAP AB 4X1 4 PNH PH ZN 3 RVB BD MIDI BD MTG 641 13116 SCRW TAP AB 4X3 8 FH PH BZ 8 643 01728 NUT 6 32 KEP ZN 5 643 08200 NUT 4 40 HEX ZN 2 STOP BRKT TO FP 644 01735 WSHR FL 6CLX3 8ODX1 32THK 1 680 13988 CABLE RECP DE9S 9C 18 L 1 NLX CPU COM1 I O BPL J7 680 13989 CABLE RECP DB15P 15C 18 L 1 MIDI BD TO I O BPL J8 680 13990 CABLE 100 SCKT SCKT 2X20C 2 L 2 BPL 911 TO NLX BPL J14 BPL J10 TO NLX BPL J15 680 13991 CABLE 100 SCKT SCKT 2X20C 6 L 1 680 13992 CABLE 100 SCKT SCKT 2X17C 6 L 1 FL DR TO NLX BPL J7 PS CABLE TO FL DR 680 14203 CABLE 100 SCKT SCKT 2X20C 9 L 1 HD DR TO NLX BPL J9 PS CABLE TO HD DR 680 14206 CABLE 059 SCKT SW amp LED 4C 14 L 1 PWRSW TO NLXBPL J20 680 14305 CABLE 059 SCKT SW 3C 14 L 1 RESET SW TO NLX BPL J21 680 14306 CABLE 100 SCKT SCKT 2X5C 18 L 1 NLX CPU COM2 TO BPL J6 700 13965 RAIL TOP BOTTOM 960L 2 REAR OF CHASSIS 700 13967 COVER TOP BOTTOM 960L 2 700 14406 FRAME SUPP AIR FILTER 4 46X3 6 1 701 13346 BRACKET NLX PS 960L 1 701 13963 BRACKET MTG RACK 4U 960L 2 701 13968 BRACKET SUPPORT FAN 960L 1 701 13969 BRACKET SUPPORT CD DISK 960L 4 701 13985 PLATE EXPANSION BLANK 960L 1 701 13986
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186. 54 2 SSVdA8 8850 1 88 8 _ SPA 06 0 WW uoorxe avd ON y 0 I 0 ms 0 0 me 894 0 8 199 0 0 eduvds sou on 0 gt 83 ar 9 gt Tes 1 SN Jon r1 N 0 228 suy sen I Sa ul Sa I say L sa 1 wl wl Suy sen I Su I Sa I zl ul aul ond 52 829 SOT mp som oT HT HT SET ST eT oT sT OT OT oT pa ou quer Ls N Es SuO1IOVdV9 55 4 V3uvds 0 mH E 0 my isa 0 5 8 8 Su3dWnr TVN9SIS GND SISSVHO Qs S3tuvds a T Nrd pee 090668 400 Q3ONVHO OH ual SNOISA38 L 4 9 9 1 9 39 5 L 4 v 3 9 30 3 12 69661 66118 i awa 3 di EHR Mo 29 amp
187. 6 R138 and if a scope is triggered on word clock it is possible to see the audio samples in these data streams The assignment of these signals to the cards in the system is under software control and changes depending upon how the I O bus is populated The TMIX1 NSAC signal is the audio word clock interrupt to the 56301 7 34 Lexicon T MIX 2 sheet 5 2 shown on sheet 5 sends serial digital audio to audio output cards on the bus These digital audio streams are formatted with eight audio samples per word clock These audio streams can be probed on R146 R157 and if a scope is triggered on word clock it is possible to see the audio samples in these data streams These signals represent digital audio that has been processed by the Reverb Card and when monitored in conjunction with the signals on T MIX 1 are an indicator of the end to end integrity of the Reverb Card s audio processing chain assignment of these signals to the cards the system is under software control and changes depending upon how the bus is populated The SPO0 7 signals on the T MIX are general purpose pins which are used to drive the signals RSTO and DBRD RST1 These are the reset signals to the Lexichips Gals sheet 6 The logic to interface the 56301 to its on board peripherals is shown on sheet 6 The 56301 Strobe Control GAL 019 creates the strobes that interface to the T MIX control ports SAMP RD
188. 688001 NO 10620166 X00 G39NVHO SDH 20 SNOISIA3N Lexicon 4 9 JO 33HS 2 9 314 z 69551 090 0002 9 1 3009 325 660 8 1096 08 SAY N3HOS NOSS300MdOMOIN 480 66 wywal STWAOUddY 3o 06 10 WW uooixe 00 802166 400 G39NVHO 10 620166 300 Nad G39NVHO 40580 SNOISIA3N sin 984 7814 i INI cel t vl FELE 838VdS 0 LOL O lt 6914 sas sare leorz eare eore ean 2472 TOO 959 1104109 8 pp i OV SNVEL _ 88 7 8 950 E ON TES 454 Tas 508 Ol XOL AOS nos axa 588 8588888 ZHINGS 10698450 ud NOSH XINL 92 77 6 20014904 ouo 12841 1450
189. 758 240 13217 241 09798 244 10423 245 09869 245 09895 245 10561 245 10562 245 12485 270 00779 270 06671 270 11545 270 12323 270 14359 300 10509 300 10563 300 10564 300 11599 300 13881 310 10510 330 09796 330 09889 330 10523 330 14355 330 14357 340 09244 RESSM RO 5 1 10W 2 2K OHM RESSM RO 5 1 10W 10K OHM RESSM RO 5 1 10W 470 OHM RESSM RO 5 1 10W 47 OHM RESSM RO 5 1 10W 4 7K OHM RESSM RO 5 1 10W 47K OHM RESSM RO 5 1 10W 100 OHM RESSM RO 5 1 10W 680K OHM RESSM RO 5 1 4W 220 OHM RESSM RO 5 1 4W 270 OHM RESSM RO 1 1 10W 4 99K OHM RESSM RO 1 1 10W 681 OHM CAP ELEC 100uF 25V RAD LOW ESR CAPSM ELEC 1uF 50V 20 5 5mmH CAPSM ELEC 47uF 16V 20 CAPSM TANT 10uF 10V 20 CAP MYL 22uF 50V RAD 5 BOX CAPSM CER 001uF 50V Z5U 20 CAPSM CER 10pF 50V COG 1096 CAPSM CER 100pF 50V COG 5 CAPSM CER 150pF 50V COG 1096 CAPSM CER 1uF 25V Z5U 20 FERRITE BEAD FERRITE CHOKE 2 5 TURN FERRITESM CHIP 600 OHM 0805 FERRITESM CHIP 750 OHM 0805 COILSM VAR 10H 596 5 6X6 2X6MM DIODESM 1N914 SOT23 DIODESM DUAL SERIES GP SOT23 DIODESM SCHOTTKY LOW VF SOT DIODESM GP 1N4002 MELF DIODESM VARACTOR BB132 TRANSISTORSM 2N3904 SOT23 ICSM DIGITAL 74AC00 SOIC ICSM DIGITAL 74ACT04 SOIC ICSM DIGITAL 74HCU04 SOIC ICSM DIGITAL 74HC123A SOIC ICSM DIGITAL 74FCTT ABT244SOIC ICSM LINEAR 78LS05 5V REG SOIC QTY 5 5 1 EFFmINACT N N N Q N f N N N Q
190. 8 VIVO 11018 03 SUBAISOSNVEL 0 221 6 1 RI ONIS L 2 v L 8 Lexicon 9 43 5 L 2 r 5 9 1 8 5 8 or 0 1358 FTES qanssi 69201090 29 8 AagwnN 3goo azis 69 0 78 HT 88098 orsus EDD 818 WHOS SRL NL 06 0 VW quoaqag xwevoe 6 OONAS XINI 1 5 5 lo 0 16 _ OGL TS 19539 OMS 4 E 5315 YOM LOL MENE XINI NH Prey TAS NONE XII 150 LO 5 aay 4 5 gt sr leas SO ws Z IVO 8 E poas OH 18 16045 Enn iyi 1 dV x 8 8046 feast 1048 8 LAS 1 0 d 16 895 lt CARS 250049 uU divs 2 4 s aqu Nep wrod idis 124
191. 801 9NnOSO ON SEGOV 50601 ON EGY SnBOl SEGOV 55801 ON OSTEO annon ON SHO boel saaa enaoi DECOY EOL SV1VG 81801 50801 80801 s VIVO 80801 50801 worl ee OVIVG 50801 0 1 1 0 5780 Ag TAY ON BESET ANNONO 20535 FENZ TE TES ON CMON 00835 ZANT ON 010455 A 50935 SESS XL pw j 65 ON 1 CANOES ON TOYS L LOND ZONO xn TS ON 00438 ON CES ON FERES ON ON 538957 Ico TN SIO TIN 10d 1018 TRONS T ford ZU XI Tola Pacha 765 sayl suu L sz szv sav say L sa 35 57801 15913 8 GOT WOT SHOT WIT LOT HOT COT 10 DO XL DE XAL CANOES 852 eror 5 SEDI DON XL asnoss BITIN STO 57801 QN AS 5382 81801 II3S38 51801 LES 7188 1018 om ouo 5 Y Mor Y 00001166 Q3ONVHO L DOS MAL L s 9 8 9 17
192. 8015 144 5 3 530 405 0350 LON INYO OL INYO AddO1j OL INYA 09 OL a3sn 10 0 1 OL ozr XIN OL zi Wall sau 31882 350 XlddnS Md 301538 H19N31 318 2 5532 3 4001 Wvuovi Yad SHOIO3NNOO NI 9Md W3MOdNns AlddNS N3MOd 00 8280004 003 tid AINO VIII OOV 003 Sd 3MVMQNYH OIN 35038 00 21 0004 00 20 000 700 260004 00 905000 00 2420004 00 0120004 00 611000 003 Yad 35 3 99158 3105 LON 00 NOLWONdd 0350 ASS LGN 1096 S81 NI 01 8 300801 5014 8 5 0 1 OL SH1 NI 01 8 S81 NI 01 8 Sold cir ur 10 0 1 OL Sold 2 338 581 9 3NOYOL 798 XIN OL 3 581 4 5 300801 6 3AMO 02 30 3OvJunS 401 73 13 88 318 355 5248 cer 5914 2 69 Vo XIN OL 9 1 dns 1r 148 XIN OL S81 NI 01 8 3nouoL 300301 581 8 9 3nbuoL 581 2 1 5078 581 2 300401 5014 9 81
193. 88661 090 9850 SNL NYO am 3000 azis 6690 9d 1041NO2 865 00 oat on 7086 GBSAVWEHOS SNOEN 06 10 VW 0 UN VOSS ng avd E Tes M 24120 NILOO 20 sono Sn 222222 S eano 1 nouis POA 9090000 NO 1 555555 Par 010855 OXINL 39 b QODOSO m ONILOO INILOO SNILOO 000 108 lt 001 ans frou lt pa Se i MM3SIXINL OYISINI t ES 271 OE ms OLQN3SIXINL BOYISZXINL suse VO bon ew fequasixWi soso bol ZGH3SIXWL ZOM3SZXIML ZS NL lt POM rqu lt 1015 2 JOM 1018 LEE 04 1018 MO XIN 7 1 1 a SDIOW ADS iu len lear lt IIS ear eg AO b Ap IBIN 105 con laje 19 RIN AON 8 n HTT a n h aci 0910 OU S SEND AO lt QUOS se ai 2 01 6 Z lt ar EHO VOXOW NOM pp veo vou 00 ON FON eH Add
194. 90 95 97 103 106 R111 113 119 122 127 R129 135 138 143 145 R151 R23 24 26 27 29 30 R32 33 35 36 38 39 R41 42 44 45 48 53 R58 63 68 73 78 83 R19 R47 49 51 52 54 56 R57 59 61 62 64 66 R67 69 71 72 74 76 77 79 81 82 84 86 88 102 104 118 120 R134 136 150 R91 94 96 100 107 R110 112 116 123 126 R128 132 139 142 R144 148 R22 25 28 31 34 37 R40 43 8 5 960L Multi Channel Digital Effects System Service Manual PART DESCRIPTION QTY EFFalNACT REFERENCE 203 12719 RESSM THIN 1 1 10W 2 00K OHM 16 R89 93 98 101 105 R109 114 117 121 R125 130 133 137 R141 146 149 203 14296 RESSM THIN 196 1 10W 6 49K OHM 16 R50 55 60 65 70 75 R80 85 92 99 108 115 R124 131 140 147 240 00608 CAP ELEC 2 2u0F 50V RAD 2 C13 14 240 09367 CAPSM ELEC 10uF 25V NONPOL 20 16 C165 180 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 5 02 17 00 11 12 18 21 205 across 28 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 6 02 17 00 11 12 18 21 205 206 240 11111 CAPSM ELEC 47uF 6V NONPOL 20 8 157 164 240 12330 CAPSM ELEC 2 2uF 35V 2096 8 C93 96 99 102 105 C108 111 114 240 13803 CAP ELEC 560uF 35V RAD LOW ESR 1 C15 241 11799 4 7 6 3 20 32 29 31 33 35 37 39 41 43 47 50 53 56 59 62 65 68 70 71 C73 74 76 77 79 80 82 83 85 86 88 89 91 92 244 09390 CAP MYL 01uF 5 RAD MINI 8 181 184 187 190 193 196 199 202 244 10423 CAP MYL 22uF 50V RAD 5 BOX 4 2 3 17 20 245 09875 CAPSM CER 1uF 50V Z5U 20 7 22 28 245 10416
195. 9601 Multi Channel Digital Effects System Service Manual 960L Multi Channel Digital Effects System Service Manual Precautions Save these instructions for later use Follow all instructions and warnings marked on the unit Always use with the correct line voltage Refer to the manufacturer s operating instructions for power requirements Be advised that different operating voltages may require the use of a different line cord and or attachment plug Do not install the unit in an unventilated rack or directly above heat producing equipment such as power amplifiers Observe the maximum ambient operating temperature listed in the product specification Slots and openings on the case are provided for ventilation to ensure reliable operation and prevent it from overheating these openings must not be blocked or covered Never push objects of any kind through any of the ventilation slots Never spill a liquid of any kind on the unit This product is equipped with a 3 wire grounding type plug This is a safety feature and should not be defeated Never attach audio power amplifier outputs directly to any of the unit s connectors To prevent shock or fire hazard do not expose the unit to rain or moisture or operate it where it will be exposed to water De not attempt operate unitif thas been dropped damaged exposed to liquids it exhibits a distinct change in performance indicating the need for service This unit should only
196. 960166 309 Yad Q3ONVHO v 681008 Wed bed 00 020188 GELO ae 00210166 X00 2 6911 8 Wed po 00 82066 G39NVHO 33803H9 0140539 2 S L 8 9 7 B 9 4 8 5 8 5 929 60 6 eenz SNS gez Es 60501 090 29 8 3EWAN 325 66121 HO SH0193NNOO OSIN cerge HME 06 10 VW ooixe AVO 0402 ON y w x 40 22 Ni I303WVI x eer zn in n t SW 88 1 1 f z w L d 088 gt 15 933 305 993 5 sd al ad g ESAS 2 waw eal M t ange PA 9 x 5 L ser E E
197. Analog Output card Test The syntax for the Analog Output card test is JOAOutBdTest optional NumRepeats 6 15 960L Multi Channel Digital Effects System Service Manual This tests the control interface to the Analog Output card This command writes a walking 1s pattern to the control register on the IO backplane s Analog Output card reading the data back to confirm it Card Id This defines which card in the system to access Initial systems will only contain a single card so a value of 0 should be used An additional card would use a value of 1 NumRepeats optional This defines how many times the test is run The default if not entered is 1 time A value of 0 runs the test infinitely Pressing any key exits the loop AES card Test The syntax for the AES card Test is JOAESBdTest CardID optional NumRepeats This tests the control interface to the AES card This command writes a walking 1s pattern to the control register offset 0x20 on the IO backplane s AES card reading the data back to confirm it Card Id This defines which card in the system to access Initial systems will only contain a single card so a value of 0 should be used An additional card would use a value of 1 NumRepeats optional This defines how many times the test is run The default if not entered is 1 time A value of 0 runs the test infinitely Pressing any key exits the loop 960L Troubleshooting Tools As outlined in the sections
198. C Fill Memory with a Pattern Ifthe PROGRAM MACHINE keys were pressed during the Power On Diagnostics the LARC2 will now request the Menu mode from the 960L Mainframe when the LARC2 is connected to a 960L The LCD display on the LARC2 will indicate the following Requesting Menu Mode from 960L Ifthe PROGRAM MACHINE keys were not pressed during the Power On Diagnostics the LARC2 will now perform a normal boot process and attempt to establish communications with the 960L Mainframe when the LARC2 is connected to a 960L The LCD display on the LARC2 will indicate the following Looking for 960L 6 30 Lexicon For detailed information on the Power On Diagnostics amp Boot Sequence refer to the flowchart below 6 31 960L Multi Channel Digital Effects System Service Manual Execute Power On Diagnostic Tests Begin monitoring continuously for PROGRAM MACHINE keys being held Are the PROGRAM ENTER keys pressed Is RS 422 Wraparound Plug Installed Else Yes Enter Interactive Yes Diagnostics Menu Exit Are the REGISTER CONTROL keys pressed Check for the presence of Option Board amp PCMCIA Card Is the Initialize PCMCIA Card PCMCIA Card amp present Detect Card Type Yes Perform Voltage Test Were the PROGRAM MACHINE keys pressed Were the Option Board amp PCMCIA Card present
199. C52 56 60 FB12 19 R1 36 37 39 40 42 R43 45 46 88 95 R108 119 R16 17 R2 3 18 31 35 R23 25 27 29 R4 15 24 26 28 30 R22 R48 50 52 54 56 71 R98 101 104 107 R38 41 44 47 R72 87 C1 2 C17 20 23 26 C19 22 25 28 C41 44 C3 16 18 21 24 C27 29 40 45 49 C53 57 FB4 6 8 10 FB1 3 5 7 9 11 L1 4 U4 5 8 7 960L Multi Channel Digital Effects System Service Manual PART DESCRIPTION QTY EFFalNACT REFERENCE 330 13867 ICSM DIGITAL 74VHC245 S0IC 1 345 14245 ICSM INTER CS8403A XMTR SOIC 4 U10 13 345 14246 ICSM INTER CS8413 RCVR SOIC 4 350 14205 ICSM FPGA XCS10 3 14X14 1 350 14376 IC SPROM 960L AES V2 1 1 8 430 10421 LEDSM INNER LENS GRN 470 12913 XFORMER PULSE AES 1 1 2X 4SP TX2 4 6 8 10 12 TX14 16 490 02356 CONN JUMPER 1X025 2FCG 4 W1 4 pins 2 amp 3 500 05855 CONN EURO C ROW a b c MALE RA 1 J1 510 02899 CONN POST 100X025 HDR 3MC 4 W1 4 510 10881 CONN XLR 3MC PCRA PLASTIC 4 J7 10 510 11086 CONN XLR 3FC PCRA LATCH SMALL 4 J3 6 520 00941 IC SCKT 8 PIN LO PRO TIN 1 U3 620 12428 LUG Z4 INT STAR XLR GND 4 J7 10 641 11466 SCRW TAP 4X3 8 PNH PH BZ TRI 16 XLR J3 10 TO PANEL 702 13980 5 960 1 RVB BD ASSY 960L 202 09794 RESSM RO 0 OHM 0805 1 R169 202 09871 RESSM RO 5 1 10W 1K OHM 22 R41 42 52 56 63 116 R122 125 133 141 143 R161 164 191 195 196 202 09873 RESSM RO 5 1 10W 10K OHM 110 R12 39 43 51 57 58 R65 69 71 80 83 87 R89 92 94 102 R105 112 118 121 R123 124 126 140 R145 146 159 160
200. CONN POST 100 HDR 2X20MCG LP 4 I O BPL ASSY 960L 202 09794 55 0 0805 5 202 09873 RESSM RO 5 1 10W 10K OHM 29 202 10559 RESSM RO 5 1 10W 100 OHM 6 202 10597 RESSM RO 5 1 10W 180 OHM 5 8 2 REFERENCE CHASSIS REAR SIDE SUPPORT TO NLX BPL J4 NLX BPL BD ASSY R1 4 7 10 104 106 R98 103 154 158 164 R13 42 52 81 R2 3 5 6 8 9 11 12 R94 113 120 122 R126 140 R107 109 111 R108 110 112 R162 R43 51 82 93 96 97 C3 5 8 9 11 13 20 C22 25 27 29 33 35 C37 39 43 45 47 54 C56 59 68 71 73 76 78 80 84 86 88 90 C94 96 98 101 C103 106 C120 122 124 C4 6 7 10 12 14 19 C21 23 24 26 28 C30 32 34 36 38 C40 42 44 46 48 53 C55 57 58 60 69 70 C72 74 75 77 79 C81 83 85 87 89 C91 93 95 97 99 100 102 104 105 107 C110 123 J1 4 10 13 J6 J22 J20 J21 J26 17 J8 9 14 15 R1 42 45 R4 15 17 33 R2 16 34 36 38 40 R3 35 37 39 41 240 12136 240 13216 245 10416 245 12485 330 10527 500 13907 510 13877 510 13942 510 13993 510 13994 DESCRIPTION CAPSM ELEC 33uF 10V 20 CAPSM ELEC 22uF 16V 20 CAPSM CER 1000pF 50V COG 596 CAPSM CER 1uF 25V Z5U 20 ICSM DIGITAL 74HC138 SOIC CONN EURO C 96P abc RECP VERT CONN POST 100 HDR 2X5MCG LP CONN POST 100 HDR 2X20MCG LP CONN POST 100 HDR 2X8MCG LP CONN HDR 200 4MC SHRD CLK BD ASSY 960L 202 09795 202 09873 202 09897 202 09899 202 10557 202 10558 202 10559 202 10947 202 11072 202 11073 203 10424 203 10895 240 09786 240 10
201. D 6e617607 address 08180000 The location of the failure s can be found by converting the hexidecimal values to their binary equivalent The example below shows that the data sent GD does not match the data received BD at bits 1 and 6 GD 17645 110 1110 0110 0001 0111 0110 0100 0101 BD 6e617607 110 1110 0110 0001 0111 0110 0000 0111 Address 08180000 1000 0001 1000 0000 0000 0000 0000 NOTE The data checking that is performed during the Program App routine when the Program Flash memory is programmed only verifies the data that was written to the flash and does not test the unused portion of the flash memory 6 46 Lexicon Chapter 7 Theory of Operation NLX Backplane This section describes the theory of operation of the 960L IO Backplane card Overview The NLX PC form factor is an industry standard platform originally developed by Intel The significant difference between this form factor and other commodity PC form factors is that all system interconnect is removed from the motherboard and located on a separate riser card Since there are no cables connected to the motherboard it can be easily removed The NLX backplane is a custom NLX riser card that Lexicon developed to meet the needs of the integrated PC and its peripherals along with providing Lexicon specific functionality not possible utilizing other standard PC form factors The 960L NLX backplane provides the interconnect between the PC motherboard DSP cards o
202. D sub Aux PS 2 Keyboard 6 pin Mini DIN Ext Power concentric 2 5mm Operating Distance With power from 960L up to100 feet With Ext Power up 101000 feet Power Requirements 12 VDC 3 A max Dimensions Size 12 7 L x 8 25 W x 5 0 323mm x 210mm x 127mm Weight 4 165 Regulatory Approvals FCC Class A CE EN55103 1 EN55103 2 TUV EN60065 Environment Operating 5 to 40 C Storage 30 to 70 C Humidity 95 max non condensing Lexicon Chapter 4 Performance Verification This section describes the tests and procedures for verification of the operation of the 960L with LARC2 and the integrity of its analog and digital audio signal paths Initial Inspection and checkout Note Please refer to the chassis assembly drawing in the Schematics and Drawings section later in this manual 960L Mainframe 1 Remove the top and bottom covers of the 960L 2 Inspect the entire unit for obvious signs of physical damage 3 Unscrew the front panel screws and fold down the front panel 4 Verify that the main processor board midi card and reverb cards are seated properly and are held down with screws Also verify that all cable connections to the midi card main processor board and backplanes are in place 5 Atthe back of the unit in the power supply section verify that all connections are firmly seated to the backplane Verify all ribbon cables firmly seated to the backplane and that Pin 1 of all ribbon
203. ETER BD METERBD 4 RED METERBD 5 RED METERBD 46 RED METER BD METER BD STEP 0 0 1 212 2 12 3 3 3 LOCATION LED X ON 3 7 7 6 7 8 9 0 3 6 Lx TT TT te T Lx EDIT MAIN BD METER BD METER BD METER BD METER BD jj 6 37 960L Multi Channel Digital Effects System Service Manual Joystick Test This test is used to verify the operation of the Joystick hardware and circuitry This test has been designed to display the movement of the Joystick on the LCD display During the test the Joystick must be moved along the outside edges farthest from the center a minimum of two times When the test is executed the following screen will appear on the LCD display The outer White brackets in the corners of the LCD display represent the lower limits of the Joystick Test The inner Red brackets on the LCD display represent the upper limits of the Joystick Test During the test an image box is drawn in the center of the LCD display as the Joystick is moved which represent the values read from Joystick A D converter The image displayed in each corner of the LCD display represents a magnified view of the four corners from the image drawn in the center of the LCD display as shown in the example below NOTE The image drawn in the center of the LCD dis
204. EV LAYOUT SCALE N A SHEET 1 OF 1 J R22 i OCTIN OCTIN OCTIN OCTOUT 1 OCTIN OCTOUT OCTIN OCTOUT OCTOUT OCTOUT CK I WCK I 18 15 R21 AESTB TX AESS6 TX AES34 TX 57 Qats12 R39 re 3 Rig ers 3 R 861810 RIS 85 89 14 RARE 21 28 E a 5 5 2 EPA Gs 5 5 x i 8425 5 R60 IR40 c22 R25 9 e R58 20 E E88 AES34 Rx O gt 557 R24 FB5 5 I A 3 1 R23 o ERa 18 5 R56 F84 AES12 EE eS o wes EIE M 2 t R88 gt IESS 5 ED RTT zi E S R76 R84 gt 9 RST kh ERL
205. Fea 2 Cm 4 er Ne eom 21 12 220488 XINL 4 08 N zavas Orl 024435 0d TS 480 XINL a QN EL eius TOES AW wd Nf sal nous sq oes ALE EA 60835 r grasas 16 vey amus oe ES SOY SNS pad ANYS NF 70856 95 dS 98 81 co ar zorz zow awie ECL dNVS fat 20435 92446 00 ANYS sieuueuo tags 180403 50838 FPO 050218 1 0 ANYS suas gaa O2 INO eva tp IVO Sp IVO Sy IYO div SOAS 1p IVO dS B7 PIAS 1 0 dS QS ELAS IVO diNS 16 E 10438 TNT 52 OLAS YQ dS GAS LY dS 09 8 3 1 0 dMVS 0 1 ZXINL 00835 19118180 dS Z9 AS IVO ANYS 9 ET 809 lt S9 __ TAGE 19 ENG Jv ANYS 88 ZAG IVO div LAS Yd div ON INO dis 0 02 18 LYO dWvs OUS GORT ar 68051 686201 00002168 2 nN N een 66 6 101 10 62066 DOH Lexicon
206. I O Extender cards P N 023 14426 e 9601 120V Power Cord Lexicon P N 680 09149 1 1 960L Multi Channel Digital Effects System Service Manual compatible personal computer capable of running Windows 95 98 minimum 200mHz Pentium Processor 128MB memory 4GB Hard Disk Drive SVGA Monitor Video card w 4MB memory Mouse 17 monitor Windows 95 Keyboard CD ROM Drive 3 5 High Density Floppy Disk Drive and Windows 95 98 Operating System 6 DE 9 Female to DE 9 Female RS 232 Serial Cable DE 9 Male to DE 9 Male RS 232 Null Modem Adapter e Female RS 422 Wraparound Plug see Chapter 5 for spec drawing PS 2 Keyboard or 102 104 key keyboard with PS 2 adapter e Optional e High Current Continuity Tester 10 100 milliohm Associated Research 5030DT or equivalent 1 15 Computer Monitor 1 PS 2 Mouse LARC2 Option Board Rev 1 Lexicon P N 023 14310 32MB PCMCIA FLASH Memory Card PCMCIA 2 1 Compliant 5 Volt LINEAR Flash PC Card Centennial P N FL32M 20 11736 J5 e External Power Supply 12VDC 5 5 mm O D 2 5 I D barrel connector with the positive voltage on center contact PowDec Model WI60 12V or equivalent Lexicon Chapter 2 General Information Periodic Maintenance Under normal conditions the 960L system requires minimal maintenance Use a soft lint free cloth slightly dampened with warm water and mild detergent to clean the exterior surfaces Do not use alcohol benzen
207. I Test Passed All test PASSED If it fails then the display will read MIDI Test Failed No data received One or more tests failed 7 To exit Diagnostics power off then power on the unit Listening Test Setup 1 Connect the two audio XLR male cables from the low distortion oscillator to Analog Inputs marked 1 and 2 on the back of the 960L 2 Connect the two audio XLR female cables from the Headphones Amplifier to the Analog Outputs marked 1 and 2 on the back of the 906L 3 Set the oscillator to 220Hz 2 5VRMS 4 9 960L Multi Channel Digital Effects System Service Manual 4 Turn the volume control on the Headphone Amplifier completely counter clockwise and plug in the stereo headphones 5 Poweron the 960L 6 Configure the 960L as follows Control Mode to Stereo Program load Bank 12 Halls then load program 1 Large Halls Verify Clean Audio 1 Puton Headphones 2 Press the Edit button on the LARC2 make sure the Mix Wet slider is set to Wet 3 Slowly increase the volume on the Headphone Amplifier unit it s at a comfortable listening level 4 Slowly sweep the oscillator across the audio frequency band and verify that no pops clicks static hash and breakup in the audio 5 Move the input and output cables to the next machine pair of the 960L 3 4 5 6 and 7 8 6 Repeatthe test for each paired output Shock Test 1 While still listening with the headphones Lift each corner to the 960L a few inches o
208. IGHT C 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File O htm REM REM Description This document is a script file that runs all available tests 6 18 Lexicon REM REM History 03 13 2000 rjs Created REM REM ML REM help REM Script 1 REM REM 960L Diagnostics Test Script COPYRIGHT C 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF THIS DOCUMENT MAY BE REPRODUCED ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 1 htm REM REM Description This document is a script file that runs all available tests REM REM History 03 13 2000 rjs Created REM 05 17 2000 clc modified to run all the system tests REM REM TimeDate cd Midi MidiTest cd cd Serial SerialTest 2 Reverbcardtests Dpramtest 0 0 Dpramtest 0 1 Z80BootTest 0 0 Z80BootTest 0 1 Z80DpramTest 0 0 Z80DpramTest 0 1 56kToZ80CmdTest 0 0 56kToZ80CmdTest 0 1 Z80To56kCmdTest 0 0 Z80To56kCmdTest 0 1 LexichipWcsTest 0 0 0 LexichipWcsTest 0 0 1 LexichipWcsTest 0 1 0 LexichipWcsTest 0 1 1 LexichipAdfTest 0 0 LexichipAdfTest 0 1 LexichipAdfTest 0 2 LexichipAdfTest 0 3 LexichipDramTest 0 0 0 LexichipDramTest 0 0 1 LexichipDramTest 0 1 0 6 19
209. IN 7805 5V REG TO263 ICSM LIN OPA2134 DU OP AMP SO8 ICSM LIN DRV134 BAL LINE DRVR ICSM FPGA XCS05 3 10X10 PLCC SPROM 960L AOUT V1 ICSM DAC AD1853 24BIT SSOP RELAY 2P2T DIP 5V HI SENS CONN EURO C ROW at b c MALE RA CONN XLR 3MC PCRA PLASTIC IC SCKT 8 PIN LO PRO TIN LUG 4 INT STAR XLR GND SCRW TAP 4X3 8 PNH PH BZ TRI PANEL I O AOUT 960L AES BD ASSY 960L 202 09794 202 09794 202 09871 202 09873 202 09897 202 09899 202 10890 202 11496 202 12365 202 12366 240 12136 241 09798 244 11589 245 10562 245 12485 270 11545 270 13572 270 14441 330 13866 RESSM RO 0 OHM 0805 RESSM RO 0 OHM 0805 RESSM RO 5 1 10W 1K OHM RESSM RO 5 1 10W 10K OHM RESSM RO 5 1 10W 470 OHM RESSM RO 5 1 10W 47 OHM RESSM RO 5 1 10W 220 OHM RESSM RO 0 OHM 1206 RESSM RO 5 1 4W 110 OHM RESSM RO 5 1 4W 22 OHM CAPSM ELEC 33uF 10V 20 CAPSM TANT 10uF 10V 20 CAP MYL 068uF 63V RAD 5 BOX CAPSM CER 150pF 50V COG 10 CAPSM CER 1uF 25V Z25U 2096 FERRITESM CHIP 600 OHM 0805 FERRITESM CHIP 200 OHM 0805 50 2 2 ICSM DIGITAL 74VHC244 SOIC QTY 00 PE Oi 29 29 N N N EFFalNACT 06 06 00 06 06 00m Lexicon REFERENCE D12 15 17 18 Q2 Q3 5 7 9 11 13 15 17 Q4 6 8 10 12 14 XLR J2 9 TO PANEL R1 36 37 39 40 42 R43 45 46 88 95 C48
210. IS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 5 htm REM REM Description This document is a script file that tests the MIDI Port REM REM History 03 13 2000 lt Created REM 05 17 2000 clc modified to run the REM Z80 SRAM and Wait Tests REM REM Reverbcardtests Z80SramTest 0 0 Z80SramTest 0 1 z80waittest 0 0 0 z80waittest 0 0 1 z80waittest 0 1 0 z80waittest 0 1 1 Script 6 REM REM 9601 Diagnostics Test Script REM COPYRIGHT 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF THIS DOCUMENT MAY BE REPRODUCED ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 6 htm REM REM Description This document is a script file that tests the MIDI Port REM REM History 03 13 2000 rjs Created REM 05 17 2000 clc modified to run the TMIX Tests REM REM 6 22 Lexicon REM cd Reverbcardtests TMIXHostPortTest 0 0 TMIXHostPortTest 0 1 TMIXHostPortTest 0 2 TMIXDspRamrTest 0 0 TMIXDspRamrTest 0 1 TMIXDspRamrTest 0 2 TMIXPingPongRamTest 0 0 TMIXPingPongRamTest 0 1 TMIXPingPongRam Test 0 2 cd REM Script 7 REM REM TTT REM 960L Diagnostics Test Script REM REM COPYRIGHT C 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF
211. K OHM 5 202 09899 RESSM RO 5 1 10W 47 OHM 9 202 10426 RESSM RO 5 1 10W 15K OHM 8 203 10583 RESSM RO 1 1 10W 10 0K OHM 16 203 12363 RESSM RO 1 1 10W 90 9 OHM 16 203 12477 RESSM RO 1 1 10W 13 3K OHM 8 203 13219 RESSM THIN 1 1 10W 422 OHM 8 203 13917 RESSM THIN 1 1 10W 40 2K OHM 16 203 13918 RESSM THIN 1 1 10W 4 02K OHM 16 203 14296 RESSM THIN 196 1 10W 6 49K OHM 16 203 14437 RESSM THIN 1 1 10W 13 3K OHM 32 203 14438 RESSM THIN 1 1 10W 2 74K OHM 16 240 09786 CAP ELEC 100uF 25V RAD LOW ESR 2 240 11111 CAPSM ELEC 47uF 6V NONPOL 20 16 240 11827 CAPSM ELEC 10uF 16V 20 24 244 10423 CAP MYL 22uF 50V RAD 5 BOX 4 245 10562 245 11596 CAPSM CER 150pF 50V COG 10 18 CAPSM CER 6800pF 50V COG 5 8 02 17 00 U6 J6 7 DSUB J9 10 TO PANEL J6 7 DIN J3 5 TO PANEL BNC J6 8 TO PANEL BNC J6 8 TO PANEL R1 10 17 24 R7 9 11 16 R2 6 12 15 R81 84 85 88 89 92 R93 96 R97 112 R33 48 82 83 86 87 90 91 94 95 R25 32 R113 128 R49 52 53 56 57 60 R61 64 65 68 69 72 73 76 77 80 R161 176 R129 160 R50 51 54 55 58 59 R62 63 66 67 70 71 74 75 78 79 7 8 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 10 13 14 17 18 21 22 25 50 58 61 62 65 66 69 70 73 2 3 5 6 1 4 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 35 36 39 40 43 44 47 48 PART 245 11625 245 12485 270 06671 270 09799 270 11545 300 11599 340 11573 340
212. LEDSM RED 100MCD 3 2X2 8MM 440 13906 FUSESM 75A RESETTABLE 18X 13 453 13916 SW PBM 1P1T 7MMSQ 160GF PCRA 480 13915 XDUCER PIEZO CER 2kHz 50MM LD 500 13908 CONN EURO R 96P abc PLUG VERT 510 03484 CONN DC POWER PC SMK S G9314 510 13902 CONNSM FFC 5MM 18POS PCRA 510 13903 CONNSM HDR 059 6P SHRD POL 510 13909 CONN MINIDIN 6FC PCRA SHLD GND 510 13935 CONNSM HDR 059 3P SHRD POL 510 13936 CONNSM FFC 5MM 20POS PCRA 510 14172 CONN DSUB 9MC PCRA 4 40SCRW 520 00941 IC SCKT 8 PIN LO PRO TIN 520 13901 IC SCKTSM PLCC 44 PIN W O LOC 530 12360 STRAIN RELIEF CABLE MSA XFRMR 640 01701 SCRW 4 40X1 4 PNH PH ZN 640 02812 SCRW 4 40X3 8 PNH PH BLK 640 14038 SCRW M3X4MM FH SLOT ZN SMHD 680 14241 CABLE 059 SCKT ST amp T 3C 3 1 4 L 701 09640 BRACKET KEYSTONE 621 4 40X2 701 14214 BRACKET FADER LARC2 702 14218 PANEL REAR LARC2 METER BD ASSY LARC2 202 09871 RESSM RO 5 1 10W 1K OHM 202 10586 RESSM RO 5 1 4W 100 OHM 202 11041 RESSM RO 5 1 10W 680 OHM 241 09798 CAPSM TANT 10uF 10V 20 245 12485 CAPSM CER 1uF 25V Z5U 20 310 10422 TRANSISTORSM 2N4403 SOT23 330 10535 ICSM DIGITAL 74AC273 SOIC 430 13900 LEDSM GRN 25MCD 3 2X2 8MM 430 14312 LEDSM RED 25MCD 3 2X2 8MM 430 14313 LEDSM YEL 15MCD 3 2X2 8MM 510 13936 CONNSM FFC 5MM 20POS PCRA 635 14036 SPCR SWAGE 0 80X1 4 1 8RD ZN QTY 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 3 5 N O N N EFFalNACT m07 24 00 Lexicon
213. M pgs Lexi le pa pa DRAM DRAM DRAM 1M x 12 1M x 12 1M x 12 Pg 10 Pg 13 Pg 12 10 BUS 2914 Figure 1 1 Reverb Card Block Diagram Circuit Description This section is a page by page description of the 960L Reverb Processor schematic PCI Bus sheet 1 The PCI bus is a 33 MHz 32 bit multiplexed address data bus that serves as the interface between the Reverb Card and the host Pentium processor The DSP 56301 provides an integrated glue less interface to the PCI bus including all of the configuration and address mapping registers Master and slave modes are supported The Reverb card requires 12V 5V and 3 3V 56301 DSP Microprocessor sheet 2 The 56301 operates at 3 3V which is provided by the PCI connector The 56301 is clocked from an external 6 MHz crystal Y1 sheet 2 and the on chip PLL is used to generate 80 MHz clock which is output as DSP CLKOUT The reset control chip U37 creates a reset pulse with a minimum duration of 20ms as required by the 56301 The Once Port is used for development and is not populated for production cards The 56301 moves samples to from the T MIX devices and its internal memory using the DSP bus which appears on the right hand side of the chip symbol The DSP56301 has internal address decoders that are 7 33 960L Multi Channel Digital Effects System Service Manual used to generate the AA1 AA2 and AA3 chip select signals These add
214. NE 18 8 gt OU sooo 2 gel gt E C3uvdSv L 10 02166 4 v 00 020166 490 00 20166 JOC 2 00 82 066 5 SNOISIA38I 5 L 2 S 9 4 6 408 66720 Wd qanssi aly 60661 090 g 60000 20 3000 325 682 THO v 391 590123 02 808480 1 6892 wg 7096 XIN waHos ava SUN 06 10 VW AYYd AVO u ON Li sa Lol cen L aa L zl sen ozh con oz azl seul al say L d ELIP 927 680 T 880 T S60 T 9604 169 T 060 Te 169 T 969 139010 T 019 207 9019 Ti 501 1 8 4 4 1 8 sio 60 1 60 9019
215. OG 4ol W 9661 00 9 BOS NEE 0 1 OL 049 XN 7 81 OSXZ DIOS DIOS OL 980 90 v1 089 SION XIN OL MS 13538 1 91 O MS DIOS 690 069 089 7 148 XIN OL MS 1 91 Or 0319 5 1905 660 18 2 9007 089 i XIN Ol NO 1 6 200 2 1995 1405 OL 318VO lt 0071 089 70 799 XIN OL 30 Add014 1 9 0LLXC DIOS DIOS OL 318vO 06661 089 766 XIN OL WOY 09 1 9 200 2 DiOS DIOS 21872 16661 089 ec XIN OL 798 0 1 2 2002 1405 1405 31872 06661 089 LE 0 1 OL 08 IGIN 1 81 OG dsi8Q dO3N 4182 68671 089 9 0 1 OL X1 1 81 26 s630 dO3H MAYO 8866 089 756 14044105 4015 OL 4015 MHL 26 1 X do 8 6 X 19 9 4 HSM 9810 09 dj OL 1988 dOlS 2 O LAN 00080 59 1 1804405 4015 OL 4015 1888 OL XIN SISSVHO OL dnS Md 6 NZ d34 5 9 LAN 80 10 299 of IN OL 5198008 78 Hd Hd 8 X av MYOS 901 199 60 1 O8 IGIN 2 91W NZ Hd HNd v L X MYOS 60 10 199 82 47 SISSVHO OL IN NOVY 9 78 Hd HNd 2 1 26 01 MYOS 9661 09 92 9 5391933 AINO WLS Z I3Nvd 81091 20 21 9 Ol 1498 91 78 HNd NWOXEW MYOS 86 01 099 GT 9 WVOJONOO 133599 vObvl 0ZL lL 2 OL 8 X19 OL 148 XIN IGIN 124 ASSY 808 16091 08
216. OM 27256 960L RVB V1 00 350 14365 ICSM GAL 16V8 960L TMXSEL V100 350 14366 ICSM GAL 16V8 960L 56KDEC V 100 350 14367 ICSM GAL 16V8 960L 56KSTB V100 350 14368 ICSM GAL 16V8 960L LXCTL V100 350 14369 ICSM GAL 16V8 960L LXSTB V100 350 14370 ICSM GAL 16V8 960L ZLXIF V100 350 14371 ICSM GAL 16V8 960L ZLXCLK V 100 365 09883 ICSM uPROC Z80 CMOS 10MHz QFP 365 12047 ICSM uPROC TMIX 144PIN TQFP 365 12315 ICSM uPROC DSP 56301 80MHz 390 12075 CRYSTALSM 6MHz PAR 18pF 390 12427 CRYSTAL OSCSM 50MHz 430 10421 LEDSM INNER LENS GRN 640 01701 SCRW 4 40X1 4 PNH PH ZN 701 13970 BD LEFT 960L 701 13971 BD RIGHT 960L BO GQ N N N G NLX CPU BD ASSY 640 02704 SCRW 6 32X1 4 PNH PH BLK 2 701 14307 BRACKET SUPPORT NLX CPU 960L 1 701 14311 SHIELD I O NLX CPU 9 3X1 9 H 1 750 14030 PCB ASSY NLX CPU 2DIMM 10X8 25 1 750 14032 MODULE SDRAM 32MB 100MHz 1 750 14033 CPU KIT CELERON 300MHz PFANHS 1 NLX BPL EXT BD ASSY 960L 500 13944 CONN EDGE 2X60C 050 VERT PCI 2 510 13336 CONN POST 100 HDR 2X32P LK RA 2 640 01701 SCRW 4 40X1 4 PNH PH ZN 6 701 13970 BD LEFT 960L 1 701 13971 BD RIGHT 960L 1 BPL EXT BD ASSY 960L 500 05855 CONN EURO C ROW a b c MALE RA 1 500 14427 CONN EURO R 96P abc RECP RA 1 510 13336 CONN POST 100 HDR 2X32P LK RA 2 Lexicon REFERENCE D9 10 U45 040 42 46 48
217. ON 88804 i 80 lore eae OI 18 09352 Linoas 9 007804 SUNN esl lewe w D W no noz lt 5211852 Tert LN DIG 8 TONO ZZ 65 W Gaul a 7 vi gg W N 002 AE W m NI 82 8 00254 SW YEZ d vl M WIS E Seo nod V YAZ aue WEES 88 NIS3ZIS EVE 16 0 ENV dn 0782 ood 043 6 ee 70302 TS Odd 00302 1 5 2 80ld VW 4 eaen 1848 HAS OF PAG 11082154 dNOGY 0 808 ANHE least 896 170792992 nores oos 25 016177114 001005 011005 No TIO HEE Ta ONIS WHS 10 8335 e512 ULNOOM Wee N DM paT 18001 310848 114 080 MON S 1 NEAL NI WON AN i 2 OONISI Td E Ta re 10 0 us OX N no a 5 siaav 1 aw GOL OL e AM ENUI EE xav awoov VENE nsvox u 2 WEE sd N ASvOx 9 vol
218. OOTOGYOM ILL TVN3J31X3 40 10 1 3900 L 3400 1 29 WOT PEN lt onan Be ON OF ON vOGENZ e 9997 Si oz 0183 684 0 t z ANdLNO IAIN ERIS Wu 2 k 0 oz 3an z zn Iam 10901d9H S3uvds AHL IAIN i Nrd eani p 00 04466 1 SOHO SNOISIA3H Lexicon 3 z v 9 9 4 02 n 6620 wrd 8 8 2920 a wm waawnn aaoo 6820 WO3 gy 2 S N39 30010 66120 HMY 7096 08710 N3H29S ul aa STWAOuddY OEZLO VW avd uoo ON SRL ovr SAL NYO y 10 001 XL ovr OL Tak ano zr Y 0 5 PA vn j 1 3124261922 T
219. OS settings Pressing together and holding for 2 seconds the PROGRAM and MACHINE buttons on the LARC2 immediately after powering on the 960L enters the diagnostics When the LARC 2 displays Requesting Menu Mode from 960L the buttons can be released In approximately 1 minute 30 seconds the LARC2 will display the following boot menu 960L Boot Menu Version X XX Speed XXX MHz BIOS 11 22 99 1 Run 960L 2 Update 960L Software 3 Update LARC2 Boot ROM 4 Update LARC2 Software 5 960L Diagnostics Can t lock CD Drive Access is denied The Version refers to the latest version of the boot menu that is running The current version is 1 00R however this may change without requiring this document to be updated The speed refers clock speed of the Celeron processor This value is 1 3 MHz below the actual value So a value of 398 MHz would actually be a 400 MHz Celeron The date after the BIOS refers to the date of the Intel SU810 BIOS Currently version 5 of the BIOS dated 11 22 99 is the version required running on the 960L Pressing the 5 button on the LARC2 enters diagnostics The display will appear similar to the sample below on the LARC2 upon entering the diagnostics Lexicon 960L Diagnostics Version X XX MM DD YYYY HH MM SS kkkkkkkkkkkkkkkkkkkkkkkkkkkkk Chameleon Configuration kkkkkkkkkkkkkkkkkkkkkkkkkkkkk VxD Version 6A Num Cards 1 Card 0 Configuration Config Valid YES Subvendor ID 4863 56301 ID
220. P N 021 14511 Removal and Replacement of Larc2 Piezo Transducer For units with the transducer soldered Rev 5 PCB and up Removal 1 Wick the solder from the transducer and the PCB solder pads 2 Re flow the remaining solder while gently lifting the transducer edge with an X acto blade Replacement 1 Prep the PCB solder pads as needed 2 Assemble the transducer as outlined in the assembly notes on DWG 080 14234 ASSY DWG MECH MAIN BD LARC 2 3 Solder the transducer to the six pads provided NOTE Solder the pads alternately across from each other to minimize overheating of the transducer For units with the transducer epoxied Rev 4 PCB and below Removal 1 Gently insert the blade between the PCB and transducer to pry it loose from the 5 minute epoxy 5 1 960L Multi Channel Digital Effects System Service Manual Replacement 1 Assemble the transducer as outlined in the assembly notes on DWG 080 14234 ASSY DWG MECH MAIN BD LARC 2 Lexicon Female RS 422 Wraparound Plug Female RS 422 Wraparound Plug Solder Side View Female DB 9 AmphenolP N 17S DE 9S Instructions Using 24 buss wire or equivalent solder pin 2 to 8 and pin 3 to 7 5 3 960L Multi Channel Digital Effects System Service Manual Male RS 422 Wraparound Plug MALE RS 422 Wraparound Connector Solder Side View Male D Sub 9 Pin Amphenol P N 175 095 Instructions Using 24 28 AWG buss wire or equivalen
221. Perform normal Boot Enter Request Menu process Establish Option Board Mode from the communications Menu 960L Mainframe w 960L Mainframe Looking for 960L 6 32 DIAGNOSTICS The following section describes the operation of the Interactive Diagnostic Tests Lexicon There are two ways that the Interactive Diagnostics menu mode can be invoked they are as follows 1 Press amp hold the PROGRAM ENTER keys while powering on the LARC2 then releasing the PROGRAM ENTER keys when a chase pattern appears on the Meter Board and Keypad LED s 2 Install the Female RS 422 Wraparound Loop Back Plug into the connector labeled HOST on the LARC2 rear panel then power on the LARC2 NOTE Do not touch any of the faders until the power on diagnostics test results have been checked Touching the faders will clear the power on diagnostics test results displayed on the Meter Bd LED s NOTE If any of the Red or Yellow LED s on the Meter Board remain lit a diagnostic error has occurred NOTE When the LARC2 has entered the Interactive Diagnostics menu mode the Fader Touch and A D converter information for the fader being touched and or moved is displayed on the Meter Board LED s The Red LED s 1 8 indicate which fader 1 8 is being touched respectively The Yellow LED s act as a level meter which displays the value read from the A D converter of the fader being touched and or moved 17Min 8 Max
222. R 0x2301 DB Lexichip Lexicon DB Version 2 Card Info Card 0 Clock Version X Card 1 unknown Card 2 AES Version X Card 3 Analog In Version X Card 4 Analog Out Version X Press 0 for a list of tests gt The text below Card 0 Configuration verifies that a reverb card is present and be identified by the diagnostics After that the cards in the cage are identified At this point if the reverb card cannot be identified look at the 4 leftmost LEDs on the reverb card They should be lit If the LEDs are not lit correctly then the reverb card has a problem If the reverb card has this serious a problem that it cannot be initialized then the most likely problem is with he 56301 and associated circuitry If the cards are all recognized then the diagnostics can be run There are 10 sets of diagnostic scripts available with the 960L In addition custom scripts can be written and run from the floppy drive The 10 built in scripts are run by pressing the numbered button corresponding to the script desired to be run and then pressing the ENTER button For a description of the scripts and their operation see the section labeled Functional Diagnostic test Scripts Audio I O Algorithm 8 In 8 Out The audio data must be generated from an external source such as an Audio Precision The audio program is provided in the audio preset program with the parameters modified to produce a dry signal
223. RC2 1 BOX 17 1 2X12 3 4X9 LARC2 1 INSERT FOAM LARC2 LEFT 1 INSERT FOAM LARC2 RIGHT 1 CERTIFICATE CE 1100 DR LARC2 1 LABEL LEXICON DIG AUDIO 3 X5 2 POWER CORDS 680 09149 680 08830 680 10093 680 10096 680 10097 680 10094 680 10095 680 10098 SHIP MAT L PACKAGING MISCELLANEOUS 070 14353 070 14354 541 00780 1730 04346 730 09 730 14316 730 14350 730 14352 730 14516 740 07693 750 14300 8 14 CORD POWER IEC 10A 2M NA SVT 1 CORD POWER IEC 6A 2M EURO 1 CORD POWER IEC 5A 2M UK 1 CORD POWER IEC 6A 2M AUSTRALIA1 CORD POWER IEC 6A 2M JAPAN 1 CORD POWER IEC 6A 2M ITALY 1 CORD POWER IEC 6A 2M SWISS 1 CORD POWER IEC 6A 2M UNIVERSAL1 MANUAL OWNER S 960L NOTICE S W RELEASE 960L BUMPER FEET 3 M 5 5023 CARD WARRANTY LEXICON 8 5X11 CARD REGISTRATION GENERAL CERTIFICATE CE 960L LARC2 24 22 3 4 11 1 2 1 LEXICON INSERT FOAM 4UX17 5 LICENSE AGREEMENT END USER LABEL LEXICON DIG AUDIO 3 X5 CD 960L V1 05 fh REFERENCE R10 18 R1 3 RQ C26 28 30 32 C1 10 13 14 19 25 C27 29 31 J1 PCMCIA SCKT MTG PCMCIA SCKT MTG 50 CABLE Lexicon Spare Assemblies PART NO DESCRIPTION QTY EFFalNACT REFERENCE 021 14500 PL SHIP NLX BPL TESTED 960L 021 14501 PL SHIP I O BPL TESTED 960L 021 14502 PL SHIP I O CLK BD TESTED 960L 021 14503 PL SHIP AIN BD TESTED 960L 021 14504 PL SHIP AOUT BD TESTED 960L 021 14505 PL SHIP AES BD TESTED 960L 021 14506 PL SHIP RVB BD TESTED 960L
224. RW 0 OSC DRIVES BNC Active High When set the BNC Output is derived from local 48K oscillator For test purposes only The purpose is to loop the BNC OUT to the BNC IN and attempt to lock to it This confirms that the BNC input and output paths circuits are functional CTLREG 6 RW 0 SEL 1X CLKMODE Active Low Set to zero for 44 1 48K else one for 88 2 96k 5 4 RW 0 WCKSEL 1 0 System Word Clock Source Select WCKSEL 1 0 0 Selects 48 96 Khz internal oscillator as word clock source WCKSEL 1 0 1 Selects 44 1 88 2Khz internal oscillator as word clock source 2 Selects EXT BNC signal as word clock source 3 Selects Backplane SLOT as word clock source WCKSEL 1 0 WCKSEL 1 0 CTLREG 3 RW 0 Preview Word Clock Select PVW SEL 70 Selects EXT BNC clock as this board s preview word clock source PVW_WCK_SEL 1 Selects the current SLOT as this board s preview word clock source CTLREG 2 RW 0 PWCLK EN Active High Preview word clock enable When asserted this board s selected preview word clock will be asserted onto the PREVIEW WCLK pin on the IO Backplane Care must be taken so that no more than one PCB on the IO backplane asserts it preview workclock onto the backplane CTLREG 1 RW 1 XTAL_EN Active High Enables XTAL Oscillators This must be asserted to use osc s as internal clock source CTLREG 0 w 0 TESTMODE Active High For development purposes only When enabled OSC s drive system cloc
225. Register 0x1000 0000 Static Bank Select 2 LARC2 Registers 0x0800 0000 Static Bank Select 1 8 Mb Flash 0x0000 0000 Static Bank Select 0 Boot ROM Table 2 1 LARC2 Memory Map The bottom partition 0 0000 0000 to Ox3FFF is dedicated to static memory devices ROM Flash 5 and to the PCMCIA expansion bus area This space is divided into four 128 M byte blocks for static memory devices and two 256 Mbyte blocks for PCMCIA The next partition 0x4000 0000 to Ox7FFF FFFF is reserved Accessing this reserved space results in a data abort exception The third partition 0 8000 0000 to OXBFFF FFFF contains all on chip registers This block is further subdivided into four blocks of 256 M bytes each They contain the control registers for the major functional blocks within the chip The LCD and DMA controllers occupy the top 256 M byte partition The fourth partition 0 000 0000 to OxFFFF FFFF contains DRAM memory The bank sizes for DRAM are fixed at 128 Mbyte each The next 256 Mbyte block in this partition is mapped within the memory controller and returns zeros when read This function is intended to facilitate rapid cache flushing by not requiring an external memory access to load data into the cache Writes to this space have no effect The top 384 M byte of this partition is reserved Accessing this space causes a data abort exception Reset Controller U5 sheet 1 When power is applied U5 DS1233 asserts RESET and m
226. S 55 240 Lat n BOG vos mnn ES Wiad x S 0249 dia vor 881 6149 6199 58 5 S giao ONVW D leet gt a 251 949 uva er 6305 Siu tS Ead 630 8 SN 69 849 5 8301 254 OL 5305 mae LEES be ir ise 6307 1031649 I 2 uai 630 003199 tH 189 L c 6 02 vr Eur 51449 L JASE 7 SL 91901 ONION NOSE HENAN 133HS I9HOSIS Mod is 549 d seus Ley 6L 1 090 40078 0H1NOO 1N3Nn200 Od 1351959 130d vioWod od P 8 E ZA ZM LN IMS OP x 0 154 11 Lar 70184 810 03801 SYOLYNOISIO 19 1 2 Q3TIVISNILON x HLM SIN3NOdWOO 9 133HS satoNaa ouod s 98000 p amod SSSvHo F DOWNY Y x CE EX 07 SHOLIOWdYO GALVOIGNI 88511 cou i TOv 8 50195 35 T31VOIONI 3SIMBHIO SSTINN Z corr 25 JAV SSM T I 880 Vox S310N ud TAS nn uo oX TOL lt HO We 34430 Ion D 01 om San sor 1031409 AHOWSN xor 998 5 2 ot gza sza 020
227. S WCLK IOBUS 64 5 and IOBUS 256FS are not used Ancillary clocks for charge pumps are also derived from TMIX VBOSCU VBOSCD and VCCOSC see below 125 FS and 125 64FS scale with sample rate FS 7 23 960L Multi Channel Digital Effects System Service Manual 125 256 5 is the master clock to the D A converters and is 256FS in single speed mode and 12825 in double speed mode Source resistors in the clock lines reduce ringing due to reflections to provide proper clocking Digital Audio Interface Audio data flows between the IO cards e g Analog Input Analog Output AES on the IO backplane and TMIX chips located on DSP e g reverb cards on the NLX backplane over high speed serial audio channels called octals TMIX chips define the octal format and timing The bit rate of an octal is either 11 2896 Mbps for a 44 1Khz word clock or 12 288 Mbps for a 48Khz word clock An octal channel contains eight time slots Each time slot can carry a 24 bit sample with up to 8 bits of status per sample Note that the TMIX interface does not directly support double speed sampling rates Octal serial digital audio from the backplane appears on 6 pins of U1 as 3 distinct pairs of channels A controllable multiplexer implemented within interface U1 selects one pair of these octals to be the digital source for analog output The octal pair selection is determined by the state of the octal select field in the CTLREG register within U1 Within
228. SLOT_WCLK 25 PLL_512FS 29 48K_512FS 24 44K_512FS 43 44 2 1 WCKI 2 256FS 3 128 5 4 64FS 5 5 19 WCLK OUT 6 PVW WCLK PLL Signals 22 PUMP UP 20 PUMP DN 26 LKERRDET 27 PLL LOCKED Type INPUT OUTPUT INPUT INPUT INPUT INPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT Description Not used Not Used CHIP SELECT 0 this slot is being selected 1 not selected DATA STROBE data is captured on rising edge of DS WR RD 0 write operation 1 read operation Address 0 select which register is written read to from see register description section Data Bus lt 7 gt data is written read over this bus Data Bus 6 data is written read over this bus Data Bus 5 data is written read over this bus Data Bus lt 4 gt data is written read over this bus Data Bus 3 data is written read over this bus Data Bus 2 data is written read over this bus Data Bus 1 data is written read over this bus Data Bus 0 data is written read over this bus External BNC wordclock input Wordclock from another slot on the IO backplane PLL master clock The frequency of PLL 512FS is 512 times the WCKI rate Nominally 24 576 or 22 5792Mhz Local 24 576Mhz oscillator
229. SM DIGITAL 74LVC16245A TSSOP ICSM DIGITAL 74LVC162244 TSSOP ICSM DIGITAL 74HCT74 SOIC ICSM LIN LM393 DUAL COMP SOIC ICSM LIN LM317M ADJ REG DPAK ICSM LIN LM358 DUAL OPAMP SOIC ICSM LIN LM3940 5 3V REG TO263 ICSM LIN LM2676 5V REG TO263 ICSM LIN ECONORESET 3 3 SOT223 ICSM LIN L293 4CH DRVR SOIC ICSM LIN LM2941C ADJ TO263 ICSM INTER 75ALS180 DR RC SOIC ICSM DRAM 4MX16 60NS TSOP ICSM FPGA XCS10XL 4 14X14 TQFP ICSM FLASH 2MX8 3V 90NS TSOP QTY 1 1 2 1 1 2 4 4 1 3 8 99 BRAM A E ARPA BOR E BO lt N N N R35 C90 92 150 153 C39 5 9 62 91 98 100 106 107 113 114 120 11 18 27 29 152 93 96 101 104 108 111 115 118 1 2 34 35 37 38 94 97 102 105 109 112 116 119 C3 4 7 12 13 16 19 26 28 30 33 36 40 61 63 89 95 103 110 117 121 140 142 144 146 148 149 151 10 5 6 4 7 9 1 2 L1 U9 D9 13 23 24 D1 2 15 22 04 7 8 025 Q4 6 9 Q1 2 7 8 U6 U1 U24 U23 U15 19 21 22 U32 35 U10 13 14 16 PART _ DESCRIPTION 350 14374 IC SPROM LARC2 MAIN V1 00 350 14375 ICSM FLASH 1M LARC2 BOOT V1 00 355 13929 ICSM ADC TLV1548C 10b SSOP 365 13930 ICSM uPROC SA 1100 160MHz TQFP 390 12733 CRYSTAL OSCSM 2MHz TRI 390 13932 CRYSTALSM 32 768kHz PAR 390 13933 CRYSTALSM 3 6864MHz PAR HC49 430 10419 LEDSM INNER LENS RED 430 10421 LEDSM INNER LENS GRN 430 13914
230. TMIX 2 octals 2 amp 3 to TMIX 1 octals 10 amp 0 TMIX 2 octals 8 amp 9 to TMIX 1 octals 2 amp 3 TMIX 2 octals 10 amp 11 to TMIX 1 octals 11 amp 1 Reverb card Introduction This section describes the theory of operation of the 960L Reverb Card Overview The 960L Reverb Card is a 128 channel 24 bit audio DSP processor that is the central DSP resource in the 960L system Up to three of these cards can be inserted into the PCI bus for mixing effects and other processing needs The card has four Lexichip reverb processors which are controlled by two 7 80 microprocessors Audio mixing and the host interface are implemented with a Motorola 56301 DSP microprocessor Digital audio data is transferred to and from the card via the 960L bus by two T MIX serial audio engines ASICs The host Pentium microprocessor controls the peripheral cards the 960L by sending commands through the Reverb card to the I O bus A third T MIX ASIC is used to transfer serial digital audio to and from the four Lexichip III chips The 56301 reads and writes audio samples to the T MIX devices via a high speed 24 bit data path Figure 1 1 is a block diagram of the 960L Reverb Card 7 32 Lexicon PCI BUS e 1 ONCE 8 PORT DSP56301 BOOT T SAMP_DATE31I 245 2244 Host Port DSP Pol HostPort USP Pol TMIX 3 TMIX 2 Li Dual Port RA
231. TMIX Octal data Received from TMIX2 Octal 10 Octal selection is determined by the octal select field in the FPGA control register see register description for details 10 SDO5 INPUT TMIX Octal data Received from TMIX2 Octal 11 Octal selection is determined by the octal select field in the FPGA control register see register description for details Audio Control 44 DEEPMH OUTPUT Deemphasis control Enabled when asserted 1 39 RLY_MUTE OUTPUT Relay Mute Control Analog outputs are muted when asserted 0 27 DAMUTE OUTPUT DA Mute Digital output from DA is muted when asserted 1 28 DAC_RST OUTPUT DAC reset All DACs are reset when asserted 0 26 96K_EN OUTPUT 96K sample rate enable DACs operate in 2x 88 2 96K sampling mode when asserted 1 Charge Pump Support 38 36 VBOSCU VBOSCD OUTPUT Charge pump clock signals 58 VCCOSC FPGA Support 32 MODE INPUT MODE Serial download interface mode signal Nomimally zero for loading from external SPROM 55 PROG INPUT FPGA Program 0 causes the FPGA to reload its program from the external SPROM 73 Serial clock signal 53 DONE OUTPUT FPGA DONE Asserted when FPGA program cycle has completed 41 INIT OUTPUT FPGA serial download initialization signal 71 DIN INPUT FPGA configuration data from SPROM 15 16 TDI TCK TMS INPUT JTAG Interface Not used 17 75 TDO OUTPUT JTAG Interface Not used Power Supply Power conditioning for the Analog Output
232. U20 Unwanted hum and noise at the input are unlikely to reach such high levels but for a single ended input half the signal is common mode at this level A D Converter A D converter U4 AK5393 is powered on its VD pin by the main 5VD system power from the backplane and on its VA pin by higher quality 5 regulated on board by 03 Power is decoupled by ferrites FB4 and bypassed by C10 11 12 13 The channel 1 analog input is applied to the left stereo input AINL The associated internally developed reference voltages VREFL and VCOML are filtered by C37 51 27 U4 operates its serial digital audio port 125 mode SMODE 2 1 1 0 U4 receives 125 framing and bitclock ADLRCK and ADSCK12 from interface fpga U1 sheet 4 and delivers two channels of 24 bit serial digital audio back into U1 AD12 SDO carries channel 1 and 2 data as left and right respectively Master clocks to the four A D chips are distributed on separate lines from one pin of U1 MCK12 connects to 04 the converter for channels 1 and 2 Two A D logic inputs are under the control of host software via the U1 interface CONV RESET and DFSO are applied to all four A D chips in parallel DFS1 connected to the TEST pins is grounded by 0 ohm jumper R1 Signal Polarity There are no inversions in the analog signal path so a positive voltage between J2 2 and J2 3 appears as a positive differential signal between AINL and AINL and produces a positive digital value fed in
233. V supplies Within the PLL 5VA is decoupled at multiple points with ferrites and bypass capacitors Phase Frequency Detector The PFD implemented within CPLD U2 is a well known edge detector type which compares the phase and frequency of two logic signals and detects zero error at zero phase Here the PFD inputs are the selected reference wordclock and the single speed wordclock derived from the VCO both of which exist internal to the CPLD If the VCO frequency is too low or too high the PFD drives output pins of the CPLD with a train of mutually exclusive PUMP UP or PUMP DOWNY pulses respectively As the VCO frequency changes to approach lock one train of pulses of varying width is generated When the frequencies are essentially equal the pulses depend on the phase error between the two wordclock rate signals If the wordclock from the VCO lags the reference due to approach from a lower frequency PUMP UP is generated and PUMP DOWN remains inactive The opposite is true when approaching from a higher frequency In an ideal PFD of this type when the edges of the two wordclock waveforms within the CPLD are exactly in phase neither pulse would occur the zero error phase lock condition occurs when the edges are coincident In the basic PFD if the reference signal drops to zero frequency i e is absent the logic would assert PUMP DOWN constantly to try to force the VCO frequency to zero to match the reference prevent this special log
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237. a cache 512 byte mini data cash that allocates data based on the MMU 4 entry read buffer and an 8 entry write buffer Integral memory management unit MMU The logic outside the core and caches is grouped into the following three modules Memory and PCMCIA control module MPCM Memory interface supporting ROM Flash DRAM SRAM and PCMCIA control signals System control module SCM Twenty eight general purpose ports interrupt capable Real time clock watchdog and interval times Power management controller Interrupt controller Reset controller Two on chip oscillators for connection to 3 686 MHz and 32 768 kHz crystals Peripheral control module PM Six channel DMA controller Gray color active passive LCD controller 230 Kbps SDLC controller 16550 compatible UART IrDA serial port 115 Kbps 4 Mbps Synchronous serial port UCB1100 UCB1200 SPI TI uWire Memory Map Table 2 1 shows the memory SA 1100 memory map The map is divided into four main partitions of 1 Gbyte each 0000 Reseved 7 0000 Zeros Bank lt C 0x8000 0000 Internal Registers 1 18 27 0 4000 0000 Reserved 2 2105 06 22 0 3000 0000 PCMCIA Socket 0 8 Mb Flash alternate 0x2000 0000 PCMCIA Socket 1 Optional PCMCIA Socket 7 40 Lexicon Base Address SA 1100 LARC2 0x1800 0000 Static Bank Select 3 Configuration
238. ace Audio data flows between the IO cards e g Analog Input Analog Output AES on the IO backplane and TMIX chips located on DSP e g reverb cards on the NLX backplane over high speed serial audio channels called octals TMIX chips define the octal format and timing The bit rate of an octal is either 11 2896 Mbps for a 44 1Khz word clock or 12 288 Mbps for a 48Khz word clock An octal channel contains eight time slots Each time slot can carry a 24 bit sample with up to 8 bits of status per sample Note that the TMIX interface does not directly support double speed sampling rates Within U1 the four 125 stereo streams from the converters are merged into a pair of octal serial digital audio channels at 11 2896 or 12 288 Mbps to feed A D input into the system via the backplane At double speed sampling rates 88 2 96Khz each octal carries 4 audio samples during each 125 word clock period so a pair can carry all 8 samples Within a pair samples from odd numbered input channels lefts are split off and carried by one member of the pair TMIX1 SERDO 2 10 even numbered ones rights by the other TMIX1 SERD 1 3 11 This division is the same at single speed rates and so is the bit rate but fewer actual input samples are being provided by the converters After a group of 4 samples has been clocked out at high speed the next word clock has not occurred and there are not yet any new samples to follow In this case the FPGA hardware repeats
239. actual data is then written to the Data Port which the TMix writes to the appropriate Host Register using the address in the Pointer Port Confirming that the Pointer Port is working properly would require setting specific Host Registers then checking to make sure that the TMix operating mode changed appropriately The Host Ports on the three TMIX s in the system are at the following addresses in 56301 memory space TMix 1 Pointer Port 0 902000 Data Port 0 902001 TMix 2 Pointer Port 0 903000 Data Port 0x9D3001 TMix 3 Pointer Port OX9D4000 Data Port 0 904001 Parameters This number selects which reverb card to test Legal values 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 TMixld This specifies which TMix on the card to test Legal Values are 0 1 and 2 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running TMIX DSP RAM Test The syntax for the TMIX DSP RAM Test is TMixDspRamTest Cardid TMixID NumRepeats This tests the 563015 ability to access the DPRAM a TMIX chip test begins by filling the memory space under test with a specific data value then reading back the contents of each memory location confirming the data contained therein is correct Values of 0
240. al pole in the overall filter characteristic Power 026 VCC is derived from capacitive charge pumps which augment the 12V system supplies to 18V nominal unregulated sheet 7 see below The higher voltage accommodates a modest common mode output voltage arising from some degree of load imbalance or an equivalent external source of output common mode voltage while providing the supply current necessary at program peaks With a perfectly balanced load each output leg referred to common is 18dBu full scale 8 7Vpeak around 5 6V below clipping The output can therefore tolerate up to several volts of peak common mode voltage regardless of how it arises Note that the output driver cannot produce full 24dBm level if the output is wired for single ended unbalanced operation with one leg grounded as this would result in a common mode voltage of 18dBu corresponding to a peak output voltage greater than 17V beyond clipping level If grounded unbalanced wiring is employed the maximum digital signal that can be accommodated is around 2 dBFS Mute Relay RY1 in the normally closed position mutes the differential output by grounding pins 2 and 3 of XLR connector J2 When energized under software control RY1 connects J2 to the active output circuitry 7 22 Lexicon Relays for each pair of channels are energized by one transistor when software sets RLY_MUTE to a high logic level Signal Polarity A positive digital value en
241. ale differential signal at U8 is 7Vp p If the input is single ended the driven side of U20 develops 8 7 and U16 output swings between about 1 3 and 7 volts to balance the differential input to U8 which is still 7Vp p 08 drives the differential A D converter input through a low impedance attenuating RC filter network consisting of R33 R26 R34 and C36 The network scales 7Vp p signals down to 4 9Vp p to match the nominal fullscale input level of the converter so digital fullscale corresponds to 24dBu at the input connector The single pole 180kHz lowpass filter attenuates energy at the 128FS A D sampling frequencies by gt 55dB while passband response is flat within 0 2 to 40kHz Common Mode Performance Good common mode rejection requires well matched gains at the two input buffers and on boths sides of the summing balancing network where unequal common mode gain on the two signal paths can convert a common mode signal to an apparent differential mode signal Precision 0 196 resistors are used as appropriate to ensure that the minimum common mode rejection ratio of the input circuitry is better than 45dB Other resistors affect differential gain but not common mode rejection and 1 precision is sufficient 7 15 960L Multi Channel Digital Effects System Service Manual With a full scale signal the allowable additional input common mode voltage range is at least 18dBu 8 7Vpeak limited by the clipping level of
242. alled The following Meter Board LED s will be turned on to indicate the three errors that have been detected as shown in the table below LED 4 2 3 4 5 46 7 48 6 28 Lexicon Red 0 0 0 0 0 0 1 Yellow 0 o o 1 1 0 Green 11111111 0 1 1 YELLOW 6 LED was turned to indicate Keyboard Test failure because the External Keyboard was not detected 2 The YELLOW 7 LED was turned on to indicate a Loop Back Test failure because the RS 232 Wraparound Plug was not detected 3 The RED 8 LED was turned on to indicate a Keystuck Test failure because the PROGRAM ENTER keys were being held Prior to the execution of the Power On Self Tests the Realtime Clock is tested This test verifies the operation of the 32 768kHz crystal the SA 1100 TEST 1 Motor Waveform Registers Test This test writes to control registers in SA 1100 then verifies the value written can be read TEST 2 Motor Control Registers Test This test writes to control registers in SA 1100 then verifies the value written can be read TEST 3 A D Control Registers Test This test writes to control registers in SA 1100 then verifies the value written can be read TEST 4 A D Self Test This test reads the MIN MID and MAX values based on the reference voltage of the A D converter TEST 5 Not Used TEST 6 External PS 2 Keyboard Test This test initial
243. be 11 5 VRMS 1 5V Move the audio output cable to the 2 Output and repeat the test Repeat the test on the remaining Input Outputs pairs 3 4 5 6 and 7 8 DPN Frequency Response Analog In to Analog Out Frequency Response Test Note Change the Clock Source to Internal and Inputs to Analog see Audio Functional Tests Setup 1 Disable all filters on the distortion analyzer 2 Connect a balanced XLR audio cable between the low distortion oscillator and the 960L 1 Audio Input Connect a balanced XLR audio cable between the 960L 1 Audio Output and the distortion analyzer Apply a 1kHz sinewave 2 45 VRMS Set the Analyzer for reference 1khz Sweep the oscillator from 20Hz to 20kHz and verify the level is 1dBr throughout the sweep Repeat the test on the remaining Input Outputs 2 8 NOR Analog To Digital Out Frequency Response Test 1 Disable all filters on the digital distortion analyzer 2 Connect a balanced XLR audio cable between the low distortion oscillator and the 960L 1 Audio Input 3 Connect a balanced XLR audio cable between the 960L 1 2 AES Output and the digital distortion analyzer Apply a 1kHz sinewave 6 90 VRMS Set the Analyzer for a OdB reference 1khz Sweep the oscillator 20Hz to 20kHz and verify the level is 1dBr throughout the sweep 4 6 7 8 Lexicon Move the Audio Input cable to Audio Input 2 and repeat the test Repeat the test
244. board One is used to get the position of the wiper arm on the 8 faders The second takes care of the joystick Lexicon button and the 12 volt sense A single 8 bit command register is implemented to enable the scanning of both A Ds and to have direct access to the A D converters When the enable command is given the FPGA will do a continuous scan of the inputs storing the values in the FPGA The addressing of the two converters is interleaved allowing faster updates of the values If the scanner is not enabled the command register will allow the selection of a single input or one of the other commands When the command is given software must wait atleast 60 secs before reading the value The value of the selected input is stored in the register locations based on bits 3 0 of the command This means that one converter will overwrite the locations of the other when in this mode 4 5 Motorized Faders 7 45 960L Multi Channel Digital Effects System Service Manual Motor Drivers sheet 5 The motors on the faders are driven using the raw 12 volts through SGS Thompson Push Pull drivers Software loads an eight word by 32 bit memory array within the FPGA with bit patterns that determine the waveforms that are the inputs to each pair of drivers for each fader The column of the array is scanned at a programmable clock rate At the beginning of each column clock the row clock cycles through each row and with the enable bit and the direction bit lat
245. cables identified by a red stripe are at the top of the connectors 6 Carefully turn the unit over 7T Verify that all of the drives are properly secured in place Verify all ribbon cables and power cables to these devices are firmly seated 8 Verify all ribbon cables to both the NLX and I O backplanes are firmly seated 9 Onthe back panel of the 960L make sure all cards are tightly screwed in place Inspect all connectors for wear or breaks that might cause intermittent operation LARC2 controller 1 Inspect the entire unit for obvious signs of physical damage such as cracked or broken plastic housings 2 Verify display is not cracked or shattered 3 Verify all sliders move up and down smoothly and do not bind 4 Verify the joystick also has a smooth fluid movement 5 Depress all the buttons to insure non stick operation Cables Inspect both the 960L power cable and LARC cable for physical damage or excessive wear Power Supplies Note It is important that the power supply be tested while fully connected in the 960L mainframe to insure proper voltage readings System Current Draw Tests 1 For 100 120V operation verify that the voltage selection switch on the back of the 960L is set to the 115 Volt setting 2 Setthe voltage level on the Variable AC power supply down to 0 volts then turn it ON 3 Plug the 960L into the variable AC power supply and switch the main power switch on the rear panel to the ON posi
246. cation address 29 has the value 29 written into it address 30 has the value 30 written into it etc Parameters CardID This number selects which reverb card to test Legal values are 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 TMixld This specifies which TMIX on the card to test Legal Values are 0 1 and 2 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Serial Audio Tests The syntax for the Serial Audio Test is SerialAudioTest CardID NumRepeats This tests serial audio paths in the system The number 555555 hex is written to each channel on each octal serial line between devices in the system The following lines are tested TMI to Lexichip3 1 TMI to Lexichip3 2 TMIX to Lexichip3 TMI to Lexichip3 4 Lexichip3 1 to TMIX Lexichip3 2 to TMIX Lexichip3 to TMIX Lexichip3 4 to TMIX Lexichip3 1 to Lexichip3 2 and Lexichip3 2 to Lexichip3 1 Lexichip3 to Lexichip3 4 and Lexichip3 4 to Lexichip3 TMIX 2 port 8 to TMIX 1 port 2 through the AES TMI 2 port 9 to TMIX 1 port through the AES TMIX 2 port 2 to TMIX 1 port 10 through the AES card 2 port 3 to TMIX 1 port O through the AES
247. ches the corresponding output registers to generate an individual differential drive waveform for each motor the MOTOR and MOTOR signals At the end of the 32 bit shifts the process starts again forming a continuous train of drive pulses It is the responsibility of the software to stop the motors by either writing zeros in the enable register or by setting all the memory waveform bits to zero The ENAB GPIO bit is a master enable to all motor driver chips Dir Reg REG Motor From CPU TZ 8 x 32 Bit Ram Mux REG Motor Enab Reg Figure 4 2 FPGA Internal Motor Control Logic Position Sensing sheet 5 Each motorized fader is based on a 10K linear sliding potentiometer Each potentiometer is connected to a dc source 5VA and produces a 0 to 5V dc voltage proportional to its position To digitize the position information each voltage is fed to one channel of A D converter U30 The serial port of the converter is scanned under the control of FPGA 018 018 supplies the serial input to control the channel multiplexing and receives the serial output from the resulting A D conversions converting the data from serial to parallel and storing the results in a memory block within the FPGA itself The saved position locations of the faders are eight 10 bit registers located on word boundaries These registers are cleared upon power on or after a software re
248. connected to the LARC2 AUX port Determining boot cause Reset detected Memory Data Test Beginning memory wipe Copy Rom and Enable MMU Copy Verified After MMU SP After Stack Running tests ERR KB08 Keyboard TimeoutReset socket 1 succeeded PCMGetStatus Socket 1 GPLR 0bdae36c PcCard 1 is present PcCard 1 Requesting window Read first tuple Checking Card Type Card Type 6 Checking Card Type Card Type 6 The Debug terminal should be configured as follows Baud Rate 57600 Bits Per Second Data Bits 8 Stop Bits 1 Parity None Flow Control Xon Xoff Terminal Emulation ANSI 6 25 960L Multi Channel Digital Effects System Service Manual POWER ON DIAGNOSTICS There are two LED s located on the LARC2 Main Board which are used for displaying the status of the Power On Diagnostic tests that are performed before the LED s on the Meter Board or LCD display are enabled Upon normal power up the two LED s MSB 1 and LSB 0 perform a binary countdown from 3 to 0 11 10 01 amp 00 NOTE There are no error messages during this portion of the Power On Diagnostics In the event that a diagnostic failure has occurred the system will halt on the failed test The binary value displayed on the two LED s indicates where the failure occurred during the Power On Diagnostic test sequence Power On Diagnostics Sequence When the LARC2 is first powered on all of the LED s on the Meter Boar
249. d and Main Board keypad will be turned on for approximately 5 seconds during this period the following sequence of operations are performed as the Power On Diagnostic tests are executed These operations are all being executed from the Boot ROM e Initialization During this operation the SA 1100 is reset its registers are initialized the interrupts are disabled and the Main Board LSB 0 and MSB 1 LED s are turned on to display the binary value of 3 MSB 1 ON LSB 0 ON e Determine Boot Cause During this operation the Boot cause is determined which is normally because reset has been detected Boot ROM Checksum During this operation the checksum of the Boot ROM is verified and the Main Board LSB 0 LED is turned OFF to display the binary value of 2 MSB 1 LSB 0 OFF e Memory Test DRAM Data Bus During this operation the DRAM Data Bus is tested by first writing 00000000 hex into 512 memory locations of the DRAM then the same 512 locations are read to verify the data written in these locations is correct The same write read sequence is also performed using the following hex values FFFFFFFF AAAAAAAA 55555555 33333333 99999999 amp 66666666 During the test the DRAM data lines SA 0 5 031 are tested using the data patterns listed in the table below Refer to the table below for the hex to binary conversion of the data patterns FFFFFFFF AAAAAAAA 55555555
250. d loop continuously at the failed address location The address where the error occurred along with the data sent and the data received is sent to the Debug Port NOTE Since this test utilizes 32 bit words 4 bytes it is not possible to test the address lines 0 amp 1 Copy ROM to RAM 6 27 960L Multi Channel Digital Effects System Service Manual During this operation the Boot ROM is copied to the DRAM then the data written to the DRAM is verified by performing a byte by byte compare with the data stored in the Boot ROM The Main Board MSB 1 LED is turned OFF and the LSB 0 LED is turned ON to display the binary value of 1 MSB 1 OFF LSB 0 ON During this operation the MMU and interrupts are enabled on the SA 1100 The Stack Pointer is initialized and the LARC2 jumps to the C code program This is where the LARC2 begins to execute the program from the DRAM The Serial Debug port Keyboard AUX port and Timers to setup the system clock are initialized The LCD display is turned on displaying the Lexicon splash screen From this point on the software begins to continuously monitor for PROGRAM MACHINE keys being pressed If the PROGRAM MACHINE key combination is detected a flag is set for the LARC2 to enter Menu Mode upon completion of the Power On Diagnostic tests The LED s on the Main Board and Meter Board are turned off The FPGA loads its code from the Xilinx SPROM and waits for the FPGA Done signa
251. d mu 1 Was gano ST ora Wars adoz any 6012 oT T9 z nuno vivos wesc es yu o ova lt xon tros 170 zegd 9001 Wor grow eas Aur 9 8019 n 880 1 1 1 099 0184 Irois very verc va Y Y e on T ir ovv Noa 136 TSE lt Pon ved ros x na no SHO Te 2 34022 HONO lpg 1 a ON 12 w os 4 6284 0 gr uino omn Bot ova os ven 20002 anty T2 WT ys 13 vivos lt 1 INE Tog ova 09 ay uno oj vars z uno Eur velzvao s 272 m Y Na 396 1 JH Ne e 79 508 895 OOL OEL woa Coit n m 00 0000 003 Tel wWo3 er er 1nd1no NOISH3ANOO 20 SNOISAS8 L c 9 4 8 9 27
252. dio 3 1250 4 1251 5 1252 6 1253 18 1254 19 1255 24 1256 25 1257 20 SDOO 14 SDO1 INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT Type OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT Lexicon POWER OK not used RESET 0 not used ALL MUTE 0 forces 125 data to zero digital mute CHIP SELECT 0 this slot is being selected 1 not selected DATA STROBE data is captured on rising edge of DS WRIRD 0 write operation 1 read operation Address 0 select which register is written read to from see register description section Not used Data Bus lt 7 gt data is written read over this bus Data Bus 6 data 15 written read over this bus Data Bus lt 5 gt data is written read over this bus Data Bus lt 4 gt data is written read over this bus Data Bus 3 data is written read over this bus Data Bus 2 data is written read over this bus Data Bus 1 data 15 written read over this bus Data Bus 0 data is written read over this bus master TMIX clock All local clocks I2S FS 25 64FS 125 256 5 derived from this clock TMIX WCKI Input frequency is nominally 24 576Mhz or 22 5792Mhz for 48 96Khz and 44 1 88 2 sample rates respectively CKI 2 not used WCKI TMIX
253. document is a script file that tests the MIDI Port REM REM History 03 13 2000 rjs Created REM 05 17 2000 clc modified to test the 56301 and Z80 REM to the Dual Port Ram Reverbcardtests Dpramtest 0 0 Dpramtest 0 1 Z80BootTest 0 0 Z80BootTest 0 1 Z80DpramTest 0 0 Z80DpramTest 0 1 56kToZ80CmdTest 0 0 56kToZ80CmdTest 0 1 Z80To56kCmdTest 0 0 Z80To56kCmdTest 0 1 Script 4 REM REM 9601 Diagnostics Test Script REM COPYRIGHT 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF THIS DOCUMENT MAY BE REPRODUCED IN ANY FORM WITHOUT THE REM EXPRESSED WRITTEN PERMISSION OF LEXICON INC REM REM File 4 htm REM REM Description This document is a script file that tests the MIDI Port REM REM History 03 13 2000 rjs Created REM 05 17 2000 clc modified to run the Lexichip tests REM REM cd Reverbcardtests LexichipWcsTest 0 0 0 LexichipWcsTest 0 0 1 LexichipWcsTest 0 1 0 LexichipWcsTest 0 1 1 LexichipAdfTest 0 0 LexichipAdfTest 0 1 LexichipAdfTest 0 2 6 21 960L Multi Channel Digital Effects System Service Manual LexichipAdfTest 0 3 LexichipDramTest 0 0 0 LexichipDramTest 0 0 1 LexichipDramTest 0 1 0 LexichipDramTest O 1 1 cd REM Script 5 REM REM MATHML REM 960L Diagnostics Test Script REM REM COPYRIGHT C 2000 LEXICON INC ALL RIGHTS RESERVED REM NO PART OF TH
254. e 5 VA voltage test point just below U3 between D8 and D9 Verify the voltage is 5VDC 25VDC 9 Locate the VB voltage test point on the right side of the card just to the left of C15 Verify the voltage is between 6 27 and 6 93 VDC 10 Locate the VCC voltage test points on the right side of the card VCC is just to the right of C206 and VCC is just to the right of that under FB54 Verify the voltage to be 17 50VCC and 17 50VCC 1 0 volt each SUO Analog Input Card Voltage Test The supplies being tested on this card will be the 12 VSUP provided by the main supply via the backplane and the 5VD and 5VA created on the card Before powering on the 960L for this test remove the Analog Input card from the rear of the chassis Insert the extender card and install the Analog Input card into the extender card Power on the 960L For your ground reference locate test point marked GNDA just above D7 So TO Lexicon At the back right hand corner of the card locate the FB1 Measure the 12 volts here and verify the voltage is 12VDC 6VDC Next locate FB2 Measure the 12 volts here and verify the voltage is 12VDC 1 2VDC Using the same ground reference measure pin of U3 5 VA Verify the voltage is 5VDC 25VDC Locate the 5 VD test point on the left side of the card just to the left of U1 Using the ground reference marked GNDD2 just to the right of the 5 VD verify th
255. e VCO is from around 18 to 30 MHz and control voltage is typically 4 to 6 volts when locked to 44 1 to 48 2 wordclocks 22 579 to 24 576 MHz Active Filter Op amp U6 NJM4580 and associated circuitry form an integrator that serves as the active loop filter The non inverting input of UG is biased at 2 5V by R7 and R8 and bypassed to ground by C22 The feedback capacitors C20 and C23 integrate the current introduced to the summing node by input resistors R9 and R11 R9 connects to logic level UP through series diode D3 and R11 connects to DOWN through series diode 04 7 12 Lexicon PLL Action PLL action can be understood by first disregarding the effect of R10 and D2 in the active filter In a perfect lock condition neither the UP or DOWN logic level is asserted so there is ideally no summing node current because D3 and D4 are both reverse biased and therefore the voltage out of integrator U6 holds at some constant value The VCO output is correspondingly constant and its frequency and phase are exactly the constant value required to satisfy the PFD lock condition In lock there are no error signals to integrate The correct control voltage exists and remains constant at a value that was attained by integrating errors that occurred previously If the PFD generates UP pulses either because frequency is too low or because phase is lagging the integrator output voltage rises in increments that depend on the width of the UP pulse
256. e default version of all the following tests are executed by running the complete system script which is number 1 In order to access executing individual tests the correct path to where sets of test are located must be entered on the keyboard The following directories folders exist MIDI Tests The MIDI tests reside in a directory called MIDI Reverb Card Tests The reverb card tests reside in a directory called reverbcardtests Serial Port Tests The serial port tests reside in a directory called serial Card Cage Tests lO card tests in directory called OBackPlane 6 5 960L Multi Channel Digital Effects System Service Manual In order to run an individual diagnostic test a keyboard must be connected to the LARC2 and the path typed on the keyboard To get to the MIDI tests type the word MIDI after the command prompt which is the gt greater than symbol and then ENTER The commands are case insensitive To get back to the root directory type the command cd which is the DOS command for change directory followed by a space then the period two times and the ENTER To get to the reverb card tests type reverbcardtests all one word with no spaces and then press ENTER Once you are in the desired directory typing help and then pressing ENTER will provide a listing of the available tests To see a description of any particular test type more help then the name of the test For example to see a description of the dual por
257. e or acetone based cleaners or any strong commercial cleaners Avoid using abrasive materials such as steel wool or metal polish It the unit is exposed to a dusty environment a vacuum or low pressure blower may be used to remove dust from the unit s exterior 960L s cooling fan located on the right side of the mainframe facing the front has a removable filter It should be cleaned periodically with water and mild detergent rinsed thoroughly dried and reinstalled Ordering Parts When ordering parts identify each part by type price and Lexicon Part Number Replacement parts can be ordered from LEXICON INC 3 Oak Park Bedford MA 01730 1441 Telephone 781 280 0300 Fax 781 280 0499 email ATTN Customer Service Returning Units to Lexicon for Service Before returning a unit for warranty or non warranty service consult with Lexicon Customer Service to determine the extent of the problem and to obtain Return Authorization No equipment will be accepted without Return Authorization from Lexicon If Lexicon recommends that a 960L be returned for repair and you choose to return the unit to Lexicon for service Lexicon assumes no responsibility for the unit in shipment from the customer to the factory whether the unit is in or out of warranty All shipments must be well packed using the original packing materials if possible properly insured and consigned prepaid to a reliable shipping agent When returning a unit for
258. e test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Notes Itis assumed that the following tests pass DPRAM Test Z80BootTest Z80DpramTest Lexichip3 WCS Test Details This command alternately loads two small programs into the DPRAM for the Z80 which move data to write and from read Z80 memory space Data is written into the ADF through direct memory writes to the Lexichip3 but read back using the Host Wide Data Latch TMIX Tests The following TMIX tests verify the operation of the 3 TMIX chips on the Reverb card 960L Multi Channel Digital Effects System Service Manual TMIX Host Test The syntax for the TMIX Host Port Test is TMixHostPortTest Cardld TMixID NumRepeats This tests the 56301 s ability to access a TMix s host port This test confirms that the 56301 fully access the host port on specified TMix chip This command writes a walking 1 s pattern 0000 00001 0000 0010 etc to the Test Control Register address 0x7B on the specified TMix chip Each value is written to the register then read back and confirmed before moving on to the next value While the data path is fully tested the test makes no attempt to confirm that it is writing to reading from the correct register in the TMix Writing to the host port and therefor a Host Register involves writing the address of the selected Host Register to the TMix s Pointer Port The
259. e ver 1 I gt XY 2 190 8301 Em s 364 E E 4 1 se sois bon p ni zv lt T AgNO 8301 s lt ZO vel 98 SV bad rm d E 16506 lt BOG 8301 LELE OHV 8301 e 856 orc lt SVS YSI a bad ar Dd 023 19206 000 8301 018 830 VS 19 SO VSI em RN ta sia eC 9301 3 00 830 a Our VSI ee tly Sig fenig lt gt 7100 8018 200 8301 8019 T Zi BO w 75655 154 18009 2 09 9301 50 5 iive vel mi 00104 e 600 8301 201831 kos ENS vS a NO Dd Sig Load 830 206 OS m iss VSI Gd t Dr em sacras ze E Rie Eos tom dev IN5 Dd Tota tiv INS 94 eas Es gt ww E R1 401 1018 1353 830 92 5 lt Say lov Pis Sa 980 0218 SVC gn nL pm ES or 1150 618 802 FE Z E m E kaki ze ava o 2 DIO Od 1986 2x orc aive YS Qd 097 58 sv eos 1O31 AOAO VIOI 956 mO var 554 aN 80 2 1860 Vati
260. e voltage is 5VDC x 25VDC AES Input Output Card Voltage Test The supply being tested on this card will be the 5VD provided by the main supply via the backplane Dore Oma Before powering on the 960L remove the AES Input Output card from the rear of the chassis Insert the extender card and install the AES Input Output card into the extender Power on the 960L Locate the ground reference test point marked GND1 just above U3 Locate test point marked 5 V to the right of the GND1 test point With the DMM verify the voltage is 5VDC 25VDC Input Output Clock Generator Card Voltage Test The supplies being tested on this card will be the 12 VSUP and the 5VD provided by the main supply via the backplane Before powering the 9601 remove the Input Output Clock card from the rear of the chassis Insert the extender card and install the Input Output Clock card into the extender card Power on the 960L For a ground reference locate test point marked GND2 on the right side of the card Locate the ferrite bead FB3 at the back of the card just to the right of the connector and measure the 12 volts Verify the voltage is 12VDC eVDC FB4 is next to FB3 Measure the 12 volts here Verify the voltage 12VDC x 1 2VDC Locate the ground reference test point marked GND1 on the left side of the card just to the left of U1 Locate test point marked 5 V just below 01 With the DMM
261. ead only register at address 0x1000 0700 When the output buffer is read the controller sends information to the SA 1100 The information can be keyboard scan codes or auxiliary device data The input buffer is an 8 bit write only register at address 0x1000 0700 When the input buffer is written to the input buffer full bit 1 in the status byte is set to 1 The data is sent to the keyboard 4 9 2 PS 2 Status Register The PS 2 Status Register is an 8 bit read only register at address 0x1000 0704 4 9 3 Interrupts The PS 2 Controller produces two interrupts TXRDY and RXRDY TXRDY is connected to GPIO11 on the SA 1100 and indicates that the input buffer is empty This bit is set to 1 on power on or reset RXRDY is connected to GPIO12 on the SA 1100 and indicates that that there is a byte in the output buffer This is set to 0 on power on or reset LCD Interface sheet 7 The LCD interface that is on the LARC2 is a Passive Matrix Color Display with 640 x 240 dots This display is driven directly from the LCD interface native to the SA 1100 microprocessor Encoded pixel data is stored in the external DRAM and the LCD controller has its own dedicated DMA controller for moving the data to the output FIFO LCD contrast is adjustable by R136 CONTRAST located on the rear panel R136 is enabled by CONT ON permanently asserted low J1 and J3 support the pinouts of alternative LCD modules Host Interface Port sheet 7 The Host Interface uses Ser
262. ed output of the filter is ac coupled to the DRV134 differential transformerless line driver to deliver fullscale differential output at 24dBm to XLR connectors A two pole muting relay prevents uncontrolled transients from appearing on the output when power is applied or removed from active circuitry The design supports nominal sample rates of 44 1 48kHz in single speed mode and 88 2 96kHz in double speed mode Circuit Description The following detailed circuit description applies to channel 1 sheet 1 The seven other channels are similar D A Converter D A converter U6 AD1853 is powered on its DVDD pin by the main 5VD system power from the backplane and its AVDD pin by higher quality 5VA regulated on board by U3 Power is decoupled by ferrites FB5 FB13 and bypassed by C29 30 45 71 U6 operates its serial digital audio port in 125 mode IDPM 1 0 01 125 signals 1251 1 BICK and DAC LRCK are provided by interface fpga U1 sheet 4 Master clocks to the eight D A chips are distributed from U1 in pairs MCK12 driving U6and 07 channels 1 and 2 respectively The remaining four D A logic inputs are under the control of host software via the U1 interface RST DAMUTE DEEMPH and 96K EN are applied to all eight D A chips in parallel The SPI control port is not utilized CLATCH CCLK and CDATA are connected to OV Analog reference current for U6 is set at about 1mA by R22 filtered by C46 C47 The differential output
263. ens closes and provides information in a log file The Log File records all displayed information from the diagnostics into a text file This is useful for reviewing the activities of an automated script file or reporting bugs The logfile command can also be used to acquire the serial number of a 960L Usage When executed with no parameters displays the current log file name When executed with ON as a parameter the log file is enabled opened When executed with OFF as a parameter the log file is disabled closed When executed with a file name as a parameter the new name is used for the log file If the LogFile was already enabled the previous file is closed and the new file is opened To acquire the serial number turn the logfile off by typing logfile disabled Then change the name of the logfile by typing logfile cX960lserialno Then type the command viewlog The serial number of the 960L on the hard drive will be displayed followed by the date of manufacture The date of manufacture is listed as a four digit number with the month being the first two and the year being the last two Exit This command exits the diagnostic program Root This command goes to the top of the command tree Dir The dir command shows all of the commands available at the current level This is similar to the DOS equivalent LISTING of RESIDENT SCRIPTS Script 0 REM REM MMA REM 960L Diagnostics Test Script REM REM COPYR
264. erial port or reports the current selection This command sets the serial port that will be used by the diagnostic commands executed with no parameters the currently selected serial port is reported Parameters Legal values for the port num are 1 and 2 Note that the SerialSetPort cannot be run if the Terminal is enabled Terminal mode is the default for Port 1 due to the LARC2 using this port Global Commands TimeDate Displays the current time and date This command is typically used in script files to provide a timestamp which will appear in a log file This can be examined later to determine when the test was run before or after repairs were made for instance Version Reports the current version of the diagnostics Prints the current version on the display or log file along with date and time the software was created Rem text Allows comments to be added to script files The Rem remark command allows comments to be added to script files The command itself actually does nothing Echo Echo followed by a message prints messages to the screen log file The echo command allows messages to be printed on the display Though it will operate directly from the command line Echo was really added to provide documentation and feedback from script files Up to 16 words 32 characters long can be used Script The script command followed by a complete path and filename executes commands from a script file This comma
265. es etc including amplifiers which produce heat Ventilation Make sure that the location or position of the unit does not interfere with proper ventilation For example the unit should not be situated on a bed sofa rug or similar surface that may block the ventilation openings or placed in acabinet which impedes the flow of air through the ventilation openings Wall or Ceiling Mounting Do not mount the unit to a wall or ceiling except as recommended by the manufacturer Power Sources Connect the unit only to a power supply of the type described in the operating instructions or as marked on the unit Grounding or Polarization Take precautions not to defeat the grounding or polarization of the units power cord applicable in Canada Power Cord Protection Route power supply cords so that they are not likely to be walked on or pinched by items placed on or against them paying particular attention to cords at plugs convenience receptacles and the point at which they exit from the unit Nonuse Periods Unplug the power cord of the unit from the outlet when the unit is to be left unused for a long period of time Water and Moisture Do not use the unit near water for example near a sink in a wet basement near a swimming pool near an open window etc Object and liquid entry Do not allow objects to fall or liquids to be spilled into the enclosure through openings Cieaning The unit should be cleaned
266. esent A diagnostic error message is also sent to the Debug Port to indicate when a failure has occurred as shown in the example below Loop Back Not installed TEST 8 Keystuck amp Fader Touch Test This test checks for stuck keys on the Main Board or if any of the Faders were being touched during the Power On Diagnostic tests LCD Test This test is used to verify the operation of LCD display circuitry by displaying various attributes of the LCD display which includes a display of vertical color bars dimming the LCD display turning the LCD display off and on and displaying a white screen with a red border When the test is executed the ENTER key is used to advance step through six different screens to verify the operation of the LCD display as described in the table below STEP DESCRIPTION The LCD displays vertical color bars at full brightness The LCD displays Vertical Color Bars that are dimmed The LCD display is turned off The LCD displays Vertical Color Bars that are dimmed The LCD displays Vertical Color Bars at full brightness The LCD displays a white screen with a red border NOTE white screen with border from Step 6 above is the best screen use for verifying there are no defective pixels which would appear as black dots on the LCD display This is also useful for checking the alignment of the LCD display with the Display Housing assembly
267. ext pre designated position When the test is executed all of the 8 faders are moved to their minimum position and are moved slowly to their maximum position then back down to their minimum position During the test the A D converter values of the 8 Faders are monitored to determine their respective positions When a failure has occurred an error message is sent to the LCD display and also to the Debug Port as shown in the example below FAIL Timeout on fader 2 Press or Enter on debug port key to acknowledge Press the key on the LARC2 or press ENTER on the Debug Terminal to continue Lexicon Test This test is used to verify the operation of the piezo transducer circuitry This test has been designed to read the values from the piezo transducer s A D converter and verify that two Max values can be achieved When the test is executed the Lexicon key is pressed amp released until a Max value below 300 and a Max value above 600 is displayed on the LCD display When a failure has occurred an error message is sent to the LCD display and also to the Debug Port as shown in the example below Did not hit full range Press or Enter on debug port key to acknowledge Press the key on the LARC2 or press ENTER on the Debug Terminal to continue 6 39 960L Multi Channel Digital Effects System Service Manual Memory Test This test performs a non destructive memory test on all memory
268. ferent outlet so that the computer and receiver are on different branch circuits If necessary the user should consult the dealer or an experienced radio television technician for additional suggestions The user may find the following booklet prepared by the Federal Communications Commission helpful How to identity and Resolve Radio TV Interference Problems This booklet is available from the U S Government Printing Office Washington DC 20402 Stock No 004 000 00345 4 Le pr sent appareil num rique n met pas de bruits radio lectriques d passant les limites applicables aux appateils num riques de la class prescrites dans R glement sur le brouillage radio lectrique dict par le minist re des Communications du Canada Copyright 1999 Lexicon Inc All Rights Reserved Lexicon Inc e 3 Oak Park e Bedford MA 01730 1441 e Tel 781 280 0300 e Customer Service Fax 781 280 0499 Lexicon Part 070 14826 Rev 0 Printed in the United States of America 9601 Multi Channel Digital Effects System Service Manual Read instructions Read all safety and operating instruc tions before operating the unit Retain Instructions Keep the safety and operating instruc tions for future reference Heed Warnings Adhere to all warnings on the unit and in the operating instructions Follow Instructions Follow operating and use instructions Heat Keep the unit away from heat sources such as radia tors heat registers stov
269. ff board frequency references The on board references are two high accuracy 10ppm crystal oscillator modules U3 24 576MHz and U4 22 5792 2 that are connected to inputs of U2 These crystal frequencies are multiples of the standard 48 96kHz and 44 1 88 2kHz sampling rates respectively Off board references are sample rate wordclocks that come either from the on board BNC receiver circuitry described above or from pin C5 of the backplane Other modules can supply this wordclock via the backplane so that a variety of external sources can provide the reference clock for the system according to the specific type of I O interface module PLL Support Logic within U2 that is involved with the operation of the PLL is described below Phase Locked Loop All clocks that are distributed to the digital audio systems in the 960L ultimately derive from the oscillator in the on board PLL sheet 3 The PLL consists of a Voltage Controlled Oscillator VCO U10 MC12148 a Phase Frequency Detector PFD implemented within CPLD U2 and an active filter formed by op amp UG and associated circuitry The VCO oscillates around the 22 24MHz range depending on sample rate The PFD and other logic within U2 lock the oscillator appropriately to whatever source is chosen to be the frequency reference Reference sources affect the system only indirectly when they become the reference for the PLL Logic within U2 divides the VCO frequency to form the
270. ff the workbench and drop 2 Verify there is no audio break up 3 Inspect all components after to be sure nothing was loosened by this test 4 10 Lexicon ATE Summary Ision Lexicon Audio Prec Bojeuy 00087 eju eju eju eju eju eju eju puo 07 005 Uu ISr1096 JezKjeuy Bojeuy 359 1 Bojeuy 00087 nulio 110848 ZHNZZ ZH0L gt X001 ej 10000 zooo 90000 N GHL 96 puo leg xoz oz 2 Bojeuy 00087 MULIEPO 10848 008 2 300 L 0 puo leg Oy xoz oz 459 boy 00087 0848 2 008 2 01 300L Sec 18421 ngp ov 466 ngpec ngpec e e 1ez jeuy Bojeuy 10je1ouac Bojeuy 81691 Sav 00096 niy Lepo no 8ul 8 2 01 700 Ho 10000 2000 900070 N GHL eju eju eju 466 8389 8389 U PU JNO 96 sav 0S0 r6 0S6 26 0848 2 22 2 01 gt 001 10000 2000 90000 411056 0 3696 96 deems 466 Sagpi Sdgpi Ux pu U 496 3591 JnO u
271. ftware from the Option Board Menu The following options are available Boot from Ram the image downloaded to DRAM Boot from PCMCIA Boot from Flash Program Flash Decompress from Flash as shown in the menu below kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk App Options kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk r Boot From Ram p Boot from PCMCIA f Boot from Flash d Decompress from Flash X Download via Xmodem This menu selection is used to download the LARC2 Boot boot rom and or Program Flash image larc2 rom via the Debug Port on the LARC2 Option Board using the Xmodem transfer protocol 6 42 Lexicon F Flash Operations This menu selection is used for programming the Program Flash memory with the LARC2 application Program App and or to program the Boot ROM Burn Boot Flash These options are available from the menu shown below koe Kk k he ke e e k k k k he ke k k kk k k Flash Management Options w Program App b Burn flash e Erase PROGRAM flash s Save a copy of the BOOTROM r Restore BOOTROM 2 Program STAGE2 D Interactive Diagnostics This menu selection is used to enter the Interactive Diagnostics Menu from the Option Board Menu S Diagnostics Suite This is the same test that resides on the Interactive Diagnostics Menu This menu selection can also be used to execute the Diagnostics Suite from the Option Board Menu Z ZModem Download Thi
272. g you locate the solder side of connector J26 on the Left side of the NLX backplane 4 Clip the ground lead of the DMM meter to the chassis for ground reference 5 Take the Plus lead and using the table below verify the voltage levels indicated on J26 Pin Wire Color Voltage Range 1 Orange 3 volts DC 4 0 4 Red 5 volts DC 25 10 Yellow 12 volts DC 6 12 Blue 12 volts DC 1 2 13 Black Ground 18 White 5 volts DC 5 Lexicon Orange 3 0 to 3 4 volts DC Blue 10 80 to 13 20 volts DC Black Ground Green ON Red 4 75 to 5 25 volts DC Black Ground Grag PWR White 4 50 to 5 50 volts DC Purple 5 58 Red 4 75 to 5 25 volts DC Yellow 11 40 to 12 60 volts DC J26 NOTE The following voltage tests are to insure that the connectors are plugged into the NLX backplane and that power is being properly distributed to the other devices This may also help in determining whether or not the devices themselves are defective To gain easier access to the test points called out in the following tests you will want to turn over the mainframe of the 960L so the bottom faces up or rest it on its side All power connections to the backplane Hard Drive CD ROM Drive and 3 5 Floppy Drive have the same colored wiring code Color Voltage Range Yellow 12 volts DC 6 Black Ground Red volts DC 25 NLX Backplane Connector J9 Vo
273. gpec ngpec N8 Bojeuy 00087 Eureju NO 8 Ul 8 1 ZH107 lt ZHOL gt en eju oel okl Ell Sagp pu leg ov 302 02 ngpoe ngpoe Bur ufp p e Bojeuy 00087 8 1 ZH10Z lt ZHOL gt eju eju 021 v6 Okk 8359 puo lea ov 402 02 napec Ur pul Bojeuv 00087 no sug 284 01 eju eju be L 0 19491 pu lea ov 402 02 ngper 4591 xgy p e Bojeuy 00087 niy Lepo ino 8418 2184 04 gt eju eju 2 0 be 18491 S49P leg ov 466 ngpec ueb pe dazAjeuy jey ia Boleuv lues ZHY A Y eju eju eju eju eju 30055 01 gt WOOL wu 000 001 666 PaT eju eju eju eju eju Siu 1ezKjeuy Bojeuy Bo euy 1591 oinos oye oimnos uoneunByuo pueg inse W 18497 32014 jequn zy OWEN 159 ejdures 20152 19 01 1ezKjeuy 10 Bojeuy 9 10 dnjes 1096 WIZATVNV 39HhnOS 4 11 960L Multi Channel Digital Effects System Service Manual 4 12 Lexicon Chapter 5 Service Notes Motherboard lithium battery The motherboard has a lithium battery This is not user replaceable Only a qualified service technician should replace it Lithium batteries may be
274. he RD signal is no longer used Only one of the Reverb Cards in 960L can serve as the I O Bus master so all control signals are only driven if ENAB_IOBUS Is low otherwise all Bus outputs from the card are tri stated The ENAB_IOBUS signal is controlled by the Pentium host software through the 56301 I O bus data is transferred through 039 and the I O Bus address is driven through 031 032 and 044 Provisions for a serial EEPROM on the I O Bus backplane are supported by the control signals driven through U50 The IOBUS INT shown 030 is a wire ored interrupt signal from the I O Bus that is not currently used The Audio Clock 045 is used to provide clocks to the T MIX devices at start up The start up clocks are INIT CLK and WCLK After initialization of the 960L Clock IO card the and TMIX WCKI signals are active and the mux is switched to use these clocks for the T MIX devices Startup Sequence At power up the 56301 is held in the reset state by the power supply monitor U37 sheet 1 for a minimum of 20 ms after 5VD has stabilized Once the DSP_RESET signal has gone high the 56301 will exit the reset state and read its bootup program from the Boot PROM 018 sheet 6 If the bootup procedure completes successfully then the clock measured on R168 will be 80 MHz If the 56301 failed to boot correctly this clock will be 3 MHz After the 56301 has completed its bootup procedure it waits for a startup progra
275. he IO backplane can also interrupt the DSP cards by asserting the IOBUS INT signal The ALL signal is provided to allow for a hardware assisted System wide mute The power provided by the NLX power supply comes in on connector J26 This is an NLX standard connector and pinout The power connectors provide 5x 3 3v 12v and 5VSB supply rails supplies can be remotely controlled The NLX motherboard is capable of shutting off the power supply by 7 2 Lexicon asserting the 5 ON signal It does so on system software shutdown or when the STANDBY POWER Switch is pressed DSPBUS Connectors Sheet 8 9 Communication between DSP cards and the IO cards in the system are provided over a Lexicon proprietary control and audio interface using a second set of PCI style connectors J10 J13 Passive termination networks R015 R109 R110 R104 R107 R108 R106 R111 R112 are used on TMIX 2 TMIX WCKI to maintain signal integrity i e manage signal reflections and levels All serial audio data signals TMIX1 SERD and TMIX2 SERD are pulled up by resistors R13 R20 127 R140 The capacitors on these pages are for power supply decoupling and bypassing 7 3 960L Multi Channel Digital Effects System Service Manual Backplane Introduction This section describes the theory of operation of the 960L IO Backplane card Overview The 960L IO Backplane provides the interconnect between the DSP ca
276. here D5 is labeled SYSTEM OK will be lit and the process is completed The total time to perform the entire operation takes approximately 2 minutes The NLX motherboard has beeping that assists the technician The first beeping occurs at 13 seconds and is 2 quick beeps to indicate no keyboard is present The you will hear floppy drive and CD ROM motor activity The second beep occurs at 21 seconds and is 1 beep to indicate the BIOS is completed loading and the operating system is beginning execution If no beeps or any other beeping pattern occurs the motherboard is not booting properly and a system level failure has occurred In the event of a failure the first thing to check is the power supplies After that the motherboard is suspect and should be swapped out with a known good motherboard Extreme care should be exercised when changing a motherboard The bottom of the motherboard must never be allowed to come into contact with the metal chassis of the 960L The motherboard contains a lithium battery with a thru hole battery holder If the leads of the battery holder come into contact with the metal chassis the battery will be shorted out and permanent damage can occur Also the amount of force required to insert the NLX motherboard into the NLX connector is considerable The contact pins are small and it is very easy to misalign the pins in the connector or not fully seat the motherboard giving rise to false failures To ensure fully seating the motherb
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278. ial Port 1 of the SA 1100 This port is a combination synchronous data link controller SDLC and universal asynchronous receiver transmitter UART serial controller This port is configured as a UART and is identical to Serial port 3 This connects to an ALS180 RS422 driver receiver U2 The pinout for the host interface is shown below Ground SC Plus 12 Volts DC Ground RC Table 4 1 Host interface pinout 7 48 Lexicon Option Board Interface sheet 4 Connector J6 brings out signals to support additional plug in option board for additional I O and memory PCMCIA Interface The SA 1100 provides control signals to support a two slot PCMCIA interface Slot 1 is used for the on board program Flash memory and slot 2 is used for the option board PCMCIA card slot Expansion Serial Interfaces Serial Port 0 Serial port 0 is a universal serial bus USB device controller that supports three endpoints and can operate half duplex at a baud rate of 12Mbps slave only not a host or hub controller This port is connected to the option board connector for future expansion Serial Port 2 Serial port 2 is an infrared communications port ICP It operates at half duplex and provides direct connection to commercially available Infrared Data Association IrDA compliant LED transceivers This port is connected to the option board connector for future expansion Debug Interface The debug Interface available through the optio
279. ic in PFD defeats PUMP DOWN if the reference is lost preventing the forced rapid drop of VCO frequency Pulses from the CPLD are buffered by inverting stage U8 and become the UP and DOWN pulses fed to the active loop filter U8 is supplied by the regulated 5V to clamp the pulses to a constant amplitude removing any fluctuations that may be present on the main logic supply Voltage Controlled Oscillator VCO U10 oscillates at a frequency which depends on L1 1 uH C35 10pF and the capacitance of varactor diode D7 BB132 The output of U10 is around 700 mVp p at a dc level of nearly 4V This small signal is amplified and buffered by U9 74HCU04 to develop PLL 512 5 a suitable logic level to drive CPLD U2 The oscillation frequency is normally in the range of 22 to 25MHz and when in lock oscillation is at an exact multiple 256 or 512 of the reference wordclock frequency The capacitance of D7 varies with its reverse bias voltage D7 is the element that allows voltage to control frequency The anode of D7 is constant at about 1 7 V established by the VREF pin of U10 The voltage at the cathode of D7 controls the VCO frequency A greater positive voltage increases the reverse bias reducing the capacitance and producing a higher VCO frequency The network formed by R13 C24 FB8 and C37 helps keep high frequency noise from being introduced at the cathode of D7 to reduce undesirable modulation of the VCO The range of oscillation for th
280. ics are executed every time the 960L chassis is powered on The reverb card is minimally checked for correct operation by the 960L application and the cards in the cage are identified The minimal checking of the reverb card is for time purposes To fully verify the reverb card diagnostically the time required is approximately 20 minutes This is unacceptably long each and every time the 960L is powered on The results of the power on diagnostics are not displayed on the LARC2 The only method to verify that the minimal operation of the reverb card is to observe the Reverb card LEDs for 6 4 Lexicon correct operation The reverb card has 8 LEDs along the front left edge on the side of the card that faces the NLX motherboard when the card is observed mounted in the 960L chassis When powering on the 960L and executing the 960L application allow it to boot to normal operating mode the LEDs will initially be off for about 1 minute 45 seconds Then all the LEDs will be lit very quickly After that the 4 leftmost LEDs D1 D4 that are labeled Z80 2 Z80 2 Z80 1 and Z80 1 respectively will light in a periodic pattern where D1 D4 the two outside LEDs will be on and the other two off and then D2 D3 the two inside LEDs will be lit and the two outside LEDs will be off This pattern will occur 4 times and take about 7 seconds Then all four leftmost LEDs D1 D4 will be all lit for about 5 seconds Finally the five leftmost LEDs D1 D5 w
281. ies which Lexichip3 associated with a particular Z80 to test Legal values are 0 and 1 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Notes Itis assumed that the following tests pass DPRAM Test Z80BootTest Z80DpramTest Details This command alternately loads two small programs into the DPRAM for the Z80 which move data to write and from read Z80 memory space Lexichip3 ADF Test The syntax for the Lexichip3 ADF Test is Lexichip3ADFTest Lexichip3ld NumRepeats This tests the ADF Audio Data File memory on the Lexichip3 The test begins by filling the ADF memory with a specific data value then reading back the contents of each memory location confirming the data contained therein is correct Values of 0 OXFFFFFF OXAAAAAA and 0x555555 are tested This test confirms that the Z80 can access all of the Lexichip3 s ADF memory space and that the memory itself is operational Parameters CardID This number selects which reverb card to test Legal values are 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 Lexichip3ld This specifies which Lexichip3 to test Legal values are 0 and 1 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs th
282. impedance is gt 13kohm and low frequency response is 0 1dB down at 1Hz Voltage division by 2 6dB reduces a 24dBu level on either XLR pin to a maximum of 18dBu 8 7 at the inputs of unity gain buffers U20 The series resistances of R130 R132 prevent damage from excessive current if the input is overdriven The common mode component out of U20 is sensed by U16 which scales it by approximately 0 66 The output of 020 is also applied to the summing network formed by R49 50 51 and 52 which scales it by approximately 0 4 and subtracts the common mode component scaled by approximately 0 6 x 66 0 4 The common mode voltage is substantially removed and only the differential mode component of the input signal appears at the input of unity gain buffer U8 regardless of whether the applied input is balanced or unbalanced The dc voltage at the non inverting input of U16 is set at 2 5Vdc by R97 98 to create the offset that biases the A D converter the middle of its 5V range Due to the gain of the stage the dc level at the output of 016 is 140 66 x 2 5V 4 15V which then is scaled back down by the summing network and appears at 2 5V at the inputs of U8 R81 supplies part of the dc current drawn by the summing network reducing the dc load on 016 With 24dBu balanced input the voltage out of each side of U20 is 4 35Vpeak the two sides have opposite phase and there is no ac signal developed at the output of U16 The resulting fullsc
283. in a 44 pin PLCC socket The Boot Flash is programmed prior to insertion onto the board but there is code in the Boot Flash to perform updates to the code The memory is not byte writeable and must be programmed on a half word boundary 16 bits 7 43 960L Multi Channel Digital Effects System Service Manual Boot Flash memory occupies address space 0x0000 0000 to 0x0001 FFFF Program Flash 010 013 U14 016 sheet 2 The program Flash uses the PCMCIA socket 0 interface It can also be addressed through CS1 address space This will result in the possibility of having dual entries in the cache Care should be taken when updating this flash that all entries in the cache are invalidated before doing an update to this Flash The memory consists of four 16 MBit Flash memory chips The memory is organized as 2 MBytes by 32 bits The flash is not byte writeable and must be written on word boundaries 32 bits Program Flash memory occupies address space 0x0800 0000 to 0x087F FFFF Peripheral 1 Subsystems 018 sheet 3 The FPGA connects to the cpu address and data buses to interface the cpu with peripheral subsystems It controls the fader motors the fader position A D converters and the PS 2 keyboard port Additionally it acts as a conduit for buffering other peripheral data to the cpu These functions are described in the following sections Keypad sheet 8 The keypad is a rubber assembly containing molded in conductive
284. input Local 22 5792 Mhz oscillator input TMIX CKI TMIX master clock TMIX CKI 2 A clock that runs at half the rate of TMIX All edge transitions are timed with the falling of of the TMIX CKI clock WCKI TMIX word clock Rising edge denotes start of an octal frame All edge transitions are timed with the falling of the TMIX clock A clock signal whose frequency is 256 times the sample rate All edge transitions are timed with the falling of the TMIX CKI clock A clock signal whose frequency is 128 times the sample rate This signal is typically used as the 125 bit clock The falling edge denotes the stqart of a bit cell All edge transitions are timed with the falling of the TMIX CKI clock A clock signal whose frequency is 64 times the sample rate The falling edge denotes the start of the word clock period All edge transitions timed with the falling of the TMIX clock A clock signal whose frequency is equal to the sample rate All edge transitions are timed with the falling of the TMIX clock A clock signal whose frequency is equal to the sample rate This signal is identical to B FS except when 5 DRIVES is set in the CTLREG All edge transitions are timed with the falling of the TMIX clock Preview word clock This signal when enabled via the PVWCLK EN in the CTLREG is driven by the WCLK or the SLOT WCLK signal The selection is determined by the state of
285. itter of the VCO both exceed the requirement of AES3 1992 Amendment 1 1997 Phase Detector Offset As a practical matter it is undesirable to operate the PFD at zero phase error Because finite response times are involved in the logic that generates the UP and DOWN error signals the PFD has a zone around zero phase where it is non linear which causes undesirable loop operation Improved loop performance is achieved by intentionally introducing a small dc error in the integrator by means of R10 A small current from the summing node to ground through R10 acts to raise the output voltage and VCO frequency To maintain lock the loop compensates for this by developing a narrow positive DOWN pulse whose integral over one period is equal and opposite to the effect of R10 such that there is no net dc into the summing node R10 is chosen to require a compensating DOWN duty cycle of about 1 128 and this small phase error in the PFD keeps it away from the zero phase point In lock then the PLL wordclock applied to the PFD is made to lead the reference wordclock by a constant phase offset 1 128 of the wordclock period so the PLL wordclock is not aligned with the reference Within the CPLD an additional wordclock is produced that is delayed lags by precisely this amount It is this wordclock which is almost perfectly aligned with the reference that is distributed for use throughout the 960L The PLL wordclock that actually feeds the PFD has no visibilit
286. izes the External Keyboard and tests for the presence of a keyboard connected to the AUX port of the LARC2 by sending 8 characters out the port and monitors any data that is received The data received is then compared to what was sent NOTE This test requires an External Keyboard connected to the AUX port Otherwise the test will fail when an External Keyboard is not present Diagnostic error messages are also sent to the Debug Port to indicate when a failure has occurred as shown in the example below ERR KB01 TXRDY 0 should 1 GPIO fffc7ec ERR KB02 IBFULL 1 should be 0 Stat 12 GPIO fffc7ec ERR KB03 Keyboard Timeout TEST 7 Host Port Loop Back Test This test checks for the presence of a Loop Back Plug connected to the HOST port of the LARC2 by sending 8 characters out the port and monitors any data that is received The data received is then compared to what was sent NOTE This test requires a Female RS 422 Wraparound Plug installed in the HOST port Otherwise the test will fail when the Loop Back Plug is not present A diagnostic error message is also sent to the Debug Port to indicate when a failure has occurred as shown in the example below 6 29 960L Multi Channel Digital Effects System Service Manual Loop Back Not installed TEST 8 Keystuck amp Fader Touch Test This test checks for keys stuck closed on the LARC2 Main Board or if any of the Faders were being touched during the Power
287. k tree directly bypassing the PLL Clock Bus Interface All digital audio clocking in the 960L system is derived from 02 and associated on board circuitry Clocks from U2 are buffered by U1 7 244 74ABT244 and driven onto the I O backplane which distributes them to other modules 7 10 Lexicon All system clocks are derived from the PLL_512FS clock signal The frequency of PLL_512FS is 512 times the rate fo TMIX_WCKI The table below lists the rates of each system clock as a function of the system sample rate Sample Rate Signal 44 1 Khz 48 Khz 88 1 Khz 96 Khz PLL 512FS 22 5792 Mhz 24 576 MHz 22 5792 Mhz 24 576 MHz TMIX 22 5792 Mhz 24 576 MHz 22 5792 Mhz 24 576 MHz WCKI 44 1 Khz 44 1 Khz 48 Khz 48 Khz B 256FS 11 2896 Mhz 12 288 Mhz 22 5792 Mhz 24 576 MHz B 64FS 2 8224 Mhz 3 072 Mhz 5 6384 Mhz 6 144 Mhz B FS 44 1 Khz 48 Khz 88 1 Khz 96 Khz BNC WCOUT 44 1 Khz 48 Khz 88 1 Khz 96 Khz The external BNC wordclock can be used to derive system clocking The 960L system software can first preview the incoming BNC wordclock by assigning it to the backplane SLOT PCLK INT signal Once satified the 960L system software can select the BNC word clock as the source for system clocking Clock selection and preview clock enable are controlled by the control register CTLREG in the U1 FPGA Clock Selection Clocks can be derived from both on and o
288. l The Main Board LSB 0 LED is turned OFF to display the binary value of 0 MSB 1 OFF LSB 0 OFF e During this operation the GPIO s on the SA 1100 are enabled The External Keyboard hardware is reset The HOST port is initialized and the A D Converters are setup values are written to registers on the SA 1100 Power On Self Tests Pass Fail Results From this point on the Pass Fail results for the Power On Diagnostic tests are displayed on the Meter Board LED s The LED column numbers are used to indicate the number of the test 1 4 amp 6 8 respectively For example the Pass Fail results for Test 1 are displayed on the LED s located in column 1 The LED colors are used to indicate the Pass Fail status of the diagnostic tests are as follows Red Failed Yellow Undetermined Green Passed NOTE The term Undetermined means the diagnostic test did not detect the presence of a device connected to the LARC2 and the associated circuitry in the LARC2 could not be tested As a result the diagnostic test could not determine whether the associated circuitry was good or bad Upon normal power up with the PS 2 Keyboard and RS 422 Wraparound Plug installed the Meter Board LED s will display the Power On Diagnostics test results as shown in the table below 0 1 When the Interactive Diagnostics are entered by holding the PROGRAM ENTER keys during power up without the PS 2 Keyboard and Wraparound Plug inst
289. l 3201 96 Y A sav 002 000 lt Lepo 108418 20 2 1 001 JO 10000 2000 70000 01 deems 266 539 Sdgpi Ux pu U sav 0520 2 5769 112190 1708498 00 10009 2000 0000 90927 0 8469 85 dooms 166 Sdgpi sdgpi 5159 ul PIOM V A Sav 0017 170848 2 Ho 10000 2000 90000 eju eju 166 5 uspurino xpo Sav 00087 708498 ZHNZZ ZH01 gt 4001 10009 2000 90000 eju eju eju 166 5 SdgPI uspurino E P 1ez Ajeuy 9 2010 V A eju Ov 001 MYLIEPO nO 8ul 8 eju eju oS 09 1004 ZH eju 0 001 deems aed ldues dno nuu pow eju eju 8 en eju c 094 0092 Jene1 eu eju eju eu 0008 dda 0052 nui Bojeuy yndinonndul 3591 Sav 00096 Sav 3 2 0 700 eju 115 elk eju eju eju 02 04 48 09 39 09 96 Sav 00096 sav MYLIEPO 08418 JZZ 015 700 eju 10000 2000 900070
290. l source e distortion analog oscillator e analog distortion analyzer and level meter with Audio Band Pass filter e 100 MHz oscilloscope e digital distortion analyzer amp digital function generator e g Stanford Research Systems Model 05360 or Audio Precision System 1 with DSP Option System 2 e Variable AC Power Supply with voltage and current meters known as a Variac adjustable from 0 140VAC and 0 2Amps BK Precision 1653 or equivalent e 100 120 to 220 240 VAC step up transformer e LARC2 to 960L Interface Cable Lexicon P N 680 03525 2 Male D9 5422 Wraparound Connectors see Chapter 5 for spec drawing e 2 audio cables XLR male on one end with appropriate connectors on the opposite end for connection to the low distortion oscillator 2 audio cables XLR female on one end with appropriate connectors on the opposite end for connection to a headphone amplifier e Stereo Headphones XLR male to XLR female audio cables maximum length 1 meter XLR male to XLR female audio cables maximum length 2 meters e BNC to BNC Cables maximum length 5 meters e XLR male to XLR female 110 ohm AES digital audio cables maximum length 1 meter e 8 XLR male to XLR female 110 ohm AES digital audio cables maximum length 2 meters e 2 5 DIN to 5 Pin DIN Cables maximum length meters MIDI Cables Hosa Technology P N MID 305 or equivalent Lexicon 960L PCI Extender cards P N 023 14297 e Lexicon 960L
291. liv 22 82 D WI 087 HOV 22 LI MR s 79 90 ZZ Wr Diis 2 00 S YE LuV ZZ Sr 1 2 la aao 330 ewer 68141 22 TIN SW T TINT 98 5 gt awa w care cena TEN RV TNI 780 dd SI ES 189 14040 22 0r mo dS 9819249 Y WVHSIHOd TWN q 0 5 04 22 00 268 Q3ONVHO Z 10620186 X00 1 k 2 5 9 8 Lexicon 9 51 L 4 5 9 1 8 S 8 1220s 212 6966 eats wra 8 wo 28 69 1 090 8 20 5 am usewnn 3900 325 6808 M amomo 54 NIY ZZ dIHOIX31 68048 71096 WSHOS 06 10 MYO u 09 ON V 1OYSINOO em QNO 1 oia 80
292. ltage Level Test 1 Locate the power connector J9 on the rear backplane 2 Measure the voltages on the connector with your DMM leads 3 Place the DMM ground lead on the Black wire connector and the DMM plus lead on the Yellow wire connector and verify the voltage is 12 VDC 6 VDC 4 Place the DMM ground lead on the Black wire connector and the DMM plus lead on the Red wire connector and verify the voltage is 5 VDC 25 VDC 3 5 Floppy Drive Connector 1 Locate the power connector on the back of 3 5 Floppy Drive 2 With your DMM leads measure the voltages on the connector 4 3 960L Multi Channel Digital Effects System Service Manual 3 Place the DMM ground lead on the Black wire connector and the DMM plus lead on the Yellow wire connector and verify the is 12 VDC 6 VDC 4 Place the DMM ground lead on the Black wire connector and the DMM plus lead on the Red wire connector and verify the voltage is 5 VDC x 25 VDC CD ROM Drive Connector 1 Locate the power connector on the back of CD ROM drive 2 With your DMM leads measure the voltages on the connector 3 Place the DMM ground lead on the Black wire connector and the DMM plus lead on the Yellow wire connector and verify the voltage is 12 VDC 6 VDC 4 Place the DMM ground lead on the Black wire connector and the DMM plus lead on the Red wire connector and verify the voltage is 5 VDC x 25 VDC Hard Drive Connector 1 Locate the power co
293. m to be sent through the PCI interface This startup program is sent when the host system is starting the Windows operating system If this program is received and executed correctly the DSP LED is illuminated Once the 960L application is launched another 56301 program is sent from the host computer 7 36 Lexicon Upon receipt of this program the 56301 initializes the three T MIX devices and loads a program into the Z 80 dual port RAMs The 56301 releases the Lexichips and Z 80s from the reset state by driving the DBRD_RSTn signals high and the Z80_INITn signals high At this point the Z 80s execute their startup code from the dual port RAMs and pass messages back to the 56301 using the DB_MAS_INTn interrupt signals and the dual port RAM interrupt vector locations The Z 80s will illuminate the Z 80 LEDs under software control to indicate their startup success or failure The 56301 then receives commands from the host to detect which cards are resident on the 960L I O bus After reporting this information to the host processor through the PCI bus the 56301 is commanded by the host to initialize the cards resident on the 960L I O bus DSP 56301 Expansion Port Memory Map Address Attribute Address Resource Number SDoo400 SFEFEFF SD00000 50003 Boot PROM E 9D4002 9D7FFF 2 9923002 5035 20 AA1 9D2002 9D2FFF 2 02 9D1800 S9DIFFF 0 200 AAI
294. must be offset by the currents through R49 R88 7 21 960L Multi Channel Digital Effects System Service Manual so equilibrium is achieved when U14 outputs are somewhat below the Vbe of Q3 although not quite 0 A slight positive equilibrium point is desirable to accomodate the asymmetrical tolerances of the 12 System supplies as well as the asymmetrical output capability of the OPA2134 with the objective of maximizing the voltage range available for the audio signal In addition to compensating for D A bias current the dc feedback also compensates for the FILTR compliance voltage which requires another 0 4mA through each bias resistor The presence of R47 and R51 at summing nodes increases the noise gain of the converter stages but the effect decreases as the resistance increases so large values are used Q4 derives the bias current from VB which is about 30Vdc R47 and R51 develop a voltage of around 2 4mA 10k 24V so the collector of Q4 operates at about 28V filtered by C93 The bias voltage at this point is common mode so any noise present is rejected to a high degree by the differential signal stages By eliminating dc bias in the output of the converters their usable range is available for developing a large audio signal which is favorable for achieving a high signal to noise ratio Full scale ac signal voltage at U14 1 is 9 8Vpeak 19dBu The sigma delta current from the D A has substantial components at fre
295. n master clock All local clocks I2S_FS 125 64FS 125 256 5 derived from this clock TMIX WCKI Input frequency is nominally 24 576Mhz or 22 5792Mhz for 48 96Khz and 44 1 88 2 sample rates respectively CKI 2 not used TMIX WCKI TMIX word clock Rising edge denotes start of octal frame Input frequency is 44 1Khz or 48Khz Not used Not used Not used Not used AD Frame Sync falling edge denotes start of frame Locally generated AD bit clock falling edge denotes start of bit period Locally generated AD MCLK signal Locally generated Description 125 audio data for channels 1 2 I2S audio data for channels 3 4 I2S audio data for channels 5 6 I2S audio data for channels 7 8 Octal data Drives TMIX1 Octal 0 Tristate control is determined by the octal select field in the AIN control register see register description for details TMIX Octal data Drives TMIX1 Octal 1 Tristate control is determined by the octal select field in the AIN control register see register description for details TMIX Octal data Drives TMIX1 Octal 2 Tristate control is determined by the octal select field in the AIN control register see register description for details TMIX Octal data Drives TMIX1 Octal 3 Tristate control is determined by the octal select field in the AIN control register see register description for details TMIX Octal data Drives TMIX1 Octal 10 Tristate control
296. n board connector uses Serial Port 3 of the SA 1100 This port is a combination synchronous data link controller SDLC and universal asynchronous receiver transmitter UART serial controller For LARC2 it is configured as a UART Power Supply Power Source sheet 7 The LARC2 operates from a source of 10 to 12VDC which may either come from the host 960L via the 9 pin HOST connector J20 or from a dc source connected to the EXT POWER jack J21 When connected to the regulated 12VDC supply in the 960L the LARC2 voltage at J20 will be lower due to IR losses in the 9 pin cable and this limits the length of cable that can successfully supply the operating current of 1 to 2 Amps A plug in J21 opens the switching contacts A amp B which disconnects the 12HOST and substitutes the external supply External power on the center pin of J20 pin D connects through FB3 and D4 D4 prevents damage due to a misconnected external power jack AC or the wrong polarity of DC Main 12V sheet 7 The voltage at the cathode of D4 connects through PS1 to become the main dc supply nominally 12V reduced by the diode drop PS1 is a 0 75 Amp self resetting thermally activated fuse Normally the fuse exhibits a low series resistance a few tenths of an ohm When overloaded by currents gt 1 5 the fuse undergoes self heating and switches to a high resistance state due to the thermal characteristics of its material This high resistance limits the current drawn
297. n is opposite at all instants of time The latched value is therefore opposite and in the touched state is constantly high The operation of the touch sense circuits for the other odd numbered faders is identical The even numbered circuits operate similarly but their excitation square wave is of the opposite phase This helps ensure proper touch sensing in the case where multiple knobs are touched simultaneously The states of DET 8 1 can be read by software via tri state buffer 024 and the FPGA 4 6 Joystick sheet 5 Channels 0 and 1 of A D converter U31 are used to digitize the position of the two axis joystick connected to J7 and J8 As with the faders the joystick is supplied with 5Vdc to produce position dependent X and Y dc voltages which are digitized by the two channels Piezo Transducer sheet 5 A piezoelectric ceramic transducer disk is mounted flat on the pc board under the Lexicon button When the button is pressed it not only makes contact with switch pattern SP47 it also produces flexure of the piezo element The resulting voltage is peak detected and amplified by U29 LM358 then digitized by A D U31 The amplitude of the piezoelectric voltage gives an indication of how hard the button was pressed which software can determine from the profile of the digitized waveform 4 8 Notes on A D Operation The A D reference and the potentiometer excitation voltages are the same so the digitized positi
298. n the PCI bus IDE hard drive IDE CDROM drive Floppy drive IO backplane and power distribution and management functions Communication between DSP cards and the IO cards in the system are provided over a Lexicon proprietary control and audio interface using a second set of PCI style connectors The following system block diagram highlights its place within the 960L system NLX CPU 32MB SDRAM 433MHZ CELERON 3 5 Floppy NLX Edge Connector RS232 Com1 RS232 Com2 Floppy Primary IDE a IDE Peripheral Buses NLX Backplane PCI Bus II i PCI DSP PCI DSP PCI DSP PCI DSP icd Slot3 BUS Slot2 BUS Slot BUS 500 BUS 10805 10805 Bottom Slot3 Slot2 Slot1 Top Slot0 Conn Conn MIDI Ensoniq MIDI Spare sit Spare sit Spare sit RVB mem IO Backplane Host Bus Address Data Control 7 pudo Bus Octals Clocks 2 db db Slot 2 Slot 3 System Block Diagram Circuit Description This section is a page by page description of the 960L NLX Backplane card schematic 7 1 960L Multi Channel Digital Effects System Service Manual NLX Interface Sheet
299. n two ways The 5v 12 rails come directly from the 960L power supply via connector J9 The 12 is supplied by the NLX backplane via connectors J11 sheet 1 MIDI The MIDI interface signals come from a MIDI card located on the NLX backplane Signals are carried over a 15 pin ribbon cable to connector J8 RS232 The two RS232 ports on the PC motherboard are connected to the IO backplane using 10 pin ribbon cables COM Port 1 connects connector J6 and COM Port 2 connects to connector J7 Miscellaneous The serial audio data signals TMIX1 SERD TMIX2 SERD are pulled up by resistors RA R10 R17 R23 Capacitors C2 C11 are bypass capacitors Clock Input Output and Clock Generator card The Clock card provides external interfaces and clock generation for the digital audio subsystems Interfaces for midi control and external wordclock sync are supported along with ports for the LARC2 remote control for the 960L Clocks can be derived from internal crystal timebases or from external sources via an on board Phase Locked Loop PLL The supported sampling rates are 44 1 or 48kHz in single speed mode or 88 2 96kHz in double speed mode Midi Interface On board signal conditioning circuitry interfaces external midi current loop signals with internal logic levels which connect to a midi adapter card located in slot 3 bottom slot of the NLX backplane Midi input on J3 MIDI INPUT is current limited
300. nces from existing between the 5V pins of the converters Dropping diodes in series with U3 reduces the operating voltage resulting in cooler operation 7 20 Lexicon Analog Output card The Analog Output card consists of eight channels of D A conversion and output circuitry sheets 1 4 bus interface fpga and connector sheets 5 6 and on board power conditioning sheet 7 This card is plugged into the IO backplane which is accessed from the rear of the 960L chassis The following system block diagram highlights its place within the 960L system Overview The basis for each channel of analog output is a single AD1853 sigma delta D A converter which converts 24 bit serial digital audio at its 125 port to differential analog current AD1853 is a two channel device applicable to conventional stereo conversion but as applied in this design the two channels are combined to form a single channel in order to achieve improved overall performance Within a single wordclock period the digital data pattern presented for the left channel is the inverse of the data for the right channel while the analog outputs are cross connected In this way one differential current pair is formed which is the in phase sum of currents resulting from two simultaneous conversions The differential current is converted to a differential voltage by low noise operational amplifier stages which drive a differential input two pole active filter stage The unbalanc
301. nd allows multiple commands or tests to be executed from a text based script file Commands are entered in the file as they would be on the command line The effect is very similar to a DOS batch file Several commands from the DOS world have been emulated here to facilitate writing maintaining and using script files Echo and Rem Like it s DOS equivalent Echo echos text following the command to display when the script is run The Rem command basically does nothing but allows emarks or comments to be added to the script file to help document what is going on Help The help command provides a list of tests available in the directory that you are in and also information about other commands 960L Multi Channel Digital Effects System Service Manual More HELP command The More command followed by help and then a test name displays extended help for the indicated command This displays the extended help information for the command entered on the command line after the word HELP If no command is specified it attempts to locate information on the previous command CD parameters The cd command changes the current directory level of the diagnostics Like it s DOS equivalent this command changes the current working directory When executed with a directory name as a parameter the directory is entered When executed with without the quotes the diagnostics go up a level stopping at the root LogFile The logfile command op
302. nd hold the REGISTER CONTROL keys while powering on the unit then release the keys after approximately 8 seconds This mode is used primarily for programming the LARC2 Boot ROM and Program Flash Memory during the manufacturing test process Refer to the Option Board Menu section of this document for more information 2 enter the Menu mode press and hold the PROGRAM MACHINE keys while powering on the unit This mode is used primarily for programming the LARC2 Boot ROM and Program Flash Memory when the LARC2 is connected to a 960L mainframe Refer to the 960L Diagnostics Descriptions document P N 010 13397 for more information Debug Port The text that is displayed on the LARC2 LCD display in these modes is also sent to the Debug port of the LARC2 Option Board when installed Connecting a RS 232 serial Debug terminal to the Debug port is an extremely useful tool for debugging purposes Another advantage of using the debug terminal is that the terminal keyboard can also be used to execute the Interactive Diagnostic tests on the LARC2 when the use of the keypad is not possible or impractical During the Power On Diagnostics diagnostic information is sent to the Debug port of the LARC2 Option Board when installed which is not displayed on LARC2 LCD display as shown in the example below NOTE In the example below a PCMCIA Ethernet Card was installed on the LARC2 Option Board and an External Keyboard was not
303. nd tests the ability of the Z80 to notify the 56301 of a new command The 56301 processor sends messages to the Z80s and the Z80s send messages to the 56301 through the DPRAM The DPRAMs have a special feature that facilitates this the last two addresses of the DPRAM trigger the INT pins when written to When address 7FE is written to from the right 56301 side the INTL pin goes low If the Z80 then writes to the same address the line returns high If the Z80 writes to address 7FF the INTR pin goes low If the 56301 then writes to the same address the line returns high The Z80 writes data to address 7FF of the DPRAM driving the INTR line low The INTR line feeds the interrupt pins of the 56301 The test resets the Z80 then loads a tiny Z80 program into the beginning of the DPRAM The Z80 program writes to DPRAM address 7FF which pulls the INTR pin of the DPRAM low triggering an interrupt on the 56301 then halts After loading the program into the DPRAM the PC releases the reset on the Z80 allowing the program to run The PC then continuously checks a memory location in the 56301 for a particular bit to be set indicating that a Z80 interrupt has occurred As soon as the PC detects the bit it clears it instructs the 56301 to write to address 7FF on the DPRAM to clear the INTR pin and reports the test as passed If the bit never goes high the PC eventually times out and an error is reported In order for this test to pass the INTR line must be co
304. nes Each address has 8 data bits and is one row within the matrix A bit that is set to 1 in the register indicates that the key is down 7 44 Lexicon Notes Lighted Num ROW COL Figure 4 1 Rows Columns Keypad Leds sheet 8 There are 12 keys on the keypads that are lighted The array of LEDs that illuminate the keypad is organized for scanning as 4 rows by 4 columns Under software control the array is driven by sequentially saturating one of the four column driver transistors Q4 Q6 One output of U6 74AC273 gets set to a logic low to sink base current for one transistor through the associated base resistor R26 R29 while the other three transistor control lines remain high keeping the other transistors off The transistor collectors drive the column lines LED G 3 0 sourcing the anodes of the LEDs the from the SVD power rail The cathodes of each column of LEDs connect through current limiting resistors R22 R25 to the remaining four outputs of UG the row drivers Within a driven column an LED lights when a row driver sinks current from its cathode Software asserts WR to load U6 with the appropriate sequence of row and column scanning patterns In reset all LEDs will be lit because all outputs of U6 are set low sourcing all anodes via the transistors and sinking current from all cathodes A D Converters There are two 8 channel 10 bit Analog To Digital converters TLV1548M on the main
305. nnected along with the dc power via J2 Logic level LCD VBR from the cpu switches transistor Q2 to set brightness control voltage VBR for two brightness levels from OVdc bright to 1 6Vdc dim Logic level LCD VRMT drives transistor Q1 to switch the on off control VRMT between 5 backlight on and ground backlight off Main 5V sheet 9 The main 5V logic supply is derived from 12 by switching regulator 040 LM2676 The switching pulse waveform at pin 1 SW of 040 is filtered by L1 and C15 to produce 5Vdc which is the average value of the pin 1 voltage The positive excursion of the switching pulse is produced by the series switch within U40 which connects 1 SW to pin 2 VIN which is the main 12V heavily decoupled by FB5 and associated capacitors When the switch is off the negative excursion of the switching pulse drops to a fraction of a volt below 0 determined by the forward voltage of catch diode D25 The switching frequency remains constant at around 260 kHz The regulator senses the filtered 5V fed back into pin 6 FB and varies the switching duty cycle to maintain regulation The switching regulator efficiently converts the relatively high voltage low current 10 to 12V input into the low voltage high current 5V output At lower input voltages the regulator draws more current to provide the constant power consumed by the 5V output load 3 3V and 2V sheet 9 The 3 3V logic supply is derived from the 5V by a fixed
306. nnected to the buffer feeding the interrupt pins of the 56301 The Z80 must be able to access the DPRAM memory and run programs and the mechanism within the DPRAM that triggers the INTR line going low must be functional for the test to pass Parameters CardID This number selects which reverb card to test Legal values are 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 28014 This specifies which 780 on the card to test Legal Values 0 and 1 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Notes following tests must pass before using this test 56301DpramTest Z80BootTest Z80DpramTest Z80 SRAM Test The syntax for the 780 SRAM Test is Z0 SramTest 2801 NumRepeats Tests the Z80 s SRAM and the Z80 s ability to access it This command loads alternately loads two small programs into the DPRAM for the Z80 which move data to write and from read Z80 memory space The test begins by filling the memory space under test with a specific data value then reading back the contents of each memory location confirming the data contained therein is correct Values of 0 OxFF OxAA 6 9 960L Multi Channel Digital Effects System Service Manual 0x55 are tested An address
307. nnector on the back of Hard Drive 2 With your DMM leads measure the voltages on the connector 3 Place the DMM ground lead on the Black wire connector and the DMM plus lead on the Yellow wire connector and verify the voltage is 12 VDC 6 VDC 4 Place the DMM ground lead on the Black wire connector and the DMM plus lead on the Red wire connector and verify the voltage is 5 VDC x 25 VDC For the following voltage tests an extender card part 023 14426 will be needed to bring the cards out of the mainframe in order to gain access to the test points called out in the following tests Analog Output Card Voltage Test The supplies being tested on this card will be the 12 VSUP and the 5VD provided by the main supply via the backplane and voltages 5VD 6 6V 18V 24V and 36V created on the card Before powering on the 960L for this test remove the Analog Output card from the rear of the chassis Insert the extender card and install the Analog Output card into the extender card Power on the 960L For your ground reference locate test point marked GND to the Left of U3 At the back right hand corner of the card locate the 12V test point just below FB2 Verify the voltage is 12VDC 1 2VDC Next locate the test point marked 12V just below FB3 Verify the voltage is 12VDC 6VDC Locate the 5VD voltage test point left side of the card just above U6 Verify the voltage is 5VDC 25VDC 8 Locate th
308. not selected DATA STROBE data is captured on rising edge of DS WRIRD 0 write operation 1 read operation Address 0 select which register is written read to from see register description section Not used Not used Not used Not used Not used Not used Not used Data Bus lt 7 gt data is written read over this bus Data Bus 6 data 15 written read over this bus Data Bus 5 data is written read over this bus Data Bus lt 4 gt data is written read over this bus Data Bus 3 data is written read over this bus Data Bus 2 data is written read over this bus Data Bus 1 data 15 written read over this bus Data Bus 0 data is written read over this bus 13 78 2 51 TMIX_WCKI 7 IOBUS_WCLK 35 IOBUS_64FS 10 IOBUS_128FS 57 IOBUS_256FS 8 125 5 37 125 64 5 9 125 256FS Serial Audio 3 1250 4 1251 5 1252 6 1253 19 SDOO 18 SDO1 14 SDO2 20 SDO3 24 004 25 005 Audio Control 27 CONV_RESET 26 28 DFS1 DFS0 FPGA Support 32 MODE 55 PROG 73 CCLK 53 DONE 41 INIT 71 DIN 15 16 TDI TCK TMS 17 75 TDO INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT Type INPUT INPUT INPUT INPUT OUTPUT TRISTATE OUTPUT TRISTATE OUTPUT TRISTATE OUTPUT TRISTATE OUTPUT TRISTATE OUTPUT TRISTATE OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT OUTPUT INPUT INPUT OUTPUT Lexico
309. nt the 12V which in a perfect pump would make VB 36V neglecting losses In practice VB is somewhat over 30V at its normal load of approximately 40mA 16 2 4mA 7 27 960L Multi Channel Digital Effects System Service Manual AES card Introduction This section describes the theory of operation of the 960L AES card Overview 960L AES Card supports eight channels of AES digital audio I O at 44 1KHz 48KHz and 88 2 KHz 96 kHz The AES inputs are received using four Crystal CS8413 digital audio receivers and the outputs are driven with four CS8403A digital audio transmitters The receivers pass 125 audio to the AES FPGA which packs the eight samples into octal serial streams that interface to the Reverb Card via the Bus transmitters receive 125 audio from the FPGA These 125 streams are unpacked from octal serial streams that are sent from the Reverb Card The FPGA contains control and status registers as do the AES devices which are accessed by the Reverb Card via the Bus Figure 1 1 is a block diagram of the 960L AES card Address Bus Data Bus N Ly AES AES AES AES AES RX RX RX TX TX Figure 1 1 AES Card Block Diagram 7 28 Lexicon Circuit Description This section is a page by page description of the 960L AES card schematic Crystal RX TX Devices sheets 1 4 Sheet 1 of the schematic shows a single Crystal receiver and transmitter and associated support circuitry Sheets 2
310. o checks the size of the card so that it will not attempt to test memory that isn t present Then it performs the following tests as shown in the example below NOTE In the example below the information sent to the Debug port was captured using a Debug Terminal The comments added below describe the operations that are performed during the test Checking Card Type Card Type 1 Testing PCCard flash memory of size 0x2000000 33554432 decimal Erasing Flash PCcard This takes a few moments Erasing block 0 This portion of the test erases the PCMCIA Flash Memory card Erasing block 1 Erasing block 2 Erasing block 4 Erasing block 8 Erasing block 16 Erasing block 32 Erasing block 64 Erasing block 128 This portion of the test verifies the address lines on the PCMCIA Flash Memory card are functioning properly by writing a walking 1 s pattern across the address lines During the test the current address values are written to memory then the same memory locations are read to verify the data written in these locations is correct If any errors are detected the failure results are reported and the test then waits for acknowledgement of the error NOTE The first address bit is not tested because the test is writing 16 bit values 6 44 Writing to 0 3 000000 Writing to 0x3c000002 Writing to 0x3c000004 Writing to 0x3c000008 Writing to 0x3c000010 Writing to 0x3c000020 Writing to 0x3c000040 Writing to 0x3c000080 Writing to 0x3c00010
311. oard verify that the right notched edge of the motherboard is almost against the NLX connector on the NLX backplane and that the threaded standoffs in the front of the chassis are up against the slot cutout of the motherboard support bracket If the 960L still won t boot and the power supplies are good and a known good motherboard is installed correctly the next thing to verify is the reverb card After that verify the CD ROM hard disk drive and floppy drive are working 960L Functional Diagnostic Descriptions NOTE The nomenclature for the four Lexichip3s on the reverb card will be Lexichip3 followed by a space and then the number of the Lexchip3 The 960L functional diagnostics verify that the 960L can pass MIDI data from the Out to In ports the two serial ports function most of the reverb card functions and the cards in the I O cage can read and write to registers on their respective FPGA s or CPLD The following sections describe the diagnostic tests available The syntax for the diagnostics is listed in the first line For troubleshooting purposes a PS 2 keyboard can be connected to the LARC2 prior to powering on the 960L and individual diagnostic tests can be executed any number of times by typing the diagnostic test name followed with the optional number of times desired 0 entered means to run the test forever until a key is pressed on the keyboard If no number is entered the test runs once and stops This is the default version Th
312. ode it should use These resistors set the 56301 to boot from the Boot PROM U18 After the 56301 is initialized it enables the DSP Interrupt Buffer using the signal which passes the interrupt requests to the 56301 T MIX 3 sheet 7 T MIX 3 shown on sheet 7 transfers serial digital audio to the four Lexichips the Reverb Card These digital audio streams are formatted with four audio samples per word clock These audio streams are the LEXI n SER IN and the LEXI n SER OUT signals The LEXI WCLK IN signal driven from U38 is the word clock signal for the four Lexichips The SPOO 7 signals on the T MIX are general purpose pins that are used to drive the signals Z80 INIT1 and Z80 INIT2 These are the reset signals to the Z80 microprocessors The Z80 Lexichip Interface GAL U26 contains the glue logic to connect the Z80s to the Lexichips It generates chip select and memory request signals and also generates the ZWAIT1 and ZWAIT2 signals which are signals that are sent to the Z80s to extend data transfer cycles as required by the Lexichips Z 80 1 sheet 8 280 1 and its associated local SRAM and dual port SRAM are shown on sheet 8 This Z80 U33 is the control processor for the Lexichip 1 amp 2 reverb engines 040 046 Its address and data lines are connected directly to both the local SRAM and dual port SRAM and the chip selects for these SRAMs generated by Lexichip 1 DPORT 1 CS SRAM1 5 The dual p
313. on information from the potentiometers is a ratiometric measurement insensitive to the exact value of the 5V excitation In contrast the accuracy of both the 12V sense and the piezo transducer channels do depend on the accuracy of 5VA which is 5 The hardware controlled interface implemented in the FPGA produces all the A D control words clock and chip selects The serial bit clock rate is 2MHz The entire A D scan cycle takes 200usec so each channel is 7 47 960L Multi Channel Digital Effects System Service Manual sampled 5000 times per second The serial data is stored in parallel form in a memory block within the FPGA where software can read it via the FPGA parallel port as necessary PS 2 Keyboard Interface sheet 7 The PS 2 port 719 allows the user to connect a PS 2 compatible keyboard to LARC2 Clock and bidirectional data are driven by open collector nand gate U1 74ALS38 Logic within the FPGA receives incoming serial data from the keyboard checks the parity and presents the data to the system as a byte of data at address 0 1000 0700 The controller does not translate the scan codes The controller also passes command information serially with parity appended to the auxiliary device through address 0x1000 0700 A read only status register resides at 0x1000 0704 The PS 2 controller is a pass through interface and does not support any of the controller commands Input and Output Registers The output buffer is an 8 bit r
314. on Functional Diagnostic Test Scripts and in the Functional Diagnostic Descriptions custom test scripts can be implemented and individual tests can be performed to troubleshoot defective 960Ls In order to perform these actions a PS 2 keyboard must be connected to the LARC2 prior to powering on the 960L See these sections for information on how to use the keyboard to perform these functions MIDI Troubleshooting Tool MIDI Send The syntax to send MIDI data is MIDISend data This tool outputs MIDI General MIDI messages This command sends data to the MIDI output device Currently only general MIDI messages are supported no SysEx NOTE Data must be in the hex format Example MIDISend CO 00 Sends a MIDI program change message on channel 1 for program 1 0 MIDI Information The syntax to get MIDI information is MIDIInfo no parameters This tool displays information about MIDI devices in the system This command displays information about the MIDI devices in the system It takes about a second to process the command Serial Port Troubleshooting Tools Send Serial Data The syntax to send serial data is SerialSend data 6 16 Lexicon This tool sends serial data bytes out the serial port This is a debugging tool that allows data to be sent out the serial port Up to 15 bytes can be sent at a time Set the Serial Port The syntax to set the serial port is SerialSetPort port num This tool sets the active s
315. onitors the rise of the 3 3V logic supply Once it rises above 2 97V within 10 of 3 3 V RESET remains asserted for an additional 350msec allowing circuitry to stabilize at nominal operating voltage in the reset state When the RESET signal is asserted low SA 1100 stops executing instructions asserts the RESET OUT pin and then performs idle cycles on the bus When the RESET is negated SA 1100 does the following 1 Forces the internal program counter to fetch the next instruction from address Oh0000 0000 2 Based on the state of ROM SEL pin fetches the instruction from either 16 bit ROM SEL low or 32 bit space ROM SEL high Main Memory sheet 2 DRAM 011 017 sheet 2 LARC2 uses two 64 Mbyte 60 ns EDO DRAM chips organized as 1 bank x 4 M Words x 32 bits giving the system 16 MBytes of DRAM The memory occupies address space 0 000 0000 to OxCOFF FFFF The following table lists the memory transactions that are supported Bus Operation Burst Starting Description Size Address Bits 4 2 Generated by core DMA or read buffer request 7 41 960L Multi Channel Digital Effects System Service Manual Read burst Generated by read buffer or DMA request 4 Read burst Generated by cache line fills or read buffer requests Write single 1 ny 1 4 bytes are written as specified by byte mask Generated by write buffer or DMA request All four bytes of each word are written 6 Generated by write buffer or DMA reque
316. ors EE ros S gr vivo 34 yers gL INAANO 2 s jen arg 3 39000 50032 OWaat 3r ON 8 Es w ros 1 Wad 6 sr eno rors suy Juv Ot g 9 nnno MINIS UE misa asl 1 9 9 4 gr ova 708 vin gno Zon asl uno 36000 2 n 02 01 683 lt rors 39022 1 rgo 4 1210 rg 9817 Las ney 264 log 60 F Sa 00902 00542 Wed 1921 We 992 zortizooo O03 wad 28 9 SLHS aa0NVHO 183 31 ool NOS 4 HA 00011000003 S133HS G3ONVHO 2 WAS OOM 686021 Nid UU LNdLNO 431843ANOO 5 NOISM3ANOO VIG 10102168 X90 HW HIN L 2 S 9 2 8 9 25
317. ort SRAM is initialized with the 280 start up code by the 56301 using the port shown on the right hand side of the chip symbol The Z80 accesses this SRAM using the port on the left hand side of the chip symbol Message passing between the 7 35 960L Multi Channel Digital Effects System Service Manual 56301 and the Z 80 is also accomplished through this dual port SRAM Address 7FF in the dual port SRAM is used to generate an interrupt to the 56301 DB MAS INTO The 56301 then reads this address which is written with interrupt vector data by the Z 80 The interrupt is cleared when this address is read by the 56301 In a similar fashion address 7FE in the dual port SRAM is used by the 56301 as an address to create an interrupt to the Z 80 MAS DB INTO The description of this page also applies to Z80 2 and its associated SRAM shown on sheet 11 Lexichip 1 sheet 9 Lexichip 1 040 and its associated DRAM 041 are shown on sheet 9 Lexichip processes serial digital audio that is received on the LEXI1 SER signal that is sent from T MIX 3 Serial digital audio is passed from Lexichip 1 to Lexichip 2 through the LEXI1 TO LEXI2 SER signal and serial audio is returned via the LEXI2 TO LEXI1 SER signal Finally serial audio is returned after processing to T MIX 3 on the LEXI1 SER OUT signal completing the audio data path through this group of two Lexichips Serial audio is shifted in and out of the Lexichips using the LEXI 256FS clock
318. path Three audio paths are tested Analog in to digital out A D digital in to analog out D A and analog in to analog out A A Digital in to digital out D D is not tested directly during manufacturing proof of performance but is available as a troubleshooting tool to repair defective AES cards User Audio Testing The user will be processing audio through the 960L and LARC2 and a system all the time The user will always be evaluating audio performance of the system If the user detects a problem the hardware diagnostics can be executed to see if the hardware is working If however a problem is not detected then if the user has the necessary equipment the Audio program can be executed to see if the 960L and LARC2 versus something else in the users system is the problem Functional Diagnostic Test Scripts Resident Scripts To perform the functional diagnostics scripting files in ASCII text are executed These files function like DOS batch files in that they contain the test or list of tests to be executed one after the other There are 10 built in resident scripts They are executed by pressing the corresponding numbered button on the LARC2 and then pressing the ENTER button For example to run the script number 3 press the 3 button and then press the ENTER button The 10 scripts that are resident with the 960L are described as follows Script 0 Lists the menu displays a list of available scripts on the LARC2 Script 1
319. peats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Lexichip3 Tests Lexichip3 WCS Test The syntax for the Lexichip3 WCS Test is Lexichip3WCSTest 2801 Lexichip3ld NumRepeats This is a memory test of the WCS program memory on the Lexichip3 This test confirms that the Z80 can access all of the Lexichip3 s WCS program memory space The test begins by filling the memory space under test with a specific data value then reading back the contents of each memory location confirming the data contained therein is correct Values of 0 OxFF and 0x55 are tested An address test is also run that writes each address value into its associated memory location address 29 has the value 29 written into it address 30 has the value 30 written into it etc If this test fails but the Z80BootTest and Z80DpramTest pass there is probably a problem with the address data or control lines between the Lexichip3 and the Z80 Parameters 6 10 Lexicon CardID This number selects which reverb card to test Legal values are 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 28014 This specifies which 280 on the card associated with a pair of Lexichip3 s to test Legal Values 0 and 1 Lexichip3ld This specif
320. pecific Z80 via the 56301 This command performs a memory test on the dual port RAM DPRAM associated with a particular Z80 on a particular reverb card Values of 0 0xFF 0xAA and 0x55 are written to the DPRAM via the 56301 then read back and confirmed An address test is also run that writes each address value into its associated memory location address 29 has the value 29 written into it address 30 has the value 30 written into it etc This test confirms that the 56301 can access all of the DPRAM memory If this test fails there is a problem with the address data or control lines between the 56301 and the DPRAM Parameters This number selects which reverb card to test Legal values 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 2801 This specifies which DPRAM associated with particular 280 test Legal Values 0 1 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running 56301 to Z80 Test The syntax for the 56301 to 280 test is 56 280 Cardid 2801 NumRepeats Tests the 56301 s ability to notify the Z80 of a command This command tests the ability of the 56301 to notify the 280 of a new command 56301 processor sends message
321. perform the test the data and address values the tiny 280 program are modified repeatedly to fill the DPRAM with specific data which the PC reads back via the 56301 side of the DPRAM and checks Values of 0 OxFF and 0x55 are tested An address test is also run that writes each address value into its associated memory location address 29 has the value 29 written into it address 30 has the value 30 written into it etc If this test fails but the 280 1 passes there is probably a problem with the hi address lines between the Z80 and the DPRAM Parameters This number selects which to test Legal values 0 1 since only two reverb cards will be supported If only one card is present use the number 0 28014 6 8 Lexicon This specifies which Z80 on the card to reset Legal Values are 0 and 1 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Notes This test explicitly does NOT make use of the interrupt command lines INTL INTR It is assumed that the DPRAM Test which accesses the DPRAM from the 56301 side passes Z80 to 56301 Tests The syntax for the 280 to 56301 Test is Z80To56kCmdTest 2801 NumRepeats Tests the Z80 s ability to notify the 56301 of a command This comma
322. play should always be drawn in the same direction as the joystick up down amp left right movement This test is useful for verifying the correct wiring of the Joystick NOTE During the test the Meter Board RED and GRN LED s act as a level meter which displays the values read X Y position from the joysticks A D converter 1 8 Max for troubleshooting purposes 38 Lexicon The RED LED s indicate the Left Right position of the joystick and the GRN LED s indicate the UP DOWN position of the joystick When a failure has occurred an error message is sent to the LCD display and also to the Debug Port as shown in the example below Test invalid Did not test edges enough Joystick touched inner boundary Be careful not to move joystick away from the edges after beginning test Press or Enter on debug port key to acknowledge Press the key the LARC2 or press ENTER on the Debug Terminal to continue NOTE During the test there is a special mode that is available for debugging purposes which sends the values read X Y position from the joysticks A D converter to the LCD display when the CONTROL key is pressed as shown in the example below Horzntl 1023 Vertical 118 Fader Motor Test is test has been designed to verify the ability of the Fader and Motor circuitry to detect the current position of the fader then move the fader in the proper direction until it has reached the n
323. quencies well above the audio band and C121 C95 and C94 are important for accommodating and reducing this high frequency content in the conversion Filter U22 and associated components form a 2 pole multiple feedback active filter that further reduces the non audio content of the analog output This filter has a characteristic lying between Bessel and Butterworth with a 3dB frequency around 120kHz The overall filter characteristic of the channel is designed to have a flat frequency response well within 0 5dB out to 40kHz and to exhibit a transient response consistent with the enhanced temporal spatial resolution available at the double speed 88 2 96kHz sampling rates Mid band gain is around 0 45 6 9dB producing a full scale CH1 signal of about 18dBu 8 7Vpeak Output Driver The output of the filter is ac coupled by C157 to 026 a monolithic transformerless differential output line driver DRV134 The differential output is fed back via dc blocking capacitors C165 C166 to its sense inputs The driver has an output impedance of 50ohms and a nominal voltage gain of 6dB when driving 600ohms With this low output impedance the output level with and without a 600ohm load dBm vs dBu differs by 1dB Full scale output is nominally 24dBm and the transformerless characteristic makes signal level insensitive to load imbalance high common mode output impedance C181 placed directly across the 50 ohm differential output forms the fin
324. r serial testing So the serial Port1 test will fail and the serial port 2 test will pass if the circuit is functioning The system test all script script number 1 only tests serial port2 This test performs a test of the serial ports of the 960L This command tests the currently selected serial port The test sends the hex values 00 FF 55 and AA out the designated port TxD and attempts to read them back RxD The port settings can be set in the Global Settings under the Help menu If Terminal mode is enabled the diagnostic serial tests will fail The terminal mode is for LARC2 communication with the 960L The default settings are for terminal mode or LARC2 communication on port 1 and serial test enabled on port 2 An optional NumRepeats value can be entered on the command line When this is done the test is repeated that number of times before reporting an error A value of 0 repeats infinitely This can be useful for debugging serial port problems Reverb Card Tests The reverb card tests consist of testing the various parts of the reverb card These are the 56301 the 56301 to 280 DPRAM Dual Port RAM the 2 2805 the 780 SRAM static RAM the 4 Lexichip3s and the 3 TMIX chips 56301 Tests The following reverb card tests check the 56301 DSP PCI Interface chip 56301 DPRAM Test The syntax for the 56301 to dual port RAM test is DPRAMTest Cardld Z80ID NumRepeats 6 6 Lexicon Tests the Dual Port RAM associated with a s
325. r the user to refer to the instruction manual in order to protect against damage to the instrument indicates dangerous voltage Terminals fed from the interior by voltage exceed ing 1000 volts must be so marked The WARNING sign denotes a hazard it calis attention to a procedure practice condition orthe like which if not correctly performed or adhered to could result in injury or death to personnel The CAUTION sign denotes a hazard It calis attention to an operating procedure practice condition orthe like which if not correctly performed or adhered to could result in damage to or destruction of part or ali of the product The NOTE sign denotes important infor mation it calls attention to procedure practice condition or the like which is essential to highlight NOTE CAUTION Electrostatic Discharge 5 Precautions The following practices minimize possible damage to ICs resulting from electrostatic discharge or improper inser tion Keep parts in original containers until ready for use e Avoid having plastic vinyl or styrofoam in the work area Wear an anti static wrist strap Discharge personal static before handling devices Remove and insert boards with care When removing boards handle only by non conduc tive surfaces and never touch open edge connectors except at a static free workstation Minimize handling of ICs Handle each by its body
326. rds located on the NLX Backplane and the system clock and control and audio IO cards which comprise a 960L effects system It also connects via ribbon cables the PC motherboard RS232 serial and MIDI ports to the IOCLK PCB The following system block diagram highlights its place within the 960L system 6GB T CRDOM 3 5 Floppy Edge Connector Primary IDE Secondary IDE Floppy Peripheral Buses NLX Backplane NLX CPU 32MB SDRAM 433MHZ CELERON RS232 Com1 5232 Com2 PCI Bus DSP Bus 11111 E DSP DSP PCI DSP BUS BUS Slot0 BUS Slot2 Slot1 Top Slot0 IO Backplane DSP BUS Slot3 MIDI Ensoniq MIDI Host Bus Address Data Control Bus Octals 1 LL Slot 2 Slot 3 System Block Diagram Lexicon MIIDI Mains voltage In Out Thru Remotes selector Mains power Word Clock connectLARC2to optional per PS Mfr switch Option plate In Out Loop porti vary per PS Mir Analog In AES In Option plate IEC power balanced XLR XLR channel pairs connector Analog Out AES Out may vary per PS Wir balanced XLR XLR channel pairs Figure 1 1 960L Rear Panel The IO Backplane supports five uniquely addres
327. ress decodes are assigned to AAO BUS 16 wait states T MIX Host bus Dual Port Ram Boot PROM 8 wait states AA2 T MIX devices DSP bus 3 wait states AA3 Not Used DSP 56301 Interrupts The 56301 external interrupts are assigned as follows IRQA Word Clock Interrupt IRQB I O Bus Interrupt not used IRQC Dual Port Ram Interrupt from 280 1 IRQD Dual Port Ram Interrupt from 280 2 56301 SCLK Output The 56301 SCLK output is used to supply a clock to the T MIX devices at start up through the mux U45 on sheet 15 This clock is needed at start up because the TMIX_CKI signal may not be available when the T MIX devices are initialized After the TMIX_512FS signal becomes available the 56301 switches the mux DSP 56301 Timers The 56301 has three timers that use the pins TIOO TIO1 2 TIOO receives the PREVIEW_CLKS signal which is a word clock signal that is sourced from any of the available word clock sources in the 960L The timer measures this signal and the result is used by software to determine if the selected word clock frequency is acceptable This clock is not necessarily the one the system is currently using TIO1 receives the TOT WCK signal which is the word clock the system is currently using TIO2 is a watchdog timer output from the 56301 56301 Data amp Address Buffers sheet 3 The DSP bus is used the 56301 to access the T MIX devices the Z80s and is the pathway
328. rial PROM U3 Bus Buffers sheet 6 The buffers to interface the AES card to the I O Bus are shown on sheet 6 Bus Connector sheet 7 The I O Bus connector J1 is a 96 pin Euro DIN connector that is used to interface the AES card to the Reverb Card Bypass Caps and Ground Jumpers sheet 8 The chassis ground signal ground jumpers shown on sheet 8 should be installed to connect chassis ground to signal at the AES card to meet EMC requirements Startup Sequence At power up the AES FPGA clocks in serial configuration data from its companion SPROM This program is used by the FPGA to configure its internal gates and memory to perform the desired functions for the AES card After the FPGA has successfully configured itself it illuminates the DONE LED D1 sheet 6 The AES card is now ready to respond to a request from the Reverb Card to identify itself This process consists of the Reverb Card reading the configuration register in the AES FPGA which is set a value of 32 hex This tells the Reverb Card that this is an AES card in this slot on the I O bus and the Reverb Card then programs the FPGA registers and the registers in the Crystal devices for card to operate The AES card is accessed periodically by software during normal operation to poll the status of the incoming AES audio data streams for errors and the Reverb Card also accesses the AES card registers to perform the sequence required when locking the 960L sample clock
329. rs NEC Section 810 21 Ground Clamps lt Power Service Grounding Electrode System NEC National Electrical Code NEC Art 250 Part 1 42 25 22 9601 Multi Channel Digital Effects System Service Manual SAFETY SUMMARY The following general safety precautions must be observed during all phases of operation service and repair of this instrument Failure to comply with these precautions or with specific warnings elsewhere inthese instructions violates safety standards of design manufacture and intended use of the instrument Lexicon assumes no liability for the customer s failure to comply with these requirements GROUND THE INSTRUMENT To minimize shock hazard the instrument chassis and cabi net must be connected to an electrical ground The instru ment is equipped with a three conductor AC power cable The power cable must either be plugged into an approved three contact electrical outlet or used with a three contact to two contact adapter with the grounding wire green firmly connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet international Electrotechnical Commission IEC safety standards DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE Do not operate the instrument in the presence of flammable gases or fumes Operation of any electrical instrument in Such an environment constitutes a definite safety hazard
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331. s When UP is low D3 is forward biased and current flows through R9 charging the integrator capacitors As the voltage rises 50 does the frequency and eventually the feedback action of the loop reduces the low frequency lagging phase error to zero The loop is satisfied and no further phase error occurs so no further change to the VCO output occurs which is the locked condition described above A similar description applies to approach from the opposite direction The magnitude of the up and down current pulses is nominally the same due to the 2 5V bias at the non inverting input of U6 If the VCO voltage at the cathode of D7 drops below 1 7V the varactor begins to forward bias and the VCO may completely cease to oscillate D2 in the feedback path of U6 limits the VCO voltage to a low value of about 1 8V to ensure that the VCO always oscillates At normal VCO operating voltages D2 is reverse biased and has negligible effect Jitter To a degree a PLL locks to the average of the reference frequency rejecting short term variations in phase or jitter The ability of the loop to track or reject variations in the reference phase is characterized by its jitter gain as a function of jitter frequency This PLL is a second order system Its jitter gain is slightly overdamped due to R12 with a corner frequency around 150Hz principally determined by C20 in conjunction with the dc gain around the loop The jitter gain of the PLL and the intrinsic j
332. s filter on the distortion analyzer Lower the input by 60dB to 61dBFS Verify the THD N at the 1 output to be lt 110 dB Move the audio output cable to the 2 Output and repeat the test Repeat the test for the remaining Input Outputs pairs 3 4 5 6 and 7 8 Functional Tests Midi Tests Setup 1 This test will require 1 Midi cable The cable is connected to the Midi In and Out connector on the back of the 960L creating a loop that the internal diagnostics requires to perform the test 2 The 960L must first be placed into Diagnostic mode This is done by powering on the 960L s main power switch on the rear panel then immediately pressing and holding down the Program and Machine buttons on the LARC2 for 2 seconds When the LARC2 displays Requesting Menu Mode the buttons can be released The display will take about two minutes then it should state the following 960L Boot Menu Version Speed BIOS date H Note are placeholders for actual values which may vary 1 Run 960L 2 Update 960L Software 3 Update LARC2 Boot ROM 4 Update LARC2 5 960L Diagnostics Can t lock CD Drive Access is denied 3 Press the 5 button to enter the Diagnostics 4 The display will scroll through some information then settle At the bottom of the display it will read Press 0 for a list of tests 5 Press the 9 on the LARC2 then the Enter button 6 If the Midi circuitry is good the display will read MID
333. s menu selection is used to download the LARC2 Boot ROM boot rom and or Program Flash image larc2 rom via the Debug Port on the LARC2 Option Board using the Zmodem transfer protocol O Option Board Test This menu selection is used to execute the Option Board Test from the Option Board Menu NOTE The remaining selections available from the Option Board Menu were designed specifically for use during the LARC2 hardware development and are outside the scope of this document 6 43 960L Multi Channel Digital Effects System Service Manual MISCELLANEOUS TESTS Option Board Test The Option Board Test was designed for debugging problems encountered when programming the Program Flash memory by verifying the operation of the PCMCIA interface This test resides in the Option Board Menu and requires the LARC2 Option Board with 32MB PCMCIA Flash Memory card installed in the Option Board Connector on the LARC2 The Option Board Test can only be executed from a Debug Terminal connected to the Debug port of the LARC2 Option Board When executed the test checks for the presence of the PCMCIA Flash Memory card first by checking the card type If there is no PCMCIA Flash Memory card installed it reports that fact and will not run any further Then it checks the header of the PCMCIA Card for the existence of a legitimate 960L application and warns if a header is present with the option to quit or continue destroying the cards contents It als
334. s to the 2805 through the DPRAM The 5 have a special feature that facilitates this the last two addresses of the DPRAM trigger the INT pins when written to When address 7FE is written to from the right 56301 side the INTL pin goes low If the Z80 then writes to the same address the line returns high If the Z80 writes to address 7FF the INTR pin goes low If the 56301 then writes to the same address the line returns high The 56301 writes data to address 7FE of the DPRAM driving the INTL line low The INTL line feeds pin 54 M R ofthe Lexichip3 which can then be read via the Lexichip3 by the Z80 Before any of this however atiny program is loaded into the DPRAM for the Z80 to run which has the Z80 constantly reading address Ox3B18 in the Lexichip3 and checking for a low on bit 6 of the data it gets back Address 0x3B18 is the location in the Lexichip3 in which the INTL pin s state is stored at bit 6 When bit 6 goes low the program writes OxAA into address 0x0014 of the DPRAM which the 56301 reads to confirm that the message was received If the value at address 0x0014 of the DPRAM is not OxAA then the Z80 did not detect a message from the 56301 and the test fails In order for this test to pass the INTL line must be connected to pin 54 of the Lexichip3 The Z80 must also be able to read from the Lexichip3 s memory so the address and data lines between the Z80 and the Lexichip3 must be intact Obviously the mechanism within the
335. sable card slots which are accessed from the rear of the 960L chassis Fig 1 1 With the exception of the slot address decodes the interface signals to each slot is identical However because of mechanical and specific electrical constraints not all cards can or should be randomly located The recommended slot ordering is Slot 1 top IO Clock Slot 2 Spare Slot Slot 3 AES PCB Slot 4 AIN PCB Slot 5 bottom AOUT PCB Table 1 1 Recommended Rear Panel Slot Ordering The most critically placed is the IO Clock card This card supplies the master bit TMIX and word clock TMIX WCKI for the entire system and needs to be located in the topmost slot to drive one end of the transmission line Note 256FS 128 5 64 5 and FS clocks are also available but are not currently used by any IO card Circuit Description This section is a page by page description of the 960L IO Backplane card schematic Sheet 1 NLX to IO Backplane Connectors Sheet 1 The NLX backplane and the IO backplanes are connected by two 40 pin ribbon cables which connect to J10 and J11 This interface is comprised of an 8 bit non multiplexed address and data system control bus 7 5 960L Multi Channel Digital Effects System Service Manual and serial audio data and clock signals R15 R16 and C1 provide filtering for the SYSTEM RESET signal provided by the DSP cards The cards in the IO backplane can
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337. service please include the following information Name Company Name Street Address City State Zip Code Country Telephone number including area code and country code where applicable Serial Number of the unit Description of the problem Preferred method of return shipment Return Authorization on both the inside and outside of the package Please enclose a brief note describing any conversations with Lexicon personnel indicate the name of the person at Lexicon and give the name and telephone daytime number of the person directly responsible for maintaining the unit Do not include accessories such as manuals audio cables footswitches etc with the unit unless specifically requested to do so by Lexicon Customer Service personnel 2 1 Chapter 3 Specifications 960L Mainframe Analog Input Connectors Eight Female XLR Impedance 50Kohm balanced Level for 0 dbFS 24dBu Freq Response 48K 20Hz 20KHz 1db Freq Response 96K 20Hz 40KHz 1db A D Conversion 24 bits 128x oversampled A D Dyn Range gt 110 dB 20 20kHz THD lt 002 CMRR gt 50db Crosstalk 1Khz lt 100dB Analog Output Connectors Eight Male XLR Impedance 50 Ohm balanced Level at 0 dbFS 24dBu Freq Response 48K 20 2 20 1db Freq Response 96K 20Hz 40Khz 1db D A Conversion 24 bits 8x oversampled 44 1 48Khz 4x oversampled 88 2 96Khz D A Dyn Range gt 110 dB 20 20kHz THD lt 002 Crosstalk 1Khz lt
338. set Motor Power 12V Sensing sheet 5 Channel 2 of A D U31 receives a voltage proportional to the main 12V scaled by 1 3 by the voltage divider formed by R120 R121 The voltage divider scales supply voltages from 0 to 15V to be within the 0 5V range of the A D Since LARC2 can be powered from the 960L or from the optional Power Pack 12 volts can vary This provides software with a means to monitor the voltage for the motor drivers The output waveform can then be adjusted accordingly The 12V sense register is cleared upon power on or after a software reset Fader Nulling Automatic nulling of a fader is based on a software feedback loop When it is time to move the faders algorithms within the code calculate the difference between the desired target position and the current A D position data and issue appropriate control waveforms to the motors factoring in the measurement of the actual motor supply voltage 7 46 Lexicon Fader Touch sensing sheet 6 Each motorized fader is equipped with an electrically conductive knob which connects to a terminal of the fader through a sliding track This feature makes it possible to sense when a knob is touched by an operator When an operator touches the knob the apparent capacitance at the terminal increases due to the added capacitance of the operators body This additional capacitance is detected in a bridge circuit where the apparent capacitance of the touch track is compared with a
339. st NE MEM All four bytes of each word are written Generated by write buffer or DMA request Write burst 4 All four bytes of each word are written Generated by write buffer or DMA request Write burst 8 0 Cache line copyback All 32 bytes are written Table 3 1 SA 1100 Transactions Refresh timing The SA 1100 provides support for a CAS before RAS CBR refresh cycle which is shown below an Ses n SA RAS Figure 3 1 Refresh Timing 7 42 Lexicon Read Write timing cpu LLL ADDR Fowa j__J SA_RAS A SAXD ST s Reads SA_OE Mem DQ C X Writes SA WE Mem DQ MDCASO 1100 0001 1111 0000 0111 1100 0001 1111 MDCAS1 1111 0000 0111 1100 0001 1111 0000 0111 MDCAS2 1111 1111 1111 1111 0000 0111 1100 0001 MDCNFG TRP 4 MDCNFG CDB2 0 TDL 00 Figure 3 2 Dram Single Transactions MEM CLK SA_ADDR SA_RAS 22 05 52272222 220 2024 0111 Reads Mem DQ Writes SA WE Mem DQ MDCAS1 1100 0 1100 1100 1100 1100 1100 1100 1100 0111 MDCNFG TRP 4 MDCNFG CDB2 0 TDL 00 Figure 3 3 Dram Burst Transactions Boot Flash U12 sheet 2 The Boot Flash is a 1 Mbit 3 Volt Flash memory organized as 64 k words by 16 bits The chip is mounted
340. st Memory Test crono RB 6 41 960L Multi Channel Digital Effects System Service Manual OPTION BOARD Menu The following selections are available from the Option Board Menu mode when the LARC2 Option Board is installed in the LARC2 and is connected to a debug terminal as shown below LARCZ Menu file built 11 2000 14 52 36 Bootrom Version 0 13 REESE 1 Display Register X Download via XModem 21 Set Register F Flash Operations 3 Dump Memory K Keyboard Echo 41 Set Memory D Interactive Diagnostics 5 Erase FLASH I Enable Interrupts 7 Display Ethernet Information L Loop on read 8 Set Up Ethernet Information 81 Diagnostics Suite 9 Download Image Via Ethernet ESHELL 21 zModem Download Load from PCMCIA Flash O Option Board Test B Boot 8 90000000 C Fill Memory with Pattern gt gt NOTE top line of the Interactive Diagnostics menu displays the date time of the Boot build and line 2 displays the Boot ROM version the actual text may vary Descriptions for the most commonly used selections available from the Option Board Menu are as follows 9 Download Image Via Ethernet ESHELL This menu selection is used to download the LARC2 Program Flash image larc2_enet bin via a PCMCIA Ethernet card in order to reduce test time during the manufacturing test process B Boot d0000000 This menu selection is used to Boot the LARC2 application so
341. t solder pins 2 to 8 and 3 to 7 5 4 Lexicon Chapter 6 Troubleshooting Check the Lexicon web site and Customer Support Knowledgebase for the latest software and information http www lexicon com http www lexicon com kbase kbase asp Diagnostics Overview The purpose of this document is to describe the diagnostic tests in the 960L The diagnostics in the 960L are utilized to verify performance and functionality The 960L and LARC2 are a high end digital audio effects system The 960L and LARC2 system is a multi channel digital audio effects processor that can also be configured as a single channel processor The LARC2 provides full control of 960L through a 50 foot 9 pin cable The 960L and LARC2 system is composed of the following printed circuit assemblies manufactured by Lexicon NLX backplane I O backplane Clock Analog In Analog Out Reverb AES LARC2 Main LARC2 Meter n addition there 6 devices NLX PC processor card motherboard with Celeron CPU Processor NLX ATX power supply 3 5 floppy drive CD ROM MIDI Card Hard Disk Drive 9601 Diagnostics 9601 has 3 sets of diagnostics power on functional and troubleshooting The power on diagnostics are executed every time the 960L is powered on The power on diagnostics verify basic reverb card functionality checks which cards are present in the I O cage and communicates with the LARC2
342. t 0 8W about at 12V which is the short circuit condition The trip time is typically 0 2 seconds at 8 Amps which is a severe overload Smaller overloads can take many seconds to trip Resetting occurs when the load is removed and the fuse cools returning to the low resistance state Full duplex remote serial communication is based on RS 232 COM ports built into the NLX motherboard U14 75ALS180 forms the interface between the bipolar unbalanced RS 232 levels of the COM1 port and the unipolar balanced RS 422 levels of the REMOTE 1 port The RS 232 signals from connect to the IO backplane J6 via a ribbon cable connected to the 9 pin D sub connector on the IO panel of the motherboard The backplane brings 1 signals to J1 as 5232 TXD1 and 5232 RXD1 spacing positive RS232_TXD1 feeds the driver section of U14 through R27 and dual diode D9 BAV99 which essentially limits the bipolar RS232 signal to a logic level TXD1 within the range acceptable by 014 When the serial port is idle i e marking TXD1 is low The output of the U14 driver is wired to make TX1 high and TX1 low so the marking state of the differential RS422 signal is positive according to convention The U14 driver is wired as an inverting stage because of the sense of RS232_TXD1 The receiver section of U14 accepts differential RS422 input from REMOTE 1 and produces logic level signal RS232 RXD1 As with the driver
343. t ram test first go the directory where the test resides reverbcardtests then press ENTER Then type more help dpramtest followed by ENTER and a description of the dual port ram test will be displayed on the LARC2 MIDI Test The syntax for the MIDI test is MIDITest optional NumRepeats The 960L MIDI tests verify the MIDI In to MIDI Out path The MIDI pattern OxCO 0x00 is generated by the 960L and sent to the MIDI Out port Using a 5 pin DIN to 5 pin DIN cable connected from the MIDI In to MIDI Out port the CO 00 data pattern is read and the test passes This command sends a program change message on MIDI channel 1 for program 1 0xCO 0x00 then waits a short period for it to come back The test reports if no data is received if the status byte is incorrect or if the data byte is incorrect Optionally a decimal number can be entered on the command line to repeat the test When this is done the error messages are held off until the last test try The count is a long variable so the test can be repeated literally millions of times for scope loop testing A value of 0 runs the test infinitely Serial Port Test The syntax for the serial test is SerialTest PortNum optional NumRepeats Where PortNum is the port number Ports 1 and 2 are available Port 1 is the D9 connector labeled Remote 1 on the I O Clock card and port 2 is labeled Remote 2 The default configuration is that Port 1 is enabled for LARC2 operation and Port 2 is enabled fo
344. tering interface U1 from the backplane is converted to the corresponding positive value in the right channel of the D A 125 stream its binary complement the left channel This makes U14 1 positive U14 7 negative U22 7 CH1 negative and U26 3 J2 2 positive so a positive digital input value from the backplane produces a positive voltage on the conventional differential XLR output System Interface Logic U1 Xilinx XCS05 sheet 5 is the interface between the backplane control data host and audio and clock buses and the D A converters and their associated controls When power is applied to the card the FPGA automatically receives its internal configuration from companion SROM U2 Configuration takes a few tens of msec after which the onboard logic assumes its default state and is ready to be interrogated programmed by system software Control Interface The Analog Output card appears as two byte wide ports on the I O backplane databus IOBUS DATA T 0 at the addresses determined by the decoding of SLOT SEL and one address bit IOBUS ADDR O IOBUS WR RD determines the direction of data transfer low write high read with IOBUS 5 being asserted low during data transfers U1 captures write data on the rising edge of IOBUS_DS Five pins of the fpga are control outputs whose states get programmed from the host computer Four pins DEEMPH DAMUTE RST 96K EN control all the D A converters in parallel and
345. terminated elsewhere in the system The input squarewave is applied to the high impedance non inverting input of line receiver U13 75ALS180 that produces the buffered waveform The receiver threshold is set at about 1 6V by resistors R25 and R26 BNC WCIN is fed to a multiplexer implemented within the programmed logic of CPLD U2 XC9572 where it can be selected by software to be the reference for the on board PLL A squarewave derived from the internal wordclock WCOUT is generated by U2 and fed to the line driver section of UT3 OUTPUT BNC J8 is driven by the non inverting output of U13 Output impedance is around 15 ohms and output voltage is typically 3 5Vpeak when loaded with 75 ohms to ground Larc2 Interface J9 and J10 female 9 pin D subminiature connectors are ports for LARC2 remote control consoles REMOTE 1 and 2 Each port delivers fused 12Vdc power and provides separate full duplex RS 422 serial communication channels 49 5 delivers 12Vdc from the system 12V supply through self resetting fuse PS1 0 75Amp Normally the fuse exhibits a low series resistance a few tenths of an ohm When overloaded by currents gt 1 5 the fuse undergoes self heating and switches to a high resistance state due to the thermal characteristics of its material This high resistance limits the current drawn from the supply under the overload condition The fuse maintains the high resistance state as long as it dissipates abou
346. test is also run that writes each address value into its associated memory location address 29 has the value 29 written into it address 30 has the value 30 written into it etc This test confirms that the Z80 can access all of its banked SRAM If this test fails but the Z80BootTest and Z80DpramTest pass there is probably a problem with the address data or control lines between the SRAM and the Z80 Parameters This number selects which reverb card to test Legal values 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 28014 This specifies which 280 the to test Legal Values 0 1 NumRepeats This optional parameter specifies how many times to run the test A value of 0 runs the test indefinitely until a key is pressed Dots are shown on the display to indicate that the test is still running Notes Itis assumed that the following tests pass DPRAM Test 280 Z80DpramTest Z80 Wait Test The syntax for the Z80 Wait Test is Z80WaitTest Cardld 2801 NumRepeats This test verifies the WAIT line from the Lexichip3 to the Z80 Parameters This number selects which reverb card to test Legal values 0 and 1 since only two reverb cards will be supported If only one card is present use the number 0 28014 This specifies which 280 on the card to reset Legal Values are 0 and 1 NumRe
347. test is used to verify the operation of the LED s and driver circuitry of the 12 Main Board LED s and the 24 Meter Board LED s When the test is executed the MACHINE key is used to advance the test to the next LED IMPORTANT When the LARC2 is reset all of the LED s on the Main Board and Meter Board are turned on and the brightness of the LED s may vary considerably because the LED s are not being scanned The LED Test should always be used whenever it is necessary to compare the brightness of the LED s because the LED s are being scanned during the LED Test When the test is executed the following message is sent to the LCD display and also to the Debug Port as shown in the example below Press MACHINE n on debug port to advance when finished NOTE When the LED Test is exited before all of the LED s have been tested an error message is sent to the LCD display and also to the Debug Port as shown in the example below Did not check every LED Press or Enter on debug port key to acknowledge Press the key on the LARC2 or press ENTER on the Debug Terminal to continue Refer to the table below for more information about the behavior of the Main Board keypad and Meter Board LED s during the LED Test 6 36 Lexicon MAIN BD MUTE MACH MAIN BD MUTE ALL MAINBD MACHINE MAINBD CONTROL EDT 2 GREEN x 5 GREEN 6 GREEN 7 GREEN METER BD METER BD M
348. tests verify communication with the cards in the Cage These are the Clock Analog In Analog Out and AES cards Clock card Test The syntax for the Clock card test is OClockBdTest CardlD optional NumRepeats This tests the control interface to the IO Clock card This command writes a walking 1s pattern to the control register on the IO backplane s Clock card reading the data back to confirm it Card This defines which card in the system to access Initial systems will only contain a single card so a value of 0 should be used An additional card would use a value of 1 NumRepeats optional This defines how many times the test is run The default if not entered is 1 time A value of 0 runs the test infinitely Pressing any key exits the loop Analog Input card Test The syntax for the Analog Input card Test is OAInBdTest CardID optional NumRepeats This tests the control interface to the Analog Input card This command writes a walking 1s pattern to the control register on the IO backplane s Analog In card reading the data back to confirm it Card Id This defines which card in the system to access Initial systems will only contain a single card so a value of 0 should be used An additional card would use a value of 1 NumRepeats optional This defines how many times the test is run The default if not entered is 1 time A value of 0 runs the test infinitely Pressing any key exits the loop
349. the 960L 1 Audio Input Connect a balanced XLR audio cable between the 960L 1 2 AES Output and the digital distortion analyzer Apply 997Hz sinewave 10 94 VRMS Enable the Audio Band Pass filter on the distortion analyzer Verify the level on AES Output 2 to be lt 100 dB throughout the sweep Move the Input cable to the 2 Input and repeat the test for AES Output 1 Repeat the test for the remaining Input Outputs pairs 3 4 5 6 and 7 8 S gt Digital In to Analog Out Crosstalk Test Note Change the Clock Source and Inputs to AES see Audio Functional Tests Setup 1 Connect a balanced XLR audio cable between the digital function generator and the 960L 1 2 AES Input Connect a balanced XLR audio cable between the 960L 2 Audio Output and the distortion analyzer Apply a 997Hz sinewave 1 dBFS Enable the Audio Band Pass filter on the distortion analyzer Verify the level on Output 2 to be lt 100 dB throughout the sweep Move the audio output cable to the 1 Output and repeat the test Repeat the test for the remaining Input Outputs pairs 3 4 5 6 and 7 8 NOARWN Dynamic Range Tests Analog In to Analog Out Dynamic Range Test Note Change the Clock Source to Internal and Inputs to Analog see Audio Functional Tests Setup 1 Connect balanced XLR audio cable between the low distortion oscillator and the 960L 1 Audio Input Connect a balanced XLR audio cable between the 960L
350. the PVW WCK SEL field in the CTLREG VCO pump up signal Active low VCO pump down signal PLL Lock error detected signal Indicates that the PLL is locked to the selected word clock source The state of this can be read from the CPLD CTLREG 7 9 960L Multi Channel Digital Effects System Service Manual 36 XTAL EN OUTPUT Local oscillator output enable control When negated all oscillators are disabled to reduce signal noise created by the oscillators when not in use CPLD Support 15 16 TDI TCK TMS INPUT JTAG Interface Not used except to program the part in place 17 30 TDO OUTPUT JTAG Interface Not used except to program the part in place Control Interface The I O Clock card appears as two byte wide ports on the backplane databus IOBUS DATA T 0 at the addresses determined by the decoding of SLOT SEL and one address bit IOBUS ADDRO IOBUS WR RD determines the direction of data transfer low write high read with IOBUS 5 being asserted low during data transfers U2 captures write data the rising edge of IOBUS_DS IOBUS RESET and PWROK are used to initialize various internal FPGA state When low ALL MUTE forces the octal audio data lines TMIX1 SERDO 1 2 3 10 11 to zero Register Descriptions OFFSET NAME Default ADDR Val TT Acce 4 Description SS 0x00 IDREG 7 0 RO 0x00 Board ID IDREG 7 4 0 0 PCB IDREG 3 0 1 Interface revision 0x01 7 0 CTLREG 7
351. the previous group so that in single speed mode there are two successive groups of 4 samples within each word clock period that are the same In both single and double speed modes two high speed channels are necessary to carry 8 samples U1 is capable of driving one of 3 alternate channel pairs 5000 1 SDO2 3 or SDO10 11 on the backplane System software loads the CTLREG register within U1 to enable the drivers for one of the available pairs driving 8 channels from one Analog Input card into the system 960L Multi Channel Digital Effects System Service Manual TMIX_WCKI IOBUS WCLK 5000 2 4 5001 3 5 1250 1 2 3 1 1 3 5 7 1 2 4 6 8 TMIX_WCKI 4 5000 24 5001 3 5 1250 1 2 3 52 1 3 5 7 Pin Descriptions Pin Name Host Interface 40 PWROK 44 RESET 82 ALL MUTE 50 CS 47 DS 48 WR RD 66 A0 65 1 62 2 61 60 4 59 5 58 6 56 AT 67 D7 68 D6 69 D5 70 D4 72 D3 77 D2 80 D1 81 D0 Clocks 7 18 Type INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR S2 2 4 6 8 3 1 3 5 7 53 2 4 6 8 channel number Description POWER OK 0 resets various internal state 1 normal operation RESET 0 resets various internal state 1 normal operation ALL MUTE 0 forces SDIO 5 to zero 1 normal operation CHIP SELECT 0 this slot is being selected 1
352. tion 4 Slowly bring the variable AC power supply voltage up to 120 Volts The current draw will vary from between approximately 0 5A and 1 5A 5 At 120V verify that the current draw is approximately 0 75 A and that the Green Power On LED above the Front Panel power switch is on 6 Power off 4 1 960L Multi Channel Digital Effects System Service Manual For 220 240V operation verify that the voltage selection switch on the back of the 960L is set to the 230 Volt setting Follow steps 2 through 6 above Note the current draw should be approximately one half of that listed in the steps above dependant upon the accuracy of the current meter It should not be higher Note Different manufacturer s power supplies have been specified for the 960L There are some slight mechanical differences in some of these power supplies Some units will have a power supply with a voltage setting switch as noted above Some units will have a power supply that does not have a voltage selection switch The AC voltage input will be automatically sensed by the supply Be sure to inspect the unit in case of the need to switch for the appropriate AC input voltage Main Power Supply Connector J26 Voltage Level Tests 1 Remove the top and bottom covers of the 960L 2 Remove all DSP cards and the Midi card from the card cage in the front section of the 960L and place them in static shielding bags 3 With the front of the 960L facin
353. to the bus The DSP data bus interface to the 56301 uses 3 3V logic levels The 56301 address bus also drives 3 3V logic levels The 56301 control bus drives 3 3V logic levels but control inputs to the 56301 are tolerant of 5V logic levels 5V 3V interface devices are required to interface the 56301 to the T MIX devices since these Asics have 5V CMOS inputs and outputs The 5V 3V level translation is accomplished by using Quickswitch 052345 bus switches to attenuate 5V signals to levels These devices 010 011 and U12 on sheet 3 These devices will attenuate the 5V signals provided they are powered by a 4 3V source which is provided by an adjustable regulator U2 sheet 14 The T MIX devices must have 5V CMOS levels on their input pins so the signals from the 56301 must be converted to 5V CMOS logic levels This is done using FCT2244 buffers 04 05 06 07 08 09 013 014 on sheet 3 Pull up resistors are used on the SAMP_DATSV bus to set the data bus to a valid logic level when the bus drivers are tri stated T MIX 1 sheet 4 The Reverb Card has three T MIX devices These chips function as serial to parallel converters for digital audio The 56301 transfers 24 bit parallel audio samples to from the T MIX chips T MIX 1 shown on sheet 4 receives serial digital audio from audio input cards on the I O bus These digital audio streams are formatted with eight audio samples per word clock These audio streams can be probed on R12
354. to the system via interface 01 System Interface Logic 91 Xilinx XCS05 sheet 5 is the interface between the backplane control data host and audio and clock buses and the A D converters and their associated controls When power is applied to the card the FPGA automatically receives its internal configuration from companion SROM U2 Configuration takes a few tens of msec after which the onboard logic assumes its default state and is ready to be interrogated programmed by system software Control Interface The Analog Input card appears as two byte wide ports on the I O backplane databus IOBUS 7 0 at the addresses determined by the decoding of SLOT SEL and one address bit IOBUS ADDRO IOBUS WR RD determines the direction of data transfer low write high read with IOBUS 5 being asserted low during data transfers U1 captures write data on the rising edge of IOBUS 05 Two pins of the FPGA are control outputs whose states get programmed from the host computer CONV RESET and DFSO control all the A D converters in parallel DFS1 is permanently grounded as described above IOBUS RESET and PWROK are used to initialize various internal FPGA state When low ALL MUTE forces the octal audio data lines TMIX1 SERDO 1 2 3 10 11 to zero Register Descriptions OFFSET NAME Access Default Description ADDR Value 0x00 IDREG 7 0 RO Ox11 Board ID register IDREG 7 4 RO 1 1 IDREG 3 0 1 Interface re
355. vision number 0x01 CTLREG 7 0 CTLREG 7 6 RW 0 3 TMIX1 output serial octal drive select 00 Drives TMIX1 SERDO TMIX1 SERD1 octal pair 01 Drives TMIX1 SERD2 TMIX1 SERDS octal pair 10 Drives 1 SERD10 TMIX1 SERD 1 1 octal pair 11 AIN Octals are not driven all drivers are tristated 5 RW 0 AKM5394EN This enables the DFS1 driver for use with the 5394 7 16 Lexicon Should only be set if the AKM5394 is used CTLREG 4 RW Reserved CTLREG 3 RW 0 DFS1 AKM5394 DFS1 control signal Setting is only significant if AKM5394 AD is used CTLREG 2 RW 0 DFS0 Double Speed Sampling Enable for AKM4393 1 RW 0 CONV_RESET Active High AD converter reset control line All converters are reset when asserted Software must assert then negate CTLREG 1 to complete a soft reset sequence 0 RW Reserved Clock Interface The following onboard digital audio clocks are derived from bus clocks and TMIX WCKI 125 FS I28 64FS and 125 256FS The bus clocks TMIX CKI 2 IOBUS WCLK IOBUS 64FS and IOBUS 256FS are not used 125 FS 125 64FS scale with sample rate FS 125 25625 is the master clock to the D A converters and is zzzcheck this make sure 2x operation is right see AOUT design 256FS in single speed mode and 128 5 in double speed mode Source resistors in the clock lines reduce ringing due to reflections to provide proper clocking Digital Audio Interf
356. y 4 98 91 11 SHOMOL 1 88 2 40 T9009 Ww 5 1 4 3 HOI 549 t 9 2 AVE b b q uim nor orl seen sem v LOH wd d w mu 3669 27 66u 868 I Y Y SVAS SVAS P 5 T A ON 4 ae y Bud u lt lt 9081 Bid PIE cora za THONOL En 4 2 E wees solu vols 2 SVAS T f 30 5268 2 66019 u We 00 10168 400 Q39NVHO 1 SUAE SNOISIASS 55 6 0002 1 2 9 9 4 8 6 dO L 6666 66 8 9 Wed WYN 31 MO 6 1 090 338 SHOLVOIGNI SHOLO3NNOO 8829 yaa xnv 031 2 YILIN WaHOS va STVAOUddY 06 10 VW uooixe rdi 00 Yd U ON lt 5 Tho bae VIVO Sd 9 Ed e Dasw tan 0 6 0857 9 gig 4 VIS eT su vr Y wn a F 722 a zn J 1S0H
357. y outside the CPLD Lock Detector If the clocks from the PLL are not closely aligned with the reference the PLL is considered to be unlocked If lock is not within plus or minus 1 128 of a wordclock period on any clock cycle logic within the CPLD generates a LKERRDET pulse which triggers integrating one shot U5 R6 and C8 set the timing of U5 at about 50 msec The output of U5 is returned to the CPLD where it can be polled by software to ensure the 7 13 960L Multi Channel Digital Effects System Service Manual quality of phaselock and proper operation of the audio systems in the 960L If lock remains within tolerance and no LKERRDET pulse occurs for 50 msec U5 times out and the system is considered to be in lock During lock capture 05 gets retriggered frequently so PLL LOCKED does not get asserted at all and the software can tell that the PLL is not locked On board LED D1 is driven directly from 05 to give a visible indication of the UNLOCKED condition Default Operation By default the CPLD configures the PLL to lock internally to crystal U3 producing a 48kHz sampling rate when power is first applied to the card Power Supply Power conditioning for the I O Clock card involves local filtering and regulation of supplies from the backplane Main 5VD from the backplane supplies the CPLD and other digital logic The 12V supplies from the backplane 12VSUP 12VSUP are filtered by FB1 FB2 and associated capacitors to supply

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