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pdp-7 interface and installation manual

1. 61 Serial 71 Tape Control 21 Relay Buffer 01 Standard 11 Analog to Perforated Digital or Type 140 Drum Type 57A Tape Reader Digital to Type 24 and Control Analog Converters 72 Tape Control Type 57A 62 Serial Drum 22 Inter Processor Buffer Type 195 02 Standard _ Perforated Tape Punch 73 Tape Control Type 57A 33 1 33 KSR Skip 2 Clear Flags 4 Open 23 Inter Processor Buffer Type 195 13 A D A Stimulus 03 1 Keyboard 2 Keyboard 4 JORS 74 Tape Control 24 incremental Type 57A Plotter Control Type 350 04 Teleprinter 65 Automatic 75 DECtape 55 Automatic 05 Displays Types 34F Priority Line Printer Control Interrupt Type 647 Type 550 30D or 340 Type 172 i 06 Displays 16 26 Plotter 56 API 172 76 DECtape Control Type 550 66 Automatic Line Printer Type 647 07 Display 17 Boundary 27 Memory 67 Card Reader 77 Memory and Register Parity Type CR 01B Extension Light Pen Type KA70A Type 176 or Type CR 02A Type 1488 Level Use 1 18 connections employed for RB of the tape reader 2 First 9 connections employed for status signals of IORS instruction IOT 0314 and last 6 connections are as signed to the step counter SC of the Type 177 EAE option when present 3 5 All 18 co
2. Interface Connections and Signal Identification e 9 9 9 9 9 9 o 0 e e 0 e e 0 e 9 9 6 9 9 10 11 13 14 16 16 18 19 19 22 24 29 31 33 33 37 37 37 38 39 41 41 CONTENTS continued Chapter Page 5 cont Loading and Driving Considerations TE TIPP 43 Device Selector Tm 73 Information Collector TT PPP 74 Information Distributor Ma 76 Power Clear Output Signals TP TT 78 Begin Buffered Output Signal 78 Run Output Signal am 78 Slow Cycle Request Input Signal 78 Program Interrupt Request
3. gt GENERATOR Nim PULSES 18 BIT REGISTER aA MB INSTRUCTION WORD OUTPUT INFORMATION DATA DISTRIBUTOR 10 INPUT DATA ACCUMULATOR REGISTER AC INFORMATION COLLECTOR 1C INPUT 7 ouTPUT skip LSKIP FACILITY 108 PROGRAM INTERRUPT PROGRAM INTERRUPT REQUEST FACILITY PT SLOW CYCLE SLOW CYCLE REQUEST FACILITY Figure Programmed Data Transfer Interface Block Diagram CONNECTIONS TO INPUT OUTPUT OEVICE All programmed data transfers take place through the accumulator the 18 bit arithmetic register of the computer The computer program controls the loading of information into the accumulator AC for an output transfer and for storing information in core memory from the AC for an input transfer Information in the AC for output transfer is power amplified and supplied to the bussed connections of many peripheral devices by the information distributor ID Then the program selected device can sample these signal lines to strobe AC data into a control or information register Input data signals arrive from many periph eral devices at input mixer circuits of the information collector IC which transfers data into the AC In the input output skip facility IOS command pulses from the device selector DS sample the condition of I O device flags The IOS allows branching of the program based on the condition or availability of peripheral equipment effectively making program
4. ON NUN m x _ sa lt 1 1 T ma 1 ua CN SUN MAN UN me mo Drawing Signal Destination in Package Destination in Signal Destination in Package Package Signal Destination in Processor KA77A Symbol Interface Module Module Logic Drawing Module Module Logic i Connector Terminal Element Number Terminal Element Number eS Signal EIC10 EIC12 EICI3 14 EIC15 EIC16 EICI7 DAO3 0 04 0405 DA06 DAO7 DA08 DA09 DA10 TABLE INPUT SIGNALS continued Signal Destination in Package Signal Destination in Processor KA77A Connector Terminal Type Element Number Terminal Type Element S e A MN I LE See Te pO w Drawing Number DATI DA12 DA13 DA14 15 DA16 DA17 0100 1 0101 1 D102 1 21030 01041 0105 1 D106 1 0107 1 0108 1 TABLE 1 INPUT SIGNALS continued Signal Destination in cl Signal Destination in Package KATIA cl Signal Destination in Package KATIA KA71A Signal Destination in Processor KA77A Symbol Interface Module Module Logic Drawing Module Module Logic Drawing Connecto
5. Signal Destination in Processor KA77A Symbol Interface Module Module Logic Drawing Module Module Logic Drawing Connector Terminal Type Element Number Terminal Type Element Number hr s 4 G lol IM EE TA ENEE IC 3 3 3 3 olei MEE dida c 8 HN ER NS NEN OMNES ONE EN E E Eo MEO NN MON NN O A NC UNE NL mal MEE EN NM RNC MMC F02V R141 OS TABLE 1 INPUT SIGNALS continued Signal Destination i Destination in Package Destination in Package Package KA71A Signal Destination in Processor KA77A zigag Interface Module Module Logic Drawing Module Module Logic Drawing Connector Terminal Type Element Number Terminal Type Element Number E p 07 HIIS R14 KBD FLG 1 E04J 8141 IG Signal 5 12 1 SC13 1 SC14 1 5 150 SC16 1 SCI7 1 EICO0 EICOI EICO2 EICO3 EICOA EICOS EICO6 EICO7 EICOB EICO9 TABLE 1 INPUT SIGNALS continued Lope BE K z GU OM sqa IL lt T T _ LL mnj T T x IO m j j j x pem EET j j T j pee ERIN
6. When a large amount of computing is required the computer should process data rather than simply wait for an I O device to become ready to transfer data The PI facility when enabled by the program re lieves the main program of the need for repeated flag checks by allowing I O device ready flags to auto matically cause a program interrupt break At the break location program control transfers to a subroutine which determines the requesting device and initiates an appropriate service routine The basic PI facility can accommodate interrupt requests from nine devices and is expandable As shown in Figure 14 the PI facility receives a negative signal from the flag of a device to request an interrupt This flag signal input to the PI can also connect to the IOS facility to allow the program interrupt sub routine to detect the device requesting the interrupt if multiple devices are connected to the Pl On Figure 14 note that any flip flop or flag signal connected to an input of any of the six 3 input NOR gates of the I O package triggers the interrupt control circuits of the processor to cause a program inter rupt break if a break is not already in progress and if the interrupt system is enabled 19 S NS W M R ot oau M ip 2 COMPUTER PROGRAM INTERRUPT FACILITY Z 6 NO BREAK STARTED A y PROGRAM INTERRUPT g FACILITY ENABLED et 7 x 19 P di J 2 DA EXTERNAL
7. DEVICE COMPUTER I O SKIP FACILITY Figure 14 Program Interrupt Facility If only one device is connected to the PI facility program control can be transferred directly to a routine that services the device when an interrupt occurs This operation occurs as follows 21 Tag Address 1000 1001 1002 0000 0001 SR 2000 3001 3002 3003 1003 1004 Instruction INTERRUPT JMP SR ION JMP 1 0000 Remarks MAIN PROGRAM MAIN PROGRAM CONTINUES INTERRUPT REQUEST OCCURS OCCURS LINK EXTEND AND TRAP FLIP FLOP STATES EXTENDED PROGRAM COUNT AND PROGRAM COUNT PC 1003 ARE STORED IN 0000 ENTER SERVICE ROUTINE SERVICE SUBROUTINE FOR INTERRUPTING DEVICE AND SEQUENCE TO RESTORE AC AND RESTORE L AND EPC IF REQUIRED TURN ON INTERRUPT RETURN TO MAIN PROGRAM MAIN PROGRAM CONTINUES MULTIPLE USE OF IOS AND PI In common practice more than one device is connected to the PI facility Therefore since several devices can cause an interrupt the IOS must identify the device requesting service When an interrupt occurs routine is entered to identify the device requesting an interrupt and to branch to an appropriate service routine The device can be identified by IOT pulses that sample a device flags and cause the pro gram to branch or not branch according to the status Figure 15 shows connections for three typical de vices The following programming example illustrates t
8. vice buffer register To clear the AC prior to the transfer bit 14 of the OT instruction should contain al This microprogramming clears the AC at event time 1 computer time T5 and an XX12 pulse causes the transfer to occur at event time 2 computer time T7 Following the transfer possibly in the same instruction the program issues an XX04 command pulse to initiate further operation of the device This pulse also clears the device flag For simplicity the transfer path in Figure 12 shows only a single channel of the IC gates DATA TRANSFERS OUT OF THE PDP 7 XX02 and XX04 command pulses control an external output device as indicated in Figure 13 The is loaded with a word e g by a LAC instruction then the IOT instruction is issued to transfer the word into the control or data register of the device by an XX02 pulse and operation of the device is initiated by an IOT XX04 pulse The word transferred in this manner can be a character to be operated upon or can be a control word sampled by a status register to establish a control mode Connecting an output device to the PDP 7 interface adds at least three commands to the instruction rep ertoire These commands use an IOT pulse to skip on the ready condition of the device flag an XX02 pulse to effect a transfer from the AC to the device and an XX04 pulse to initiate opera tion of the device PROGRAM INTERRUPT PI
9. MQI AC JIE JH SC 12 1 JMK SC 13 1 JM SC 14 1 JP SC 15 1 Js SC 1611 JUT SC 17 1 Juv 340 Precision Incremental Display H10D H11D H10E HIE H10H HT OK F04V H10M FO5V H10P FO6V 105 FO7V H10T F08V H11T FO9V 69 Signal ACB 00 1 01 1 ACB 02 1 ACB 03 1 041 ACB 05 1 ACB 06 1 ACB 07 1 ACB 08 1 0602 0604 0704 B 0504 B DTI 00 1 DTI O1 1 DTI 02 1 DTI 03 1 DTI 04 1 DTI 05 1 DTI 06 1 DTI 07 1 DTI 08 1 Terminal H17D HI7E H17H H17K H17M H17P 175 H17V H26D H26E H26H H26K H26M H26P H26S H26T H26V TABLE 3 PREWIRED INTERFACE CONNECTIONS continued Signal 340 Precision Incremental Display continued ACB 09 1 ACB 10 1 ACB 11 1 ACB 12 1 ACB 13 1 ACB 14 1 ACB 15 1 ACB 16 1 ACB 17 1 STOP FIG 340 LP FLG DATA RQ DATA IN ADDR ACC DATA ACC BGN V EDGE FLG H EDGE FLG 550 DECtape Control HOSD HOSE HOS H HOS K HOS M HOSP HOSS HOST HO5V 70 DTI 09 1 DTI 10 1 DTI 11 1 DTI 12 1 DTI 13 1 DTI 14 1 DTI 15 1 DTI 16 1 DTI 17 1 Terminal 2170 J17E J17H J17K J17P 175 J17T J17V J26D J26E J26H J26K J26M J26P 4265 J26T J26V HO6D HO6H HO6K HO6M HO6P HO6S HO6T HO6V TABLE 3 PREWIRED INTERFACE CONNECTIONS continued Signal Terminal Signal Terminal 550 DECta
10. infor mation in the MB is written into core memory by the normal write operation Data Ready Output Signal During of a data break cycle in which the transfer direction is out the level causes nega tive DATA RDY in early systems called MB INFO OUT pulse to be generated This pulse may strobe MBB information into the external device buffer for this purpose the signal may be delayed within the de vice to strobe the data into the buffer after an appropriate setup time Note that the transfer must occur prior to T2 of the next computer cycle 80 Data Information Output Signals Data break transfer from core memory to an O device is made through the MB whose output is buffered for this purpose by 18 Type B684 Bus Drivers Each bus driver is capable of driving a 40 ma load The MBB output terminals are in the I O package 81 6 INSTALLATION PLANNING PHYSICAL CONFIGURATION The basic PDP 7 is housed in a three bay cabinet and consists essentially of mounting panels of FLIP CHIP modules Figure 29 shows the physical location of the memory processor package operator con sole tape reader and tape punch within the basic system Space is available for optional equipment below the table in the center bay and above the I O package in the right bay For example a three bay PDP 7 with 8192 words of core memory could also include an Automatic Priority Interrupt Type 1728 and have spac
11. Cable Connector Locations and Assignments Information Collector Channel Assignments Basic PDP 7 Component Locations e o e e 9 0 9 e 0 9 Typical PDP 7 System Component Locations Basic PDP 7 Installation Dimensions e 9 e 09 e 11 12 13 14 15 17 18 20 21 23 25 26 29 30 32 34 35 38 38 39 40 42 77 84 85 86 Table Co N TABLES Input Signals co t in SER aie ele uM Outp t Signals ase A Rv Prewired Interface Connections OT Code Assignments seriada Installation vi 1 INTRODUCTION Since the processing power of a computer system depends in large measure upon the range and number of peripheral devices that can be connected to it the Programmed Data Processor 7 PDP 7 has been designed with a very broad flexible and expandable interface This manual defines the interface char acteristics of the computer to allow the reader to design and implement any electrical interfaces required to connect devices to the PDP 7 This manual also provides information for planning the installation of a PDP 7 system I
12. DECtape Control 550 2 1 5 Automatic Magnetic Tape Control 57A 5 2 Serial Drum 24 3 0 Incremental Plotter and Control 350 3 0 89 Card Reader and Control Option DS Channels IC Channels Oscilloscope Display 34F Precision CRT Display 30D Symbol Generator 33 for 300 Precision Incremental Display 340 Subroutine Option 347 for 340 _ Character Generator 342 for 340 Slave Display 343 for 340 Photomultiplier Light Pen 370 Relay Buffer 140 Analog to Digital Converter 1 o gt General Purpose Multiplexer 139E P N 00 hb m Digital to Analog Converter ni Data Communications System 630 Automatic Line Printer 647 Card Reader and Control CRO2A 1 Interprocessor Buffer 195 m 2 O O O 90 5119 EQUIPMENT CORPORATION MAYNARD MASSACHUSETTS Printed in U S A 15 3 66
13. Each selector channel in a PDP 7 with a serial number c over 100 requires a W103 Device Selector module and a W640 Pulse Amplifier module three circuits 400 Ipsec pulses The standard information collector on PDP 7 with a tape reader tape punch and Teletype contains 5 spare input channels One Type 175 Information Collector Expansion option extends the standard IC by seven additional channels making a total of 12 available channels The 175 requires one channel of the standard the total number of available channels is 11 The following list specifies the number of DS and IC channels required for standard DEC options for the PDP 7 By using the following list the need for DS or IC expansion can easily be determined for any system configuration containing standard DEC options If required these expansion elements should be included in purchase orders and construction requisitions cases where only half a channel is the remaining half is available for other options Half channels are designated as 0 5L for the left half bits O through 8 or 0 56 for the right half bits 9 through 17 Option DS Channels IC Channels Second Console Teletype and Control 649B 2 1 Memory Extension Control 1488 1 0 Memory Parity 176 1 0 Memory Increment 197 1 1 Memory Boundary Register KA70A 0 0 Automatic Priority Interrupt 172B 2 0 Data Interrupt Multiplexer 173 0 0 Extended Arithmetic Element 1778 0 1 58
14. MA contains 13 bits the flip flops are designated MA5 through The two extension flip flops are added to the most significant end of the register and are de signated EMA3 and 4 Each of these flip flops is loaded with the information on the DATA ADDRESS lines supplied by the device when the ADDRESS ACCEPTED pulse occurs The data break facility gen erates the ADDRESS ACCEPTED pulse at time of a break cycle caused by a negative DATA BREAK REQUEST signal Figure 21 shows this data address interface logic of the computer DATA INFORMATION INPUT AND OUTPUT Input data from an external device is received by the MB during a data break as 18 DATA INFORMATION or DI signal levels The DATA INFORMATION input signals should be present when the data break request is made but can be delayed if they are settled prior to T3 time of the break cycle Each signal binary 1 enables a 2 input NAND gate at the 1 input of an MB flip flop The DATA ACCEPTED 33 pulse strobes all these gates This pulse is generated in the data break facility at T3 of the break cycle by negative DATA BREAK REQUEST and TRANSFER DIRECTION signals which request an input data break Figure 22 shows the data information input interface to the MB o Figure 21 Data Address Input Interface of Computer Output data from the computer during a data break is supplied to the external device as an 18 bit MB buffered DATA INFORMATION word The negative binary 1
15. POSITIVE OR POSITIVE GOING PULSE DEC STANDARD NEGATIVE LEVEL DEC STANDARD GROUND LEVEL FLOW 15V LOAD RESISTOR CLAMPED AT 3v PNP TRANSISTOR INVERTER 1 EMITTER 2 BASE 3 COLLECTOR LOGIC AND GATE FOR NEGATIVE SIGNALS WITH COMPLEMENTARY OUTPUT SIGNALS LOGIC OR GATE FOR GROUND LEVEL SIGNALS WITH COMPLEMENTARY OUTPUT SIGNALS LOGIC NANO GATE FOR NEGATIVE SIGNALS 227 3 DIODE CAPACITOR DIODE GATE 1 CONDITIONING LEVEL INPUT 2 TRIGGERING PULSE INPUT 3 PULSE OUTPUT 2 5 FLIP FLOP BISTABLE MULTIVIBRATOR 1 GATED SET TO 1 INPUT 2 GATED CLEAR TO O INPUT 3 DIRECT CLEAR TO O INPUT 4 5 OUTPUTS A gt Figure 2 Logic Symbols el M Y INVERTING BUS DRIVER B OR W SERIES PULSE AMPLIFIER OUTPUT CAN BE MADE POSITIVE OR NEGATIVE BY REVERSING GROUND AND SIGNAL OUTPUT TERMINALS R SERIES PULSE AMPLIFIER OUTPUT ALWAYS POSITIVE REFERENCED TO 3v OPTIONAL DEVICE SELECTOR LOGIC AS USED FOR ONE SELECT CODE Figure 2 Logic Symbols continued 2 PROGRAMMED DATA TRANSFERS The PDP 7 is a parallel transfer machine that collects and distributes data in bytes of up to 18 bits Figure 3 shows information flow within the computer to effect a programmed data transfer with input output equipment BITS 0 3 10T IOP INSTRUCTION PULSES IR i INSTRUCTION REGISTER COMMAND IR e
16. a logical NOR gate for negative signal levels The Type B201 Flip Flop modules in both the MA and MB use two series connected inverters as 2 input gates Schematically these are identical to of the 8105 module In data break transfers these gates receive the DATA ADDRESS signals in the MA and receive the DATA INFORMATION signals in the MB In each case the inverter nearest the flipflop i triggered by an internally generated 70 nsec pulse and the data signal is received at the inverter with the grounded emitter Each inverter is analogous to a switch If the inverter base is at and the inverter emitter is at ground the PNP transistor is saturated and a conducting path is established between the emitter and collector If the base is at ground the emitter collector path is open circuited i e will not allow current to flow and there is no static load When the base input is at 3v the static load is 1 The base can reject 0 5v of noise Delay through the inverter is approximately 12 nsec for lightly loaded inverters driven by pulse Figure 23 shows the inverter circuit schematically BUS DRIVERS Type R650 Bus Driver modules are used by the ID to drive AC output lines in programmed data output transfers The R650 contains two inverting bus drivers for driving heavy current loads to either ground negative voltages In this application terminals S are grounded to insert an integra
17. device select codes 00 through 07 and a section for optional equipment used to expand the DS for all other select codes Each channel of the optional DS consists of a Type W103 Device Selector module and a W640 Pulse Amplifier module Complementary output signals from bits 6 11 of the 1OT instruction in the MB are distributed to all channels of the optional DS These six bits serve as a device select code The 1 or O signal from each MB bit is wired or disconnected in each W103 module to enable a gate only when a pre established select code occurs in the OT instruction When enabled by the correct select code W103 module duces any OP pulses as complementary IOT command pulses Positive IOT pulses are buffered by a cir cuit of W640 module before being transmitted over long cables to peripheral devices These pulses are used in O devices for functions such as clearing flags gating data setting operation modes etc The last digit of any pulse designation corresponds to the number of the pulse which causes generation of that IOT pulse e g combination of a device code XX with pulse produces 4 pulse select code assignments are given in Table 4 Pulse outputs of the W103 Device Selector module are 100 nsec or 400 nsec collector outputs and can drive any standard R series FLIP CHIP module located in the proximity of the package However most options are located at som
18. of a NOR gate in each module of the MA Address Accepted Output Signal At time of the break cycle the DATA B level combines with timing pulse T to produce ADDR ACC pulse called DATA ADDR MA pulse in early systems This pulse transfers the memory address in the address register of the I O device into the processor MA This pulse also acknowledges to the external device that its address has been accepted Data Information Input Signals The 18 DI lines establish the data to be transferred into the MB from an external device during a data break in which the direction of transfer is into the PDP 7 The DI signal levels presented to 2 input negative NAND diode gates at the binary 1 input of the MB are transferred into the MB by the DATA ACC pulse This information in the MB is then written into core memory during a normal write operation The DI signals are to designate a binary 1 or ground potential to specify binary 0 and should be available at the time the break request is made _ Data Accepted Output Signal During time T3 of a data break cycle when the external device requests a transfer into the PDP 7 the DATAeB level causes a negative DATA ACC pulse called DATA INFO in early systems to be generated This pulse strobes the data input gates of the MB to transfer a data word from an external de vice into the MB This pulse is also an output for device synchronization Starting at time T5
19. output of each MB flip flop is buffered by a non inverting bus driver and supplied to the interface connection for strobing by the device The DATA INFORMATION signals are available by T3 time of the break cycle and must be strobed by the DATA READY pulse or a pulse derived from it no later than 400 nsec after T2 time of the cycle follow ing the break Figure 22 also shows this data information interface logic of the computer 34 of Computer Figure 22 Data Information Input and Output Interface 4 DIGITAL LOGIC CIRCUITS component circuits in the PDP 7 are standard digital logic circuits as described in the Digital Logic Handbook C 105 Functional operation of basic circuits typical applications and detailed descriptions for the complete line of circuit modules available for construction of interfaces are presented in this cata log The PDP 7 uses four types of circuits to transmit or receive signals from other equipment inverters bus drivers pulse amplifiers and diode gates INVERTERS Type B105 Inverter modules are used throughout the computer for gating inverting and buffering The DATA BREAK REQUEST or DATA RQ signal is received from external equipment by 105 in the data break facility The PROGRAM INTERRUPT REQUEST or PROGRAM REQ signal is received from I O devices by a B124 Inverter module Internal common collector connections on groups of three inverters facilitate use of this module as
20. pese x lt IOT 0304 B IOT 7502 IOT 7404 CA A 96 Signal IOT 7602 7304 TABLE 1 INPUT SIGNALS continued Signal Destination in Package KA71A Signal Destination in Processor KA77A Symbol 3 Interface Module Module Logic Drawing Module Module Logic Drawing Connector Terminal Type Element Number Terminal Type Element Number __________________________________________________________________________ _________________ __ __ _____ __ _________ ZS ACB01 1 ACB02 1 ACB03 1 ACB04 1 ACB05 1 ACB06 1 s Y P YW 2 21 TABLE 2 OUTPUT SIGNALS Signal Origin in Signal Origin in I O Package Package Signal Origin in Package Z n se ACB E poem e Dmm E n a se Signal Origin in Processor KA77A ACBOB E won 7 R650 AC Bus Drivers ACB09 1 ACB10 1 ACB13 1 ACB14 1 ACBI5 1 E ii J14M J21M J14P J21P 145 215 W021 MO8T R650 R650 AC Bus Drivers AC Bus Drivers M09 J R650 AC Bus Drivers M10J M10T R650 AC Bus Drivers AC Bus Drivers R650 AC Bus Drivers Drawing Number 8S TABLE 2 OUTPUT SIGNALS continued Signal Origin Pac
21. side at the front of the machine or from right to left as viewed from the module side at the back of the machine Terminals of a module receptacle are assigned capital letters from top to bottom omitting 1 O and For example AO3E in the package is in the top module row A the third connector from the left 03 and the fifth terminal from the top E logic signals that pass between the PDP 7 and the equipment are standard DEC levels or standard DEC pulses Logic signals have mnemonic names that indicate the condition represented by assertion of the signal Standard levels are either ground potential 0 0 to 0 3v designated by an open diamond lt gt or are to 4 0v designated by a solid diamond Standard pulses in the posi tive direction are designated by an open triangle gt and negative pulses are designated by a solid triangle Pulses originating R series modules positive going pulses which start at go to ground for 100 nsec then return to Pulses originating in B or W series modules are bipolar are always referenced to ground are 2 5v in amplitude 2 3 to 3 0v with a 2v overshoot and are of 400 nsec duration or 1 psec if selected on the W640 Tables 1 and 2 provide connections distribution and logic circuit information for the basic PDP 7 inter face signals Numbers in the Drawing Number column of these tables should
22. speed drum memories or CRT display systems containing memory elements PERTINENT DOCUMENTS The following publications serve as source material and complement the information in this manual 1 Digital Logic Handbook C 105 This book describes the functions and specifica tions of FLIP CHIP modules and module accessories used in the PDP 7 control interfaces and peripheral devices 2 PDP 7 Brochure F 71 This leaflet presents the basic functions of the PDP 7 hardware software instructions and standard optional equipment 3 PDP 7 Users Handbook F 75 This book contains computer organization in formation detailed information on the function of interface facilities and de scriptions of the timing and operations performed by all instructions 4 PDP 7 Maintenance Manual F 77A This manual gives functional descrip tion principles of equipment operation interface installation operating procedures and detailed maintenance information for machines with serial numbers above 100 5 Instruction manuals for appropriate input output device options used in PDP 7 systems are available 6 PDP 7 Price List F 72 This leaflet contains current price information on the basic computer computer options and standard input output equipment LOGIC SYMBOLS Figure 2 defines the symbols used to express digital logic circuits and signals in the illustrations of this manual DEC STANDARO NEGATIVE PULSE DEC STANDARD
23. the DS provide input connections to each gate as shown in Figure 10 In this manner IOT instruction can check the status of an I O device and skip the next instruction if the device requires servicing Programmed testing in this manner allows the routine to jump out of a sequence to a subroutine that services the device tested Assuming that a device is already operating a possible program sequence to test its availability follows Address Instruction Remarks 100 703401 SKIP IF DEVICE 34 IS READY 101 6001 00 JUMP 1 102 1OXXXX ENTER SERVICE ROUTINE FOR DEVICE 34 e lt 40 SEN AS 7 N 170 SKIB A 4 SERV FACILITY i 2 a uet p di Pd ad lt gt 2 di O WX FROM DEVICE 7S D oo 7 SEL e d 24 COMPUTER PROGRAM INTERRUPT FACILITY Pd 24 xs Wop gu Figure 10 Input Output Skip Facility 15 When the program reaches address 100 it executes an instruction skip with 703401 The skip occurs only if device 34 is ready when the IOT 3401 command is given If device 34 is not ready the flag signal disqualifies the IOS gate and the skip does not occur Therefore the program continues to the next in struction which is a jump back to the skip instruction In this example the program stays in this waiting loop until the device is ready to transfer data at which time the gate in the IOS is enabled and the skip occurs When
24. the device requires servicing the condition of the flag connected to the Type 8124 Inverter module in location 027 of the I O package 78 can request a program break The flag of the external device should also be connected to the skip facility so that the interrupt program can sense the OT 01 pulse to determine the device requesting the program break The PROGRAM INTERRUPT signal level is the NOR of requests from up to nine devices that require programmed attention The program interrupt facility can be expanded to accommodate re quests from nine additional devices by inserting another Type 8124 module in location 028 of the package When the program break is entered a subroutine 15 initiated to determine which device of many is to be serviced and then to perform the appropriate service usually by supplying or receiving data under program control Data Break Request Input Signal A high speed device may originate a data break request by placing a DATA RQ level on the request line connecting the device to the computer In the interrupt control the DATA RQ level is synchronized with delayed timing pulse T5 T5 DLY of the current computer cycle and sets the DATA SYNC flip flop to 1 This causes a BK RQ level to be transmitted to the major state generator Com pletion of the current instruction permits the major state generator to enter a break state producing a B l vel This B level combines with the DAT
25. the skip occurs the instruction in location 102 transfers program control to a subroutine to service device 34 This subroutine can load the AC with data and transfer it to device 34 or can load the AC from a register in device 34 and store it in some known core memory address INFORMATION COLLECTOR IC The information collector is a 7 channel gated input mixer that transfers bytes of up to 18 bits into the AC from signals supplied by an external device Each channel consists of 18 2 input diode AND gates trig gered a common IOT command pulse from the DS Usually the IOT instruction that strobes information into the AC via the IC is microprogrammed with bit 14 containing 1 50 that the AC is cleared at event time 1 Figure 11 shows the IC logic circuit configuration The perforated tape reader and I O status bits each occupy one 18 bit IC channel The teleprinter occu pies eight bits of a third channel The remaining four and one half channels are available for connection to any peripheral and optional input equipment Each PDP 7 input option connects directly into one or more channels of the IC For operation of more than seven input devices the IC is easily expandable in blocks of seven channels to accommodate any number of channels INFORMATION DISTRIBUTOR ID The ID 15 an output bus system that transfers information from the AC to external devices Accumulator output signals are buffered by 18 bus driver circuits and driv
26. the status of flags for all equipment connected into the system When this routine issues IOT instruction 700301 the 1 status of the keyboard flag is identified and program control jumps to a subroutine that services the keyboard This subroutine assuming that the L and EPC need not be restored before returning to the main program could consist of the following 24 OPERATING PROGRAM BREAK REQUEST BREAK GRANTED PROGRAM INTERRUPT DIS ABLED TO PREVENT OTHER INTERRUPTS FROM OCCUR RING UNTIL THIS INTERRUPT IS COMPLETED CONTINUE PROGRAM LOAD BUFFER KEYBOARD OPERATIONS AND SUBROUTINES lt lt YES GENERATE CHARACTER SET KEYBOARD FLAG KEYBOARD FLAG SET NO YES INTERRUPT ENABLED NO REQUEST INTERRUPT STORE L PC IN LOCATION 000000 i m o JUMP TO FLAG CHECK SEQUENCE KEYBOARD rede FLAG SET 2 K FLAG 1 SKIP READ KEYBOARD BUFFER AND CLEAR KEYBOARD FLAG K SUBROUTINE TO STORE CHARACTER IN CORE MEMORY RESTORE L AND EPC IF NECESSARY ENABLE INTERRUPT ION RETURN TO INTERRUPTED PROGRAM JMPI 0 Figure 16 Programmed Data Input Flow Diagram 25 TELEPRINTER OPERATING OPERATIONS PROGRAM AND SUBROUTINES INITIALIZING COMMAND LOAD PRINT BUFFER AC gt PB GENERATE CHARACTER SET TELEPRINT FLAG al INTERRUPT ENABLED REQUEST INTER
27. was essentially an output device receiving data from computer the IOT then DAC I 10 sequence might be replaced by LAC 1 10 then sequence EXAMPLE OF PROGRAMMED DATA INPUT AND OUTPUT The following example explaining the function and connections of the Teletype unit and Type 649B Teletype control summarizes interfacing a device with programmed input and output data transfers using both program interrupt and skip facilities Figure 16 shows the sequence of operations for a transfer into the computer from the keyboard and Figure 17 shows the sequence for printing information transferred out of the computer Assume that a program is in progress and the keyboard of the Teletype is manually operated to send infor mation into the computer When the key is struck the control generates the 8 bit character and shifts it into a keyboard buffer one bit at a time When the character is complete in the register the keyboard flag is set to request a program interrupt If the program interrupt is enabled meaning the program in operation can be interrupted when the flag is raised a break occurs at the conclusion of the instruction in progress During the break cycle the contents of the link trap mode bit extended program counter EPC and the program counter are stored at core memory address 000000 and the next instruction is taken from address 000001 This instruction is usually a jump to an interrupt routine which checks
28. 19 Signal 1077202 1077204 IOT7301 1077302 1077304 10T7401 1017402 1077404 1017501 1017502 1077504 1017601 1077602 1017604 MBBO4 0 MBBO5 0 TABLE 2 OUTPUT SIGNALS continued Signal Origin in I O Package KATIA Origin in Signal Origin in Package KATIA Package KA71A E ttt aa 828 KR peo EC CA dol E NINE La E 3 7 GANE DR RN pe gt A NOR NEN S e we os pe o gt d Le fr a AAA rn ES ee ee E 0 20 ERN EL ONEN oe x _ _______ se nene Signal Origin in Processor KA77A Drawing Number 18 29 Signal MBBO9 0 MBB10 0 MBB11 0 MBB 2 0 MBBOO 1 MBBO 1 MBBO2 1 MBBO3 1 MBBOA 1 5 1 6 1 7 1 MBBO8 1 Signal Origin i Signal Origin in VO Package KA7IA Signal Origin in VO Package KA7IA Package KA71A Symbol Interface Module Module Logic Drawing Module Module Logic 9 Connector Terminal Type Element Number Terminal Type Element TABLE 2 OUTPUT SIGNALS continued JO3T 013 8684 MB Bus Drivers HO2M D24D B684 MB Bus Drivers H025 ONE CEN AN MB Bus Driver Signal Origin in Processor KA77A Drawing Number 9 _ MBBO9 1 MBBIO 1 MBB11 1 MBB12 1 MB
29. 22V Channel Flag 8 17 67 Signal MBB 06 1 MBB 07 0 MBB 08 1 MBB 09 1 MBB 10 0 MBB 10 1 MBB 11 0 MBB 11 1 T5 T DATA RQ DATA IN DATA ACC ADDR ACC DATA RD Y DATA SLO RQ MQ 00 1 MQ 01 1 MQ 02 1 MQ 03 1 MQ 04 1 MQ 05 1 MQ 06 1 MQ 07 1 MQ 08 1 H27D H27E H27H H27K H27M H27P 275 H27T H27V J28D J28E J28H J28K J28M J28P 285 J28T J28V 177 Extended Arithmetic Element HO3D HO3H HO3K HO3M HO3P HO3S HO3T HO3V 68 TABLE 3 PREWIRED INTERFACE CONNECTIONS continued Terminal Signal 172 Automatic Priority Interrupt continued OPI 2 4 CLK FLG 1 0004 B PWR CLR NEG BGN B MB 12 0 00 EN 173 Data Interrupt Multiplexer Control 09 1 MQ 10 1 11 1 MQ 12 1 MQ 13 1 MQ 14 1 MQ 15 1 MQ 16 1 17 1 Terminal H28D H28E H28H H28K H28M H28P 285 H28T H28V HO4D 4 HO4H HO4K HO4M HO4P 045 HO4T TABLE PREWIRED INTERFACE CONNECTIONS continued Signal Terminal Signal Terminal 177 Extended Arithmetic Element continued ACB 00 1 H14D ACB 09 1 7140 01 1 14 ACB 100 ACB 0241 HI 4H ACB 11 1 ACB 03 1 H14K ACB 12 1 0411 130 J14M ACB 05 1 HI4P ACB 14 1 J14P 06 1 145 150 7145 0711 ACB 160 ACB 08 1 4 ACB 17 1 JV SCI AC JD
30. A SYNC level to produce a negative B level An external device connected to the data break facility of the computer supplies a DATA RQ level a 15 bit core memory address for the transfer a signal indicating the direction of the transfer as into or out of the computer core memory and input or output connections to the MB for 18 data bits The DATA RQ level is sent to the computer at the time the data is ready fora transfer into the PDP 7 or when the data register in the external device is ready to receive information from the PDP 7 This request level must be 3v for assertion meaning request for a data break and drives a transistor base requiring 2 ma of input current Transfer Direction Input Signal This signal specifying the direction of data transfer for a data break 15 received by the computer from the requesting device Transfer direction 15 referenced to the computer core memory not to the device This signal 15 a level when the transfer direction 15 in is ground for transfer A 3 input NAND diode gate for negative levels receives this signal at terminal NI8F The gate also receives the internally generated DATA B level and pulse to cause generation of the DATA ACC pulse which strobes the DI lines into the MB 79 Data Address Input Signal During an ADDR ACC pulse of a break cycle the data address given by an device is transferred to the MA by connections made at the DA level input
31. B13 1 14 1 MBB15 1 MBB16 1 MBB17 1 TABLE 2 OUTPUT SIGNALS continued Signal Origin in Processor KA77A Signal Origin i Stanal Origin in O Package Stanal Origin in Package Package Signal Symbol Interface Module Module Logic Drawing Module Module Logic Connector Terminal Type Element Number Terminal Type Element E pe pm p eee CIE A NICA EUN E sC EEN pem eem _ Lem e oe n pem e em x w poe pem nn Im pp n pem em cy Drawing Number TABLE 3 PREWIRED INTERFACE CONNECTIONS Signal Terminal Signal Terminal 57A Automatic Magnetic Tape Control ACB 00 1 H16D ACB 09 1 J16D ACB 01 1 H16E ACB 10 1 J16E ACB 02 1 HI6H 11 1 030 H16K ACB 12 1 041 HI6M ACB 13 1 J16M ACB 05 1 16 14 1 J16P ACB 06 1 165 154 165 ACB 0711 H16T ACB 16 1 0841 16 17 1 J16V IOT 7002 H24D 7404 H25D IOT 7004 H24E PWR CLR NEG H25E IOT 7102 H24H BGN B H25H IOT 7104 H24K MBB 12 1 H25K IOT 7202 H24M MBB 12 0 H25M 7204 H24P H25P IOT 7302 245 255 7401 H24T H25T 7402 H24V H25V ERF ERF ENB J25D HO7D WCO WCO ENG J25E TCR J25H HO7H T READY J25K CA 03 1 HO7K DATA ACC J25M CA 04 1 HO7M ADDRESS ACC J25P 05 1 DATA IN 2256 CA 06 1 HO7S DATA RQ J2T CA 07 1
32. CA 15 1 CA 16 1 CA 17 1 140 Relay Buffer 66 ACB 09 1 ACB 10 1 ACB 11 1 ACB 12 1 ACB 13 1 ACB 14 1 ACB 15 1 ACB 16 1 ACB 17 1 Terminal 2240 J24E J24H J24K J24M J24P 1245 J24T J24V J19D J19E J1 H JI9K J19P 195 J19V TABLE 3 PREWIRED INTERFACE CONNECTIONS continued Signal Terminal Signal Terminal 172 Automatic Priority Interrupt Clear Flag 0 7 H12D Clear Flag 8 17 J12D Clear Flag 0 7 H12E Clear Flag 8 17 J12E Clear Flag 0 7 H12H Clear Flag 8 17 J12H Clear Flag 0 7 H12K Clear Flag 8 17 J12K Clear Flag 0 7 H12M Clear Flag 8 17 J12M Clear Flag 0 7 HI2P Cleor Flag 8 17 J12P Clear Flag 0 7 125 Clear 8 17 125 Clear Flag 0 7 H12T Clear Flag 8 17 J12T Clear Flag 0 7 H12V Clear Flag 8 17 J12V ACB 00 1 H18D ACB 09 1 J18D 01 1 H18E ACB 1001 J18E ACB 02 1 H18H ACB 11 1 J18H ACB 03 1 H18K 12 1 J18K ACB 04 1 13 1 J18M ACB 05 1 H18P ACB 14 1 J18P ACB 06 1 H18S 15 1 185 ACB 07 1 HI8T ACB 16 1 08 1 H18V ACB 17 1 Channel Flag 0 7 H22D Channel Flag 8 17 J22D Channel Flag 0 7 H22E Channel Flag 8 17 J22E Channel Flag 0 7 H22H Channel Flag 8 17 J22H Channel Flag 0 7 H22K Channel Flag 8 17 J22K Channel Flag 0 7 H22M Channel Flag 8 17 J22M Channel Flag 0 7 H22P Channel Flag 8 17 J22P Channel Flag 0 7 225 Channel Flag 8 17 1225 Channel Flag 0 7 H22T Channel Flag 8 17 J22T Channel Flag 0 7 H
33. CHECK PANEL MEMORY MEMORY CC DM A D CONVERTER DECTAPE NE NEN 34 DISPLAY OSCILLOSCOPE FANS FANS 176 MEMORY FOR TU55 PARITY CHECK 172 AUTOMATIC nn PRIORITY INTERRUPT BLANK rrr RATOR i BLANK CONSOL ari MAGNETIC BLANK EP 000 TAPE CONTROL KA77A TABLE PROCESSOR BLANK KATIA I O PACKAGE DECTAPE KBO3 DEVICE 177 EXTENDED CONTROL SELECTOR ARITHMETIC EXPANSION ELEMENT is I C EXPANSION d 828 POWERIRECEPTACOE FANS BLANK BLANK MAGNETIC TAPE MULTIPLEXER TRANSPORT INTERFACE 520 521 MULTIPLEXER MAGNETIC TAPE EXPANSION BLANK INTERFACE 5 4 BAY 3 BAY 2 BAYI 0 738 POWER SUPPLY POWER SUPPLY 728 POWER SUPPLY POWER SUPPLY 728 728 POWER SUPPLY POWER SUPPLY 779 POWER SUPPLY UNAVAILABLE TABLE 739 WER SUPPLY 328 T28 POWE P R TR POWER SUPPLY PME POWER SUPPLY POWER SUPPLY 739 RELAY PANEL 15 DELAYED REAL TIME TRANSFORMER REAR NOTE IF 522 INTERFACE IS USED TWO MOUNTING PANELS ARE REQUIRED Figure 30 Typical PDP 7 System Component Locations 85 POWER REQUIREMENTS The PDP 7 requires a source of 115v 60 cps single phase power On special request all equipment can be factory wired for 50 cps and or 220 to 250v power The power source must maintain the nominal voltage within 10 under normal and transient load cond
34. DI 16 DI 17 DA 09 10 DA 11 DA 12 DA 13 DA 14 DA 15 DA 16 DA 17 Terminal J30D J305 J30T J30V J32D J32E J32H J32K J32M J32P J325 J32T J32V The R650 Bus Driver has two types of outputs fast and slow or ramp Using fast output the bus driver operates as a fast amplifier When ramp output is used an integrating capacitor is inserted between the input of the bus driver and the output stage causing the output lines to move from ground to 3v or reverse in approximately 800 This connection desirable to reduce crosstalk between lines is used on the ACB buffered accumulator lines The W640 Pulse Amplifier modules should be carefully terminated If sufficient noise is generated at the output of these modules regeneration may result For this reason it is recommended that output lines of W640 Pulse Amplifier modules be well shielded The outputs of W640 modules may be either 400 nsec or l usec in width All connections on the standard PDP 7 use the 400 nsec pulse width All input signals to the PDP 7 are received by diode gates or inverters Diode gate inputs draw 1 ma of current from the driving circuit shared among all inputs at ground potential Inverter inputs draw 2 ma when the signal is at and provide no load when the signal is at ground potential Timing is in general determined by the machine itself However the following timing con
35. EC PULSE DATA INFORMATION FROM COMPUTER BREAK CYCLE le 120 NSEC i I i 600 NSEC 760 NSEC 390 NSEC lt 600 NSEC n 640 NSEC OE I T5 T6 17 T3 14 T5 T6 17 TI T2 n NO REQUEST LATEST POSSIBLE TIME TO REQUEST A BREAK EARLIEST POSSIBLE TIME TO REMOVE REQUEST REQUEST MUST BE REMOVED BY TS FOR THE NEXT CYCLE IS AT END OF ADDRESS ACCEPTED J IF NEXT CYCLE IS NOT TO BE A BREAK REQUEST NOT AVAILABLE ao LATEST POSSIBLE TIME TO DETERMINE DIRECTION IS T3 EARLIEST POSSIBLE TIME TO REMOVE DIRECTION IS AT END OF DATA ACCEPTED IN OR DATA READY OUT AVAILABLE mE LATEST POSSIBLE TIME TO AVAILABLE DETERMINE ADDRESS 15 1 OF BREAK EARLIEST POSSIBLE TIME TO REMOVE ADDRESS 15 AT END OF ADDRESS ACCEPTED AVAILABLE NOEL CEE lt sss s MEE LATEST POSSIBLE TO DETERMINE nd EARLIEST POSSIBLE TIME TO REMOVE INPUT WORD INPUT WORD IS AT T3 15 AVAILABLE cL LIT OL es cL ume GROUND 7 eee 3 VOLTS Tt GROUND 3 VOLTS i T3 GROUND 3
36. EMENTS The 7 processor and input output devices operate satisfactorily under ordinary conditions of humidity shock and vibration in a 50 to 122 F temperature range However a 70 to 85 F temperature range and a 30 to 80 humidity range are recommended Consult the system heat characteristics listed in Table 5 if room air conditioning is planned 83 REAR SPACE REQUIREMENTS EQUIPMENT TYPE 7T28A POWER SUPPLY 734A B C POWER SUPPLY 743A POWER SUPPLY 772A POWER SUPPLY POWER SUPPLY POWER SUPPLY 832 POWER CONTROL VERTICLE SPACE REQ D 8 INCHES 8 INCHES 12 INCHES 8 INCHES 12 INCHES 12 INCHES B INCHES Figure 29 ene D 5 1 4 INCH MOUNTING PANEL SPACE AVAILABLE ON REAR DOORS mijo ojo r c caja BAY 1 199 MEMORY FANS KA77A PROCESSOR FANS BAY 3 738 POWER SUPPLY 728 POWER SUPPLY 728 POWER SUPPLY 779 POWER SUPPLY 832C POWER CONTROL 15 DELAYEO REAL TIME TRANSFORMER 84 BAY 2 TAPE PUNCH BLANK POWER SUPPLY UNAVAILABLE TABLE 728 POWER SUPPLY Basic PDP 7 Component Locations BAY 3 INDICATOR PANEL MARGINAL CHECK PANEL 1 0 PACKAGE BAY 1 728 POWER SUPPLY 728 POWER SUPPLY 739 POWER SUPPLY 739 RELAY PANEL AM EN TYPICAL 4 INCHES zu BAY 0 BAY 1 BAY BAY 3 BAY 4 BAY 5 INDICATOR PANEL 1955 TAPE PUNCH TRANSPORT MARGINAL
37. H07T J25V CA 08 1 H07V 64 TABLE 3 PREWIRED INTERFACE CONNECTIONS continued Signal Terminal Signal Terminal 57A Automatic Magnetic Tape Control continued CA 09 1 DR LATE 10 1 PARITY ERR CA 110 HOSH READ COMP ERR H10H 12 1 EOF 130 WRITE LOCK HIOM 14 1 HOSP LOAD POINT H10P CA 15 1 HO8S END POINT 105 16 1 HOBT TRD WR LR H1OT CA 17 1 H10V REWIND H11D MISS CHAR 57A JOB DONE H11H FO4V FO5V FO6V HIIP FO7V HIIS FOBV FO9V H11V 138 Analog to Digital Converter H11H H10K F04V FO5V 06 H10S FO7V HIIS H10T F08V H11T H10V FO9V 65 Signal FOAV FO5V FO6V FO7V FOBV FO9V ACB 09 1 ACB 10 1 11 1 ACB 121 ACB 13 1 ACB 14 1 ACB 15 1 ACB 16 1 ACB 17 1 ACB 00 1 ACB 01 1 ACB 02 1 ACB 03 1 ACB 04 1 ACB 05 1 ACB 06 1 ACB 07 1 ACB 08 1 TABLE 3 PREWIRED INTERFACE CONNECTIONS continued Terminal 138 Analog to Digital Converter continued H23D H23E H23H H23K H23M H23P HIIS HIIT J20D J20E J20H J20K J20M J20P 205 J20T J20V HI9E HI9H HI9K HI9M HI9P H19S H19T H19V Signal 139 Multiplexer IOT 1101 IOT 1102 1201 12 1 CA 13 1 CA 14 1
38. INTERFACE AND INSTALLATION MANUAL DIGITAL EQUIPMENT CORPORATION MAYNARD MASSACHUSETTS F 78A 3 66 PDP 7 INTERFACE AND INSTALLATION MANUAL DIGITAL EQUIPMENT CORPORATION MAYNARD MASSACHUSETTS Copyright 1966 by Digital Equipment Corporation Chapter 2 3 CONTENTS INTRODUCTION s pU Rc S E e As Programmed Data Transfers Data Break Transfers Pertinent Documents D Logic Symbols no vs PROGRAMMED DATA TRANSFERS Timing Cycle dcs PRESA eR IOP Generator os vr sre nie i a4 RAI I hg Device Selector DS id as oA a Slow Cycle Facility Input Output Skip IOS Information Collector IC Information Distributor Dy Ses e en s Data Transfers into the PDP 7 Data Transfers out of the PDP 7 Program Interrupt 1 Multiple Use of IOS and Pl Example of Programmed Data Input and Output DATA BREAK TRANSFERS Data Break Facility Dota AddFess iia WES Sacs Data Information Input and Output DIGITAL LOGIC CIRCUITS eno Ro RR ADERAT BUS Drivers duse ws coe e Len v bes ve Pulse Amplifiers dd Diode Gates ii ow e INTERFACE CONNECTIONS
39. Input Signal sd ada 78 Data Break Request Input Signal Tm Maui 79 Transfer Direction Input Signal 79 Data Address Input Signal e Ie bate add 80 Address Accepted Output Signal 80 Data Information Input Signals oc 80 Data Accepted Output Signal a 80 Data Ready Output Signal ia 80 Data Information Output Signals 81 6 INSTALLATION PLANNING T es Physical Configuration oooooromooosososorororrorsncorsnsssss s 83 Environmental Requirements 83 Power Requirements DI 86 Cabling Requirements 86 Appendix 1 PDP 7 DEVICE SELECTOR AND INFORMATION COLLECTOR REQUIREMENTS FOR STANDARD OPTIONS M 89 ILLUSTRATIONS Typical PDP 7 Installation vii 2 Logic Symbols em TE noo 4 Figure O N O Oc Q ILLUSTRATIONS continued Programmed Data Transfer Interface Block Diagram Decoding of OT Instructions dr UD S ERRARE ARE Programmed Data Transfer Timing Diagram IOP Generator A asss Generation of IOT Comman
40. NC flip flop causes generation of a BK RQ or BREAK REQUEST signal level that establishes the break state for the next cycle if the current cycle completes an instruction Therefore to initiate a data break the DATA BREAK REQUEST signal must be present negative at the time the T5 DLY pulse occurs during the cycle immediately preceding the break Similarly when the break is granted the DATA BREAK REQUEST signal must be removed ground or open by the time the T5 DLY pulse occurs or the next cycle will also be a break state Note that a break state but not a data break can also be caused by a program interrupt PROG SYNC 1 signal or by the real time clock CLK SYNC 1 signal The 1 status of the DATA SYNC flip flop combines with the break condition of the major state generator to produce a DATA e B signal level that enables generation of the ADDRESS ACCEPTED or ADDR ACC DATA ACCEPTED or DATA ACC and DATA READY or DATA RDY pulses 3l Figure 20 Data Break Facility Interface of Computer 32 The 70 nsec negative ADDRESS ACCEPTED pulse occurs at 1 time of all data break cycles to strobe the 15 device supplied DATA ADDRESS signals into the computer MA and EMA extended MA registers This pulse available at the interface can be used by the device to remove the DATA BREAK REQUEST signal or to clear or change the data register in preparation for the next cycle The 70 nsec negative DATA ACCEPTED pulse occurs at T3 time of th
41. OLLET UU UU oe A EA E UNE ELI YE EN E NE NE AE A EA CA NEM MEE QUE LI M A EA MERA A EE EA 25 5 1 EA NN U EARL IE IMAN E NM NE SELINCE CE NEN NE ho UE ONCE NECS NEN NE LORI ILE EMBA DA E S 9y Signal MQ15 1 MQ16 1 MQ17 1 DTIOO 1 DTIO1 1 DTI02 1 DTIO3 1 DTIO4 1 DTI05 1 DTI06 1 DTIO7 1 DTI08 1 DTI09 1 DTI10 1 DTI11 1 DTI12 1 TABLE 1 INPUT SIGNALS continued Signal Destination in Package KA71A Interface Module Module Logic Drawing Module Module Logic Connector Terminal Type Element Number Terminal Type Element THOSE F02N R141 ER s 1HO5T R141 owe T 1 e E I L L Signal Destination in Processor KA77A Drawing Number Lv Signal DTI13 1 DTI14 1 DTI15 1 DTI16 1 DTI17 1 CA03 1 04 1 CA05 1 CA06 1 CAO7 1 CA08 1 CA09 1 CA10 1 CA11 1 CA12 1 CA13 1 TABLE 1 INPUT SIGNALS continued Signal Destination 1 Signal Destination in Package Signal Destination in Package Package Symbol Interface Module Module Logi
42. ONVERTER 139 MAGNETIC TAPE CONTROL 57A STATUS OR DECTAPE STANDARD PRECISION CONTROL TELETYPE arci a 550 KEYBOARD AS STATUS BUFFER CHANNEL 5 CHANNEL 6 CHANNEL 7 1 1 I 1 HO9 x 1 HO Hi MAGNETIC TAPE CONTROL 57A STATUS PRECISION L INCREMENTAL DISPLAY 540 X REGISTER Y REGISTER ANALOG TO lANALOG TO DIGITAL DIGITAL CONVERTER CONVERTER 138 ADBO 8 138 ADB9 17 Power Clear Output Signals The PWR CLR POS and PWR CLR NEG pulses generate in the I O package during the first 5 sec interval following setting of the POWER switch to the on position These pulses initialize and clear processor registers and controls during the power turnon period and are available to perform similar functions in external equipment The PWR CLR POS signal is a 375 kc 100 nsec positive pulse generated in the R401 Clock module at location C15 The PWR CLR NEG signal is a 400 nsec negative pulse pro duced in a pulse amplifier of the Type W640 module at location C13 that is triggered by the PWR CLR POS pulses Begin Buffered Output Signal The BGN B signal is supplied to external equipment through a connection in package interface This signal is a 400 nsec pulse generated by a W640 Pulse Amplifier at location C13 of the I O package during timing pulse SPIECONTINUE NOT In I O equipment the signal clears registers and resets c
43. RUPT BREAK REQUEST BREAK GRANTED STORE L EPC PC IN LOCATION 000000 JUMP TO FLAG CHECK SEQUENCE FLAG 0 NO SKIP TELEPRINTER FLAG SET CHECK NEXT FLAG 1 SKIP CLEAR TELEPRINTER FLAG LAST CHARACTER x SUBROUT IN LOAD NEXT CHARACTER INTO AC AND TRANSFER INTO PRINT BUFFER CLEAR TELEPRINTER FLAG PRINT COMMAND RESTORE IF NECESSARY ENABLE INTERRUPT ION CONTINUE PROGRAM RETURN TO INTERRUPTEO PROGRAM JMP I Figure 17 Programmed Data Output Flow Diagram 26 Octal Mnemonic Remarks 700312 KRB CLEAR AC THEN LOAD AC FROM CONTENTS OF KEYBOARD BUFFER AND CLEAR KEYBOARD FLAG O6XXXX DAC STORE WRITE CHARACTER AT ADDRESS CONTAINED AUTOINDEX REGISTER STORE 20XXXX LAC AC SAVE RESTORE AC FROM LOCATION AC SAVE 700042 ION ENABLE INTERRUPT SYSTEM FOR NEXT CHARACTER 620000 JMP 10 RETURN TO MAIN PROGRAM FROM ADDRESS STORED IN 00000 WHEN BREAK WAS STARTED Upon completion of this subroutine the main program continues and the keyboard awaits the next manual key operation Assume that the main program has accumulated and stored data in core memory and that the data is to be printed by the Teletype while the main program continues When the program recognizes the need to print it initializes a print subroutine by setting an autoindex register equal to the core memory addres
44. SEC PULSES 3 VOLTS GROUND 4 3 VOLTS GROUND VOLTS OPTIONAL DEVICE GROUND SELECTOR OUTPUT 400 NSEC PULSES 3 VOLTS GROUND E 9 3 VOLTS COMPUTER TIME TIMING PULSE GENERATOR GROUND COMPOSITE OUT TO NSEC PULSES 3 VOLTS MEMORY BUFFER AVAILABLE REGISTER OUTPUT AVAIL ABI E ACCUMUL ATOR DATA FOR NOT READY OUTPUT TRANSFER READr ACCUMULATOR CLEARED FOR NOT READY DATA INPUT TRANSFER IF 4 CONTAINS 1 READY IOP GENERATOR COMPOSITE GROUND OUTPUT 400 NSEC PULSES 3 VOLTS OPTIONAL DEVICE SELECTOR GROUND COMPOSITE OUTPUT 400 NSEC PULSES 3 VOLTS ANY INSTRUCTION FETCH CYCLE 1 75 MICROSECONDS 120 120 le a Vo NSEC 120 150 NSEC 120 NSEC a a LO iP i NSEC i 240 n 270 210 pla 240 k n 270 210 gt La 649 NSEG 6 T y 5 75 T6 m T5 T6 T2 T3 T5 T6 T T2 T3 T4 T5 T6 72 t 25 NSEC T4 100 NSEC T7420 dae 20 NSEC OF NEXT CYCLE T5440 NSEC MC E CECI Cr noe NNNM Tit 40 NSEC OF NEXT CYCLE gt NORMAL CYCLE ANY IOT INTRUCTION FETCH CYCLE 1 36 MICROSECONDS 2 PRESET PERIODS gt gt PRESET ACCORDING TO SLOWEST seer de Ed I O DEVICE M MIC RO
45. SECOND id ise ton Ti T4 T5 a ee Ye e UW T3 T4 5 T6 T T2 T4 75 Da wt Laos NSEC le 210 NSEC 120 120 Nos NSEC PRESET ACCORDING SLOWEST 1 0 DEVICE 1 MICROSECOND MINIMUM je 210 T6 16 100 NSEC 20 NSEC T44 100 NSEC 5 20 NSEC T7 20 NSEC T1 20 1 OF NEXT CYCLE IOP 4 11440 OF NEXT CYCLE 5 40 NSEC 77 40 NSEC Pas IOT XXO IOT IOT 4 b SLOW CYCLE Figure 5 Programmed Data Transfer Timing Diagram Devices which require immediate service from the computer program which take considerable computer time to discontinue the main program until transfer needs are met can use the program interrupt PI facility In this mode of operation the computer can initiate operation of equipment and continue the main program until the device requests servicing signal input to the Pl requesting a program interrupt causes storing of the conditions of the main program and initiates a subroutine to service the device At the con clusion of this subroutine the main program is reinstated until another interrupt request occurs TIMING CYCLE Cycle time of an IOT instruction is either normal or slow depending upon the device addressed see Figure 5 All devices use the normal cycle unless the device selector for the selected equipment is wired to re
46. VOLTS NOT AVAILABLE Ma T2 325 NSEC AVAILABLE mE AN A BREAK Figure 19 Data Break Transfer Timing Diagram The computer provides the following signals to the device using data break facility ADDRESS ACCEPTED Standard DEC 70 nsec negative pulse when device supplied address is strobed into MA DATA ACCEPTED Standard DEC 70 nsec negative pulse when device supplied information is strobed into MB DATA READY Standard DEC 400 nsec negative pulse when information is available in MB for strobing by external device The external device can use this pulse to strobe the MB information into its register either directly or when gate set up time is required after a delay of up to 1 psec DATA INFORMATION 18 bits 3v for 1 ground for O DATA BREAK FACILITY The data break facility controls entry into the break state to execute a data break and produces the pulses that strobe address and data into the computer and indicate data is ready to be strobed out of the computer Figure 20 shows the interface circuits of the data break facility Data break requests are synchronized with the computer timing cycle and the execution of instructions by a DATA SYNC flip flop The T5 DLY pulse T5 delayed 50 nsec sets this flip flop if the DATA BREAK REQUEST or DATA signal level 15 at making a request or clears it if the request 15 not made signal level is at ground When set the DATA SY
47. ach channel requires a different address or select code One device can therefore use several channels of the DS Figure 7 shows generation of command pulses by several channels of the DS IOP 2 4 MBB6 MBB7 MBB8 MBB9 MBBIO COMMAND PULSES TO DEVICE 34 I ss BUSSED INPUT TO ALL DEVICE SELECTORS Figure 7 Generqtion of IOT Command Pulses by Device Selector The logical representation for a typical channel of the DS using channel 34 is shown in Figure 8 A 6 input NAND gate wired to receive the appropriate signal outputs from MB6 11 for select code 34 acti vates the channel In the DS module the NAND gate contains 14 diode input terminals 12 of these con nect to the complementary outputs of MB6 11 and 2 are open to receive subdevice or control condition signals as needed Either the 1 or the O signal from each MB bit is disconnected by removing the appro priate diode from the NAND gate when establishing the select code The ground level output of the gate indicates when the IOT instruction selects the device and can therefore request a slow cycle for the device This output also enables three gating inverters allowing them to trigger pulse amplifier if an pulse occurs The positive output from each pulse amplifier is an IOT command pulse identified by the select code and the number of the initiating IOP pulse Three inverters receive the positive pulses to produ
48. al conditions one input of each of the three gates that trigger pulse amplifiers to produce the IOP pulses Each 3 input NAND gate is operated by the condition of a bit in the instruction and a computer timing pulse to produce one of the sequential pulses Each IOP pulse goes to one gate of all device selector channels to allow generation of an IOT command pulse at one of the three se quential event times within the instruction Figure 6 shows the computer timing pulses and instruction kit conditions which generate each IOP pulse for the three event times 10 TIME 2 EVENT TIME 3 Figure 6 IOP Generator DEVICE SELECTOR DS The DS selects an device or subdevice according to the address code of the device specified in bits 4 through 13 of the IOT instruction Selection of the device can request a slow cycle The DS then gener ates command pulses for each IOP pulse received and transmits these commands to the IOS the IC and or the device Generally IOT command pulses are used as follows Command Use 1 Applied to the IOS to sense the condition of the device flag XX02 Applied to the IC to transfer data into the computer or applied to the device to initiate a data transfer from the computer and clear device flags XX04 Applied to the device to initiate some operation start read etc Each group of these command pulses requires one channel of the DS and e
49. anels of options Core Memory Module 147 Fits in first bay of basic PDP 7 12 16K memory requires minimum four bay configuration Depth incl Dimensions wa inches O 17 1 2 27 1 16 32 3 8 27 1 16 27 1 16 51 30 1 4 10 27 1 16 Core Memory Module 147 continued 20 32K memory requires five bay configuration Draws no extra power Extended Arithmetic Element 1778 Fits in second bay of standard 7 TABLE 5 INSTALLATION DATA 2 1 4 8 3 4 18 5 16 8 3 4 30 18 5 8 Dual DECtape Transport 555 Provision is made for installation of this unit in bay two of standard PDP 7 Table model dimensions are given Also can be mounted in two mounting panel positions DECtape Control 550 Mounted in standard bay This information is invalid for PDP 7 s with serial numbers below 100 Mounted within basic computer Service Clearance Required inches d Bos o C AE Magnetic Tape Transport 570 Nonstandard cabinet Oscilloscope Display 34F Space for control logic is provided in basic package Oscilloscope RM503 requires additional panel or may be mounted externally Current Amps 0 62 0 45 0 12 1 73 0 69 0 12 Card Reader amp Control Table top model Requires one panel of additional cabinet space CRT Display 340 Requires one panel in bay three for cable connection to the external cabinet 87 Heat Dissipation Power Dissipatio
50. anual control and visual indication of programmed operations An 18 bit switch register per mits manual entry of data and instructions or status information to be sensed by the program The console displays all active registers including the memory address register memory buffer register accumulator link bit machine state instruction register program counter register and multiplier quotient register of the optional extended arithmetic element The basic PDP 7 system consists of a Type KA77A Processor Type 149 Core Memory and Package composed of FLIP CHIP circuit modules and solid state power supplies These hybrid silicon FLIP CHIP is a trademark of Digital Equipment Corporation Maynard Mass 1 circuits have an operating temperature range exceeding the limits of 32 to 122 F so no air conditioning is required at the computer site Standard 115v 60 cps power operates the computer The basic system is self contained in a 3 bay cabinet 69 1 8 inches high and 61 3 4 inches wide This unit weighs ap proximately 1150 lb requiring no subflooring or bracing In addition to the standard tape reader tape punch and Teletype keyboard reader the PDP 7 system can operate over 64 input output devices Existing interface designs permit connection of a number of DEC options to the computer including devices such as line printers magnetic tape transports magnetic drums card equipment analog to digital
51. be prefixed by BS D KATA 0 or BS D KA77A 0 to form the complete number of engineering drawing that shows 41 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 12 02 03 04 05 06 07 08 09 10 0t INFORMATION DISTRIBUTOR INFORMATION COLLECTOR DATA ADDRESS 3 8 DATA ADDRESS 3 8 IN IN 0 8 0 8 lt lt a lt E lt a A 172 PI SIGNALS 172 API MBB S o IOT S 57A SIGNALS 57A 1015 SIGNALS 172 CHANNEL FLAGS 0 7 140 172 177 550 57 340 172 CHANNEL FLAG CLEARS 0 7 IC LEVEL IC LEVEL IC LEVEL IC LEVEL IC LEVEL IC LEVEL IC LEVEL IC LEVEL 0 8 9 17 9 17 IC LEVEL 3 0 8 MBB O 1 8 1 MBB O 8 t DATA ADDRESS 9 17 DATA ADDRESS 9 17 9 17 9 17 IN i IN Ini DATAIDATA 73 SIGNALS 173 SIGNALS 340 SIGNALS SIGNALS 139 SIGNALS o Qt o 8 172 CHANNEL FLAGS 10 17 m o a 2 a E o a m lt 5 gt 2 o O 172 CHANNEL FLAG CLEARS 10 17 177 EAE SC SIGNALS IC 0 8 TO PROCESSOR 9 17 TO PROCESSOR MISCELLANEOUS PROCESSOR SIGNALS MISCELLANEOUS PROCESSOR SIGNALS PROCESSOR TIMING PULSES MISCELLANEOUS PROCESSOR SIGNALS MISCELLANEOUS PROCESSOR SIGNALS MBB 4 0 12 0 MBB 9 1 17 1 MBB 9 1 17 1 gt 42 Interface Cable Connector Locat
52. c Drawing Module Module Logic Connector Terminal Type Element Number Terminal Type Element MESE HE EE NN MIN MUN 1H06P R141 SI DE n fe a p 1 T s T T T p TI L a A DE eee lt 1 I j xe _ I Signal Destination in Processor KA77A Drawing Number 87 Signal CA14 1 CA15 1 CA16 1 CA17 1 DATA FLG BLK FLG ERR FLG OFF END MISS IND REV STATUS GO TRK ERR UNABLE DR LATE PARITY ERR TABLE 1 INPUT SIGNALS continued Signal Destination Package KA71A nn t im ame eee LTE d CR EN Rie NN Tne IL HO9E EO2T R141 a A we fe fe EIA EIA MC O UNE HO9T R141 Signal Destination in Processor KA77A Drawing Number Signal EOF WRITE LOCK LOAD POINT END POINT TRD WR LR A B FR TTIOO 1 TTIO1 1 TTI02 1 TT103 1 TTIOA 1 11105 1 11106 1 111070 REWIND MISS CHAR TABLE 1 INPUT SIGNALS continued Signal Destination i Signal Destination in Package KATIA Signal Destination in Package KATIA Package
53. ce complementary IOT output pulses A pulse amplifier module can be connected in each channel of the DS to provide greater output drive or to produce pulses of a specific duration required by the selected device 500 4 4 e 87 MIO gt gt 49 me Q 2 9 SES AS A 2 o lt o EN o lt gt se lt AS lt lt 3 DAN Figure 8 Typical Device Selector Device 34 SLOW CYCLE FACILITY Up to twelve devices can request a slow IOT cycle by connecting the ground level select signal output of the DS channel to the slow cycle request facility This facility consists of a 12 input diode NOR gate for ground levels as shown in Figure 9 None of the basic PDP 7 input output devices require a slow cycle LEVELS FROM DEVICE SELECTOR TO REQUEST SLOW CYCLE FOR UP TO 12 DEVICES Figure 9 Slow Cycle Facility INPUT OUTPUT SKIP IOS The condition of an I O device flag and generation of pulse combine in the IOS to cause the program to skip over one instruction Incrementing the program count without executingthe instruction at the current program count causes skipping The 105 facility consists of multiple 2 input AND gates with outputs nected in parallel to allow any gate to trigger the pulse amplifier which produces the IO SKIP pulse flag or status level from the device and an IOT pulse from the appropriate channel of
54. converters CRT displays and digital plotters The PDP 7 system can also accept other types of instruments or hardware devices that have an appropriate interface The simple techniques of the PDP 7 allow inexpensive straight forward device interfaces to be realized Any device interface needs control to determine when an information exchange is to take place and to specify the location s in the computer core memory which accept or yield data Either the com puter program or the transferring device may exercise this control Transfers made under control of the computer program are called programmed data transfers Transfers made under control of the external device are called data break transfers PROGRAMMED DATA TRANSFERS The majority of transfers occur under control of the computer program The maximum realistic rate of transferring 18 bit words is 33 kc in the program interrupt mode Normally this speed is well beyond that required for laboratory or process control instrumentation To transfer and store information under program control requires about six times as much computer time as under data break control In terms of real time the duration of a programmed transfer is rather small due to the high speed of the computer To realize full benefit of the built in control features of the PDP 7 programmed I O transfers should be used in most cases Controls for devices using programmed data transfers are usually simpler and less expens
55. d Pulses Device Selector Typical Device Selector Device 34 Slow Cycle Facility suse een a anes es we Macer di io RA Rr Input OUtpul Skip Facilily eo Information Collector and Information Distributor Programmed Data Input Transfer Programmed Data Output Transfer Program Interrupt Facility Multiple Use of IOS and PI e oe e e 9 e 0 e 0 Programmed Data Input Flow Diagram Programmed Data Output Flow Data Break Transfer Interface Block Diagram Data Break Transfer Timing Diagram 9 9 9 9 e O 6 5 9 e e Data Break Facility Interface of Computer Data Address Input Interface of Computer Data Information Input and Output Interface of Computer Inverter Circuit Bus Driver Output Circuit Pulse Amplifier Output Circuit Diode Gate Circuit ea Interface
56. e output of a diode gate with an internal clamped load resistor can drive an 18 ma external load A flip _ consists of two cross connected diode gates The direct set and clear terminals draw 1 ma The out put capability is 20 ma less 2 ma for the load resistor permanently connected in the flip flop and 1 ma required to condition the opposite side of the flip flop The flip flop can therefore drive a 17 ma ex ternal load The DCD gate circuits on flip flops and pulse amplifiers draw 2 ma at the level inputs 3 ma at the pulse inputs when the level is conditioned and 1 ma when the level input is disabled When two DCD gates are driving both sides of the same flip flop the load on both pulse inputs totals only 4 ma When the level inputs are tied together as in a complement configuration the total input load is only 3 ma Capacitive loading adversely affects the performance of series R modules therefore where long lines are being driven extra clamped loads should be added to sufficiently discharge the cable capacitance As a general rule an extra 2 ma of clamped load current should be added for every foot of wire beyond 1 1 2 ft An exception to this rule is the R650 Bus Driver module This module is designed to drive co axial cable of 100 ohm characteristic impedance through a series driving resistor If coaxial cable is not used the direct output may be used when the lines are short If reflections occur on the line the resis t
57. e data break cycle if the device supplied TRANSFER DIRECTION signal level is at 3v to specify a data direction into the computer This pulse strobes the 18 device supplied DATA INFORMATION signals into the MB and is available at the interface for use by the device to clear and or change the data buffer register for the next cycle The direction of a data break transfer is always stated with respect to the computer The TRANSFER DIRECTION signal should be gt to specify a transfer into the PDP 7 should be ground to specify a transfer out of the PDP 7 This signal should be present at the time the data break request is made however it need not be present until T3 of the break cycle B The 400 nsec negative DATA READY pulse occurs at T3 time of all data break cycles This pulse is not used in the computer but is produced for the device to use directly or delayed to allow for gate setup time to strobe the 18 computer DATA INFORMATION signals into its data buffer register DATA ADDRESS Fifteen DATA ADDRESS or DA signals are recieved from the external device to specify the core memory address to be used for the data break transfer These signals are to signify a binary 1 They should be present when the data break request is made but may be delayed if they are settled prior to Tl time of the break cycle These signals are received by a 2 input NAND gate at the 1 input of each MA flip flop and extended MA flip flop Since the
58. e device and therefore do not affect the arithmetic or program control elements of the PDP 7 Transfer rates of up to 571 000 words per second or over 10 million bits per second can be realized through this independent data handling channel Figure 18 shows information flow to effect a data break transfer with an device Figure 19 indicates timing requirements for input and output control and data signals and the availability of register data signals DATA MEMORY ADDRESS ADDRESS ADDRESS 15 REGISTER MA DATA INFORMATION 18 BITS IN CORE MEMORY DATA MEMORY BUFFER REGISTER M8 DATA INFORMATION 18 BITS OUT CONNECTIONS TO INPUT OUTPUT DEVICE ADDRESS ACCEPTED DATA ACCEPTED DATA BREAK FACILITY DATA BREAK REQUEST TRANSFER DIRECTION IN Figure 18 Data Break Transfer Interface Block Diagram External devices requesting storage or retrieval access to core memory supply the following signals to the computer DATA BREAK REQUEST 3v for assertion TRANSFER DIRECTION for into PDP 7 ground for out DATA ADDRESS 15 bits for 1 ground for 0 DATA INFORMATION 18 bits 3v for 1 ground for O 29 08 COMPUTER TIME DATA BREAK REQUEST TRANSFER DIRECTION DATA ADDRESS DATA INFORMATION TO COMPUTER ADDRESS ACCEPTED 70 PULSE DATA ACCEPTED 70 NSEC PULSE DATA READY 400 NS
59. e distance and require signal transmission over relatively long cables The W640 Pulse Amplifier modules are capable of driving cables and are wired into appropriate locations to transmit OT pulses to external devices The W640 produces 400 nsec pulses or 1 pulses when appropriate terminals are connected together Information Collector The IC reads data or status information into the AC from various devices Seven channels or levels available in the basic machines Each of these channels is wired to a signal cable connector correspond ing to an upper half bits 0 8 and a lower half bits 9 17 of the AC for optional equipment or is wired directly to controls for the standard PDP 7 equipment On the basic machine the paper tape reader occupies one complete channel the Teletype occupies the lower half of a channel and the status register occupies nominally one channel If no card reader card punch or line printer is connected to the system the lower half of the status register channel may be used for other purposes Thus in the basic machine the equivalent of five free channels is available for additional IC inputs Channel availability of the IC is specified as follows 74 GZ TABLE 4 CODE ASSIGNMENTS 00 1 RT Clock 10 Symbol 20 Memory 60 Serial 70 Auto Magnetic 2 Prog Interrupt Generator Increment Drum Tape Control 4 RT Clock Type 33 Type 197 Type 24 Type 57A
60. e for analog to digital or CRT display options Larger systems are constructed by adding standard computer bays to either or both sides of the basic machine and or in free standing cabinets Memory options above mount in bays to the left of the processor and additional I O options mount to the right of the I O package The location of many options is fixed for technical reasons For example the Extended Arithmetic Element Type 177B mounts above the Power Receptacle Type 828 in the center bay of the basic machine Preferred locations for most options are shown in Figure 30 Each standard DEC cabinet bay can accommodate twelve module mounting panels However the top and bottom locations are reserved for indicator panels fans etc and should not be used to mount logic cir cuits Standard cabinet bays are joined by removing end panels and bolting the frames together Over all dimensions are then reduced by the width of the removed end panel 1 1 4 inches per side weight is reduced 45 pounds per end panel Access to all logic wiring is from the console side of the computer cabinet bays are mounted on four heavy duty casters The floor plan for the basic PDP 7 shown in Figure 31 can be used for installation planning Table 5 summarizes physical and electrical data for the basic PDP 7 and for most optional equipment The number of cabinet bays required for a particular installation can be determined from this table ENVIRONMENTAL REQUIR
61. en through cables to the package The ID in the package contains nine 18 bit connection points or channels for each bussed signal one channel receives bussed connections from the processor seven channels are available for individual de vice cable connections one channel is for external expansion of the ID The paper tape punch and teleprinter receive AC output signals directly from the bus drivers and do not require connection through the ID If all seven channels are used the ID can be expanded to any of output channels adding suitable non inverting buffering and distribution channels similar to the standard ID 16 nd Information Distributor Figure 11 Information Collector a Sao PN sevice 2 dt a Figure 12 Programmed Data Input Transfer DATA TRANSFERS INTO THE PDP 7 XX02 and IOT XX04 command pulses control an external input device as indicated in Figure 12 When ready to transfer data into the PDP 7 accumulator the device sets a flag connected to the IOS The program senses the ready status of the flag and issues an IOT instruction to read the contents of the external device buffer register into the AC Usually this instruction contains a clear AC command and an XX02 XX12 to effect the transfer If the AC 15 cleared before the transfer the resultant word in the AC is the inclusive OR of the previous word in the AC and the word transferred from the de
62. erred to the interrupt routine The program interrupt routine as described 27 previously for the keyboard senses the status of flags for all devices connected to the interrupt facility until it determines the device requesting service When the TSF instruction is given IOT 700401 to skip on the ready status of the printer flag the print subroutine is again entered to load and print the next character At exit from the subroutine the main program is reentered from the point of the program break If the main program is an arithmetic routine that uses the link or a routine using extended memory the AC L and EPC s be restored by the device service routine prior to issuing the ION instruction Res toration of the L is accomplished by an instruction sequence such as Octal Mnemonic Remarks 200000 LAC 0 LOAD WORD CONTAINING L 740010 RAL ROTATE TO RESTORE Restoration of the EPC is described in the PDP 7 Users Handbook F 75 under the description of the Type 148 Memory Extension Control The AC should always be restored by the service routine 28 3 DATA BREAK TRANSFERS The data break facility allows one device to transfer information directly with the PDP 7 core memory on cycle stealing basis Up to four devices can connect to the data break facility through the optional Type 173 Data Interrupt Multiplexer Data break information transfers occur directly between the computer MB and a data register of th
63. es These command pulses are des ignated by the octal code of the twelve least significant bits of the instruction in which they are generated e g IOT 3401 usually bits 4 and 5 are unused and are assumed to be O s unless otherwise specified These IOT command pulses from the DS go to the IOS the IC and to a specific device whose action they control In this manner the program produces commands to transfer data into or out of I O devices to cause the program to skip or not skip an instruction based on the condition of an external device flag or to start stop or perform operations in devices controlled by a command pulse IOT instructions can use the normal computer cycle time of 1 75 usec or can occur in a slow cycle ad justed to the speed of the slowest device The device selector can be wired to cause entry into a slow cycle for any device when its select code is in the instruction being executed Figure 5 shows the timing of command pulses for devices using the normal or slow cycle and the availability of the AC for transfers COMPUTER TIME TIMING PULSE GENERATOR GPOUND COMPOSITE OUTPUT 70 NSEC PULSES 3 VOLTS NOT AVAILABLE AVAILABLE MEMORY BUFFER REGISTER OUTPUT NOT READY READY ACCUMULATOR DATA FOR OUTPUT TRANSFER ACCUMULATOR CLEARED FOR NOT READY DATA INPUT TRANSFER 14 CONTAINS A 1 READY GROUND 1 3 VOLTS GROUND OUTPUT 4 2 400 N
64. gure 25 DIODE GATES Type R141 Diode Gate modules are used in the IC and 105 to receive signals from peripheral devices The R141 consists of seven 2 input diode AND gates for negative signals whose outputs supply the inputs to a diode NOR gate Back to back diode circuit operations are facilitated by eu internal bias resistor connected to the input of each second stage diode The bias holds the input of the second stage at 3v unless one of the first stage inputs is grounded The total transition time is 45 nsec for output rise and 70 nsec for output fall The input receives standard 100 nsec pulses standard levels of 3v and ground 39 70 nsec negative pulses Input load is 1 ma per input pair shared by the grounded inputs When any pair of inputs is not being used at least one of the two must be grounded Figure 26 shows the basic circuit configuration 15V INPUTS 15V HOV _ INPUTS Figure 26 Diode Gate Circuit A Type B171 Diode Gate module is used in the package to receive SLOW CYCLE RE QUEST signals The 8171 is 12 input diode NOR gate for ground level signals additional inverter allows comple mentary output signals Typical total transition time is 40 nsec for output fall and 60 nsec for output rise Static input load is 1 25 ma A Type B115 Diode Gate module in the data break facility receives the TRANSFER DIRECTION DATA IN signal from the external device The B115 consists of
65. hese functions Tag Address 1000 1001 1002 0000 0001 FLG CK Instruction INTERRUPT JMP FLG CK 3401 SKP JMP SR34 4401 5 JMP 5 44 5401 SKP JMP SR54 Remarks MAIN PROGRAM MAIN PROGRAM COUNTINUES INTERRUPT REQUEST OCCURS OCCURS STORE LINK EPC AND PC PC 1003 ENTER ROUTINE TO DETERMINE WHICH DEVICE CAUSED INTERRUPT SKIP IF DEVICE 34 IS REQUESTING NO TEST NEXT DEVICE ENTER SERVICE ROUTINE 34 SKIP IF DEVICE 44 S REQUESTING NO TEST NEXT DEVICE ENTER SERVICE ROUTINE 44 SKIP IF DEVICE 54 IS REQUESTING NO TEST NEXT DEVICE ENTER SERVICE ROUTINE 54 22 N COMPUTER DEVICE SELECTOR o 9 COMPUTER PACITY LU p P Pa 4 2 PROGR FACILITY di BREAK STARTED uu PROGRAM INTERRUPT eM FACILITY ENABLED 2 es S STATUS FLIP FLOP Figure 15 Multiple Use of IOS and PI 23 Assume that the device that caused the interrupt is input device e g tape reader The following example of a device service routine might apply Tag Instruction Remarks SR DAC TEMP SAVE IOT XX12 TRANSFER DATA FROM DEVICE BUFFER TO AC DAC 110 STORE IN MEMORY LIST 152 COUNT CHECK FOR END SKP NOT END JMP END END JUMP TO ROUTINE TO HANDLE END OF LIST CONDITION RESTORE L AND EPC IF REQUIRED LAC TEMP RELOAD AC ION TURN ON INTERRUPT JMP 10 RETURN TO PROGRAM If the device that caused the interrupt
66. hese static levels into an device register The static level of each ACB output signal is when the bit is a binary 0 or 15 at ground potential when the bit is a binary The binary 1 output of each AC flip flop is power amplified by a Type 650 Bus Driver module in the processor and is applied to the ID for distribution to output devices These modules have terminals H and S connected to ground so that the output signals have rise time of approximately 800 nsec Without these terminals grounded the rise time is about 50 nsec Each R650 output delivers about 20 ma to ground The ID provides a series of nine output channels for connection to external devices for the buffered AC signals in locations 13 21 of rows and J of the package The prewired connections of the ID to the interface cable receptacles are listed in Table 3 76 LL CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 1 I x Jit HO3 1 4 HO5 HO6 ADDITIONAL STATUS OR STANDARD TAPE STATUS READER EXTENDED ARITHMETIC ELEMENT 177 STEP COUNTER SC12 17 EXTENDED ARITHMETIC ELEMENT 177 MULTIPLIER QUOTIENT REGISTER X DATA LINES PREWIRED NO CABLE CONNECTORS NEEDED Figure 28 Information Collector Channel Assignments DECTAPE CONTROL 550 DATA INPUT DTIO 17 MAGNETIC TAPE CONTROL 57A CURRENT ADDRESS OR PRECISION INCREMENTAL DISPLAY 340 DISPLAY ADDRESS COUNTER OR ANALOG TO DIGITAL C
67. ions and Assignments Figure 27 signal destination or signal origin in the package or processor Table 3 lists the interface terminals and connectors This prewiring simplifies installation of standard PDP 7 options Because of the large number of options available there is redundancy in the interface connector wiring This re dundancy has been planned so that two options not likely to be included in the same system use a common connector Some wiring changes and or ground jumper disconnections are required when connecting any device which the interface connectors are not prewired to receive Note that alternate terminals of the Type W021 Signal Cable Connectors carry ground lines for cable shields These grounds on terminals C F J L N R and U are not listed in Table 3 LOADING AND DRIVING CONSIDERATIONS All interface circuits within the PDP 7 consist of series R and W FLIP CHIP modules When interconnecting these circuits with those in the peripheral equipment it is important to keep the load on each circuit within its driving ability Driving and loading capabilities of most DEC modules used in the PDP 7 and in standard DEC optional equipment are specified in detail in the Digital FLIP CHIP Modules Catalog C 105 All inputs to series R modules consist of either diode gate or diode capacitor diode DCD gate circuits All inputs draw current in the same direction Each diode gate input at ground level draws 1 ma Th
68. itions The electrical characteristics of in dividual units are given in Table 5 CABLE ACCESS TYPICAL FOR 3 CABINETS REMOVEABLE CASTER SWIVAL RADIUS END PANEL 7 RS 615 E SWINGING DOORS 10 EN a N yt b y LOAD POINT REMOVEABLE END PANEL 5 We FAN TYPICAL FOR 3 CABINETS SCREEN TYPICAL FOR 3 CABINETS 5 fu 8 16 TABLE x FLOOR PLAN Figure 31 Basic PDP 7 Installation Dimensions CABLING REQUIREMENTS All system power sources should have 115v 30 amp Hubbel Twistlock flush receptacles or their equiv alent to mate with equipment power cables 86 Standard 7 Core Memory Module 147 Memory Extension Control 1 48 Core Memory Module 149A Priority Interrupt 172B Data Interrupt Multiplexer 173 Extended Arithmetic Element 177B Dual DECtape Transport 555 DECtape Control 550 Magnetic Tape Transport 50 Automatic Magnetic Tape Control 57A Magnetic Tape Transport 570 Magnetic Tape Transport 545 Serial Drum 24 Oscilloscope Display 34F CRT Display 340 Slave Display 343 18 Bit Relay Buffer 140 A D Converter 138E 64 Channel Multiplexer Control 139E Data Communication System 630 8 line Automatic Line Printer and Control 647 Card Reader and Control 100 cpm Typical Standard Cabinet Bay empty REMARKS Standard PDP 7 Third bay has space for five p
69. ive output of the bus driver may be used to correct the problem Shunt termination on the far end of the transmission line is not recommended 43 Signal RBOO 1 1 2 1 RBO3 1 RBO4 1 RBO5 1 RBO7 1 RBOB 1 RBO9 1 RB10 1 RB11 1 RB12 1 RB13 1 RB14 1 RB15 1 RB16 1 TABLE 1 INPUT SIGNALS Signal Destination i Signal Destination in Package KATIA Signal Destination in Package KATIA package Signal Destination in Processor KA77A Symbol Interface Module Module Logic ES Module Module Logic D rawing Connector Terminal Type Element Number Terminal Element Number EZ ER ER e pe ppp IS e 1 1 MARE 38 CR NN HIE Signal RB17 1 MQ00 1 MQ01 1 MQ02 1 MQ03 1 MQOA 1 MQ05 1 MQ06 1 MQ07 1 MQ08 1 MQO9 1 MQ10 1 MQ11 1 MQ12 1 MQ13 1 MQ14 1 TABLE 1 INPUT SIGNALS continued Signal Destination i Signal Destination in Package KATIA Signal Destination in Package KATIA Package symbol Interface Module Module Logic Drawing Module Module Logic Connector Terminal Type Element Number Terminal Type Element Signal Destination in Processor 77 Drawing Number Pee nn A yg HO3D L R141 NE SE IIS 2k N
70. ive than controls for devices using data break transfers Analog to digital converters digital to analog converters digital plotters line printers message switching equipment and relay control systems typify equipment using the programmed data transfer channels Using programmed data transfer channels simultaneous operation of devices is limited only by the relative speed of the computer with respect to the device speeds and the search time required to determine the device requiring service The percent of computer time taken for servicing is roughly 961 O time sum of device rates in cps x service time usec per interrupt x 1074 For comparison it takes less than 3 of computer running time to read or write conventional IBM compatible magnetic tape at 556 bits per inch and 75 inches per second DATA BREAK TRANSFERS Devices which operate at very high speed or which require very rapid response from the computer use the data break transfer channel This channel permits an external device almost arbitrarily to insert or ex tract words from the computer core memory bypassing all program control logic Because the computer program has no cognizance of transfers made through this channel programmed checks of input data are made prior to use of information received in this manner The data break is particularly well suited for devices that transfer large amounts of data in block form e g high speed magnetic tape systems high
71. kage KA71A Signal Origin in Processor KA77A Connector Terminal Type Element Number Terminal Type Element Number T DO wear IOTO102 D21T R603 NEN NUN NN RN 1070402 D23T R603 65 TABLE 2 OUTPUT SIGNALS continued Signal Origin in Sigal Origin in VO Package KAIA Sigal Origin in Package Signal Origin in Processor KA77A Signal Interface Module Module Logic Drawing Module Module Logic Drawing Connector Terminal Type Element Number Terminal Type Element Number _ II Le im __ 10T0704 CZE EN A A CR ERE we M U acne ed MUN LA f o m celu MEME DNE II id MENO SLE iind Pol RA ANE EIL MEE WS IUD 09 TABLE 2 OUTPUT SIGNALS continued Signal Origin in Package KA71A Signal Origin in Processor KA77A E ETICA al E oma m rm we os Tae O EN ma wama ona z prm e lt LE eje L L 1071204 E31U W640 oi ono LOU MES ce mu we os ee oe IOT2104 E27U W640 1 L ome ee me pes De we e LL me Due 1 Drawing Number
72. med decisions to continue current program or to jump to another part of the program such as a subroutine that services an I O device The DS generates command pulses during execution of input output transfer instructions All in structions stored in core memory as a program sequence are read into the memory buffer register MB to be executed The operation code in the four most significant bits bits O through 3 of the instruction is transferred into the instruction register IR and decoded to produce appropriate control signals When the operation code is recognized as an IOT instruction the generator produces time sequenced pulses a function of the three least significant bits of the instruction bits 15 through 17 in the MB The IOP pulses with an I O device selection code in bits 6 through 11 of the instruction are supplied as bus inputs to all gates of the DS The gating circuits of the DS associated with a specific device are enabled by the select code to regenerate 5 as specific command pulses Figure 4 shows the decoding of an instruction and Figure 5 indicates the timing of the IOP and pulses OPERATION CODE DEVICE CLEAR AC AT EVENT 70g INSTRUCTION SELECTION TIME 1 IF IS A 1 7 7 3 SUBDEVICE SuBDEVICE IOP PULSE SELECTION SELECTION GENERATION CONTROL Figure 4 Decoding of IOT Instructions One IOT instruction can generate one two or three sequential IOT puls
73. n Nineteen wire ribbon cables with Type W021 Cable Connectors provide signal connection between the computer and optional equipment in the basic computer cabinets or in cabinets bolted to the basic com puter bays These cables are connected by plugging the W021 Connectors into standard FLIP CHIP module receptacles Fifty wire shielded signal cables with Amphenol 115 11 4P male connectors at both ends interconnect the processor and peripheral equipment in separate free standing cabinets Any special equipment using these cables must have Amphenol 115 1145 female connectors and 1391 shells to accept signal cables Unless otherwise specified power cables are supplied in 25 ft lengths permanently wired at one end to individual units Signal cables come unattached in 25 ft lengths Power and 50 pin signal cables mea sure 11 16 and 13 16 inch in diameter respectively All free standing cabinets require independent 115v receptacles However these units may be turned on or off or controlled from the PDP 7 console Cables are connected to cabinets through a drop panel in the bottom of cabinets Subflooring is not necessary because cabinets are elevated from the floor by casters to afford sufficient cable clearance 88 APPENDIX 1 PDP 7 DEVICE SELECTOR AND INFORMATION COLLECTOR REQUIREMENTS FOR STANDARD OPTIONS The standard device selector on a PDP 7 with a tape reader tape punch and Teletype contains 12 spore selector channels
74. nformation in this manual applies only to PDP 7 systems with serial numbers above 100 Refer to the PDP 7 Interface and Installation Manual F 78 dated 1 66 for information on systems with serial numbers below 100 The PDP 7 is a digital machine designed for use as a general purpose computer an independent informa tion handling facility or as the control element in a complex processing system The PDP 7 is a single address fixed 18 bit word length parallel processing binary computer using 1 5 complement arithmetic 2 s complement arithmetic facilitates multiprecision operations Cycle time of the random access core memory is 1 75 psec permitting a computation rate of up to 285 714 additions per second Programming features of the computer include indirect addressing microprogramming combining instructions to occur in one 75 usec machine cycle and programmed monitoring of peripheral devices Real time features of the computer include program interrupt entry into a subroutine caused by a request from an device input output skip facility program flow modification as a function of the status of a selected peripheral device and high speed data break channel direct input output access to computer core mem ory for cycle stealing data transfers at a rate of over 10 million bits per second Eight autoindex registers simplify sorting searching and multiple input output list processing operations An operator console pro vides m
75. nnections open and assignable 6 First 10 connections are open and last 8 connections are assigned to Teletype unit 7 First 12 connections open and assignable Each level or channel of the IC consists of one 2 input negative AND gate for each of the 18 possible bits of an input word The two inputs are usually supplied by a data signal and an pulse which is common to each bit of the input word Outputs from the seven channels for each bit are NOR combined to set the appropriate accumulator flip flop One bit for each of the seven channels is provided by a 141 Diode Gate module the entire IC is constructed of 18 of these modules When designing a PDP 7 system it is necessary to consider the number of 1 channels required by peri pheral equipment If more than seven channels are required the IC must be expanded to accommodate the additional information Expansion requires a Type 175 Information Collector Expander consisting of 18 R141 Diode Gate modules 6 Type W640 Pulse Amplifier modules and the appropriate mounting panel and hardware The Type 175 option connects into the standard IC through two signal cable con nectors reserved for this purpose and adds seven additional information channels Figure 28 represents the channel assignments for the standard 1 Information Distributor Data in the AC is available at the ID of the computer interface as static levels pulses from the DS can strobe t
76. ontrol flip flops to initial conditions when the START key on the PDP 7 operator console is operated Run Output Signal The 1 output of the RUN flip flop is supplied to external equipment through the interface circuits This RUN 1 signal is at 3v when the computer is performing instructions and is at ground potential when the program is halted Magnetic tape and DECtape equipment use this signal to stop transport motion when the PDP 7 halts preventing the tape from running off the end of the reel Slow Cycle Request Input Signal The device selector supplies the SLOW CYCLE REQUEST ground level signal to request that all IOT in structions which address a specific device be executed in a computer slow cycle This signal is added at the time a slow I O device is added to the computer system IOT instructions for the device are de coded in W103 Device Selector module The ground level output at terminal BD when the device is selected requests the slow cycle by connection to the input of a Type B171 Diode Gate module This latter module 15 used as a ground level NOR gate for all such request signals and a negative output terminal D of this module 15 applied to the processor timing circuits The Type B171 module which ceives the SLOW CYCLE REQUEST signals from various devices is located at El 4 of the 1 0 package Program Interrupt Request Input Signal The flag of an external device can request a program interrupt When
77. ould be made to terminals E or F L or M Sor T other than shorting them together to obtain 1 output pulses Output i is a DEC standard 2 5v 400 nsec pulse 1 psec if E and are shorted which occurs every time the input signal meets the input requirement The output is negative if the positive terminal is grounded Each output can drive 10 ma of load equivalent to 10 inverter bases These amplifiers should not be used without a terminating resistor typical values are 47 to 150 ohms schematic of the output circuit is shown in Figure 25 OUTPUTS an Figure 25 Pulse Amplifier Output Circuit Type W607 Pulse Amplifier module in the data break facility provides the ADDR ACC DATA and DATA RDY pulses The W607 contains three standardizing pulse amplifiers The output is a standard 70 nsec 2 5v pulse Delay through the pulse amplifier is approximately 20 nsec t occurs at the out put every time the input signal meets the input requirement The output is negative if the positive terminal is grounded Each output can drive 10 ma of load equivalent to 10 inverter bases These amplifiers should not be used without a terminating resistor When driving 1 to 5 ma of load the line may be ter minated by 47 ohms to ground and when driving 6 to 10 ma of load 82 ohms to ground These values are approximate and depend on length of the line The output circuit is similar to that of the Type W640 shown in Fi
78. pe Control continued ACB 00 1 H15D 09 1 2150 01 1 HI5E ACB 10 1 J15E ACB 02 1 HI5H 11 1 JI5H ACB 03 1 H15K ACB 12 1 JI5K ACB 04 1 HI5M ACB 13 1 JI5M ACB 05 1 15 ACB 14 1 J15P ADB 06 1 155 15 1 155 ACB 07 1 H15T ACB 1611 JI5T 08 1 H15V ACB 17 1 JI5V DATA FLG HO9D 7501 J23D BLK FLG 7502 ERR FLG HO9H IOT 7504 H23H OFF END HO9K 7604 H23K MISS IND HO9M RUN 1 B H23M REV STATUS HO9P MBI H23P GO HO9S 550 IOT 7501 235 TRK ERR HO9T 550 IOT 7541 H23T UNABLE HO9V PWR CLR NEG H23V Unspecified Data Break Device MBB 00 1 HO2D MBB 09 1 2020 MBB 01 1 HO2E MBB 10 1 JO2E MBB 02 1 H02H MBB 11 1 J02H MBB 03 1 H02K MBB 12 1 J02K 041 HO2M MBB 13 1 J02M MBB 05 1 HO2P MBB 14 1 J02P MBB 06 1 025 MBB 1511 2025 07 1 HO2T 160 J021 MBB 08 1 MBB 17 1 71 Signal DI 00 DI 01 DI 02 DI 03 DI 04 DI 05 DI 06 DI 07 DI 08 DA 03 DA 04 DA 05 DA 06 DA 07 DA 08 T5 T DATA RQ DATA IN DATA ACC ADDR ACC DATA RD Y DATA SLO RQ TABLE 3 PREWIRED INTERFACE CONNECTIONS continued Terminal Signal Unspecified Data Break Device continued H30D H30E H30H H30M H30P H30S H30T H30V H32D H32E H32H H32K H32M H32P 325 H32T H32V J28D J28E J28H J28K J28M J28P 285 J28T J28V 72 DI 09 DI 10 DI 11 DI 12 DI 13 DI 14 DI 15
79. quest a slow cycle The normal IOT cycle time is 1 75 psec or equal to a normal computer cycle At computer time 5 T5 is produced at time 7 T7 IOP2 is produced and at time 1 T1 of the next cycle is produced Time 1 of the next cycle can be used for since time 1 is normally used only to prepare to read the next instruction into the MB from core memory so the IR and MB still contain the same information The time from the start of to the start of IOP2 is 450 nsec from the start of IOP2 to is 150 nsec f consecutive instructions occur the time from the start of in the first instruction to the start of IOPI of the second instruction is 1 15 usec The slow IOT cycle time produces IOP pulses at the same computer times as during a normal cycle however the delay between timing pulses is adjustable from a 1 psec to 4 usec Under special conditions modifi cations to the delay modules can produce even longer time delays In all cases delays are set to ac commodate the slowest device using the slow cycle feature of the computer this timing exists for all devices requesting a slow cycle complete slow cycle requires a 3 36 psec minimum GENERATOR The logic circuits of the IOP generator are shown in Figure 6 When the instruction register decoder detects an IOT instruction the operation code in bits 5 11105 it generates the signal The sign
80. r Terminal Type Element Number Terminal Type Element Number pue S S n a a LLL A A sn e L em sm em sm w sm oe pep 1p n mw O m sm A e EI COI TABLE 1 INPUT SIGNALS continued Signal Destination in ce Signal Destination in VO Package ce Signal Destination in VO Package Signal Destination in Processor KA77A signal symbol Interface Module Module Logic Drawing Module Module Logic Drawing Connector Terminal Type Element Number Terminal Type Element Number Rr z 2 2 a llaw a lt ae na I T WK O NCEE 14 1 J30P El M B201 16 1 02 1 HJ4JL B210 17 ICO7 1 1 08 1 ICO9 1 1 10 1 IC11 1 1 12 1 IC13 1 1 14 1 IC15 1 1 16 1 IC17 1 TABLE 1 INPUT SIGNALS continued Signal Destination in Package KATIA Destination in Signal Destination in Package KATIA Package Signal Destination in Processor KA77A Syl Interface Module Module Logic Drawing Module Module Logic Drawing Connector Terminal Type Element Number Terminal Type Element Number NUM KUN UE LI MN W SIL gt m lt m m ea so lt m lt gt lt p m CIC oL
81. s 1 for the establishing a check for the last character to be printed initializing a counter to track the number of characters printed etc and then enters the print subroutine to print the first character The basic print subroutine might be similar to the following Octal Mnemonic Remarks 22XXXX LAC I 10 LOAD CHARACTER INTO AC FROM ADDRESS SPECIFIED BY AUTOINDEX REGISTER 10 44XXXX ISZ COUNT COUNT CHARACTERS 741000 SKP NOT LAST CHARACTER 60XXXX JMP END LAST CHARACTER 700406 TLS TRANSFER CHARACTER FROM AC INTO PRINTER BUFFER CLEAR PRINTER FLAG AND INITIATE PRINTING RESTORE L AND OR EPC IF NECESSARY THEN 700042 ION ENABLE INTERRUPT SYSTEM FOR NEXT CHARACTER BREAK 620000 JMP 10 RETURN TO MAIN PROGRAM FROM ADDRESS STORED IN ADDRESS 000000 Exit from this subroutine reestablishes the main program which now continues until interrupted by a pro gram break Having been initiated by the subroutine mechanical printing of the first character continues until complete then raises the print flag The print flag in the 1 state indicates that the teleprinter has printed the last character and is ready to receive another character and requests a program interrupt f the interrupt system is enabled at the end of the current instruction the break state is entered to store the contents of the EPC and PC in address 000000 The next instruction is then taken from address 000001 and program control is transf
82. siderations apply to the modules The R111 Diode Gate sets up in approximately 50 nsec in either direction under normal load conditions The DCD gates set up in 400 nsec from the end of the preceding 100 nsec pulse and the pulse input must return to for 400 nsec before the next pulse is applied Series R pulses are 100 nsec in width measured from the 9096 point of the leading edge to the 1096 point of the trailing edge Fall time is not critical on these pulses provided that the pulse has returned to 3v in time to come up for the next cycle All output signals from the PDP 7 routed through the interface have been provided with adequate buf fering to meet the input requirements of normal I O equipment Whenever it becomes necessary for the user to draw out other signals besides those connected in the standard interface care must be taken that the loads presented to the sources of these signals do not exceed their driving ability When it is evident that the source would be overloaded a suitable driver must be provided between the signal source and the device employing the signal Device Selector The DS generates IOT pulses that control I O equipment and effect information transfers between the computer and peripheral devices The DS contains a section for standard devices program interrupt con trol real time clock interrupt control tape reader tape punch Teletype units and display equipment 73 or
83. three 3 input diode NAND gates for negative signals The TRANSFER DIRECTION signal supplies one input to one of these gates The remaining two inputs are supplied by a negative level and a negative timing pulse produced within the computer The 1 25 ma static load is shared by all inputs at ground 40 5 INTERFACE CONNECTIONS INTERFACE CONNECTIONS AND SIGNAL IDENTIFICATION signals interchanged between the PDP 7 processor and the peripheral equipment pass through the interface section of the I O package in the computer Interface connections are made either by coaxial cable or by ribbon cables terminated in a Type W021 Signal Cable Connector described in detail in the Digital Logic Handbook C 105 The cable connector plugs into the appropriate FLIP CHIP module re ceptacles in rows H and J of bay 3 containing the package Figure 27 shows the relative location and signals assigned to these connectors Some cable connections for the Type 177B EAE option for ex ample are made directly to the processor in bay 2 In general all interface connections to the processor are made through the package except for options that are normally installed at the factory when the system is built In any system bays are numbered left to right as viewed from the front Rows of modules are lettered from top to bottom within one prewired option Module receptacles are numbered from left to right as viewed from the wiring
84. ting capacitor into the circuit to avoid ringing on long lines The driver operates with typical output rise and fall delays 37 of 50 nsec and total transmission time of 800 nsec output rise and 700 nsec for output fall If this ground connection 15 removed the bus driver operates with typical rise and fall times of 25 nsec typical total transition times of 60 nsec for output rise and 65 nsec for output fall The standard DEC level output can drive 20 ma of external load at either ground or 3v Figure 24 is a schematic of the output circuit of the bus driver Figure 23 Inverter Circuit 10V OUTPUTS 680 pF LD 15V Figure 24 Bus Driver Output Circuit Type B684 Bus Driver modules are used by the MB to drive the DATA INFORMATION or MBB lines in data break output transfers The 8684 contains two noninverting bus drivers and 3v supply Each bus driver provides standard DEC output levels capable of driving 40 ma Delay through the driver 15 approx imately 30 The output circuit is similar to that of the Type R650 shown in Figure 24 PULSE AMPLIFIERS Type W640 Pulse Amplifier modules in the DS reproduce or buffer command pulses The W640 contains three standardizing pulse amplifiers Delay through the pulse amplifier is approximately 40 nsec Output pulses can be either 1 if E and are connected together or 400 wide E and open No 38 connections sh

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