SIS3811 VME Multiscaler User Manual - Hades Wiki
Contents
1. Open Open GND Open Open GND Open Open Open GND Open GND Z S 8 Oo Q o O Q O O Zza OO s OOo re Bs Q Z J ie 5 ad 5 Open Open Open GND Open e 5 alalo s o 3 c 1 Q Q O Q Q O Z d Open GND GND Open GND GND 5 Q J o s elelgigigls s Iolo ls S olos d ojo Pin Pin Pin Pin Pin seegeke 8 Iols lols o occae CIS 2 8 ols a Z s PIQIO o o o e 5 oo ooo OS IZ lols SION No N c 21 O pen Ea jen EN ERN a E UNI lis Gre popu HERI EN 9 GN 10 GND Pett pop it as Cae 4 dst 106 ay 08 eee 20 IE SEN Open Open GND GND 5 5 open GND Open N N N N Q o aa e 5 DIDO JOJO Jo F O 5 SIZ 5 22 ala Z olo olek s Iolo o 3 GND Open Open Open Open Open Open Open Open Open GND GND en Oo o 5 o 5 QIQJO O Z Z S 919 9 Scc 1 5 oobis 8 Iols lols o Q 18 13 Additional Information on VME The VME bus has become a popular platform for many realtime applications over the last decade Information on VME can be obtained in printed form via the web or from newsgroups Among the sources are the VMEbus handbook http www vita com the home page of the VME international trade2. e mea 25 disable external clear external LNE Cd a H3 disable 23 Mis text pases OOOO O O OOOO 1l dearinptmodebit i 0 9 disable FIFO test mode S 8 switchoffuserLED 0 7 reserved S switch off user LED 4 X enable25 MHztestpulses O k set input mode bit 1 3 set input mode bit 0 enable FIFO test mode o0 switch on user LED denotes the default power up or key reset state Page 17of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 6 3 Module Identification and IRQ control register 0x4 This register has two basic functions The first is to give information on the active firmware design This function is implemented via the read only upper 20 bits of the register Bits 16 3 hold the four digits of the SIS module number like 3801 or 3600 e g bits 12 15 hold the version number The version number allows a distinction between different implementations of the same module number the SIS3801 for example has the 24 bit mode with user bits and the straight 32 bit mode as versions Module Identification Bit Module Identification Bit15 30 read only Module Identification Bit 14 Module Id Digit 3 29 readonly Module Identification Bit 13 28 readonly Module Identification Bit12 27 l Readonly Module Identification Bit I1 Identification Bit 11 26 readonly Module Identifi
3. j4 Ox10000008 Trailermodule2 8 Bytes 5 Ox18000000 Headermodule3 Geo 3 6 0x18000008 Trailer module 3 8 Bytes _ sf 0x20000008 Trailermodule4 8 Bytes Page 42 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 18 8 Operation notes Due to the flexibility of the SIS3811 firmware designs the unit covers a broad range of counter based data acquisition applications In some cases the user may find possible uses of the board we did not see yet during the design test and documentation phase on the other hand we found possibilities which may not be obvious to the first time user Two of them are described below 18 8 1 Time Monitoring If you use the external external prescaled or channel 1 prescaled LNE source you can monitor the time between LNE signals with the 25 MHz channel 1 reference pulser This allows you to determine the speed of a stepper motor if the motor clock is used as prescaled LNE signal to give an example 18 8 2 Retrieve FLASHPROM contents If you are not sure what firmware designs are actually burned into your FLASHPROM you can find out by making use of the jumper array J500 FLASPROM file selection and the module identification and IRQ register Set your unit to file O all jumpers set power up the crate and read the module identification register Proceed with selecting file 1 lowest jumper open and continue until the unit does not boot module stuck in LED selftest
4. As we do not make FLASHPROMS with gaps in between the boot files you will have a complete listing of all files on the FLASHPROM at this point Page 43of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 18 9 Cascaded FIFOs The SIS3811 board can be stuffed with one or four synchronous FIFO chips the standard unit comes with one 64K FIFO chip as default The FIFO flags are handled by a PLD programmable logic device if four FIFO chips are installed The meaning of the almost empty half full and almost full flag is redefined in this case as these flags are derived from the status of all four FIFO chips as data are written to and read from the FIFO chips in a ring buffer fashion Find below two table with the FIFO conditions for the V2 and the V3 FIFO GAL FIFO Hete Asinine in 2508 sis in 256K case empty empty Bed almost empty 25 to 5096 full 0 lt 64K 128 16 bit words 0 or 1 between 64K 128 16 bit words and 128 K 256 16 bit words 1 2128 K 256 16 bit words half full dontcare almost full 50 to 75 full 0 128K 256 16 bit words 0 or 1 between 128K 256 16 bit words and 192 K 384 16 bit words 1 2192 K 384 16 bit words setiffull O set if full doms flag Meaning in Seapine n 2568 ce case empty empty M almost empty 25 to 50 full 0 lt 64K 128 16 bit words 0 or 1 between 64K 128 16 bit words and 128 K
5. 24 control hot swap 30 46 input 38 http input modes 28 Iwww vita com 47 Cooling 30 Input Configuration 25 copy disable register 8 input mode 17 copy in progress 8 input modes 28 Count Enable 9 input test mode 17 31 custom firmware 6 Insertion Removal 30 CVI 33 interrupt call back routines 33 acknowledge cycle 18 project file 33 condition 22 D08 O 18 control 18 D16 23 level 22 D32 23 42 logic 22 data format vector 18 22 CBLT 24 VME 22 Data Format 23 interrupt level 18 DC DC converter 38 interrupter type 18 driver IRQ source 17 500 27 J A11 14 38 high impedance 27 J101 J108 38 drivers 33 J115 38 dwell time 6 8 J500 10 38 39 Page 48 of 49 SIS Documentation J520 10 38 39 jumper firmware selection 11 VME addressing mode 14 Jumper overview 38 Jumper and rotary switch locations 38 key address 15 LED 13 Access 13 Color 13 Power 13 Ready 13 user 10 live insertion 30 46 LNE 31 inhibit 28 source 31 LNE Load Next Event 7 module number 18 monostable 13 NIM 26 Operating conditions 30 Operation notes 43 OR VP6 33 output 27 Outputs 28 PCB 6 Pentium II 33 Pin Assignments 36 PLD 44 polling 9 Power Consumption 30 Priority Input 31 Readout Considerations 9 Reference pulser channel 1 31 register CBLT setup 15 20 41 42 control 15 17 22 control and status register 15 copy disable 19 IRQ and version 22 module identification and IRQ control 15 18 43 SIS3811 SIS GmbH 4 Multiscaler Counter VME statu
6. Cooling e este oe RATED EL MEN UU D EAM DELL et 30 15 3 Insertion Removal teta a tesa WO Ug ite e REV Ote b tle te te ed 30 16 d l 3l Page 3of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 16 1 LED Gelftest sone ertet itte e Re nee etd eon oe hee 16 2 Internal pulser tests ee SOR pec Bhasin ben tb rt LEA RR RE SEAE este saunas 16 2 1 ngle Pulse COS sascha as Bisa Me Lakes evel IHRER Moe C DE 16 2 25 MHz Pulser 163 Reference pulser channel 1 164 Signal Input Priority sts Em v 165 LNE source PEotity 35 e oe sak e EDEN RE ne Det con E AEEA E aas 16 67 EIEQT6SU a Gere a eo pet ie ce o RU ER o nete d OO e qutt dee eme 17 Software Support 17 1 Contents of the included Floppy 18 Append Ra m 18 1 Address Modifier Overview ds 18 2 Front Panel Layout ss 183 Flat cable Input Output Pin Assignments 18 3 1 18 3 2 18 4 List of Jumpers 18 5 Jumper and rotary switch locations 18 5 1 Addressing mode and base address selection serene tenerte 18 5 2 J500 Bootfile Selection and J520 SYSRESET Behaviour n of 18 6 Board Layout ea eee ee Ie AEN ate Siete te ce aah EN A Mee a ed 1
7. association VITA and comp bus arch vmebus In addition you will find useful links on many high energy physics labs like CERN or FNAL SIS GmbH f VME Page 47of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 19 Index 10 MHz 31 ECL 25 36 24 bit mode 19 23 EN_A16 10 14 38 25 MHz Pulser 31 EN_A24 10 14 38 25 MHz test pulses 17 EN_A32 10 14 38 32 bit mode 19 23 Factory Default Settings 10 A_11 10 38 FIFO 6 14 21 A16 11 almost full 16 A24 11 cascaded 44 A32 11 full 16 address GAL 16 44 geographical 42 half full 16 Address Map 15 half full flag 9 Address Modifier Overview 34 test mode 16 address modifiers 34 firmware 5 Address Space 14 firmware design 10 11 18 addressing Firmware Selection 11 A16 A24 A32 38 Bootfile 12 addressing mode 34 Examples 12 Addressing mode 38 FLASHPROM 5 6 11 addressing modes 14 contents 43 Adressing 10 FLASHPROM Versions 45 bank 23 Floppy 33 bank number 23 FNAL 47 Base Address 11 14 38 Front Panel BERR 41 LED 13 BLT 34 Front Panel Layout 35 BLT32 42 GAO0 47 board layout 40 GAI 47 Boot File Selection 38 GA2 47 Bootfile Selection 39 GA3 47 Broadcast Addressing 21 GA4 47 bus error 41 GAL 16 44 byte count 24 GAP 47 CBLT 10 11 14 15 20 24 34 geographical address 24 data format 24 pins 47 setup example 42 Geographical Address 47 CERN 47 geographical addressing 46 channel 23 Getting Started 10 CIP 8 16 28 header 42 Connector Specification 27 header word
8. into account 14 3 User Bits The status of the user bits Version 2 4 and 6 is latched with the leading edge of the external next pulse A setup time of greater equal 10 ns and a hold time of 25 ns is required i e the signal should have a length of greater 35 ns and has to be valid 10 ns before the leading edge of the next clock pulse arrives Page 29of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 15 Operating conditions 15 1 Power Consumption Voltage requirement Although the SIS3811 is prepared for a number of VIPA features it was decided to use an ob board DC DC converter to generate the 5 V which are needed for driver and receiver chips to allow for the use of the module in all 6U VME environments The power consumption is counting rate dependent it varies from the idle value of 5 V 3 3 A to 5 V 4 5 A with all channels counting at 200 MHz i e the power consumption is lt 23 W 15 2 Cooling Forced air flow is required for the operation of the SIS3811 board 15 3 Insertion Removal Please note that the VME standard does not support live insertion hot swap Hence crate power has to be turned off for installation and removal of SIS3811 scalers The leading pins on the SIS3811 VME64x VME connectors and connected on board circuitry are designed for hot swap in conjunction with a VME64x backplane a VME64x backplane can be recognised by the 5 row VME connectors while the standard VME backplane has
9. is a combination of firmware and hardware description This manual describes the firmware versions 7 and 8 of the SIS3811 multiscaler which were developed for the HADES detector at the GSI Darmstadt for the combined efficient level 1 trigger readout of the multiscaler a SIS3600 latch and other front end modules All cards of the family are equipped with the 5 row VME64x VME connectors a side cover and EMC front panel as well as the VIPA LED set For users with VME64xP subracks VIPA extractor handles can be installed The base board is prepared for VIPA style addressing the current first version of the SIS3801 firmware does not feature VIPA modes yet however As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info struck de the revision dates are online under http www struck de manuals htm A list of available firmware designs can be retrieved from http www struck de sis3638firm htm Page 5of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 2 Technical Properties Features The SIS3811 is rather a firmware design in combination with given board stuffing options than a name for the board this is the reason why the modules are named SIS360x 38xx on the front panel and the distinction of the units is made by the module identifier register The fir
10. 256 16 bit words 1 2128 K 256 16 bit words half full almost full 50 to 75 full 0 lt 64K 128 16 bit words 0 or 1 between 64K 128 16 bit words and 128 K 256 16 bit words 1 2128 K 256 16 bit words set if full Example If the FIFO almost empty flag is cleared the user can read a minimum of 64K 128 16 bit words from the FIFO in a block transfer and has the guarantee that he can store an additional28 K 256 words before running into overflow Note The difference between the V2 and the V3 FIFO GAL lies in the condition of the almost full flag As the almost empty condition itself can not be used to generate a VME interrupt the almost empty condition is used for the almost full flag in the V3 GAL what gives you much more time to handle the interrupt and the FIFO data It will depend on the application whether the V2 or V3 design is appropriate Page 44 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 18 10 FLASHPROM Versions A list of available FLASHPROMs can be obtained from http www struck de sis3638firm htm Please note that a special hardware configuration may be necessary for the firmware design of interest the SIS3811 design requires the installation of a FIFO e g The table on the web is of the format shown below SIS36 38xx FLASHPROM table The table below is an excerpt form the full table which is on the web only Boot File s SIS3800 201098 O
11. 3 Reference pulser channel 1 The reference pulser for channel 1 can be seen rather as a monitoring feature than a test feature It sets the counting rate of channel 1 to 25 MHz note that a simultaneous front panel signal on channel 1 is ignored 16 4 Signal Input Priority If the user happens to enable more than one input option enable test mode enable reference pulser scaler enable at the same time the priority is as show in the table below Reference Pulser channel 1 only Front Panel Inputs Example If test mode and reference pulser are enabled at the same time channel one will count test pulses i e will count synchronous with the test pulser 16 5 LNE source Priority A software LNE pulse is always passed to the logic If the user happens to enable the internal 10 MHz pulser and the front panel LNE signal at the same time the actual used LNE source depends on the status of the prescaler enable Page 31of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME If the LNE prescaler is enabled and both the internal and external LNE sources are disabled the channel 1 input signal will be used as LNE source Channel 1 will not count external pulses in this case but can be used to count pulses from the 25 MHz reference pulser Find below a summary of the possible combinations 0 0 0 soft onl 0 chanel 0 S 1 0 J sSsofonly 0 P1 1 1 J intprscled ext ext prescaled ex
12. 5 Control 5 8 The schematics of the NIM input circuitry is shown below GND DEL Y Ref 0 35 V Page 26 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 10 3 TTL The TTL input level option is possible with LEMO and flat cable connectors 10 3 1 TTL LEMO The low active TTL LEMO input circuitry is sketched below A high active version can be implemented by replacing the 74F245 with a 74F640 m ulis 10 3 2 TTL Flat Cable In the flat cable TTL version the positive right hand side of the connector is tied to ground du s 11 TTL output configuration Standard TTL units drive high impedance signals i e 24 mA current a 50 Q driver piggy driving 48 mA pack is available on request It plugs into the socket U170 instead of the standard driver chip 12 Connector Specification The four different types of front panel and VME connectors used on the SIS360x and SIS38xx boards are 160 pin zabcd VME P1 P2 Harting 02 01 160 2101 20 pin header Control flat cable versions DIN41651 20 Pin AMP e g 34 pin header Inputs flat cable versions DIN41651 34 Pin AMP e g LEMO Control and Input LEMO versions LEMO ERN 00 250 CTL Page 27of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 13 Control Input Modes The assignment of the control inputs can be controlled via the input mode bits in the control register Control Input Modes Input assignment Mo
13. 8 7 GCBIZT readout s ete e Bu tea ie RUEDA ens bote eto end 18 7 1 CBLT Setup example 18 8 Operation notes 18 8 1 Time Monitoring 18 8 2 Retrieve FLASHPROM contents 18 9 Cascaded FIFOS 18 10 FLASHPROM Versions 18 11 Row d and z Pin Assignments 18 12 Geographical Address Pin Assignments 18 13 Additional Information on VME Page 4 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 1 Introduction The SIS3811 is one of the multi channel scaler multiscaler boards of the SIS360x 38xx VMEboard family The SIS3811 is a single width 4 TE 6U double euro form factor card The design is derived from the SIS3801 multiscaler design CBLT readout was implemented at the cost of removing functions like the LNE prescaler This document was written with the focus on the user of the unit who wants to integrate the board into a data acquisition system and interested parties who consider the module for future use in their setup and would like to get an overview on the designs capabilities The SIS360x 38xx card is a flexible concept to implement a variety of latch and counter firmware designs The flexibility is based on two to six Xilinx FPGAs in conjunction with a FLASHPROM from which the firmware files are loaded into the FPGAs Depending on the stuffing options of the printed circuit board the user has the possibility to cover several purposes with the same card hence the manual
14. Front view INx ECL High active INx ECL Low active OUTx ECL High active OUTx ECL Low active Page 36 of 49 H E Y 4 SIS Gmb F SIS3811 Multiscaler Counter VME SIS Documentation 18 3 2 TTL N M o o e S S ES oO o e o o S S o 2 a 8 S a Z A 4 lt Z 9 i 4 lt Z i Z A Data Connector Channel 1 16 SIGNAL PIN Front view Front view INx TTL Low active 74F245 INx TTL Low active 74F245 Control Connector Input 1 4 Output 5 8 d EA GND GND GND GND GND OUTT OUT6 OUTS O8 N 9T T INS z Z E on E z Z S i Z A Front view 74F245 INx TTL Low active OUTx TTL Low active 74F244 Page 37of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 18 4 List of Jumpers Find below a list of the jumpers and jumper arrays 18 5 Jumper and rotary switch locations 18 5 1 Addressing mode and base address selection The EN A32 EN A24 EN_A16 A 11 and the 5 rotary switches are located int the middle of the upper section of the board close to the DC DC converter the corresponding section of the PCB is shown below ojo 5 pel 93 Sk E o eazjn o o o o o o o o 7 og N ooon S 32U SU_AS2L SH A24U SL A24L SU MS NO a ou o 8 ou o u Ld a Tstn o co o o oo o M oooo o oo o o oo o o o 3 alaa a q J5 olola u200 ORS ns rex ere o
15. RQ and version register The internal VME interrupt flag can be used to check on an IRQ condition without actually making use of interrupts on the bus The VME interrupt level 1 7 is defined by bits 8 through 10 and the VME interrupt vector 0 255 by bits 0 through 7 of the VME IRQ and version register In general an interrupt condition is cleared by disabling the corresponding interrupt clearing the interrupt condition i e clear overflow and enabling the IRQ again Note In most cases your experiment may not require interrupt driven scaler readout but the interrupt capability of the SIS3811 provides a way to overcome the problem of missing front panel inputs on most commercial VME CPUs VME_IRQ_ENABLE VME IRQ Source 1 INTERNAL_VME_IRQ Source 2 Source 3 Page 22 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME 9 Data Format The data format of the actual counter values is described for the two operating modes 24 32 bit and the two possible data word widths D16 D32 in this section 9 1 32 bit Mode Version 7 In these modes the data word contains the straight scaler contents 9 1 1 D16 high Byte irst read Data Bits 31 24 Data Bits 23 16 Data Bits 15 8 Data Bits 7 0 9 1 2 D32 Data Bits 31 24 Data Bits 23 16 Data Bits 15 8 Data Bits 7 0 9 2 24 bit Mode Version 8 In these modes the lower 24 bits hold the scaler value the upper eight data bits contain the latched st
16. SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME SIS3811 VME Multiscaler User Manual SIS GmbH Moorhof 2d 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version 1 00 as of 01 02 01 Page lof 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME Revision Table 02 01 01 Generation from SIS3801 V5 VA manual Page 2 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME Table of contents l InttOduCtioTi ero pt e RO RR tte EEA AE AETAT 2 Technical Properties Features ettet teet eode geld t entre reete ee E RE Fee bl eter eee ue 2 1 hpnulbimic 2 2 Counter Design and Modus Operandi 2 3 Minimum Dwell Time tete eere te EI Re RH Eee pe RR Rehd Ree 2 4 Readout Considerations 2 5 Count Enable Logic 3 Getting Started E Factory Default Settings m A s E 3 1 1 Eun X 3 12 System Reset Behaviour ss e ete E UR ey bbc eei pe Eee ti Pete ee E 11 4 Firmware Selection s bed ues 4 1 locii RE Front Panel E EDS s ee RP TRE ee e ERE DEED A ET HE sevens ro ee et re ues 5 VME addressing e T m s 5 1 Address Spaceu s snot EREMO II eurem dept ets 5 2 B se Address etta te RU m OT SERT EEEE ER ER ares 5 2 1 VME a 5 3 Address Map 6 X Register Description sees T T
17. SIS3800 Version SIS3801 201098 O SIS3800 Version 1 SIS3800 Version 2 SIS3803_280798 O SIS3803 Version SIS3811 310101 0 SIS3811 Version7 SIS3800 Version 2 Page 45of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 18 11 Row d and z Pin Assignments The SIS3801 is prepared for the use with VME64x and VME64xP backplanes Foreseen features include geographical addressing and live insertion hot swap The prepared pins on the d and z rows of the P1 and P2 connectors are listed below Rowz Do GND GND Eg Oooo E N Rowz eae GND Ooo GND p E EDEN Ooo Boa a Ooo GND p GND an p E p i CREME poo a5 GND Oo pd eel GND E GND ed Oooo E Oooo ae GND Oooo el GND GND Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors Page 46 of 49 SIS Documentation SIS3811 Multiscaler Counter 18 12 Geographical Address Pin Assignments The SIS38xx board series is prepared for geographical addressing via the geographical address pins GAO GA1 GA2 GA3 GA4 and GAP The address pins are left open or tied to ground by the backplane as listed in the following table Slot GAP Number Pin 1 WN Open Open Open Open Open Open Open Open Open Open Open Open GND
18. T Sh 6 1 Status Register 0x0 eost RR RARO OPERE RUN GRUPO PDA Ue THURIS 6 2 Control Register 0X0 54 eiie tete tee ree ertet eie tede tete ER UE as doubts edle Geese eas 6 3 Module Identification and IRQ control register 0x4 T ue 6 4 Copy disable register OX C euet Mee ee tete o tee tie tse ete e ERR 6 5 CBLT setup register 0x80 R W 6 6 FIFO 0x100 OxIFC 7 Broadcast Addressing 8 VME Interrupts ds m p ui DQ Data POrmiatis ee 9 1 9 1 1 ues a i 3 9 1 2 DBD otto e ROS east UR nt RR bU b Id pedea e RR 9 2 9 2 1 d E i 3n 9 2 2 1932 db o OUO RUD UR IR DEOR ane 9 3 CBLT data structure 9 3 1 Header Word 9 3 2 Trailer Word 10 Input Configuration 10 1 ECL 10 2 NIM 103 TTL m its in 3 103 ETEZEEMTQS ttt e ee tse a MU Ur eti oie e Oaerto ce IRR 27 10 3 2 SELLS Bat Cable ttr tH PERRO RC REDE PEOR I TRATADO 27 11 TTL output configuration Ves ahs ies E EEEE 27 12 Connector Specification e m s n 27 13 Control Input Modes 22 wets ee ES IUS MN SSS AMO Iu 14 Signal Specification ee wees ies ed HT Control Signals eee on RR UE ER o pate a EO E te ERE I MEDI 14 3 User Bits 15 Operating conditions s 15 1 Power Consumption Voltage requirement es 30 15 2
19. Via the test enable toggle bits in the control register the input of the counter is switched to test pulses or front panel signals Enable Scaler Scaler Channel N gt Count Enabl Control Input Disab 25 MHz reference channel 1 only Input N 25 MHz test pulse Single Test Pulse External Test Pulse Page 9of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 3 Getting Started The minimum setup to operate the SIS3811 requires the following steps e Check the proper firmware design is selected should be design zero i e all jumpers of jumper array J500 set Select the VME base address for the desired addressing mode Select the VME SYSRESET behaviour via J520 turn the VME crate power off install the scaler in the VME crate connect your signals to the counter turn crate power back on e issue a key reset by writing to 0x60 issue FIFO clear by writing to 0x20 define CBLT address and parameters via register 0x80 enable next logic by writing to 0x28 issue first next clock pulse to start counting by soft or hardware after one or more subsequent next clock pulses data can be read from the FIFO from the addresses 0x100 through Ox1FC Note Issuing a FIFO clear is essential on units with 256 K FIFO to synchronise the cascaded FIFO chips A good way of checking first time communication with the SIS3811 consists of switching on the user LED by a write to the control register at offset address OxO w
20. annels A mixed LMEO control flat cable counter input version is available also The units are 4 TE one VME slot wide the front panel is of EMC shielding type VIPA extractor handles are available on request or can be retrofitted by the user if he wants to change to a VIPA crate at a later point in time In the drawing below you can find the flat cable left hand side the LEMO control flat cable input middle and Lemo front panel layouts Note Only the aluminium portion without the extractor handle mounting fixtures is shown SS GmbH CONTROL 1 E a 8 1 6 5 a 4 3 2 1 Page 35of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 18 3 Flat cable Input Output Pin Assignments 18 3 1 ECL Data Connector Channel 1 16 Data Connector Channel 17 32 PIN SIGNAL SIGNAL PIN PIN PIN cg cry E i e IN14 I INI3 IN29 I IN11 IN27 IN27 IN IN6 IN22 10 IN5 ms 9 10 IN21 IN2I 9 8 M4 M4 8 IN20 IN20 6 TNSS m 5 6 N9 N9 5 Ni IND 1 IN17 Front view Front view INx ECL High active INx ECL High active INx ECL Low active INx ECL Low active Control Connector Input 1 4 Output 5 8 ar m mN IN SIGNAL SIGNAL UT8 UT8 UT7 OUT7 UT6 OUT6 OUTS5 Q Z 5 gla Z 5 oO O OO UT Q Z FI Z J 4 IN4 3 IN3 2 IN2 4 1 INI
21. ar and the Scaler enable LED are monostable i e the duration of the on phase is stretched for better visibility the other LEDs reflect the current status An LED test cycle is performed upon power up refer to the chapter 16 1 Page 13of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 5 VME addressing 5 1 Address Space As bit 11 is the lowest settable bit on the 360x 38xx board an address space of 2 Kbytes Offset plus 0x000 to Ox7ff is occupied by the module 5 2 Base Address 5 2 1 VME The VME addressing mode A16 A24 A32 is selected via the jumpers EN Al6 EN_A24 and EN_A32 The mode is selected by closing the corresponding jumper it is possible to enable two or all three addressing modes simultaneously The base address is set via the five rotary switches SW_A32U SW_A32L SW_A24U SW A2AL and SW_A16 and the jumper J All The table below lists the switches and jumpers and their corresponding address bits Switch Jumper Affected Bits SW A32U 31 28 SW AL 27 24 In the table below you can see which jumpers and switches are used for address decoding in the three different addressing modes fields marked with an x are used _ SW_A32U SW_A32L SW_A24U SW_A24L SW_A16 JAN x x xe dL ee op eme 2 Oox k k e T oe er ee es hs eee ees aes a ee oe Note J_A11 closed represents a 0 J_A11 open a one The module will also participate in CBLT transfers with the programmed CBLT addre
22. atus of the two user bits and the bank and channel information The bit names and their function are listed in the table below Bit User Bit 1 User Bit 0 Bank number 0 1 Channel number Bit 4 Channel number Bit 3 Channel number Bit 2 Channel number Bit 1 Channel number Bit 0 9 2 1 D16 PhghBye tow Byte O irstread Ul UO B C4 C3 C2 CI C0 Data Bits 23 16 Data Bits 15 8 Data Bits 7 0 9 2 2 D32 U1 UO B C4 C3 C2 C1 CO Data Bits 23 16 Data Bits 15 8 DataBits 7 0 Page 23of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 9 3 CBLT data structure The SIS3811 will pass FIFO data to VME as participant of a CBLT until the FIFO empty condition will be reached The user has to avoid a dead lock condition by ensuring that the scaler is not generating data at a higher speed than the VME master can digest The module will pass header and trailer word if the FIFO is empty at start of readout The data format of the SIS3811 and the structure of the header and trailer words is given below Header Word First data word Last data word Trailer word 9 3 1 Header Word The header word holds the geographical address to identify the data source 31 27 Geographical address as defined by bits 15 11 of register 0x80 26 0 0 S 9 3 2 Trailer Word The trailer word holds the byte count and the geographical address 31 27 Geographical address as defi
23. cation Bit 10 Module Id Digit 2 25 readonly Module Identification Bit9 ei pooni Module Montes BiS O Module Identification Bit 7 32 read only Module oR Module Id Digit 1 21 readonly Module Identification BitS 20 readonly Module Identification Bit4 Module Identification BES Identification Bit 3 rig readonly Module Identification Bit2 Module Id Digit 0 17 readonly Module Identification Bit 5 readony VersionBit3 ooo 14 Do sss i E read write is D o readisrie VMEIRO Level Bi I 8 read write VMEIRQLevelBitO U O IRQ Vector Bit t placed on D7 during VME IRQ ACK cycle 6 read write IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 5 read write IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle 4 read wrte IRQ Vector Bit 4 placed on D4 during VME IRQ ACK cycle 3 ___fread wvrite 00 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle IRQ Vector Bit 2 placed on D2 during VME IRQ ACK cycle HL essei IRQ Vector Bit 1 placed on D1 during VME IRQ ACK cycle IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle The second function of the register is interrupt control The interrupter type of the SIS3811 is D08 O Via bits 0 7 of the module identifier and interrupt control register you can define the interrupt
24. de 0 bit120 bit020 input gt external next pulse input 2 gt external user bit 1 input 3 gt external user bit 2 input 4 gt inhibit LNE Mode 1 bit120 bit0z1 input gt external next pulse input 2 external user bit 1 input 3 disable counting input 4 inhibit LNE Mode 2 bit1 1 bit0 0 input gt external next pulse input 2 gt external user bit 1 input 3 gt external user bit 2 input 4 gt disable counting Mode 3 bitl 1 bit0z1 input 4 gt external test 13 1 Outputs Four ouput signals are defined on the SIS3811 board They are copy in progress CIP FIFO empty FIFO half full and FIFO full ERROR Their assignments to the control lines are listed in the table below Control Signal FIFO empty 6 FIFO half full 7 FIFO full is Page 28 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME 14 Signal Specification 14 1 Control Signals The width of the clear and external next pulse has to be greater or equal 10 ns an external inhibit disable counting has to be present for the period you desire to disable counting An internal delay of some 15 ns has to be taken into account for all external signals 14 2 Inputs The SIS3811 is specified for counting rates of 200 MHz for ECL and NIM signals and 100 MHz for the TTL case Thus the minimum high and low level duration is 2 5 ns 5 ns respective Signal deterioration over long cables has to be taken
25. e FIFO size can be increased up to 256K as a stuffing option One as to keep in mind that two FIFO words are needed to hold one 32 bit scaler value i e a 64K FIFO can hold 32K scaler words or 1K events time slices with all 32 channels enabled The packing of the FIFO data into VME D32 words is handled without user intervention upon VME read cycles from the FIFO In high data rate applications the readout scheme will make use of the FIFO half full flag or FIFO almost full flag in the 256K FIFO case via a VME interrupt or polling in most cases as a minimum known number of 32K 32K 64 respective longwords can be read out being blocked into smaller chunks by VME with a block transfer Example Assume 32 channels are read out with a dwell time of 10 us i e at a rate of 100 KHz with a 64K FIFO unit The data rate is 32 channels x 4 bytes x 100 KHz corresponding to some 12 MB s The FIFO half full interrupt or flag will be asserted for the first time after 0 5 ms of data acquisition the VME master has to digest 64Kbytes within less than 0 5 ms including IRQ handling or polling to prevent the FIFO from overflow Note No new data can be acquired before a FIFO reset if the FIFO full condition has occurred i e the FIFO full condition is considered an error condition which should not occur in standard operation 2 5 Count Enable Logic A channel acquires input or test counts if the count enable and the global count enable conditions are true
26. e requirements of the selected firmware design a base board without FIFO can not be operated as multi channel scaler e g A total of 8 boot files from the FLASHPROM can be selected via the three bits of the jumper array The array is located towards the rear of the card between the VME P1 and P2 connectors The lowest bit sits towards the bottom of the card a closed jumper represents a zero an open jumper a one Page lof 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 41 Examples The figures below show jumper array 500 with the soldering side of the board facing the user and the VME connectors pointing to the right hand side Bootfile 0 selected With all jumpers closed boot file 0 is selected Bootfile 3 selected With the lowest two jumpers open bit 0 and bit 1 are set to 1 and hence boot file 3 is selected Page 12 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME Front Panel LEDs The SIS3811 has 8 front panel LEDs to visualise part of the units status Three LEDs according to the VME64xP standard Power Access and Ready plus 5 additional LEDs VME user LED Clear Copy in Progress Scaler enable and VIPA user LED ee ed a a O O o a a Signaln confiauredllonc Signals bank clear Signals copy in progress S sar Enable aem igus one or more nia chame The LED locations are shown in the portion of the front panel drawing below The VME Access the Cle
27. ed into the FIFO all other channels are disabled The minimum dwell time is in the order of 750 ns 4 channels x 120 ns 260 ns overhead the exact value can be measured on the CIP output for this example Page 19of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 6 5 CBLT setup register 0x80 R W This register defines whether the SIS3811 will participate in a CBLT The configuration of this register and the registers of other participating modules is essential for proper CBLT behaviour Bit 31 CBLT address bit 31 21 BLT address bit 27 CBLT address bit 26 24 CBLTaddssbit2d O O O OOOO A ee 23 0 E Aa To C e PEREENMUNENEEEMDBMJSZSZ ZSA 9S 19 0 8 10 oo INE aa EC Geographical address bit 3 113 Geographical address bit 2 12 Geographical address bit O Z OZ Geogra pica address bit 1 First to be set to 1 on the first module in the CBLT chain Last to be set to 1 on the last module in the CBLT chain lO enable CBLT to be set to 1 on all modules in the CBLT chain The function meaning of the CBLT and the geographical address is illustrated in section 18 7 1 Page 20 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME 6 6 FIFO 0x100 0x1FC The FIFO can be accessed from addresses 0x100 through Ox1FC to facilitate the readout with different types of CPUs For masters with block transfer capability without address increment its most convenient to read all data from add
28. eded for the copy progress can be measured on the copy in progress CIP output the output is active for the duration of the process the signal can also be of help to control or synchronise external components As the maximum number of counts the unit can acquire within microsecond time frames is in the order of a couple of hundred one may consider to go for a 16 bit counter design if shorter dwell times are envisaged the readout time is reduced to 50 ns 16 bit word in such a design the FIFO is of 18 bit synchronous type Page 8 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 2 4 Readout Considerations One of the major advantages of a FIFO based counter multiscaler is the decoupling of the time slice bank switching and the actual VME readout of the data Depending on the application the FIFO may be used to buffer one or two reads only before a DSP processes the data on the fly in this case the FIFO is used to establish readout pipelining in other cases the maximum possible FIFO size is of interest to store a complete set of data points for a pulsed or non continuous measurement Continuous multiscaling can be established as long as the VME master can cope with the amount of data generated by the scaler i e the FIFO is never allowed to run into the FIFO full condition The 64K default FIFO size of the SIS3811 V2 4K on V1 boards is considered to be a save value for most applications for more demanding applications th
29. et the same CBLT address in the case of the SIS3811 the CBLT address is defined by the upper 8 bits of the CBLT setup register The module closest to the CPU has to be defined as First CBLT module the module at the end of the chain is defined as Last CBLT module All modules have to have their CBLT enable bit set the modules must occupy a contiguous set of VME slots as shown in the sketch below The token is passed from the previous module to the next module via the IRQ daisy chain lines as soon as all data have been read The last module in the chain terminates the transfer with a VME bus error BERR VME Crate Schematic CBLT setup Page 41of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 18 7 1 CBLT Setup example Assume 4 SIS3811 as shown in the crate above are supposed to participate in a CBLT The modules are set to D32 addressing and VME base address configuration as shown in the table below 0x45 is used as CBLT address and the CBLT setup registers of the three modules are configured as shown in the list A BLT32 read from VME address 0x45000000 will result in a CBLT over the 4 modules with the selected geographical addresses showing up in the header and trailer words If the modules contain no scaler data the resulting VME data will look like shown below 0x08000000 Header module 1 Geo 1 2 Ox08000008 Trailer module 1 8 Bytes 3 0x10000000 Headermodule2 Geo 2
30. he front panel is available as flat cable ECL and TTL or LEMO NIM and TTL version The board layout is illustrated with the block diagram below Page 6 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME Level Adaption Driver Receiver XILINX __ Level Adaption Driver Receiver 7 VME Interface XILINX Control m Level Adaption Driver Receiver w Counter Level Adaption L XILINX Driver Receiver Level Adaption Driver Receiver a File Level Adaption Selection Driver Receiver Level Adaption Driver Receiver a Level Adaption Driver Receiver Level Adaption Driver Receiver EH Level Adaption XILINX Driver Receiver SIS3811 Block Diagram 22 Counter Design and Modus Operandi The counters are implemented in XILINX FPGAs One of the counter FPGAs holds 8 32 bit or 24 bit deep counter channels Two counter banks are implemented the actual multiscaling mechanism is implemented as bank switching between the two counter banks and copying the data of the inactive bank to the FIFO Bank switching can be initiated via an external pulse or a VME command A sketch of the bank mechanism can be found below In nuclear physics on refers to the time slice length i e the period during which counts are acquired into the same bank as dwell time In many cases the dwell time will be constant but the user is free to use varying time intervals as long as the minimum time be
31. int prescaled 16 6 FIFO Test FIFO tests via the VME bus are helpful to debug the FIFO on the SIS38xx in case of spurious data and to debug an overall VME system with driver problems on the CPU side or flaky VME termination e g In FIFO test mode the user can write defined data into the units FIFO via the VME bus and to compare them wit the read back result FIFO test mode is enabled by setting bit one of the control register and disabled by setting bit 9 of the control register With FIFO test mode enabled data can be written to the FIFO at the address offset 0x100 through Ox 1FC Writing to the location with FIFO mode Page 32 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 17 Software Support VME multiscaler boards are tested at SIS with an OR VP6 VME CPU Pentium II based under Windows 95 and a National Instruments CVI user interface The actual VME C code makes use of the OR Windows 95 DLL which has straightforward to read and understand routines like VMEA24StdWriteWord a32address KEY RESET 0x0 Key Reset rdata VMEA24StdReadWord a32address STAT REG In most cases the user setup will be using different hardware a full fleshed real time operating system like VxWorks and a different user interface We still believe that it is helpful to have a look at the code which is used to test the units and to take it as an example for the implementation of the actual scaler reado
32. ith data word Ox1 the LED can be switched back off by writing 0x100 to the control register 3 1 Factory Default Settings 3 1 1 Adressing SIS3811 boards are shipped with the EN_A32 the EN A24 and the EN AI16 jumpers installed and the rotary switches set to Lsuma s oy qp cw p oe gr tg ora 9 Jumper A 11 is open bit 11 set Page 10 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME Hence the unit will respond to the following base addresses 0x38383800 0x383800 0x3800 In addition the module will respond to CBLT access under the programmed register 0x80 CBLT address in BLT32 if chained block transfer is enabled the user has to make sure proper overall configuration of the modules which are supposed to participate in the chained block transfer Firmware Design File 0 SIS3811 Version 7 of the FLASHPROM is selected all jumpers of jumper array J500 set 3 1 2 System Reset Behaviour J520 is set ie the SIS3811 is reset upon VME reset 4 Firmware Selection The FLASH PROM of a SIS360x 38xx board can contain several boot files A list of available FLASHPROM versions can be found on our web site http www struck de in the manuals page If your FLASHPROM has more than one firmware design you can select the desired firmware via the firmware selection jumper array J500 You have to make sure that the input output configuration and FIFO configuration of your board are in compliance with th
33. mware makes use of part of the possibilities of the SIS360x 38xx PCB if the SIS3801 or other firmware designs of the family come close to what you need but something is missing a custom firmware design may be an option to consider Find below a list of key features of the SIS3811 e 32 channels e 200 MHz counting rate ECL and NIM 100 MHz for TTL 24 32 bit channel depth NIM TTL ECL versions flat cable TTL ECL and LEMO TTL NIM versions 64K FIFO 256 K available on request e A16 A24 A32 D16 D32 BLT32 CBLT32 e Base address settable via 5 rotary switches A32 A12 and one jumper A11 e VME interrupt capability e VIPA geographical addressing prepared e VIPA LED set 3 8 us minimum dwell time with all channels active 2 external user bits in 24 bit mode Reference Pulser capability Up to eight firmware files e single supply 5 V 2 1 Board Layout Xilinx FPGAs are the working horses of the SIS360x 38xx board series The counter prescaler latch logic is implemented in one to four chips each chip handles eight front end channels The VME interface and the input and output control logic reside in two Xilinx chips also The actual firmware is loaded into the FPGAs upon power up from a FLASHPROM under jumper control The user can select among up to eight different boot files by the means of a 3 bit jumper array The counter inputs the control inputs and the outputs can be factory configured for ECL NIM and TTL levels T
34. ned by bits 15 11 of register 0x80 Co 26 18 Page 24 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME 10 Input Configuration SIS36 38xx boards are available for NIM TTL and ECL input levels and in LEMO and flat cable versions The boards are factory configured for the specified input level and connector type input termination is installed 10 1 ECL The 100 Q input termination can be removed in groups of four channels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel RNIO i 4 RNIUI2 RN20 58 J RN2122 RN30 RN31 32 RN40 13 16 RN41 41 RNSO 17 20 RNS1 52 RN6O 21 24 RN61 62 1 K Networks 1 4 5 8 RN80 29 32 RN81 82 RN110 Control 1 4 RN111 RN112 RN120 Control 5 8 RNI2I RNI22 RN70 25 28 RN71 72 The schematics of the ECL input circuitry is shown below SIL RN 1 X1 SIL RN 1 X0 SIL RN 1 X2 Page 25of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 10 2 NIM The 50 Q input termination can be removed in groups of four channels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel 13 16 U75 Pins 10 to 6 25 28 U115 Pins 1 to
35. ns as the control register Bit Status VME IRQ source 3 FIFOalmost full Status enable external clear Status enable external next Status Enable next logic 14 eae ee ee ag almost fullO inverted almost empty flag on 256K units with V3 FIFO GAL FIFO flag half full lo FIFO flag almost empty inverted on 256K units IS A FIFO flag empt 7 0 Status 25 MHz test pulses Status input mode bit 1 Status input mode bit 0 2 Status FIFO test mode o Status user LED The reading of the status register after power up or key reset is 0x300 with 64K FIFO installed and 0x100 with 256 K FIFO installed see default settings of control register Page 16 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME 6 2 Control Register 0x0 The control register is in charge of the control of most of the basic properties of the SIS3811 board in write access It is implemented via a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which has a different location within the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time On read access the same register represents the status register disable IRQ source 3 disable IRQ source 2 disable IRQ source 1 disable IRQ source 0 clear software disable counting bit
36. ress 0x100 For masters with block transfer address auto increment it is straightforward to set up repeated block reads with a length of 256 Bytes the maximum VME block transfer size from address 0x100 and the autoincrement uses the addresses 0x100 through Ox1FC for the transfer If FIFO test mode is enabled data can be written to the FIFOs addresses 7 Broadcast Addressing Broadcast addressing options which are part of SIS3801 firmware versions 1 4 are not available in SIS3811 firmware version 7 and 8 due to restrictions of the Xilinx control chip Page 21of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 8 VME Interrupts Four VME interrupt sources are implemented in the SIS3811 firmware design e start of CIP e FIFO half full e FIFO almost full e FIFO full error condition The interrupter is of type D8 O If the unit is equipped with four FIFO chips the FIFO half full flag can not be used to generate a useful interrupt condition In this case the FIFO almost full flag is set upon the FIFO almost empty condition being cleared i e at 25 50 filling level what gives the user reasonable safety regarding the readout time The interrupt logic is shown below For VME interrupt generation the corresponding interrupt source has to be enabled by setting the respective bit in the VME control register disabling is done with the sources J K bit Interrupt generation has to be enabled by setting bit 11 in the I
37. s 15 rotary switch 38 Signal Specification 29 Control 29 Inputs 29 Single Pulse 31 Software Support 33 source LNE 31 Status Register 16 SW_A16 10 14 SW_A24L 10 14 SW_A24U 10 14 SW_A32L 10 14 SW_A32U 10 14 SYSRESET Behaviour 39 System Reset 11 Technical Properties Features 6 Time Monitoring 43 trailer 42 trailer word 24 TTL 27 37 user bit 23 29 version number 18 VIPA 30 addressing 5 extractor handles 5 LED set 5 VITA 47 VME 30 47 addressing 14 addressing mode 14 Base Address 14 CPU 33 interrupt 9 22 SYSRESET 39 SYSRESET Behaviour 38 VME64x 46 connector 5 VME64xP 5 46 Voltage requirement 30 VxWorks 33 Windows 95 33 Xilinx 7 8 Page 49of 49
38. se LCA 3190 PQl60 oe LLE DE io tides tm ie Page 38 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 18 5 2 J500 Bootfile Selection and J520 SYSRESET Behaviour The jumper array J500 is located between the P1 and the P2 connector An open position in J500 defines a one see also chapter 3 the lowest bit is next to the P2 connector J520 is located to the left of J500 and closer to the DC DC converter With jumper J520 closed the SIS3811 executes a key reset upon the VME SYSRESET signal The section of the board with the jumper array and the SYSRESET jumper is shown below D51232 bal 000 0 of vcoo0270 U285 Bero pg 520 Ig b o o joj cece 3520 El g b U180 us00 LCA 3190 PQ160 car U261 w Page 39of 49 t g g 8 70O AS A s Ug S S SIS Documentation 18 6 Board Layout H j cesi m E EI mom mei 7 ol AD TIN LI bes g P 3 _4 Te Page 40 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 18 7 CBLT readout CBLT is a method to speed up the readout of small amounts of data from a larger number of slaves in conjunction with long setup time masters As header and trailer words are added in CBLT this readout approach is less efficient than low setup overhead list sequencer readout of masters like the SIS3100 VME sequencer Modules which are supposed to participate in a CBLT have to g
39. ss in a proper overall CBLT setup The only resource which is accessible in CBLT is the FIFO Page 14 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME 5 3 Address Map The SIS360x 38xx boards are operated via VME registers VME key addresses and the FIFO where installed The following table gives an overview on all SIS3811 addresses and their offset from the base address a closer description of the registers and their function is given in the following subsections 0x000 R W D16 D32 Control and Status register 0x004 R W DIGD32 Module Identification and IRQ control register foxooc W DI9D22 Cop disable register 0x010 fW _ D16 D32_ Write to FIFO in FIFO test mode _ 0x020 KA D16 D32 clear FIFO logic and counters xv XA w DIGD32 VME next sleek 0x060 D16 D32 _ reset register global reset 0x068 D16 D32 Test pulse generate a single pulse 0x080 R W DI6 D32 CBLT setup register 0x100 R W D32 read FIFO Ox1FC BLT32 Note D08 is not supported by the SIS38xx boards The shorthand KA stands for key address Write access with arbitrary data to a key address initiates the specified function Page 15of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 6 Register Description 6 1 Status Register 0x0 The status register reflects the current settings of most of the SIS3811 parameters in read access in write access it functio
40. three row connectors only Page 30 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 16 Test The SIS380x scaler series provides the user with a number of test features which allow for debugging of the unit as well as for overall system setups 16 1 LED selftest During power up self test and LCA configuration all LEDs except the Ready R LED are on After the initialisation phase is completed all LEDs except the Ready R LED and the Power P have to go off Differing behaviour indicates either a problem with the download of the firmware boot file or one or more LCA and or the download logic 16 2 Internal pulser tests 16 2 1 Single Pulse A single pulse into all channels can be generated with a write to the key address 0x68 if test mode is enabled via the control register In conjunction with the count enable register more complex count patterns like increment patterns e g can be generated before readout 16 2 2 25 MHz Pulser Simultaneous pulsing at 25 MHz into all channels can be used to test the complete readout chain and internal counter logic of the SIS3811 The feature is activated by enabling input test mode and 25 MHz test pulses via the corresponding bits in the control register The 25 MHz test pulser gives easy access to your VME CPUs readout timing By making subsequent reads to the same counter and multiplying the difference in counts with 40 ns you can measure the single word access time 16
41. tween two next event pulses is smaller than the minimum dwell time with the given number of active channels An approach to measure the length of the time slices is the readout of a fixed frequency clock on one of the counter channels the accuracy of the measurement is defined by the frequency stability of the clock and the interval length Firmware versions 5 and 6 are furnished with an internal 10 MHz pulser which can be routed via an LNE Load Next Event prescaler alternatively to the LNE front panel This allows standalone readout with fixed time intervals as well as readout on the Nth occurrence of an external signal like a clock tick from a shaft encoder or stepper motor Page 7of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME LNE eemeos 9 13 Counter Xilinx 8 Scaler Inputs LNE e Eo m Counter Xilinx 8 Scaler Inputs 23 Minimum Dwell Time The minimum dwell time on the SIS3811 isdefined by the time which is needed to copy the data from the idle scaler bank to the FIFO The time required to copy one 32 bit data word from the counter Xilinx chips to the FIFO is 120 ns The overhead is 260 ns thus the minimum dwell time is some 4 0 us with all 32 scaler channels active The firmware designs 3 4 5 and 6 have a channel count dependent dwell time Via the copy disable register the number of active channels can be reduced if lower dwell times are of interest The time which is ne
42. ut application A floppy with our test software is enclosed with SIS3811 shipments Depending on the user feedback and co operation we expect that we will have drivers or at least example routines for the commonly used VME CPU operating systems at hand in the mid term 17 1 Contents of the included Floppy The Floppy contains a readme txt file with the most up to date information the CVI project file and all home made files from the project The important part of the code for the implementation of your own program is sitting in the CVI call back routines Page 33of 49 SIS Documentation SIS3811 SIS GmbH 4 Multiscaler Counter VME 18 Appendix 18 1 Address Modifier Overview Find below the table of address modifiers which can be used with the SIS360x 38xx with the corresponding addressing mode enabled AM code Mode AMcode Mode 0 0 0 0x09 A32 non privileged data access Future option CBLT Page 34 of 49 SIS Documentation SIS3811 SIS GmbH I Multiscaler Counter VME 18 2 Front Panel Layout The front panel of the SIS3811 is equipped with 8 LEDs 8 control in and outputs and 32 counter inputs On flat cable units ECL and TTL the control connector is a 20 pin header flat cable connector and the channel inputs are fed via two 34 pin headers On LEMO NIM and TTL units the control in and outputs are grouped to one 8 channel block and the counter inputs are grouped into 2 blocks of 16 ch
43. vector which is placed on the VME bus during the interrupt acknowledge cycle Bits 8 through 10 define the VME interrupt level bit 11 is used to enable bit set to 1 or disable bit set to 0 interrupting Page 18 of 49 SIS Documentation SIS3811 SIS GmbH Multiscaler Counter VME Module identification and version example The register for a SIS3801 in straight 32 bit mode version 1 reads 0x38011nnn for a SIS3801 in 24 bit mode version 2 it reads 0x38012nnn the status of the lower 3 nibbles is denoted with n in the example 6 4 Copy disable register 0xC The copy disable register implementation of firmware versions 5 and 6 is derived from version 3 and i e the dwell time depends on the number of active channels In these firmware implementations the first set bit counting from zero will define the end of the copy process loop and the duration of the copy in progress and hence the minimum dwell time depends on the number of enabled channels Due to space limitations in the control Xilinx chip bits 31 through 25 can not be set i e have the same status as bit 24 Hence you can operate the multiscaler with 1 to 24 or all 32 channels enabled The copy time was measured to be some 120 ns channel an overall overhead in the order of 260 ns This allows you to make measurements with very short dwell times with a limited number of channels Example If 0x10 is written to the copy disable register the data of channels 1 through 4 are copi
Download Pdf Manuals
Related Search