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Express-HL User's Manual

1. ND 23 L2 CN OQ WA N m s lt gt All tolerances 0 05 Other tolerances 0 2 Express IB 3 Pinouts and Signal Descriptions The following information is a summary of the most important information regarding pinout and signal description in the official PICMG COM 0 Rev 2 0 soon 2 1 The pinout is noted here to emphazise issues that have not been followed in the past The following might have small inacuaracies so in case of doubt the offical design guide of PICMG should be consulted 3 1 CD Pin Definitions The Express HL is a Type 6 module supporting USB3 0 and DDI channels on the CD connector All pin in the specification are described also those not supported on the Express HL Those not supported on the Express HL module are crossed out Row A Row B Row C Row D 1 GND FIXED GND FIXED C1 GND FIXED D1 GND FIXED mm BENE GBEO B3 LPC A4 GBEO_LINKioo lPC ADO 04 6 DA GBEO LINK1000 amp 85 c GND X 05 GND GBEO MD2 86 66 USB 55 7 USB_SSTXt eseo ime GBEO MDI B9 DRQi4 GBEO B10 LPC D10 evene en
2. 10 212 Op rating 10 2 15 5 8 0 AG B 10 218 42 15 52 11 2 17 Mechanical 12 3 Pinouts and Signal Descriptions 13 3 1 AB7 CD Pin DefiniflonS u u u uuu u uuu EE 13 3 2 Signal Description 8 16 3 3 AB Signal 17 22 PICO URINE m 17 202 Analog S u E S 17 3 3 3 RUP a 17 MEC cie TETTE S ms 18 D CEP our Aa 19 3 3 6 SEK ____ 20 22 PS e Emm 20 3 3 8 LPE DUS 21 3 3 9 __________ _ _____ __ 21 Express IB A 3 3 10 SPI BIOS OnLy 22 3 3 11 PSC Li CUS uu E 22 3 3 12 NIB UE 22 3 3 13 EAE EE 23 3 3 14 General Purpose DO SPIO wa 23 3 3 15 Power And System 23 3 3 16 Power and Ground Aa 24 3 4 25 3 4 1 121585 OI c
3. ml 00 00 e I B107 B108 B109 C109 GND FIXED B110 GND FIXED C110 GND FIXED D110 GND FIXED D107 A10 D108 N Express IB 0 OD 3 3V 5V 3 3V O 5V 10 3 3V 10 5V 3 3Vsb P REF PDS PU PD ADLINK 3 2 Signal Description Terminology The following terms are used in the COM Express AB CD Signal Descriptions below Input to the Module Output from the Module Bi directional input output signal Open drain output Input 3 3V tolerant Input 5V tolerant Output 3 3V signal level Output 5V signal level Bi directional signal 3 3V tolerant Bi directional signal 5V tolerant Input 3 3V tolerant active in standby state Power Input Output Reference voltage output that may be sourced from a module power plane Pull down strap This is an output pin on the module that is either tied to GND or not connected The signal is used to indicate the PICMG module type to the Carrier Board ADLINK implemented pull up resistor on module ADLINK implemented pull down resistor on module Express IB 3 3 AB Signal Descriptions 3 3 1 Audio Signals Signal Pin Description PU PD Comment 0 Reset output to CODEC active low 3 3VSB Sample synchronization signal to the CODEC s O 3 3V BEEN Serial data clock generated by the external 10 3 3V CODEC s AC
4. Serial ATA channel 0 Receive Input differential pair SATA1 TX O SATA SATA1 TX Serial ATA channel 1 Transmit Output differential pair UJ UJ N O SATA1_RX SATA SATA1_RX Serial ATA channel 1 Receive Input differential pair UJ UJ SATA2 TX SATA2 TX Serial ATA channel 2 Transmit Output differential pair gt gt N 2 2 Serial ATA channel 2 Receive Input differential pair gt gt Ro AC coupled on Module AC coupled on Module AC coupled on Module _ SATA SATA3_TX Serial ATA channel 3 Transmit Output differential pair SATA3_RX SATA SATA3_RX B25 B26 Serial ATA channel 3 Receive Input differential pair STA 28 ATA parallel and serial or SAS activity 3 3V indicator active low Express IB ADLINK 3 3 6 Express Signal Pin Description PU PD Comment PCIE_TX0 68 Express channel 0 Transmit Output differential O PCIE AC coupled on Module 69 pair PCIE_RX0 B68 Express channel 0 Receive Input differential PCIE AC coupled off Module B69 pair PCIE_TX1 64 Express channel 1 Transmit Output differential O AC coupled on Module PCIE TX1 A65 pair PCIE 1 B64 PCI Express channel 1 Receive Input differen
5. 11 Diez T EHE HHH x pma Express IB ADLINK TECHNOLOGY INC gt COM Express Module Pin Description Interface Signal Remark Pin Interface Signal Remark VCC_SPI SPI Power Input from flash tool to 21 BMC Program TXD6 Program module HW need add MOS FET to interface interface switch SPI power for SPI ROM continued G RXD6 SPI_BIOS FUMDO _ 50 SPI_BIOS _CS1 SPI_BIOS _MISO RESET_IN DATA SPI_BIOS _MOSI SPI_BIOS _CLK CLK OCDOA Include a jumper to connect OCDOA 1 pull up to 3 3V_BMC LPC Bus 3V3_LPC System power 3 3V provide from COM module OCDOB Include a jumper to connect OCDOA 1 pull up to 3 3V_BMC GND BIOS_DIS 0 RST co Test points PWRBTN Z SYS_RESET SUS_S3 ME 32 LPC AD3 susse _ suss LPC_AD1 always power 3 3V provide from 36 BMC Debug POSTWDT_DIS Connect to Jumper for COM module signals Debug LPC_ADO SEL_BIOS Connect to Jumper for Debug 3 3V_BM always power 3 3V provide from 38 BIOS_MODE Connect to Jumper for C COM module Debug 3 3V_BM always power 3 3V provide from 39 BMC_STATUS COM module oo Note the pin description on the debug module is the inverse of that on the COM Express module N N BDO N
6. 25 3 4 2 TESS aus ______ 25 313 26 3 4 4 DDI to DP HDMI SDVO Mapping creen retention 28 3 45 PCIExpress Graphics x16 PEG Lu ___________ 29 3 4 6 Module Type Definition 30 347 30 4 Connector Pinouts Module 31 4 1 40 pin Multipurpose 32 4 2 sO og 8 ee ee eee 34 4 3 35 4 4 F ONC i u 36 4 5 BIOS Setup Defaults RESET SWIECDY IA 36 4 6 PCI Express Configuration Switch 36 4 7 PCle x16 to two x8 Adapter Card 37 5 Smart Embedded Management Agent SEMA 38 5 1 B ard Specie SEMA FUNCUONS Llu URS 38 VOEO ee 38 5 1 2 uyu anasu 39 5 13 BS qfi rn 39 ME 21080 0 uuu uu unun T 39 5 1 5 u au MAA 40 System RA 5 2255 52 54 42155524 2 553 22445552564 32 23212 552554 423444 2532 2 41 6 1
7. fen ono greoi ano reo __ A12 GBEO 2 08 D2 B13 62 D13 Ai4 CTREF GND GOD _______ 505 538 B15 c15 DDH PAIR pis CTRLCLK SATA0 B16 TX 16 DDI1_PAIR6 D16 CTRLDATA AUX RSVD SUS 54 RsvD D18 Ai9 SATAO RX PCIE RX6 019 PCIE SATAO RX PCIE RX 20 PCIE TX6 GND FIXED B21 GND FIXED C21 GND FIXED ____ 021 GND FIXED SATA2 TX B22 TX C22 000 Eo 505 S5 c24 024 RSVD ______ 7 2000 A26 2 DDH 026 BATLOW WDT DDI1_PAIRO C28 RSVD 028 RSVD 29 B29 C29 DDH PAIRb ____ 029 A30 B30 AC HDA SDINO C30 DDI1_PAIR5 030 DDH PAIRI A31 GND FIXED B31 GND FIXED C31 GND FIXED D31 GND FIXED A32 B32 _ E C32 DDI2 CTRLCLK D32 DDIT_PAIR2 A33 A34 A35 B33 occ C33 DD CTRLDATA AUX 033 DDI1_PAIR2 TO DDC AUX SEL AUX SEL le 5 RSVD 635 Express IB ADLINK Rea Rar __ RowG Nam
8. 3 4 CD Signal Descriptions 3 4 1 USB 3 0 extension Signal Pin Description Comment USB_SSRX0 C3 Additional Receive signal differential pairs for the PCIE USB_SSRX0 C4 SuperSpeed USB data path on USBO USB_SSTX0 D3 Additional Transmit signal differential pairs for the O PCIE AC coupled on Module USB_SSTX0 D4 SuperSpeed USB data path on 5 0 USB SSRX1 C6 Additional Receive signal differential pairs for the PCIE USB SSRX1 C7 SuperSpeed USB data path on USB1 USB_SSTX1 D6 Additional Transmit signal differential pairs for the O PCIE AC coupled on Module USB_SSTX1 D7 SuperSpeed USB data path on USB1 USB_SSRX2 C9 Additional Receive signal differential pairs for the PCIE USB SSRX2 C10 SuperSpeed USB data path on USB2 USB SSTX2 D9 Additional Transmit signal differential pairs for the O PCIE AC coupled on Module USB SSTX2 D10 SuperSpeed USB data path on USB2 USB SSRX3 C12 Additional Receive signal differential pairs for the PCIE USB SSRX3 C13 SuperSpeed USB data path on USB3 USB SSTX3 D12 Additional Transmit signal differential pairs for the O PCIE AC coupled on Module USB SSTX3 D13 SuperSpeed USB data path on USB3 3 4 2 Express 1 Signal Pin Description PU PD Comment PCIE_TX6 D19 Express channel 6 Transmit Output O PCIE AC coupled on Module PCIE_TX6 D20 differential pair PCIE_RX6 C19 Express channel 6 Receive Input PCIE AC coupled off Module PCIE_RX6 C20 d
9. Me mO m 41 6 2 Direct Memory Access Channels 41 6 3 OP IVA __________ 42 6 4 Interrupt Request IRQ 44 6 5 Space 46 6 6 PCI Interrupt Routing Map 47 Express IB ADLINK TECHNOLOGY INC Safety Instructiolis 48 Getting Service MEET 49 Express IB 1 Introduction The Express HL is a COM Express 0 R2 1 6 module supporting the 64 bit 4th Generation Intel Core 17 15 3 processor with CPU memory controller and graphics processor on the same chip Based on the latest Mobile Intel QM87 Express chipset the Express HL is specifically designed for customers who need high level processing and graphics performance in a long product life solution The Express HL features the Intel Core 17 15 13 processor supporting Intel Hyper Threading Technology up to 4 cores 8 threads and DDR3 dual channel memory at 1333 1600 MHz to provide excellent overall performance Intel Flexible Display Interface and Direct Media Interface provide high speed connectivity to the Intel QM77 Express chipset Integrated Intel Generation 7 5 includes features such as OpenGL 3 1 DirectX11 Intel amp Clear Video
10. 2 C61 PEG RX3 61 TX3 62 PCIE 2 2 PCIE 2 62 062 PEG TX3 A63 GPH As 063 RSVD A64 PCIE TXi B64 PCIERX1 C64 RSVD 064 RSVD Om _ WAKEO C66 PEG RX 066 PEG TX4 lepe NSE _ PE me pes lesno s PCIE Txo 69 PCIE Rxo 69 PEG 5 069 TX D cm comme pm TIUS AT2 B72 PEG TX6 B73 GND A74 875 B76 B77 RSVD 7 B78 B79 _ 80 GND FIXED 80 GND FIXED 680 GND FIXED GND FIXED GND FIXED gt gt o gt gt Express IB ADLINIC Row Row Row Row D Name Pin Name B81 TPM_PP D83 RSVD B34 VCC_5V_SBY B85 vcc sv sev B86 Bss PEG RX114 088 PEG 11 aso pcico ck_REF vca Rep A90 GND FIXED B90 POWER VGA GRN PEG TX124 a92 sPi_miso VGA BLU VGA HSYNC SPI CLK VGA VSYNC PEG 13 95 VGA I2C CK C95 PEG TX13 _ GND SPI 58 RSVD 22747 B98 PEG_TX14 SERO RX B99 GND FIXED B100 GND FIXED SER1 TX FAN PWMOUT PEG TX15 SER1_RX FAN_TACHIN LID SLEEP B94 L
11. COMI Express Express HL User s Manual Manual Revision 0 10 Preliminary Revision Date August 28 2013 Part Number 50 1J046 1000 ADLINK TECHNOLOGY INC ADLINK Revision History Revision Description Date LN Preliminary release 2013 08 28 Express IB Preface Copyright 2013 ADLINK Technology Inc This document contains proprietary information protected by copyright All rights are reserved No part of this manual may be reproduced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Disclaimer The information in this document is subject to change without prior notice in order to improve reliability design and function and does not represent a commitment on the part of the manufacturer In no event will the manufacturer be liable for direct indirect special incidental or consequential damages arising out of the use or inability to use the product or documentation even if advised of the possibility of such damages Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union s Restriction of Hazardous Substances RoHS directive and Waste Electrical and Electronic Equipment WEEE directive Environmental protection is a top priority for ADLINK We have enforced measures to ensure tha
12. DP2_LANE3 DP2_HPD DP2 AUX DP2 AUX DP3 LANEO DP3 LANEO DP3_LANE1 DP3_LANE1 DP3_LANE2 DP3_LANE2 DP3_LANE3 DP3_LANE3 DP3_HPD DP3 AUX DP3 AUX TMDS1 DATA2 TMDS1 DATA2 TMDS1_DATA1 TMDS1_DATA 1 TMDS1 DATAO TMDS1 DATAO TMDS1_CLK TMDS1_CLK HDMI1_HPD HMDI1_CTRLCLK HMDI1_CTRLDATA TMDS2_DATA2 TMDS2_DATA2 TMDS2_DATA1 TMDS2_DATA 1 TMDS2 DATAO TMDS2 DATAO TMDS2_CLK TMDS2_CLK HDMI2_HPD HDMI2_CTRLCLK HDMI2 CTRLDATA TMDS3 DATA2 TMDS3 DATA2 TMDS3_DATA1 TMDS3 DATA1 TMDS3 DATAO TMDS3 DATAO TMDS3 CLK TMDS3 CLK HDMI3_CTRLCLK HDMI3_CTRLDATA Express IB 3 4 5 PCI Express Graphics x16 Signal Description PU PD Comment PEG 0 Express Graphics transmit differential pairs AC coupled on Module PEG PEG 1 PEG 1 PEG RX2 PEG RX2 PEG RX3 PEG RX3 PEG 4 PEG RX4 PEG RX5 PEG RX5 PEG RX6 PEG RX6 PEG RXT7 PEG 7 PEG RX8 PEG RX8 PEG 9 PEG RX9 PEG 10 PEG RX10 PEG RX11 PEG RX11 PEG 12 PEG RX12 PEG 13 PEG RX13 PEG 14 PEG 14 PEG 15 PEG RX15 PEG 0 Express Graphics receive differential pairs AC coupled off Module PEG PEG 1 PEG TX1 PEG TX2 PEG TX2 PEG TX3 PEG TX3 PEG 44 PEG TX4 PEG 5 PEG TX5 PEG TX6 PEG TX6 PEG 7 PEG TXT PEG TX8 PEG 8 PEG 9 PEG TX9
13. C1 A Co DO N oo LPC_FRA 1 1 111 Program interface co RO N BO O gt A e a gt PC Express IB ADLINK 4 2 Status LEDs To facilitate easier maintenance status LED s are mounted on the board gt LED Descriptions Name Color Connection Function LED1 Blue BMC output Power Sequence Status Code BMC Power Changes RESET see 5 1 4 Exception Codes below LED2 Green Power Source 3Vcc S0 LED ON 53 54 55 LED OFF ECO mode LED OFF BMC output Module power up WD LED LED OFF Watchdog counting WD LED LED OFF and same signal as WDT watchdog timed out WD LED LED ON B27 on BtB connector _ Watchdog RESET WD LED LED ON Rebooted after WD RESET WD LED LED ON Rebooted after PWRBTN WD LED LED ON Rebooted after RESET BTN WD LED LED OFF Note only a RESET not initiated by the BMC can clear the WD LED user action Express IB 4 3 Debug header The debug port is a connection into target system environment that provides access to JTAG run control system control and observation resources The XDP target system connector is a Samtec 60 pin BSH 030 01 series connector Specific plating types locking clips and alignment pins versions of this connector can be obtained from
14. HDA_RST SYNC HDA_SYNC AC_BITCLK A30 A29 A32 33 AC SDOUT HDA SDOUT A Serial TDM data output to the CODEC 3 3V B28 Serial TDM data inputs from up to 3 CODECs 10 3 3VSB B30 3 3 2 Analog VGA _SDIN 2 0 HDA SDIN 2 0 Signal Pin Description PU PD Comment VGA_RED B89 Red for monitor O Analog Analog DAC output designed to drive a 37 5 Ohm equivalent load VGA_GRN Green for monitor O Analog If VGA is used than signal should Analog DAC output designed to drive a be pulled to GND by 1500 on the 37 5 Ohm equivalent load carrier If VGA is used than signal should be pulled to GND by 1500 on the carrier VGA_BLU Blue for monitor O Analog If VGA is used than signal should Analog DAC output designed to drive a 37 5 Ohm equivalent load be pulled to GND by 150Q on the carrier Horizontal sync output to VGA monitor 3 3V VGA_VSYNC B Vertical sync output to VGA monitor O 3 3V VGA 12 CK B95 DDC clock line port dedicated to identify OD 3 3V PU 2k2 3 3V VGA monitor capabilities VGA_I2C_DAT B96 DDC data line OD 3 3V PU 2k2 3 3V VGA_HSYNC B93 94 3 3 3 LVDS Pin Description PU PD Comment LVDS_A0 LVDS Channel A differential pairs OLVDS LVDS_AO LVDS_A1 LVDS A1 LVDS A2 LVDS A2 LVDS A3 LVDS A3 LVDS A 81 LVDS Channel A differential clock OLVDS LVDS A CK A82 LVDS_BO LVDS Channel B differential pairs
15. PEG 104 PEG TX10 PEG_TX11 PEG_TX11 1 12 PEG_TX12 PEG_TX13 PEG_TX13 PEG_TX14 PEG_TX14 Express IB ADLINK Description PU PD Comment PEG_TX15 D101 AC coupled off Module _ 15 0102 PEG_LANE_RV D54 PCI Express Graphics lane reversal input strap 1 05V Pull low on the Carrier board to reverse lane order 3 4 6 Module Type Definition Description Comment The TYPE pins indicate to the Carrier Board the Pin out Type that is implemented on the module The pins are tied on the module to either ground GND are no TYPE2 connects NC For Pinout 1 these pins are don t care X TYPE2 TYPE1 TYPEO X X Pinout Type 1 NC NC Pinout Type 2 NC GND Pinout Type 3 no IDE GND NC Pinout Type 4 no PCI GND GND Pinout Type 5 no IDE no NC NC Pinout Type 6 IDE no The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off e g deactivates the ATX_ON signal for an ATX power supply if an incompatible module pin out type is detected The Carrier Board logic may also implement a fault indicator such as an LED 3 4 7 Power and Ground Signal Description PU PD Comment 104 109 Primary power input 12V nominal All available 12V pins on D104 D109 the connector s shall be used C1 C11 C21 C31 Ground DC power and signal and A
16. 10K 3 3V Carrier shall pull to GND or leave no connect BIOS DIS12 Selection strap to determine the BIOS boot device PU 10K 3 3V Carrier shall pull to GND or leave no connect 3 3 11 Miscellaneous Signal Pin Description PU PD Comment SPKR B32 Output for audio enunciator the speaker in PC AT 3 3V systems WDT B27 Output indicating that a watchdog time out event has 3 3 occurred THRM B35 Input from off module temp sensor indicating an over temp 3 3V situation THERMTRIP A35 Active low output indicating that the CPU has entered 3 3V thermal shutdown FAN_PWMOUT B101 Fan speed control Uses the Pulse Width Modulation OD 3 3V PWM technique to control the fan s RPM FAN_TACHIN11 B102 Fan tachometer input for a fan with a two pulse output OD 3 3V PU 10k 3 3V 11 Trusted Platform Module TPM Physical Presence 3 3V PD 3 3V If TPM not installed on Active high TPM chip has an internal pull down This module than remove PD signal is used to indicate Physical Presence to the TPM 3 3V 3 3 12 SMBus Signal Pin Description PU PD Comment SMB_CK System Management Bus bidirectional clock line Power I O OD 3 3VSB PU 2k2 3 3VSB sourced through 5V standby rail and main power rails SMB_DAT B14 System Management Bus bidirectional data line Power 10 OD 3 3VSB PU 2 2 3 3VSB sourced through 5V standby rail and main power rails SMB_ALERT B15 System M
17. Edge Level Trigger register CF8 CFB configuration address register 32 bit I O only 1800 PM ACPI Base Address for SB 1860 Alias for ICH TCO base address w Express IB ADLINK 6 4 Interrupt Request IRQ Lines PIC Mode Typical Intterupt Resource Connected to Pin Available w ho Serial Port 1 PCI marca ra w Secondary IDE controller IRQ15 SERIRQ PIRQ Note 1 Note 1 These IRQs can be used for devices when onboard device is disabled APIC Mode Typical Intterupt Resource Connected to Pin Available u x ms s 9 EI mu w C w RN iM Serial Port 3 COM3 IRQ10 SERIRQ PIRQ Serial Port 4 IRQ11 SERIRQ Note 1 PS 2 Mouse IRQ12 via SERIRQ PIRQ Note 1 Express IB IRQ Typical Intterupt Resource Connected to Pin Available Primary IDE controller IRQ14 via SERIRQ PIRQ Secondary IDE controller IRQ15 via SERIRQ PIRQ Intel HDA PCIE Port 0 1 2 3 4 5 6 Conterller Note 1 2 P E G Root G D Controller PCIE Port 0 1 2 3 4 5 6 P E G Root Port PCIE Port 0 1 2 3 4 5 6 P E G Root Port SMBus Controller EHC Controller 2 Gbe Contr
18. LPC bus Signal Pin Description PU PD Comment LPC AD 0 3 B4 B7 LPC multiplexed address command and data bus 10 3 3V LT FRAMEZ 83 LPC frame indicates the start of an LPC cycle 3 3V LPC_DRQO serial DMA request 3 3V LPC_DRQ1 LPC_SERIRQ A50 LPC serial interrupt VO OD 3 3V PU 8k2 3 3V EL clock output 33MHz nominal 0 3 3V 3 3 9 USB Signal Pin Description PU PD Comment USB0 A46 USB differential data pairs for Port 0 10 3 3VSB USB 1 1 2 0 compliant USBO A45 USB1 B46 USB differential data pairs for Port 1 3 3VSB USB 1 1 2 0 compliant USB1 B45 0582 A43 USB differential data pairs for Port 1 3 3VSB USB 1 1 2 0 compliant USB2 A42 USB3 B43 USB differential data pairs for Port 2 10 3 3VSB USB 1 1 2 0 compliant USB3 B42 USB4 pes USB differential data pairs for Port 3 10 3 3VSB USB4 USB5 B40 USB differential data pairs for Port 4 10 3 3VSB USB5 B39 USB6 A37 USB differential data pairs for Port 5 10 3 3VSB USB6 A36 USB7 B37 USB differential data pairs for Port 6 10 3 3VSB USB7 B37 USB_0_1_OC USB over current sense USB ports 0 and 1 A pull up 3 3VSB for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low PU 10k 3 3VSB Do not pull high on carrier USB 2 3 USB over current sense USB ports 2 and 3 A pull up 3 3VSB PU 1
19. O LVDS Express IB ADLINK Pin Description Comment LVDS 0 LVDS B1 LVDS 1 LVDS B2 LVDS B2 LVDS B3 LVDS B3 m mmm _ LVDS B CK B82 3 3 4 Gigabit Ethernet Gigabit Ethernet Pin Description GBEO_MDI0 Gigabit Ethernet Controller 0 Media Dependent Interface Differential I O Analog Twisted pair GBEO MDIO Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10Mbit sec signals for GBEO modes Some pairs are unused in some modes according to the external GBEO MDI1 following transformer _______1000 __ 100 10 013 01 0 DA TX 0 MDI3 MDI 1 B1 RX RX i MDI 2 B1 _DC MDI 3 B1 00 GBEO CTREF Reference voltage for Carrier Board Ethernet channel 1 and 2 GND min magnetics center tap The reference voltage is determined by the 3 3V max requirements of the Module PHY and may be as low as OV and as high as 3 3V The reference voltage output shall be current limited on the Module In the case in which the reference is shorted to ground the current shall be 250 mA or less Express IB 3 3 5 Serial ATA Signal Pin Description I O PU PD Comment KA 0 KA _ m m SATAO TX O SATA SATAO TX A16 A17 Serial ATA channel 0 Transmit Output differential pair SATAO A SATA _
20. Samtec No specific plating types locking clips or alignment pins are required for the XDP tool Pin XDP Signal Target Signal Device Pin Signal Target Signal Device e ke w w Preot Io processor 1 Processor PROVE O ommo crater 1 Processor 7 GND GND NA 8 GND GND NA 9 0 V pocesor 0 crose Processor s o 14 00 s o ow tm ftw 5 o o X joo J a 10 28 OBSDATADO 00001100 processor 8 vo pocesor o fost mo e a o ajo 99 8 Hooo ____ fi sem m 0 sem mo oven jm s voc oss as 1 vooio our fi 5 0 46 m ____ 4 o ftw S sow sp to e mo To 1 s su _ 78 0 GND ND or XDP_ PRESENT if required Notes 1 These signals are optional can be left as OPEN No Connect if debug by Intel will not b
21. 0k 3 3VSB for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low USB 4 5 OC USB over current sense USB ports 4 and 5 A pull up Do not pull high on carrier 3 3VSB PU 10k 3 3VSB Do not pull high on carrier for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low USB 6 7 USB over current sense USB ports 6 and 7 A pull up 3 3VSB PU 10k 3 3VSB for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low Do not pull high on carrier Express IB ADLINK TECHNOLOGY INC 3 3 10 SPI BIOS only Signal Pin Description Comment SPI_CS Chip select for Carrier Board SPI BIOS Flash 0 3 3VSB SPL MISO Data in to module from carrier board SPI BIOS flash 3 3VSB SPI MOSI Data out from module to carrier board SPI BIOS flash 3 3VSB 3 SPI Clock from module to carrier board SPI BIOS flash 3 3VSB 1 f f SPI POWER A91 Power supply for Carrier Board SPI sourced from Module 3 3VSB nominally 3 3V The Module shall provide a minimum of 100mA on SPI POWER Carriers shall use less than 100mA of SPI POWER POWER shall only be used to power SPI devices on the Carrier BIOS_DISO Selection Strap to determine the BIOS boot device PU
22. 7 37W 4C GT2 Intel Core 15 4400 2 7 GHz 3 3 GHz Turbo 37W 2C GT2 e Intel amp Core 15 4402 1 6 GHz 2 7 GHz Turbo 25W 2C GT2 Intel Core 13 4100 2 4 GHz no Turbo 3MB 37W 2C GT2 Intel Core 15 4102 1 6 GHz no Turbo 3MB 25W 2C GT2 e Intel Celeron L3 Cache 6MB for i7 4650U 3MB for 15 4400 15 4402 13 4100 and 13 4102 Memory Dual channel non ECC 1600 1333 MHz DDR3L memory up to 32GB in dual SODIMM socket Chipset Mobile Intel QM87 Express Chipset BIOS AMI EFI with CMOS backup in 8MB SPI BIOS with Intel AMT 9 0 support WV 2 Expansion Busses PCI Express x16 Gen3 or Express 2 x8 or 1 x8 with 2 x4 6 PCI Express x1 AB Lanes 0 1 2 3 4 5 1 PCI Express x1 CD Lane 6 LPC bus SMBus system user Y 2 3 SEMA Board Controller gt ADLINK Smart Embedded Management Agent SEMA gt Supports e Voltage Current monitoring e Power sequence debug support e mode control Logistics and Forensic information e X Flat Panel Control e General Purpose 12 e Failsafe BIOS dual BIOS e Watchdog Timer and Fan Control 2 4 Video ntegrated in Processor Intel amp Generation 7 5 graphics core architecture gt GPU Feature Support independent and simultaneous display combinations of DisplayPort HDMI LVDS monitors e HD content Playback of
23. C signal return path sh E E ES All available GND connector pins shall be used and tied to carrier C100 C103 110 D1 board GND plane 011 021 031 D41 051 060 067 070 076 080 084 087 090 093 096 0100 D103 D110 Express IB ADLINK 4 Connector Pinouts on Module This chapter describes connectors and pinouts LEDs and switches that are used on the module but are not included in the PICMG standard specification gt Connector and LED Locations XDP 60 pin to CPU BIOS Defaults RESET Switch 40 pin Multi Purpose Express IB ADLINIC 4 1 40 pin Multipurpose Connector gt Connector type 59GF Flex 10042867 gt Pin orientation PIN No 1 PIN 0 15 045 3 5 n San 4 95 000 3 dd R Ec a 4 T 1 Fimananinrmraramininiqiwparimininiqp aaa kai hia 1111 LIT 1 kE e i B 55 5 EFFET EC Sm CF R 3 940 8 i gt 20 E E T IE IT TET 5 515 FESETz X oe b PAROK px 7 1002 d par md imp
24. DDI3_DDC_AUX_SEL pulled high VO OD 3 3V HDMI3 CTRLDATA DDI3 DDC AUX SEL C38 Selects the function of DDI3 PD 1M and DDI3 CTRLDATA AUX This pin shall have a 1M pull down to logic ground on the Module If this input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair contains the CRTLCLK and CTRLDATA signals Express IB 3 4 4 Pin DDI to DP HDMI SDVO Mapping ADLINK HDMI DVI D26 D27 D29 D30 D32 D33 D36 037 C25 C26 C29 C30 C15 C16 C24 D15 D16 D34 D39 D40 D42 D43 D46 D47 D49 D50 D44 C32 C33 C34 C39 C40 C42 C43 C46 C47 C49 C50 C44 C36 C37 C38 DDI1 DDI1 PAIRO DDI1_PAIR1 DDI1_PAIR1 DDI1_PAIR2 DDI1_PAIR2 DDI1_PAIR3 DDI1 PAIR3 0012 0012 0012 0012 PAIR1 0012 PAIR2 0012 2 0012 0012 008 008 008 008 PAIR1 008 PAIR2 008 PAIR2 008 008 SDVO1_RED SDVO1_RED SDVO1 GRN SDVO1 GRN SDVO1 SDVO1 BLU SDVO1 SDVO1 CK SDVO1 INT SDVO1 INT SDVO1 TVCLKIN SDVO1 TVCLKIN SDVO1_FLDSTALL SDVO1 FLDSTALL SDVO1 CTRLCLK SDVO1 CTRLDATA DP1 LANEO DP1 LANEO DP1 LANE1 DP1 LANE1 DP1 LANE2 DP1 LANE2 DP1 LANE3 DP1 LANE3 DP1 HPD DP1 AUX DP1 AUX DP2 LANEO DP2 LANEO DP2_LANE1 DP2_LANE1 DP2_LANE2 DP2_LANE2 DP2_LANE3
25. G interface PCle x16 The card reroutes the PCle x16 to two x8 and allows testing of two independent PCle add on cards with x8 x4 x2 x1 width To use the card set SW1 to 2 x8 PCI Express as above PClex16 to two x8 Adapter Card Model 16 028 Part No 91 79301 0010 Express IB ADLINK 5 Smart Embedded Management Agent SEMA The onboard microcontroller BMC implements power sequencing and Smart Embedded Management Agent SEMA functionality The microcontroller communicates via the System Management Bus with the CPU chipset The following functions are implemented Total operating hours counter counts the number of hours the module has been run in minutes On time minutes counter counts the seconds since last system start Temperature monitoring of CPU and board temperature minimum and maximum temperature values of CPU and board are stored in flash Power cycles counter Boot counter counts the number of boot attempts Watchdog Timer Type ll Set Reset Disable Watchdog Timer Features auto reload at power up System Restart Cause Power loss BIOS Fail Watchdog Internal Reset External Reset Fail safe BIOS support In case of a boot failure hardware signals tells external logic to boot from fail safe BIOS Flash area 1kB Flash area for customer data 128 Bytes Protected Flash area Keys IDs etc can be stored in a write and clear protectable region Board Identify Vendor Board Serial n
26. HD Technology Advanced Scheduler 2 0 1 0 XPDM support and DirectX Video Acceleration DXVA support for full AVC VC1 MPEG2 hardware decode Graphics outputs include VGA LVDS and three DDI ports supporting HDMI DVI DisplayPort or SDVO The Express HL is specifically designed for customers with high performance processing graphics requirements who want to outsource the custom core logic of their systems for reduced development time The Express HL has dual stacked SODIMM sockets for up to 32 GB DDR3 memory The Intel amp Mobile QM87 Express chipset integrates VGA and dual channel 18 24 bit LVDS display output In addition to the onboard integrated graphics a multiplexed PCI Express x16 Graphics bus is available for discrete graphics expansion or general purpose x8 or x4 PCI Express connectivity The Express HL features a single onboard Gigabit Ethernet port four USB 3 0 ports and four USB 2 0 ports and 4 SATA 6 Gb s ports Support is provided for SMBus and 12 The module is equipped with AMI EFI BIOS with CMOS backup supporting embedded features such as remote console CMOS backup hardware monitor and watchdog timer Express IB ADLINIC 2 Specifications N 1 Core System gt CPU 4th Generation Intel Core i7 Processors Mobile 22nm also known as Haswell Platform e Intel amp Core i7 4860EQ 2 4 GHz 3 2 GHz Turbo 47W 4C GT3 Intel Core i7 4700EQ 2 4 1 7 GHz 3 4 GHz Turbo 4
27. Ltd Indian Liaison Office Address 1st Floor 50 56 Between 16th 17th Cross Margosa Plaza Margosa Main Road Malleswaram Bangalore 560055 India Tel 91 80 65605817 91 80 42246107 Fax 91 80 23464606 Email india adlinktech com Page 50 Express IB
28. anagement Bus Alert active low input can 3 3VSB be used to generate an SMI System Management Interrupt or to wake the system Power sourced through 5V standby rail and main power rails Express IB 3 3 13 12 Bus Pin Description Comment 2 CK General purpose port clock output input 10 OD 3 3VSB PU 2k2 3 3VSB 20 DAT E General purpose port data line OD 3 3VSB PU 2k2 3 3VSB 3 3 14 General Purpose 1 0 GPIO Signal Pin Description PU PD Comment Utm De meme mm GPI 0 54 General purpose input pins 3 3V PU 10K 3 3V PU not in PICMG Pulled high internally on the module suggest 10K GPI 1 A63 General purpose input pins 3 3V PU 10K 3 3V PU not in PICMG Pulled high internally on the module suggest 10K GPI 2 A67 General purpose input pins 3 3V PU 10K 3 3V PU not in PICMG Pulled high internally on the module suggest 10K 85 General purpose input pins 3 3V PU 10K 3 3V PU not in PICMG Pulled high internally on the module suggest 10K 3 3 15 Power And System Management Signal Pin Description PU PD Comment PWRBTN Power button to bring system out of 55 soft off active on falling edge 3 3VSB PU 10k 3 3VSB SYS_RESET Reset button input Active low request for module to reset and reboot May 3 3VSB PU 10k be fal
29. and 4 with interrupt 2 8 TPM Trusted Platform Module Chipset ATMEL AT97SC3204 Type TPM 1 2 Optional TPM is qualified during design but is an option in production 2 9 Debug gt 40 pin multipurpose flat cable connector to be used with DB 40 debug module supports BIOS POSTCODE LED BMC access SPI BIOS flashing Power Testpoints Debug LEDs gt 60 header for ICE debug of CPU Chipset 2 10 Power Specifications Power Modes AT and ATX mode AT mode start controlled by SEMA gt Standard Voltage Input ATX 12V 5 5Vsb 5 or AT 12V 5 gt Wide Voltage Input 5 20 V 5Vsb 5 or AT 5 20V gt Power Management ACPI 4 0 compliant Smart Battery support gt Power States supports C1 C6 50 1 54 53 55 55 ECO mode Wake on USB 53 54 WOL 53 54 55 Express IB ADLINK 2 11 Operating Temperatures Standard Operating Temperature 0 to 60 C Wide Voltage Input gt Industrial Operating Temperature 20 to 70 C Wide Voltage Input gt Extreme Rugged Operating Temperature 40 to 85 C Standard Voltage Input 2 12 Environmental Humidity 5 90 RH operating non condensing 5 95 RH storage and operating with conformal coating gt Shock and Vibration IEC 60068 2 64 and IEC 60068 2 27 MIL STD 202F Method 2138 Table 213 1 Condition and Method 214A Table 214 1 Condition D gt Halt Thermal Stress Vibration Stress Thermal Shoc
30. e Name Pin Name Pin Name B36 C36 CTRLOLK AUX 036 C38 000 aux seL 038 RSVD B39 C39 DDI3 7 039 DDI2 PAIRO C40 DDI3 PAIRo 040 DDI2 B41 GND FIXED GND FIXED D41 GND FIXED C42 DDI3_PAIRI 042 DDI2 843 DDIS 0012 PAIRI 844 DDI8 HD 1002 HPD 846 RSVD 1045 RSVD C46 008 PAIR2 046 002 A47 47 EXCD1 PERST C47 DDIS PAIR 002 PAIR PERST RSVD Ade rsvo A49 EXCDO C49 0499 A50 B50 C50 003 PAIRS 50 002 PAIRS A51 GND FIXED B51 GND FIXED 51 GND FIXED D51 GND FIXED 52 PCIE TX5 __ B52 PCIE _ 2 PEG 052 PEG TXO A53 PCIE TX5 853 C53 PEG RX0 ______ 053 PEG 1 0 A54 GPO PEG_LANE_RV A55 PCIE TX4 5 PCIE C55 PEG RXi 055 PEG As PCIE TxA n6 A57 GND 7 602 TYPE2 c DI A59 PCIE TX3 B59 cs9 PEG RX2 1 0159 PEG DO A60 GND FIXED 60 GND FIXED 60 GND FIXED D60 GND FIXED A61 PCIE TX2 B61
31. e needed 2 These CFG signals can be left as Open No Connect if not used as a strapping signal and top side probe will be used to debug processor Refer to the Shark Bay and Denlow Platforms Debug Port Design Guide DPDG Document Number 479493 Revision 1 2 Express IB ADLINK 4 4 Fan Connector gt Connector Type 24 1125 04 00 gt Pin Assignment Name Signal Description BMC_FAN_OUT PWMOUT PWM 4 5 BIOS Setup Defaults RESET Switch To perform a hardware reset of BIOS default settings perform the following steps 1 Shut down the system 2 Press the BIOS Setup Defaults RESET Switch continuously and boot up the system You can release the button when the BIOS prompt screen appears 3 BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system 4 6 PCI Express Configuration Switch Switch SW1 allows you to configure the PCI Express x16 lanes from the CPU as 1 PCle x16 2 x8 1 x8 2 PCle x4 4 HIT A Mode Pin 1 Pin 2 1 PCle x8 2 PCle x4 2 x8 PCI Express Off 1 x16 PCI Express Default Off Off Express IB 4 7 PCle x16 to two x8 Adapter Card The Express HL can be used with the PCle x16 to two x8 Adapter Card on the Express BASE6 Reference Carrier to support bifurbication of the CPU s PE
32. f any kind into the ventilation openings e Toavoid electrical shock always unplug all power cables and modem cables from the wall outlets before removing covers e Lithium Battery provided real time clock battery CAUTION Risk of explosion if battery is replaced with one of an incorrect type Dispose of used batteries according to the instructions lfoneofthe following situations arises get the equipment checked by a service personnel The power cord or plug is damaged iquid has penetrated into the equipment equipment has been exposed to moisture equipment has not work well or you can not get it work according to user s manual The equipment has dropped and damaged the equipment has obvious sign of breakage Express IB Getting Service ADLINK Technology Inc Address Tel Fax Email No 166 Jian Yi Road Zhonghe District New Taipei City 235 Taiwan 886 2 8226 5877 886 2 8226 5717 service adlinktech com Ampro ADLINK Technology Inc Address Tel Toll Free Fax Email 5215 Hellyer Avenue 110 San Jose CA 95138 USA 1 408 360 0200 1 800 966 5200 USA only 1 408 360 0222 info adlinktech com ADLINK Technology China Co Ltd Address 300 Fang Chun Zhangjiang Hi Tech Park Pudong New Area Shanghai 201203 China Tel 86 21 5132 8988 Fax 86 21 5132 3588 Email market adlinktech com ADLINK Technolo
33. gy Beijing Address 801 Power Creative E No 1 B D Shang Di East Rd Beijing 100085 China Tel 86 10 5885 8666 Fax 86 10 5885 8625 Email market adlinktech com ADLINK Technology Shenzhen Address Tel Fax Email 2F C Block Bldg A1 Cyber Tech Zone Gao Xin Ave Sec 7 High Tech Industrial Park 5 Shenzhen 518054 China 86 755 2643 4858 86 755 2664 6353 market adlinktech com LiPPERT ADLINK Technology GmbH Address Tel Fax Email Express IB Hans Thoma Strasse 11 D 68163 Mannheim Germany 49 621 43214 0 49 621 43214 30 emea adlinktech com Page 49 ADLINK ADLINK Technology Inc French Liaison Office Address 15 rue Emile Baudot 91300 Massy CEDEX France Tel 33 0 1 60 12 35 66 Fax 33 0 1 60 12 35 66 Email france adlinktech com ADLINK Technology Japan Corporation Address KANDA374 Bldg 3 7 4 Kanda Kajicho Chiyoda ku Tokyo 101 0045 Japan Tel 81 3 4455 3722 Fax 81 3 5209 6013 Email japan adlinktech com ADLINK Technology Inc Korean Liaison Office Address 8F Mointer B D 1675 12 Seocho Dong Seocho Gu Seoul 137 070 Korea Tel 82 2 2057 0565 Fax 82 2 2057 0563 Email korea adlinktech com ADLINK Technology Singapore Pte Ltd Address 84 Genting Lane 07 02A Cityneon Design Centre Singapore 349584 Tel 65 6844 2261 Fax 65 6844 2263 Email singapore adlinktech com ADLINK Technology Singapore Pte
34. high definition content including Blu ray Disc Superior image quality with sharper more colorful images Playback of Blu ray disc S3D content using HDMI 1 4a spec compliant with 3D e DirectX Video Acceleration DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode Advanced Scheduler 2 0 1 0 support e Windows 8 Windows 7 OSX Linux OS support e DirectX 11 DirectX Express IB gt Multi Display Support independent displays gt Display Types VGA Interface support with 300 MHz DAC Analog monitor support up to QXGA 2048 x 1536 LVDS Interface single dual channel 18 24 bit LVDS through eDP two lane to LVDS Realtek RTD2136R Digital Display Ports x3 DDI1 supporting DisplayPort HDMI DDI2 supporting DisplayPort HDMI DVI DDI3 supporting DisplayPort HDMI DVI 2 5 Audio gt Integrated Intel HD Audio integrated in PCH QM87 gt Audio Codec Realtek ALC886 on Express BASE6 2 6 LAN gt Integrated LAN MAC integrated in PCH QM87 gt Intel PHY Intel Ethernet Controller 12171 gt Interface 10 100 1000 GbE connection 2 7 Multi I O and Storage Integrated in Intel amp QM87 Express Chipset gt USB ports 4 ports USB 3 0 0580 1 2 3 and 4 ports USB 2 0 0584 5 6 7 gt SATA ports four ports SATA 6Gb s SATAO SATA1 SATA2 SATA3 Serial 2 UART ports COM1 2 with console redirection gt 4 GPO
35. ifferential pair PCIE TX7 D22 Express channel 7 Transmit Output O PCIE Not available used by LAN PCIE 7 D23 differential pair PCIE RX7 C22 PCI Express channel 7 Receive Input PCIE Not available used by LAN PCIE 7 C23 differential pair Express IB ADLINK 3 4 3 DDI Channels DDI 1 Signal Pin Description PU PD Comment DDI1_PAIRO Digital Display Interface differential pairs O PCIE SDVO1_RED AC coupled DDI1 PAIRO SDVO1 RED AC coupled DDI1_PAIR1 SDVO1_GRN AC coupled DDI1_PAIR1 SDVO1_GRN AC coupled DDI1_PAIR2 SDVO1_BLU AC coupled DDI1_PAIR2 SDVO1_BLU AC coupled DDI1_PAIR3 SDVO1_CK AC coupled DDI1 PAIR3 SDVO1 CK AC coupled DDI1_PAIR4 SDVO1_INT DDI1_PAIR4 SDVO1_INT DDI1_PAIR5 SDVO1_TVCLKIN DDI1_PAIR5 SDVO1_TVCLKIN DDI1_PAIR6 SDVO1_FLDSTALL DDI1_PAIR6 SDVO1_FLDSTALL Digital Display Interface Hot Plug Detect PCIE e ee 0011 CTRLCLK AUX IF DD DDC SEL is IF DDI_DDC_AUX SEL is foating PCle o ORAE 0000 IF DDI1 MN _AUX_SEL pulled high OD 3 3V SDVO1 CTRLCLK HDMI1_CTRLCLK DDI1_CTRLCLK_AUX IF DD DDC AUX SEL is floating PCle DP1_AUX IF DDI1_DDC_AUX_SEL pulled high OD 3 3V SDVO1_CTRLDATA HDMI1_CTRLDATA Selects the function of I O OD 3 3V PD 1M DDI1_CTRLCLK_AUX and DDI1_CTRLDATA_AUX This pin shall have a 1M pull down to logic ground on the Module If th
36. is input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair contains the CRTLCLK and CTRLDATA signals DDI1_DDC_AUX_SEL Express IB ADLINK TECHNOLOGY INC Description PU PD Comment DDI2_PAIRO Digital Display Interface2 differential pairs 0012 PAIRO DDI2_PAIR1 DDI2_PAIR1 DDI2_PAIR2 DDI2_PAIR2 DDI2_PAIR3 DDI2_PAIR3 000 HPD DDI2_CTRLCLK_AUX IF DDI2 DDC_AUX SEL is floating PCle DP2_AUX IF DDI2 AUX SEL pulled high OD 3 3V HDMI2 CTRLCLK DDI2 CTRLCLK AUX IF DDI2 DDC AUX SEL is floating I O PCle DP2 AUX IF DDI2 AUX SEL pulled high 10 OD 3 3V HDMI2 CTRLDATA DDI2 AUX SEL Selects the function of DDI2_CTRLCLK_AUX and PD 1M DDI2 CTRLDATA AUX This pin shall have a 1M pull down to logic ground on the Module If this input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair contains the CRTLCLK and CTRLDATA signals DDI 3 Description PU PD Comment DDI3_PAIRO Digital Display Interface3 differential pairs DDI3_PAIRO DDI3_PAIR1 DDI3 PAIR1 DDI3 PAIR2 DDI3 PAIR2 DDI3 PAIR3 DDI3 PAIR3 DDI3 CTRLCLK AUX C36 IF DDI3 AUX SEL is floating PCIe DP3_AUX IF DDI3 AUX SEL pulled high 10 OD 3 3V HDMI3 CTRLCLK DDI3 CTRLCLK AUX C37 IF DDI3 AUX SEL is floating PCIe DP3_AUX IF
37. k and Combined Test N 13 Specification Compliance PICMG COM 0 Rev 2 1 Type 6 basic size 125 x 95 N 14 Operating Systems Standard Support Windows 7 8 32 64 bit Linux 32 64 bit Extended Support BSP WEC7 8 Linux VxWorks v N 15 Specification Compliance PICMG COM 0 Rev 2 1 Type 6 basic size 125 x 95 Express IB 2 16 Functional Diagram SODIMM 2 1333 1600 MHz 1 16 GB DDR3L th e DDI 1 port B SODIMM 2 4 Generation DP HDMI DVI SDVO 1333 1600 MHz Intel Core por 1215 08 BOREL i7 i5 i3 Processor DP HDMI DVI DDI 3 port D DP HDMI DVI single dual eDP LVDS eDP 18 24 bit LVDS RTD2136R 2lane Haswell 2 x8 or 1x8 2x4 VGA 6x PCle x1 GEN2 GbE LAN 1x PCle x1 i217LM port 6 4x USB v3 0 port 0 1 2 3 CD 4x SATA3 port 0 1 2 3 PCH HDA Audio Serial ASR AT97SC3204 header LPC bus GPIO 4 PCA9535 DDC I2C SPI CSO SPI CS1 SPI Cc SPI Express IB ADLINK TECHNOLOGY INC 2 17 Mechanical Drawing En 95 1 1 IO J O OL E E E E 111111 1111 J 1111 1 1 1 11111 1 1 1 1 1 1 1 1 1 11 11111111111111 connector on bottom side 4 OV CC 6 B TE 8 Z i 45 UT u
38. ling edge sensitive For situations when SYS_RESET is not able to 3 3VSB reestablish control of the system PWR_OK or a power cycle may be used CB_RESET B50 Reset output from module to Carrier Board Active low Issued by module 3 3VSB chipset and may result from a low SYS_RESET input low PWR OK input a 12V power input that falls below the minimum specification a watchdog timeout or may be initiated by the module software PWR OK B24 Power OK from main power supply A high value indicates that the power is TBD by R amp D Should have good This signal can be used to hold off Module startup to allow carrier in CPLD weak pull up based FPGAs or other configurable devices time to be programmed SUS_STAT Indicates imminent suspend operation used to notify LPC devices 3 3VSB SUS_S3 A15 Indicates system is in Suspend to RAM state Active low output An inverted O 3 3VSB copy of SUS 538 on the carrier board also known as PS may be used to enable the non standby power on a typical ATX power supply 505 54 Indicates system is in Suspend to Disk state Active low output 3 3VSB SUS_S5 Indicates system is in Soft Off state 3 3VSB B66 PCI Express wake up signal 3 3VSB PU 10k 3 3VSB Express IB ADLINK TECHNOLOGY INC Pin Description Comment WAKE 1 B67 General purpose wake up signal May be used to implement wake up on 3 3VSB PU 10k PS 2 keyboa
39. oller Note 1 Controller 1 Note 1 These IRQs can be used for PCI devices when onboard device is disabled Express IB ADLINK 6 5 PCI Configuration Space Bus Device Function Routing Description Number Number Number Internal Intel I G D Internal HD Audio Device mm jm me ee m m etn Express IB 6 6 PCI Interrupt Routing INT P E G Audio ME ME IDE R KT GbEt HDA Line RootPort Controller Controller Controller 1 Controller 2 Controller Controller INTA46 INTA 16 INTA 21 16 INTE 20 INTG 22 INTD 19 INTC 18 INT PCIE port2 PCIE port3 PCIE port4 PCIE 5 PCIE Port6 PCIE Port7 PCIE port 8 Line 16 INTB 17 INTD 19 INTA46 1 6 INTD 19 16 INTB 47 INTC 18 16 INTB47 INTC 48 1 6 INTB 47 INTC 18 INTD 19 INTB 47 INTC 18 INTC 18 9 INTB 17 INTC 18 INTD 19 INTA 16 INTC 18 9 INTD 19 INTA46 INTC 18 INTD 19 INT EHIC 1 EHIC 2 LPC SATA SMBus SATA Thermal Line Controller Controller 1 Controller Controller 2 Subsystem o fares ome o __ mI ms mI i 1 1 T T Express IB ADLINK Safety Instructions Read and follow all instructions marked on the product and in the documentation before you operate your sy
40. rd or mouse activity 3 3VSB BATLOW 27 Battery low input This signal may be driven low by external circuitry to 3 3VSB PU 10k signal that the system battery is low or may be used to signal some other 3 3VSB external power management event LID LID button Low active signal used by the ACPI operating system for a LID OD PU 10k switch 3 3VSB 3 3VSB SLEEP Sleep button Low active signal used by the ACPI operating system to bring OD PU 10K the system to sleep state or to wake it up again 3 3VSB 3 3VSB 3 3 16 Power and Ground Signal Pin Description PU PD Comment VCC_12V A104 A109 Primary power input 12V nominal 5 19V See section 7 8 5 19 V 8104 8109 Electrical Specifications for allowable input range All available VCC_12V pins on the connector s shall be used VCC_5V_SBY B84 B87 Standby power input 5 0V nominal See section 7 Electrical 5 6 5 Specifications for allowable input range If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functions May be left unconnected if these functions are not used in the system design VCC RTC Real time clock circuit power input Nominally 3 0V f GND A1 A11 A21 A31 Ground DC power and signal and AC signal return path A41 A51 57 A66 A80 A90 A96 A100 A110 B1 B11 B21 B31 B41 B51 B60 B70 B80 B90 B100 B110 Express IB
41. stem Retain all safety and operating instructions for future use Please read these safety instructions carefully Please keep this User s Manual for later reference e The equipment should be operated only from the type of power source indicated on the rating label Make sure the voltage of the power source when connect the equipment to the power outlet lfyour equipment has a voltage selector switch make sure that the switch is in the proper position for your area The voltage selector switch is set at the factory to the correct voltage For pluggable equipment that the socket outlet shall be installed near the equipment and shall be easily accessible Place the power cord such a way that people can not step on it Do not place anything over the power cord equipment is not use for long time disconnect the equipment from mains to avoid being damaged by transient overvoltage e All cautions and warnings on the equipment should be noted e Please keep this equipment from humidity e Donotuse this equipment near water or a heat source e Lay this equipment on a reliable surface when install A drop or fall could cause injury e Never pour any liquid into opening this could cause fire or electrical shock e Openings in the case are provided for ventilation Do not block or cover these openings Make sure you provide adequate space around the system for ventilation when you set up your work area Never insert objects o
42. t our products manufacturing processes components and raw materials have as little impact on the environment as possible When products are at their end of life our customers are encouraged to dispose of them in accordance with the product disposal and or recovery programs prescribed by their nation or company Trademarks Product names mentioned herein are used for identification purposes only and may be trademarks and or registered trademarks of their respective companies Express IB ADLINK TECHNOLOGY INC Table of Contents Revision History 2 Prei sep tac u 3 i ssi M 7 2 SpechcalioiSuu uu I PUNIRE 8 2 1 Sal hec T 8 2 2 OD C RITTER 8 2 3 SEMA Board COMET IA 8 2 4 lI 8 2 5 9 2 6 EAN 9 2 7 Muli 170 3nd AA 9 2 8 TPM Trusted Platform Module PNE 9 29 B E 9 2 10 secerneren E TE 9 2 11 Operating Temperatures iia 10 2 12 EN WA 10 2 13 Speciication ComplialiCe uiscera
43. th System Resource C jm NN Express IB ADLINK 6 3 Hex Range Device 000 01F DMA controller 1 8237A 5 equivalent 020 02D and 030 03F Interrupt controller 1 8259 equivalent 02E 02F LPC SIO configuration index data registers 040 05F Timer 8254 2 equivalent 060 062 064 066 068 06F 8742 equivalent keyboard 061 063 065 067 NMI control and status 070 07F Real Time Clock Controller bit 7 mask 080 091 DMA page register cO N Reset Bit 0 Fast Gate A20 Bit 1 93 9F DMA page registers continued 0A0 0B1 and 084 Interrupt controller 2 8259 equivalent 2 and 0B3 APM control and status port respectively 0C0 0DF DMA controller 2 8237A 5 equivalent 0 Available Co processor error register 1 gt OF2 0F3 gt 0 4 IDE ID port 5 OF8 IDE Index port OF9 0FB N A IDE Data port TI C OFD OFF gt 100 179 Available 180 181 Default AIM4 SRAM control register May be remapped 182 1EF Available 1F0 1F7 Primary IDE Controller AT Drive 1FB 22F Available 230 23F Available 240 25F Serial Port 3 4 260 2F7 Available 2F8 2FF Serial Port 2 300 36F Available Express IB Hex Range Device 370 377 Alt Floppy Disk Controller 378 37F Available 3C0 3DF VGA registers CC Slave PIC
44. tial PCIE AC coupled off Module PCIE RX1 B65 pair PCIE TX2 A61 PCI Express channel 2 Transmit Output differential O PCIE AC coupled on Module PCIE TX2 A62 pair PCIE RX2 B61 PCI Express channel 2 Receive Input differential PCIE AC coupled off Module PCIE RX2 B62 pair PCIE TX3 A58 Express channel 3 Transmit Output differential PCIE AC coupled on Module PCIE TX3 A59 pair PCIE B58 Express channel 3 Receive Input differential PCIE AC coupled off Module PCIE RX3 B59 pair PCIE TX4 A55 PCI Express channel 4 Transmit Output differential O PCIE AC coupled on Module PCIE TX4 A56 pair PCIE RX4 B55 Express channel 4 Receive Input differential PCIE AC coupled off Module PCIE RX4 B56 pair PCIE TX5 A52 PCI Express channel 5 Transmit Output differential O PCIE AC coupled on Module PCIE TX5 A53 pair RX5 B52 PCI Express channel 5 Receive Input differential PCIE AC coupled off Module PCIE RX5 B53 pair A88 PCI Express Reference Clock output for all PCI O PCIE PCIE CLK REF A89 Express and PCI Express Graphics Lanes 3 3 7 Express Card Signal Pin Description PU PD Comment EXCD0_CPPE 49 ExpressCard Express capable card request 3 3V PU 10k EXCD1_CPPE B48 3 3V EXCD0_PERST A48 ExpressCard reset 3 3V Cannot be tested on Express EXCD1_PERST B47 BASE6 DVT issue Express IB 3 3 8
45. till 3 samples not influenced by the read access Main Current MSB n 8 LSB n x 8 06mA 5 1 3 BMC Status This register shows the status of BMC controlled signals on the Express HL Status Bit Signal umum wawa 5 1 4 Exception Codes In case of an error the BMC drives a blinking code on the blue Status LED LED1 The same error code 15 also reported by the BMC Flags register The Exception Code is not stored in the Flash Storage and is cleared when the power is removed Therefore a Clear Exception Code command is not needed or supported Exception Code Error Message Gunawan wa mm Express IB Page 39 ADLINIC Exception Code Error Message e CRITICAL_TEMP Lx wmm www 5 1 5 BMC Flags The BMC Flags register returns the last detected Exception Code since power up and shows the BIOS in use and the power mode 0 4 Exception Code 0 AT mode 1 mode 0 Standard BIOS 1 Fail safe BIOS Express IB 6 System Resources 6 1 System Memory Map Address Range decimal Address Range hex Size Description 4GB 2MB 00000 FFFFFFFF 4GB 18MB 4GB 17MB 1 00000 FEEFFFFF 4GB 20MB 4GB 19MB 1 0000 FECFFFFF 15MB 16 F00000 FFFFFF 1MB 15MB 100000 EFFFFF 6 2 Direct Memory Access Channels Channel Number Data Wid
46. umber Production Date Main current amp voltage monitors drawn current and main voltages For a detailed description of SEMA features and functionality please refer to SEMA Technical Manual and SEMA Software Manual downloadable at http www adlinktech com sema 5 1 Board Specific SEMA Functions 5 1 1 Voltages The BMC of the Express HL implements a voltage monitor and samples several onboard voltages The voltages can be read by calling the SEMA function Get Voltages The function returns a 16 bit value divided into high byte MSB and low byte LSB ADC Channel Voltage Name Voltage Formula V MSB 8 LSB x 1 100 x 3 3 1024 MSB 8 LSB x 3 3 1024 MSB 8 LSB x 1 100 x 3 3 1024 VDDQ V1 35 V1 5 MSB 8 LSB x 3 3 1024 MSB 8 LSB x 1 833 x 3 3 1024 MSB lt lt 8 LSB x 6 000 x 3 3 1024 MAIN CURRENT Use Main Current Function Page 38 Express IB 5 1 2 Main Current The BMC of the Express HL implements a current monitor The current can be read by calling the SEMA function Get Main Current The function returns four 16 bit values divided in high byte MSB and low byte LSB These 4 values represent the last 4 currents drawn by the board The values are sampled every 250ms The order of the 4 values is NOT in chronological order Access by the BMC may increase the drawn current of the whole system In this case there are s

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