CATCH1 User Manual
Contents
1. 1 DD A1 DIR 1 026 p19 Di A2 G 2 11 9 4 iHe 43 5 lee 6 2 5 6 14 6 5 AZ TP17 15 85 5 5 5 36 5 CND Ag 8 BDTACK 17183 DTACK 10 49 BBERR 18 2 BEER XA AI Bei Ae A11 74ALS641 1 1050 212 13 19 15 15 U27 ba A16 et GND 16 BDSO 11 9 DSO AS 217 BDS1 12 8 S 8 DS1 GND A19 18 BWRITE 1300 WRITE JACK 20 429 BAS 14 v8 6 6 JAS __ 21 20 BLWORD 15 12 5 WOFD A22 25 BIACK 1694 LA A23 22 BSYSRE 17 3 SYSRES AZ A24 Y2 A2 2 AG 25 24 18 x Yi A1 x A26 25 74ALS541 A4 A27 26 TOVME 1 28 lt Roe A28 29 DIR 1 4 Al A30 A30 PIR pis A31 230 22 4 A32 9 VCCN BB Di B1 87 7 5 B6 6 B2 85 5 2 Di Spa 4 4 585 4 83 5 2 88 85 2 2 5 5 6 BI A1 8 87 74ALS645 1 Bo 10 1 DIR u29 PI pis 7 ABTS B Br M Gp 010 86 6 6 D11 B5 55 D12 BA 44 4 B32. 2 1 NTG TRAD APD BSRD 4 3 ENRST CLHD 6 5 ENCLR USRD 8 8 ENUSER a 10 330 10 11 ENPATT d 4d 4 U2A TR GN 12 13 BSGN 2 1 ENTE green CLON 4 3 US GN 6 5 ENUSER Di BAN OWNS C5 PA GN 8 9 ENPATT uF 4 Al at 4 4 10 111 Bid 12 12 13 ERST Tig ED 7418125 5 1 10 4 3 209259 me 4519 14 918 eT i39 Di 2 3 UB e yma rst 517 9 al 1 16 QI sg use E re Q2 5 15 3 9 4 t te gt 5 6 USER 3 1 19 ger 1 gt gt FST e 05 7 4 20g 28 usc 1 ncc 211 F100325 9 8 226 Di usp E 29919494 22 5 8 joo 2 24d pg 8 12 ile DUER ududd O 1uF gt gt PATT ode sts L w 1158 4 gt gt 40MHZ 4 ES Fo 19 52 2 ur 1 13 4 195 8 18 004 F7 17 204 EN 6 6 5 5 i3 pos 4 8 gt gt EN CODE R 203 pia 5 F3 5 8 m vec 40 Do2 pis 3 6 2 202 Fo 2 X 2 001 1 22 10 001 DH m 90 031 4 4 2 1 UAR 1 25 MHz Y 74ALS04 R154 5 FIFI o 8 gt 65 ih m n uti CY7CA2d E 2 2 18 6 16 0
3. Reset switches F1 RJ 45 CPLD TEST ECL Input Robinson Nugent Connector FPGA Figure 5 Components the 4 Components on the Board In this section a brief overview will be given on the important ICs on the board Their locations can be taken from Figure 5 and detailed descriptions can be found in the corresponding data sheets or specifications 4 1 Xilinx XC95288 15 CPLD This Complex Programmable Logic Device CPLD houses the VME inter face logic and the serial transmitter for the setup data to the front end It retains its information when power is switched off but can be reprogrammed via the CPLD JTAG connector on the front panel For detailed information see 1 4 2 Xilinx XC4020E 2 FPGA This IC is a Field Programmable Gate Array in which the Test Pulse Con troller is implemented It has to be configured on each power up As already mentioned this can be done either via the VMEbus or via the FPGA connec tor on the front panel of the CATCH1 The configuration via VME requires 21 configuration data in form of a file that contains either binary or hexadecimal numbers This data will be transferred to the chip bit by bit An example routine written in C language can be found i
4. C45 C46 C47 C49 C50 C51 c52 C53 C54 c59 C60 C61 c62 C63 C64 C65 ces C67 ces 0 C71 C70 c69 12 037 LM337D2T a 12V 4 3 4 oN v 1 DROSSEL 500mA L gt R139 4 330 C55 c56 6 8uF 20V 6 8uF 20V R140 1k ME 7 19 TP20 21 22 Fakult t f r Physik Freiburg Braun Tite Catch 1 Power Size Document Rev Number FPF 288 B 04 Date Wednesday 13 1998 Sheet 7 of A B D E Figure 14 Power 37
5. sc 19183 5 Daa 1482 A2 5 1 744156451 19 b19_4 Br 9 A24 8 7 6 5 4 3 2 BAM 0 5 19 use 92 Ba Sys ase Ta 145 Ve AM1 BAM2 15 93 Ae LS AM2 16 4 iz v3 AMA 5 18702 Bo a AM5 74415541 lt 4 VME J2 P2 Fakult t f r Physik Freiburg Braun Tite Catch 1 Lower VME Connector Size Document Rev Number FPF 288 B 04 Date Wednesday 13 1998 heet 6 of 7 A B c D Figure 13 Lower connector 36 L1 4 voc 4 5 DROSSEL 3A _ Z5 6 8uF 20V c12 C13 C14 VCC 4 c15 C17 c19 c20 C21 c22 C24 O pF M M M 4 C25 C26 C27 C28 C29 C30 c31 c32 C33 C34 4 c35 c36 C37 C38 c39 C41
6. UNIVERSIT T FREIBURG BUTTON DESCRIPTION S clears all registers of FPGA soft re set and both S and H put the CATCHI power up state hard reset status of the Test Pulse Controller For deti Clapier 25 PWR green power CPLD green interface is busy ERR red FPGA error during configuration ERR red corrupted data from front end SYNC green synchronization characters received DATA yellow serial data arrives from the front end TRG red green Trigger RST red green Reset CLR red green Clear USR red green User PAT red green Pattern Strobe red internal green external ECL CONNECTOR DESCRIPTION carries serial HOTLink data USER commands the 40 MHz clock all differ ential and serial front end setup data Setup data and USER commands are transmitted synchronously to the 40 clock CPLD coded connector to program the CPLD TEST coded connector to debug the FPGA FPGA coded connector to program the FPGA ECL ECL inputs for the trigger signals PATTERN OUT TTL test pattern transfer with 64 pins Robinson Nugent test pattern including 12 DAC value 1 pin DAC control 1 pin trigger and 10 pins GND Figure 4 The Front Panel of the 17 Table 9 Robinson Nugent Connector SIGNAL NAME PIN NUMBER SIGNAL NAME GND GND DACSTR DACSTR GND GND not used not used DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU
7. USER2 i 5 SERIAL OUT i ____ gt USERS _ SERIAL OUT d USERA AEN SERIAL OUT E 05 Figure 3 USER command timings on the connector can be individually enabled with the SETUP TRIGGER command see Table 3 The applied signals must be at least 30 ns long After one signal has been encoded the next one can be handled one clock cycle later Maximum rates for the USER commands can be found in Chapter 5 2 The timing of the outgoing USER commands with respect to the 40 MHz clock can be taken from Figure 3 Because the incoming signals from VME automatically generated Triggers or ECL signals arrive asynchronously at the USER Command Coding Unit the encoded USER commands have an uncertainty of one clock cycle In Figure 3 incoming signals that are present in the 25 ns interval ending 4 5 ns before the rising edge of clock cycle 4 produce encoded signals with the same timing The 4 5 ns are the chip s internal register setup time For incoming signals that are present within this time before a rising edge of the clock it is not predictable if the encoding will start with the next rising edge or only one clock cycle later The USER command transfer via VME is done with the WRITE_TRIG command that has the offset address 9650 Here the signals are sent via the VME data lines D03 to D00 which correspond to the User the Clear the Reset and the Trigger signals respectively Whenever two U
8. 5 D14 2 5 Dis 74ALS645 1 uso G2 pi G1 ys 8 9 Va OAL A21 vo AS A20 5 A5 5 A19 YA 4 5 19 3 1 2 2 5 15 74415541 19 ust 8251 7 9 A Y8 A8 7 8 ds YE AS rg A12 YS AB 5 11 ME om A10 5 2 2 C16 2 AB go 74ALS541 GND A19 C19 A18 C20 C19 19 A 021 C20 use 92 51 16 c22 21 A15 C23 028 9 AZ A14 C24 vs CAS Ua 6 A13 C25 024 7 AS A12 C26 25 E 6 6 4 11 C27 26 voy AD 3 A10 C28 27 n C29 29 3 1 Y2 2 3 32 1 cao Yi A1 x sh C31 74415541 vcoN amp AMOS 4 UPPER CONN Fakult t f r Physik Freiburg G Braun Catch 1 Upper Connector Size Document Rev Number FPF 288 B 04 Date Wednesday 13 1998 Sheet 5 o 7 A B D E Figure 12 Upper VME connector 35 TOVME DIR 1 4 uss PIR pis 11 2 D16 13187 7 7 14 86 ABTG 15 85 5 5 020 16 4 4 021 173 03 022 2 2 1881 1 D23 74ALS645 1 DIR H usa PIR pis 4 13187 7 7 026 14 86 6 6 027 16785 5 DR
9. bits 031 to 024 empty offset LSB register default value 07h bits 1223 to 016 empty offset MSB register default value 00 bits D15 to D08 full offset LSB register default value 07h bits D07 to DOO full offset MSB register default value 00h All eight bit are written into the least significant bit registers LSB whereas only the five least significant bits are written into the most significant bit registers Therefore the user can program the almost empty and the almost full flags in the range from 0 to 7905 Front end data can be read from the FIFO using the READ FIFO com mand with the offset address 9608 Each time three words of eight bit are read in the big endian format The first word read from the FIFO is trans ferred in bits 23 to 16 the second in bits 15 to 8 and the third in bits 7 to 0 For each word two more bits are read out the first is the ninth FIFO bit which indicates possible transmission errors of the incoming serial data stream The second one is the empty flag of the FIFO buffer In case of transmission errors the error bit is one and when the FIFO buffer is empty the bit containing the empty flag is zero Reading data from an empty FIFO buffer results in getting always the same datum i e the last datum that was written into the buffer The bit assignment for the READ FIFO command can be found in Table 2 Table 2 Bit assignment for the front end data read from the FIFO buffer 91 0
10. uo 5 7 VO 6 VO 203 5 2 53 Hia 84 07 VO 202 6 54 He 5 201 A4 05 HS i9 O9 VO 200 5 06 Hs VO 10 199 37 07118 VO 11 VO 198 25 7 8 VO 12 VO 197 54 A8 VO 13 VO 196 51 9 VO 195 23 A10 VO 15 GND gt 11 VO 16 VO 193 A12 1017 16 192 192 25 A13 VO 18 VO 191 A14 VO 19 VO 190 20 VO 20 189 2 VO 21 VO 188 55 VO 22 VO 187 WE 23 186 VO 24 VO 185 GND VO 184 VCC VO 27 GND DLE VO 28 VO 181 ATS VO 29 VO 180 RADDO RDAT4 RADE 51 VO 30 VO 179 BADDI 32 VO 178 VO 32 VO 177 RADD3 33 VO 33 VO 176 B 2___34_ io 34 VO 175 1 35 36 VO 35 VO 174 37 VO 36 VO 173 80MHz ND VO 172 5 39 98 GND 20 0 59 VO 170 uei VO 40 169 22 VOA VO 168 48 VO 42 VO 167 dd VO 43 VO 166 50MHz IHA VO 44 VO 165 CLOEPG 5 VO 45 VO 164 OUT 46 49 1 VO 46 VO 163 u22 VO 162 Mi 48 O 48 VO 161 GD 49 D 50 ND GND 21 150 159 1 ne nc X nc nc U23A s ME 74ALS74 voc 55 ne ne 84 voc 6 voc 1 56 153 29 156 CCLK 185 VO 57 VO 152 EPIN CLK VO 58 VO 151 150 AANE 5 m 2 VO 59 lO 150 VO 60 VO 149 149 VO 6t VO 148 VO 62 VO 147 VO 63 VO 146 VO 64 VO 145 VO 65 VO 144 VO 66 VO 143 GND VO 68 VO 141 VO 9 VO 140 VO
11. FREADY 74 Vo 74 VO 135 H 2 BDTACK VO 134 IN BBERR VO 76 VO 133 EDATIS 72 VO 77 VCC Dovme lt EDAT4 78 75 VO 181 79 FDATi3 80 VO ap ae 8h VO 128 DA 52 VO 127 N A VO 83 VO 126 FDATO EDAT 10 84 VO VO 125 LS FDATI FDATS 65 yo as VCC FDAT2 i 56 vo VO 123 VO 87 VO 122 FDATA VO 121 IN VO 89 VO 120 FDAT6 EAS 20 VO 90 VO 119 MO 91 091 VO 118 IN 9 2 voc VO 417 IN FDAT8 2 94 ND VO_116 En VO 415 FDAT 10 CNS 38 YO_95 VO 114 gt gt BAMIO 5 FDAT11 MS EN FDAT12 96 VO 97 VO 112 gt gt BA 1 23 FDAT 13 0 1 FDAT14 DA 00 VO 90 VO 110 99 3599 EN gt gt BA 24 31 FDAT15 A VO 10 VO 109 L1 FDATO 101 y 101 108 __ END gt gt BD 0 15 TE 102 vo ic VO 107 492 S01 106 vex gt gt BD 16 31 0 Fakultat f r Physik Freiburg Braun Title Catch 1 CPLD JE Size Document Number FPF 288B 04 Date Wednesday 13 1998 heet 3 o 7 5 Figure 10 33 CPLD FDAT4 FDAT5 FDAT6 FDAT7 FDAT8 FDAT9 FDAT 10 FDAT11 FDAT 12 FDAT 13 FDAT 14 FDAT 15 XC4020 Uto 1 208 X ne 398 3 AND 506 CY7C199 10 aon EC 205 voc 10 Jing 1 X VOS VO 204
12. 2s 3143 1 17 810 99 17 4 4 4 Y3 16 2 4 re Q2 18 2 FIFO2 46 VORA 514 15 22 92 19 PROS 6 6 6 A5 Y5 14 4 FIF 2 20 4 FIFO4 SEZ gt Qo 18 7142 we O3 04 04 21 2 E 17 8 12 6 32 22 6 5 1 1 NAE Q 9 Lo 96 23 37 H AB m FIFO7 e 8 8 g FIFO8 1 4 1 R27 TL 6 3 as 3 199 Hk 28 WENT RENT 6 WENZ ID RENZ 12 FIFOREN lt 23 mer 74005941 27 1 rirorci 110300 26 ME soja 19 4 013 8 FPAE vec by Avs 10 810 Fo PAF FPAF CY7B933 7 26 4 14 4 278983 in 28 EFS H BSTEN 2 lt He F2 1 FFF FE 4 245 F3 FS E 4 F4 5 F5 470k T6 hs Rae 19 6 B PEST 4 e IPs 31 18 TP9 1218 F8 37 FIFORST 5 1319 ro FIFO LD FIFOWQLK 1 77 cv ES B 7 ns 555 22V10plcc Fa Uu 2 CYENA Rot a TR CYRVS GYRDY CYRI CYBIST 470 4 vec 11 5 1 9 5 cy EAH Ww 7 ns 555 LEDye y 5 DATA 3 2 REB a TR uA 4 4705 rhe gt mr 016 5 giz our Fakult t f r Ph Freiburg G Braun LEDd
13. 5 os 9 6 ERROR siala EET Catch 1 Data Transfer to from FE 4 3 Bize Documert lov Number FPF288B 05 alo Thursday October 15 1998 heet 1 o 7 X 5 D E Figure 8 Data Transfer from to FE 31 5 6 gt voc gt gt CPLDLED voc gt gt ANT 210 Dii 3 LED 3mm 2 low current LEDgi LEDrd PWR CPLD FPGAEFR sees TSEG6 2 pa TSEGS DSi SEGA HDSP7801 gn TSEG2 Z e 75608 7SEGA a 3 17330 E99 SEG U17A r L2 339 E40 6 4 Pat 1 2 gt Suo PAS SEGA voc SOFTRES c L8 1396 144 P42 91 359 1345 73 2 27k 741307 a 10330 46 SEG HARD
14. D TACK is asserted by the module itself and the signal BERR is fore seen but not yet implemented in the design The CATCH1 works in the A32 6 addressing mode and recognizes the following Address Modifier codes indicates hexadecimal numbers 5 00 extended supervisor data access 5 9609 extended non privileged data access The base address of the can be manually selected with two four bit rotary switches on the board which are compared to the address lines A08 A15 Hence the Base Address can be selected in the range of 000 0000 to 000 FFOO The module transfers data in the D32 mode It responds to Quad Byte Transfers which require the signals 050 DS1 LWORD and 401 to be low The commands controlling the CATCH1 module are encoded in the ad dress lines A02 A07 Therefore an offset has to be added to the module s base address for each command Most commands also require the transfer of data There 13 commands defined for the CATCHI which perform the following actions 00 READ ID reads a unique board identifier 08 READ FIFO reads front end data from the FIFO buffer 10 READ STATUS reads the status of the board s components 18 READ_FPGA reads scalers of the Test Pulse Controller 40 WRITE SERIAL writes front end setup data to the serial transmitter 48 WRITE FPGA writes test pattern or control data to the Test Pulse Controller 50 WRITE_TRIG writes USER1
15. DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU T63 T61 T59 T57 T55 T53 T51 T49 T47 T45 T43 T41 T39 T37 T35 T33 T31 T29 T27 T25 T23 T21 T19 T17 T15 T13 T11 9 T07 05 T03 01 B40 e B39 e B38 e B37 e B36 e B35 e B34 e B33 e B32 e B31 e B30 e B29 e B28 e B27 e B26 e B25 e B24 e B23 e B22 e B21 e B20 e B19 e B18 e 17 e B16 e B15 e 14 e B13 e B12 e 11 e 10 e B09 e 308 e e B06 e B05 e B04 e B03 e B02 e 1 e 18 e A40 e A39 e A38 e A37 e A36 e A35 e 34 e A33 e A32 e A31 e A30 e A29 e A28 e A27 e A26 e A25 e 24 e A23 e A22 e A21 e A20 e A19 e A18 e A17 e A16 e A15 e A14 e A13 e A12 e A11 e A10 e A09 e A08 e A07 e A06 e A05 e A04 e A03 e A02 e A01 GN DOUTSTR DOUTSTR DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU DOU T60 T56 T54 T52 T50 T48 T46 T44 T42 T40 T38 T36 T34 T32 T30 T28 T26 T24 T22 T20 T18 T16 T14 T12 T10 08 06 04 T02 TOO The differential signals should be decoupled by capacitors on the front end board Table 6 shows the pin assignment for the RJ 45 connector Three connectors are foreseen for programming and debugging of the FPGA and the CPLD devices With the CPLD JTAG connector the VME interface
16. Ere Dis DEPT TRE bits i to data 1 T bits belong to data word 2 t bits belong to data word 3 2 4 Serial Transmitter 10 Mbit s The serial interface for the front end setup data can be selected with the WRITE SERIAL command with the offset address 9680 The interface works unidirectional and provides no error handling Each transmission consists of two start bits 24 data bits and two stop bits Both the start and the stop bits are a sequence of one zero After data transmission the interface stays at zero This serial transmitter runs with a frequency of 10 MHz which is derived from the 40 MHz clock The serial data is transmitted to the front end system synchronously with the 40 MHz clock This clock can be used to decode the serial data on the front end side and to synchronize the front end equipment in the experiment 2 5 Test Pulse Controller The Test Pulse Controller is implemented in programmable logic device FPGA which has to be configured after each power up This configuration process can be either done from a PC via a connector on the front panel of the CATCHI or via the VMEbus The programming via the VMEbus is done using the PROG_FPGA com mand with the offset address 88 Depending on the datum written to this 10 address three programming pins of the FPGA can be enabled disabled set or reset These are the PROG pin initializes the FPGA the DIN pin here the serial configuration data is a
17. It features the same communications with the front end as those being used in the COM PASS experiment All the data between front end board and are transferred via an S UTP cable CAT 5 the digitized detector informa tion Chapters 2 2 and 2 3 initialization data for the front end electronics Chapter 2 4 four USER commands e g TRIGGER for the front end Chapter 2 6 and distribution of a 40 MHz clock The main difference is that the CATCHI only communicates with one front end board 64 chan nels whereas in the experiment 16 front end boards will be read out by one CATCH module 64 analog pulses Pulser Box 1 FE board 64 bit Pattern S UTP CAT 5 cable Amplitude DAC Data 250 MHz Pattern strobe USER 1 4 40 MHz Setup 10 MHz 40 MHz clock External ECL CATCH 1 USER 1 4 Pattern pulse VME bus A32 D32 Setup Control amp Readout Figure 1 Possible test setup with the CATCHI board The CATCHI is a very flexible device It provides up to 64 independent TTL test pulses which can be programmed via the VMEbus The pulses are converted into analog signals in an external Pulser before being used to simulate a detector system This makes it easy for the user to adjust pulse shapes to the needs of the front end system which is to be tested The data flow for a possible test setup can be found in Figure 1 Another feature are internal s
18. 012 Z 2 2 5 DOUTSIR ROB NUGENT 80poig Plug Fakultat f r Physik Freiburg Braun Catch 1 Test Outputs Size Documert Rev Number FPF 288 Thursday October 15 1998 2 of X 8 6 5 E Figure 9 Test Outputs 32 voc 5 88 fbi voc i 208 S1 GD 2 Wo VO 208 207 GND 1 762 COND GND 206 750 DPS 1 3 298 1 0 VO 205 208 VO 5GTS4 Voc CYENA 86 06 VO 208 axan FAN 7 6 E 6 5 gge 0 202 Reime 10600 dae VO 12 VO 197 FTRIG2 GND 13 m 196 A d 14 ND VO 196 195 BD 1 d 15 19 14 19 185 194 T Swi 16 193 BD4 ADD 12 15 CPLDRES 17 16 193 192 1811 2 17 VO 192 97 PO A FIF 19 18 191 190 GND JDIPO 145 gt 29 VO 19 146 VO 20 1 21 vo A m cn 23 9 2 d 4 24 WO 4 27 cms
19. 4 to the USER Command Coding Unit 80 PROG FIFO sets the programmable flags of the FIFO buffer 88 PROG FPGA sets the pins for programming the FPGA 90 BISTEN enables the Built In Self Test of the serial data receiver 98 REFRAME toggles the REFRAMING option of the se rial data receiver on off 0 RESET_FIFO resets the FIFO buffer ADDRESS ONLY cycle 8 RESET_FPGA Soft reset of the Test Pulse Controller ADDRESS ONLY cycle T In the following these commands will be described in more detail overview of all commands their offset addresses and the data transferred can be found in Table 5 at the end of this chapter Chapter 4 contains a brief description of all the components on the The board identifier is of the form CA1000XX hexadecimal where the XX stands for the serial number of the CATCHI1 The READ ID command has an offset address of 9600 The offset address of the READ STATUS command is 9610 It reads nine bit VME data lines D15 to D07 of status information The different bits have the following meaning bit D15 INIT pin is 1 if the Test Pulse Controller is programmed 0 when an error occurred during configuration bit D14 DONE pin is 1 if the Test Pulse Controller is programmed bit D13 EF pin is 0 if the FIFO is empty bit D12 pin is 0 if the FIFO is almost empty programmable bit D11 PAF pin is 0 if the FIFO is almost full programmable bit D10 pin is 0 if the FIFO is
20. ECL level dynamically terminated with 100 23 ECL input pulses e width gt 30 ns The device driving the external ECL signals must have a 750 Q emitter pull down resistor and a ground connection to the CATCHI must exist USER command output e width 25 ns to 100 ns e USERI TRIGGER frequency lt 15 MHz fastest e USERA User frequency lt 5 MHz slowest Test Pulse Pattern output e Pattern strobe width 30 ns e DAC data strobe width 150 ns e DAC data setup time 120 ns e DAC data hold time 20 ns On the CATCHI the timing of DAC data strobe DACSTR and data signals DOUTO00 DOUT11 is adjusted to the requirements of the digital to analog converter used on the Pulser AD7845 6 Signal levels and timing can be taken from Figure 6 where the 12 bit DAC data DOUTOO DOUT 11 are active high 150ns DACSTR DACSTR 120 5 2120 ns 2 DOUT11 AM Figure 6 DAC setup timing The 64 test pattern signals are active high and remain present at the Robinson Nugent connector until another pattern is transferred to the Test Pulse Controller Pattern strobe is also a differential signal DOUTSTR 4 is positive and DOUTSTR negative when the test pattern is sent to the front end board 24 Performance with MVME 2604 Writing 64 bit test pattern pattern strobe 0 33 MHz Writing only pattern strobe 1 92 MHz Writing USER c
21. VO 25 2 OS 28 VO 28 E DONE 58 10 26 DN 31 030 PROG 32 31 14 INIT 33 123 sw2 SOFTRES 34 3 io 00 ADD 8 11 FECB 35 174 esysres __36 35 174 173 2 D12 330 R149 UART 37 35 VO 173 175 50 38 YO_37 171 BA22 24 1 CYBVS 39 38 171 170 GYBDY 169 BA21 D13 330 R150 BDY 40 vO 20 VO 169 Hee BASE 1 AND VO 41 VO 168 67 BA20 22 1 m ND VO 167 FOREN VO 43 VO 166 ORE VO 44006 VO 165 E 4 380 RISI VO 45 VO 164 4 VO 46006 GND VO 47 VO 162 19 162 055 330 R152 VO 49 160 7 4 1 VO 50 VO 159 ENG 5 VO 51 VO 158 D16 330 R153 GND voc P 4 fFIFORST lt 83 voc Gub CYENA 55 54 VO 155 5 x LED SMD gr n CUR 55 VO 55008 154 CYBIST 57 056 eo 57 vo 57 VO 152 eave 28 VO 58 VO 451 CYRDY 5 VOC VO_150 FHA 60 VO VO 149 abies 61 VO 6t VO 148 A lt e VO ce VO 147 VO 146 A FIFCO Yc H 1064 VO 145 A 2265 voc VO 144 BDSO PRG 98 1065 VO 143 VO 67 VO 142 BWRITE EP 88 GND BAS ERES 65 VO 140 BLWCFD FIFOs 20 vo 70 VO 139 BIACK m 72 7 vores BSYSRES RO L VO 72 VO 137 A EBEADY 74 9 73 VO 136
22. amp bit if bit break else if bit 21204 PROG_FPGA DIN_H set the DIN pin to PROG_FPGA CCLK_H assert one CCLK clock cycle PROG_FPGA CCLK_L else if bit 20204 PROG_FPGA DIN_L set the DIN pin to PROG_FPGA CCLK_H assert one CCLK clock cycle PROG_FPGA CCLK_L T for i 0 lt 15 i i 1 FPCA DIN B PROG_FPGA CCLK_H 16 more ones to the FPGA PROG_FPGA CCLK_L required to finish configuration check whether programming was successful DONE pin high printf nReading BOARD STATUS VALUE READ STATUSO VALUE amp 0 4000 7 1 0 printf DONE d n if a 1 printf nConfiguration cycle completed else printf nConfiguration cycle failed n n PROG_FPGA ENA_L disable programming pins exit 1 28 SUBROUTINES PROG_FPGA change state of FPGA s programming pins void PROG_FPGA unsigned long VALUE unsigned long ADDRESS ADDRESS 0xE0000000 0x00000088 BASE OFFSET unsigned long ADDRESS VALUE return READ STATUS check the status of the two pins INIT amp DONE unsigned long READ STATUS unsigned long ADDRESS DATUM ADDRESS 0 0000000 0x00000010 BASE OFFSET DATUM unsigned long ADDRESS return DATUM Wait a while void WAIT int i printf nWA
23. can be reprogrammed PROG and TEST can be used to program and debug the FPGA Table 7 shows the pin assignments The external signals USER1 to USERA and Test Pattern Strobe can be applied to the ECL connector The pinning is listed in Table 8 The test pattern output is an 80 pin Robinson Nugent connector This connector is used to transfer the TTL test pattern to the Pulser Box The 64 bit test pattern are transferred via lines 1200 to D63 Optionally lines D00 D11 can carry the 12 bit needed to set the DAC This information is loaded into the DAC with the differential signal DACSTR DOUTSTR is the second differential signal enabling the analog output of the Box Table 9 shows the pin allocation for the signals 3 3 Rear Panel Pin Assignments Tables 10 and 11 show the pin assignment for the VME signals used on the CATCHI board 3 4 Jumper Settings Five different clock speeds can be selected for the programmable logic devices on the CATCH1 board 8 and 17 MHz are derived from an exchangeable 33 MHz clock and 25 MHz are derived from an exchangeable 50 MHz clock These clocks can be individually selected for both chips by shorting the ap propriate jumpers JP4 FPGA and JP5 CPLD For the FPGA there is also a 80 MHz clock foreseen which can only be selected by the logic imple mentation in this device and is unused in the current design Figure 5 shows the location of the jumpers for clock selection on the board
24. data or READ SCALER command no error WRITE command expected READ SCALER expected WRITE PATTERN data word 1 2 or 3 expected WRITE PATTERN data word 4 expected unknown command 2 6 User Command Coding Unit The USER Command Coding Unit uses the 40 MHz clock to encode four different USER commands Trigger Reset Clear and User in terms of clock cycles before they are transmitted to the front end board via the S UTP cable The shortest signal is the Trigger with a length of one clock cycle 25 ns while the Reset the Clear and the User commands have lengths of 50 ns 75 ns and 100 ns respectively During normal operation the Test Pulse Controller sends an automatically generated trigger signal to the USER Command Coding Unit for each test pattern that was written to the Pulser Box Delay between Test Pattern Strobe and the trigger signal can be adjusted in multiples of 25 ns plus an offset of 975 ns in the Test Pulse Controller In case the automatic trigger generation is disabled the trigger signals can either come from the VMEbus or from the ECL input connector on the front panel These are the only possibilities to feed the other three USER commands and the pattern strobe into the The five ECL channels 13 o 2506 1 1 2 i 3 4 15 6 7 8 9 10 40 MHz Clock SERIAL OUT E E
25. the USER Command Coding Unit to send a trigger signal to the front end board for each Test Pattern Strobe that was received either via VME or from the front panel The latency is programmable t tp n 25 ns The offset is between 975 ns and 1000 ns The multiplier n can be selected in the range from 0 to 27 As will be explained in Chapter 2 6 the USER com mands arrive at the USER Command Coding Unit asynchronously Hence there is an uncertainty of 25 ns one 40 MHz clock cycle for the timing of the USER commands Five LEDs on the front panel indicate whether internal red or external green USER commands and Test Pattern Strobe will be used 11 With the PREPARE SCALERS command the user can do two things he can prepare a scaler for readout and he can select which scaler s he wants to clear Scalers can be prepared for readout and cleared at the same time but only after this command the scaler can be read out with READ SCALER Because these commands belong together they are treated as being one com mand in Table 3 Table 3 List of the commands for the Test Pulse Controller MODE BITS VALUE COMMAND 1 WRITE 118 016 00 SETUP TRIGGER D21 01 disable USER Command Cod ing Unit 026 022 00 1A delay between pattern and trig ger in multiples of 25 ns 1F disable automatic trigger D31 D27 1 enable external USER signals 0 disable external USER signals Test Pattern Strobe D31 User D30 Clear D29 Reset D28 and Trigger inp
26. 70 VO 139 VO 71 VO 138 VO 72 VO 137 VO 73 VO 136 VO 74 VO 135 VO 75 VO 134 VO 76 VO 133 VO 77 VO 132 GND VO 80 VO 129 VO 8t VO 128 VO 82 VO 127 VO 83 VO 126 VO 84 VO 125 VO 85 VO 124 TAALSTA VO 86 VO 123 VO 87 VO 122 8131 VO 88 VO 121 R132 1 Q g GND 907 0 89 VO 120 R133 3 Douraz 91 ND GND 5 SES 92 VO 91 118 R135 5 2 9 VO 9e VO 117 R136 x t D 54 0 93 VO 116 R137 5 0 94 115 R138 96 O 95 VO 114 113 DOUT26 8x 27k VO 96 VO 113 voc 97 112 DOUT27 VO 97 VO 112 98 v5 yo 111 Att Bouts 99 0 5 110 CLO amp 0M voc VO 99 VO 110 09 t voc 33 MHz 19 109 108 5 192 ND PROGRAM HSS OUT 103 nc nc Hos X DONE 103 106 voc 025 104 DONE VCC 105 nc Fakult t f r Physik Freiburg Braun Title Catch 1 FPGA Size Document Rev Number FPF 288 04 Date Bheet 4 Wednesday May 13 1998 D Figure 11 FPGA 34
27. COMPASS Note 1998 16 CATCHI Test facility for COMPASS Front End Electronics User Manual G Braun H Fischer J Franz A Gr nemaier F H Heinsius K K nigsmann M Schierloh T Schmidt H Schmitt J Urban Fakultat f r Physik Universitat Freiburg 79104 Freiburg Germany November 23 1998 Abstract 6U VME based printed circuit board for testing the functionality of the COMPASS front end electronics will be described The user can generate up to 64 independent test pulses to simulate pulses from a detector system The data produced from these artificial signals or from a real detector equipped with front end boards can be read out to a computer via the VMEbus Readout and control of the front end boards is done via a standard RJ 45 connector as used in COMPASS flexible design allows to create complex test setups Contents 1 Introduction 2 Functional Description 221 VME Interface lt xke Rex RT ee Me CC US 2 2 HOTLink serial receiver 2997 Buffet m Bee oe okt eo dis 2 4 Serial Transmitter 10 Mbit s 2 22 2 RR SERE 2 5 Test Pulse Controller 2 6 User Command Coding Unit 3 Board Layout 3 1 Front Panel Information 3 2 Front Panel Pin Assignment 3 3 Rear Panel Pin Assignments JA Jumper Seb bg gae qeu duc D dote eg dote ee 3 5 Rotar
28. D AM3 A19 19 D21 20 GND A18 20 D22 21 IACKIN A17 21 D23 22 IACKOUT 16 22 23 GND A15 23 D24 24 A07 14 24 D25 25 A06 A13 25 D26 26 A05 12 26 027 27 04 11 27 D28 28 A03 10 28 D29 29 02 09 29 D30 30 01 08 30 031 31 12 31 32 5 5 5 32 5 to the FPGA via the PROG connector on the front panel There is no need to change these settings during normal operation 3 5 Rotary Switches Two rotary switches adjust the base address of the board in the range of 0000000 to 96E000FF00 Switch SW2 selects the lower four bit and switch SW1 the upper four bit of the base address For the location on the board see Figure 5 20 VME J1 P1 Connector VME J2 P2 Connector Default JUMPER Settings CPLD FPGA 4 50 foe s 33MH 33 33 25 25 17 17 o8 os EXT INT EXT 50 MHz FPGA HOTLink O O Swi sw2 FIFO 80 MHz 40 MHz GAL GAL JP1 F2 F4 CPLD Rotary switches
29. Ds connectors and buttons 3 2 Front Panel Pin Assignment There are four connectors on the CATCHI front panel The uppermost is RJ 45 for the communication with the front end board via S UTP cable CAT 54 While the high speed data transfer via HOTLink PECL the USER commands LVDS and the 40 MHz clock are differential signals the serial setup data is generated as a single ended signal TTL However because an opto coupler will be used to receive this signal on the front end board the cable carries both lines to drive the LED of the opto coupler 6 RJ 45 Connector PIN SIGNAL NAME CON 2 Co 40 MHz Clock 40 MHz Clock 4 Serial Setup Data USER 1 4 4 USER 1 4 Serial Setup Data HOTLink Data HOTLink Data Signal Name USER 1 USER 2 USER 3 USER 4 PIN WwW gt OLD I Table 8 ECL Connector CPLD Voc GND n c TDO TDI TMS PIN 10 e 08 e 06 e 04 e Pattern Strobe 02 e 16 e 09 e 07 e 05 e 03 e 01 Pattern Strobe RD TRIGG TDI TCK TMS CLKI CLKO Table 7 Programming Connectors GND CCLK DONE DIN PROG INIT SOFTRES Signal Name USER 1 USER 2 USER 3 USER 4 FPF 288 PWR ERR CPLD SEG
30. ITING for i 0 i lt 500000 i i 1 printf return 29 C List of Sheets m 0557801 GN CORS Bo oooon 52 o 9 SOFTRES Dia 74BL5 amp 41 1 74045541 74845541 74015541 12 15 edF 151 7485541 2 usi 74045541 55 m 06 07 HE 1 5 n xm 0 1 n L 0932 ET
31. RES Si o gt gt PROG gt gt CPLDRES Fi 250mA Y gt voc PROG F2 250mA 5 0 P voc 9 ET 6 5 DONE 3 DIN 2 PROG 1 ANT SOFTRES FRT FRD 32 x 270 FTRIGG A01 B01 264 Hoz 01 B01 50 gt 865 FTOK MoS A02 021967 268 Faos A03 3541569 H70 Abe A04 B04 71 272 A05 805 505873 B74 A97 A06 Bo7 H75 B76 Mog A07 B07 Bog EZZ 278 apg A08 Bog H79 CTDO 280 Ho 09 gio P8l FB2 A10 B10 511 983 CTMS 445 11 11 12885 Magg A12 12 6151887 288 ATS A13 89 12 A14 814 151 91 He AIS 5 3 gt gt DOUTI 3 My A16 816 5 AT A17 B17 7 Fes Hajo 18 B18 H619 P99 R100 A20 A19 B19 B20 R101 R102 A20 B20 5518103 104852 A21 B21 85218105 R106 22 B22 82318107 R108 454 A23 B23 6271109 R110 Se A24 24 855 M 112 52 25 B25 5218113 R114 ASS A26 B26 BSS H115 De 116 2 A27 B27 pg RHIZ H118 455 A28 B28 39 8119 m loma R120 A30 A29 B29 B30 R121 R122 A30 B30 R123 A31 B31 90C031 R124 A31 B31 R125 A32 B32 2x270 8 126 355 A32 B32 83318127 1 4 A34 B33 634 Hi28 DO4 EN 1 A34 B34 R129 Dow EN A35 B35 A35 B35 A36 B36 1 A36 886 B37 1 A37 B37 A38 B38 A39 8 B38 gag 5 40 A39 B39 Bao Do2 A40 0 Doe 3
32. SER commands are applied at the same time the shorter output signal has priority For instance only the trigger signal will be encoded if both the trigger and the reset signal are applied to the coding unit However this should not be done via the VME command WRITE TRIG If necessary the trigger coding unit can be disabled from the Test Pulse Controller see Table 3 14 Table 5 Offset addresses of the commands COMMAND OFFSET DATA WORD READ ID 9600 D31 D00 CATCHI identifier READ FIFO 9608 D31 D00 three data words READ STATUS 10 D15 D07 status bits READ_FPGA 18 D31 D16 scaler values WRITE_SERIAL 40 D23 D00 setup data to front end WRITE FPGA 0648 D31 D16 pattern pulse height WRITE TRIG 50 D03 1 User command D02 1 Clear command D01 1 Reset command D00 1 Trigger command PROG FIFO 80 D31 D16 set FIFO flags PROG FPGA 0688 D07 D00 data transferred 01 enable programming pins 02 disable programming pins 04 set PROG pin to 0 08 set PROG pin to 1 10 set DIN pin to 1 20 set DIN pin to 0 40 set CCLK pin to 1 80 set CCLK pin to 0 REFRAME 98 D07 D00 01 enable reframing 02 disable reframing BISTEN 90 D07 D00 01 start built in self test 02 stop built in self test RESET FIFO 0 reset FIFO buffer RESET FPGA 8 reset Test Pulse Controller 15 3 Board Layout 3 1 Front Panel Information Figure 4 shows a sketch of the CATCHI front panel and a table describing the function of its LE
33. The default setting are 33 MHz for the CPLD as well as for the FPGA Besides the internal clocks on the an external one can be se lected for the FPGA This external clock is enabled with Jumper JP3 and can be taken from a PC Selecting external clocks should only be done for debugging the FPGA During normal operation the two INT pins are shorted with a jumper by default see Figure 5 The remaining two jumpers also serve debugging purposes If JP1 is shorted the user can send trigger signals via the TEST connector to the FPGA A shorted jumper JP2 allows soft reset signals to be sent from a PC 19 Table 10 VME J1 P1 Connector Table 11 J2 P2 Connector PIN ROW ROW ROW PIN ROW ROW ROW C C 1 D00 1 5 nc 2 101 09 2 GND 3 D02 010 3 4 D11 4 A24 n c 5 D04 D12 5 25 6 D05 013 6 A26 7 D06 D14 7 A2T 8 07 015 8 28 9 GND GND 9 29 10 BG3IN 10 A30 11 GND BG3OUT BERR 11 A31 12 DS1 SYSRESET 12 13 DS0 LWORD 13 5V nc 14 WRITE 5 14 D16 15 GND 23 15 017 16 DTACK AMO A22 16 D18 17 GND AMI A21 17 D19 18 AS AM2 A20 18 D20 19 GN
34. calers for the USER commands Chap ter 2 5 This for instance allows to keep track of the number of exter nal TRIGGER signals All functions of the CATCHI board as well as the readout of the front end data are controlled via the VMEbus Chapter 2 1 Additional connectors on the front panel allow to apply external signals as well In the experiment the VME interface will only be used to transfer data needed for initialization of the front end electronics and to collect data for slow control purposes The data from the front end side will be ordered by events on the CATCH module before being passed ahead to the on line filtering via a fast optical S Link IPULPO PULse and Pattern bOx 2 Functional Description The CATCHI is a one unit wide 60 VME slave module Its main features are a unit to control an external module for test pulse generation a USER Command Coding Unit one serial port to transmit data one to receive data HOTLink and VME interface logic See the block diagram Figure 2 for more details The Test Pulse Controller receives test pattern and four USER commands in the following referred to as Trigger Reset Clear User from the VMEbus This unit can apply 64 independent TTL test pulses to a connector 80 pins on the front panel of the CATCHI Via a flat cable the digital signals are transferred to an external device Pulser Box which converts them into analog signals The control signals for pulse height sele
35. ction and the test pulse duration are also transferred via this cable Moreover for the USER commands the Test Pulse Controller provides scalers which can be read out via the VMEbus 4 Flags FIFO 2 5 Direction 5 2 P 5 HOTLink 5 N n gt 4 8 VME Interface 6 Control 8 E aa Logic 8 9 Enable T 9 Setup Data Flags Serial 32 Data Transmitter a 5 4 5 Control 9 5 o 85 55 5 3 58 a a m Address 5 891 Decoder Xn 40 Address S p a aj 8 pest E 8 am 5 i 5 Rotary Switches 5 5 gt USER 1104 8 Test Pattern Strobe Test Pulse SRAM 5 Controller 32 kB E DAC Control 7841543 gt 6 64 Bit Test Pulse Pattern Tr or 12 Bit DAC Value V Figure 2 Block diagram of the 1 board The four different USER commands which can also be applied ECL level signals on the front panel are encoded into signals of different lengths by the User Command Coding Unit before being transmitted to the front end boards via one pair of wires on a S UTP cable Cat 5 The serial transmitter provides the possibility to transfer da
36. full bit 009 RVS pin is 1 if transmission errors occurred HOTLink this information is also included in the data stream here it is read out asynchronously bit 003 RDY pin is 0 if the HOTLink self test has finished bit 207 is 1 if the serial transmitter setup data is busy The FIFO buffer can be cleared with the command RESET FIFO It has the offset address 0 and causes an address only cycle which requires no data to be transferred The same applies to the command RESET FPGA with the offset address C8 This command clears all registers of the Test Pulse Controller and puts it in the initial state after configuration 2 2 HOTLink serial receiver The HOTLink is a high speed serial link On the CATCHI it runs with a 25 MHz exchangeable clock which is the reference for a phase locked loop PLL that generates the high speed transmission clock allowing the transmission taking place at 250 MHz Blocks of the incoming 10 bit coded data stream are decoded into words of one byte These can be either data characters or special characters For instance the special character K28 5 comma is a separator for the data words If the receiver decodes a K28 5 its internal free running bit counter is synchronously reset on the correct byte boundaries 8 data and command words are written into the FIFO with one ex ception If consecutive K28 5 characters are received only the first one is written into the FIFO For violations tra
37. n Appendix B Since the FPGA can be easily and quickly reconfigured it can perform quite different tasks For instance it could be used to read data into the CATCHI from the Robinson Nugent connector and thus use the FPGA for digitization For a detailed description of the XC4020E 2 see 1 4 3 Cypress CY7B933 HOTLink Receiver The HOTLink receives data from the transmitter on the front end side Both the transmitter and the receiver side must have a reference clock which must be within 0 1 to each other These clocks are exchangeable and can operate at different frequencies up to 33 MHz A detailed description of the HOTLink transmitter and receiver devices can be found in 2 4 4 251 15 JC FIFO This FIFO buffer is nine bit wide and 8 KByte deep It features empty almost empty almost full and full flags of which the almost empty full flags can be programmed The FIFO belongs to a family of pin compatible buffers and can be easily replaced in case a bigger memory is required A detailed description can be found in 3 4 5 Lattice GAL22V10C GAL The USER Command Coding Unit and part of the interface logic between HOTLink and FIFO buffer are each implemented in a GAL Generic Array Logic They are exchangeable and can be reprogrammed However these devices are not capable to hold as much logic as a CPLD For more details see 4 4 6 199 10 Memory This memory 36 KByte can be accessed via the FPGA but i
38. nsmission errors and special com mands the HOTLink has two bits that are combined by or into the ninth FIFO bit to identify corrupted data The command feature of the HOTLink is not used on the front end board To avoid erroneous framing on wrong byte boundaries the REFRAME command offset address 98 be used Certain data sequences can be taken for a special K28 5 character and could cause corrupted data When reframing is switched off the HOTLink receiver will not try to reframe the incoming serial data whenever it decodes such a special character Another command is BISTEN with the offset address 9690 With this command the receiver enters a built in self test state For a successful self test of the transmitter receiver system it is necessary to start the test function on the front end side too For example this could be done with the User command USERA 2 3 FIFO Buffer The FIFO buffer is nine bit wide and can hold up to 8 KByte of data It has four flags which indicate that it is full almost full almost empty or empty By default the almost full flag is asserted when the FIFO has space for up to seven more words On the other hand the almost empty flag is asserted when it contains seven or less words The user can alter the value at which a flag should be asserted with the PROG_FIFO command It has the offset address 9680 and transfers 32 bit of data into the FIFO s programmable flag registers These 32 bit are split into 4 bytes
39. o Li 20 s noc nd I 5 A nuu 90 031 m z 5 nmm 0 2 000 550 0 ae oo oo 2 ua ool 2 og H 5 D 5 5 D m a E p Ut 270 LE 270 BH 270 270 270 27 OF 6659249 ozn rio u35 7405541 27 4 E 5 gt a Li Ez Dx ids dL 5 E T SLUR 9 zl NL OD ng 5 3 raacsza ss i 7450572 3 52 Es 0000 0 0 0 8 2 i 5 5 2 08 Booo Hooo n o o o o o o o o o o o o o o o o
40. o o o o o o o o o o n o o 8 0320 0 0 0 0 0 0 00 0 0 0 0 0 0000 00 0 0 0 0 0 00 8320 0 0 0 0 0 0 0 00 0 0 00 00 00 00 0 00 00 00 0 320 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 00 0 0 0 0 0 0 0 0 hi 31 P1 UPPER 27 DROSSEL cse eo eo oo oo oo oo oo oo oo oo eo oo oo oo oo oo oo a8 JH _J2 P2_LOWER_CONN Figure 7 IC Placement 30
41. ommands 2 73 MHz Reading FIFO data 1 11 MHz Reading Board Status 1 20 MHz 5 3 Power Requirements Mechanical Size 5 V 1150 mA protected with a 3 A fuse F3 12 V 25 mA protected with a 250 mA fuse F4 5 V CPLD F1 and PROG F2 connectors each protected with a 250 fuse For the location of the fuses see Figure 5 The is a single width 60 VME module References 1 2 Xilinx The Programmable Logic Databook 1996 CYPRESS Semiconductor Corporation CY7B923 33 HOTLink Trans mitter Receiver Data Sheet CYPRESS Semiconductor Corporation CY7C42r1 8 9 Synchronous FIFO Data sheet Lattice Semiconductor Corporation Data Book 1994 e CYPRESS Semiconductor Corporation CY7C199 Memory Data sheet Analog Devices AD7845 D A Converter Data sheet 25 Getting started with the CATCH1 The consecutive steps necessary to run tests with the board are described in this Appendix 1 2 switch off the power of your crate select suitable base address es for your CATCHI board s plug in the board s connect the Pulser Box es and the front end electronics Switch power on again now change to directory where your software is installed run the configuration routine for the FPGA file containing the design required when the seven segment display shows a zero everything is ready if not use
42. pplied and the CCLK pin is a clock for the data Two more pins INIT and DONE can be read out with the READ STATUS command They indicate whether the configuration was finished successfully An example routine written in C language that config ures the Test Pulse Controller via VME is given in Appendix B The different words transferred with PROG_FPGA and their results are described below Data lines D08 to DOO 01 enable programming 02 disable programming via default 7604 set PROG pin to 0 7608 set PROG pin to 1 7610 set DIN pin to 1 7620 set DIN pin to 0 40 set CCLK pin to 1 80 set CCLK pin to 0 Once the controller is configured 16 bit of data can be either written to or read from the Test Pulse Controller Two commands WRITE FPGA with the offset address 48 and READ FPGA with the offset address 18 can be used for this data and command transfer via the VME data lines D31 to D16 The Test Pulse Controller knows five different commands which are en coded in the three least significant data lines D18 to D16 and its default mode is to wait for a command A list of all possible data transfers is given in Table 3 The first command is SETUP TRIGGER Here the user can write all the information to select the delay and the source of the trigger signals disable USER Command Coding Unit see Chapter2 6 prevents USER com mands from being sent to the front end board Automatic trigger generation causes
43. s not used in the current design For example test pattern could be stored here before being sent to the Pulser A detailed description of this device is available in 5 22 5 Electrical and Mechanical Specifications 5 1 Cables The three connectors for programming and debugging the CPLD and the FPGA require special Xilinx adapters These have to be connected to a PC and should not be used during normal operation The following list gives an overview of the cables for the other connectors on the front panel S UTP cable CAT5 shielded twisted pair Length lt 20m Wires 8 Twisted pair flat cable to Pulser Box Length lt 3m Wires 80 Twisted pair flat cable for ECL signals Length lt 3m Wires 10 5 2 Signal Characteristics Signals on the S UTP cable HOTLink data Differential PECL level max frequency 330 MHz the lines are terminated with 110 2 to and with 300 2 to GND USER commands Differential LVDS level Clock Serial setup data Differential LVDS level frequency 40 MHz TTL level frequency 10 MHz Serial setup data for driving the LED of an opto coupler Signals on the twisted pair cable 80 wires Data lines 000 63 TTL level DACSTR Differential LVDS level DOUTSTR Differential LVDS level remaining wires GND or not used Signals on the twisted pair cable 10 wires USER commands ECL level dynamically terminated with 100 Pattern Strobe
44. ta needed for initialization of the front end electronics This serial port runs at 10 Mbit s and transfers 24 bit of data on a second pair of wires on the S UTP cable with each transmission It cannot receive data and has no provision for error handling The third wire pair on the S UTP cable is used to transmit the 40MHz clock to the front end On the CATCHI this clock is used by the User Command Coding Unit and the serial transmitter Both components send their data synchronously to the clock Data generated on the front end boards are received by the HOTLink via the last pair of wires on the S UTP cable It operates at frequencies up to 330 MHz and monitors transmission errors Having arrived on the module the data are parallelized into words of 8 bit The data are stored in a FIFO buffer from where they can be read out to the VMEbus An additional bit indicating transmission errors is also stored in the FIFO buffer being nine bit wide 2 1 VME Interface The VME interface of the consists of an address decoder and a state machine address decoder monitors the VME address lines and passes a valid command to the state machine where the corresponding actions are carried out Table 1 lists the VME data transfer bus signals monitored by the CATCHI Table 1 VME data transfer bus signals Addressing Data Control A31 A01 031 000 AS AM5 AMO 50 DS0 DS1 DS1 WRITE LWORD BERR DTACK SYSRESET
45. the right configuration data 26 Example FPGA Configuration Here an example will be given to demonstrate how the logical design must be loaded on the FPGA via VME The design must be available in form of a file containing only binary or hexadecimal numbers Hexadecimal files generated from the Xilinx software have to be converted into binary ones Here it is important that each two hexadecimal numbers are swapped and their bits are reversed before they are written to the VME include lt stdio h gt void PROG_FPGA unsigned long VALUE unsigned long READ_STATUS void WAITO main int argc char argv 1 FILE input int i aj char bit unsigned long ENA H ENA_L PROG_H PROG L DIN DIN unsigned long BASE VALUE CCLK H CCLK some constants BASE 0 0000000 _ 0 00000001 ENA_L 0 00000002 PROG_L 0x00000004 PROG_H 0x00000008 DIN_H 0x00000010 DIN_L 0 00000020 CCLK_H 000000040 CCLK_L 0x00000080 PROG_FPGA ENA_H enable the programming pins reset FPGA with the PROG pin first low then high PROG_FPGA PROG_L PROG_FPGA PROG_H WAITO INIT pin is high now FPGA is ready for programming 27 printf nReading BOARD STATUS VALUE READ STATUSO VALUE amp 0 4000 7 1 0 printf INIT d n a reading the file containing the configuration data while feof input f fscanf input 4c
46. ut D27 2a WRITE 018 016 70 PREPARE SCALERS D26 D24 9600 9603 for Trigger Reset Clear User 7604 for Test Pattern Strobe D31 D27 01 1F clear scalers for pattern strobe D31 User D30 Clear D29 Reset 028 and Trigger D27 2b READ 131 016 READ SCALER 3 WRITE 118 016 02 SET DAC D31 D19 12 bit DAC setup value 4 WRITE D18 D16 03 WRITE PATTERN 4b D31 D16 16 bit test pattern 01 16 4 b 2 16 bit test pattern 17 32 4d 16 bit test pattern 33 48 4e 16 bit test pattern 49 64 WRITE 218 016 204 PATTERN STROBE The third command is SET DAC which programs the digital to analog converter on the Pulser Box After the command WRITE PATTERN the FPGA waits for another four data transfers which contain the 64 bit test 12 pattern for the front end When all 64 bit are received they can be sent to the Pulser Box with the completing command PATTERN STROBE This command executed without new test pattern information will transfer the most recent test pattern data to the Pulser Box The seven segment display on the front panel of the CATCHI shows the actual mode of the Test Pulse Controller and possible errors Once an error occurred its value stays on the display until reset or another error occurs list of all values is given in Table 4 Table 4 The 7 Segment display shows the status of the Test Pulse Controller Display STATUS configuration error not configured controller waits for more
47. y owitches 2 2 wok vx 4 Components on the Board 4 1 Xilinx XC95288 15 CPLD 4 2 Xilinx 4020 2 4 3 Cypress CY7B933 HOTLink AA CYTC4251 15 JO FIFOs 45 Lattice GAL22V10C 4 6 199 10 Memory 5 Electrical and Mechanical Specifications Bolo 63s e Te ug alex A gt ege e Pa 5 2 Signal Characteristics 4 score ceo EE 6 ex 5 3 Power Requirements Mechanical Size A Getting started with the CATCH1 B Example FPGA Configuration C List of Sheets 16 16 16 19 19 20 21 21 21 22 22 22 22 23 23 23 25 26 27 30 1 Introduction Experiments in modern high energy physics have a demand for higher pre cision and therefore feature an increasing number of readout channels of the detectors For the COMPASS experiment at CERN which is a fixed target spectrom eter allowing beam intensities up to 2 10 particles per spill new electronics for digitization and a new data acquisition system is being developed which can cope with the large data rates Once the new front end electronics reach the stage of mass production they will have to be tested thoroughly before being used in the experiment CATCH1 module is the ideal facility for testing purposes
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