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SIS3808 Deadtimed VME Multiscaler User Manual

1. LED selftest cete eie cre ete eti eie e e e let ie e er RI es 28 Page 3 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME IC Int rnal pulser tests eerte ee ete ettet e te td te ede Res 28 16 2 T Single Pulse eR IER UD M EE AERE ERN RT DTE 28 16 22 25 MHZ Puls r i eoo SURE UU Mr RB RS 28 163 Signal Input Priority 164 FIFO Test 17 Software tr EE OU 17 1 Contents of the included Floppy ENEE 30 18 Appendix QC T Ha 18 1 Address Modifier Overview 18 2 Front Panel Layout T e s E UC EE et ei ten Ce 18 4 Jumper and rotary switch locations ENEE 18 4 1 Addressing mode and base address selection ues 18 4 2 J500 Bootfile Selection and J520 SYSRESET Behawviourt sse nnns 34 I8 Board Layout ted RENTA RO PO UN EOD Ed e t uet ar PUR 18 6 Cascaded FIFOs a eed e m 18 7 FEASHPROM Netgen 18 8 Row d and z Pin Assignments 0 0 0 esesesessensecsnssessscsececoseesscseseeseusnsnssvsosssescesssaeseesesensnesvacssensesseserseseesenensnes 18 9 Geographical Address Pin Assignments eed es s 18 10 Additional Information on VME NEEN 19 ID dE LL Page4of 41 SIS Documentation SIS3808 SIS GmbH I Deadtimed Multiscaler VME 2 Introduction The SIS3808 deadtimed multiscaler is a special version of the SIS3801 multiscaler which is in return one of the members of the SIS360x 38xx VME board family It is a single width 4
2. 34 pin header Inputs flat cable versions DIN41651 34 Pin AMP e g LEMO Control and Input LEMO versions LEMO ERN 00 250 CTL Page 24 of 41 SIS Documentation SIS3808 SIS GmbH I Deadtimed Multiscaler VME 13 Control Input Modes The assignment of the control inputs can be controlled via the input mode bits in the control register While the standard SIS3808 firmware design design 3800 version 1 has inputs only design 3800 version 2 is compatible with board where control lines 5 to 8 are configured as outputs what is the case for SIS3801 multiscaler boards 13 1 Inputs Control Input Modes Mode 0 bit120 bit020 input 1 gt external next pulse input 2 gt external user bit 1 input 3 gt external user bit 2 input 4 reset Mode 1 bit120 bit0z1 input 1 gt external next pulse input 2 gt external user bit 1 input 3 gt disable counting input 4 reset Mode 2 bit1z1 bit0z0 input 1 gt external next pulse input 2 gt external user bit 1 input 3 gt external user bit 2 input 4 gt disable counting Mode 3 bitl 1 bit0z 1 input 4 gt external test 13 2 Outputs Four ouput signals are defined on the SIS3801 board They are copy in progress CIP FIFO empty FIFO half full and FIFO full ERROR Their assignments to the control lines are listed in the table below Control Signal 5 Testout CHO 6 FIFO almost full FIFO full C If deadtimed mode is enabled the deadtimed
3. oa Z J Z d GND Open Open Open Open Open Open Open Open ND GND Open GND pen GND GND OQ O O QG O 5 OJO 5 ooo SIS Oo ES O 18 10 Additional Information on VME The VME bus has become a popular platform for many realtime applications over the last decade Information on VME can be obtained in printed form via the web or from newsgroups Among the sources are the VMEbus handbook http www vita com the home page of the VME international trade association VITA and comp bus arch vmebus In addition you will find useful links on many high energy physics labs like CERN or FNAL ogseogsessseoss S Iolo ls S oos S lolos IS o5 c d QIQJO O Z Z S SSC Scc en Pin Pin Pin Pin Pin eebe ges 8 Iols lols o Gelee CIS 2 8 ols o e 5 oobis 8 Iols lols o Q SIS GmbH f VME Page 39 of 41 SIS Documentation SIS3808 SIS GmbH i Deadtimed Multiscaler VME 19 Index 24 bit mode dehet eee eds 18 25 MHz Pulser 28 25 MHz test pulses 16 32 bit mode 18 IA ULT tese boe oett te fee ded 33 VG EE 10 A2A 10 A24 Broadcast Example 19 AI 32 5 c sepe petet ntn 10 A32 Broadcast Example wld Address Map IA Address Modifier Overview address modifiers Address Spaces s ele geen reet dto decet eU 13 addressing
4. 41 SIS Documentation SIS3808 SIS GmbH I Deadtimed Multiscaler VME 10 Data Format Due to restrictions of the counter XILINX chips the channel depth of the SIS3808 is limited to 20 bits where the SIS3801 is available with a 24 bit and a 32 bit mode The data format of the actual data word is described below User Bit 1 User Bit 0 Bank number 0 1 Channel number Bit 4 Channel number Bit 3 Channel number Bit 2 Channel number Bit 1 Channel number Bit 0 es high Byte Den Byte lowBye O use TUR OTBTGRTGSTCRTCT TOV Bits 23 20 read as 0 Data Bis 1 16 Data Bits 15 8 10 1 2 D32 read as 0 19 16 15 8 7 0 Page 21 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 11 Input Configuration SIS36 38xx boards are available for NIM TTL and ECL input levels and in LEMO and flat cable versions The boards are factory configured for the specified input level and connector type input termination is installed 11 1 ECL The 100 Q input termination can be removed in groups of four channels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel NI 1 4 RNII 12 RN20 5 8 RN21 22 RN31 32 RN41 41 1 K Networks 1 4 5 8 RN51 52 RN61 62 RN71 72 RN81 82 RN111 RN112 RN120 Control 5 8 RNI2I RNI22 The schematics of th
5. TE 6U double euro form factor card and the firmware was designed for the requirements arising in conjunction with the use of large PMT tubes with afterpulsing behaviour Le the unit was designed in a fashion that the individual channel has a deadtime which has to elapse before new counts are recognised by the channel after a counted pulse The programmed deadtime value is common to all channels but the deadtime counter or deadtime interval is applied to the individual counter This document was written with the focus on the user of the unit who wants to integrate the board into a data acquisition system and interested parties who consider the module for future use in their setup and would like to get an overview on the designs capabilities The SIS360x 38xx card is a flexible concept to implement a variety of latch and counter firmware designs The flexibility is based on two to six Xilinx FPGAs in conjunction with a FLASHPROM from which the firmware files are loaded into the FPGAs Depending on the stuffing options of the printed circuit board the user has the possibility to cover several purposes with the same card hence the manual is a combination of firmware and hardware description All cards of the family are equipped with the 5 row VME64x VME connectors a side cover and EMC front panel as well as the VIPA LED set For users with VME64xP subracks VIPA extractor handles can be installed The base board is prepared for VIPA style addre
6. of channel 1 and 3 are not copied into the FIFO 76 FIFO 0x100 0x1FC The FIFO can be accessed from addresses 0x100 through Ox1FC to facilitate the readout with different types of CPUs For masters with block transfer capability without address increment its most convenient to read all data from address 0x100 For masters with block transfer address auto increment it is straightforward to set up repeated block reads with a length of 256 Bytes the maximum VME block transfer size from address 0x100 and the autoincrement uses the addresses 0x100 through Ox1FC for the transfer If FIFO test mode is enabled data can be written to the FIFOs addresses Page 18 of 41 SIS Documentation SIS3808 SIS GmbH I Deadtimed Multiscaler VME 8 Broadcast Addressing Broadcast addressing is an efficient way to issue the same command to a number of modules It can be used in A24 and A32 mode on SIS360x 38xx boards The higher address bits are used to define the broadcast class the distinction of the modules is done via the A16 rotary switch and the A 11 jumper If broadcast addressing is used the A32 U the A 32 L the A24 U and the A24 L rotary switches must have the same setting in A32 mode in A24 mode the A24 U and A24 L setting must be the same on all participating units One of the participating units must be configured as broadcast handshake controller by setting bit 7 in the units control register All of the participating units must have set bit 6 e
7. 808 SIS GmbH 4 Deadtimed Multiscaler VME 9 VME Interrupts Four VME interrupt sources are implemented in the SIS3808 firmware design e start of CIP e FIFO half full e FIFO almost full e FIFO full error condition The interrupter is of type D8 O The interrupt logic is shown below For VME interrupt generation the corresponding interrupt source has to be enabled by setting the respective bit in the VME control register disabling is done with the sources J K bit Interrupt generation has to be enabled by setting bit 11 in the IRQ and version register The internal VME interrupt flag can be used to check on an IRQ condition without actually making use of interrupts on the bus The VME interrupt level 1 7 is defined by bits 8 through 10 and the VME interrupt vector 0 255 by bits 0 through 7 of the VME IRQ and version register In general an interrupt condition is cleared by disabling the corresponding interrupt clearing the interrupt condition i e clear overflow and enabling the IRQ again Note In most cases your experiment may not require interrupt driven scaler readout but the interrupt capability of the SIS3808 provides a way to overcome the problem of missing front panel inputs on most commercial VME CPUs VME_IRQ_ENABLE VME IRQ Source 1 INTERNAL_VME_IRQ Source 2 Source 3 Note The FIFO Half Full and Almost Full flags have different meaning on 256 K FIFO units see section 18 6 Page 20 of
8. ATG A24 A32 gege eege EE 33 addressing mode As Addressing mode 33 addressing modes eene 13 Adressing Gs Bank number 21 B se address eege EE 10 Base Address BED eteeenercpitun udo i reines Board Layout eerte RE Boot File Selection d Bootfil Select n aee eerte en Broadcast Addressing see 19 broadcast handshake controller 19 broadcast mode 16 broadcast mode handshake controller 16 broadcast time jitter sss 19 CBLT Al CERN E 39 CIPRO ERES RE SES 8 15 25 Connector Specification eese 24 Control and Status register i Control Input meter ent ER 33 Control Input Modes eee 25 Control Register au Gooling mere EAE dE copy disable register essere 8 Copy disable register CODy iil DIOSTeSS ee ge istis oie ced 8 Count Ernabl ertt eee 9 project file 30 D08 O acl Data Format 421 IERT EE 33 deadtime Page 40 of 41 EE LEE 10 BN ET ierra reae been 13 33 En A24 i tere Ree 10 EN A D4 vss etre edite aet 13 33 IEE E AEA EE ESAT eie e e 10 EN ee EA 13 33 Factory Default Settings sse 10 FIFO iia 6 18 almost empty cone ete dene oe EO ce cascaded full 2 half full half full flag test mode e c etse ael e ete eene teet een firmware design essent Firmware Design
9. Firmware Selecton essen 11 Lee EE Examples EFLASHPROM nione it ig e 5 6 11 FLASHPROM Version 36 Front Panel Layout 32 GAO GAI GA2 GA3 GA4 geographical address PINS he M Geographical Address geographical addressing Getting Started ied dae hots EE http LIN WN WACOM iip oot puerto Input Configuration INPUt MOE P a Tipt Priority socere esie Rer eet te ees input test mode Insertion Removal ertet s interrupt acknowledge cycle sess 17 interrupt condition 20 interrupt control sel interrupt level rte etn 17 20 interrupt lOfiC erne eter t ns 20 interrupt Vecto er tne terit 17 20 interruptertyDe o set ete tie tet exe 17 IRQ SOUICE esae e RO RR 16 TAA WE tete ete bes tee eines 13 33 AKON EEA RI 33 A E D EEA EE O E EET EOE 33 T5005 cs date orat eh e etae 10 33 34 JS ees Ade ee Ee 10 33 34 jumper firmware selection ete Hee 11 VME addressing mode 13 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME Jumper SW ZA A32LI echt ree orte et coh 10 13 OVERVIEW an een beer bere Det ern de eo et els 33 SW A32U stes its bee isa em Seelen des 10 13 Jumper and rotary switch locations 2 33 SYSRESET Behaviour 34 key address niece JA System Reset wold EED ireren 412 Technical Properties Features eee 6 ACCESS 12 TED
10. Ox00C f W DI6D32 Copy disable register __ __ 0x010 D16 D32 Write to FIFO in FIFO test mode Do EX 7W DISD32 dear FIFO logic and counter Test pulse generate a single pulse 0x100 RW DI6 D32 read FIFO Ox1FC BLT32 Note D08 is not supported by the SIS38xx boards The shorthand KA stands for key address Write access with arbitrary data to a key address initiates the specified function Page 14 of 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME 7 Register Description 7 1 Status Register 0x0 The status register reflects the current settings of most of the SIS3808 parameters in read access in write access it functions as the control register Bit Status VME IRQ source 3 FIFO full Status VME IRQ source 1 FIFO almost empty Status VME IRQ source 0 start of CIP VME IRQ internal VME IRQ Status VME IRQ Enable Bit Source 3 S O Status VME IRQ Enable Bit Source 2 Status VME IRQ Enable Bit Source 1 Status VME IRQ Enable Bit Source 0 19 i 14 DEES 8 LEO flag almost emp 8ST FIFO flag empty CCC 7 Status broadcast mode handshake controller 6 Status broadcast mode o O 2 Status input mode bt Status input mode bit 0 Status VME IRQ Enable Bit Source 3 2 Status FIFO test mode o Status user LED The reading of the status register after power up or key reset is 0x300 0x100 on units with 256 K FIFO see default settings of control register Not
11. SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME SIS3808 Deadtimed VME Multiscaler User Manual SIS GmbH Moorhof 2d 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info struck de http www struck de Version 1 1 as of 10 12 98 Page of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME Page 2 of 41 SIS Documentation SIS3808 SIS GmbH I Deadtimed Multiscaler VME 1 Table of contents I Tabhleatemntemts geeiert eee co coo ec eo eene o e e eo ne e ee eec a eee eee eeu eo a ce c eoe o ea vo aen ee oae vo c SR Vu d Oe Uer EE 6 3 Technical Properties Feat res 44er ee eee neenon eo een aane ro YE ER Y YR Pu 3 ERR FY PU ior aU ar er E e nee 3 1 Board Eayout EE 312 Counter Design and Modus Operandi 3 3 Minimum D well Title aene t rem he eise 3 4 Readout Considerations ege deed titer tet pe ede Yee stvsonceghaveedivsnncoucaresbsstscnsoseserspesdevieteed 3 5 Count Enable uge sik no o ERROREM oe need een A CCRC E a E eerte LL 4 1 Factory Default Settings 4 1 1 EUNTEM 4 1 2 System Reset Behaviour ipren tee EUER RE EHE REED EE 10 5 Firmware ENN 5 1 Examples erae beu Een uoo n Lu AM EL M T 11 Front Panel RE 12 6 AMET DARET TIT TULIT LO 6 1 Address Space s eere teta i RR dre o et e e I o tate ode 6 2 B sezAddr 8 5n eta tree mete e RR irt 62 1 KA EE 6 2 2 VIPA VME64x 6 3 Address EE 7 Register Descriptio E E 7 1 S
12. VME IRQ ACK cycle 6 read write IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 5 read write IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle 4 read wrte IRQ Vector Bit 4 placed on D4 during VME IRQ ACK cycle E 00 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle IRQ Vector Bit 2 placed on D2 during VME IRQ ACK cycle HL Jesse IRQ Vector Bit 1 placed on D1 during VME IRQ ACK cycle IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle The second function of the register is interrupt control The interrupter type of the SIS3808 is D08 O Via bits 0 7 of the module identifier and interrupt control register you can define the interrupt vector which is placed on the VME bus during the interrupt acknowledge cycle Bits 8 through 10 define the VME interrupt level bit 11 is used to enable bit set to 1 or disable bit set to 0 interrupting Module identification and version example The register for a SIS3801 in straight 32 bit mode version 1 reads 0x3801Innn for a SIS3801 in 24 bit mode version 2 it reads 0x38012nnn the status of the lower 3 nibbles is denoted with n in the example Page 17 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 74 Deadtime register 0x8 The deadtime register is used to program the number of deadtime steps and the deadtime step width The number of deadtime steps is in the range of 0 to 63 i e 7 bits t
13. aged the readout time is reduced to 50 ns 16 bit word in such a design the FIFO is of 18 bit synchronous type Page 8of 41 SIS Documentation SIS3808 SIS GmbH I Deadtimed Multiscaler VME 3 4 Readout Considerations One of the major advantages of a FIFO based counter multiscaler is the decoupling of the time slice bank switching and the actual VME readout of the data Depending on the application the FIFO may be used to buffer one or two reads only before a DSP processes the data on the fly in this case the FIFO is used to establish readout pipelining in other cases the maximum possible FIFO size is of interest to store a complete set of data points for a pulsed or non continuous measurement Continuous multiscaling can be established as long as the VME master can cope with the amount of data generated by the scaler i e the FIFO is never allowed to run into the FIFO full condition The 64K default FIFO size of the SIS3808 is considered to be a save value for most applications for more demanding applications the FIFO size can be increased to 256K One as to keep in mind that two FIFO words are needed to hold one 32 bit scaler value i e a 64K FIFO can hold 32K scaler words or 1K events time slices with all 32 channels enabled The packing of the FIFO data into VME D32 words is handled without user intervention upon VME read cycles from the FIFO In high data rate applications the readout scheme will make use of the FIFO half full flag or th
14. ared the user can read a minimum of 64K 128 16 bit words from the FIFO in a block transfer and has the guarantee that he can store an additional28 K 256 words before running into overflow 18 7 FLASHPROM Versions A list of available FLASHPROMSs can be obtained from http www struck de sis3638firm htm Please note that a special hardware configuration may be necessary for the firmware design of interest the SIS3808 design requires the installation of a FIFO e g The table on the web is of the format shown below Page 36 of 41 SIS Documentation SIS3808 SIS GmbH A Deadtimed Multiscaler VME SIS36 38xx FLASHPROM table the table given below contains only part of the available designs the up to date full list has to be retrieved from our web site Boot File s SIS3800 201098 O SIS3800 Version SIS3801 201098 0 SIS3800 Version 1 SIS3803 280798 O SISS803 Version SIS3808 231098 0 SIS3808 Version 1 SIS3801 Version 1 peer 2 SIS3801 Version 2 3 SIS3800 Version 2 Page 37 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 18 8 Row d and z Pin Assignments The SIS3801 is prepared for the use with VME64x and VME64xP backplanes Foreseen features include geographical addressing and live insertion hot swap The prepared pins on the d and z rows of the P1 and P2 connectors are listed below Rowz ME GND GND Eg Oooo DE N Ro
15. e The FIFO Half Full and Almost Full flags have different meaning on 256 K FIFO units see section 18 6 Page 15 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 72 Control Register 0x0 The control register is in charge of the control of most of the basic properties of the SIS3808 board in write access It is implemented via a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which has a different location within the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time On read access the same register represents the status register disable IRQ source 3 disable IRQ source 2 disable IRQ source 1 s disable IRQ source 0 clear software disable counting bit EE 73 disable external clear C9 Se Dronas aki mode handshake controller 9 disable FIFO test mode S O 8 switch off user LED 6 Lembie broadcastmode S enable input test mode 5 enable input test mode o O 3 set input mode bit 1 enable FIFO test mode S 0 switchon user LED S denotes the default power up or key reset state Page 160f 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME 7 3 Module Identification and IRQ control register 0x4 This register has two basic functions The fi
16. e ECL input circuitry is shown below GND SIL RN 1 X1 SIL RN 1 XO SIL RN 1 X2 Page 22 of 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME 11 2 NIM The 50 Q input termination can be removed in groups of four channels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel U15 Pins 10 to 6 U15 Pins 1 to 5 13 16 U75 Pins 10 to 6 25 28 U115 Pins 1 to 5 Control 5 8 The schematics of the NIM input circuitry is shown below GND DEL Y Ref 0 35 V Page 23 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 11 3 TTL The TTL input level option is possible with LEMO and flat cable connectors 11 3 1 TTL LEMO The low active TTL LEMO input circuitry is sketched below A high active version can be implemented by replacing the 74F245 with a 74F640 5V m E 1K 245 11 3 2 TTL Flat Cable In the flat cable TTL version the positive right hand side of the connector is tied to ground NE 3 1K EE 245 12 Connector Specification The four different types of front panel and VME connectors used on the SIS360x and SIS38xx boards are Connector Purpose Part Number 160 pin zabcd VME P1 P2 Harting 02 01 160 2101 20 pin header Control flat cable versions DIN41651 20 Pin AMP e g
17. e FIFO almost empty flag in the cascaded FIFO case see section 18 6 via a VME interrupt or polling in most cases as a minimum known number of 32K longwords or 32 K 128 in the cascaded case can be read out being blocked into smaller chunks by VME with a block transfer Example Assume 32 channels are read out with a dwell time of 10 us i e at a rate of 100 KHz The data rate is 32 channels x 4 bytes x 100 KHz corresponding to some 12 MB s The FIFO half full interrupt or flag will be asserted for the first time after 0 5 ms of data acquisition the VME master has to digest 64Kbytes within less than 0 5 ms including IRQ handling or polling to prevent the FIFO from overflow Note No new data can be acquired before a FIFO reset if the FIFO full condition has occurred i e the FIFO full condition is considered an error condition which should not occur in standard operation 3 5 Count Enable Logic A channel acquires input or test counts if the count enable and the global count enable conditions are true Via the test enable toggle bits in the control register the input of the counter is switched to test pulses or front panel signals Enable Scaler Scaler Channel N gt Count Enabl Control Input Disab 25 MHz reference channel 1 only Input N 25 MHz test pulse Single Test Pulse External Test Pulse Page 9 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 4 Getting Started The minimum s
18. e teer eh deseas 24 Color 12 User Bit 26 Power v2 User Bit 1 Ak Ready 12 version number 17 USeT 10 MIPA erinin ed Live insertion e ER te PR Ree 27 38 addressing oos ee hee eR MAE aye eet 5 Module Identification and IRQ control register 14 17 base address WK module number PUE extractor handles eee 5 monostable a2 LED SEU ster tenendo eed S EUN 5 INIM E eere 5 23 VIDA ponto e 39 Operating conditions Su MME t deett eI EE AA E e 27 39 OR VEG incense 1 30 addressing mode esee 13 1 ge e e MR Ls Ei Cot iced 6 Base Adress eder ee tere ERES 13 POUDE reete ete fete rre ete e th Power Consumption eere Readout Considerations Ee SWOR arrena ter ee e hee ee E Signal Specification sene Control SW A24L SW A24U VME addressing E VME control register of VME interTupt some rem me pe RO VME Intert pts eerte ee PERS VME IRQ and version register VME O4X EE CONECTO nc Sequere npe VME64xP Voltage requirement eese VxWorks Page 41 of 41
19. er Receiver Counter File Level Adaption XILINX Selection Driver Receiver Level Adapti Driver Receiver Counter Level Adaption XILINX Driver Receiver Level Adapti Driver Receiver Counter Level Adaption XILINX Driver Receiver SIS3808 Block Diagram 3 2 Counter Design and Modus Operandi The counters are implemented in XILINX FPGAs One of the counter FPGAs holds 8 20 bit deep counter channels Two counter banks are implemented the actual multiscaling mechanism is implemented as bank switching between the two counter banks and copying the data of the inactive bank to the FIFO Bank switching can be initiated via an external pulse or a VME command A sketch of the bank mechanism can be found below In nuclear physics one refers to the time slice length i e the period during which counts are acquired into the same bank as dwell time In many cases the dwell time will be constant but the user is free to use varying time intervals as long as the minimum time between two next event pulses is smaller than the minimum dwell time with the given number of active channels An approach to measure the length of the time slices is the readout of a fixed frequency clock on one of the counter channels the accuracy of the measurement is defined by the frequency stability of the clock and the interval length If deadtime mode is enabled the individual counters are preloaded with a deadtime count As soon as a channel acquires one co
20. ests 16 2 1 Single Pulse A single pulse into all channels can be generated with a write to the key address 0x68 if test mode is enabled via the control register In conjunction with the count enable register more complex count patterns like increment patterns e g can be generated before readout 16 2 2 25 MHz Pulser Simultaneous pulsing at 25 MHz into all channels can be used to test the complete readout chain and internal counter logic of the SIS3808 The feature is activated by enabling input test mode and 25 MHz test pulses via the corresponding bits in the control register The 25 MHz test pulser gives easy access to your VME CPUs readout timing By making subsequent reads to the same counter and multiplying the difference in counts with 40 ns you can measure the single word access time 16 3 Signal Input Priority If the user happens to enable more than one input option enable test mode enable reference pulser scaler enable at the same time the priority is as show in the table below Front Panel Inputs Example If test mode and front panel pulses are enabled at the same time the channels will count test pulses Page 28 of 41 SIS Documentation SIS3808 SIS GmbH I Deadtimed Multiscaler VME 16 4 FIFO Test FIFO tests via the VME bus are helpful to debug the FIFO on the SIS38xx in case of spurious data and to debug an overall VME system with driver problems on the CPU side or flaky VME termination e g In FIFO test mode t
21. etup to operate the SIS3808 requires the following steps e Check the proper firmware design is selected should be design zero i e all jumpers of jumper array J500 set Select the VME base address for the desired addressing mode Select the VME SYSRESET behaviour via J520 turn the VME crate power off install the scaler in the VME crate connect your signals to the counter turn crate power back on e issue a key reset by writing to 0x60 issue FIFO clear by writing to 0x20 enable next logic by writing to 0x28 issue first next clock pulse to start counting by soft or hardware after one or more subsequent next clock pulses data can be read from the FIFO from the addresses 0x100 through Ox1FC Note Issuing a FIFO clear is essential on units with 256 K FIFO to synchronise the cascaded FIFO chips A good way of checking first time communication with the SIS3808 consists of switching on the user LED by a write to the control register at offset address OxO with data word Ox1 the LED can be switched back off by writing 0x100 to the control register 4 1 Factory Default Settings 4 1 1 Adressing SIS3808 boards are shipped with the En A32 the En A24 and the En A16 jumpers installed and the rotary switches set to ECCUCHNS RE TN MUN WEN MEE OU EE RC SN ERE NI Jumper A 11 is open bit 11 set Hence the unit will respond to the following base addresses 0x38383800 0x383800 0x380 Firmware Design File 0 SIS3808 Versi
22. g below you can find the flat cable left hand side and Lemo front panel layouts Note Only the aluminium portion without the extractor handle mounting fixtures is shown NWA ORIG CONTROL 1 0 51536 38xx Page 32 of 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME 18 3 List of Jumpers Find below a list of the jumpers and jumper arrays 18 4 Jumper and rotary switch locations 18 4 1 Addressing mode and base address selection The EN_A32 EN_A24 EN_A16 A_11 and the 5 rotary switches are located int the middle of the upper section of the board close to the DC DC converter the corresponding section of the PCB is shown below in 4 Ps o dag Seed a ladajo o o o o o o o Glo 0 9 9 0 9 9 9 7 t E 35 ooon SU_AS2U Sl 32L SH A24U SL A24 Su AMS aa a og o g8 ou o u gt Ku o INE oo o o o m oooo o oo o o oo o o o dl EX i olola u200 Rh 23 S g mis N o SS z LCA 3190 Dien S WR Page 33 of 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME 18 4 2 J500 Bootfile Selection and J520 SYSRESET Behaviour The jumper array J500 is located between the P1 and the P2 connector An open position in J500 defines a one see also chapter 4 the lowest bit is next to the P2 connector J520 is located to the left of J500 and closer to the DC DC converter With jumper J520 closed the SIS3801 executes a key reset upon the VME SYSRESET signal The section of the board wi
23. he step width can be set to 120 ns 240 ns 480 ns or 960 ns The actual deadtime is define by the number of steps plus one times the selected step width A worst case jitter of 40 ns to 320 ns depending on the width see table below to the positive side has to be taken into account Example If the number of deadtime steps is preset to 9 and 120 ns step width are selected the deadtime is 9 1 x 120 ns 0 ns 40 ns i e between 1200 ns and 1240 ns Bit assignment of the deadtime register Bits 31 10 Bits 9 8 deadtime step width number of deadtime steps Deadtime step width settings Bit9 Bit 8 o fo o 1 j240m 0 80ns a 1 O 480ns 0 160ns Note If the deadtime setting is to be changed following steps have to be performed e disable deadtime via control register program new deadtime settings e enable deadtime via control register 7 5 Copy disable register OxC The copy disable register can be used to exclude single channels or arbitrary groups of channels The value from the copy disable register is used from the following next pulse on i e the user has the possibility to change the readout pattern in a dynamic fashion In the current implementation the copy in progress time is not depending on the number of active channels it was measured to be 3 8 us If bit N of the register is set channel N 1 is excluded from the copy process Example If 0x5 is written to the copy disable register the data
24. he user can write defined data into the units FIFO via the VME bus and to compare them wit the read back result FIFO test mode is enabled by setting bit one of the control register and disabled by setting bit 9 of the control register With FIFO test mode enabled data can be written to the FIFO at the address offset 0x100 through Ox 1FC Writing to the location with FIFO mode Page 29 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 17 Software Support VME multiscaler boards are tested at SIS with an OR VP6 VME CPU Pentium II based under Windows 95 and a National Instruments CVI user interface The actual VME C code makes use of the OR Windows 95 DLL which has straightforward to read and understand routines like VMEA24StdWriteWord a32address KEY RESET 0x0 Key Reset rdata VMEA24StdReadWord a32address STAT REG In most cases the user setup will be using different hardware a full fleshed real time operating system like VxWorks and a different user interface We still believe that it is helpful to have a look at the code which is used to test the units and to take it as an example for the implementation of the actual scaler readout application A floppy with our test software is enclosed with SIS3808 shipments Depending on the user feedback and co operation we expect that we will have drivers or at least example routines for the commonly used VME CPU operating systems a
25. nable broadcast in the control register The broadcast time jitter was measured to be less than 40 ns within a VME crate i e you have the possibility issue commands under software control with a maximum uncertainty of 40 ns like clear all counters what sure is worse than a hard wired front panel clear but is much better than a VME single cycle loop over a number of units The four broadcast commands are executed via the VME key addresses at offset 0x030 through Ox3C A32 Broadcast Example Let four SIS3801 participate by setting the A_32 jumper and setting the base address of the units to Unit 1 0x32001000 Unit 2 0x32001800 Unit 3 0x32002000 Unit 4 0x32002800 Switch on enable broadcast by setting bit 6 in the control register of the four units Enable broadcast handshake controller on unit 4 by setting bit 7 of its control register An A232 write to address 0x32000034 will issue one software next clock on units through 4 A24 Broadcast Example Let three SIS3801 participate by setting the A 24 jumper and setting the base address of the units to Unit 1 0x541000 Unit 2 0x542000 Unit 3 0x543000 Switch on enable broadcast by setting bit 6 in the control register of the three units Enable broadcast handshake controller on unit 1 by setting bit 7 of its control register An A24 write to address 0x540030 will clear the counters FIFOs and the logic on units 1 through 3 Page 19 of 41 SIS Documentation SIS3
26. on 1 of the FLASHPROM is selected all jumpers of jumper array J500 closed 4 1 2 System Reset Behaviour J520 is set ie the SIS3808 is reset upon VME reset Page 10 of 41 SIS Documentation SIS3808 SIS GmbH I Deadtimed Multiscaler VME 5 Firmware Selection The FLASH PROM of a SIS360x 38xx board can contain several boot files A list of available FLASHPROM versions can be found on our web site http www struck de in the manuals page If your FLASHPROM has more than one firmware design you can select the desired firmware via the firmware selection jumper array J500 You have to make sure that the input output configuration and FIFO configuration of your board are in compliance with the requirements of the selected firmware design a base board without FIFO can not be operated as multi channel scaler e g A total of 8 boot files from the FLASHPROM can be selected via the three bits of the jumper array The array is located towards the rear of the card between the VME P1 and P2 connectors The lowest bit sits towards the bottom of the card a closed jumper represents a zero an open jumper a one 5 1 Examples The figures below show jumper array 500 with the soldering side of the board facing the user and the VME connectors pointing to the right hand side Bootfile O selected With all jumpers closed boot file 0 is selected Bootfile 3 selected With the lowest two jumpers open bit 0 and bit 1 are set to 1 and hence boot file 3 is
27. r driver and receiver chips to allow for the use of the module in all 6U VME environments The power consumption is counting rate dependent it varies from the idle value of 5 V 3 3 A to 5 V 4 5 A with all channels counting at 200 MHz i e the power consumption is lt 23 W 15 2 Cooling Forced air flow is required for the operation of the SIS3808 board 15 3 Insertion Removal Please note that the VME standard does not support live insertion hot swap Hence crate power has to be turned off for installation and removal of SIS3808 scalers The leading pins on the SIS3808 VME64x VME connectors and connected on board circuitry are designed for hot swap in conjunction with a VME64x backplane a VME64x backplane can be recognised by the 5 row VME connectors while the standard VME backplane has three row connectors only Page 27 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 16 Test The SIS380x scaler series provides the user with a number of test features which allow for debugging of the unit as well as for overall system setups 16 1 LED selftest During power up self test and LCA configuration all LEDs except the Ready R LED are on After the initialisation phase is completed all LEDs except the Ready R LED and the Power P have to go off Differing behaviour indicates either a problem with the download of the firmware boot file or one or more LCA and or the download logic 16 2 Internal pulser t
28. rst is to give information on the active firmware design This function is implemented via the read only upper 20 bits of the register Bits 16 31 hold the four digits of the SIS module number like 3808 or 3600 e g bits 12 15 hold the version number The version number allows a distinction between different implementations of the same module number the SIS3801 for example has the 24 bit mode with user bits and the straight 32 bit mode as versions Module Identification Bit Module Identification Bit15 30 read only Module Identification Bit l4 Module Id Digit 3 29 readonly Module Identification Bit 13 28 readonly Module Identification Bit12 27 l Readonly Module Identification Bit I1 Identification Bit 11 26 readonly Module Identification Bit 10 Module Id Digit 2 25 readonly Module Identification Bit9 E Module Identification Bit 7 5 read only Module Identification Bite Module Id Digit 1 21 readonly Module Identification BitS 20 readonly Module Identification Bit4 Module Identification BES Identification Bit 3 D readonly Module Identification Bit2 Module Id Digit 0 17 readonly Module Identification Bn 5 readonly Version D 14 Do sss i E read write is D o readisrie VMEIRO Level Bi I 8 read write VMEIRQLevelBitO U O IRQ Vector Bit t placed on D7 during
29. s settable via 5 rotary switches A32 A12 and one jumper A11 VME interrupt capability VIPA geographical addressing prepared VIPA LED set channel based deadtime 0 63 deadtime steps 120 240 480 and 960 ns deadtime step length 3 8 us minimum dwell time with all channels active 2 external user bits Up to eight firmware files single supply 5 V 3 1 Board Layout Xilinx FPGAs are the working horses of the SIS360x 38xx board series The counter prescaler latch logic is implemented in one to four chips each chip handles eight front end channels The VME interface and the input and output control logic reside in two Xilinx chips also The actual firmware is loaded into the FPGAs upon power up from a FLASHPROM under jumper control The user can select among up to eight different boot files by the means of a 3 bit jumper array The counter inputs the control inputs and the outputs can be factory configured for ECL NIM and TTL levels The front panel is available as flat cable ECL and TTL or LEMO NIM and TTL version The board layout is illustrated with the block diagram below Page 6 of 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME Level Adaption C Driver Receiver 4 Tam Level Adaption I Driver Receiver 7 GC Control Ee Interface XILINX Level Adapti Driver Receiver Counter Adapti r Receiver Level Drive Level Adapti Driv
30. selected Page 11 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME Front Panel LEDs The SIS3808 has 8 front panel LEDs to visualise part of the units status Three LEDs according to the VME64xP standard Power Access and Ready plus 5 additional LEDs VME user LED Clear Copy in Progress Scaler enable and VIPA user LED BELT IDEE hein a P Power Lei Flags presence of VME power Rc Ready lied Signanconigured lope Signals bank clear Signals copy in progress ZE ae igus one or more nia channels The LED locations are shown in the portion of the front panel drawing below The VME Access the Clear and the Scaler enable LED are monostable i e the duration of the on phase is stretched for better visibility the other LEDs reflect the current status An LED test cycle is performed upon power up refer to the chapter 16 1 Page 12 of 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME 6 VME addressing 6 1 Address Space As bit 11 is the lowest settable bit on the 360x 38xx board an address space of 2 Kbytes Offset plus 0x000 to Ox7ff is occupied by the module 6 2 Base Address 6 2 1 VME The VME addressing mode A16 A24 A32 is selected via the jumpers EN_A16 EN_A24 and EN_A32 The mode is selected by closing the corresponding jumper it is possible to enable two or all three addressing modes simultaneously The base address is set via the fi
31. signal of counter channel is present on this output with deadtime disabled this ouput is unused Page 25 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 14 Signal Specification 14 1 Control Signals The width of the clear and external next pulse has to be greater or equal 10 ns an external inhibit disable counting has to be present for the period you desire to disable counting An internal delay of some 15 ns has to be taken into account for all external signals 14 2 Inputs The SIS3808 is specified for counting rates of 200 MHz for ECL and NIM signals and 100 MHz for the TTL case Thus the minimum high and low level duration is 2 5 ns 5 ns respective Signal deterioration over long cables has to be taken into account It is obvious that the maximum count rate is lower with deadtime enabled 14 3 User Bits The status of the user bits is latched with the leading edge of the external next pulse A setup time of greater equal 10 ns and a hold time of 25 ns is required i e the signal should have a length of greater 35 ns and has to be valid 10 ns before the leading edge of the next clock pulse arrives Page 26 of 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME 15 Operating conditions 15 1 Power Consumption Voltage requirement Although the SIS3808 is prepared for a number of VIPA features it was decided to use an ob board DC DC converter to generate the 5 V which are needed fo
32. ssing the current first version of the SIS3808 firmware does not feature VIPA modes yet however As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info Gstruck de the revision dates are online under http www struck de manuals htm A list of available firmware designs can be retrieved from http www struck de sis3638firm htm Page 5 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 3 Technical Properties Features The SIS3808 is rather a firmware design in combination with given board stuffing options than a name for the board this is the reason why the modules are named SIS360x 38xx on the front panel and the distinction of the units is made by the module identifier register The firmware makes use of part of the possibilites of the SIS360x 38xx PCB if the SIS3808 or other firmware designs of the family come close to what you need but something is missing a custom firmware design may be an option to consider Find below a list of key features of the SIS3808 e 32channels e 200 MHz counting rate ECL and NIM 100 MHz for TTL in non deadtimed mode 20 bit channel depth NIM TTL ECL versions flat cable TTL ECL and LEMO TTL NIM versions 64K FIFO 256 K available on request A16 A24 A32 D16 D32 BLT32 CBLT32 prepared Base addres
33. t hand in the mid term 17 1 Contents of the included Floppy The Floppy contains a readme txt file with the most up to date information the CVI project file and all home made files from the project The important part of the code for the implementation of your own program is sitting in the CVI call back routines Page 30of 41 SIS Documentation SIS3808 SIS GmbH Deadtimed Multiscaler VME 18 Appendix 18 1 Address Modifier Overview Find below the table of address modifiers which can be used with the SIS360x 38xx with the corresponding addressing mode enabled AM code Mode AMcode Mode gt gt SSS 0x09 A32 non privileged data access Future option CBLT Page 31 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 18 2 Front Panel Layout The front panel of the SIS3801 is equipped with 8 LEDs 8 control in and outputs and 32 counter inputs On flat cable units ECL and TTL the control connector is a 20 pin header flat cable connector and the channel inputs are fed via two 34 pin headers On LEMO NIM and TTL units the control in and outputs are grouped to one 8 channel block and the counter inputs are grouped into 2 blocks of 16 channels The units are 4 TE one VME slot wide the front panel is of EMC shielding type VIPA extractor handles are available on request or can be retrofitted by the user if he wants to change to a VIPA crate at a later point in time In the drawin
34. tatus SEIS RD ntt e eege EE EEGENEN SN 7 2 Control Register OKO user covets te n E e NOR et re E RO er He eiecit 7 3 Module Identification and IRQ control register 0x4 7 4 Deadtime register OX8 2 esee erre ie nin eee a niet ette EU e ntt see e teens TS Copy disable register UR 43 6 BEIEO 0x100 0x BC ee EE 8 BroadcasCAddEessllig e eee p e ex eet eed ex eI RR OO beca oni n te dea puedan edtas LO 9 VME VE Ce DU MOE Data Oral EA 10 1 1 D16 10 1 2 D32 IH mput Configuration E DE 11 1 ECL 11 2 NIM DES ta N e sheet Ne Se as cecal E Gt cal a nL eet a tn ane ad MN Naa eh Ey e M ME at Hb VPELIDBMO s siedouuo cic IE aha vate colar NI AR nace ADI QU ola ates 24 ee ple Plat E UBI ah eet lah LM er Eege 24 12 Connector Specification eege nne aer nae eu Fe Ya en pao eS euo vorn oes ev aer ra eo deeg 24 13 Control Input MOUSE FERRY Een vA ERE soon ee sana e eoe n vei ERE x e teen e rsen mei 2D IER EE 25 HAMO C EE EE EE EEN 25 14 Signal SDecifICatloBi oor reo rna eoe ipo ges Eesvs gewvcaspesvuce pv eek eve ea rPI M eere over 20 LL Control Signals ip ERREUR iret Ee 26 142 Inputs xxn tease deci DR e RR bed ARUM e I AES 26 E SO DC E S DR M 26 15 Operating conditions EE 27 15 1 Power Consumption Voltage requirement NENNEN 27 15 2 Cooling MEER 27 15 3 Jnsertion RemovaLl eerte e ec tenete d viene tec lesa Ae te de 27 LUMBER 16 1
35. th the jumper array and the SYSRESET jumper is shown below wwuvwww D81232 DA 0000 U285 dz iounooo D J520 D ULB LCA 3190 PQ160 Page 34 of 41 SIS3808 O u bei o n E x oO E CH c O O SIS Documentation 18 5 Board Layout ip i ill v BEBB BBR goe ca ERT fay ULL I T 9e dh an m Page 35 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 18 6 Cascaded FIFOs The SIS3808 board can be stuffed with one or four synchronous FIFO chips the standard unit comes with one 64K FIFO chip as default The FIFO flags are handled by a PLD programmable logic device if four FIFO chips are installed The meaning of the almost empty half full and almost full flag is redefined in this case as these flags are derived from the status of all four FIFO chips as data are written to and read from the FIFO chips in a ring buffer fashion Find below a table with the FIFO conditions FIFO Oe Meaning in 220 case in 256K case empty Jemp almost empty 25 to 50 full 0 lt 64K 128 16 bit words 0 or 1 between 64K 128 16 bit words and 128 K 256 16 bit words 1 gt 128 K 256 16 bit words half full almost full 50 to 75 full 0 lt 128K 256 16 bit words O or 1 between 128K 256 16 bit words na and 192 K 384 16 bit words 1 gt 192 K 384 16 bit words ll set if full Example If the FIFO almost empty flag is cle
36. unt it starts to decrement the deadtime count with the programmed deadtime step width 120 ns 240 ns 480 ns or 960 ns and will not count the next input pulse before the deadtime counter has reached zero The deadtime counter is automatically preloaded for the next deadtime phase Page 7 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME LNE ect Counter Xilinx 8 Scaler Inputs LNE e Loi Gem Counter Xilinx 8 Scaler Inputs 3 3 Minimum Dwell Time The minimum dwell time on the SIS3808 is defined by the time which is needed to copy the data from the idle scaler bank to the FIFO The time required to copy one 32 bit data word from the counter Xilinx chips to the FIFO is 100 ns The overhead is 600 ns thus the minimum dwell time is 3 8 us with all 32 scaler channels active Future SIS3801 designs will have a channel count dependent dwell time Via the copy disable register the number of active channels can be reduced if lower dwell times are of interest The time which is needed for the copy progress can be measured on the copy in progress CIP output the output is active for the duration of the process the signal can also be of help to control or synchronise external components As the maximum number of counts the unit can acquire within microsecond time frames is in the order of a couple of hundred one may consider to go for a 16 bit counter design if shorter dwell times are envis
37. ve rotary switches SW_A32U SW A32L SW_A24U SW A2AL and SW A16 and the jumper J All The table below lists the switches and jumpers and their corresponding address bits SW ADAL 19 16 SW AI6 15 12 LA In the table below you can see which jumpers and switches are used for address decoding in the three different addressing modes fields marked with an x are used SW_A32U SW AZL SW A24U SW A24L SW A16 JAN x x Hooccee doo ume 0 oe 1 pU a i E RT e T oe er ee es AELE E E GE Note J A11 closed represents a 0 J A11 open a one 6 2 2 VIPA VME64x As the VME64x and the VME64xP VIPA standard are not yet standards to refer to and to declare conformity with addressing modes like geographical addressing e g according to these standards are prepared but not yet implemented in the current firmware revisions Page 13 of 41 SIS Documentation SIS3808 SIS GmbH 4 Deadtimed Multiscaler VME 6 3 Address Map The SIS360x 38xx boards are operated via VME registers VME key addresses and the FIFO where installed The following table gives an overview on all SIS3808 addresses and their offset from the base address a closer description of the registers and their function is given in the following subsections 0x000 R W DI6 D32 ControlandStatusregister 0x004 R W DI6 D32 Moduleldentification and IRQ control register 0x08 w DIGD32 Dead meregister o Z o Y
38. wz x GND Ooo GND p E EDEN Ooo Boa a Ooo GND p GND an p E p i CREME poo a5 GND Ke H pd REESEN GND E GND ed Oooo E Oooo ae GND Oooo el GND GND Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors Page 38 of 41 SIS Documentation SIS3808 Deadtimed Multiscaler 18 9 Geographical Address Pin Assignments The SIS38xx board series is prepared for geographical addressing via the geographical address pins GAO GA1 GA2 GA3 GA4 and GAP The address pins are left open or tied to ground by the backplane as listed in the following table Slot GAP Number Pin 1 LA Ikea lt m m ltz ltz Cc poj oo JAIN INIA o Jd 21 hs Sa jen EN ERN EE SE EE Wee EE SE 100 EET it as e JH WEE 106 ay 08 ET 20 IE SEN Open Open Open Open Open Open Open Open Open Open Open Open GND Open Open GND Open Open GND Open Open Open GND Open GND Z S 8 Oo Q o O Q O O ZIZ is OO s OOo re Bs Q Z J ie 5 N Open GND Open Open GND Open Open GND Open N N N N e 5 QIQIO 8 ZIZ 5v o 5 Z d Q Q O Q Q O DIDO JOJO Jo F O 5 Open GND GND Open GND GND Open Open Q J 5 Q J 8

SIS3808 Deadtimed VME Multiscaler User Manual

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