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M6713 User's Manual

1. TABLE 27 External Interrupt Input Control Register Addresses 122 Development Package Manual Interrupts Bit Interrupt Description 0 PCI write FIFO int Interrupt to DSP when PCI write FIFO is below the set threshold 1 PCI read FIFO int Interrupt to DSP when PCI write FIFO is above the set threshold 2 13 Not used 14 BM rd packet end all data rcv d in An interrupt to the DSP indicating that the busmaster controller the FIFO on a read packet has retrieved all the data in a packet 15 Not used 16 Mod 0 Int 0 Omnibus Module 0 int 0 17 Mod 0 int 1 Omnibus Module 0 int 1 18 Mod 1 Int 0 Omnibus Module 1 int 0 19 Mod 1 Int 1 Omnibus Module 1 int 1 20 Ext Clk 0 Interrupt from the Ext Clk SMB input 0 21 Ext Clk 1 Interrupt from the Ext Clk SMB input 1 22 fpdp tx fifo int FPDP TX port FIFO is above the set threshold 23 fpdp rx fifo int FPDP RX port FIFO is below the set threshold 24 fpdp rx sync int FPDP Rx port interrupt when a sync is received the number of points received in the frame may be read 25 Sync 4 SyncLink input 4 26 Sync 5 SyncLink input 5 27 fpdp tx next frame int FPDP Tx port is ready for the next frame size 29 27 Not Used 30 Acknowledged mode NMI and INT4 Sets acknowledged mode if true which requires that each interrupt only source be acknowledged with a write to the interrupt ack register 0 non ack d d
2. 3M P50E BO Pins FPDP Rx 3M 50 B0 Pins OMNIBUS Site 0 OMNIBUS Site 1 MOR 100 sue Ext Trigger sus IDC 50 Memory There two memory maps for the M6713 the DSP memory map and PCI mapped devices on card The following figure gives the DSP memory map of the M6713 for external peripherals and memory Please note that this table ignores any on chip resources see TI peripheral manual for TMS320C6713 for on chip peripherals CE DSP Memory Logic Logic Access Read Description Space Address Device Address Type Write Decimal Ceo 0x80000000 PCI 0 Async Ww DIG config Ceo 0x80010000 PCI 1 Async WwW DIG_data 102 Development Package Manual Memory Map Ceo 0x80020000 PCI 2 Async Ww DDS control Ceo 0x80030000 PCI 3 Async DDS data Ceo 0x80040000 PCI 4 Async W Ceo 0x80050000 PCI 5 Async W INT4 status ack Ceo 0x80060000 PCI 6 Async W Ceo 0x80070000 PCI 7 Async Ww DMA int enable Ceo 0x80080000 PCI 8 Async NMI status ack Ceo 0x80090000 PCI 9 Async Ww INT4 enable Ceo 0x800A0000 PCI 10 Async Ww INT5 enable Ceo 0x800B0000 PCI 11 Async Ww INT6 enable Ceo 0x800C0000 PCI 12 Async Ww INT7 enable Ceo 0x800D0000 PCI 13 Async W NMI enable Ce0 0x800E0000 PCI 14 Async Not used Ceo 0x
3. Cancel Help 2 55 Building a Target DSP Project Type the boilerplate code below into your source file This is the minimum code needed for any Pismo C application App cpp include Pismo h using namespace II Applicatio void IIMain In In e Click the menu Project Build Options to invoke the compiler Build options dialog Then select the Files Category then enter the pathspec to the Examples opt file in the Examples direc New Build Options for Test pjt Ad xl Open Use External Makefile General Compiler Linker Link Order Export to Makefile Add Files to Project g q fr C Vista Examples T est Debug DEBUG my6710 Save Close CI gt Category r Basic Target Version Gompile File Bi pi Generate Debug Info Fut Symbolic Debug a 7 Rebuild All Opt Speed vs Size Speed Most Critical no ms 7 Stop Build Opt Level None Show Dependencies Program Level Opt 7 Scan All Dependencies Configurations Build Opti File Specific Options Function Level Options Recent Project Files 4 o cane tory to the Options File edit box Writing a Program e Click on the Link Order tab then add Examples cma to the Link Order List Build Options for AnalogCapture pjt 21 x General Compiler Linker Link Order Link order 4
4. These options insure that projects are built with minimal dependencies on external DLLs See the FAQ What DLLs do I have to deploy with my newly created executable in the Troubleshooting chapter for details on which DLLs must be deployed with user written executables Appropriate library and include paths Click on Project Options on the main BCB toolbar to invoke the Project Options dialog Then click on the Directories Conditionals tab to edit the default Include and Library paths which should be used when constructing a Malibu based application x Version Info Packages Tasm CORBA CodeGuard Forms Application Compiler Advanced Compiler C Pascal Linker Advanced Linker Directories Conditionals Directories Include path ECB include BCB include vel BCE VAr 7 El Library path S BCB ProjectsiLib BCBJNibrobi BCB ib E Debug source path SIECB source wel C Program Files Borland y El Intermediate output l El Final output GG E E BP Boupt Conditionals Conditional defines DEBUG y E Aliases Next click on the ellipses next to the Include Path edit box to invoke the Include Path editor dialog Add an entry for BCB Innovative then click Ok to accept these edits 28 Borland Builder Setup and Use be Directories Ordered list of Include paths InnovativeCommon M alibu BCB innovative BCB in
5. C6713 has an advanced cache controller that helps access times by putting data into local DSP memory from the SDRAM This makes the SDRAM look to the programmer like a large virtual mem ory pool of very fast memory The cache controller allows the SDRAM to operate at approximately 106 Development Package Manual M6713 OMNIBUS 80 the efficiency of internal memory in many cases by caching instructions and data in on chip mem ory for faster access M6713 OMNIBUS The M6713 has two Omnibus I O sites mapped into the processor memory space A variety of Omni bus IO modules are available with many types of analog and digital IO that can be mixed and matched to suit the particular user s functional requirements Omnibus is an open standard that allows customers to design application specific modules to use with the M6713 and other Omnibus cards The OMNIBUS slots are accessed as memory mapped peripherals with the M6713 providing four decoded chip select signals per slot for a total of eight on the M6713 The following figure gives the memory map for the OMNIBUS slots and shows the decode signal to slot mapping Function Starting Address Module Slot MNIBUS Strobe 0 0xB0000000 S Strobe 1 0xB0010000 S Strobe 2 0xB0020000 S Strobe 3 0xB0030000 S Strobe 4 0xB0040000 S Strobe 5 0xB0050000 S Strobe 6 0xB0060000 MNIBUS Strobe 7 0xB0070000 Ol OI OI O OI OI O lt lt lt lt lt
6. 0 33 About the Baseboard Requested true Available Acquire return Snaps protected Fields volatile int FCount Data bool Requested Semaphore Available IntBuffer Snaps int Cursor int CaptureEvents Methods void Execute echo input to output while Terminated AIn Get FCount main thread wants a block copy it to him if Requested continue int Residual Snaps Ints Cursor int Chunk std min Residual AIn Buffer Ints Snaps Copy AIn Buffer Cursor Chunk Cursor Chunk if Cursor CaptureEvents Requested false Available Release LoopThread Loop tpHigher Not Just for C Experts Note that even if you re not a C maven the code is quite clear and understandable In fact one of the benefits of using C is that while it helps to mitigate and manage complexity to support creation of larger more sophisticated applications it is often simply used as a better dialect of the C language C is essentially a superset of C As such you may freely intermix calls to legacy functions newly written C functions Assembler functions and C functions called methods within C programs You need not fully understand all of the enhanced capabilities and fea tures of C in order to fully exploit the features of the class libraries provided in Pismo 34 Analog I O Streams
7. Add to link order list Files without link order Extension AnalogCapture CDB CDB AnalogCapturectg cmd cmd AnalogCapturectg s62 s52 AnalogCapturecfg c c AnalogCaptureT est cpp e Click the Incremental Build button to rebuild the template application It should compile and link Debug Profiler GEL Option Tools PBC DSP BIOS Wir qu r Debug al without errors Writing a Program The basic program given in the example above includes a Main function Main DSP BIOS the OS used in the Pismo library uses code inserted after exiting from the normal C language main to initial ize features of DSP BIOS This means that some language features are not available then To avoid these problems the Pismo library provides a main function and uses it to create a single thread This thread when executed calls the Main function Inside of this thread all DSP BIOS is initialized and ready for use It is required that the user include this function and use it as the equivalent of the old main process function in C Host Tools for Target Application Development The Innovative Integration Pismo Toolset allows users of Innovative DSP processor boards to develop complete executable applications suitable for use on the target platform The environment suite consists of the TI Optimizing C Compiler Assembler and Linker the Code Composer debugger and code authoring environment a
8. Connector types Number of pins 50 Mating connector The following table gives the pin numbers and functions for the JP6 OMNIBUS slot 0 and JP10 OMNIBUS slot 1 connectors The functions for JP10 are identical to those of JP6 except where AMP 05 Subminiature D male AMP 173279 3 noted Direction Pin Number JP6 Function JP10 Function from M6713 1 19 Digital 5V O power 2 20 Digital ground O power 3 18 Data bus 0 15 21 43 40 45 Address bus 2 8 O 39 26 27 28 Reset active low O 29 External interrupt 0 External interrupt 2 I 30 Bus ready active low I open collector 31 Processor ECLK 2 37 5 MHz 32 DSP timer channel 0 O 33 R W O 34 DDS timebase O 35 38 IOMODO 3 decoded selects IOMOD4 7 decoded selects O active low active low 25 Analog 15V OMNIBUS O power 12V 23 Analog 15V OMNIBUS O power 12V 41 42 Analog ground O power 22 24 Analog 15V O power 44 46 Analog 15V O power 47 49 Analog 5V O power 48 50 Analog 5V O power TABLE 38 OMNIBUS Bus Connectors 140 Development Package Manual Connector pinouts The following table gives the pin numbers and functions for the JP5 OMNIBUS slot 0 and JP9 OMNIBUS slot 1 connectors Direction Pin Number JP5 Function JP9 Function from M6713 1 3 6 Address bus 9 13
9. FIGURE 15 FIGURE 16 FIGURE 17 FIGURE 18 FIGURE 19 FIGURE 20 FIGURE 21 Some Classes in Malibu 80 Terminal Emulator Applet 94 RtdxTerminal File Menu 95 RtdxTerminal DSP Menu 96 RtdxTerminal Form Menu 96 RtdxTerminal Help Menu 97 RtdxTerminal Options 98 M6713 Block Diagram 102 FPDP Overview 110 FPDP Timing Diagrams for ALL Data Framing Types 111 Standard FPDP Timing Diagram For Single Frame And Repeated Frame Data 112 PCI Interface Block Diagram 114 PCI Packet Format 115 DDS and Post scaler 117 Digital IO Port Block Diagram 120 Digital Port Timing 122 JP12 SyncLink Connector Pin Orientation 147 JP14 JP15 DSP Serial Port Connector 148 JP16 DSP JTAG Debugger Connector 149 JP18 Power Test Connector 150 JP17 Interface Logic Spartan3 JTAG Connector 151 SBC6713e User s Manual 10 SBC6713e User s Manual CHAPTER 1 Introduction Introduction When making reference to the baseboard in this manual we will be referring to the M6713 single board computer baseboard What is the M6713 The M6713 is Innovative Integration s PCI plug in base board architecture that integrates modularized high performance analog and digital peripherals with a high performance DSP and peripheral cores The M6713 is equipped with a 64 bit 66 MHz PCI bus interface allowing high speed data trans fers with the host The baseboard includes an onboard TMS320C6713 DSP with 128 MB cached S
10. Files of type Building a Target DSP Project e Right click on Test pjt in the project window click Add Files then select the the newly cre ated Test cmd for addition to the project aixi Look in Ea res y EE Debug File name testota cmd Files of type Linker Command File cmd Cancel Help 2 e Right click on Test pjt in the project window select Add Files then browse to the Examples directory and select Examples for addition to the project i Fis to Pret 2 Look in fa Target y ct Er File name HdwLib ib Files of type Object and Library Files 0 P Cancel Help 2 Add an new C source file to the project ista CPU_1 C6711 Code Composer Studio Click File New Source File to create File Edit Object View Project Debug Profiler GEL Option Tools P an empty source document Source File Ctrl N Open Ctro DSP BIOS Configuration Close Visual Linker Recipe Rename the new source document to Save Chrl 5 ActiveX Document Test cpp To use the Pismo libraries you So i i ave must use C files and the C compiler Test CDB Load Program Estimated Data Size 2765 Est M even if you intend to restrict your own Load Symbol X coding to the C subset of C Add Symbol 1 2 Instrumentation Save in Y Test y er El File name Test cpp Save as type
11. SBC6713e User s Manual Borland C Builder Problems 133 DSP Hardware Problems 135 CHAPTER 11 Appendices 137 Connector pinouts 137 Board Layout Drawing Rev 152 SBC6713e User s Manual SBC6713e User s Manual TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 TABLE 10 TABLE 11 TABLE 12 TABLE 13 TABLE 14 TABLE 15 TABLE 16 TABLE 17 TABLE 18 TABLE 19 TABLE 20 TABLE 21 TABLE 22 TABLE 23 TABLE 24 TABLE 25 TABLE 26 TABLE 27 TABLE 28 TABLE 29 TABLE 30 TABLE 31 TABLE 32 TABLE 33 TABLE 34 TABLE 35 TABLE 36 TABLE 37 TABLE 38 TABLE 39 TABLE 40 TABLE 41 Typographic Conventions 13 C6713 DSP EMIF Control Register Initialization Values 32 Device Driver and Stream Classes 35 Stream object Clock Methods 39 Stream object Pretrigger Methods 40 Stream object Start Trigger Methods 40 Stream object Stop Trigger Methods 40 Stream object Retrigger Methods 41 Interrupt Lock Classes 44 Pismo Example Programs 61 The Servo Class Virtual Function 66 Servo Time Measurements 68 M6713 DSP External Memory Map 105 M6713 Bus Control Register Initialization Values 106 M6713 I O Bus Memory Mapping 107 I O Bus Power Ratings 109 FPDP Memory Map 113 FPDP Rx Configuration Register 113 FPDP Tx Configuration Register 113 PCI DMA Rates Summary 115 DDS Post dscaling Control Register Module 0 0x8020002C Module 1 0x80200030
12. 0x1b 60 Example Programs cio monitor The two lines of the program that being with a are include statements which include the header files for the hardware and utility I O libraries These include prototypes for all the library classes within Pismo The cio lt lt init invokation will setup the standard monitor I O interface and reset the terminal win dow The next lines perform the basic standard I O functions of printing Hello World amp Echoing keystrokes These two lines are where custom code could be inserted The following do loop sequence simply echoes keys typed at the terminal emulator back to the terminal display until the Esc key is pressed When Esc is pressed the cio monitor function effectively terminates the program except that interrupts are still active and interrupt handlers if they had been installed would still execute properly The test program is very simple but it contains the basic components of a typical DSP application as well as the initialization needed to interact with the terminal emulator Use of Library Code Library routines can be compiled and linked into your custom software simply by making the appropri ate call in the source and adding the appropriate library to the linker command file Refer to the library reference within the Pismo online help for library location information on each class and method In general user software needs to include
13. 118 AD9851 Control Registers 118 Timer0 and DDS Pin Output Sources Module 0 0x80200034 Module 1 0x80200038 119 Digital I O Control Registers 120 Digital IO Port Control Register Bit Definitions 121 Digital Port Timing Parameters 122 External Interrupt Input Control Register Addresses 122 External Interrupt Control Register Bit Definitions 123 External Interrupt Status and Acknowledge Register Addresses 125 Interrupt Burst Counting Control Register 126 DMA Address for Interrupt Control 126 Interrupt Access Counting Control Registers 126 External Clock Input Termination Jumper Settings 127 SyncLink O Signal Selection Register Bit Definitions 128 SyncLink 1 Signal Selection Register Bit definitions 128 SyncLink 2 Signal Selection Register Bit definitions 128 ClockLink Signal Selection Register Bit Definitions 129 OMNIBUS Bus Connectors 140 I O Module Bus Connectors 141 Digital O Connector 142 FPDP JH1 Tx Port Connector 144 SBC6713e User s Manual TABLE 42 TABLE 43 TABLE 44 TABLE 45 TABLE 46 TABLE 47 FPDP JH2 Rx Port Connector 146 SyncLink Connector 147 DSP Serial Port Connector 148 DSP JTAG Debugger Connector 149 Power Test Connector 150 JP17 Interface Logic Spartan3 JTAG Connector 151 SBC6713e User s Manual FIGURE 1 FIGURE 2 FIGURE 3 FIGURE 4 FIGURE 5 FIGURE 6 FIGURE 7 FIGURE 8 FIGURE 9 FIGURE 10 FIGURE 11 FIGURE 12 FIGURE 13 FIGURE 14
14. 4 Remove the card from its protective static safe shipping container being careful to handle the card only by the edges 5 Touch the chassis of the PC to dissipate any built up static charge Securely install the JTAG board in an available PCI slot in the host computer 7 Connect the JTAG pod to the host pod cable Connect the host pod cable to the connector located on the end bracket of the JTAG PCI plug in board 19 Installation DSP Board Installation When installing the target card 1 Power off the host system and touch the chassis of the host computer system to dissipate any static charge 2 Remove the DSP card from its protective static safe shipping container being careful to handle the card only by the edges 3 Install or place the M6713 card into an available PCI slot within your PC If available a 64 bit slot will provide optimal performance 4 Connect the JTAG debugger pod cable from the JTAG board connection to the JTAG connector on the target board 5 Connect the target cable between the JTAG PCI board within your PC to the mating JTAG pod con nector A Few Considerations BEFORE Power up Double check everything before applying power Are the JTAG if needed and baseboard cards seated correctly in the slot It can t be overemphasized double check your cabling BEFORE connection to the baseboard Also don t cut corners and hot plug the cables This can cause latch up of components on the card
15. Incr Ed Settings DestinationAddr dest_array DestinationIncr DmaSettings Incr Define a linked DmaSettings Cfg Cfg Priority 1 ElementSize 0 Sourcelncr 1 DestinationIncr 1 Cfg TCInt true TCCode 1 FrameSync true Cfg SourceAddr int src_array 0 DestinationAddr int dest_array 50 Cfg ElementCount 50 Element Index 1 Cfg FrameCount 0 FrameIndex 1 Ed AddLink Cfg Ed LinkTcIntInstall 0 Isr Binder Ed TcIntClear This EDMA operation will trip a terminal count interrupt when all data has been moved InitArrays Ed TcIntEnable true qdma not done true Ed Submit We software initiate the EDMA here but if this EDMA were using EINT4 7 then an external int hardware pulse would remove need for Ed Set below Ed Set while qdma not done Need to sync L2 cache with the of SDRAM so that CPU can see the data CACHE clean CACHE L2 dest array sizeof dest array Transfer the second transfer block Ed Set while qdma_not_done Need to sync L2 cache with the of SDRAM so that CPU can see the data CACHE clean CACHE L2 dest array sizeof dest_array The above example sets up a two block linked transfer triggered by software A TC Interrupt is config ured to signal the completion of each block in the transfer The mainline waits for each block transfer to finish as notified by the interrupt handler Then the next blo
16. Rev B ooo ann m E lt lt S me d gt A ae e a Al 5309 aay a AA nia lt on a Y La ha S yw gt Y a ov a E DE g y y mu H 99900000 Noro 2006000909900 nua nan E AY iT een Y D Ne f L la a6 f A S 5 lt m lo lai O a amp Loc am lt LY U Saat E E 9 z nes iau 9900080 0000030 External Clock O 4 415in JP4 Omnibus IO JPI Test Only JH1 FPDP Tx Port JH2 FPDP Omnibus Slot 1 Rx Port 7 713 in 152 Development Package Manual Board Layout Drawing Rev B Development Package Manual 153 Appendices 154 Development Package Manual Board Layout Drawing Rev B Development Package Manual 155 Appendices 156 Development Package Manual Board Layout Drawing Rev B Development Package Manual 157 Appendices 158 Development Package Manual Board Layout Drawing Rev B Development Package Manual 159 Appendices 160 Development Package Manual Board Layout Drawing Rev B Development Package Manual 161 Appendices 162 Development Package Manual Symbols c file 58 A Applets BinView 92
17. bold lt lt 7Demonstrate file I Onn lt lt normal lt lt endl Note the use of manipulators such as bold and normal to force formatting of the text string as it is streamed to the host Termlo features many such manipulators to perform functions such as setting text color setcolor clearing to end of line clreol clearing the screen cls and so forth Other manipula tors are available to format numeric values as they are streamed to the host For example the phrase cio lt lt Hello lt lt hex lt lt showbase lt lt 4660 lt lt dec displays the string Hello 0x1234 on the console display converting the integer value 4660 as a hexa decimal number on the target prior to streaming it to the host Other manipulators are available provid ing extensive control over the display of floating point numbers as well as integer values It is also frequently necessary to obtain input from an operator during the run time execution of a target application For example it may be necessary to prompt for a sample rate at which analog I O is to be streamed The code fragment below illustrates the necessary technique 76 C Terminal I O Prompt the user cio lt lt Enter a float lt lt flush float x2 Bat user input GUO gt gt 2 The stream manipulator gt gt is overloaded to allow streaming directly into floating point integer and string variables directly from UniTerminal To perform file
18. 32 35 33 84 34 34 35 83 36 33 37 82 38 32 39 81 40 31 41 80 42 30 43 79 44 29 45 78 46 28 47 77 48 27 49 76 50 26 138 Development Package Manual Connector pinouts The following table shows the interconnections between the JP8 OMNIBUS slot and JP5 OMNI BUS IO connector JP8 Module 1 Pin JP5 Pin Numbers 1 75 2 25 3 74 4 24 5 73 6 23 7 72 8 22 9 71 10 21 11 70 12 20 13 69 14 19 15 68 16 18 17 67 18 17 19 66 20 16 21 65 22 15 23 64 24 14 25 63 26 13 27 62 28 12 29 61 30 11 31 60 32 10 33 59 34 9 35 58 36 8 37 57 38 7 39 56 40 6 41 55 42 5 43 54 44 4 45 53 46 3 47 52 48 2 49 51 50 1 SS ES ff 41 PIN1 SIN PINS SIN 2IN11 PINI PINI PINI PIN19 21421 PIN23 SIN PIN27 SIN PINS1 PIN PIN PIN37 SING PIN41 DINA PIN45 PING N49 ko E gt Dn Dn JP48 MDR100RTF OQ 4 amp UO 4 D U U U O U O GU U U U Y U O U O U O U U U U N U G Development Package Manual 139 Appendices JP5 6 9 10 OMNIBUS Bus Connectors
19. Analog I O Streams The Analog I O is for most applications the most important feature of the M6713 baseboard Most of the peripherals on the hardware are related to Analog I O Most of the configuration options are related to Analog I O It is the part that causes the most problems in development To maximize the chances for success the Pismo library provides a set of classes that hide all of the details of data acquisition From the application level the user simply processes buffers of data The details of hardware and software management are isolated from the application Stream Objects and Device Drivers Data I O in DSP BIOS is accessed and controlled via custom device drivers Access to the device driver is controlled by a Stream class These drivers are dynamically installed by the Stream when needed by the user application From the point of view of the application the stream control class provides all of the user interface function needed to configure and operate the I O operation TABLE 3 Device Driver and Stream Classes Device Driver Class Stream Class Description AnalogInputDriver AnalogInStream Streamed Input from an analog source Continuous data flow with buffering Data flow stops only via trigger control AnalogOutputDriver AnalogOutStream Streamed Output to an analog source Continuous data flow with buffering Data flow stops only via trigger control CaptureInputDriver CaptureInStream Burst Input from an analog
20. Bus The M6713 implements a JTAG 1149 1 compatible scan path loop through the onboard C6713 with connector compatible with the specification provided in the 7MS320C6000 User s Guide JP16 is the JTAG connector for use with a JTAG controller card cable from an Innovative Integration Code Hammer debugger card Texas Instruments XDS 510 or other vendor s JTAG hardware Power Requirements The M6713 uses the PCI bus power for operation On card power supplies make some of the unique voltages required by the M6713 for the DSP FPGA and analog IO from the host power supplied over the PCI bus Supply Voltage Current Use 3A max 0 82A 5VDC typical All digital electronics including DSP and FPGA Module 12V dependent Omnibus Supply usually for analog IO Module Omnibus Supply usually for analog IO 12V dependent Updating the M6713 logic The M6713 logic may be updated in the field under normal circumstances without removing the card from the system There are two FPGA logic devices on the card the PCI control logic and the Interface logic The Interface logic must be loaded each time the M6713 is powered up since there is no on card memory is provided for the Interface logic FPGA The PCI controller logic has an on card FLASH memory that holds its logic image and may be reprogrammed in the field Reprogramming the PCI Controller Logic The PCI FPGA logic is held in a reprogrammable FLASH that can be written by the DSP so
21. CPU is strongly recommended since AMD and other clone processors are not compati ble with the Intel MMX and SIMD instruction set extensions which the Malibu Host library utilizes extensively to improve processing performance within a num ber of its components The host system must have at least 128 Mbytes of memory 256MB recommended 100 Mbytes available hard disk space and a CDROM drive Windows 2000 or XP referred to herein simply as Windows is required to run the developer s package software and are the target operating systems for which host software development is supported Software Installation The development package has an installation program that will guide you through the installation 15 Installation Note Before installing the host development libraries VCL components or MFC classes you must have Microsoft MSVC and or Borland C Builder installed on your machine depending on which of these IDEs you plan to use for Host development If you are planning on using one of these environ ments it is imperative that these environments be tested and known operational before proceeding with the library installation Additionally you must install Code Composer Studio prior to installation of the development package software If these items are not yet installed then the installation program will not permit installation of the associated development libraries However drivers and DLLs only may be install
22. Close Projects m Gompile File Build Rebuild All Stap Build Show Dependencies Scan All Dependencies Configurations Build Options File Specific Options Function Level Options Recent Project Files Specify the location for the new project and its name In this example a new project called Test is being created in the 6713 NV Examples Ws directory Change the location to accomodate your x Project Name Test Location C AVista Examples Test El Project Type Executable out Target 5320 57 y coca _ board type and processor type After the new project has been created it will appear in the CCS project window under the Projects folder 2 Files II6x gel E Projects EH B Test pjt 52 Building a Target DSP Project Click File New DSP BIOS Configuration to create a new CDB file for use in the project ista CPU_1 C6711 Code Composer Studio Save As Save All Load Program Load Symbol Add Symbol Reload Program Load GEL Gros Data Workspace File 1 0 Print Print Preview Visual Linker Recipe Select the template for the baseboard from the list of CDBs in the New CDB dialog box This CDB is named after the baseboard type For example for the M6713 choose m6713 cDB and for the Conejo baseboard choose the
23. DSP JTAG Debugger Connector FIGURE 19 JP16 DSP JTAG Debugger Connector EMUO R78 47K Development Package Manual 149 Appendices JP18 Power Test Connector Connector type Shrouded header Number of pins 14 Mating connector AMP 746285 2 This connector is only for debug Normally used for production testing Pin Number JP18 Function 1 DGND 2 5V 3 4 AGND 5 DSP Core Voltage 1 4 V 6 3 7 SV 8 E 9 3 3V 10 AV 15 11 2 5V 12 AV 15V 13 1 2V Spartan3 FPGA Core 14 5V TABLE 46 Power Test Connector FIGURE 20 JP18 Power Test Connector OLTAGE TEST HEADER P TEST ONLY NO HIGH CURRENT PATH NEEDED IDC14VM 150 Development Package Manual Connector pinouts JP17 Interface Logic Spartan3 JTAG Connector Connector type 2MM unshrouded header Number of pins 10 Mating connector Samtec SQT style for board board applications This connector is for programming and developing logic for the Spartan3 Interface logic FPGA Pin Number JP17 Function DGND TDI DGND TDO DGND TMS DGND TCK 0 DGND IN TABLE 47 JP17 Interface Logic Spartan3 Connector FIGURE 21 JP17 Interface Logic Spartan3 JTAG Connector SPARTAN 3 JTAG JP17 IDC10VM Development Package Manual 151 Appendices Board Layout Drawing
24. Development Package software libraries Be sure to include initialization of these values whenever software is devel oped outside the Development Package or when a JTAG hardware assisted debugger is employed for code downloading to the M6713 i e when using Code Composer Studio or any other JTAG debugger package The DSP also must initialize the clock PLL and steering The input clock is 37 5MHz which is multi plied by 8 in the DSP PLL for the main processor 300 MHz clock The clock control in the DSP is also configured to provide a 75 MHz clock on SYSCLK3 for the EMIF clock Here are the intialization val ues as used in the support software For 300 MHz Processor Divider DO PLLREF 37 5 MHz PLL x8 PLLOUT 300 MHz Divider D1 1 SYSCLK1 300 Divider D2 2 SYSCLK2 150 MHz must be Y SYSCLK1 Divider D3 4 SYSCLK3 75 MHz for EMIF and so that Omnibus is 37 5MHz External Memory The M6713 external memory is synchronous DRAM SDRAM organized as 32Mx32 128 Mbytes The SDRAM operates at a fixed rate of 75 MHz for a maximum burst throughput of 300 Mbytes sec Practical use of the SDRAM for the best performance normally requires thoughtful allocation of the DSP on chip memory for local memory and cache use SDRAM is only fast to access in bursts to con sective memory addresses random accesses to memory are very slow often requiring at least 6 external clock cycles per access The cache controller The
25. Innovative we encourage you to discuss this requirement with our technical staff Many details involved in the use of the PCI busmastering interface are not obvious DSP Software Support for Using the PCI DMA Controller The DSP can use the PCI bus interface DMA controller by writing to the FIFO or reading from the FIFO when an interrupt signals that data is available The data packets must be formatted with the 2 word header as described Interrupts to the DSP are used in both data flow directions to pace the data movement In the DSP to host direction the DSP sets a FIFO level at which an interrupt will occur in the PCI FIFO level control register CEO 0x80180000 signaling that there is more room in the FIFO for data A DMA channel on the DSP is used to move data based on this interrupt to the FIFO CE1 0x90000000 In the host to DSP direction the DSP moves data from the FIFO CE1 0x90000000 when an interrupt signals that a packet is available The DSP then reads the header and programs a DMA channel according to the packet size to move the data from the FIFO to the DSP The FIFO management requires that the DSP use the PCI FIFO level control register to control the interrupts from the FIFOs The FIFO is 256 deep so large packets must be split into pieces usually 32 to 128 words in size for the DSP DMA channel to move The DSP DMA channel is programmed to move the entire packet size as small pieces driven by an interrupt from the PCI F
26. Set up a real time clock to send commands to host on Target channel Irq Timer0 intTimer0 Timer0 Install TimerBinder Timer0 Enable false Turn on the clock at 5 hz DspClock Tclk0 50 0 150 0 Timer0 Enable true In the example TimerBinder is an object that collects the handler function ontimerFired and its argu ment 0 This object is passed into an Ira object associated with the interrupt When the timer interrupt fires the handler will be called with its argument The binder is a template allowing any type of argument to be used with an interrupt handler Class Irq Class is an object that can be created to manage a specific interrupt It has functions to set clear enable and disable the interrupt and also allows a handler to be installed that will be called whenever the interrupt fires In the above code see how all functions involving the interrupt were encapsulated in the methods of the Timero class object Interrupt Lock Classes A common need in a program is the ability to disable a particular interrupt or all interrupts in a portion of the program The standard means of standalone functions an disable fol lowed by a enable interrupts has a few problems The first is that the means does not nest well If a function blocking interrupts is nested in a second one interrupts will be re enabled at the wrong time A second is that if the function has multiple return paths each m
27. Simplified management of and access to all TI Chip Support Library CSL and DSP BIOS API functions including Semaphores Mutexes Mailboxes Timers Edma Qdma Atoms McBsp Timebases Counters etc e Foundation base classes for DMA driven device driver development Templatized queues Partial standard template library functionality via STLPort For example the code fragment below uses the Pismo tntBuffer class to initialize a QDMA quick DMA to perform a memory to memory move of a constant value 0 into a 4096 word buffer at Src then to copy the source buffer Src to the destination buffer Dst Create a source buffer of 0x1000 integers IIBuffer Src 0x1000 Initialize the source buffer with zeros Src Set 0 Create a destination buffer of 0x1000 integers IIBuffer Dst 0x1000 Dst Copy Src Simple To Use In the same way peripheral specific class libraries dramatically simplify access to board specific peripheral features For example the code fragment below illustrates real time process ing and display of analog input signals running on the M6713 DSP board equipped with an Omnibus module within a separate thread of execution class LoopThread public Thread public LoopThread IIPriority priority Thread priority FCount 0 Cursor 0 Requested false int Count return FCount void Resize int size CaptureEvents size Snaps Resize size IntBuffer amp Acquire Cursor
28. and dam age them irreparably Be aware that the cables to analog inputs are an important part of keeping the sig nals clean and noise free Shielded cables and differential inputs where applicable help to control and reduce the noise After completing the hardware installation boot up your PC After Power up If using the Innovative Code Hammer debugger Windows should detect and auto configure the device at start up Under rare circumstances Windows will fail to auto install the device drivers for the JTAG If this happens please refer to the TroubleShooting section Use M6713LogiclLoader to program the user logic Please refer to Chapter 8 Before invoking the JTAG debugger the user must boot the DSP using M6713Download utility Please refer to Chapter 8 Note The user must load the user logic and boot the DSP before start the Code Composer setup 20 Code Composer Studio v2 x Setup Code Composer Studio v2 x Setup To setup Code Composer Studio v2 x and activate the Innovative supplied Code Hammer JTAG board driver the Code Composer Setup Utility must be run Since the Code Hammer debugger is XDS510 compatible Code Composer Studio setup must be configured to use the homogeneous XDS510 driver for the C6000 This driver is named C62xx C67xx XDS510 Emulator within the Code Composer setup utility In the figure below it is the first item listed in the Available Board Simulator Types column of the Setup prog
29. baseboard using the supplied Pismo soft ware There are a wide selection of peripheral devices available as plug in Omnibus modules for many types of signals from DC to RF frequency applications or audio processing Additionally multiple base boards cards can be used for a large channel or mixed requirement systems and data acquisition cards from Innovative can be integrated with Innovative s other DSP or data acquisition baseboards such as ChicoPlus for high performance signal processing Why do I need to use the M6713 baseboard One of the biggest issues in using the personal com puter for data collection control and communications applications is the relatively poor real time per formance associated with the system Despite the high computational power of the PC it cannot reliably respond to real time events at rates much faster than a few hundred hertz The PC is really best at pro cessing data not collecting it In fact most modern operating systems like Windows are simply not focused on real time performance but rather on ease of use and convenience Word processing and spreadsheets are simply not high performance real time tasks The solution to this problem is to provide specialized hardware assistance responsible solely for real time tasks Much the same as a dedicated video subsystem is required for adequate display performance dedicated hardware for real time data collection and signal processing is needed This is precisely t
30. delay is set by the Delay property of the Servo object Channel Selection The ServoBase objects InputChannels and OutputChannels methods are used to obtain access to the channel information objects for the module s input and output peripherals Generally the use of these methods is to specify the number of active input and output channels 67 Servo Applications Servo Timing Error correction and DSP BIOS interrupt e Analog Delay A D Conversion t1 t2 A D Read Servo Fin D A update gt 4 gt t4 t5 t6 t7 E gt lt y dh Analog Dela Free Time A 19 Dac Delay Period Minimum t Minimum Servo Time t10 TABLE 12 Servo Time Measurements Servo16 Module Interval Purpose Period in uS Period in uS w Dispatcher w o Dispatcher tl Adc Analog Delay 15 0 2 Adc Conversion 10 0 t3 Logic Interrupt Time 0 8 2 9 0 8 1 0 t4 2 13 13 7 11 8 5 A D Read Time 3 1 for 8 pairs 0 8 for 1 pair t6 Servo Calculation Time 2 t7 D A Write and Update plus 4 8 for 5 8 pairs module interrupt acknowl 3 2 for 3 4 pairs edge 2 3 for 1 2 pairs t8 Minimum Dac Delay Time 16 8 21 6 14 9 19 7 t9 Dac Analog Delay 15 0 t10 Total Servo Time 31 8 36 6 29 9 34 7 The analog delay inserts a fixed skew between input and output and does not affect update rate directly 68 A Servo Tutorial A Servo Tutorial The following section walks
31. dependent on Windows system DLLs such as Advapi32 dll Kernel32 dll Version dll Comctl32 dll Gdi32 dll User32 dll Ole32 dll and Oleaut32 dll These dependencies cannot be eliminated but will not cause a runtime error since Win dows systems allways provide these DLLs If the utility exposes DLL dependencies that you would like to remove follow the steps in the question above I created an EXE file and when I try to run it the system requires a DLL which I don t have 134 DSP Hardware Problems DSP Hardware Problems The I O seems like it is not connected or doesn t work Double check the connections to the I O connector The most common error is to connect to the wrong pins on the I O connector Check the trigger and timebase setups For the analog I O be sure that the timebase you have selected is running and the trigger method is valid No data can be collected on these cards without a timebase and an active trigger start trigger occurred stop has not yet occurred How can I tell what version of logic I am using The logic versions are reported by the FlashBurn applet When the applet is opened the current bus and analog logic version numbers are displayed The I O seems like it is not connected or doesn t work Double check the connections to the module I O connector The most common error is to connect to the wrong pins on module connector As described in the paragraph OMNIBUS I O Connector JP
32. description of the modes a module supports and the UI interfaces a module supports in each mode are listed in the online help with the description of each module Interrupt Handling In DSP BIOS all hardware interrupts are intended to be managed by a DSP BIOS hardware manager This manager allows user functions to be called as part of the interrupt process while still cooperating with DSP BIOS As a part of the configuration process the user can direct the HWI manager to call a user function Interrupts in a C Environment In a system using C this means of attaching interrupts leads to several difficulties A minor problem is that of name mangling C creates a new name for every func tion created in order to allow overloaded functions The DSP BIOS configuration does not understand the new name and results in a linker error There is a simple work around for this extern C void MyHandlerFunction void arg This declares to the compiler to create a standard C symbol name for this function _MyHandlerFunction which can be used by to the DSP BIOS configuration tool A more fundamental problem is that this mechanism does not allow the interrupt handling function to be changed during the life of the program Also this handler function may not be a class member func tion This restriction can make designing a class object that handles interrupts awkward The Pismo Solution The solution implemented in the Pismo environm
33. external interrupt 4 use the EDMA channel 4 For EDMA before a transfer can be initiated the parameters are loaded into the EDMA PRAM regis ters This is performed by the Submit method which loads the PRAM with the transfer information Unlike QDMA this does not start the transfer itself The transfer will be initiated when the associated hardware interrupt occurs If using software triggering use the Set function to initiate a transfer One Set call is required for each link block in the transfer Each Edma transfer allocates blocks from the PRAM pool to configure its Link blocks These blocks are a limited resource and the alloction may fail If the failure occurs the IsValid function will return false If a terminal count interrupt is not used a call for WaitForComplete will delay until the completion occurs TestComplete will return a flag that can be used to check completion without blocking Edma transfers may be configured to generate Terminal Count interrupts on completion of any and all blocks in the transfer Which TC bit is signalled is configured in each settings block This means there can be different handlers for different blocks in the transfer A user supplied handler similar to an interrupt handler can be associated with the terminal count inter rupt by a call to the TcIntInstall or LinkTcIntInstall method The Link function is used to install a handler for one of the link blocks as opposed to the pri
34. in as an argument and needs to be overwritten with the data to be written to all enabled output peripherals The data is passed in the same format as the peripherals produce for example paired data in channel order on the Servo16 module Similary the output format is that which the output peripherals will require If the channels output are different than those input or more or fewer the data is stored left justified within the event buffer for proper results to be obtained This may seem complicated but it is really rather simple in practice The job of this function is to take the input data and convert it into an output event using your own algorithm All other details are taken care of by the system Timebases The Servo object performs analog input and analog output just as device drivers do so it needs to allow timebase information to be passed into it A clock user interface object is manipulated in a fashion iden tical to the streaming analog drivers to initialize the servo conversion clock DAC Delay Some modules such as the Servo16 support a mode which delays the conversion of the DACs a fixed amount relative to the conversion clock The purpose of this delay is to give time for the Servo interrupt processing code to acquire analyze and produce the output data for the DAC to output This value needs to be tuned to match the time it takes your specific application to do this operation depending on the servo code The
35. informa tion and will override the default behavior of the applet Multiple instances of the terminal emulator may be invoked simultaneously in order to support installa tions utilizing multiple target boards Instances of the terminal emulator after the first loaded instance must be configured via command line switches in order to properly communicate with their associated target e board boardtype Use the board switch to force an instance of the terminal emulator to communi cate with a specific type of target board boardtype Supported boardtypes are those configured using the Code Composer Setup utility such as C64xx Rev 1 1 XDS560 Emulator 99 Applets cpu cputype Use the cpu switch to force an instance of the terminal emulator to communicate with a specific CPU on a target board Supported CPU types are those configured using the Code Composer Setup utility such as CPU_1 or CPU_A f filespec Use the f switch to force the terminal emulator to load and run the specified COFF file The filespec field should be a standard Windows file specification including both the path and file name as a unit to allow the user to force the terminal emulator to download the specified file to the target DSP board as soon as the terminal emulator is loaded This field is particularly useful in situations where the the terminal emulator is shelled to from within an other Host applications to facilitate
36. input and output from within target applications first instantiate a TermFile object as below TermFile File Then use the TermFile Open method to open the file for access on the host using the desired open attributes if File Open wave bin wtb cio lt lt nOutput file open error Program terminating lt lt endl cio monitor This method returns a Boolean indicating success if the file open is successful To store data into the file or retrieve data from the file use the Write or Read methods respectively For example transferred File Write char amp Buffer 0 10000 writes 10000 bytes of Buffer into the disk file When disk operations have been completed the file should be closed using the TermFile Close method 77 Communication to the Host 78 CHAPTER 7 Developing Host Code This section describes the Innovative Integration Windows host software develop ment environment for the M6713 Support for controlling the board and the net work libraries is provided by the native C class libraries named Malibu that can be linked into any application Sample applications show how to use the Malibu Library to initialize the hardware and communicate with to the hardware in opera tion Malibu for the M6713 is a native C class library It provides a limited amount of software to support threading buffer manipulation and other system functions The use of native C code w
37. long as the DSP card is functioning normally prior to re programming In this case an application provided with the Pismo Toolset allows the user to load new logic to the card over the PCI bus link Development Package Manual 129 M6713 Hardware A few precautions should be taken so that the card is not left in an unrecoverable state from an unsuc cessful programming attempt First the power should remain on during the entire logic burning process as partial rewrites will cause failures Second the card must communicate normally prior to burning the logic or a faulty logic image may be downloaded Third use only logic image files BIT provided by Innovative for the M6713 during the update process Warning Should the card ever fail during the update or if it is not functioning normally contact technical support at Innovative Do not attempt logic updates under this condition or the card could be rendered useless Updating the logic is only supported using the logic update program from Innovative included in the Pismo toolset Reprogramming the Interface Logic The Interface logic may be reprogrammed at any time on the M6713 No on card logic image is stored for the Interface logic and it must be loaded after each power up The Interface logic is loaded over the SelectMap Interface from the PCI bus or over JTAG The JTAG download is usually used during the logic development and debug process The SelectMap Interface is mapped
38. software maintenance downloads of development kit software and tele phone technical hotline support for a one year period 89 Applets ReserveMemoryDsp Each Innovative PCI based DSP baseboard requires from 2 to 8 MB of memory to be reserved for its use depending on the A rates of bus master transfer traffic which each baseboard will Spratt ee a generate Applications operating at transfer rates in excess of Matador fami 20 MB sec should reserve additional contiguous busmaster m memory to ensure gap free data acquisition System 2048 BM Region Size KE To reserve this memory the registry must be updated using 2048 7 Rsv Region Size KB the ReserveMemDsp applet If at any time you change the ee number of or rearrange the baseboards in your system then Total physical memory 255 you must invoke this applet found in Start Programs Mat Non paged pool size MB 4 ador ReserveMemoryDsp See the help file Reserve m UE MemDsp hlp for operational details Update Help Exit Ready Target Download Utility M6713Download exe The download applet is used to deliver known arme Co DN era operational DSP executables to DSP base a boards The utility may be used to start DSP _ rage applications on PC power up through its com mand line interface or to start a DSP applica tion from its GUI Windows user interface It is also capable o
39. source Data flow is dis continuous filling each buffer requested and stop ping ServoBase ServoIntf Continuous low latency analog capture and playback suitable for performance servo control applications Event at a time application data processing Stream FpdpInStream Burst Input from the FPDP hardware Stream FpdpOutStream Burst Output to the FPDP hardware Hardware Isolation and Independence The Analog and the Capture driver allow a single Stream to be used with different analog hardware In the M6713 for example Omnibus modules allow a wide variety of analog choices on a single baseboard Each of the Stream classes can be attached to a par ticular module and will automatically configure itself to use that hardware The Servo driver provides low latency interrupt driven data processing suitable for real time control applications albeit at the expense of high CPU usage It is currently implemented only for the Servo16 module The FpdpInStream and FpdpOutStream drivers provide communications with external Front Panel Data Port devices Stream I O Types There are two distinct categories of Streams implemented within Pismo Continu ous and Burst 35 About the Baseboard Continuous Streams use the model that the input or output is a continual process whether periodic or not Thus in order to avoid data loss when the application is momentarily busy internal buffering is pro vided so that the hardware may o
40. template allows the binding of stand alone function with an argument of any type In this example the onTimerFired function is bound to a timer interrupt Timer Interrupt Handler Function void OnTimerFired int arg Binder Object for Timer typedef void IntFtnType int arg FunctionHandler lt IntFtnType int gt TimerBinder OnTimerFired 0 This is the installation of the handler in the program Set up a real time clock to send commands to host on pep Target channel Irq Timer0 intTimer0 Timer0 Install TimerBinder Timer0 Enable false Turn on the clock at 5 hz DspClock Tclk0 50 0 150 0 Timer0 Enable true EDMA and ODMA Handling The TI C6000 processor supports a rich powerful DMA engine to move data without CPU intervention There are two kinds of DMA allowed One EDMA is full featured but can take some time to set up QDMA is 5 facility for quick DMA movement of data It is similar to a normal DMA transfer except that it is software triggered and performs only a single transfer No linking of blocks is permitted with QDMA It also is faster to initiate as only a few registers need to be set to start a new transfer Both kinds of DMA use a set of registers to define the configuration of a DMA transfer By properly configuring the settings many different transfer types can be performed such as interelaved data two dimensional arrays and so on See the TI Peripheral Library
41. the logic onboard the M6713 is capable of high speed PCI busmastering to move data between target and host memory This busmaster facility can be used to transfer data between host and target applications Enhanced DMA is used to move data between DSP memory and a logic based FIFO The firmware within the baseboard logic moves data between this FIFO and Host PC memory CPU Busmastering Implementation Packet Based Transfers The CPU busmaster interface implemented within the the M6713 transfers discrete blocks between the source and destination Each data buffer is transferred completely to the destination in a single operation Only if several transfers are requested at once will any delay in begin ning transmission occur as multiple requests have to be serialized through a single hardware system The data buffers transferred can be of different sizes Each requested buffer is interrogated for its size and fully transmitted At the destination the destination buffer is dynamically re sized to allow the incoming data to fit If the buffer given is too small for the data it will be reallocated to allow the trans fer Reallocating buffers can take some time for best performance buffers should be pre sized to be large enough for the largest transfer expected This will make allocation of buffers at critical times unnecessary Blocking Interface CPU busmastering uses a simple blocking interface for its send and receiving functions The sending funct
42. the relevant library header file in source code The header files define prototypes for all library functions as well as definitions for various data structures used by the library functions The files HdwLib h and UtilLib h should be included within all programs The file pspLib h should be included if a program uses functions in the DspLib signal processing library Example Programs Under lt baseboard gt Examples in the install directory the baseboard s example programs are installed Some examples have no host component and some use the terminal emulator applet as the host Host examples are written in C either under Borland Builder or Microsoft MSVC or both Target exam ples are written using CCS 2 x and DSP BIOS Note that not all of the examples listed below are avail able for all targets TABLE 10 Pismo Example Programs Example Host Target Illustrates AEcho terminal DSP BIOS Use of DSP BIOS drivers Analog output driven from emulator analog input AnalogIn terminal DSP BIOS Analog capture into DSP memory Rate limited by emulator Omnibus interface 61 Building a Target DSP Project TABLE 10 Pismo Example Programs Example Host Target Illustrates Al6D2AnalogIn terminal DSP BIOS Analog capture into DSP memory Tailored version of emulator AnalogIn example to exploit special mux features of A16D2 module AnalogOut terminal DSP BIOS Analog waveform playback from buffer in DSP memory emulator Rate l
43. to do movement to and from hardware to memory so that hardware interrupt rates rarely exceed 1 KHz The net effect is that virtually all of the bandwidth of the CPU is available for application processing without requiring any application DMA program ming Multitasking Friendly The Stream classes support efficient cooperation in multitasking applications Any function that requires a delay to complete will block using DSP BIOS functions that release other OS threads for efficient utilization of the processor Using Analog Streams in an Application The AnalogInStream AnalogOutStream and CaptureInStream all allow fast data movement between the application and the hardware in different modes Once associated with a hardware device they allow all configuration and control of the session to take place through the methods of the Stream Every Stream must consider these questions to make a functioning application Which stream to use Input vs Output or Continuous vs Burst Which hardware to use and in which hardware mode Which clock source to use and with what parameters Which triggering mode to use and with what parameters Once these are taken care of using the Stream to perform the Analog I O is a simple matter Consider the code fragment below which illustrates all of the steps necessary to fully initialize and stream a stream a continuous 1 kHz sine wave to the analog outputs present on a SD16 Omnibus module attached to a
44. true Q Submit while qdma_not_done Class Edma This class manages the posting of EDMA requests It contains functions to allow confi gration of a transfer initiating a transfer and completion notification via either an interrupt or a polling function Because the system state is saved in the object transfers can be predefined and saved to be posted at a later time An additional feature of EDMA is the ability to build complicated transfers by linking EDMA transfer blocks or by chaining EDMA transfers together For more information on EDMA see the TI Peripheral Guide As with all DMA objects the Edma object uses one or more internal DmaSettings object to define the transfer One block is allocated for the primary transfer and one for each linked block The Settings method provdes access to the primary transfer block s settings object The LinkSettings similarly allows to one of the link blocks s DmaSettings object Each of these can be used to call DmaSetting s own configuration functions or configurations can be loaded from a second object with the Load method 47 About the Baseboard Ed is a Edma object here we change the destination address Ed Settings DestinationAddr int dest_array 0x10 The EDMA transfer can be attached to one of a number of channels To attach an EDMA to a hardware interrupt use the channel with the same number as the hardware interrupt For example to attach an EDMA to
45. usage will be restricted to a 20 day trial period for the terminal emulator and other applets con tained in the Toolset To register fill out the contents of the Registration Form then click on the Regis ter Now button This will print a Registration report which must be faxed to Innovative Integration Innovative Integration will E mail you an Access Code which must be typed into the Registration Form for all the features to be enabled Terminal Emulator Menu Commands The terminal emulator provides several menus of commands for controlling and customizing its functionality These functions are available on the menu bar located at the top of the the terminal emulator main window Speed button equivalents for each of the menu options are also available on the button bar located immediately beneath the menu bar The following is a description of each menu entry available in the terminal emulator and its effects 94 RtdxTerminal The Terminal Emulator File Menu File Dsp Load Reload Save Print Exit FIGURE 3 RtdxTerminal File Menu g e File Load provides for COFF Common Object File Format program downloads from within the terminal emulator When selected a file requester dialog box is opened and the full pathname to the COFF filename to be downloaded is selected by the user Clicking Open in the file requester once a filename has been selected will cause the requester to close and the file to be dow
46. 38000 TABLE 2 C6713 DSP EMIF Control Register Initialization Values During the development process code may be downloaded to the baseboard using a JTAG debugger or via the PCI bus interface After development is complete the debugged application image may be downloaded from within a Host application using standard functions within the Malibu librares DSP JTAG Debugger Support Standard TMS320 family JTAG debugger operation is supported by each baseboard An external debugger connector is supplied that allows use of industry standard JTAG debugger hardware from Innovative Texas Instruments and other third party suppliers The DSP is the only device in the scan path Software for JTAG debugging and code development is TI Code Composer Studio 32 The Pismo Class Library The Pismo Class Library Innovative Integration s Pismo is a software class library allows the developer to fully exploit the advanced hardware features of the Innovative DSP product lines and to reap all the benefits from Texas Instrument s DSP BIOS Operating system Every board peripheral has been carefully integrated into the OS and its functionality encapsulated in a device driver that can readily be controlled within DSP BIOS applications including PCI interface analog I O external bus and memory serial ports and other I O devices Pismo provides extensive C class support for Dynamic creation and runtime control of tasks
47. 4 the pins on the module have a mapping to the end connector which means the pin numbers do NOT correspond one to one The module pin numbers in the Omnibus hardware manual are the pin numbers on the mating connectors on the card itself These internal pins are mapped to the MDR 100 type connector on the card end for user connections according to the Omnibus MDR 100 mapping table in the Hardware chapter How do I update the logic The logic may be updated using the FlashBurn program This applet is capable of updating the PCI bus coprocessor Loader and Talker images as well as the images for both the bus and analog FPGAs The utility also supports embedding a C6713 executable as generated by the PromImage exe utility The updating process is straightforward and is generally trouble free Two big mistakes that can occur are burning the wrong logic into the Flash and terminating the application before completion If you put the wrong logic into the card this may be recoverable by just repeating the programming process Pro vided that the logic file is from another version this will usually work If the file is completely wrong DO NOT POWER CYCLE THE baseboard So long as power is applied the logic image in the FLASH is not yet used and you can still reprogram the correct one into the card If the program crashes or terminates early for any reason during the programming sequence the card will almost certainly need to be returned to Inno
48. 49 249 DERE 85 CD29 IX D28 Sf DGND X D 39 TX D26 41 TX D25 DGND TX D24 DGNDI gg Sans TX D23 45 TX 022 da Den 47 TX D21 DGND IX b19 51 TX D18 TXDI7 DGND 32 2 TX 016 55 SEB X_D 57 TX_D14 NB 59 TX DT TX D12 61 SENO Di 63 TX D10 TXD 65 SIE DEDE 67 DGND IX D7 69 TX D6 Bons 71 TX D5 TX D4 73 SENE XD 75 TX D2 77 TX Di TX DO DGND Z DGND JH2 FPDP Receive Port Connector Connector type PSOE 080P1 S1 TG Number of pins 80 Mating connector P25E 080S TGF Manuf 3M 144 Development Package Manual Connector pinouts The following table gives the pin numbers and functions for the JH2 connector Direction from Pin Number JH2 Function M6713 1 3 4 5 6 8 10 Digital Ground Power 12 14 16 18 20 22 24 26 28 30 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 2 Rx Strobe I 7 Rx NRDY I 9 Rx DIRN I 13 Rx Suspend N I 17 Rx PIO2 I 19 Rx PIOI I 25 Rx PStrobe P I 27 Rx PStrobe N I 29 Rx Sync N I 31 Rx DValid N I 33 34 36 37 RxD31 RxD30 RxD29 RxD28 I 39 40 42 43 RxD27 RxD26 RxD25 RxD24 I 45 46 48 49 RxD23 RxD22 RxD21 RxD20 I 51 52 54 55 RxD19 RxD18 RxD17 RxD16 I 57 58 60 61 RxD15 RxD14 TxD13 RxD12 I 63 64 66 67 RxD11 RxD10 RxD9 RxD8 I 69 70 72 73 RxD7 RxD6 RxD5 RxD4 I 75 76 78 79 RxD3 Rx2D RxDI I Development Package Manual 145 Appendic
49. 7 simulator 1 IE ARM7 Simulator Little Endian ARM7 simulator RE ARM7 XDS510 Emulator ARM xds510 Ig ARM7 XDS560 Emulator ARM xds560 ARMS 05510 Emulator ARMS xds510 ARMS XDS560 Emulator ARMS xds560 ARM926E S Simulator Little ARMS simulator Ig 240 05510 Emulator C24xx xds510 Ig F240 05560 Emulator 24 xds560 WEF 2401 05510 Emulator C24xx xds510 2401 405560 Emulator 24 xds560 2402 05510 Emulator 24 xds510 IM 2402 05560 Emulator C24xx xds560 II F2403 05510 Emulator 24 xds510 EF 2403 XD5560 Emulator 24x xds560 FF 2406 05510 Emulator C24xx xds510 EF 2406 05550 Emulator C24xx xds560 Ig F2407 05510 Emulator 24 xds510 EF 2407 XD5560 Emulator C24xx xds560 Ir 241 05510 Emulator C24xx xds510 Ig F241 05560 Emulator C24xx xds560 IW F243 XDS510 Emulator C24xx xds510 Ig F243 XDS560 Emulator C24 xds560 27 Cycle Accurate Simulator C27xx simulator WE C27xx XDS510 Emulator C27xx xds510 IB C27xx XDS560 Emulator C27xx xds560 m n rav EN Factory Boards Custom Boards Create Board f Remove All Drag a device driver to the left to add a board to the system Finally the setup configuration should be saved After saving the configuration and shutting down the setup tool Code Composer Studio should launch successfully If you encounter difficulty launching CC
50. 800F0000 PCI 15 Async Ww Not used Ceo 0x80100000 PCI 16 Async Ww INT type Ceo 0x80110000 PCI 17 Async Ww INT polarity Ceo 0x80120000 PCI 18 Async Ww Burst count register INT4 Ceo 0x80130000 PCI 19 Async Ww Burst count register INT5 Ceo 0x80140000 PCI 20 Async Ww Burst count register INT6 Ceo 0x80150000 PCI 21 Async Burst count register INT7 Ceo 0x80160000 PCI 22 Async Ww Burst count register DMA int Ceo 0x80170000 PCI 23 Async Ww Not used Ce0 0x80180000 PCI 24 Async W PCI FIFO level control register Ceo 0x80190000 PCI 25 Async Ww Not used Ceo 0x801A0000 PCI 26 Async Ww Not used Ceo 0x801B0000 PCI 27 Async W Burst address register INT4 Ceo 0x801C0000 PCI 28 Async Burst address register INT5 Ceo 0x801D0000 PCI 29 Async W Burst address register INT6 Ceo 0x801E0000 PCI 30 Async Burst address register INT7 Ceo 0x801F0000 PCI 31 Async Burst address register DMA int Development Package Manual 103 M6713 Hardware Ceo 0x80200000 Intf 0 Async Ww Control reg Ceo 0x80200004 Intf 1 Async W SyncLink config Ce0 0x80200008 Intf 2 Async ClockLink config Ceo 0x8020000C Intf 3 Async WwW Module site trigger config Ceo 0x80200010 Intf Async W FPDP Rx BITIO Ceo 0x80200014 Intf 5 Async Ww FPDP Rx Config Ceo 0x80200018 Intf 6 Async Ww FPDP Tx Config Ceo 0x8020001C Intf 7 A
51. ALID NOT ASSERTED STROB I Mon Be 1 DVALID lt eo X en on lt a on NY 1 I XA b REPEATING FRAME DATA BOTH TYPES SYNC ASSERTED WHILE DVALID ASSERTED FIGURE 11 Standard FPDP Timing Diagram For Single Frame And Repeated Frame Data Fixed And Dynamic Size Repeating Frame Both of the Repeating Frame Data Types the synchronization event occurs coincident with the last data word transferred in the block before This means that reception of the first frame may not be synchro nized and it should be ignored by the receiving board Both cases requires the synchronization event occurs at the end of the block prior to that being synchronized while DVALID i e Data Valid active low is still asserted The difference between both repeating frames is that fixed size repeating frame permits only frames of the same length whereas the dynamic size repeating frame sizes to vary from frame to frame in an arbi trary manner CE Space Address Function R W Type 1 0 90002200 FPDP Tx PIO R W Async 1 0x90002300 FPDP Rx PIO R W 1 0x90002100 FPDP Rx Frame Count R Async 1 0x90000C00 FPDP Rx Config W Async 1 0x90000D00 FPDP Tx Config W Async 1 0x90000E00 FPDP Tx Frame Count W Async 2 0xA0000000 FPDP FIFO R W Burst 112 Development Package Manual C6713 McBSP Se
52. AVCC 5 500 15 System dependent AV 15V System dependent 3 3V 3 3V 250 mA 108 Development Package Manual FPDP Port I O Expansion TABLE 16 I O Bus Power Ratings Note The M6713 implementation of the OMNIBUS expansion slots deviates from the standard specifi cation in the way the power supplies are handled In order to provide a more compact form factor for the host card the M6713 does not supply discrete 12V power supplies as required by the OMNIBUS specification Instead it connects the AV rails to the 12V OMNIBUS power pins resulting in a 3V absolute overvoltage on those supply pins Designers of custom OMNIBUS modules intended for use with the M6713 should keep these revised power supply values in mind when planning circuitry which connects to these power supplies Please note that the AGND and DGND busses are separated on the M6713 and for proper ground refer encing they must be tied together on modules which use the analog power supplies any supply other than digital 5V 12V or 12V Innovative Integration recommends that either a ferrite bead Panasonic EXC ELSA35V or equivalent or a hard wire connection depending on expected ground return current and frequency content from the analog power supplies being used on custom modules to connect the two ground busses The current steering used by the separate grounds prevents high frequency digital noise on the DGND bus from polluting th
53. B BinView 92 Borland C C 58 C C Builder 11 E edit compile test cycle 58 E Mail 13 errors 59 Innovative Integration E Mail 13 Technical Support 12 Web Site 12 13 L Library Code 61 M Matador 11 T target applications 58 Technical Support 12 Troubleshooting 133 Pantera User s Manual 163
54. Close cio lt lt nProgram terminating lt lt endl cio monitor The loop continues to run until the user hits a key on the operating panel The main thread must be kept from terminating to keep the Servo alive The above code is a simple way to do it Then when the loop is finished we close down and exit Terminate streaming status Servolo Close Debugging Note It is important that the close method be called during debugging or that the CPU be reset for proper servo results We have found that if the servo is interrupted and the program reloaded 71 Servo Applications in CodeComposer directly the servo may be delayed an additional clock cycle Either performing a full download from the host program or allowing the servo to close avoids this problem Conclusion The power of the Pismo library and the servo application is that the details of configuring the analog are hidden in the objects provided yet can be configured if necessary The code that is writ ten is much clearer since the support code is concealed internally The application is simpler and easier to maintain because the code is almost entirely the important servo algorithm 72 CHAPTER 6 Communication to the Host Overview Many applications involve communication with the host CPU in some manner All applications at a minimum must be reset and downloaded from the host even if they run independently from the host after
55. DRAM The DSP accesses to the entire baseboard peripheral complement directly as memory mapped devices The baseboard supports DMA over the PCI bus at speeds up to 512 MB sec a packet message based bus interface two vari able function Omnibus I O module sites dedicated Front Panel Data Ports FPDP and SyncLink buses for inter board connectivity a precision DDS timebase to serve as an accurate programmable clock source from DC 25 MHz and a program mable digital I O port Because of the onboard DSP the baseboard is capable of performing data collection servo or other real time processing and data movement automatically without Host PC CPU involvement What is C Builder C Builder is a general purpose code authoring environ ment suitable for development of Windows applications of any type The M6713 host software library is a C class library that provides classes for control of the board hardware communication with the target board over the PCI bus link and support classes By using standard C classes multiple host platforms can be sup ported with a single code base sharing identical functionality and interfaces What is Microsoft MSVC MSVC is a general purpose code authoring environ ment suitable for development of Windows applications of any type 11 Introduction What kinds of problems can I solve Embedded data acquisition servo control stimulus response and signal processing jobs are easily solved with the M6713
56. DS510 Emulator The Configuration File combo box should be changed to Auto generate board data file with extra configuration file The Configuration File edit box should be changed to lt drive gt ti Drivers II PciPod cfg where drive is the letter for the drive onto which CCS 2 x was installed 21 Installation Under the Board Properties tab the I O port value for the driver should be set to virtual device address 0 21 Board Name amp Data File Board Properties Processor Configuration Startup GEL File s Property Value 0x0 Change property value as necessary in the right column Next gt Cancel Under the Processor Configuration tab processors of the appropriate type should be added to the Processors on the Board list box 21 Board Name amp Data File Board Properties Processor Configuration Startup GEL File s Available Processors Processors On Board Init Order MS 1 TMS320C8x1x BYPASS Add _ Add Mute _ Bemwe Processor Name cPu 2 Identify processors on your board by selecting a processor type from Available Processors changing the Processor Name as required and then select Add Single or Add Multiple Repeat for all processors on your board Next gt Cancel To configure for debugging the C6713 DSP highlight the TMS320C6x 1x then click the Add Single but ton to a
57. Echo out to file C Vista Examples VEcho file stored on the hard disk G and ascertains the complete DUMP completeted normally memory consumption by the DSP program Memory usage for each of the sections defined in the applications command file are tabularized and the results are writ ten to the Windows NotePad scratch buffer 91 Applets Target Project Copy Utility CopyCcsProject exe 21 0 copy all project settings from a known good Source Project template project into a new DSP Code Com E ET poser project This simplifies new project E Conejo E xamples Scope Wa C Destination Project Name Help development by eliminating the multi step pro pa EE cess of copying the myriad individual project settings from a source project in a newly cre ated project include HdwLib h include UtilLib h using namespace II void IIMain 0 t Binary File Viewer Utility BinView exe BinView is a data display tool specifi EI View c vista ynta cally designed to allow simplified view Q ma gt H4O 92 ing of binary data stored in data files or Time Frequency Text Summary Server resident in shared DSP memory Please lt lt Zombu 2 gt gt gt see the on line BinView help file in your Amplitude vs Offset Binview installation directory 20 cho 1 5 1 0 05 00 Counts e9
58. IFO level with a final terminal count interrupt when the packet move is completed Timers The M6713 provides a total of two counter timers as well as the DDS used for timebase generation These timers are independent and may be used as on board timebase generation for use in timing data acquisition servo controls real time counters and many other applications The counter timer func 116 Development Package Manual Timers tionality are two 32 bit timer channels on the C6713 processor and a 32 bit direct digital synthesizer DDS channel in the AD9851 This section discusses the AD9851 synthesizer in detail for more infor mation on the on chip timers see the 7M S320C6000 Peripherals Reference Guide SPRU 180 On chip Timers The on chip DSP timers are available for use as software timebases and interrupt generators Note that the C6713 does not support timer operation during JTAG emulation halt when the timers are pro grammed to use an external source When clocking from an external signal halting the DSP from a JTAG debugger will also halt the on chip timers This does not apply when the timers are run from the processor clock timers will run when the CPU is halted AD9851 Direct Digital Synthesizer The AD9851 direct digital synthesizer DDS is a precision programmable clock source which is capa ble of generating frequencies in the range of 0 to 25 MHz with a resolution of 0 019 Hz step Unlike a digital coun
59. M6713 User s Manual The M6713 User s Manual was prepared by the technical staff of Innovative Integration on March 20 2006 For further assistance contact Innovative Integration 2390 A Ward Avenue Simi Valley California 93065 PH 805 578 4260 FAX 805 578 4225 email techsprt innovative dsp com Website www innovative dsp com This document is copyright 2005 by Innovative Integration All rights are reserved VSS Distributions M6713 Documentation Manual M6713 book Rev 1 09 M6713 User s Manual CHAPTER 1 CHAPTER 2 CHAPTER 3 CHAPTER 4 CHAPTER 5 CHAPTER 6 Introduction 1 Introduction 11 Finding detailed information on Pismo and the Host Libraries 12 Installation 15 Host Hardware Requirements 15 Software Installation 15 Tools Registration 18 Hardware Installation 19 Code Composer Studio v2 x Setup 21 Code Composer Studio v3 x Setup 24 Borland Builder Setup and Use 27 About the Baseboard 31 DSP Baseboard Hardware Features 31 Digital Signal Processor 32 The Pismo Class Library 33 Analog I O Streams 35 Interrupt Handling 42 EDMA and QDMA Handling 45 Building a Target DSP Project 51 Building a Target DSP Project 51 Writing aProgram 57 Host Tools for Target Application Development 57 Edit Compile Test Cycle using Code Composer Studio 58 Anatomy of a Target Program 60 Example Programs 61 The Next Step Developing Custom Code 62 Servo Applications 65 U
60. O 2 19 20 49 Digital ground O power 50 7 9 11 13 15 Reserved Reserved NA 17 8 10 Digital 3 3V Power 14 Module trigger 0 O 16 Module trigger 1 O 18 Module trigger 2 O 21 Processor timer channel 1 O 22 Module trigger in External trigger 1 23 25 Analog 15V OMNIBUS O power 12V 24 CLKSO CLKS1 I 26 CLKRO CLKRI TO 27 FSRO FSRI 28 CLKX0 CLKX1 IO 29 External interrupt 1 External interrupt 3 I 30 DRO DRI I 31 FSX0 FSX1 IO 32 DXI O 33 48 Data bus 16 31 VO TABLE 39 I O Module Bus Connectors Development Package Manual 141 Appendices JP8 Digital I O Connector Connector type 0 1 double row shrouded header center bump polarized Tho mas and Betts 609 5027 Number of pins 50 Mating connector AMP 1 746285 0 ap de 55 in y D O CI i O C O CI CI CO opp EXT DIG RD CLK ip FU SP1 SEE Py 5E mi CO DGND The following table gives the pin numbers and functions for the digital IO connector Direction Pin Number JP8 Function from M6713 1 32 Digital I O bit 0 31 IO 33 36 Not used 37 External Digital Readback Clock latch falling edge I 38 Not used 39 47 Spare pins from PCI FPGA 49 DVCC digital 5 V Power 50 DGND digital ground Power TABLE 40 Digital I O Connector 142 Develop
61. S 3 x run the JtagDiag exe utility provided in your toolset to reset the debugger interface Then restart Code Composer Studio As a consequence of these steps a new ccBrd0 dat file will be created This file has been customized for the particular DSP target being used Borland Builder Setup and Use Borland Builder Setup and Use Following the normal installation of the Innovative Integration toolset components numerous VCL components and C classes are automatically added to the BCB IDE Additionally Innovative recom mends that the following IDE and project options be manually changed in order to insure simplified use and proper operation Automatic saving of project files and forms during debugging Invoke the Tools Environment Options dialog from the main BCB toolbar C Builder 6 File Edit Search View Project Run Component Database Tools GExperts Window Help D gt E a ec gt ES e El a Sta Environment Options iu v 2 Editor Options This will invoke the Environment Options dialog Environment Options Environment Variables Type Library CORBA C Builder Direct Interr Preferences Designer Object Inspector Palette options Compiling and running Editor files Show compiler progress Project desktop TT Beep on completion Cache headers on startup Docking Warn on package rebuild Auto drag do
62. Send method transfers both the bulk dataand header stored in an Innovative PmcBuffer object to the target Completion of a Send requires that a thread within the target DSP application be blocking within a call to Transfer Recv If the target has not done so or the system is otherwise unready both the sender and receiver will block and not return until the data is completely transfered out and the buffer arguments can be reused This makes these methods possibly unsafe to call from user interface code in a Windows application Since there is some internal queuing in the system the completion of the send may not mean that the target has actually recieved and processed the packet either In general it is best to call the functions Send and Recv from within background threads only on both Host and Target However the Malibu library implements a very efficient event callback scheme which can circumvent this requirement in some common cases See the ASnap example for an illustration To receive data and commands from the target use the Recv method This function will not return until the request is satisfied by receipt of a PmcBuffer from the target The Peripheralld field within the header of this buffer may be examined in order to retreive an application specific code describing the Development Package Manual 81 Developing Host Code nature of the data in the packet and the PacketSize field contains the size of the data payloa
63. To add Innovative help files if they did not automatically get added follow the instructions above except add help files All help files can be found at Program Files Innovative Documents manuals The files to be added should not include files with Pismo or Zuma in their names as these are target side help files I created an EXE file and when I try to run it the system requires a DLL which I don t have Depending on the settings your application has for building it may require certain DLLs such as borindmm dll When you try to run your newly created executable 133 Troubleshooting you may get an error such as Dynamic link library borlndmm dll can t be found One cause of this is when you have the project set for dynamic rather than static linking of the Borland VCL packages While dynamic linking can result in smaller EXEs dynamic linking can result in dynamic link error messages such as the one mentioned above when a DLL is unavailable or not find able by the applica tion program at invokation We recommend static binding of all executables To do this Bring up the Project Options menu by clicking the Project Options menu in Builder Select the Linker tab e Deselect the Use dynamic RTL option This will force the inclusion of the DLLs that are required by your application Another possibility is that you have built your application with runtime packages By building in this fashion
64. Used Ceo 0x8020007C Intf 31 Async R W Not Used Cet 0x90000000 PCI 0 Burst R PCI fifo data read Cel 0x90000000 PCI 0 Burst Ww PCI fifo data write Ce1 0x90200000 Intf 0 Burst R FPDP Rx fifo data Ce1 0x90200000 Intf 0 Burst FPDP Tx fifo data Ce2 0xA0000000 Not Burst R W SDRAM connecte d to logic Ce3 0xB0000000 Intf 0 Async R W IOMODO Ce3 0xB0004000 Intf 1 Async R W IOMOD1 Ce3 0xB0008000 Intf 2 Async R W IOMOD2 Ce3 0xB000C000 Intf 3 Async R W IOMOD3 Ce3 0xB0010000 Intf 4 Async R W IOMOD4 Ce3 0xB0014000 Intf 5 Async R W IOMOD5 Ce3 0xB0018000 Intf 6 Async R W IOMOD6 Ce3 0xB001C000 Intf 7 Async R W IOMOD7 TABLE 13 M6713 DSP External Memory Map M6713 Hardware Initialization Requirements The M6713 design requires the following values to be written to its hardware control registers in order to provide access to on board hardware Development Package Manual 105 M6713 Hardware Register Address Value EMIF Global Control 0x01800000 0x00003078 CEI Control 0x01800004 0x0000C041 CEO Control 0x01800008 0x21A28A22 CE2 Control 0x01800010 0x00000030 CE3 Control 0x01800014 0x11010420 SDRAM Control 0x01800018 0x6B338000 SDRAM Refresh 0x0180001C 0x00000350 SDRAM Extension 0x0180001C 0x000544a7 Interrupt Polarity 0x019C0008 0x00000000 TABLE 14 M6713 Bus Control Register Initialization Values These values are initialized automatically by C programs compiled under the M6713
65. a Bus FPDP Tx Interface Logic Spartan Ile 300k 600k A 32 bit Data Bus FIGURE 9 FPDP Overview The primary method used for moving data to the DSP and from the DSP memory is by using a DMA channel In most cases DMA delivers data in the most efficient method because it preserves DSP CPU bandwidth is more efficient at bus utilization and has a lowest interrupt latency Using CPU accesses or DMA single data point access may also be performed Since the FPDP FIFOs are burst memory devices the maximum write and read rate will be about 1 3 the speed of larger burst packets due to the transfer setup cycles inherent on the DSP burst memory access protocol Data Link Layer Specification Many applications of FPDP are high performance data acquisition and transfer systems These fre quently deal with multiple channels of data It is essential to have a method for identifying the channel associated with each item of data The method chosen is to allow for data frames where each frame is delineated by an assertion of the SYNC active low signal The data frame types defined by this standard are as follows 110 Development Package Manual FPDP Port I O Expansion e Unframed Data e Single Frame Data e Fixed Size Repeating Frame Data e Dynamic Size Repeating Frame Data NOT Supported by the Software yet Unframed Unframed Data interfaces are intended for use where the organization of th
66. ables given in the OMNIBUS Manual should be treated appropriately For exam ple the description of the OMNIBUS DIG module notes that the byte 3 direction control register for a module installed in site 0 is mapped to address IOMOD 2 3 This address should be literally inter preted as 0xB002000C where IOMOD2 is equal to 0xB0020000 and the offset adds decimal 12 three 32 bit words of offset IOMOD2 3 should NOT be interpreted as 0xB002003 since the offset is 3 32 bit words and not 3 bytes This addressing is most easily handled in C by using integer pointers and integer pointer arithmetic which will always result in the required address alignment For example the following code defines a pointer and accesses the byte 3 direction control register with the documented offset unsigned int pointer 0xB0020000 pointer 3 0x0 set byte 3 to output mode The actual accessed memory location is 0xB002000C due to the way pointer math is handled in C OMNIBUS Power The OMNIBUS interface provides six separate power supplies for use by modules along with two sepa rate ground return connections The following table lists the power supplies and their power ratings A separate digital 5V supply is provided along with separate digital grounds to minimize the digital noise present on the analog power supplies Pin Name Voltage Current Rating max DVCC SV digital System dependent AVCC 5V analog 500 mA
67. al is implemented as an out of process extension to Code Composer Studio Consequently it must be used in conjunction with CCS and a JTAG debugger it cannot operate stand alone 93 Applets sio File Dsp Form Help aaa a ama 2 Hello 0x123434661 Enter an integer 1 You entered 01 Enter a float 2 You entered 2 File wrote OK at 7 kB sec Filesize 4096 File read ok at 18 kB sec Press any key to display disk file COTTI Terminal Log Restarting DSP connected Running 36 813 FIGURE 2 Terminal Emulator Applet The terminal emulator is straightforward to use The terminal emulator will respond to stdio calls auto matically from the target DSP card and should be running before the DSP application is executed in order for the program run to proceed normally The DSP program execution will be halted automati cally at the first stdio library call if the terminal emulator is not executing when the DSP application is run since standard I O uses hardware handshaking The stdio output is automatically printed to the cur rent cursor location with wraparound and scrolling and console keyboard input will also be displayed as it is echoed back from the target The terminal emulator also supports Windows file I O using the TermFile library object Important Note Before using the terminal emulator you must register your Pismo Toolset Until you do so
68. ator set to I O Port 0x240 Drag a device driver to the left to add a board to the system Click this driver from the Available Factory Boards control within the setup utility and drag it into the System Configuration control Then right click on the newly created C671x XDS510 Emulator board icon to invoke the Properties Dialog for the driver Connection Properties Connection Name amp Data File Connection Properties Connection Name Auto generate board data file with extra configuration file C671xXDS510 Emulator C6000 XDS Texas Instruments 2x Configuration CCStudio_v3 10 divers IPciPod Diagnostic Uti Eg Diagnostic Arguments Within the Connection Name and Data File tab the Connection Name edit box should list C671x XDS510 Emulator The Configuration File combo box should be changed to Auto generate board data file with extra configuration file The Configuration File edit box should be changed to path spec DriversMIPciPod cfg where lt pathspec gt is the valid path specification to the folder into which CCS 3 x was installed including drive letter 24 Code Composer Studio v3 x Setup Under the Connection Properties tab the I O port value for the driver should be set to virtual device address 0 Click Finish to dismiss this dialog Connection Properties Ax Connection Name amp Data File Connection Properties Proper
69. cLink 2 Signal Selection Register Bit definitions The SyncLink master bit is controlled by the DSP at address 0x80200004 Write a 1 to bit 0 of this register to allow the M6713 to act as the SyncLink master thus making it the source of the synclink sig nals Only one master should be enabled between all the cards on the SyncLink bus to prevent conflicts The SyncLink signals are recommend for use below 2 MHz to a maximum of 8 TTL loads Termination may be required depending on the cable and impedance of the loads to prevent signal ringing More than eight loads may require additional buffering ClockLink is intended for higher speed signals that are usually card to card The ClockLink allows the M6713 to share clocks up to 80 MHz over short distances or farther for slower signals Flat ribbon cable performs well but twisted pair cable is recommended for the best signal integrity Note that the transmit receive signal wire pairs must be crossed to connect two cards together ClockLink may source a variety of signals as shown in the following table controlled by the Clocklink Configuration Register at 0x8014000 Bit Signal Output as SyncLink 0 0 DSP timer 0 1 DSP timer 1 2 External Interrupt Signal J2 128 Development Package Manual Bit Signal Output as SyncLink 0 3 Timer Clock 80 MHz 4 DDS Output TABLE 37 ClockLink Signal Selection Register Bit Definitions JTAG Test
70. captureInSt ream is a new type of driver that is used to emulate manual capturing of data to a buffer In this mode the analog hardware is inactive until a buffer is presented for filling When this occurs an acquisition is started that will fill the presented buffer after which data taking is stopped The process repeats for each buffer presented In the capture mode no processing is taking place when data is not requested This is a major difference from AnaloginStream Also if the buffer is sized to be smaller than the analog hardware s own FIFO or 38 Analog I O Streams storage each buffer will be a snapshot dump of the FIFO contents This makes capture useful for snap shots of very high rate analog input faster than the module can be read There is no way to take contin uous data sets larger than a single buffer in capture mode There will be a gap between any two captures AnalogInStream should be used for continuous applications Selecting and Configuring Hardware The M6713 supports Omnibus Modules allowing multiple hardware configurations on the same baseboard Modules are attached to an Omnibus site by a call to LoadModule Load Module onto site 0 LoadModule Omnibus mSite0 Omnibus mtSD16 Once a module is loaded it can be accessed by the stream object s Module method This returns a generic pointer that can be converted to an exact module pointer to allow its methods to be called The functions
71. ch as following plotting via Binview generate an audible tone Alerts if enabled alert conditions encountered during standard I O such as upon display of the ASCII bell character generate an audible tone Coff Load Group Controls within the Coff Load group box govern behaviour surrounding a COFF executable download e Reset Before if enabled the Code Composer Debug Reset DSP behaviour is executed before attempting to download the user specified COFF file Run After if enabled the Code Composer Debug Run behaviour is executed immediately following the download of a user specified COFF file Debugger Group Controls within the Debugger group box specify the target DSP with which RTDX communications is established Board specifies the board hosting the target DSP to be used in RtdxTerminal stdio communications This combo box is populated with all available board types configured using the Code Composer Setup utility Cpu specifies the identifier of the specific DSP to be used in Rtdx Terminal stdio communications This combo box is populated with all available CPUs present on the baseboard as configured using the Code Composer Setup utility Terminal Emulator Command Line Switches The terminal emulator also provides the following command line switches to further modify program behavior The switches must be supplied via the command line or within Windows shortcut properties see the Installation section for more
72. ck transfer is triggered by a second call to Set The Cache functions are required to assure that the cache and memory contents are back in syn chronization Linked and Chained blocks EDMA transfers may span multiple transfer blocks On the completion of the primary transfer the first link block is loaded into the primary block and initiated When this block completes the next linked block is loaded and so on A link block can form a loop but it is important to remember that the primary block can never be part of a loop Since it is overwritten by the first linked transfer this transfer can only occur once Because of this to make a loop of two transfers 49 About the Baseboard requires three blocks to be configured The primary block contains the first transfer the first link the second transfer and the third is a repeat of the first transfer that is linked back to the first link block Link blocks are allocated by a call to AddLink This call automatically configures the preceding block to link to this newly added block It returns the index of the newly added block that can be used in order to configure the link block To form a closed loop in a block chain call LinkBackTo This connects the final block in the chain back to the block whose index is given in the argument Transfer chaining is a mechanism for having a transfer trigger another on completion The ChainTo and ChainEnable methods set up a chaining relation be
73. cking Hide designers on run Pressing the Control key while Minimize on Run dragging will prevent window docking Tm Background compilation Enable autosaving of Editor Files and the Project Desktop so that project files are automatically saved each time a project is rebuilt and debugged Static binding of built executables Click on Project Options on the main BCB toolbar to invoke the Project Options dialog Then click on the Linker tab Uncheck Use Dynamic RTL checkbox Project Options for Default exe Directories Conditionals Packages Tasm CORBA Compiler Advanced Compiler een Pascal Linker Linking Warnings v Create debug information All Use dynamic RTL Selected Use debug libraries Generate import library PE file options Ranorata lih file Min stack size 27 Installation Next click on the Packages tab and uncheck the Build with runtime packages checkbox Project Options for Default exe Compiler Advanced Compiler C Directories Conditionals Packages Design packages Borland ActionBar Components Borland ADO DB Components Borland Base Cached ClientDataset Borland BDE DB Components Borland C Builder COM Server Com Borland C Builder Internet Explorer SAK lt c program files borland cbuilder6 Bin c Add Remove Runtime packages Build with runtime packages
74. cking while writing a one selects external hardware clocking If software clocking is selected then the port latches programmed for input will clock in the digital data present on the external pins at the beginning of a read cycle executed on the port data register 30 50 ns before the data is returned to the processor depending on processor clock speed If external clocking is selected then the port will latch data on the falling edge of the TTL sig nal EXT_DIG_RD_CLK at the digital I O connector The data will be held for the processor to read until the next low going edge of the EXT DIG RD CLK signal In the external hardware clocking mode read operations by the processor do not affect the contents of the digital I O latch The latched data may be reread as many times as is required and only another EXT_DIG_RD_CLK pulse will cause new data to be latched into the port Digital VO Timing The following diagram gives timing information for the digital I O port when used in external readback clock mode see above for details This data is derived from device specifications and is not factory tested text di g_rd_clk ext_dig_rd_clk gt data Development Package Manual 121 M6713 Hardware FIGURE 16 Digital I O Port Timing Parameter min ns 27 text_dig rd_clk TABLE 26 Digital I O Port Timing Parameters Digital IO Electrical Characteristics The digital IO
75. clude Greyed items denote invalid path Replace Add Delete Delete Invalid Paths Cancel Next click on the ellipses next to the Library Path edit box to invoke the Library Path editor dialog Add entries as shown below then click Ok to accept these edits BOCCE Ordered list of Library paths InnovativeCommon NLibXBcb BCB Projects Lib Greyed items denote invalid path Replace Add Delete Delete invalid Paths Cancel Help These changes insure that the standard Malibu headers and object files are available to projects during compilation Note that these paths may either be added to the default BCB project by editing these options without first opening a specific project or to specific projects after opening them The advan tage of the former is that the settings are automatically present on allsubsequently created projects Installation 30 CHAPTER 3 About the Baseboard DSP Baseboard Hardware Features The M6713 baseboard features a TMS320C6713 digital signal processor with 128 Mbytes of SDRAM memory To complement this core one or two modular Omnibus I O modules may installed into the onboard I O sites A wide variety of I O modules are available to address myriad application requirements The combined baseboard module system serves a variety of applications including servo applications data acquisition s
76. configured to use the C671x XDS510 driver for the C6000 This driver is named C671x XDS510 Emulator within the Code Composer setup utility In the figure below it is the second to last item listed in the Available Board Simulator Types column of the Setup program Code Composer Studio Setup x File Edit View Help system Configuration 3 Available Factory Boards C6711 Device Cycle Accurate Simu E C6711 Device Cycle Accurate Simu Eg C6712 Device Cycle Accurate Simu C6712 Device Cycle Accurate Simu 6713 Device Cycle Accurate Simu C6713 Device Cycle Accurate Simu E C6713 Device Functional Simulator E C6713 Device Functional Simulator 671 XDS510 Emulator BR C671x XDS560 Emulator Eg C67xx CPU Cycle Accurate Simulat 67 CPU Cycle Accurate Simulat 240 XD5510 Emulator EB F240 X05560 Emulator 241 05510 Emulator FB Factory Boards EW Custom Boards C67xx C67xx C67xx C67xx C67xx C67xx C67xx C67xx C67xx 67 C67xx C67xx F24x F24x F24x Cda Multiple simulator simulator simulator simulator simulator simulator simulator simulator 45510 xds560 simulator simulator xds510 45560 45510 Create Board C671x XDS510 Emulator Configuration file Location CACCStudio_v3 1 O drivers c671x_xds510_0x240 ccs Pre configued Board Description One TMS320C671x CPU connected an XDS510 Emul
77. d contained in the buffer The code below illustrates the typical sequence used in the receipt of a buffer from the target void TForml HandleDataAvailable Innovative PacketStreamDataEvent amp Event static PmcBuffer Packet static int LoginTally 0 Get the packet from the system Event Sender gt Recv Packet PmcDataAccess pda Packet Data Process the packet short PacketType pda Header gt Peripheralla In this code Packet is the PmcBuffer which will contain the data received from the target The call to Event Sender gt Recv Packet blocks until a complete data packet has been received from the target However as illustrated in the ASnap example provided with the board an asynchronous event notifica tion mechanism is provided which provides a callback to a user application funtion such as Hanale DataAvailable above when data is sent from the target to the host In that context the call to the Recv will complete immediately since data is available Once the packet is received it is common practice to examine the header to discover the type of mes sage sent then dispatch accordingly The call to pda Header gt Peripheralia reads the ID tag sent by the target from the PmcBuffer header Ordinarily the application uses a switch table to execute the appropriate code for each ID code that can be received For example switch PacketType case ccAcqusition Report gt L
78. dd CPU_1 to the scan path as device 1 in the Init Order Code Composer Studio v2 x Setup Under the Startup Gel Files tab the Startup Gel File combo box should be the board specific initializa tion GEL script for the target board Innovative supplies an appropriate board specific GEL initializa tion file in the root of the board specific libraries toolset directory For example for the M6713 this should be set to c Mnnovative M67 13MI6x gel Board Name amp Data File Board Properties Processor Configuration Startup GEL File s CPU Startup GEL File C lnnovativeS Sbc671 3e II6x gel ni Cancel Finally the setup configuration should be saved After saving the configuration and shutting down the setup tool Code Composer Studio should launch successfully If you encounter difficulty launching CCS 2 x run the JtagDiag exe utility provided in your toolset to reset the debugger interface Then boot the 6713 DSP using M6713Coff Download utility Then restart Code Composer Studio As a consequence of these steps a new ccBrd0 dat file will be created This file has been customized for the particular DSP target being used 23 Installation Code Composer Studio v3 x Setup To setup Code Composer Studio v3 x and activate the Innovative supplied Code Hammer JTAG board driver the Code Composer Setup Utility must be run Since the Code Hammer debugger is XDS510 compatible Code Composer Studio setup must be
79. e Output PCI Output gt DIO Input 4 L Ext Dig Clk Not DIO Read FIGURE 15 Digital IO Port Block Diagram The digital I O port controls are mapped into memory space using two addresses one to read write the digital I O data as a single 32 bit word one for direction control and for each byte of the port and con trolling the source of the clock edge used to latch input data into the digital I O port register The fol lowing table lists the addresses and their functions Function Address Digital I O Data Register 0x80010000 Digital I O Direction Control and input latch clock control 0x80000000 TABLE 24 Digital I O Control Registers The direction control register provides for software control of the drive direction of the port and the source of the input latch clock The least significant four bits of the register control the four bytes avail able on the I O port Bit DO sets the direction for the least significant eight bits if the port port bits 0 7 D1 the next least significant bits 8 15 D2 the next least significant 16 23 and D3 the most signifi cant 24 31 Each byte is individually controllable by writing a zero to select output or a one to select input to the respective bit in the direction control register For example if the value OxC were written to the direction control register bits 0 15 would act as inputs while bits 16 31 would act as ou
80. e clean AGND return Omnibus Data Rates Omnibus data rates vary from module to module Most modules can achieve a data rate of 48MB s on the M6713 as designed The Omnibus clock is 37 5 MHz on the M6713 so the typical module access is 3 clocks Custom designs where the Omnibus interface is replaced in the baseboard and module logic can achieve data rates of up to 200 MB s For these rates custom logic must be implemented that supports synchro nous data transfers top the M6713 Designing Custom Omnibus Modules Custom Omnibus designers should review the Omnibus Specification from Innovative We also mechanical drawings to assist customers in design Logic designs showing typical interfaces with FIFOs and memory decoding for FPGAs are also available from Innovative Contact technical support for this information FPDP Port I O Expansion The Front Panel Data Port FPDP feature provides two 32 bit data ports one for input and one for out put used for communicating with other I O devices or DSP cards These ports support a FPDP as defined in VITA 17 specification The FPDP bus is intended to provide data transfer between two or more VMEbus i e Versa Module Europa Bus boards up to 200MB s with the lowest possible latency FPDP is a 32 bit parallel synchronous bus wired by means of an 80 conductor ribbon cable connector at the front of the VMEbus board A single master generates a free running clock Data Strobe or PECL Data Strobe
81. e data is of no relevance and the FPDP RM i e FPDP Receiver Master or FPDP R i e FPDP Receiver interface does not need to be informed of a synchronization point in the data stream When using unframed data the sync pulse signal is not used roo STROB PSTROBE PSTROBE DVALID E 17 0 0 STROB D lt 31 00 gt VALID X lt VALID gt lt VAUD X VAUD SD GD DO vo gt vo X DVALID I SUSPEND l I I 4 FIGURE 10 FPDP Timing Diagrams for ALL Data Framing Types Single Frame The single Frame Data and the two Repeating Frame Data type definitions serve the requirements of interfaces which must pass data in response to an event such as multi channel A D converters devices that transfer fixed length data files This is accomplished by synchronizing data acquisition at FPDP RM or FPDP R interface to a separate signal sync pulse In Single Data Frame Data the synchronization is intended to occur between blocks As a result Single Frame Data compliant interfaces require that the synchronization event occurs prior to the data being synchronized before the assertion of DVALID i e Data Valid active low Development Package Manual 111 M6713 Hardware DI VAUD VALID DVALID a SINGLE FRAME DATA SYNC ASSERTED WHLE DV
82. ed to facilitate field deployment Win2K XP Users Only You must have Administrator Privileges to install and run the software hard ware onto your system refer to the Windows documentation for details on how to get these privileges To begin the installation start the host operating system and insert the installation CD The installation should autostart after you put it into the CD If the CD does not auto start click on the Start button then Run Enter the path to the SETUP EXE program located at the root of your CD ROM drive i e E SETUP EXE The setup program will run Select the appropriate tab From there select the appro Innovative Integration Product CD Innovative Integration Data Streaming PCI CompactPCI Products Stand Alone Products ISA Products Support Files The PCI and CompactPCI families of DSP base boards and their components are installed here Don t Autorun Again priate baseboard button depending on the type of hardware being installed The baseboard specific install screen will automatically come up You should see a screen similar to the following Note If you Conejo Installation Welcome to the Conejo installation program This program will install all the Conejo Armada Toolset components onto your computer Innovative Components to Install Integration real time E cu Conejo including Applets Examples and Drivers Armada including C Builde
83. efault 1 31 Enable NMI Interrupt NMI only 0 disabled default TABLE 28 External Interrupt Control Register Bit Definitions The selection bits in each interrupt control register are identical on all interrupts Set the corresponding bit true for each interrupt source that is used by that DSP interrupt For example if module 0 interrupt 0 is the interrupt source for the DSP external interrupt 4 then a 0x1000 must be written to the DSP inter Development Package Manual 123 M6713 Hardware rupt 4 select register at 0x80090000 Multiple interrupts sources may be enabled on shared interrupts Dedicated interrupts should enable only one interrupt source At reset no interrupt sources are enabled Bit 30 is the mode selection for acknowledged interrupts mode described in the section on shared inter rupts Conditioning for Interrupt Input Signals Each interrupt source has polarity and edge level selection so that nearly any interrupt source can be used by the DSP interrupts The interrupt polarity is controlled by the interrupt source polarity register at 0x80110000 with each interrupt source as numbered in the interrupt selection register above con trolled by a bit in the register Edge level selection allows the DSP to use either the interrupt source edge or level as the trigger condition for the interrupt Polarity selection is normally used to control the edge used rising or falling or the level high
84. emberHandler and Funct ionHandler templates It provides the interface the Pismo system uses to call the interrupt handler Class ClassMemberHandler Template This template allows the binding of a member function of a class object with the object to call and an argument of any type In this example the IsrHandler class is bound to a timer interrupt class IsrHandler public IsrHandler Binder this amp IsrHandler MyHandler amp Tally Tally 0 4 3 ClassMemberHandler lt IsrHandler unsigned int gt Binder void MyHandler unsigned int tally tally 1 if tally amp 0x7f 0 rtdx lt lt Isr tally lt lt tally lt lt endl private Data unsigned int Tally Instantiate concrete instance of above class IsrHandler Isr void IIMain Dynamically create an Irq object tripped from onchip timer 0 Irq Timer0 intTimer0 Bind and install the interrupt vector 44 EDMA and QDMA Handling Timer0 Install Isr Binder Program onchip timer 0 to signal at 100 Hz Timer0 Enable false DspClock Clock 100 150 true 0 Timer0 Enable true Use RTDX event log to monitor progress rtdx Enabled true rtdx lt lt Message from within IIMain endl Go to sleep while 1 TSK_yield In the above example the handler uses a int argument to pass out information from the interrupt rou tine Class FunctionHandler Template This
85. ent For more information on creating host applications see the section in this manual on host code develop ment This section supplies information on the use of the development environment in creating custom or semicustom target DSP software It is not intended as a primer on the C language For information on C C language basics consult one of the primer books available at your local bookstore Components of Target Code cpp cdb cmd pjt In general DSP applications written in TI C require at least three files a cpp file or source file containing the C source code for the application a cmd file or command file which contains the target specific memory map and build data needed by the linker a cdb file or command database file which specifies the properties of the BIOS operating system used within the application and a pjt file project file which centralizes all project specific options settings and files There may also be one or more asm assembler source files if the user has coded any portions of the application in assem bly language Edit Compile Test Cycle using Code Composer Studio Nearly every computer programming effort can be broken down into a three step cycle commonly known as the edit compile test cycle Each iteration of the cycle involves editing the source either to create the original code or modify existing code followed by compiling which compiles the source and crea
86. ent is to take over all interrupt handling by providing a full set of standard handlers The user then never needs to work in the CDB edi tor to provide handlers The standard Pismo handlers contain code that will call a user s installed inter rupt handler function if one is provided While this adds a small amount of latency to the interrupt the DSP BIOS overhead per interrupt call is still much greater and dominates the total time per interrupt In 42 Interrupt Handling general the BIOS environment is not suited for extremely high interrupt rates Luckily the use of DMA to aquire data from FIFOs on peripherals means that high rate interrupt handlers are not needed Pismo uses a special object a Binder to group a handler function and its arguments in a way that can be properly called by the standard handler One form of Binder is used to attach a stand alone function and its arguments another form allows the binding of an Object a member function of that object and its arguments This form of binder can allow a class object instance variable to act as a handler for inter rupts Here is an example from the Messages example of defining a binder for a timer interrupt Timer Interrupt Handler Function void OnTimerFired int arg Binder Object for Timer typedef void IntFtnType int arg FunctionHandler lt IntFtnType int gt TimerBinder OnTimerFired 0 And attaching the binder to an interrupt
87. erate and Put Generate uses signal generator classes to write a signal pattern into the buffer put enqueues the data for output Data output will not actually begin until the buffer queue is essentially filled with data This avoids under runs of the output For input Streams the cet method starts streaming at the first call These buffer methods should be repeated to keep the streams flowing After use of a device is complete it is closed using the Stream Close method Note that in the above example the type of module used matters very little in the finished application Simply by changing a single constant this code can be rebuilt to work on any module that supports Ana log output The module specific details are handled by the Pismo library internally Selecting the Stream Object Each Stream object is used to manage input or output on a single Omni bus module Multiple module applications need to use separate instances of the stream for each module site The Stream object is associated with a module site by the constructor allowing access to the hard ware for configuration AnalogInStream AIn Omnibus mSite0 The analogInSt ream provides continuous streaming input All data is delivered to the ring of internal buffers and from there to the application AnalogOutStream allows continuous streaming output to an output device The application must deliver data as fast as it is consumed to avoid buffer underruns The
88. es TABLE 42 FPDP JH2 Rx Port Connector JH2 P50E 080P1 S1 TG DGND DGND N POND RX DIR_N 3 3V RX susPeND_PEND STROBE S R17 DNP RX STROBE GUB R19 RX 2 U13 169 169 RX PIO1 3 30 MC100EPT21D Q 8 1 R18 0 7 d net 2 PSTROBE P p i 6 Ne a 3 CPSTHOBE N GND VBB X DVALID N DGND RX D31 R21 249 028 DGND 027 024 DGND RX 023 020 DGND RX 019 016 DGND 015 012 RX 011 RX 08 DGND RX D7 04 DGND RX_D3 RX DO 146 Development Package Manual Connector pinouts JP12 SyncLink ClkLink The SyncLink connector allows M6713 to synchronize to external hardware or other Innovative cards Connector type 0 1 double row shrouded header Number of pins 14 Mating connector AMP The following table gives the pin numbers and functions for the SyncLink ClockLink connector Pin Number JP12 Function Direction from M6713 1 Clocklink Out O 2 Clocklink Out O 3 Clocklink In I 4 Clocklink In I 5 Synclink bus pin 2 6 Digital ground Power 7 Synclink bus pin 1 8 Digital ground Power 9 Synclink bus pin 0 10 Digital ground Power 11 Synclink bus pin 3 12 Synclink bus pin 5 13 Synclink bus pin 4 14 NC TABLE 43 S
89. es a single interrupt for all TC inter rupts and the system will call the installed handler when the particular bit in the TC register becomes set The handler installer requires an Interrupt Binder Object See Interrupt Binder Templates on page 44 as an argument to associate a handler function or method and argument for the interrupt for warding mechanism of Pismo A second function TcIntDeinstall removes any installed handler Once installed TC interrupts may be enabled or disabled by a call to TcIntEnable 46 EDMA and QDMA Handling The following example shows a full Qdma transfer with TC interrupt handling In this example a class member function is bound to handle the interrupt response class Dmalsr public typedef void IntFtnType void fallow DmaIsr Binder this amp DmaIsr MyHandler NULL void MyHandler void fallow qdma_not_done false ClassMemberHandler DmaIsr void gt Binder Dmalsr Isr void IIMain DmaSettings Cfg Cfg Priority 1 ElementSize 0 SourceIncr 1 DestinationIncr 1 Cfg TCInt true TCCode 0 Cfg SourceAddr int src array DestinationAddr int dest array Cfg ElementCount 100 ElementIndex 1 Cfg FrameCount 0 FrameIndex 1 Qdma Q Cfg This QDMA operation will trip a terminal count interrupt when all data has been moved Q TcIntInstall Isr Binder InitArrays Q TcIntEnable true qdma_not_done
90. etails on all available classes methods and events FIGURE 1 Some Classes in Malibu Board Library Features Event Handlers Often in a library it is useful to call user provided code at various points in the opera tion of the object In traditional C pointers to Callback functions were often used for this purpose Malibu extends on the callback concept through use of events In event driven programming user events are a key part of your application logic An event is a mechanism that links an occurrence to some code More specifically an event is a closure that points to a method in a specific class instance From the application developer s perspective an event is just a name related to a system occurrence such as OnProgress to which specific code can be attached For example when an error is detected dur ing a system operation the OnError event might be called User events correspond to the elements in your application For example during a download operation the OnDownloadComplete event is called by the system following delivery of the last portion of the executable image to the target DSP This event can be programmed within application code to update the user interface in an appropriate manner The code you write to respond to events is called an event handler Events and their user written handlers called closures are a key part of the Malibu environment They give us the ability to assign an event handler for sy
91. f downloading a minimal boot application which is convienient when attempting to start a new Code Composer Coff File FpdpSData out debug session after having initialized the JTAG scan path with JtagDiag exe Opened target number 0 Logic Download Utility M6713LogicLoader exe The logic download applet is used to deliver CI known operational logic images to either of Target the logic devices installed on an M6713 base pem board The utility may be used to configure estesbegsWeziaMeziacinieao SSS firmware either through its command line Load interface or from its GUI Windows user inter Event Log face The former is often convenient during PC boot up This application supports configuration of the onboard Spartan3 logic device from an EXO file produced by popular logic design tools including Xil inx s It is essential that the Spartan be programmed before attempting to download COFF images to the DSP since some of the baseboard peripherals are dependent on the personality of the configured logic Logic Update Utility M6713VsProm exe Logic Update Utility M6713VsProm exe The Logic Update Utility applet is designed to allow field parara upgrades of the logic firmware on Modular baseboards ere The utility permits an embedded firmware logic update A file to reprogrammed into the baseboard Flash ROM o zl Boa
92. formation Options Tab The Options tab seen below contains controls to allow user customization of the appearance and operation of the terminal emulator 97 Applets RTDX Terminal CPU_1 ra xl File Dsp Form Help alzas a aaa e 2 Terminal Log Options Display Sounds fo Errors Polling Int olling Interval mS 7 Suspend AlwaysOnTop Pause on Plot a Clear On Restat Log Scrolled Text Coff Load Font Debugger Heterogeneous XDS560 Multi Target Y Board 05400 Buffer Size bytes CPU 1 zi Cpu fi Rtdx Buffers Resetbefore Run after Console initialized 240 10 000 FIGURE 7 RtdxTerminal Options Display Group Controls within the Display group box govern the visual appearance of the terminal emulator as detailed below Polling Interval specifies the period in milliseconds between queries for data received from the DSP via the JTAG RTDX interface Lower numbers increase performance but increase Host CPU load Always on Top specifies that the terminal application should always remain visible atop other appli cations on the Windows desktop This check box controls whether the terminal emulator is forced to remain a foreground application even when it loses keyboard focus This is useful when running stdio based code from within the Code Composer environment when it s preferable to make termi nal visib
93. ge this interrupt control is imple mented as part of the peripheral driver under DSP BIOS External The M6713 supports two external inputs via SMB connectors J1 and J2 that may be used as input tirg gers clocks or interrupts These inputs are 50 ohm terminated as selected by jumpers see table 2 jumper on 50 ohm input or unterminated 100 ohms in series to the FPGA pins These pins are a Inputs for Clocks and Interrupts 126 Development Package Manual Multi Card Timing Synchronization direct connection to the FPGA and is expected to be LVTTL compatible The inputs are 3 3V tolerant Overvoltage protection for ESD and transient protect limits the inputs to 0 to 3 3V External Jumper Input Impedance JP2 Ext Clk 0 No jumper Hi Z Jumper 50 ohms JP11 Ext CIk 1 No jumper Hi Z Jumper 50 ohms TABLE 33 External Clock Input Termination Jumper Settings Within the standard logic either of these inputs may be used as a trigger or clock source and may be shared to other cards over the synclink clocklink connections Custom logic designs may use the con nections as either inputs or outputs Multi Card Timing Synchronization The M6713 has several features to support multi card synchronization and clock sharing Synclink is a simple TTL bus that allows the M6713 to send or receive clock and trigger signals to other cards while ClockLink is an LVDS input and output pair allo
94. guide for more information on configuring EDMA and QDMA 45 About the Baseboard The QDMA has a single set of configuration registers so only one QDMA may be in progress at the same time The EDMA has a pool of blocks that may be used to define simultaneous complex transfers Class DmaSettings The DmaSettings class manages an image of the settings registers used to config ure a QDMA or EDMA transfer It provides properties to read and set the individual fields of the regis ters saving the user the effort of masking bits and shifting data It even provides functions that preconfigure some commonly used transfers saving even more programmer effort The following code fragment shows how the setter functions are used to set up for a transfer The Dma Settings class returns a reference to self on all setter functions allowing multiple parameters to be set on a single line DmaSettings Cfg Cfg Priority DmaSettings priHigh ElementSize DmaSettings is32bit Cfg Sourcelncr DmaSettings Incr DestinationIncr DmaSettings Incr Cfg TCInt true TCCode 1 FrameSync true Cfg SourceAddr int amp src_array 0 DestinationAddr int dest_array 50 Cfg ElementCount 50 Element Index 1 Cfg FrameCount 0 FrameIndex 1 Class Qdma This class manages the posting of Qdma requests It contains functions to allow configra tion of a transfer initiating a transfer and completion notification via either an inter
95. he focus of the M6713 baseboard a high performance state of the art dedicated digital signal processor coupled with real time data I O capable of flowing data via the PCI bus Finding detailed information on Pismo and the Host Libraries Information on Pismo and the host BoardLib is available in a variety of forms e On line Help Innovative Integration Technical Support Innovative Integration Web Site www innovative dsp com Online Help The on line help system for the Host support classes to control the M6713 are contained in the Ma1 ibu hlp help files placed into the Program Files Innovative Manuals directory tree during the default installationIt provides detailed information about the C control objects and usage examples An equivalent version of this help file in HTML help format is also provided Malibu chm for use within the MSVC context The documentation for the target side DSP Pismo C libraries is avail able in M6713Pismo hlp M6713Pismo chm Innovative Integration Technical Support Innovative includes a variety of technical support facilities as part of the M6713 toolset Telephone hot line supported is available via Hotline 805 520 3300 8 00 5 00 PM PST 12 Finding detailed information on Pismo and the Host Libraries Alternately you may e mail your technical questions at any time to techsprt innovative dsp com Innovative Integration Web Site Additional information on the In
96. he number of points transferred An interrupt is given o the host for each packet as determined by the header Packet Format The packet header consists of a 24 bit field for the packet size and a Peripheral Device Number The packet size is given in 32 bit words and includes the 2 word header The Peripheral Device Number may be used by the DSP or host to implement further protocol such as channelization or message passing but is simply ignored by the PCI controller FIGURE 13 PCI Packet Format Word Description Development Package Manual 115 M6713 Hardware 1 Bits 31 24 Peripheral Device Number used for backend processing Bits 23 0 Packet size in 32 bits including header 2 Not used 3 N Data Word Host DMA Software Support Software methods are provided to control the PCI busmastering pro cess The software implements all the controls necessary to efficiently use the PCI bus mastering capa bilities of the M6713 Interrupts are serviced in the device driver providing maximal efficiency for the host Credit and data management by the software allow the applicaiton to interact with the M6713 by managing credit for the data flow The M6713 Development Package contains extensive driver support for the PCI bus environment Users are strongly encouraged to make use of the standard software drivers in order to speed product development If you wish to target an operating system not supported by
97. he reference during link time and will error out This error will be displayed on the screen in the build output window Note Be sure to start the terminal emulator BEFORE starting Code Composer to avoid resetting the DSP target in the midst of the debugging session If the terminal emulator is not yet running and you wish to run the Test object file perform the following steps 1 Execute Debug Run Free to logically disconnect the DSP from the debugger software 2 Terminate the Code Composer Studio application 3 Invoke the terminal emulator application 4 Restart the Code Composer Studio application This outlines the basics of how to recompile the existing sample programs within the Code Composer Studio environment Anatomy of a Target Program While not providing much in the way of functionality the test program does demonstrate the code sequence necessary to properly initialization the target The exact coding however is very specific to the LI C Development Environment target boards and is explained in this section in order to acquaint developers with the basic syntax of a typical application program HELLO CPP Test file program for target board include hdwlib h include utillib h TIMain Cio init cio Hello World endl cio lt lt nEchoing keystrokes lt lt endl char key do cio gt gt key cio lt lt key lt lt flush while key
98. he target application may not be fully initialized and running when RequestCoffLoad is fin ished and even after the OnDownloadComplete closure is called since the target initialization routines could be arbitrarily time consuming The best approach is to have the host application wait for some message to be sent from the target program which indicates that the target is fully prepared for further communication Target Host Packet Communication Most applications require some form of contact between the target application and the host application during the running of the program The M6713 has a bi direc tional data channel configured that can be used to send commands and bulk data between the Host CPU and the C6713 DSP The communication protocol on this channel supports sending special data blocks consisting of a small header plus an arbitrarily large data packet These data packets are of type Innovative PmcBuffer The header within a PmcBuffer contains two words of information designated the Peripheralld and the PacketSize The Peripheralld is an arbitrary tag value stored into the header by the sender intended to allow the receiver to uniquely identify the purpose and contents of the packet The PacketSize field is automatically updated by the driver to accurately reflect the size of the data portion of the packet in 4 byte words This field allows the receiver to determine the amount of data payload communicated within the packet The
99. hreshold mode supports two interfaces VoltageThreshold and ConfigurableTrigger Volt ageThreshold configuration allows the threshold to be set in volts with the ThresholdLeve1 method In the above example the hardware is configured to trigger at half a volt The ConfigurableTrigger UI interface allows signals to be specified as Type edge or level and Polarity positive or negative In the example above the trigger is configured for a positive going edge This means that when the signal crosses the threshold from below to above the start trigger will fire A crossing from above the thresh old to below it will not fire the trigger Each line can be read from the inside out Stream gt StartTrigger returns the current start trigger UI object This object is input into the trigger conversion function Con igurableTriggerPtr and con verted into the configurableTrigger interface Finally the Type method of this class is called to set the trigger type to ttEdge The trigger modes a module supports and the UI interfaces its supported modules support are very mod ule dependent It is quite common to have to use several conversion functions to configure a trigger mode It is also common for a trigger to be unconfigurable exposing no trigger UI classes Similarly many modules support several triggering modes Other modules support only the default unconfig urable combination of no Pretriggering Always start Never stop and no Retriggering The
100. iciently transfer data to one another using DMA operations over the PCI bus as a bus master The DMA controller uses a data packet protocol and credit based flow management to control the data movement and provide an effi cient interface The controller and its software layers simultaneously support both high speed sustained data transfers and on demand data transfers through use of the unique credit management system and interrupts As shown in the following diagram the DSP communicates with the PCI DMA controller through a pair of 2kB FIFOs These FIFOs are mapped into the DSP memory space as burst memories and sup port transfer rates of up to 300 MB s to the DSP The DSP transfers data based upon a DMA interrupt driven by the availability of data for each packet transferred DSP DSP EMIF Int Int BKB BKB Ff PCI DMA Credit gt PCI Interrupt PCI Bus FIGURE 12 PCI Interface Block Diagram PCI DMA Data Rates The DMA transfer rates vary according to the bus speed buffering bus efficiency and other factors For our software system with the M6713 here is a guideline of what can be expected for systems we tested 114 Development Package Manual PCI Interface Typical PCI Bus Data Theoretical Sustained DMA Clock Width Rate MB s Rate MB s Comments This is a typical desktop PC Rates vary from 50 to 120 dependi
101. ides a C language compatible stan dard I O terminal emulation facility for interacting with the Termlo library running on an Innovative Integration AE Scan ecc lbirdudereche 1 MPcPod p i Revet the controles This uti val load the emulator adapter IPcPod df Thes hs selec 510 class product axDS Thit wall operate zloj x Scan Opis Hop Configuiatice 2 Ces Vernon PPs cio F Use cerigastionfie 0 Pon iddet a b sicas f Data Patten RewtScaPuh ScanConbolee 7 Sean Path Integrity Broken Pah Embedded Hardware Use Emulator Progam Clock rd The test forthe JTAG OR bos ded Ranga Miz 5 None C Center Dondi eed The JTAG DA bypass The scampati appears i the scarrpath consists of or Probe returned result code 0 J target DSP processor Display data is routed between the DSP target and this Host the terminal emula tor applet in which ASCII output data is presented to the user via a terminal emulation window and host keyboard input data is transmitted back to the DSP The terminal emulator works almost identically to console mode terminals common in DOS and Unix systems and provides an excellent means of access ing target program data or providing a simple user interface to control target application operation dur ing initial debugging RtdxTermin
102. ill make the use of the libraries when ported to other plat forms straightforward since the interface for all classes will be identical on all plat forms Host software development is directly supported under both the Borland C Builder 6 0 and Microsoft MSVC v7 0 environments for generating 32 bit Win dows applications While the supplied DataXfer example uses the Borland VCL or MSVC foundation classes for the user interface the Malibu class library iteself is not dependant on any particular compiler specific frameworks Please Note Only Windows application development is currently supported by the Developer s Package Foreign operating systems are not currently supported The BoardLib library All target interactions are implemented bia calls to the supplied Malibu libraries which are bound into a target executable via supplied static import libraries Development Package Manual 79 Developing Host Code The libraries supply classes that provide the means to operate the M6713 and support classes for com mon program functions such as threads buffers and inter thread synchronization Class Name Description M6713 Baseboard support class TransferPacketHeader Command Packet parsing MemoryBuffer Buffer management Event Thread Synchronization Thread Thread class Note that this is just a partial listing of available classes within the Malibu libraries See the online help file Malibu chm or Malibu hlp for d
103. imited by Omnibus interface AnalogCapture terminal DSP BIOS Full rate analog capture to FIFO memory on suitably emulator equipped Omnibus modules AWave terminal DSP BIOS Analog output driven by local signal generator objects emulator FftFloat terminal DSP BIOS Use of Fourier class to perform foward and inverse FFTs emulator FirFloat terminal DSP BIOS Use of BlockFir class to perform FIR filter functions emulator Edma terminal DSP BIOS Use of Pismo Edma and Qdma wrapper classes with emulator installable interrupt handlers Files terminal DSP BIOS Use of C Standard I O library emulator DataXfer BCB DSP BIOS Use of Pismo Host lt gt Target message and data packet MSVC passing via PCI bus interface FpdpEcho terminal DSP BIOS Use of FPDP driver to flow data through loopback con FpdpPio emulator nector Bit control of FPDP port via driver methods DisplayTest terminal DSP BIOS Features of RamTex graphics library for OLED display in emulator TOPO enclosure Numeric Test terminal DSP BIOS Features of numeric math library curve fitting statistics emulator etc Servo terminal DSP BIOS Servo application example using Servo class Not avail emulator able for Vista or Delfin Swi terminal DSP BIOS Use of Pismo SoftInt class for software interrupts emulator Timer terminal DSP BIOS Use of Pismo ClockBase objects for timebase control emulator DioData terminal DSP BIOS Use of baseboard digital I O emulator The Next Step Deve
104. in 1 0 1 5 0 10 20 30 40 50 60 70 80 90 100 Offset Analyze Ch 7 Samples 4096 92 DEF Conversion Utility DefConvert exe DEF Conversion Utility DefConvert exe The DefConvert exe applet is a simple utility to aid in the use of DLLs written using Borland Builder from within Microsoft Visual C C application programs DefCon vert parses a user specified C header file and DLL in order to create a MSVC compatible DEF file This DEF file is then submitted to the MSVC LIB utility in order to generate an MSVC compatible import library LIB Complete functionality is supplied in the DefConvert hlp file DLL Conversion Utility 101 xl Options Help mu File for DLL File r Msvc Compatible Output Files Def File del Import Library Make Output Files Log Ordinals Functions Ready Scan Path Diagnostic Utility JtagScanpath exe The JtagScanpath exe applet is a simple GUI front end to the powerful Texas Instruments XdsProbe exe com mand line utility The utility is of value in debugging JTAG debugger installation and reliability problems The tool is capable of performing comprehensive scan integrity tests for both the Innovative Code Hammer and the TI XDS560 emulators The complete reference to available tests and features is listed on the application Help tab RtdxTerminal The Terminal Emulator This applet prov
105. ine pmAcqusition ProgressBar gt StepIt StatusBar gt Panels gt Items 1 gt Text Rx String RcvMessageTally Cache gt Write pda IntPtr pda Size sizeof int break 82 Development Package Manual Host Example Program for the M6713 Baseboard When the ccacqusition code is received this application logs the contents of the data payload in the received buffer to disk The call to cache gt write pda IntPtr pda Size sizeof int calls the Host OS to perform a disk write from the data buffer starting at address paa tntptr which is the address of the first byte of the data payload within the packet cast as an integer pointer The number of bytes in the payload are returned by the phrase pda size sizeof int The target software uses a similar method for the other end of the connection The Transfer class has identical Send and Recv methods of its own for the same purposes Host Example Program for the M6713 Baseboard Overview Command and Data Packets On this baseboard using PCI bus the way to transport information is by means of asynchronous packets of data that are transferred and decoded by the destination These mes sages may be of varying sizes allowing large messages to be efficient in sending bulk data while allow ing small command messages to be mixed into the data stream When delivered to the destination the messages can be parsed and can result in any kind of pr
106. ion will not return until the transfer has completed and the buffer is ready for reuse Similarly the receiving function waits until data has arrived from the data source and trans ferred into the data buffer before returning At this point the buffer is ready for use This blocking allows sequences of transfers managed by a simple sequence of calls to transfer functions Since the transfer functions are blocking they are best avoided in the main user interface thread of a Windows application The GUI will be appear to be frozen until the transfer has completed For best results the data transfer functions should be placed in separate threads on the target and host applica tions In fact each direction of transfer should have its own thread so that the two directions of transfer can interleave as much as possible The example programs CpuBmIn and CpuBmOut illustrate the use of separate threads for data transfer Maximum Transfer Size The largest transfer allowed is half of the total size of the Dma Buffer allo cated by the INF file when the driver is installed Half of the memory is dedicated to each direction The default buffer size in the INF is 0x200000 bytes so the maximum transfer is 1 Megabyte Host Armada Library Support for CPU Busmastering The Host M6713 object contains the following two methods to support CPU Busmastering Block Transfer System Methods 74 CPU Busmastering Interface bool Send int Chan
107. ions use large buffers and large chains of these buffers to allow data to be moved from the hardware into memory without CPU intervention Thus data can be acquired at high rates but the system only needs to be involved at relatively rare intervals to process a block of data These applications are very natural for DMA and often DMA is used to move this data into memory In addition these buffers and the FIFOs in the hardware allow some slack in the system so that the application can fall behind for a short time if it is busy performing some other service After the completion of this task the sys tem can process the buffers in the queues and in the hardware FIFOs and catch up As long as enough slack is built into the system no data loss will result Servoing Applications In a Servo application the requirements are polar oppo sites from the Data Acquisition application In this case each event needs to be pro cessed at once with no delay This data is analyzed to produce an output update event that is output to the DACs in the system at once It is therefore vital that data is read into the system and processed without any buffering Hardware FIFOs are only useful at the single event level if you fall behind by even a single event your servo is failing Since the amount of data moved from the hardware is so small DMA is much less useful in this case than it is for the Data Acquisition case In fact due to very large latencies i
108. is to acquire data from the analog input perform some kind of algorithm using the new data to produce an output data event which is then output to the DACs The basic servo class handles the details of attaching the interrupt setting up the hardware reading the data from the hardware and delivering it to the user s function for processing After this it writes the modified data to the DACs Using the Servo Class The servoBase base class provides a number of methods to simplify the operation of a servoing applica tion It organizes the configuration of the hardware and the timebases to provide the exact setup needed It provides a callback hook to allow user code to be called when running the servo in order to provide custom servo processing functionality The following table gives the methods that can be overridden and when they are called TABLE 11 The Servo Class Virtual Function Function When Called Function Execute On each interrupt Servo calculations Servo Interrupt Modes The ServoBase Class sets up a configuration where the analog will drive an interrupt on every incoming point and expect a return event to be loaded very soon thereafter A key factor in the performance of the servo is the performance of the interrupt and its internal functions The servoBase class provides all the functionality of a null servo that is one that performs no modi fication of the data from input to out
109. le at all times The terminal will remain atop other windows when this entry is checked Select the entry again to uncheck and allow the terminal emulator window to be obscured by other windows Clear on Restart specifies whether the terminal display and log will be automatically cleared when ever the DSP is restarted Pause on Plot specifies whether standard I O will be suspended following display of graphical information in the Binview applet which is automatically invoked via use of the Pismo library Plot command If enabled standard I O may be resumed by clicking the i button Log Scrolled Text specifies whether text information which scrolls offscreen on the Terminal tab is appended to the Log display If enabled standard I O performance will degrade slightly during lengthy text outputs Font button invokes a font selection dialog which allows selection of user specified font within the Terminal and Log text controls 98 RtdxTerminal The Terminal Emulator Bkg Color button invokes a color selection dialog which allows selection of user specified back ground color within the Terminal and Log text controls Sounds Group Controls within the Sounds group box govern the audible prompts generated by the terminal emulator as detailed below Errors if enabled file I O and other errors encountered during operation generate an audible tone Suspend if enabled suspension of standard I O su
110. loping Custom Code In building custom code for an application Innovative Intergration recommends that you begin with one of the sample programs as an example and extend it to serve the exact needs of the particular job Since each of the example programs illustrates a basic data acquisition or DSP task integrated into the target hardware it should be fairly straightforward to find an example which roughly approximates the basic operation of the application It is recommended that you familiarize yourself with the sample pro grams provided The sample programs will provide a skeleton for the fully custom application and ease a lot of the target integration work by providing hooks into the peripheral libraries and devices themselves 62 The Next Step Developing Custom Code 63 Building a Target DSP Project 64 CHAPTER 5 Servo Applications Applications for DSP baseboards can be broadly divided into two categories Data Acquisition and Servoing applications These two types of application require very different methods of behavior by the system that cannot easily be reconciled into a single one size fits all system Yet the Pismo library needs to support both styles of program in a simple and natural way Data Acquisition Applications Acquisition applications need to acquire large quantities of data but do not need to process the data immediately In order to sup port higher rates these applicat
111. lt 2 2 2 2 2 2 D w w w ww C31 o o o TABLE 15 M6713 I O Bus Memory Mapping Each module site provides a 32 bit wide data bus connection to the processor s data bus with 12 bits of low order address signals for additional decoding beyond the four chip select signals available per slot Since the Omnibus modules are 32 bit devices and the DSP has byte addressing the address mapping to the M6713 is such that Omnibus address AO is address A2 on the DSP Each module also connects to a C6713 serial port serial port zero for slot zero and serial port 1 for slots 1 to allow serial port driven I O Bus reset RDY R W and processor clock signals are available as are power connections for digital 5V and analog 5V and 15V Timebase connections include timer channels from both the 16 bit timers and the AD9851 direct digital synthesizer DDS Each OMNIBUS slot has a 50 pin undedicated connector JP3 on slot 0 and JP7 on slot 1 that provides access from the external I O to and from a module installed in the slot The slot s I O connector is in turn pinned out to a single 100 pin MDR connector JP4 for use in attaching cables from external hard ware Cables and breakout modules for the MDR 100 output connector are available from Innovative Custom cables may also be made using the connectors specified in the appendix Connector pinouts for the module sites are provided in the appendices I
112. mary block The DMA system shares a single interrupt for all TC interrupts and the system will call the installed handler when the particular bit in the TC register becomes set The handler installer requires an Inter rupt Binder Object See Interrupt Binder Templates on page 44 as an argument to associate a han dler function or method and argument for the interrupt forwarding mechanism of Pismo A second pair of functions TcIntDeinstall and LinkTcIntDeinstallQ removes any installed handler for the TC bit used by the block Once installed TC interrupts for the entire transfer may be enabled or disabled by a call to TcIntEna bleQ The following example shows a full Edma transfer with TC interrupt handling In this example a class member function is bound to handle the interrupt response class Dmalsr public typedef void IntFtnType void fallow DmaIsr Binder this amp DmaIsr MyHandler NULL void MyHandler void fallow qdma_not_done false ClassMemberHandler lt DmaIsr void gt Binder 48 EDMA and QDMA Handling Dmalsr Isr void EdmaTest Edma Ed Ed Settings Priority DmaSettings priHigh ElementSize DmaSet tings is32bit Ed Settings Element Index 1 ElementCount 50 FrameIndex 1 FrameCount 0 Ed Settings TCInt true TCCode 1 FrameSync true Ed Settings SourceAddr int amp src_array 0 SourceIncr DmaSettings
113. ment Package Manual Connector pinouts JH1 FPDP Transmit Port Connector Connector type PSOE 080P1 S1 TG Number of pins 80 Mating connector P25E 080S TGF Manuf 3M The following table gives the pin numbers and functions for the JH1 connector Direction from Pin Number JH1 Function M6713 1 3 4 5 6 8 10 Digital Ground Power 12 14 16 18 20 22 24 26 28 30 32 35 38 41 44 47 50 53 56 59 62 65 68 11 74 77 80 2 Tx Strobe O 7 Tx NRDY N O 9 Tx DIRN O 13 Tx Suspend N O 17 Tx PIO2 O 19 Tx PIO1 O 25 Tx PStrobe P O 27 Tx PStrobe N O 29 Tx Sync N 31 Tx DValid N O 33 34 36 37 TxD31 TxD30 TxD29 TxD28 O 39 40 42 43 TxD27 TxD26 TxD25 TxD24 O 45 46 48 49 TxD23 TxD22 TxD21 TxD20 O 51 52 54 55 TxD19 TxD18 TxD17 TxD16 O 57 58 60 61 TxD15 TxD14 TxD13 TxD12 O 63 64 66 67 TxD11 TxD10 TxD9 TxD8 O 69 70 72 73 TxD7 TxD6 TxD5 TxD4 O 75 76 78 79 TxD3 Tx2D TxDI O Development Package Manual 143 Appendices TABLE 41 FPDP JH1 Tx Port Connector JH1 P50E 080P1 S1 TG GNE 1 TX STROBE DEND DGND TX NRDY 7 3 3V TX DIR_N 9 BONE O TX susPEND_ NDGND 13 BEN DGND 15 DGND R13 2 R14 TX PIO2 17 BOND 169 169 TX POT 19 PGND 0 55 DGND TX PSTROBE P 25 PONE TX PSTROBE N lov cala ta A DGND TX SYNC_N 29 BONE TX DVALID_N 31 BONE R15 2 R16 TX 531 33 TX D30 TX 52 2
114. n M6713 baseboard SD16 module at 50 KHz using namespace II AnalogOutStream Aout Omnibus mSite0 void IIMain Load Module onto site 0 LoadModule Omnibus mSite0 Omnibus mtSD16 Use default clock DDS Set Clock Rate ClockRateUIPtr Aout Clock gt Rate 50000 f Output on all channels Aout Channels gt EnableAll Size the buffers Aout Events 5000 Aout BufferCount BuffersPerSec 3 Open the streams 37 About the Baseboard Aout Open Stream loop bool run true while run Aout Generate Aout Put Terminate streaming Aout Close Examining the above code you can see the application uses an AnalogOutStream since it is an output program The next interesting line is the call to LoadModule This informs the system of which mod ule is plugged in on Omnibus mSite0 where the stream is also attached With the attachment of the module to the stream the stream object can configure hardware clock and trigger settings The next several lines configure the Stream clock rate the channel configuration and the stream buffer count and buffer size Then comes the st ream Open method which activates the device driver in DSP BIOS Afterwards the Stream Control method may be used to perform any necessary device specific initialization and or control functions Data flow begins with the calls to Gen
115. n initiating a DMA operation only quick DMA QDMA is a reasonable 65 Servo Applications candidate for use within a servo application However QDMA is not utilized within the Pismo servo driver for the following reasons 1 QDMA requires software initialization in order to initate data movement This initialization must be performed each servo interrupt cycle The amount of time saved by having the DMA engine more efficiently move between the peripheral and the servo application is roughly comparable to the amount of time lost performing QDMA setup and cache manipulation functions 2 QDMA is a limited system resource The Pismo Buffer classes use QDMA to perform high speed copies So use of QDMA within the servo driver would preclude its use elsewhere Servoing and DSP BIOS DSP BIOS uses device drivers to provide a uniform simple interface to ana log hardware for input and output The driver model used is well suited for Data Acquisition applica tions since it provides simple means for allocating and passing buffers of data in and out of the device This driver model is used for all of the streamable hardware provided on the baseboard Yet because of the strength of the model for the streaming applications these drivers fail to be able to properly servo in any efficient manner The Servo Base Class The Pismo Library supports servoing by defining a class to perform the basics of a servo operation The basic servo operation
116. nally be initiated via the mj button Dsp Restart rewinds the DSP program counter to the application entry point usually c_int00 This is functionaly identical to performing Debug Restart within Code Composer Studio This operation can optionally be initiated via the El button Dsp Reset causes the terminal emulator to bring the target board into a cold start uninitialized con dition This is functionaly identical to performing Debug Reset Dsp within Code Composer Studio This operation can optionally be initiated via the La button Form Menu Rtdx Terminal Dsp Form Help al 91 Tuck Left Tuck Right FIGURE 5 RtdxTerminal Form Menu RtdxTerminal The Terminal Emulator e Form Tuck Left repositions the main application window to the bottom left of the Windows desk top This operation can optionally be initiated via the button e Form Tuck Right repositions the main application window to the bottom right of the Windows desk top This operation can optionally be initiated via the gt button Help Menu 2 Dsp Form Help About this program FIGURE 6 RtdxTerminal Help Menu Help Usage Instructions displays online help detailing use of the application including command line arguments This operation can optionally be initiated via the button Help About this Program displays a dialog containing program revision and tech support contact in
117. nction The handler is defined as an override for the virtual Execute method The pragma places this function onchip for extra efficiency The base class passes several important parameters to the application event is a pointer to a buffer containing an array of 16 bit input samples read from the input peripheral obtained during the most recent conversion inputs and outputs are the count of active input and output channels respectively The body of the method illustrates processing on input channel zero only The value of input channel zero is clipped to 0x4000 counts For the Servo16 this clips the input voltage to half scale The clipped value is written back to the event buffer overwritting the original value The effect of this handler is to loop through all inputs unchanged to all outputs except for channel zero which is clipped 69 Servo Applications The Pismo Library creates a new main function 11Main Which is the primary application thread This thread is responsible for creating configuring and running the servo void IIMain int DacDelay int SampleRate Terminal I O cio lt lt init cio At Point 25 0 cio lt lt bold lt lt 7Servo Application n n lt lt normal lt lt endl TestServo Servolo Omnibus mSite0 First the application instantiates a Test Servo object called Servoto This provides access to the servo driver customized with a unique Execute behaviour Thi
118. ndividual pin functions are noted in the tables and in general the OMNIBUS pinout represents a direct connection to the C6713 local bus Development Package Manual 107 M6713 Hardware M6713 OMNIBUS Memory Mapping Since the C6713 processor is a byte addressable machine which implements its address bus based on a 32 bit transfer width i e the address bus starts at A2 and separate byte enable pins are supplied to con trol accesses to individual bytes within the 32 bit wide location denoted by the address bus users must take care when writing software which performs OMNIBUS accesses The OMNIBUS specification requires 32 bit accesses and does not support byte or half word 16 bit accesses No support is included in the specification for the C6713 s byte enable pins This means that software performing accesses must always perform 32 bit transactions with the OMNIBUS modules When writing C code for the M6713 programmers should use only variables of type int or unsigned int or their derived types and all accesses should be word justified the least significant nibble of the address must always be a multiple of four Accesses generated using pointers to variables of type char short or long will cause erroneous non 32 bit accesses Correct OMNIBUS module operation under these situations can not be guaranteed Please note that memory decoding within the OMNIBUS decode regions uses 32 bit addressing and that the memory map t
119. nel const IntBuffer amp Block bool Recv int Channel IntBuffer amp Block M6713 Send sends the contents of a IntBuffer object to the target All of the data in the IntBuffer is transferred There is no means of sending a partial buffer The function will not return until the block has been transferred to the target The function returns true if the transfer succeeded It returns false if the transfer failed due to a PCI bus error M6713 Recv waits for data to arrive from the target then returns the data in the buffer provided The IntBuffer will be re sized to fit the data transferred from the source If the buffer is too small this may involve a reallocation of the data block which can degrade real time performance The function returns true if the transfer succeeded It returns false if the transfer failed due to a PCI bus error Target Pismo Library Support for CPU Busmastering In the Pismo library the Utility library contains a file PciTransfer h that contains this class class PciTransfer public PciTransferBase public PciTransfer bool Send int channel const Buffer amp buffer bool Recv int channel Buffer amp Buffer PciTransfer Send sends the contents of a Buffer derived object to the Host All of the data in the buffer is transferred There is no means of sending a partial buffer The function will not return until the block has been transferred to the host The use of the base buffe
120. ng Retriggering How to handle interval before next start trigger Selecting Pretriggering Modes The pretrigger control for a stream consists of the following methods TABLE 5 Stream object Pretrigger Methods Method IsPretriggerTypeSupported SetPretriggerType Pretrigger Description Returns True if the pretrigger mode is allowed on the hard ware Change pretrigger to the selected mode Returns the pretrigger interface for the mode TABLE 6 Stream object Start Trigger Methods Method IsStartTriggerTypeSupported SetStartTriggerType StartTrigger Description Returns True if the start trigger mode is allowed on the hardware Change start trigger to the selected mode Returns the start trigger interface for the mode TABLE 7 Stream object Stop Trigger Methods Method IsStopTriggerTypeSupported SetStopTriggerType StopTrigger Description Returns True if the stop trigger mode is allowed on the hardware Change stop trigger to the selected mode Returns the stop trigger interface for the mode 40 Analog I O Streams TABLE 8 Stream object Retrigger Methods Method Description IsRetriggerTypeSupported Returns True if the retrigger mode is allowed on the hardware SetRetriggerType Change retrigger to the selected mode Retrigger Returns the retrigger interface for the mode Trigger configuration presents the same problem as the clock configuration except mo
121. ng on the bus efficiency and 33 3 32 133 80 system speed Workstation and servers are typical platforms for this bus Rates vary from 90 to 200MB s for 33 3 64 266 120 machines measured Don t see many of these Measured 120 MB s on 66 6 32 266 120 the system we tested Servers and embedded systems typically have this 66 6 64 512 280 bus type Rates vary from 200 MB s to 320 MB s TABLE 20 PCI DMA Rates Summary As would be expected the better architectures and performance of servers result in the better perfor mance In some cases the software can be a limiting factor especially as packets get small and inter rupt rates increase To get best performance bigger packets and better machines are always better Compatibility The bus interface is compatible with PICMG 2 1 standard supporting 3 3V or 5V sig naling up to 66 MHz clock rates and 32 or 64 bit operation The bus interface logic automatically detects the type of bus and configures itself accordingly PCI X slots are OK to use also since they will work as PCI as required by the specification Packet Transfer Protocol The PCI DMA interface uses data packets for transporting the data Each packet has a header and a data payload that carries the data Data sent to the PCI DMA controller MUST be in this format for proper operation Each packet is inspected by the PCI DMA controller as part of the DMA process The controller moves the number of points in each packet by counting t
122. nloaded to the target and executed Clicking Cancel will abort the file selection and close the requester with no download taking place This operation can optionally be initiated via the al button File Reload Reloads and executes the COFF file last downloaded to the target It provides a fast means to re execute the application program most recently loaded into the target board This operation can optionally be initiated via the A button NOTE File Load and File Reload functions use the JTAG debugger and Code Composer Studio in order to effect the program download File Save saves the textual contents of the Terminal and Log tabs to a user specified file e File Print prints the textual contents of the Terminal and Log tabs to a user specified printer e File Exit closes the emulator application terminating console emulation 95 Applets DSP Menu 3 Dsp Form He z Run Halt Restart Reset FIGURE 4 RtdxTerminal DSP Menu Dsp causes the terminal emulator to bring the target board into a cold start uninitialized con dition This is functionaly identical to performing Debug Run within Code Composer Studio This operation can optionally be initiated via the i button Dsp Halt causes the terminal emulator to suspend DSP program execution This is functionaly identical to performing Debug Halt within Code Composer Studio This operation can optio
123. novative product family and the M6713 DSP board is available via Innovative Online at www innovative dsp com Typographic Conventions This manual uses the typefaces described below to indicate special text TABLE 1 Typographic Conventions Typeface Meaning Monospace Type Monospace type represents text as it appears onscreen or in code It also represents anything you must type Boldface Boldface words in text or code listings represent reserved words or compiler options Italics Italicized words in text represent C Builder identifiers such as variables or type names Italics are also used to emphasize certain words such as new terms Keycaps This typeface indicates a key on your keyboard For example Press Esc to exit a menu 13 Introduction 14 CHAPTER 2 Installation Thank you for purchasing from Innovative Integration We appreciate your busi ness This chapter describes the software and hardware installation procedure for Windows 2K or XP Development under other versions of Windows are not sup ported at this time though drivers are provided to allow runtime operation under Win9x and WinME Do NOT install the hardware card into your system at this time This will follow the software installation Host Hardware Requirements The software development tools require an IBM or 100 compatible Pentium IV class or higher machine for proper operation An Intel brand processor
124. nternal buffers The size of data buffers may be specified explicitly using the Stream Events method This latter method sizes the buffers such that they can contain the at least the specified number of acquisition events where an event is defined as one sample from all enabled A D or D A channels This simpli fies most buffer processing algorithms since all buffers are guaranteed to contain an integral number of samples from all enabled channels The product of the buffer size and the number of buffers gives the load carrying capacity of the system For example the originally allocated three buffers per stream each sized at 0 1000 bytes running at 44 1 kHz equates to a load carrying capacity of 0x1000 bytes buffer x 3 buffers 44100 samples sec 2 bytes sample 139 mS Whereas in the second example with six buffers per driver pool 0x1000 bytes buffer x 6 buffers 44100 samples sec 2 bytes sample 278 mS Data integrity can thus be preserved at the expense of additional memory utilization Burst Streams place data into the buffer provided No buffering is used and data acquisition is halted when the provided data buffer is filled 36 Analog I O Streams Stream Internals The DSP CPU used on the M6713 is powerful and fast yet the Stream classes improve performance even further by drastically reducing CPU use for data movement The available DMA channels in the C6000 DSPs are fully exploited
125. ntroller will read the data from that address for the programmed count The M6713 logic has generalized this function so that a read or write to a particular is counted for the interrupt contorl This allows any peripheral device to take advantage of the interrupt counting for DMA control Each interrupt has a register set for the address and a control register for the access direction and enable Bit Function 6 0 Burst count Development Package Manual 125 M6713 Hardware 29 7 Not used 30 DSP read or write access 1 read 0 write default 31 Enable DMA burst counting interrupt mode TABLE 30 Interrupt Burst Counting Control Register Bit Function 31 0 DMA address for burst counting TABLE 31 DMA Address for Interrupt Control Address Register Description 0x801B0000 Burst address register INT4 0x801C0000 Burst address register INT5 0x801D0000 Burst address register INT6 0x801E0000 Burst address register INT7 0x801F0000 Burst address register DMA int 0x80120000 Burst count control register INT4 0x80130000 Burst count control register INT5 0x80140000 Burst count control register INT6 0x80150000 Burst count control register INT7 0x80160000 Burst count control register DMA int TABLE 32 Interrupt Access Counting Control Registers For the drive rs provided in the M6713 software development packa
126. ocessing desired By having the receipt of a message trigger the generation of additional messages a message protocol can be developed to allow the transfer of data or the execution of control functions on demand from the other side of the link This is even more natural if the applications are written in an event driven style The arrival of messages are the events to which the application responds ASnap The ASnap example is communications demonstration that resides in the M6713 Examples ASnap direc tory This example demonstrates continuous high rate analog acquisition from a suitable Omnibus module into a buffer on the target DSP After the acquisition the data is sent to a Windows disk fle via the PCIinterface This data may be examined using the supplied BinView applet Simple bidirectional communications between the target and the host are shown The target project and its source are located in the M6713 Examples Asnap directory However there are two versions of the Host project and source located in the BCB and Wc subdirectories beneath the target project These contain the source for the Borland BCB and Microsoft MSVC versions of the Host example respectively Development Package Manual 83 Developing Host Code 84 Development Package Manual Host Example Program for the M6713 Baseboard Development Package Manual 85 Developing Host Code 86 Development Package Manual Host Exam
127. olo OutputChannels EnableChannels Channels The output delay is also adjustable through use of the Delay method inherited from the base Ser voBase class int MaxDelay 1 0 SampleRate 1 e9 100 100 cio lt lt Enter the Dac Delay Time lt lt lt MaxDelay lt lt ns lt lt flush cio gt gt DacDelay cio lt lt endl Configure delay of DAC clock Servolo Delay DacDelay Interrupt latency is increasingly erratic in the presence of other interrupt sources The example allows the USB and serial port interrupt to be disabled to improve determinicity char NoComm cio Disable communications flush cio NoComm cio lt lt endl cio lt lt nServo Running press any key to stop lt lt endl Sleep 300 communications are disabled max servo interrupt latency is reduced since fewer interrupt conflicts occur if std tolower NoComm y DisableCommunications The driver is open and viable To start data flow simply call the start method Interrupt pro cessing within the Servolo Execute method will commence immediately thereafter Start processing Servolo Start while cio KbdHit Sleep 300 cio lt lt Serviced interrupt lt lt Servolo Tally lt lt cr Data flow may be suspended and resumed through repeated calls to start and stop Stop processing Servolo Stop Close driver status Servolo
128. ometimes necessary to force a complete rebuild of an output file manually such as when you change optimization levels within a project To force a project rebuild select Project Rebuild All from the Code Composer Studio menu bar IIMain replaces main Due to restrictions within Dsp Bios not all BIOS features may be safely used within main since it is called early in the system initialization sequence To circumvent this limita tion Pismo automatically constructs a default thread running within normal priority and starts this thread automatically The entry point function in this thread is called 11Main and all Pismo applica tions must define this function This function is intended to replace main in your application programs You may safely call any BIOS function within IIMain Running the Target Executable The test program may be converted into a simple Hello World example by using the built in stan dard I O features within Pismo Bring up the Test cpp source file edit screen Scroll down the source file by using cursor down button until you reach the IIMain function Edit it as follows include Pismo h cio lt lt init cio lt lt Hello World lt lt endl cio monitor You can now compile the new version by executing Build from the Project menu or by clicking on its toolbar icon This causes Code Composer Studio to start the compiler which produces an assembly language output The compiler then automa
129. or FPDP interrupts The dedicated mode does not have the burden of acknowledging the interrupts consumed so this mode is faster at interrupt servic ing than the shared interrupts Shared interrupts allow multiple devices to share an interrupt to the processor When the DSP receives a shared interrupt it must read the interrupt status register associated with that interrupt to determine the 124 Development Package Manual Interrupts interrupt source s requiring service The DSP interrupt handling in this case should be capable of han dling all the devices sharing this interrupt either alone or simultaneously to support the interrupt shar ing Upon completing the interrupt servicing it is required that the DSP acknowledge the interrupt sources that were serviced This prevents interrupts from being lost in the event that another interrupt source requires service in the meantime The interrupt status acknowledge registers are located at the address in the following table Writing a 1 to any of the bits indicates that the interrupt has been ser viced The bits have the same order as the interrupt source selection bits previously shown above Interrupt Address DSP int 4 0x80050000 NMI 0x80080000 TABLE 29 External Interrupt Status and Acknowledge Register Addresses For example if the application requires the output from external interrupt input two to drive processor interrupt input four the value t
130. or configuration each of which can be exposed by a conversion function for the class If a UI interface is not supported the conversion function returns a null pointer The following code sample shows the use of trigger conversion functions and multiple interface classes The AD40 module is in use It supports several different Pretrigger and StartTrigger modes In the example we wish to use Counted Pretriggering and Threshold Start Triggering This example for an AD40 uses pretriggering and cf start triggering Set triggers Stream gt SetPretriggerType TriggerManager ptCounted Stream gt SetStartTriggerType TriggerManager stThreshold Joh Configure Pretrigger to 500 counts CountedPretriggerPtr Stream gt Pretrigger gt PretriggerCounts 500 Set start threshold to 1 volts VoltageThresholdPtr Stream gt StartTrigger gt ThresholdLevel 5 ConfigurableTriggerPtr Stream gt StartTrigger gt ttEdge ConfigurableTriggerPtr Stream gt StartTrigger gt Polarity tpPositive Counted Pretriggering allows the preservation of data samples before the start trigger fires Normally the first data point read was taken just after the start trigger fires With Counted Pretriggering N sam ples before the trigger fires are output when the trigger fires In the example below the pretrigger is set to return 500 samples from before the trigger About the Baseboard The AD40 T
131. or low for an interrupt The following table gives the cor rect settings for the possible interrupt conditions so that the logic interacts properly with the DSP The M6713 support logic always gives a rising edge interrupt to the C6713 DSP thus the DSP requires a rising edge interrupt configuration Interrupt Type Polarity Edge Level Rising Edge 1 0 Falling Edge 0 0 High Level 1 interrupt 1 1 Low Level 0 interrupt 0 1 Interrupts must remain active at least 56 ns after changing states in either edge or level mode Shared Dedicated Interrupts The M6713 has two interrupt modes only on on the NMI and INT4 that may be used with any proces sor interrupt shared and dedicated mode Since the DSP has only five interrupts many applications need a method for sharing interrupts to support all the peripheral devices on the M6713 efficiently Shared mode has been developed so that multiple interrupt sources may share a single interrupt to the DSP In dedicated mode each interrupt to the processor is steered directly from the selection matrix through the edge level and polarity conditioning directly to the processor This allows the interrupt source to directly connect to the DSP Dedicated interrupts are not shared amongst interrupt sources and should be used for the devices requiring the highest rates of interrupt servicing These devices might be for example FIFO level interrupts from an Omnibus module
132. orage as well as storage space for data acquired generated by the baseboard analog hardware This memory is programmed to operate at 75 MHz regardless of the DSP core clock rate The initialization of all external memory spaces are defined within the file HawLib IIInit cpp and include the correct parameters for the type of SDRAM used on the baseboard including refresh timing as well as timings for all sync and async peripherals and should not be modified DSP Initialization For proper operation of the external peripheral on the baseboard the external memory interface control registers must be configured prior to use of the external memory interface Applications built under the Pismo Toolset libraries will automatically initialize the registers appropriately using code within HdwLib IIInit cpp For those customers who need to initialize the registers manually please refer to the EMIF register initialization values within the 111nit cpp source file to obtain the required register values Please note that the initialization is order sensitive and should be performed in the order given in the table below Register Name Address Value Use GBLCTL 0x01800000 0x00003078 CEOCTL 0x01800008 0 21 28 22 FPDP CEICTL 0x01800004 0x0000C041 Asynchronous devices CE2CTL 0x01800010 0x00000030 SDRAM CE3CTL 0x01800014 0x11010420 Omnibus Modules SDTIM 0x0180001C 0x00000350 SDEXT 0x01800020 0x000544a7 SDCTL 0x01800018 0x6B3
133. ort none or one or any number of all the possible Ul interface classes An interface can be accessed by the conversion function for each of the Ul interface classes If an interface is not supported the conversion function returns a null pointer The following code sample shows the use of conversion functions and multiple interface classes The DDS clock source is in use It supports both the ClockRateUI interface which allows changing the clock frequency and the ClockSyncUI interface which allows configuration of the SyncLink Clock Link master hardware to drive the DDS clock signal off the baseboard for use as a source on another board Set Clock Rate allowed on DDS 39 About the Baseboard ClockRateUIPtr Aln Clock gt Rate 50000 ClcokSyncUIPtr AIn Clock gt SyncLinkChannel scSyncLink0 Each line can be read from the inside out AIn Clock returns the current clock UI object This object is input into the clock conversion function clockRatevIPtr and converted into the clockRatevI interface Finally the Rate method of this class is called to set the rate of the clock to 50 000 Hz Selecting and Configuring Triggers The Analog Stream objects allow the user to configure the trig gering method used during the run Triggering features are divided into four parts Pretriggering Handling data before the start trigger Start Trigger How to start data taking Stop Trigger How to stop data taki
134. perate for extended periods without software intervention This means latency must be increased data may be in the queue for some time until additional data forces it out to the application Of course if the application does not process the data as fast as it arrives data will even tually be lost Burst Streams use a different model Here data movement is on demand instead of asynchronous If no request for action by the application is received the Stream is idle This type of Stream is more common for non Analog I O such as the FifoPort or PCI busmastering but the CaptureInStream implements a burst type I O model on the analog hardware Stream Buffer Model Each Stream uses data buffer class objects to pass data between its hardware and the application These buffers are all the same size Passing data between Streams is simple if the buffers are chosen to be the same size Ain Get Aout Put Ain Buffer Buffer transfers are efficient because the data buffers are not copied at any time during the transfer pro cess By default Streams allocates three buffers two internal and one swap buffer If desired the num ber of internal buffers in the pool may be modified prior to opening the Stream by assigning a new value using the BufferCount method Instantiate the analog stream objects AnalogOutStream Aout Aout BufferCount 5 AnalogInStream Ain Ain BufferCount 5 This code forces the Stream to allocate five i
135. pins are TTL compatible pins driven by LVTTL 3 3V pins on the FPGA Each pin has a 100 ohm series resistor to allow 5V tolerant IO per Xilinx requirement for the Spartan3 FPGA The pins will drive 3 3mA per pin when this resistor is used High current devices may need to provide additional current driving capacity Interrupts The C6713 processor implements five interrupt input pins plus one GPIO pin configured as a DMA interrupt that allow external hardware events to directly trigger software or DMA activity Processor interrupt inputs are supported on the M6713 through a set of control registers and multiplexers that allows application software to dynamically select the source of the signal which will drive each particu lar interrupt input as well as the polarity and edge or level sensitivity Additionally the interrupt control ler in the support logic allows interrupt sharing by peripherals on the M6713 The following table shows the addresses of the control registers for each processor interrupt input A value written to the appropriate control register causes the interrupt mux to select the interrupt source given in the next table see below Functional Address NMI Interrupt Input Select 0x800D0000 External Interrupt Input 4 Select 0x80090000 External Interrupt Input 5 Select 0x800A0000 External Interrupt Input 6 Select 0x800B0000 External Interrupt Input 7 Select 0x800C0000 DMA Interrupt Select 0x80070000
136. ple Program for the M6713 Baseboard Development Package Manual 87 Developing Host Code 88 Development Package Manual CHAPTER 8 Applets This chapter describes the Host PC utility applets that are provided with the Pismo tool suite To invoke any of these utilities go to the Start menu Programs M6713 menu and click the one you are interested in running Registration Utility New User exe Some of the Host applets provided in the Malibu Developers Package are keyed to prevent unauthorized duplication These utilities allow unrestricted use for up to 20 days trial period during which you are required to register your Toolset After the trial period operation will be disallowed until an unlock code provided by Innova tive Integrationm is used to re enable the applet After using the NewUser exe applet to provide Innovative Integration with your registration information you will receive The unlock code necessary for unrestructed use of the Host applets Registration Information User ri Last Henderson Email Address Telephone Country Code Area Code Number Extension Fax Area Code Number Company Name Innovative Integration Address City State County Postal Code Product Board Vista T Access Code 935846148 tte fuit gt A WSC tech support service code enabling free
137. pport 14 MB BoardDrivers 0 1 MB inicia zl 4c n 11114 x Space Required Space Available EC 892 MB 5 813 3 MB lo BaseFormContainer A i Select the components you want to install clear the components you do not want to install Double click on group to see all of its My subgroups 0 Applets 1 3MB Borland Components 54 1 MB GS systemDLLs 32 4 MB Documents 1 1 MB 0A Peripheral Libraries 4 9MB L1 Space Required Space Available SC 941 MB 5 819 0 MB 2 estination Director 77M c program filestinnovativevaspi You may customize your installation including or omitting components shown in these sub install menus At this point in each sub install check the desired components to be installed and click the Next gt button Note that first time development system installs usually require the installation of all components Installation The host examples included in this installation are written in C using Borland Builder or Microsoft MSVC and C on the target side using Code Composer Studio They are provided to illustrate the var ious features of the board and how these features are utilized Tools Registration Before beginning DSP and Host software development you must register your installtion with Innova tive Integration Technical support will no
138. put including installation of its own interrupt handler This handler will read data from the input peripherals into a buffer call the Execute function in which the user per forms custum servo calculations then transfers the data out to the output peripherals 66 Using the Servo Class ExecuteUser code within the overridden Execute method always executes within HWI interrupt con text This code may call BIOS routines only if the the ServoBase object used within the application is constructed with the UseDispatcher parameter set true However setting this flag results in a less efficient interrupt handler exhibiting high interrupt latencies than if UseDispatcher 18 false Once in the interrupt the application software merely manipulates samples within the event buffer whose address is passed as a parameter to the Execute method Input samples are consumed from this event buffer and output response values are stored into this same buffer Upon return from the overrid den Execute method the contents of this buffer is automatically written to the output devices The use of these methods allows the servo system overhead to be reduced to the minimum possible for this architecture The Servo example program included in the Developers Package demonstrates this technique Execute The Execute method is overridden with the user s Servo code The function is very simple the data taken from all enabled input peripherals is passed
139. r class allows any of the IntBuffer CharBuffer FloatBuffer and similar classes to be sent across the interface The function returns true if the transfer succeeded It returns false if the transfer failed due to a PCI bus error PciTransfer Recv waits for data to arrive from the target then returns the data in the buffer provided The Buffer will be re sized to fit the data transferred from the source If the buffer is too small this may involve a reallocation of the data block The function returns true if the transfer succeeded It returns false if the transfer failed due to a PCI bus error See the ASnap example for an illustration of bus master usage 75 Communication to the Host C Terminal I O The terminal emulator applet is a Host PC application which provides a C language compatible ter minal emulation facility for interacting with the Termlo Pismo library running on an Innovative Integra tion DSP processor Using the terminal emulator it is possible to develop and debug target DSP code while deferring devel opment in Host application code By using simple streaming I O functions within a target application during development DSP algorithms can be developed independently from Host applications Later when a custom Host application code is written the DSP standard I O functions may be deleted from the target application and the target application will no longer be dependent on the emulator or the ta
140. r computer Add New Hardware automatically runs to finish the installation Please refer to your Vista Manual for instructions on hardware installation before turning the machine back on to make sure everything is plugged in correctly You will need to run the NewUser exe located under Program Files Innovative New User after rebooting in order to have access to some of the components of this installation Thank you from Innovative Integration 1 805 520 3300 Shutdown Now Shutdown Later Hardware Installation The software components of the Development Package have been installed To proceed with the Devel opment Package Kit installation it will be necessary to configure and install your hardware First the emulator hardware must be configured and installed into your PC The emulator hardware is described in the table below Type Features Pod based Uses a special ribbon cable with integrated line drivers to connect the target DSP emulation signals to the JTAG debugger card Usable on 3 3 volt or 5 volt designs Including C54x and C6x PCI Pod Based Emulator Installation To install the PCI pod based emulator follow the instructions below 1 Shut down Windows and power off the host system 2 Perform the board installation in an ESD or static safe workstation 3 Power off the host system and touch the chassis of the host computer system to dissipate any static charge
141. r or MS Visual C support Innovative including C Builder or MS Visual C support Key Support software hardware security key SKIKK are attempting a full installation with development libraries for a DSP board and have not already installed Code Composer and your Host IDE Borland Builder or MSVC you should do so before pro ceeding with the installation and NOT click Install at the first selection window In this case click the 16 Software Installation Exit button to terminate If you are deploying a completed application and need driver and DLL support files only to be installed proceed There will be a chance to check drivers only and DLLs only in each of the sub installs In the example above each of the check boxes have sub installs associated with them and will open a sub install screen window with another set of check boxes allowing you to select files to be installed For example the first sub install for Conejo including Applets Examples and Drivers is shown below The second image below is for Malibu including C Builder or MS Visual C support It fol lows a similar pattern and presents another set of choices as illustrated F 1 Select the components you want to install clear the components i I roma LN i you do not want to install Double click on a group to see all of its subgroups Documentation SystemDLLs Periph Lib CCS2 Su
142. ram zinixi File Edit View Help System Configuration siete Board Simulator Types a E C6201 C6701 EVM FC6211 C6711 DSK C6 gt Import a Config gt Install a Device Uninstall b Add To System C62xx C67x XDS510 Emulator 4C62xx C67xx XD5510 Emulator BE C62xx C67xx XD5560 Emulator EC6414 15 16 Rev 1 0x 05510 Emulator EC6414 15 16 Rev 1 0 05560 Emulator BE C64xx Rev 1 1 XD5560 Emulator Ra C64xx XDS510 Emulator Ra C64xx 05560 Emulator BE C xxx Simulator Bi Heterogeneous 05510 Multi Target Bi Heterogeneous XDS560 Multi Target Device Driver Loc ctildriversWixc off Drag a device driver to the left to add a board to the system Click this driver from the Available Board Simulator Types control within the setup utility and drag it into the System Configuration control Then right click on this C6000 XDS object to invoke the Properties Dialog for the driver Boara properties zx Board Name amp Data File Board Properties Processor Configuration Startup GEL File s Board Name EB 2 7 XDS510 Emulator Auto generate board data file with extra configuration file Cono C MtiNdriversNIPciPod cfg Diagnostic Utility Browse Diagnostic Arguments Device Driver Location lo ti drivers tixds6000 dvr Next gt Cancel Under the Board Name amp Data File tab the board name edit box should list C62xx C67xx X
143. rd Fimware 02 Hardware Old 303 which stores the personality of the board Complete csi Ex functionality is supplied in the application s help file toe JTAG Diagnostic Utility JtagDiag exe JtagDiag exe is used to re initialized the JTAG scan path 7 interface which connects the Code Hammer debugger s PCI plug in board with the target DSP Use this utility prior to invoking Code Composer Studio to insure that the commu e nications link is viable and clear This utility is also convie Reset nient in confirming that the Code Hammer installation is complete and correct essi Tia Demangle Utility Demangle exe The Demangle applet is designed to simpify use of the TI dem6x exe command line utility When building C E Tor E amples ASnap Debug ASnep map applications the built in symbol mangler in the TI com Demangle View piler renders symbolic names unreadable such that miss A ing or unresolved symbol errors displayed by the linker no longer correlate to the symbol names within your code To work around this limitation enable map file generation within your CCS project Then browse to the map file produced by the linker using the Demangle utility The utility will display proper symbol names for all unresolved externals COFF Section Dump Utility CoffDump exe COn DUG exe pasen 210 x through a user selected COFF Fie window Dumping C Vista Examples VEcho Debug _V
144. re so Triggering consists of four parts each of which can be independently set In addition there are far more ways of defining triggers than there are for defining parts of a timer For example the start of data flow on Omnibus modules can be based off of an external digital signal the value of the data on an input chan nel by software command or be automatic Pretrigger and Stop trigger options are also numerous A class that had methods for all these features would be large complex and would usually have most of its functions inoperative without giving the application any feedback Trigger configuration is also complicated by Module differences Even the same type of trigger can dif fer in on different modules For example an external start trigger may allow the condition of the input signal edge or level triggering positive or negative polarity be changed Another module might not support changing these features being always positive edge triggered Another example is that thresh old triggering might be able to be triggered of any selected channel or it might be restricted to a prede termined channel The triggering configuration system uses trigger interface objects to allow configuration of the trigger ing modes There are four access functions Pretrigger StartTrigger StopTrigger and Retrigger giving interface objects for use Each of these objects supports none or one or any number of Trigger UI interface classes f
145. register in the control register before configuration and use These registers are write only The output of the DDS may be used for a variety of functions including driving interrupts as a timebase to the DSP or modules or as an output Refer to the register descriptions for interrupt use or timebase pin definition registers The M6713 Development Package includes support routines which make it easy to set the AD9851 s output frequency as discussed in the previous sections of this manual The DDS has very fine resolution allowing the application to tune the timebase to many frequencies The absolute accuracy of the DDS timebase is approximately 200 ppm for room temperature applica tions This absolute accuracy may vary with temperature and time Calibration may be required in applications requiring higher precision timebases Timer Output Control The M6713 has a variety of timers timebase controls The timer0 timer and DDS pins therefore have software programmable outputs so that any of the available triggers can drive the modules Historically Innovative has referred to these pins by the names timer0 timer 1 and DDS which reflected their dedi 118 Development Package Manual Digital I O cated function but now the timer0 pin can have any number of signals on it not just the traditional timer0 function That being said the register to program what signal is on the timer 0 and 1 pins delivered to the Omni bus
146. rget Termlo libraries Streaming methods such as lt lt and gt gt are dispatched by the Termlo object to route text and data between the DSP target and the Host terminal terminal emulator applet Text strings are presented to the user via a terminal emulation window and host key board input data is transmitted back to the DSP The terminal emulator works almost identically to console mode terminals common in DOS and Unix sys tems and provides an excellent means of accessing target program data or providing a simple user inter face to control target application operation Target Software All of the features of the terminal are accessed through the two classes TermIo and TermFile TermIo provides the basic streaming interface which allows text messages to be formatted and streamed out to the terminal as well streaming in strings and numeric values from the terminal for consumption by tar get application code The Termrile class provides a mechanism allowing target applications to open host disk files perform read and write accesses and subsequently close these files See the Files cpp example for illustratative usage of each of these classes and their functions Tutorial Using the terminal during target software development is simple The global cio object which is auto matically instantiated within the Pismo libraries Use the methods within the cio class to format text strings and then stream them to the UniTerminal applet cio lt lt
147. rial Ports TABLE 17 FPDP Memory Map Bit Function 0 FPDP FIFO Reset 0 Reset 1 Out of Reset 2 1 Sync Mode 00 Unframed 5 4 PIO Direction PIO signals are input until configured as outputs 11 For Outputs 16 8 Threshold TABLE 18 FPDP Rx Configuration Register Bit Function 0 FPDP FIFO Reset 0 Reset 1 Out of Reset 2 1 Sync Mode 00 Unframed 01 Single Frame 10 Fixed Repeating 11 Dynamic Repeating 5 4 PIO Direction PIO signals are input until configured as outputs 11 For Outputs 16 8 Threshold TABLE 19 FPDP Tx Configuration Register C6713 McBSP Serial Ports The C6713 s on chip serial ports McBSP are pinned out to connectors JP14 port 0 and JP15 port 1 for use with external hardware The serial ports are also connected to the OMNIBUS sites for use with modules Omnibus module 0 has McBSP port 0 and module 1 has McBSP port 1 Pinouts for the serial port connectors are given in the appendices Innovative Intergration recommends buffering these ports with off board hardware in order to preserve signal integrity Development Package Manual 113 M6713 Hardware PCI Interface The M6713 has a flexible PCI bus interface that supports control and configuration by the host com puter and data transfers at up to 512 MB s The DSP and host can eff
148. rupt or a polling function Because the system state is saved in the object transfers can be predefined and saved to be posted at a later time As with all DMA objects the Qdma object uses an internal DmaSettings object to define the transfer The Settings method provdes access to the object to allow calling the DmaSettings classes own con figuration functions or configurations can be loaded from a second object with the Load method is a Qdma object here we change the destination address Q Settings DestinationAddr int dest_array 0x10 For QDMA a transfer is initiated when the parameters are loaded into the QDMA registers This is per formed by the Submit method which starts the preconfigured transaction or loads the passed in con figuration and submits it Only one Qdma transfer may be active in the system at one time Multi threaded applications must arbi trate Qdmas as appropriate If a terminal count interrupt is not used a call for WaitForComplete will delay until the completion occurs TestComplete will return a flag that can be used to check completion without blocking Qdma transfers may be configured to generate Terminal Count interrupts on completion of the transfer Which TC bit is signalled is configured in the settings block A user supplied handler similar to an interrupt handler can be associated with the terminal count inter rupt by a call to the TcIntInstall method The DMA system shar
149. s driver is opened then the inter nal event buffer is relocated to onchip ram for enhanced performance LoadModule Omnibus mSite0 PickModuleType bool status Servolo Open cio lt lt Servo open lt lt status ok failed lt lt endl if status DynamicHang Servo interface not supported Locate event buffer onchip Servolo Segld 1 First the application obtains a pointer to the timebase used for the analog input This is a plain old timebase which runs continuously with no special triggering Its rate is set by the property call to Clock gt Rate cio lt lt Enter sample rate lt 100 kHz lt lt flush cio gt gt SampleRate cio lt lt endl SampleRate 1000 ClockRateUI Clock ClockRateUlPtr Servolo Clock if Clock Clock gt Rate SampleRate The example allows a variable number of channels be processed This is accomplished by manipulating the input and output channel control objects accessible through the Input Channels and OutputChannels methods int MaxChannels std min Servolo InputChannels Channels Servolo OutputChannels Channels int Channels cio lt lt Enter channels lt lt flush cio gt gt Channels cio lt lt endl Channels std min MaxChannels Channels Enable all analog input and output channels Servolo InputChannels EnableChannels Channels 70 A Servo Tutorial Serv
150. s well as Innovative s custom Windows applets such as the terminal emulator Code Composer Studio is the package used to automate executable build operations within Innovative s Pismo Toolsets simplifying the edit compile test cycle Source is edited compiled and built within 57 Building a Target DSP Project Code Composer Studio then downloaded to the target and tested within either the Code Composer Stu dio debugger or via the terminal emulator Code Composer Studio may be used for both code authoring and code debugging Details of construct ing projects for use on Innovative DSP platforms are given in the above section of this chapter Do not confuse the creation of target applications code running on the target DSP processor with the creation of host applications code running on the host platform The TI tools generate code for the TI DSP processors and are a separate toolset from that needed to create applications for the host platform which would consist of some native compiler for the host processor such as Microsoft s Visual C or Borland Builder C for IBM compatibles To create a completely turnkey application with custom target and host software two programs must be written for two separate compilers While Innovative supports the use of Microsoft C C for generation of host applications under Windows with sample applications and libraries we do not supply the host tools as part of the Development Environm
151. sing the Servo Class 66 A Servo Tutorial 69 Communication to the Host 73 Overview 73 CPU Busmastering Interface 74 C Terminal 76 SBC6713e User s Manual CHAPTER 7 CHAPTER 8 CHAPTER 9 CHAPTER 10 Developing Host Code 79 The BoardLib library 79 The M6713 in the Host Environment 80 Host Example Program for the M6713 Baseboard 83 Applets 89 Registration Utility NewUser exe 89 ReserveMemoryDsp 90 Target Download Utility M6713Download exe 90 Logic Download Utility M6713LogicLoader exe 90 Logic Update Utility M6713VsProm exe 91 JTAG Diagnostic Utility JtagDiag exe 91 Demangle Utility Demangle exe 91 COFF Section Dump Utility CoffDump exe 91 92 Target Project Copy Utility CopyCcsProject exe 92 Binary File Viewer Utility BinView exe 92 DEF Conversion Utility DefConvert exe 93 Scan Path Diagnostic Utility JtagScanpath exe 93 RtdxTerminal The Terminal Emulator 93 M6713 Hardware 101 M6713 Hardware Functions 101 Memory Map 102 M6713 Hardware Initialization Requirements 105 External Memory 106 M6713 OMNIBUS 107 FPDP Port I O Expansion 109 C6713 McBSP Serial Ports 113 PCI Interface 114 Timers 116 Digital O 119 Interrupts 122 External Inputs for Clocks and Interrupts 126 Multi Card Timing Synchronization 127 Test Bus 129 Power Requirements 129 Updating the M6713 logic 129 Making Custom Logic 130 Troubleshooting 133 Initialization Problems 133
152. stem occurances directly within application code The M6713 in the Host Environment The Board Library uses the supplied M6713 device driver for downloading and communication via the PCI bus The details of this are managed internally by the M6713 class Connection Each instance of the M6713 class manages a single board Systems containing multiple targets are supported and each target is assigned a logical board number starting with zero After con 80 Development Package Manual The M6713 in the Host Environment struction the Target method may be used to associate the object with any board installed in the system Subsegently a call to the Open method establishes communications with that target Once communica tions are completed a call to Close discontinues communications COFF loading to the 6713 processor One major requirement is to be able to download and run code on the 6713 over the network The method DownloadCoff within the Cpu data member of the M6713 object is used to begin a COFF load as a background operation During the load process the back ground thread automatically calls the baseboard class s OnDownloadProgress and OnDownloadCom plete closures to provide interim status DownloadCoff merely posts a download request into a background thread that actually performs the download of the file passed as as an argument This method does not block and will return as soon as the request is posted Note that t
153. sync FPDP Tx Frame Count Ceo 0x80200020 Intf 8 Async Ww Selection Synclink Counters Register Ceo 0x80200024 Intf 9 Async W Module 0 timebase selections Ceo 0x80200028 Intf 10 Async W Module 1 timebase selections Ceo 0x8020002C Intf 11 Async Ww DDSO post scaling register Ceo 0x80200030 Intf 12 Async Ww 0051 post scaling register Ceo 0x80200034 Intf 13 Async Ww Timer 0 Configuration Write 0 80200038 Intf 14 Async Ww Timer 1 Configuration Write Ceo 0x8020003C Intf 15 Async Ww Timer 2 Configuration Write Ceo 0x80200040 Intf 16 Async Ww Timer Write 0 Counter End Register Ceo 0x80200044 Intf 17 Async W Timer Write 1 Counter End Register Ce0 0x80200048 Intf 18 Async W Timer Write 2 Counter End Register Ceo 0x80200040 Intf 16 Async R Timer 0 counter value read Ceo 0x80200044 Intf 17 Async R Timer 1 counter value read Ceo 0x80200048 Intf 18 Async R Timer 2 counter value read Ceo 0x8020004C Intf 19 23 Async R W Not used 0x8020005C Ceo 0x80200060 Intf 24 Async R Status Register Read Ceo 0x80200064 Intf 25 Async R W Not Used Ceo 0x80200068 Intf 26 Async RW FPDP Rx PIO 104 Development Package Manual M6713 Hardware Initialization Requirements Ceo 0x8020006C Intf 27 Async R FPDP Rx Frame Count Ceo 0x80200070 Intf 28 Async R W FPDP Tx PIO Ceo 0x80200074 Intf 29 Async R FPDP Tx BITIO Ceo 0x80200078 Intf 30 Async R W Not
154. t ate a new DSP project is by o Destination Promo Deectory using an existing project as a I Ej o template The copy CcsProject applet provided in the Pismo Toolset auto mates this task To use this utility select an existing Code Composer project as the Source Project typically one of the example programs sup plied in the Pismo Toolset Next select the directory into which you wish the new project to be created using the Destination Project Directory edit control Then edit the Destination Project Name for the newly created project Finally click the Copy button to create the new project from the template The new project may be opened and used within Code Composer Templote Appheoten Code Alternately you may follow the manual steps below to create a new target DSP project The project name used below is called Test but you should name your project appropriately for your application 51 Building a Target DSP Project Start Code Composer Studio In the default configuration the project window will contain no projects but will contain ER Edt View Project Debug Profiler the default Innovative supplied board initialization GEL file Qa II6x gel Projects Click Project New on the menu bar to create a new DSP project Use External Makefile Export to Makefile Files Add Files to Project Save 6
155. t puts All bytes default to input mode upon the board power up or on reset Bit Function 0 Direction Byte 0 0 Output default 1 Input 1 Direction Byte 1 0 Output default 1 Input 120 Development Package Manual Digital Bit Function 2 Direction Byte 2 0 Output default 1 Input 3 Direction Byte 3 0 Output default 1 Input 4 Input Latch Clock 0 Latched on Digital Read 1 Latched on External Digital Read Clock TABLE 25 Digital IO Port Control Register Bit Definitions The data register allows software to directly read data from port pins programmed for input or write data to pins programmed for output Read operations performed from the data register on port bytes programmed for output will return the current value of the digital I O latch 1 the last value written to that portion of the port For example suppose that the direction controls were programmed to OxC and the data register written with the data word 0x12340000 Since the most significant 16 bits are setup as outputs those pins on the port connector would assume the value 0x1234 A subsequent read of the port would yield the value 0x1234xxxx where xxxx is the value of the signals present on the digital I O connector The input latch clock bit allows the user to select from either software read clocking or external hard ware clocking Writing a zero to the register selects software clo
156. t be provided until registration is successfully completed Additionally some of the development applets will not operate until unlocked with a passcode provided during the registration process To Register click Start Program Files M6713 New User to start the NewUser exe registration application The registration form below will be displayed Registration Information User First Last Hatcher Email Address Telephone Country Code Area Code Number Extension Fax ve Code Number Company Address City State Country y E Register Now Register Later You should fill it out completely and return it to Innovative either via email or fax Upon receipt Inno vative will provide access codes to enable downloading of update software from our website telephone hotline support and unrestricted applet access At this point you have finished the installation process and you are ready to begin development Exit with the OK button Finally the following screen appears At this point you should shut down your computer This will also allow you to physically place the board s into the machine in addition to allowing newly installed com ponents to be initialized 18 Hardware Installation Vista Installation The installation is complete Shut down your computer and install your board s and the key then reboot you
157. template New TMS320C6990 CTE uum dsk6211 cdb Vista CDB c6xxx cdb dsk6711 cdb Sbc6711 cdb c6211 cdb c64xx cdb ll xl Select an icon to see a description e configuration template By default this CDB will be named Configl Save it as Test CDB Estimated Data Size 2765 Est Min Stack em Instrumentation Scheduling Synchronization Input Output CSL Chip Support Library 53 Building a Target DSP Project Though the CDB and its support files have been created on disk you must manually add them to the Test project Right click on Test pjt in the Project window to invoke the project hot menu Click Add Files to add a file to the project ista CPU_1 C6711 Code Composer Stud File Edit View Project Debug Profiler GEL C Test pit Ei Debug Files GEL files amp 16x gel Projects T DS Ge Inc Lib So Export Makefile Set as Active Project Open For Editing Save Close Configurations Properties v Allow Docking Hide Float In Main Window Select the the newly created Test cdb for addition to the project This will implicitly add the auto generated files Testcfg s62 Testcfg s64 for Velocia cards and Testcfg_c c to the project as well CI rx Look in a Test ck E 24 Test CDB File name
158. ter timer chip which uses a digital counter to divide down a high input clock rate the DDS uses phase locked loop synthesizer technology to tune a sine wave oscillator based on a 32 bit digital word This method realizes a linear output frequency over input range rather than the nonlinear one associated with counter timer chips whose resolution drops dramatically as the period register used to program them falls The DDS should be used when a precise and accurate clock is required by the appli cation DDS Jitter Reduction The DDS has the lowest jitter when operating close to its highest frequency of 25 MHz Jitter is typically 100 pS at 20 MHz but is substantially worse at low frequencies This jitter is usually only of concern for high frequency analog sampling gt 10MHz or when the clock is used as a PLL reference The DSP timer clock outputs are lower jitter typically To reduce the jitter the M6713 has a post scaler for the DDS in the logic The post scaler divides the DDS output by 1 to 65536 DOS DDS Output dani Post scaler to logie gt Keep this FIGURE 14 DDS and Post scaler The software support package for the M6713 adjusts the DDS frequency to be as close to 25 MHz as possible then divides the output by a post scale value No resolution restriction is created by this post Development Package Manual 117 M6713 Hardware scaling since the DDS has very fine resolution and when used
159. tes or builds the executable object file and finally downloading and testing the result to see if it functions in the desired fashion In the Innovative Intergration development system these stages are accomplished within the Code Composer integrated development environment IDE By using Code Composer Studio these stages of the programming cycle are accomplished entirely within the IDE The project features of Code Composer Studio support component file editing and compilation stages along with allowing the executable result to be downloaded and tested on the target hardware This fully integrated programmers environment is more user friendly then the basic com mand line interface which comes standard with the TI tools 58 Edit Compile Test Cycle using Code Composer Studio Automatic projectfile creation When a project is created opened modified built or rebuilt the Code Composer Studio dependency generator automatically generates a project makefile named lt project file gt pjt located in the project directory which is capable of rebuilding the project s output file from its components This file is automatically submitted to the internal make facility whenever you click on build or rebuild within Code Composer Studio The make facility automatically constructs the output file by recompil ing the out of date source files including the dependencies contained within those source files Rebuilding a Project It is s
160. that Other applications need to interact with a host program during the lifetime of the program This may vary from a small amount of information to acquiring large amounts of data Some examples Passing parameters to the program at start time Receiving progress information and results from the application Passing updated parameters during the run of the program such as the fre quency and amplitude of a wave to be produced on the target Receiving alert information from the target Receiving snapshots of data from the target Sending a sample waveform to be generated to the target Receiving full rate data Sending data to be streamed at full rate These different requirements require different levels of support to efficiently accomplish The simplest method supported is performing file I O from within Code Composer using either the standard C file functions which communicate directly through CCS to the Host file system or via the Innovative terminal emula 73 Communication to the Host tor which supports simple data input and control and the sending of text strings to the user in addition to file I O However the highest level of support is given by the Bus Mastering Interface This allows sophisticated high rate transfer of commands and information between the host and target It requires more software support on the host than the standard I O does CPU Busmastering Interface Firmware within
161. that do this are called Module Conversion Functions Module Conversion Functions are provided for all supported Omnibus modules See the online help for the module class for a description of these functions An example of the use of these functions SD16 sd16 SD16Ptr AIn Module Gives valid SD16 object A4D4 a4d4 A4D4Ptr AIn Module Returns 0 not an A4D4 Note that a module conversion function will fail if the conversion can not take place Selecting and Configuring Clocks On attachment of the stream to a module the Clock configuration system becomes active It consists of the following methods TABLE 4 Stream object Clock Methods Method Description IsClockSourceSupported Returns True if a clock source is allowed on the hardware SetClockSource Change clock source to the selected source Clock Returns an interface object that allows the configuration of the Clock source The User Interface object returned by the Clock method is used to configure the selected clock source The possible ways a clock can be configured depends strongly on the type of source For example an internal clock such as the DDS can have the clock frequency programmed An external clock can not Rather than provide a complicated set of functions many of which may not work for a clock source we instead separate each distinct part of the User Interface into separate interface classes The interface object for a clock source may supp
162. the automatic execution of target applications employing standard I O 100 CHAPTER 9 M6713 Hardware M6713 Hardware Functions The M6713 is a PCI bus plug in digital signal processor DSP card based around the Texas Instruments TMS320C6713 processor The M6713 is particularly well suited to data acquisition and control tasks and may be equipped with a wide range of Omnibus IO modules for analog and digital interfaces A high performance PCI bus link provides data and control connectivity for network based instrumentation and test equipment The M6713 s features include 1 TMS320C6713 Floating point digital signal processor 2 128MB SDRAM 3 Xilinx Spartan3 1 5M gate FPGA programmable using MATLAB Simulink and VHDL 4 200 MB sec full duplex FPDP communications expansion capability 5 Analog and digital I O expansion using Omnibus compatible I O modules two available slots 6 32 bits of digital I O Synclink and clocklink trigger and clock sharing bus 8 High Performance PCI bus controller Development Package Manual 101 M6713 Hardware 9 JTAG hardware emulation support The following figure gives a block diagram of the M6713 FIGURE 8 M6713 Block Diagram TMS320C6713 DSP i Application L2 Cache amp Logic RAM 256K8 OMA 16 Channels Spartan 3 400k 1500k Spartan 2E 300k PCI Logic PCI 64 bit b6MH INISV Select Post Sealing
163. the executable requires certain BPLs to be in the system directory To build your application without this dependency click the Packages tab on your Project Options menu Deselect Build with runtime packages option What DLLs do I have to deploy with my newly created executable The following DLLs must reside on the path for any deployed Vista application Typically these files are placed in the Windows system directory For Windows 9x the system directory is the C windows system directory For Windows NT it is C Winnt system32 directory Function Required DLLs Intel native signal nsp dll nspa6 dll nspm5 dll nspm6 dll nspp6 dll nsppx dll processing libraries nspw7 dll Intel native image All files in the Innovative Lib Ipp directory tree processing libraries Innovative device iidrvx40 dll driver DLL Code Hammer TIPciPod dll Debugger Innovative Regis UserRegister6 dll BCB users design time only tration DLL How do I know what DLLs my executable is dependent on The Applets Third Party folder contains an archive call depends20_x86 zip which contains a utility called Depends exe the provides a utility that allows you to determine the external dependencies of and Windows executable file Clock File Open from the menu bar and browse to the name of your applica tion executable The utility will list all DLLs on which your application is dependent in order to run Note however that Windows programs are always
164. the frequency of which defines the maximum transfer rate of the bus The bus pro tocol does not include address or arbitration cycles so the data transfer rate is fully defined by the fre Development Package Manual 109 M6713 Hardware quency of the Data Strobe A mechanism is provided to allow a receiver to hold off the transmitter if its memory is almost full this is done using the Suspend Data Signal A mechanism is also provided to allow synchronization of the receiver to the transmitter data stream to provide for memory initialization and so that framed data can be correctly interpreted this is done using the Sync Pulse signal In the Interface FPDP Logic we have provided 512x32 FIFO memory in each direction i e Transmitter FIFO and Receiver FIFO Data is deposited in Tx FIFO port by the DSP as demanded by the process on the other hand Rx FIFO port is read by the DSP as it receives the data from other I O devices An interrupt may be signalled to the DSP based on a programmable FIFO level referred to as the interrupt threshold level For data acquisition applications larger packets may be used to reduce the DSP inter rupt rate at the expense of data latency DMA or CPU transfers MUST consume the same number of points as the threshold value before another interrupt will be signalled This prevents spurious interrupts as the FIFO crosses the threshold value during reads 80 Pin Connector 80 Pin Connector 32 bit Dat
165. through an example servo This example can be found in the distribution in the Servo directory under the Examples directory This servo modifies one channel in a simple but visible way to show the servo effect In actual practice all channels would probably be modified The first interesting operation is the derivation of a new ServoBase class This example does not utilize the non dispatcher to maximize performance The TestServo class informs the base class that the application will not make BIOS calls within the interrupt by the second false argument to the constructor class TestServo public ServoBase public TestServo Omnibus ModuleSite site Servo site false y To derive you need to create a constructor for the new class Since the ServoBase base class requires an argument C can not create one for you The base class needs to be informed of which Omnibus mod ule site is hosting the installed Servo16 I O module In this case we require our servo to have it passed in when it is created An alternative would be to hard code a value and not require or allow the user to change it Next we define our interrupt handler function Overrides pragma CODE_SECTION hwi virtual void Execute volatile short event int inputs int outputs clip above this amplitude const int Threshold 0x4000 if event 0 gt Threshold event 0 Threshold Here we actually define the servo fu
166. tically starts the assembler which produces a obj output file test ob3 Code Composer Studio then invokes the TI Linker using the testcfg cmd file which is located in the project directory This rebuilds the executable file using the newly revised test obj If no errors were encountered this process creates the downloadable COFF file test out which can be run on the target board At this point the program may be run using the terminal emulator applet which may be invoked using the terminal emulator shortcut located within the target board program group cre ated during the Pismo Libraries installation process In the terminal emulator download the test out file The program runs and outputs the message Hello World to the terminal emulator window If errors are encountered in the process Code Composer Studio detects them and places them in the build output window If the error occurred in the compiler or assembler such as a C syntax error the cursor may be moved to the offending line by simply double clicking on the error line within the build output window and the error message will be displayed in the Code Composer Studio status bar If the linker returns a build error the build output window shows the error file From this information the linker failure can be determined and corrected For example if a function name in a call is mis 59 Building a Target DSP Project spelled the linker will fail to resolve t
167. timulus response measurements and many others The tight coupling of the DSP analog IO and other peripherals make the M6713 well suited for a variety of application such as communications baseband process ing ultrasound applications multi axis controllers for high speed servos RADAR SONAR applications communications signal processing and many data acquisition applications The baseboard has a variety of features that make it easy to develop high perfor mance systems On card very low noise power supplies provide clean power for analog peripherals installed into either Omnibus I O site Other features include 32 bits of programmable digital IO FPDP data ports advanced clocking mechanisms multi card triggering and clock sharing plus a flexible timebase for data sampling and timer counters The M6713 features PCI bus mastering interface which sup ports burst transfers are rates to 512 MB sec to the host PC system 31 About the Baseboard Digital Signal Processor The M6713 baseboard uses the TMS320C6713 DSP operating at 300 MHz This DSP is a 32 bit float ing point device The DSP interfaces to the memory and peripherals on the baseboard through its exter nal memory interface EMIF which has programmable definitions for the memory interface timing DSP External Memory The M6713 baseboard provides 128 Mbytes of SDRAM memory mapped to the 6713 DSP CE2 mem ory space This memory provides space for program and data st
168. to the PCI bus The M6713 Interface logic can be downloaded using either the M6713 down loader program using the M6713_intf EXO file PROM image If you are developing custom logic for the M6713 see the FrameWork Logic User Guide that gives detailed instructions on downloading logic images over JTAG or using the downloader program Making Custom Logic See the FrameWork Logic users guide for developing custom logic and MATLAB use 130 Development Package Manual Making Custom Logic Development Package Manual 131 M6713 Hardware 132 Development Package Manual CHAPTER 10 Troubleshooting Initialization Problems Borland C Builder Problems The Builder Help Index system is blank Borland uses the standard Microsoft help system for its online help Normally this works perfectly however Windows 9x Help system has a limitation on the amount of references it can use simultaneously If you have too many links in your help index you will not see any help at all on the index However if you are in Builder and you use the 1 functionality for your help it will work perfectly To get your Help index working again you will need to slim down the contents of the Open Help Index list found Open Builder e Bring up Open Help by selecting Help Customize Click the Index tab Remove files until your Index Help is working Remember to Save the project before checking the Index Help
169. tween two transfers Note that on the TI C671x processor the second transfer must be configured on channels 8 11 Class EdmaMaster This class acts as a holder for functions and information common to all EDMA interrupts instead of associated with a single EDMA channel Only one instance of EdmaMaster is cre ated at program initialization It is accessed by calling the static member function Edma Master Object EdmaMaster contains several functions dealing with the EDMA PRAM This is a memory region shared among all EDMA objects giving a common storage for configuration blocks This is a limited resource so be wary of allocating many Edma blocks and not releasing them The method ClearPram clears all the PRAM blocks in a single operation EdmaMaster contains several functions dealing with the EDMA PRAM This is a memory region shared among all EDMA objects giving a common storage for configuration blocks This is a limited resource so be wary of allocating many Edma blocks and not releasing them Also available are func tions to give access to the area at the end of the PRAM that is not used by the system This scratchpad memory might be of use as a shared memory pool in an application 50 CHAPTER 4 Building a Target DSP Project Building a Target DSP Project Building a project suitable for an M6713 baseboard requires a particular setup of the project By far the easiest way to cre Saca Projec
170. ty Value 0 Change property value as necessary in the right column coca The M6713 has one DSP in the scan path C6713 a TMS320C6x1x device Next click on the C671x XDS510 Emulator board icon within the System Configuration pane of the Code Composer Studio Setup window The center pane will list all compatible processors which may be added to the JTAG scan path Next right click on the CPU_1 icon in the System Configuration pane then click on Properties in the pop up menu to invoke the Processor Properties dialog Edit the Gel File value to point to the board specific initialization GEL script for the M6713 The Innovative installation program automatically installs this file in the root of the board specific libraries toolset directory For example for the M6713 this should be set to c Innovative M6713 II6x gel Processor Properties xi Property Value C NnnovativeNSbcb713eMIBx g m Master Slave N A Change property value as necessary in the right column Summary 25 Installation The resulting final configuration is shown below Code Composer Studio Setup File Edit View Help System Configuration avatable Factory Boards Fandy Ration All y DI RH ARM11 VPOM2420 Platform Simu ARM11 simulator C67 1x XDS510 Emulator Ei MEE C67 1x XDS510 Emulator ARM7 VPOM2420 Platform Simul ARM7 simulator Number of Devices IRE ARM Simulator Big Endian ARM
171. ust have the re enable code in it The introduction of C exceptions makes this problem even worse The Pismo library provides a set of class objects that meet this problem These lock objects disable a particular interrupt or all interrupts in a region and restore the state to what it was on entry when the 43 About the Baseboard lock object is destroyed If the object is created on the stack any means of exiting the block in which the object is defined will cause the cleanup code to be called Calls to these objects properly nest as well TABLE 9 Interrupt Lock Classes Lock Class Interrupts Affected TI Class Library InterruptLock One IRQ CSL GlobalIntLock All interrupts CSL HwiGlobalIntLock All interrupts DSP BIOS Interrupt Binder Templates The Binder system can be thought of as a more flexible and powerful version of a function pointer vari able allowing a user callback function to be called indirectly without knowing more than the interface to the function Since the binder objects are templates the type of the function and its arguments are not fixed but can be of any type Also member functions can be bound to an interrupt which a callback function can never do The Binder system is powerful yet in practice is quite simple to use This system illustrates the power of the C language to contain a complicated system in a simple to use package Class InterruptHandler This class is a base class for the classM
172. vative for reprogramming Sorry I updated the logic but it did not work The most common reasons for this are that the wrong logic image was used or the card was not power cycled between tests The logic is not reloaded until the card is powered up again 135 Troubleshooting 136 CHAPTER 11 Appendices Connector pinouts JP3 JP7 OMNIBUS I O Connectors Connector types JP3 JP7 AMP 05 Subminiature D male AMP 173280 3 JP4 connector 3M N102A0 52E2VC Number of pins JP3 JP7 50 JP5 100 Mating connector JP3 JP7 AMP 173279 3 JP4 3M 101A0 4CZ3JL Development Package Manual 137 Appendices The following table shows the interconnections between the JP4 OMNIBUS slot 0 and JP5 OMNI BUS IO connector JP4A JP3 Module 0 Pin JP4 Pin Numbers cman MDR100RTF 1 100 0 PIN3 S49 0 PIN4 4 OT 0 PIN7 DALLO um 0 PINS 4 0 PIN md O PINTS 6 48 PINS i ene n oe H 0 PIN25 3 PIN O PIN28 10 46 O PINZO O PINO 0 P 11 95 0 PIN33 0 PIN34 12 45 D Males 13 94 Na PE 37 0 PIN 0 P is La mI 16 43 O PING 027 0 Pinag 17 92 0 49 E 26 0 0 18 42 19 91 20 41 21 90 22 40 23 89 24 39 25 88 26 38 27 87 28 37 29 86 30 36 31 85
173. wing the system to share high speed clock and trigger signals A variety of DSP and data acquisition products from Innovative feature SyncLink and Clock Link to allow the construction of multi card synchronized systems for channel expansion and common triggering The SyncLink bus has one master who is the originator of all clock and trigger signals referred to as the master while all other cards are referred to as slave devices The slave cards can only receive clock trigger signals from the master The following table below shows the signals that may be transmitted over the SyncLink bus when it is the master The SyncLink signal selection register resides at 0x80200004 Bit Signal Output Control 0 Sync Master Bit Signal Output as SyncLink 0 1 DSP timer 0 2 DSP timer 1 3 Module 0 DDS Clock 4 External clock 0 J1 5 not used Development Package Manual 127 M6713 Hardware TABLE 34 SyncLink 0 Signal Selection Register Bit Definitions Bit Signal Output as SyncLink 1 6 DSP timer 0 7 DSP timer 1 8 Module 1 DDS Clock 9 External clock 1 J2 10 not used TABLE 35 SyncLink 1 Signal Selection Register Bit definitions Bit Signal Output as SyncLink 2 11 Module 0 Trigger 12 15 not used 16 Module 1 Trigger 17 20 not used 21 Module 2 Trigger 22 24 not used 25 Module 3 Trigger TABLE 36 Syn
174. with the following bit assignments Omnibus Pin Bit Function timer0 0 DSP timer0 Output timer0 1 DSP timerl Ouput timer0 2 SyncLink 0 timer0 3 SyncLink 1 timer0 4 ClockLink In timer0 5 External Clk 0 timer0 6 External Clk 1 ddsO 16 DSP timer0 Output dds0 17 DSP timerl Ouput dds0 18 External Clk 0 dds0 19 External Clk 1 dds0 20 SyncLink 0 dds0 21 SyncLink 1 dds0 22 ClockLink In dds0 23 DDS chip output TABLE 23 Timer0 and DDS Pin Output Sources Module 0 0x80200034 Module 1 0x80200038 Digital I O The M6713 includes 32 bits of software programmable digital I O for use in controlling digital instru ments or acquiring digital inputs If you need additional bit IO the FPDP ports may be used as bit IO also The Digital IO Port is a set of simple input and output latches Outputs are enabled on a byte basis as programmed by the DIO control register The input latch may be enabled to capture the pins whenever it is not being read or whenever an external signal EXT DIG CLK is low as enabled by the Digital IO control register When used in the internal enabled mode the value read is the state of the pins immedi ately before the DSP reads them The external clock signal is actually an enable to the DSP EMIF clock use to clock the latch so it must be high a minimum of 27 nS to guarantee its operation Development Package Manual 119 M6713 Hardwar
175. with the post scaling integer division still results in the full adjustment range The software computes the optimum value for to get low jitter from the DDS Bits Function 15 0 DDS post scaling value The DDS is divided by this number DO NOT enter 0 Default is OXFFFF 0x1 no postscale no divide 31 16 Not used TABLE 21 DDS Post dscaling Control Register Module 0 0x8020002C Module 1 0x80200030 Note that there is a post scaling register for each Omnibus module site allowing different post scaling for each module DDS Control The AD9851 is mapped into memory as shown in the table below The device is inter faced using the parallel I O method with one address to write data one to trigger frequency phase updates and one to control the reset pin of the device Function VO Space Address DDS Control 0x80020000 DDS Data 0x80030000 TABLE 22 AD9851 Control Registers The write clock address latches frequency phase data into the AD9851 one byte at a time The least sig nificant eight bits of the processor bus carry the byte wide data The frequency update address causes the output frequency and phase of the DDS clock to update to the values contained in its input latches The reset address causes an active high reset pulse to be generated to the AD9851 By default the DDS reset is true at power on or reset so a 0 must be written to the DDS reset control bit bit 0 on DDS Control
176. wo should be written to memory location 0x80050000 All interrupt con trol registers default to 0 on power up or board reset Note that the processor interrupt signals generated by the logic are active high rising edge trigger and the C6713 interrupt polarity control register must be programmed to the value 0x0 to correctly receive interrupts Using Interrupts for DMA To use the interrupts to drive a DMA channel on the DSP it is necessary to control the behavior of the interrupt to prevent false interrupt triggering This often occurs when an interrupt is used to read data from a FIFO The typical arrangement is to set a level threshold for the FIFO and to trigger a DMA interrupt when the threshold is crossed The only problem is that the FIFO may also be simultaneously being accessed from the other side so the level can fluctuate as the read write accesses occur This can cause extra interrupts To control this behavior an access counting register is added so that once the interrupt signals a pro grammed number of accesses must occur before another interrupt is issued Our internal parlance for this the interrupt burst counting register This is because the DMA typically reads a burst of data from the FIFO or other device and we count the accesses in the burst The DMA controller in the DSP is pro grammed for a transfer count that is also used to program the interrupt burst counting register When the DMA interrupt signals the DMA co
177. yncLink Connector FIGURE 17 JP12 SyncLink Connector Pin Orientation Development Package Manual 147 Appendices JP14 JP15 Processor Serial Port Connectors Connector type 2 mm double row header Number of pins 10 Mating connector Samtec SQT style for board board applications The following table gives the pin numbers and functions for the JP14 McBSP 0 and JP15 McBSP 1 connectors Pin functions of JP14 are identical to those of JP15 except where noted Direction from Pin Number JP14 Function JP15 Function M6713 1 CLKSO CLKS1 I 2 FSRO FSR1 IO 3 CLKRO CLKRI IO 4 FSX0 FSX1 IO 5 CLKX0 CLKXI IO 6 Digital 3 3V Digital 3 3V Power 7 DRO DRI I 8 Digital 5V Digital 5V Power 9 DXI O 10 Digital Ground Digital Ground Power TABLE 44 DSP Serial Port Connector JP14 HEADER5X2 2MM FIGURE 18 JP14 JP15 DSP Serial Port Connector 148 Development Package Manual Connector pinouts JP16 JTAG Debugger Connector Connector type Shrouded header pin 6 removed for key Number of pins 14 Mating connector AMP 746285 2 The following table gives the pin numbers and functions for the DSP JTAG connector Direction from Pin Number JP16 Function M6713 1 TMS I 2 TRST I 3 TDI I 5 Digital 3V Power 7 TDO O 9 11 TCK I 13 EMUO I O 14 EMUI I O 4 6 8 10 12 Digital ground Power TABLE 45

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