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CPC710 PCI Bridge and Memory Controller User Manual

1. Reset Value x 0000 0000 Address x FFOO 1200 Access Type Read Write o o P D G N N E E 5 ir pS 2 9 S E D 3 5 O N y D E o vo 2 KE o Q gt E O 9 a ke wn gt gt S gt a E D E 2 O o 0 Os E E lt S 3 _ S 6 z Eee 3 2 amp g DO 85 g 2 lt w es a a 5 m o o a E A g Z 0 a 4 S 8 Dual gq o n N bg c l gt 2 a 9 L 5 5 Oo SG Su o BB eo E o 2 Ke Y OG D o no o E 5 lt L V 3 OD o gt o o o 2 2 250 e 20 DON d 2 lt x Ki s gt E FS m ZS o E O Gi a or o oto 0 Ka lt p om 5 222 4 e 5 O g Q a A a o od o FPS DB o 8s 2 gt o 9 w L Ze Loog e o o 2 2 s 222220000802 ZS uc q O 5 2 o lt S e mm E e 29 Os sa 2 oa Q z Ko o Si o CO D o D o DD o 0 0 0 23 E 3 o 2 SA O fo o E 5 bo a Q o Dd o GG oO SS SS SS SS BE BL A OO o wi ao no ao a Ac Rei Rei CC EC EC C Cu Uu Uu SG o OO ZEEEkEE LEICK A a A KA AAE EEKkE a e y ofi 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Global System Memory Address Space Enable 0 0 The CPC710 will not respond to addresses specified in Memory Configuration Extent Register SDRAMO_MCERx 1 System memory address space enabled Diagnostic Mode This bit is used to control presentation of double bit ECC errors to the system This bit is primarily intended for use in
2. 2 O bel LQ a 5 wi 3 o ZS o o UU 2 SECH 23 O 0 D Hr gg KE Sp gt ya so SEKE gt 5 Se Os 5 Reserved SA 20 Reserved y A YY yy 4 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 5 Reserved No SYS_L2 HIT Signal Detected Error Disable 6 0 60x logic will generate TEA on the system bus if SYS_L2_HIT signal not driven active after AACK 1 No action if SYS_L2 HIT detected inactive Disable Data Bus Timeout In the case of timeout the CPC710 activates the CHKSTOP and set bit 20 of the CPCO_SESR Register 7 see CPCO_SESR on page 9 35 0 The CPC710 will signal error if 8ms time out detected from DBG to TA 1 The CPC710 will not signal an error for this condition Address Parity Checking Enable 8 0 60x logic will not check address parity on the system bus 1 60x logic will check address parity on the system bus for CPU to the CPC710 access only In case of parity error the CHKSTOP signal is activated Data Parity Checking Enable 9 0 60x logic will not check data parity on the system bus 1 60x logic will check data parity on the system bus for CPU to the CPC710 access only In case of parity error the CHKSTOP signal is activated 10 28 Reserved Register Summary 9 17 CPCO_ERRC Error Control Register Bit s Description 29 PCI Internal node selection for Debug 0 PCI32 1 PCl64 30
3. Signal Name DIMM and DIMM Bank SDCSI4 DIMM 2 Bank A SDCSI5 DIMM 3 Bank A SDCS 6 DIMM 2 Bank B SDCS 7 DIMM 3 Bank B Memory Controller 6 4 SDRAM Subsystem Overview CPC710 MUX controls MUX_CLKENAT MUX_CLKENA2 MUX_CLKEN1B MUX_CLKEN2B MUX_OEA MUX_OEB MUX_SEL Memory Interface MADDRO_ODD ADDR ODD 12 0 Optional Buffers MADDR 12 1 2 cycles signals LN ADDR EVEN 12 0 MADDRO_EVEN BSO BS1 ES 4 x SDDQM E 2 x SDRAS 2 x SDCAS S 2x WE gt d 10 x SDCKE SDCS 0 7 TI ALVCH162268 l MN nl DH 071 MDATA 0 71 Je A A1 6X B i DL 0 71 DH 0 71 ADDR_EVEN 12 0 DL 0 71 MADDR_ODD 12 0 SDCS2 SDCS3 e SDCSO SDCS1 cc O a c Lu ofl DIMM Bank B DIMM Bank B 2 gt o a SO DIMM Bank A DIMM Bank A SEN Q N Lk DIMM 0 DIMM 1 SDCS6 SDCS7 z SDCS4 SDCS5 E a 0 4 T DIMM Bank B DIMM Bank B e o 9 DIMM Bank A DIMM Bank A Se o N DIMM 2 d DIMM 3 SDRAS SDCAS WE SDCKE BS0 BS1 SDDQM CLK Note The input clock for the SDRAM is the 60x bus clock which is not driven by the device Figure 6 4 SDRAM Interface Block Diagram CPC710 User s Manual 6 5 Supported SDRAM
4. Specifies the length of a device s burst period in 0 25 secs The CPC710 has no specific requirements and therefore always responds with x 00 9 72 CPC710 User s Manual PCICx_ RETRY Retry Counter Reset Value x00 Address x 50 Access Type Read Write PCICx_RETRY D 4 7 6 5 4 3 2 1 0 Bit s Description When the device is a Master on the PCI bus this register is used as a time out mechanism for continuous retries on the PCI bus Whenever a retry occurs for a particular address the PCI bridge logic increments decrements a counter 7 0 The 8 bit counter is reset whenever data is transferred If the count reaches the value specified in this register the PCI bridge logic will not retry the access and will report the Result by writing bit 5 of the PCILx_PLSSR Register see PCILx_PLSSR on page 9 101 After reset the register contains x 00 which disables the retry counter Register Summary 9 73 PCICx_REVID Revision ID Reset Value x03 Address x 08 Access Type Read Only Revision ID b 00000000 Y A 76543210 Bit s Description Provides an extension to the PCI Device ID register 7 0 The CPC710 always responds with x 03 for reads from this register 9 74 CPC710 User s Manual PCICx_STATUS PCI Status This register records status and error information from PCI bus transfers Reads from this register b
5. G_RST P_RST Out i PCI 64 amp 32 bus in Reset PCILx_CRR 0 o 4 4_ PCILx_CRR O0 T 0 Bobi T2 Sys Sys PCI PCI SDRAM Register Initialization Code an 500u Reg Reg 90043 Slots Init Start Config CPCO_RSTR 2 3 00 LL CPCO_RSTR 2 3 11 PCI Internal circuits the CPC710 are in Reset Figure 5 1 Power Up Sequence 5 2 POWERGOOD Power On Reset Using the system Power On Reset POWERGOOD signal the device resets internally and generates a reset signal to all CPUs and I O devices All device I O pins go to tri state After a POWERGOOD Initialization 5 1 cycle outputs on all interfaces are either floating or driven to their inactive state except for the reset signals sent to the board as described below 1 PowerPC bus HRESETO and HRESET1 are driven Low for the same duration as the POWERGOOD active pulse low level 2 PCI64 bus G_RST is driven Low from the beginning of the POWERGOOD assertion and remains active after POWERGOOD is deasserted G_RST is deactivated when the processor writes a 1 into bit O of PCILx_CRR on page 9 90 CPCO_PCIBAR x 000F 7EFO for PCI64 G_RST is deactivated within a period that complies with the PCI Specification 2 for the 64 bit interface 3 PCI32 bus P_RST is driven Low from the beginning of the POWERGOOD assertion and remains active after POWERGOOD is deasserted P_RST is deactivated when the processor writes a 1 into bit O of PCILx_CRR on page 9 90 CPCO_
6. 4 5 1 Precharging SYS_ARTRY and SYS SHD This function is programmable by the bit 12 of CPCO_ABCNTL register The CPC710 can be programmed to precharge the ARTRY_ and SHD_ signals This requires that all devices on the 60x bus must disable their precharge of this signal The CPC710 negates these signals in the second cycle following the last cycle of the ARTRY window for 1 2 of a bus cycle 4 5 2 SYS ARTRY Assertions The CPC710 asserts SYS_ARTRY for e SYNC operations as described in the previous section e EIEIO operations as described in the previous section e XFERDATA when more than two transfers have been initiated aprocessor access to the PCI bus when a PCI ISA bus bridge requests the same PCI bus aprocessor access to system memory when a DMA occurs to the same cache line aprocessor access to system memory when a DMA operation occurs to the same line a processor access into a range of PCI 32 or PCI64 addresses defined as potential deadlock 4 5 3 Recommended SYS_ARTRY Procedure e A master that has had its address tenure retried should negate its SYS_BR n for at least one bus cycle in the cycle immediately following detection of an active SYS_ARTRY e A master that has retried an address tenure due to a snoop hit should activate its SYS_BRIn in the cycle immediately following the detection of an active SYS_ARTRY This ensures the master that retries is serviced before the master that was retried 4 12 CPC710 User s Man
7. CKE 66MHz Clock CBE 7 0 PCI_AD 63 32 mmm PCI_AD 31 0 G_FRAME G_IRDY G_TRDY G_STOP 32 bit Word 1 3 5 7 Add 32 bit Word 2 8 Note 1 2 3 refers to each 32 bit word Figure 10 8 Read 32 Bytes from SDRAM by a PCI Master on a 66MHz PCI64 bus Timing Diagrams 10 7 CLK100MHz MDATA SDRAM_DH SDRAM_DL MADDR RAS CAS WE CKE 66MHz Clock CBE 7 0 PCI_AD 63 32 dm PCI_AD 31 0 G_FRAME G_IRDY G_TRDY G_STOP Figure 10 9 Write 32 Bytes to SDRAM from a PCI Master on the 66MHz PCI64 bus 10 8 CPC710 User s Manual Chapter 11 Signal Summary Signal Name 60x Interface Description UO SYS_BRO 3 SYS_BGO0 3 SYS_TS Bus Request Indicates the device on the 60x bus associated with this signal is requesting ownership of the address bus Should be tied up 1 if unused Bus Grant Indicates the master associated with this signal may with proper qualification assume mastership of the address bus Transfer Start Output Indicates that the CPC710 has started an address tenure and the address bus and transfer attribute signals are valid Only address only operations and snoop operation with programmable TT code are performed Input Indicates a
8. PLL_RANGE1 0 PLL frequency range selector for the System Clock 00 50 to 100 MHz 01 58 to 114 MHz 10 66 to 134 MHz 11 80 to 160 MHz PLL_LOCK Output indicating the PLL is locked O Loop stability tuning control of the PLL Recommended values 010101 if range is 50 to 100 MHz Sech HS 010011 if range is 58 to 114 MHz 010011 if range is 66 to 134 MHz 010011 if range is 80 to 160 MHz PLL_RESET Reset and Bypass mode enable of the PLL CEO TEST Reserved Power GND Ground n a OVpp Output driver voltage 3 3V n a Vop Logic voltage 2 5V n a AVpp Analog voltage 2 5V Filtered supply for PLL circuits n a Other pins Reserved Do not connect signals voltage or ground to these pins n a 11 6 CPC710 User s Manual Index C CPCO_ABCNTL 9 10 CPCO_ATAS 9 13 CPCO_AVDG 9 15 CPCO_ERRC 9 17 CPCO_GPDIR 9 19 CPCO_GPIN 9 20 CPCO_GPOUT 9 21 CPCO_MPSR 9 22 CPCO_PCIBAR 9 23 CPCO_PCICNFR 9 24 CPCO_PCIENB 9 25 CPCO_PGCHP 9 26 CPCO_PIDR 9 29 CPCO_RGBANO 9 30 CPCO_RGBAN1 9 31 CPCO_RSTR 9 32 CPCO_RTBR 9 33 CPCO_SEAR 9 34 CPCO_SESR 9 35 CPCO_SIOCO 9 38 CPCO_SIOC1 9 40 CPCO_SPOR 9 41 CPCO_SRST 9 42 D DMA0_GSCRx 9 45 DMAO_UXWAR 9 53 DMAO_XCLRx 9 47 DMAO_XPARx 9 48 DMAO_XSCRx 9 49 DMA0_XSSRx_ 9 50 DMAO_XTARx 9 52 P PCICO_DLKRETRY 9 54 PCIC1_INTRESET 9 55 PCIC1_ITADDSET 9 56 PCIC1_PPBAR 9 57 PCIC1_PSBAR 9 58 PCICx_BIST 9 59 PCICx_BUSNO 9 60 PCICx_CACHELS 9 61 PCICx_CLS 9 62
9. Register x128 Register x 68 Register x 00 BOOT ROM 2 MB PCI32 PHB BAR FF50 0000 for example when CPCO_CNFR 30 31 10 PCI64 PHB BAR FF40 0000 for example when CPCO_CNFR 30 31 11 System Space Address Map Boot RO M Space Specific PCI 32 Host Bridge Space PCILO_PSEA PCILO_PR PCILO_ACR PCILO_PIBAR PCILO_PMBAR PCILO_INTACK PCILO_CRR PCILO_CFGADDR PCILO_CFGDATA PCILO_PSBAR PCILO_PPBAR PCILO_BARPS PCILO_BARPP PCILO_CSR Specific PCI64 Host Bridge Space PCIL1_PSEA PCIL1_PR PCIL1_ACR PCIL1_PIBAR PCIL1_PMBAR PCIL1_INTACK PCIL1_CRR PCIL1_CFGADDR PCIL1_CFGDATA PCIL1_ITADRESET PCIL1_INTSET PCIL1_BARPS PCIL1_BARPP PCIL1_CSR Device Specific Configuration Space Standard System Configuration Space DMA Space DMA0_GSCRU DMA0_GSSRU DMA0_XSCRU DMA0_XSSRU DMAO_XTARU DMAO_XPARU DMA0_XWARU Specific System Space CPCO_UCTL CPCO_MPSR CPCO_SIOCO CPCO_60XC CPCO_SRST CPCO_ATAS CPCO_AVDG CPCO_ERRC CPCO_SEAR CPCO_SESR CPCO_PGCHP CPCO_GPIN CPCO_GPOUT CPCO_GPDIR Standard System Space PCILO_PSSIZE PCILO_CTLRW PCILO_PPSIZE PCILO_BIODLK PCILO_IOSIZE PCILO_TIODLK PCILO_MSIZE PCILO_BPMDLK PCILO_SMBAR PCILO_TPMDLK PCILO_SIBAR PCILO_PCIDG PCILO_PLSSR PCIL1_PSSIZE PCIL1_CTLRW PCIL1_PPSIZE PCIL1_BIODLK PCIL1_IOSIZE PCIL1_TIODLK PCIL1_MSIZE PCIL1_BPMDLK PCIL1_SMBAR
10. 01100 Kill sector No action To verify the coherency between Cache and System memory with a PowerPC 750 it is necessary for the CPC710 bridge chip to modify the TT 0 4 and thus oblige the PowerPC750 to react on snoop operations with the Address only cycles on the 60x bus It is possible to program the CPCO_ATAS register such that the Clean Flush Kill code are modified in a Snoop code for PowerPC750 Typical changes of TT 0 4 code for the PowerPC750 Clean TT O 4 00000 gt Read TT O 4 01010 Flush TT 0 4 00100 gt RWITM TT O 4 01110 Kill TT 0 4 01100 gt RWITM TT 0 4 01110 After modification to perform Cache Memory coherency the new Address only cycles are TT 0 4 OperationAnswer from the PowerPC750 TT 0 4 Answer from the 750 01010 Read Flush or Kill 01110 RWITM Flush or Kill 01110 RWITM Flush or Kill Typical CPCO_ATAS programming CPCO_ATAS 0 31 0x709C2508 TSIZ 0 2 and TBST can be programmed on the Address only cycles to the following recommended values TSIZ 0 2 000 et TBST 1 Flush modification to RWITM CPCO_ATAS 0 4 lt 01110 CPCO_ATAST 5 7 lt 000 CPCO_ATAS 8 lt 1 Kill modification to RWITM CPCO_ATAS 10 14 lt 01110 CPCO_ATAS 15 17 lt 000 CPCO_ATAS 18 lt 1 Clean modification to READ CPCO_ATAS 20 24 lt 01010 CPCO_ATAS 25 27 lt 000 CPCO_ATAS 28 lt 1 The modification is active only if bit 25 of the CPCO_PGCHP is set to 1 CPCO_PGCHP 25
11. IN A Ze W Tedak ale dab A Ek te d E EE ko Ji ee E ti CL fob O deb J mMjeb Jee O O See gt eh o 5K oS Se Wj L4d oles e L WM JMO O A A m Ed o l IER ite MEM_PCICx_STATUSUS CLK100MHz SYS_ADDR SYS_DATA MUX_MDATA MEM_DATA DH MEM_DATA DL MADDR SDDQM SDCKE SYS_TS SYS_TA Figure 10 4 Write Burst Page Miss from PowerPC CPU to SDRAM CPC710 User s Manual 10 4 22 23 24 25 10 5 Modified DW 0 Write Prech 18 19 20 21 Modified DW 0 17 DW 0 Timing Diagrams 13 14 15 16 AQ _DW 0 H S L tene 10 11 7 4 4 o o EE e DEE KREE JW 4 eut rol ee AREA SEN o o cc ee Ate aoe E Mt Ze Mes fe E PARA A ee esos ed La 0 lt lO MEM_PCICx_STATUSUS CLK100MHz SYS_ADDR SYS_DATA MUX_MDATA MEM_DATA MADDR SDDQM SDCKE SYS_TS SYS_TA Figur
12. Be e ere CS leor 2 e Em HOT Se co mid La eg oi ES So N vi il y PD SS SR AREA 7a Hei TURT AS o Gehalt r Sea Pe KS E b i Ki om SE WE Bien D EL Ie E E EC NEEN E ENEE EE EM a 8a o Sa 3 oS EE SL Jk 7 H D W r ul NEEN WE ENEE BEEM E al See o o Z a2 SL KR bal ro ae E an 0 Figure 10 3 Write Burst Page Hit from PowerPC CPU to SDRAM SE H Rav 23 4 TUE Ni JS d MEM_PCICx_STA CLK100MHz SYS_ADDR SYS_DATA MUX_MDATA MEM_DATA DH MEM_DATA DL MADDR SDDQM SDCKE SYS_TS SYS_TA 10 3 Timing Diagrams CERS EC o D MM Se Sell EENG AA eN grg E RA EE JE EA EES EN E E EE N CH E we 2d BB Ie Je Je L GEL NU E D EA tenths BI N N N Q 2 u_ Cf A CIR O O R weal EA o o SSC ME A 4d DS H DEE MEA EE EU Le H E Dt A EE A AAA kel SE WI Fe E DE D E EE IN NEE EE EEN SE N om T WI f TP O TS gt lg EEN TI O A A oe e Oo oe W L A bef Oh S EE E Lk AAA wo Lea e W ee q 4 L4 L4 42 l CEE A ee rere ae wt n oO z N l
13. F80 128 MB x F00 256 MB x E00 512 MB x C00 1 GB x 800 2 GB x 000 No Write Protected Space Enable Writing in the protected space Inactive 0 a write is possible Active 1 the write is not possible 28 Both cases differs on the memory side by activation of the SDRAM Data Mask DQM_ signals It is thus necessary to set the bit 11 of the SDRAMO_MCCR 11 1 to inhibit writing Register Summary 9 125 SDRAMO_MWPR Memory Write Protection Register Bit s Description Enable IT1 Interrupt generation when target address is in the Write Protect zone 29 IT1 is active during 4 system cycles Bit FINE when 1 finer granularity is set minimum 4 KB The result is unpredictable if bit CPCO_PGCHP 27 1 0 If FINE bit is not active reset 0 the memory size is decoded on the 12 MSB bits of the memory address gt minimum memory step size 1 MB 1 If FINE bit is active 1 the address have 8 more bits The minimum memory step size is 4 KB with address on 20 bits 30 The 8 additional bit LSB of the memory Base address are in bits 24 31 of PCIC1_PPBAR or PCILO_PPBAR PCI interface register address 000F8150 The 8 additional bit LSB of the protected Space Size are in the Register PCILx_PPSIZE 24 31 PCI interface register address 00F8110 31 Reserved Example How to protect in write a memory zone of 8 KB from address 0x02024000 to 0x02025FFF SDRAMO_MWPR 0 11 0x020 S
14. FF20 0004 x FF20 0008 to xFF20 0014 Reserved Reserved x FF20 0018 CPCO_PCIBAR x FF20 0020 to xFF20 OFFF Reserved Base Address Register Device Specific Configuration Space x FF20 1000 CPCO_PCIENB PCI BAR Enable Register x FF20 1004 to x FFDF FFFF BOOT ROM Reserved x FFEO 0000 to xFFFF FFFF IPLROM FLASH ROM Up to 2 MB RO Read Only Register Not decoded by system logic Byte accesses allowed WO Write Only Register PASARON All bits can be read Only bits 4 31 can be written All bits can be read Only bits 0 3 can be written Four beat burst read operations allowed to this address space Single byte writes only Range that IBM Dual Bridge and Memory Controller responds to is programmable 9 2 Standard PCI Configuration Space There are two sets of PCI Configuration Space registers one for each PCI bridge These registers are accessed by a R W of the PCILx_CFGDATA with the address of the target register of the Register Summary 9 5 corresponding PCI bus in the PCILx_CFGADDR 7 2 Configuration Address register which specifies the register number and operation to perform Device ID Vendor ID Status Command Subclass Code Prg Intf Rev ID Header Latency Cache Type Timer Line Size PCIC1_PSBAR for PCI64 only Reserved for Base Address Registers Reserved Reserved for Expansion ROM Base Addr Reserve
15. PCIL1_TPMDLK PCIL1_SIBAR PCIL1_PCIDG PCIL1_PLSSR CPCO_PCIENB CPCO_PCIBAR DMA0_GSCRP DMAO_XTARP DMA0_GSSRP DMAO_XPARP DMA0_XSCRP DMAO_XWARP DMA0_XSSRP CPCO_RGBANO CPCO_RGBAN1 SDRAMO_MCCR SDRAMO_MEAR SDRAMO_MESR SDRAMO_SIORO SDRAMO_SIOR1 SDRAMO_MCERO SDRAMO_MCER1 SDRAMO_MCER2 SDRAMO_MCER3 SDRAMO_MCER4 SDRAMO_MCER5 CPCO_PIDR CPCO_PCICNFR CPCO_RSTR CPCO_SPOR 4 GB 16 MB 31 Standard PCI Configuration Space Register number is specified in PCILx_CFGADDR PCI64 PCICx_VENDID PCIC1_PPBAR PCICx_MAXLTNCY PCICx_DEVID PCIC1_PSBAR PCICx_BUSNO PCI32 PCICx_CMD PCICx_HDTYPE PCICx_SUBNO PCICx_STATUS PCICx_LATTIM PCICx_DISCNT PCICx_REVID PCICx_INTLN PCICx_RETRY PCICx_CLS PCICx_INTPN PCICx_DLKRETRY PCICx_CACHELS PCICx_MINGNT PCIC1_ITADDSET o PCIC1_INTRESET Note BOXED registers are key registers that define PCI bus configuration and register settings 9 2 Figure 9 1 CPC710 Register Address Map CPC710 User s Manual Table 9 1 System Registers List Address Name Use Page Notes x FFOO 0000 to x FFO0 0007 Reserved Standard System Registers x FFOO 0008 CPCO_PIDR Physical Identifier Register x FF00 000C x FF00 0010 CPCO_PCICNFR CPCO_RSTR Connectivity Configuration Register Connectivity Reset Register x FF00 0020 x FF00 00E8 CPCO_RTBR CPCO_SPOR Refresh Time Base Register Software POR Reg
16. e CAS Latency 2 or 3 e Burstlength 2 e Maximum tRCDmin allowed is 2 or 3 Clock cycles e Maximum tRPmin allowed is 2 or 3 Clock cycles e Maximum tRASmin allowed is 5 or 6 Clock cycles Table 6 1 Memory Performance for Cache Line Operations ECC Active Pipeli CAS Latency 2 CAS Latency 3 ipeline o d Levels peration 133 MHz 133 MHz Initial 212MB s 16 1 2 1 193 MB s 18 1 2 1 Read Burst Page Hit 532 MB s 4 1 2 1 426 MB s 6 1 2 1 Sustained Page Miss 304 MB s 10 1 2 1 266 MB s 12 1 2 1 2 Initial 709 MB s 3 1 1 1 709 MB s 3 1 1 1 Write Burst Page Hit 532 MB s 5 1 1 1 532 MB s 5 1 1 1 Sustained Page Miss 355 MB s 9 1 1 1 355 MB s 9 1 1 1 Memory Controller 6 1 6 2 Bank Definitions The term bank can have several meanings depending on context 1 SDRAM banks 2 DIMM banks 3 Interleaved banks 6 2 1 SDRAM Banks As shown in the following diagram SDRAMs contain memory arranged in two or four banks The memory controller selects these banks using bank select BS address pins 6 2 2 DIMM Banks As shown in the following diagram DIMMs are available in single bank and dual bank configurations Single Bank DIMM Dual Bank DIMM Nothing on side B SDRAM Chip These 5 chips constitute DIMM Bank A These 5 chips These 5 chips constitute constitute DIMM Bank A DIMM Bank B Bank Physical Representation Schematic Representation Schemati
17. 31 1 Improper alignment of addresses when Address Increment bit is off XTAR address not doubleword aligned and XPAR address not cacheline aligned Register Summary 9 51 DMAO_XTARx DMA Transfer Translated Address Register Reset Value x 0000 0000 Address User x FF1C 00A0 Privileged x FF1E 00A0 Access Type Read Write User and Privileged Translated Address 4 4 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Translated Address Contains the 32 bit real address presented on the processor bus during the ecowx eciwx trans fer A write to this register will start the DMA operation 9 52 CPC710 User s Manual DMAO_XWARx DMA Transfer Write Back Address Reset Value x 0000 0000 Address User x FF1C 0090 Privileged x FF1E 0090 Access Type User Read Only Privileged Read Write DMA Chaining Enable Writeback Address Reserved y A A D 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Writeback Readback Address This register contains the real address used by the CPC710 to read its next buffer descriptor in memory at the end of 0 26 the DMA transfer operation For the last buffer description this register contains the real address used by the CPC710 to write its completion sta tus 27 30 Reserved assumed to be zero
18. 55 33 77 22 66 00 00 00 22 11 00 22 11 00 00 00 33 22 11 22 11 00 00 44 00 33 22 22 00 11 55 00 44 00 33 22 66 11 55 00 44 22 66 11 55 00 00 22 11 00 00 11 00 00 33 00 22 11 00 11 00 44 00 33 00 22 11 11 55 00 44 00 33 00 22 11 55 00 44 00 33 11 55 00 44 0011 0111 1110 1100 1001 0011 1000 0001 0011 1110 0111 1100 1000 0001 0000 0001 1110 0011 1100 0111 1000 0000 0000 1110 0001 1100 0011 1000 0111 1000 0000 1100 0001 1000 0011 0000 0000 1000 0001 0000 60x Interface 4 3 TSIZE 8 Bytes O 11 22 33 44 55 66 77 88 BURST 0 44 33 22 11 0000 4 88 77 66 55 0000 4 1 1 PowerPC Processor Behavior Mode The CPC710 supports PowerPC 604 and 750 processors operating in Big Endian BE and Little Endian LE modes The mode determines the order in which a multibyte scalar is stored in memory or I O In BE mode the specified address contains the scalar s most significant byte MSB the next sequential address contains the second MSB and so on In LE mode the specified address contains the scalar s least significant byte LSB the next sequential address contains the second LSB and so on 4 1 1 1 Processor Behavior in LE Mode PowerPC 604 and 750 processors normally operate in BE mode To operate in LE mode the processors generate an LE address internally and then modify or munge the thre
19. A5 AG A20 A21 A22 A23 A24 A25 A2 A2 Row Address A0 A4 A7 AQ AlO Alt A12 Aid Aid AE Al6 Al AIS A Col Address 0 Au A2 A3 A6 A20 A21 A22 A23 A24 A25 A26 A27 DP 13 9 2 O default RowAddress AO A4 A7 AQ AiO Alt AIS A3 Aid AS Al6 A AS A Col Address 0 Au A2 A3 AG A20 A21 A22 A23 A24 A25 A2 Aer 1310 2 O default Row Address AD A4 A7 AQ AlO Alt A12 Ala Al AE Al6 Al AE A Col Address 0 Au A2 A3 A6 A20 A21 A22 A23 A24 A25 A26 A27 DP 13 11 2 O default RowAddress AO A4 A7 AQ AiO Alt AIS Ai3 Aid AS Al6 A AS A Col Address 0 Au A2 A3 AG A20 A21 A22 A23 A24 A25 A2 Aer 1312 2 O default Row Address A3 A4 A7 A9 A10 Ati Ai2 Ais Aid Ais ME Ai M MIO pe eg SSC Col Address 0 Au A2 A3 AG A20 A21 A22 A23 A24 A25 A2 A27 Row Address A2 A4 A7 AQ AiO ATI Ai2 Aid Aid AS ME MI M A19 y E Se Col Address 0 Au A2 A3 AG A20 A21 A22 A23 A24 A25 A26 A2 Row Address AT A4 A7 A9 AiO Ati A12 Ais Aid Ais AG Ai M ATO pp amg See Col Address 0 Au A2 A3 AG A20 A21 A22 A23 A24 A25 A26 A27 Row Address AO A4 A7 AQ AiO Alt AIS Ai3 Aid AS Al6 Ai AS A Col Address 0 Au A2 A3 A6 A20 A21 A22 A23 A24 A25 a2 Aer DD AB 14 12 2 0 default 1 The Memory Controller interleaves with only one memory address bus To handle critical word load individual control of the LSB column address bits is required for the DIMMs MADDRO_ODD is used for the LSB address of the even and odd DIMMs 2 Bit 10
20. O No Error 8 1 This bit is set if the following 3 conditions are met 1 PCI Bridge asserted or observed P G_PERR signal on PCI bus 11 PCI Bridge acting as master 111 Bit 6 of Command Register set Target Fast Back to back Capable Read Only 7 Always returns a 1 to indicate that the PCI Bridge as a target will accept fast back to back transfers when the trans fers are not to the same device 6 0 Reserved 9 76 CPC710 User s Manual Reset Value x00 Address x41 Access Type Read Write Subordinate Bus Number 7 6 543210 Bit s Description 7 0 Specifies the largest bus number beneath this bridge After reset this register contains a value of x 00 PCICx_SUBNO Subordinate Bus Number Register Summary 9 77 PCICx_VENDID Vendor ID This register identifies the device manufacturer Reset Value x1014 Address x 00 Access Type Read Only VID b 0001 0000 0001 1000 y y 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Bit s Description Vendor Identification Number 15 0 Value x1014 x 14 for address 00 and x 10 for address 01 9 78 CPC710 User s Manual PCILO_PPBAR PCI Base Address for PCI to System Extended Access Only the PCI32 bit bridge has this register at these location For PCI64 bit bridge this register is in Stan dard PCI Configuration Space on page 9 5 This register must be used if extended memory space is used see bit
21. es SH lt e e lt lt 92 O E og s x T D how E I o SD a cr WwW O E o CS 4 ES gt st kO o y t Se o MES g 3 ES o a D SR el i oi SECHER ei o o sa D e 2 yp ze 6A O O gt ZS O O x Se 3 O gt 5 gt eg S 24256 ax eg oO SC De e O al a O Reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI32 Host Bridge Address Map Type Controls which address map is used See Address Maps on page 2 1 00 PREP mode SS 01 CHRP mode with the PCI32 Host Bridge defined as the PCI Host Bridge 0 PHBO 10 FPHB mode Base address on PCI32 is used 11 CHRP mode with the PCI 32 Host Bridge defined as the PCI Host Bridge 1 PHB1 The PCI64 is PHBO PCI64 Host Bridge Address Map Type Controls which address map is used See Address Maps on page 2 1 PREP mode 2 3 CHRP mode with the PCI64 Host Bridge defined as the PCI Host Bridge 0 PHBO FPHB mode Base address on PCI64 is used CHRP mode with the PCI64 Host Bridge defined as the PCI Host Bridge 1 PHB1 The PCI32 is PHBO 9 26 CPC710 User s Manual CPCO_PGCHP Chip Programmability Register Bit s Description Peripheral Memory Alias Enable This bit is used in CHRP mode only for processor initiated transactions to PCI Memory ki O No translation for processor access in the Peripheral memory alias space 1 Translate an address in the Peripheral memory alias spa
22. memory testing at power on time Software can use this bit when testing memory and or ECC logic in order to avoid the 1 hardware generating a machine check for double bit ECC errors The error however is still logged into the SDRAMO_MEAR 0 Normal Mode Multi bit ECC error will generate Machine Check 1 Diagnostic Mode Multi bit ECC does NOT generate Machine Check logged in SDRAMO_MEAR and SDRAMO_MESR SDRAM Initialization Status read only 2 0 SDRAM initialization is not completed 1 SDRAM initialization is completed 9 116 CPC710 User s Manual SDRAMO_MCCR Memory Controller Control Register Bit s Description ECC Mode This field provides software with a means to control ECC generation and checking b 01 is provided to allow software direct read write access to the ECC byte that is associated with every doubleword of data stored in memory and also provide a mechanism to verify the memory controller s ECC generation and checking logic In this mode byte lane O data MSB of a double word is written to the ECC byte instead of the normal ECC code byte Data byte 0 will be forced to all zeros For reads byte 0 will contain the byte stored in the ECC byte not the data at byte 0 ECC checking is not enabled for reads in this mode This mode also allows firmware write single bit and multi bit errors into memory to allow for ECC logic testing 00 Normal generation and checking of ECC codes 3 4 The device wil
23. 0 604 1 750 or later version TEA Control Disable 26 0 SYS_TEA is driven 1 SYS_TEA is not driven but Machine Check signal is only if CPCO_PGCHP 17 1 4 GB memory adress space for PCI access 27 0 The maximum memory space size is 2 GB 1 The maximum memory space size is 4 GB available for FPHB Mode or CHRP mode only DD2 0 ERRATA 10 correction for fast back to back mode 28 0 ERRATUM is not corrected 1 ERRATUM is corrected 29 31 Reserved R W Must be left to O 9 28 CPC710 User s Manual CPCO PIDR Physical Identifier Register This register provides a unique number for each processor or any 60x bus master reading this location It is primarily used by processors to differentiate themselves in multiprocessor configurations When this reg ister is read the CPC710 latches the current processors SYS_BR SYS_BG pair into this register which physically identifies the processor Each processor has a unique SYS_BR SYS_BG pair connected to it Reset Value x 0000 0000 Address x FFOO 0008 Access Type Read Only Reserved Physical Identifier D vy 4 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 23 Reserved Physical Identifier The CPC710 responds with two values for this field x00 Indicates processor associated with BRO and BGO pins 24 31 x01 Indicates processor associated with BR1 and BG1 pins x02 Indicates proces
24. 00 00 00 00 00 00 00 00 00 00 3 Bytes 00 11 22 33 00 00 11 22 00 00 00 11 00 00 00 00 00 00 00 00 4 Bytes 11 22 33 44 00 11 22 33 00 00 11 22 00 00 00 11 00 00 00 00 5 Bytes 11 22 33 44 00 11 22 33 00 00 11 22 00 00 00 11 6 Bytes 11 22 33 44 00 11 22 33 00 00 11 22 7 Bytes 11 22 33 44 00 11 22 33 00 22 11 00 00 00 00 33 22 11 00 00 44 33 22 11 55 44 33 22 55 44 33 55 44 00 00 22 11 00 00 00 00 33 22 11 00 00 44 33 22 00 55 44 33 66 55 44 66 55 00 00 00 22 11 00 00 00 00 33 22 00 00 00 44 33 00 00 55 44 00 66 55 77 66 00 00 00 00 22 00 00 00 00 00 33 00 00 00 00 44 00 00 00 55 00 00 66 00 77 BURST BURST BURST BURST BURST BURST BURST BURST BURST BURST BURST BURST BURST BURST BURST b amp b OG OG OG O Aa GG OG OG OO Aa W GG OG OO O Aa fb GG OO b amp b OF OG oO WG ORAO ER 11 00 00 00 22 00 33 22 00 11 00 00 33 44 33 00 22 00 11 00 44 44 00 33 00 22 00 11 55 44 00 33 00 22 66 44 00 33 77 11 00 00 00 22 11 33 22 11 00 00 00 33 22 33 22 00 11 00 00 44 33 33 00 22 00 11 55 00 44 33 00 22 66 11
25. 0000 0000 Address CPCO_PCIBAR x 000F 8010 Access Type Read Write PCILx_CFGDATA D 4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Description PCI Configuration Data Virtual 32 bit Register 31 0 When this Little Endian register is accessed in Read or Write the CPC710 initiates a PCI Configuration Read or Write cycle of external PCI devices the address of which is provided by PCICx_CFGADDR Register Summary 9 89 PCILx_CRR Component Reset Register This register provides software with a means to disable all devices on the PCI bus by writing a zero in bit 0 Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 7EFO Access Type Read Write E oc o o Reserved S ZS b11111 Reserved y y y y y 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Device Reset 0 0 Reset signal P_RST or G_RST is active 1 Reset signal inactive 1 5 Reserved Must be left to 1 6 31 Reserved 9 90 CPC710 User s Manual PCILx_CSR Channel Status Register This register is used to log errors during PCI Master to system transfers See PCI Master Error Handling on page 7 7 for additional details Reset Value x 0000 0000 Address CPCO_PCIBAR 000F 9800 Access Type Read Write yi Reserved Arbitration Level Reserved d
26. 02
27. 09 to 0B DC 0D PCICx_LATTIM 9 62 9 61 Latency Timer 9 70 Cache Line Size PCICx_HDTYPE PCICx_BIST Header Type 9 67 Built In Self Test PCIC1_PSBAR PCI Base Address for PCI to System access PCI64 only for PCI32 see Specific PCI Host Bridge Space PCIC1_PPBAR PCI Base Address for PCI to System extended access PCI64 only for PCI32 see Specific PCI Host Bridge Space PCICx_INTLN PCICx_INTPN Interrupt Line Interrupt Pin PCICx_MINGNT PCICx_MAXLTNCY Minimum Grant Maximum Latency PCICx_BUSNO PCICx_SUBNO Bus Number Subordinate Bus Number PCICx_DISCNT PCICx_RETRY Disconnect Counter Retry Counter PCICO_ DLKRETRY PCIC1_ITADDSET Auto Retry Counter for access in Peripheral space with potential deadlock Set PCI64 Inter Processor INT1 Interrupt PCIC1_INTRESET Reset of INTA INTB INTC INTD on the PCI64 Read Only Register write is ignored Writes will only reset bits in this register write data interpreted as 1 reset O ignore y 2 3 Only for PCI32 4 Only for PCI64 Register Summary 9 7 9 4 Specific PCI Host Bridge Registers There are two almost identical sets of registers one for each PCI bridge that can be placed by the user in the upper 16MB of the System Memory One CPCO_PCIBAR value Base Address has to be defined first for each PCI bridge for example as shown in Figure 9 1 on page 9 2 BAR_PCI32 FF50 0000 and
28. 1 Operates as a 64 bit bridge G_REQ64 always activated for CPC710 initiated transfers DMA Pipeline Enable When pipelining is enabled the CPC710 internal buffering is effectively doubled two 32 byte buffers instead of one are used for data transfer This improves DMA transfer performance 0 DMA transfers are NOT pipelined 1 DMA transfers are pipelined 2 31 Reserved Must be set to 0 Register Summary 9 99 PCILx_PIBAR PCI Base Address for I O Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 7800 Access Type Read Write PCI Base Address Reserved 4 vy y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI Base Address Contains the upper bits of the PCI base address that PCI I O is mapped to Note Address must be aligned on boundary equal to size specified in PCI I O Size register 12 31 Reserved 9 100 CPC710 User s Manual PCILx_PLSSR Processor Load Store Status Register This register provides error status information for all transfers initiated by the CPU a PCI master or the other PCI Bridge logic See Error Handling for CPU Initiated Transactions on page 4 15 for additional details on this register Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 9810 Access Type Read Write 5 jo BER 2038 ag su Ka oc A e 3 2 Re BO fo 16 a gt 8 Q oo R d bs
29. 128 x 203 x 3F0 x 3F0 128 1 256 Not equipped x 3C0 off 256 2 256 256 x 003 x 3C0 x 3C0 256 1 512 Not equipped x 380 off 512 2 512 512 x 002 x 380 x 380 512 1 1024 Not equipped x 300 off 1024 2 1024 1024 x 000 x 300 x 300 1024 1 2048 Not equipped x 200 off 2048 2 2048 2048 x 200 x 200 2048 1 4096 Not equipped x 000 off 1 DIMM size is the size in MB of one DIMM including Bank A and Bank B if dual bank DIMM 2 Number of banks per DIMM One for single bank DIMM and two for dual bank DIMM 3 x in SDRAMO_MCER x 0 2 4 or 6 4 a setting of off indicates that the bank must be disabled by setting SDRAMO_MCER x Bit 0 0 6 10 Error Handling The memory controller detects four errors 1 Single bit ECC 2 Multi bit ECC 3 Invalid address Memory Controller 6 15 4 Overlapping memory extents Errors 2 3 and 4 are considered hard errors If one occurs it is logged into SDRAMO_MESR and SDRAMO_MEAR and cannot be overwritten with a subsequent hard error Single bit ECC errors are considered soft and once logged into the soramo_MEAR and SDRAMO_MESR can be overwritten with a subsequent hard error 6 10 1 Single Bit ECC Error General Case The hardware procedure for this error is 1 Set the single bit error bit in the SDRAMO_MESR register 2 If neither a double bit error nor an address error is present store the syndrome in the SDRAMO_MESR and the address in SDRAMO_MEAR 3 Corrected data is
30. 27 of CPCO_ PGCHP register and if FPHB mode is selected this register has no action in CHRP mode or PREP mode Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8150 Access Type Read Write Reserved PCI64 Base Address for PCI32 D A y 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 23 Reserved PCI Base Address 24 31 Contains the upper bits of the PCI Base address that PCI is mapped to Register Summary 9 79 PCILO_PSBAR PCI32 Base Address for PCI to System Access Only the PCI32 bit bridge has this register at these location For PCI64 bit bridge this register is in Stan dard PCI Configuration Space on page 9 5 Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8140 Access Type Read Write R ssied System Base oe for PCI D y A y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 23 Reserved PCI Base Address 24 31 Contains the upper bits of the PCI Base address that PCI is mapped to 9 80 CPC710 User s Manual PCIL1_INTSET Set PCI64 Interrupt Register This register exists only for PCI64 Interrupt can be set only by the CPU Address CPCO_PCIBAR 000F 8310 Access Type Write Only Set_INT Reserved A vv A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
31. 30 31 Bit s Description Set_lt Writing 1 by the CPU set the bit corresponding Writing O has no action 0 3 Bit O INTA Bit 1 INTB Bit 2 INTC Bit 3 INTD 4 31 Reserved Register Summary 9 81 PCIL1_ITADDRESET Reset Addressed Interrupt Register This Virtual register exists only for PCI64 bridge Only the CPU can write to this register and reset the IT1 output interrupt signal Address CPCO_PCIBAR 000F 8300 Access Type Write Only Reset_addit Reserved D e d D 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bits Reset_addit 0 7 1 Writing a 1 in one of these 8 bits resets the interrupt signal IT1 0 No action 8 31 Reserved 9 82 CPC710 User s Manual PCILx ACR Arbiter Control Register This register provides software with a means to disable individual devices on the PCI bus from generating master bus operations Reset Value x 0000 0000 Address CPCO_PBIBAR x 000F 7F30 Access Type Read Write DD De 0 0 Ds Orr D QO O 0 2 2 0 0 2 oO bal bal bal bal bal bel bal C C E C C C C Ww DI Ww DI DI DI UI W OO e OD O st D oO F DO o o o o o o gt gt gt gt gt gt gt gt o 0 ms A AA E el 7 ll cl 22222228 asa aaa Reserved A AAA E yyy 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bi
32. 31 Bit s Description 0 2 Reserved 3 15 Transfer Length Contains the number of bytes remaining when the transfer was completed or aborted 16 19 Reserved Invalid PCI Address 20 1 DMAO_XPARXx did not match any PCI extents PCI Bus Error 21 1 Error detected during PCI bus transaction Address Error 22 1 Invalid memory address detected ECC Error 23 1 Double bit ECC error detected in memory Transfer Complete 0 Transfer is not complete 24 1 Transfer complete in Normal DMA mode of operation For the Extended Mode and the Chained mode the end of the DMA transfer is indicated only by the activation of the IT2 interrupt signal and DMAO_GSCRx 4 interrupt status bit Transfer Status 25 0 No DMA transfer in progress 1 DMA transfer operation is underway 9 50 CPC710 User s Manual DMAO_XSSRx DMA Transfer Status Register Bit s Description Transfer Halted oe 1 DMA transfer operation in progress was halted due to start of second DMA transfer operation Unaligned ECOWX ECIWX Address Error j 1 Address associated with ECOWX ECIWX is not word 32 bit aligned Unaligned Transfer Error 28 d Address alignment error when the XTAR address memory is not doubleword 64 bit aligned with XPAR address PCI Page Crossing Error sd 1 Page 4KB Crossing detected during DMA transfer TLBSYNC Detected 30 0 No TLBSYNC Detected 1 TLBSYNC detected during DMA transfer Transfer Address Increment Alignment Error
33. 7 DS MEM DATADL rr Ee 6 MEM_PCICx_STATUSUS actv_ Busta CAS La EE MADDR Ra el D gt Re E Figure 10 1 Read Page Hit from PowerPC CPU to SDRAM Timing Diagrams 10 1 HEET oe bag 2 L PER Y Mo IA A AA A nm a gt A Ir S A E EE E E E EE ma e AA WEE EE e l t O BEEN NEE D O O Jet NA A We e TE EE E E kal g a BESSE KE EE EE AA A E E E EE N Gier 7 NN ee 2 AI aed AAA eas ates N BER DI de WW Oo DORTE E EE E A AA N WS 4 4 4 WW A A E E els E O E N o 4 4 WW Eo A A EE SE SE N g m MI JI 8 ien fen WO eee A EE PETR ee N W gt E i tH E eons are O CAE N gt TS 7 TT BB Se BB Pep yep cp ye ye feld ggf a o TO Ge 4 b E EE t A EA EG t H E EE a D3 DA prech Di SCH A activ Burst U aaa es tae a Ai D D o Wir EE oo ages MEM_PCICx_STATUSUS
34. 8 2 2 2 o E o 1 Ze DD oe o vo A a o lt lt 9 Zo Se oo ee Reserved yyy ebb tide y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 Reserved Extensions Enable Read Only 4 0 The CPC710 does not perform extended error recovery 64 Bit Mode Enable Read Only 2 0 The CPC710 does not support 64 bit addresses SERR Presentation Read Only 3 0 PCI Bridge always generates Machine Check if G P_SERR driven active Create Interrupt On PHB Detected Error Read Only 4 0 PCI Bridge always generates Machine Check for PHB detected error ISA Contiguous Mode This bit programs how the CPC710 translates the first 8 MB of PCI I O space See Figure 2 4 on page 2 5 for addi 5 tional details 0 ISA space is contiguous 1 ISA space is not contiguous ISA Compatibility Mode Read Only 6 1 The CPC710 contains an external pin for this function P_ISA_MASTER 7 Reserved 8 Reserved 9 31 Reserved 9 92 CPC710 User s Manual PCILx_DLKCTRL Deadlock Avoidance Control Register This register exists on PCI32 and PCI64 It enables the deadlock avoidance circuit in the CPC710 to man age and avoid deadlock situation that could result from concurrent access to from one PCI bus The deadlock avoidance circuit is active when At least one of the bits 0 1 or 16 of the CPCO_ DLKCTRL register is set to 1 and CPCO_PGCHP register bit 24 is set to 0 This inhibits the Retry sig
35. All other supported organizations see SDRAM Subsystem Overview on page 6 6 12 9 2 13 9 2 13 10 2 13 11 2 13 12 2 14 12 2 30 31 Reserved 9 122 CPC710 User s Manual SDRAMO_MEAR Memory Error Address Register This register contains the address associated with the error logged in SDRAMO_MESR Reset Value x 0000 0000 Address x FFOO 1230 Access Type Read Write Address of Memory Error y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Address of Memory Error Register Summary 9 123 SDRAMO_MESR Memory Error Status Register This register provides error status information on memory errors In order to log additional errors software must clear the register by writing zeros throughout Reset Value Address Access Type x 0000 0000 x FFOO 1220 Read Write Single or Double Bit Error Syndrome 9 124 wn 2 Ko 5 Lu oD gt Ponsa 2 O L 0 e 5 gt E DS a S 2 o ER bei a SS US 3 3 2 Aa g Reserved de ae As E y Y y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Double Bit Error Flag 0 O No Error 1 Double Bit ECC error occurred Single Bit Error Flag 1 0 No Error 1 Single bit ECC error occurred Address Error Flag 2 0 No Error 1 Address error occurred Overlapped Memory Extents 3
36. BAR_PCI64 FF40 0000 The register space for the PCI32 or PCI64 bridge can then be accessed by the CPU with the PCI corresponding base value loaded in the CPCO_PCIBAR PCI Base Address Register at address FF20 0018 The differentiation between the PCI64 or PCI32 is made by enabling the corresponding bit in the Connectivity Configuration Register CPCO_PCICNFR 30 31 at address FFOO 000C Table 9 3 Specific PCI Host Bridge Registers Real Address Name Use Page Note or PCILx_PSEA PCI Slave Error Address 9 106 1 pa Era a PCILx_PCIDG PCI Diagnostic Register 9 99 ea PCILx_INTACK Interrupt Acknowledge Cycle 9 96 1 ee od PCILx_PIBAR PCI Base Address for UC 9 100 GE id PCILx_PMBAR PCI Base Address for Memory 9 102 OL TEEN PCILx_CRR Component Reset Register 9 90 De CPCO_PR Personalization Register 9 104 See CPCO_ACR Arbiter Control Register 9 83 RE EN t PCILx_MSIZE PCI Memory Address Space Size 9 98 SE PCILx_IOSIZE PCI I O Address Space Size 9 97 an Eni PCILx_SMBAR Se Base Address for CPU to PCI Memory 9 113 EEC y PCILx_SIBAR System Base Address for CPU to PCI I O access 9 112 GE GC t PCILx_CTLRW Configuration Register R W 9 92 EE Rosona a od PCILx_CFGADDR PCI Configuration Address Register 9 88 2 GE PCILx_CFGDATA PCI Configuration Data Register 9 89 2 1 Read Only Register write is ignored 2 Little Endian registers 3 Only for PCI32 4 Only for PCI64 CPC710 User s Manual Table 9 3
37. Bit s Description 3 Special Cycle Enable Read Only Always returns 0 Device will not respond to Special Cycle commands Bus Master Enable 2 0 PCI Bridge master capability is disabled 1 PCI Bridge performs as a PCI master for accesses to its address spaces Enable Memory Space Slave 1 0 PCI Bridge will not respond to memory accesses on the PCI bus 1 PCI Bridge will respond to memory accesses on the PCI bus Enable I O Space Slave 0 0 PCI Bridge will not respond to lO accesses on the PCI bus 1 PCI Bridge will respond to IO accesses on the PCI bus except for PREP mode see note below Note I O cycles for Slave as defined in bit O are not decoded by the CPC710 when the address mapping is in PREP mode See PREP mode definition 9 64 CPC710 User s Manual PCICx_DEVID Device ID This register identifies a particular device Reset Value PCI32 x0105 PCI64 x 00FC Address x 02 Access Type Read Only PCICx_DEVID D A 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Bit s Description Device Identification Number 15 0 Pcig2 Value x 0105 x 05 for address 02 and x 01 for address 03 PCI64 Value x 00FC x FC for address 02 and x 00 for address 03 Register Summary 9 65 PCICx_DISCNT Disconnect Register Reset Value x00 Address ECK Access Type Read Write Disconnect Counter Y A 76543210 Bit s Description The CPC710 use
38. Memory PCILx_MSIZE e PCILx_PMBAR 4GB Figure 2 6 Address Translation Disabled in PREP Mode Note Translation can be disabled for CPU to PCI transfers if the values stored in the PCILx_PMBAR and PCILx_SMBAR registers are the same Addressing Model 2 3 2 Flexible PCI Host Bridge FPHB Mode In FPHB Mode External Masters on the 32 bit and 64 bit PCI buses address system memory using the address translation model shown in the following figure This model uses several programmable registers in Specific PCI Host Bridge Registers on page 9 8 Note Each PCI bridge contains a set of programmable registers The CPC710 monitors addresses on the PCI bus to determine whether a PCI address falls within the range specified by the following PCIC1_PSBAR PCILO_PSBAR PCILx_PSSIZE registers e PCIC1_PSBAR on page 9 58 e PCILO_PSBAR on page 9 80 e PCILx_PPSIZE on page 9 103 If an address falls within this range the PCI interface logic passes the address to the 60x bridge logic for execution using the translation specified by PCILx_BARPS on page 9 85 The memory space size can be extended up to 4 GBytes by setting bit 27 of the CPCO_PGCHP register See page 9 27 In this case the addressing mechanism is the same as the one used for address from 0 to 2GBytes but it uses registers PCIC1_ PPBAR PCILO_PPBAR and PCIL_PPSIZE for PCI address definition and uses register PCIL_BARPP for bas
39. Memory Controller 6 13 Table 6 11 SDRAM Control Register Programming Bit s Description Shifted Refresh Cycles In normal operation the refresh of all the populated DIMMs is performed at the same time If the 8 DIMMs are fully populated this could produce a high current load all SDCS_ activated at the same time Setting bit 29 to 1 enables 29 the controller to perform successive Refresh only 2 SDCS_ activated at the same time in return the refresh cycle last longer depending on the number of populated DIMMs 0 All banks are refreshed in the same cycle 1 Banks are refreshed one after one Disable Page Mode 30 0 Memory controller will perform fast page accesses for back to back operations if appropriate 1 Memory controller will perform fast page access only within a burst operation It will NOT perform fast page accesses for back to back bursts even if they occur to the same RAS page Disable Queue Same Page Override 31 0 Memory queue ordering can be overridden if an operation is to the same page 1 Memory queue always processed in order received 6 9 2 SDRAMO_MCERx Registers The Memory Configuration Extent Registers SDRAMO_MCERO 5 program the start address and size of each bank The following table shows the relationship between the DIMMs and the SDRAMO_MCERx registers Table 6 12 SDRAMO_MCERx to Program Functions of DIMMs Bank Definition DIMMs equipped Corresponding SDRAMO_M
40. O Z eserve ZARTAN y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 1 Reserved SERR Detected 2 0 No Error 1 PCI Bridge detected G P_SERR active during master operation No Devsel 3 0 No Error 1 PCI Bridge did not receive G P_DEVSEL during master operation PCI Bus Timeout 4 O No Error 1 PCI Bridge detected bus time out no G P_TRDY detected Retry Count Expired 5 O No Error 1 PCI Bridge detected bus time out too many retry s see PCICx_RETRY on page 9 73 6 31 Reserved Register Summary 9 101 PCILx_PMBAR PCI Base Address for Memory Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 7810 Access Type Read Write PCI Base Address Reserved 4 vy d 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI Base Address Contains the upper bits of the PCI base address that PCI Memory is mapped to Note Address must be aligned on boundary equal to size specified in PCI Memory Size register 12 31 Reserved 9 102 CPC710 User s Manual This is the same definition for 32 bit PCI and 64 bit PCI PCILx_PPSIZE PCI to System Extended Address Space This register can be used to extend the memory space size up to 4G but must be left to 0 if extended memory is not required This functionality is available if bit 27 of CPCO_PGCHP register is set to 1 page 9 2
41. Only CPC710 User s Manual This is the same definition for 32 bit PCI and 64 bit PCI Reset Value Address Access Type Reserved x 0000 0000 CPCO_PCIBAR x 000F 8100 Read Write Reserved PCILx_PSSIZE PCI to System Address Space Size System Address Space Size 4 Y vy 4 0 1 2 3 4 5 6 s lt Enable Memory or I O Space 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 x 00 Access disabled Bit s Description 0 6 Reserved Enable Memory Or lO Space 7 0 Memory Space 1 lO Space 8 23 Reserved System Address Space Size SEET 16 MB x FE 32 MB x FC 64 MB x F8 128 MB 24 31 FO 256 MB x EQ 512 MB x C0 1 GB x 80 2 GB Register Summary 9 109 PCILx_PSWCR PCI Slave Write Control Register This register exists on PCI32 and PCI64 and it controls the PCI to Memory Long burst Write access This register permits to improve performance for an I O device master on the PCI when it is writing to the system memory through the CPC710 The normal mode of burst transfer from a PCI Master to the Memory is 32 Bytes The setting of bit O permit to have Long Burst of up to 4K Bytes with no Disconnect RETRY during the Burst Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8270 Access Type Read Write lt Errata Correction for Address Compare Mode nd Addres
42. PCI bus Enabled by Set PCI error bit in CPCO_SESR cont d bit 6 in Set error address in CPCO_SEAR register PCI If CPCO_PGCHP 26 0 1 oe Loads Signal Machine Check with SYS_TEA register Qi ah SVE MCPOT Detected PERR on store H F RE d Check with SYS_MCP0 1 Signal Machine Check with SYS_MCP0 1 Terminate CPU transaction normally Disabled by bit 6 in Set data parity error bit 15 in PCI Status register PCI Proceed normally with PCI transaction PCICx_CM Proceed normally with CPU transaction D register Notes 1 A dummy 0 is returned for read operation For write data is ignored 4 18 CPC710 User s Manual Table 4 6 CPU Initiated Transactions Page 5 of 5 Operation Error Mode Action Note Access to PCI bus cont d PCI Bus timeout P G_TRDY count expired Enabled Master abort the PCI transaction Set master aborted bit 13 PCI Status register Set PCI bus time out error in PCILx_PLSSR register Set PCI error bit in CPCO_SESR Set error address in CPCO_SEAR register If CPCO_PGCHP 26 0 Loads Signal Machine Check with SYS_TEA Stores Signal Machine Check with SYS_MCP0 1 If CPCO_PGCHP 26 1 Signal Machine Check with SYS_MCP0 1 Terminate CPU transaction normally Retry count expired Enabled Stop retrying PCI transfer Set retry count expired bit in PCILx_PLSSR register Set PCI error bit is CPCO_SESR Set error address in CPCO_SEAR register If CPCO_PGCHP 26 0 Loads S
43. PCICx_CMD 9 63 PCICx_HDTYPE 9 67 PCICx_INTLN 9 68 PCICx_INTPN 9 69 PCICx_LATTIM 9 70 PCICx_MAXLTNCY 9 71 PCICx_MINGNT 9 72 PCICx_REVID 9 74 PCICx_STATUS 9 75 PCICx_SUBNO 9 77 PCICx_VENDID 9 78 PCILO_PPBAR 9 79 PCILO_PSBAR 9 80 PCIL1_ITADDRESET 9 82 PCILx_BARPS 9 85 PCILx_BIODLK 9 86 PCILx_CFGADDR 9 88 PCILx_CFGDATA 9 89 PCILx_CRR 9 90 PCILx_CRTLW 9 92 PCILx_DLKCTRL 9 93 PCILx_DLKDEV 9 95 PCILx_INTACK 9 96 PCILx_IOSIZE 9 97 PCILx_MSIZE 9 98 PCILx_PCIDG 9 99 PCILx_PIBAR 9 100 PCILx_PLSSR 9 101 PCILx_PMBAR 9 102 PCILx_PPSIZE 9 103 PCILx_PR 9 104 PCILx_PSEA 9 106 PCILx_PSRCR 9 107 PCILx_PSSIZE 9 109 PCILx_PSWCR_ 9 110 PCILx_SIBAR 9 112 PCILx_SMBAR 9 113 PCILx_TIODLK 9 114 PCILx_TPMDLK 9 115 R registers CPCO_ABCNTL 9 10 CPCO_ATAS 9 13 CPCO_AVDG 9 15 CPCO_ERRC 9 17 CPCO_GPDIR 9 19 CPCO_GPIN 9 20 CPCO_GPOUT 9 21 CPCO_MPSR 9 22 CPCO_PCIBAR 9 23 CPCO_PCICNFR 9 24 CPCO_PCIENB 9 25 CPCO_PGCHP 9 26 CPCO_PIDR 9 29 CPCO_RGBANO 9 30 CPCO_RGBAN1 9 31 CPCO_RSTR 9 32 CPCO_RTBR 9 33 CPCO_SEAR 9 34 CPCO_SESR 9 35 CPCO_SIOCO 9 38 CPCO_SIOC1 9 40 CPCO_SPOR 9 41 CPCO_SRST 9 42 DMAO_GSCRx 9 45 DMAO_XCLRx 9 47 DMAO_XPARx 9 48 DMAO_XSCRx 9 49 DMAO_XSSRx 9 50 Index X 1 DMAO_XTARx 9 52 DMAO_XWARx 9 53 PCICO_DLKRETRY 9 54 PCIC1_INTRESET 9 55 PCIC1_ITADDSET 9 56 PCIC1_PPBAR 9 57 PCIC1_PSBAR 9 58 PCICx_BIST 9 59 PCICx_BUSNO 9 60 PCICx_CACHELS 9 61 PCICx_CLS 9 62 PCICx_CMD 9 63 PCICx_HDTYPE 9 67 PCICx_INTLN 9 68 PCI
44. Signal Summary asnicar 11 1 MOG A TA T X 1 REVISION oTe ME E O DA R 1 Contents vii viii CPC710 User s Manual Figures Figure 1 1 Figure 1 2 Figure 1 3 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 3 1 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 5 1 Figure 5 2 Figure 5 3 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 7 1 Figure 7 2 Figure 7 3 Figure 9 1 Figure 9 2 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 10 7 Figure 10 8 Figure 10 9 System Block Diagram eege id 1 3 Component Block Diagram iia tt 1 4 Internal Buffering and Data FIOW 0 0 eee ceeeeeeeeeeeeeeeeeaeeeeaeeseaeeceaaeeeeeeseaeeseaeeseaeeeneeseeeeeesaeeeeaes 1 5 Memory Map A i ts RE 2 1 CPU to PCI Addressing Model PREP and FPHB Modes sssssesssenessnseesnnnessrnnnsnnnssrnnesrrnnssnnn 2 2 CPU to PCI Addressing Model CHRP Mode 2 3 Noncontiguous I O Address Mode Enabled AAA 25 Address Translation Enabled in PREP Mode AA 2 7 Address Translation Disabled in PREP Mode A 2 7 PCI to System Addressing Model FPHB Mode AA 2 8 CHRP Address Map citadino ri a dE 2 9 Connection of Boot ROM and System I O Registers to Device ooooooconocccoccccnocncncanonancnnnncnancnonos 3 3 CPG710 Endian Logie iii at 4 2 Processor Data Bus Byte Swap for Little Endian oo ee cece eeeeeeseeeeeeeee
45. Specific PCI Host Bridge Registers Real Address Name Use Page Note CPCO_PCIBAR e S x000F 8100 PCILx_PSSIZE PCI to System address space Size 9 109 CPCO_PCIBAR R x000F 8110 PCILx_PPSIZE PCI to System extended address space Size 9 103 CPCO_PCIBAR A x000F 8120 PCILx_BARPS System Base Address for PCI to System access 9 85 CPCO_PCIBAR System Base Address for PCI to System extended x 000F 8130 PRIBCBABES access 9 84 PCI Base Address for PCI to System access SE PCICO_PSBAR PCI32 only for PCI64 see Standard PCI Config 9 80 3 uration Space PCI Base Address for PCI to System extended CPCO_PCIBAR access x 000F 8150 ELISA PCI32 only for PCI64 see Standard PCI Config 972 3 uration Space CPCO_PCIBAR Bottom of Peripheral Memory space with potential E x 000F 8200 PEILX BPMDEK deadlock Sei CPCO_PCIBAR Top of Peripheral Memory space with potential 7 X 000F 8210 Pol EME deadlock GA CPCO_PCIBAR Bottom of Peripheral I O space with potential dead x 000F 8220 PCILx_BIODLK lock 9 86 Are arre PCILx_TIODLK Top of Peripheral I O space with potential deadlock 9 114 CPCO_PCIBAR A E x000F 8240 PCILx_DLKCTRL Deadlock Avoidance Control 9 93 Ee PCILx_DLKDEV Deadlock Device 9 95 CPCO_PCIBAR i x000F 8260 PCILx_PSRCR PCI Slave Read Control Register 9 107 REN PCILx_PSWCR PCI Slave Write Control Register 9 110 CPCO_PCIBAR F i x 000F 8300 PCIL1_ITADDRESET PCI64 Reset Inter
46. To Frame Active Time out Disable 0 If the CPC710 grants the PCI bus to a PCI master and other REQs are outstanding the PCI master must acti vate the FRAME signal within 20 cycles or the CPC710 will deactivate its GNT signal 18 1 Once CPC710 has granted the bus to a PCI device it waits until it sees FRAME active from that device before deactivating its grant signal Note The 20 cycle count is not guaranteed The timer runs continuously and therefore the CPC710 could remove the grant at any time Issue Flush Snoops Instead Of Kill Snoops 19 0 PCI bridge requests the 60x logic to perform Kill snoops on 60x bus for PCI to memory access as normal 1 PCI bridge substitutes Flush snoops instead of Kill snoops to the 60x logic This is to avoid a 604 coherency problem that exists for Kill snoop operations 20 31 Reserved Register Summary 9 105 PCILx PSEA PCI Slave Error Address Register This register is used to log the PCI address when an error occurs during Device PCI slave transfer See PCI Master Error Handling on page 7 7 for additional details This register is reset to zero after a POWERGOOD or when one of the bit RSTR 2 of CPCO_RSTR on page 9 32 for PCI32 or bit RSTR 3 for PCI 64 is forced to zero or from a software reset as described in CPCO_SPOR on page 9 41 Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 6110 Access Type Read Only PCI To Memory Error Address D y 012 3 4 5 6 7 8 9 10 11
47. address falls within one of these ranges the 60x interface logic passes the address and command to the appropriate PCI bridge logic for it to execute with the translation specified by the PCILx_PMBAR or PCILx_PIBAR registers e PCILx_PIBAR on page 9 100 e PCILx_PMBAR on page 9 102 2 2 3 Peripheral I O Address Translation The first 8MB of Peripheral I O space requires additional translation To prevent 32 byte granularity accesses to ISA addresses the CPC710 supports a noncontiguous I O address mode in which the first 64KB of PCI bus I O space is divided into 32byte segments spaced at 4K intervals within system memory This mode is selected by bit 5 of PCILx_CTRLW on page 9 92 2 4 CPC710 User s Manual Peripheral UO Space 8MB PCILx_SIBAR 8MB gt Area Wrapped To First 32 Bytes 32 Bytes PCILx_IOSIZE lt PCILx_PIBAR 8 MB iN Au PCILx_IOSIZE lt lt LA NY PCILx_SIBAR 12 KB 32 Bytes Area Wrapped To First 32 Bytes Not addressable 32 Bytes PCILx_SIBAR 8 KB gt Area Wrapped To First 32 Bytes PCILx_SIBAR 4 KB gt 32 Bytes Area Wrapped To First 32 Bytes PCILx_PIBAR 64 KB Viz 32 Bytes Y PCILx_SIBAR gt Se Byes AY 32 Bytes 32 Bytes 32 Bytes 32 Bytes lt PCILx_PIBAR Figure 2 4 Noncontiguous I O Address M
48. example the CKE is sampled ON at the rising edge of the CLK signal such that at the next rising edge of the CLK the SDRAM memory is controlled At time T1 and T3 the RAS CAS WE CS combination is decoded to control the memory eene annn CKE ME L SDRAS SDCAS WE l o TO Ti T2 T3 Figure 6 6 Use of the CKE signal for SDRAM Control 6 8 Mapping of System address to SDRAM Memory address with the CPC710 The following table gives the correspondence between RAS CAS BS address bits and PowerPC bus address bits for the supported SDRAMs by the CPC710 Memory Controller 6 9 Table 6 9 System Address Mapping Msb Address on the 60X bus yo y y ola alakale kz ela d ra 29 3031 Organization olif2 3i4aislelz7isio 11123111 1 1 4990 4 2223242526 27 RowcolBank MCERx 012345678 26 29 BSO R10 RO C7 co 11 84 1010 C8 BSO R10 Ro C7 CO 11 91 b 0010 BS1 BSO R10 RO C7 CO 11 8 2 b 0001 C9 C8 Bso R10 Ro C7 co THON DOOTI GIEL Ro C7 co 12 84 Een C8 R11 BSO R10 RO C7 co 12 971 D1100 BS1 R17 BS0 Rt0 RO C7 co 12 8 2 b 0100 Ri2 R11 BSO R10 RO C7 Col o 38M DOTTO BS1 cs R11 BSO R10 RO C7 colo 12 972 0 default BS1 R12 R11 BSO R10 RO C7 col d 13 872 boom Ri2 C8 A11 BSO R10 RO C7 Col aen b 1000 Ca B51 C8 lem enen RO C7 coll y 12 1072 DOTO
49. fine tuning of the Flash and the System bus frequency the Timing parameters can be modified in Register CPCO_SIOCO O FFOO 1020 The Extended Flash parameters are programmable in the Register CPCO_SIOC1 FFOO 1090 Defines a Base address of 8 bits aligned to the size of the Flash Permits to map the Flash anywhere in the 4 GB processor address space The address on the PCI bus is defined from 0 Lsb to 28 Msb Defines size 16 32 64 128 or 256 MBytes Defines size of the bus 8 16 or 32 bits PCI AD 15 8 forthe 8 bit PCI AD 23 8 forthe 16 bit PCI AD 31 0 forthe 32 bit 3 3 3 Byte ordering in the Boot amp Extended Flash for 8 bit bus size The bytes in the boot Flash are ordered as following Add Offset for the Flash address Address b 000 Byte 00 MSB Address b 001 Byte 11 Address b 010 Byte 22 Address b 011 Byte 33 Address b 100 Byte 44 Address b 101 Byte 55 Address b 110 Byte 66 Address b 111 Byte 77 LSB The result on the PowerPC bus is SYS_DATA 0 63 00 11 22 33 44 55 66 77 3 2 CPC710 User s Manual CPC710 Dir SIO_D 15 8 XCVR RD see note F_AD 19 Msb PCI32 AT CE BUS FT DATA P_ADL 31 0 Y gt i gt ADD B side Aside Bee PAS ye c SEN LVT245 f gt OE XA
50. is Little Endian Table 7 2 PCI Bus Bridge Configuration Address Map 7 2 System Standard Configuration Registers Area Real Address Name Use Page x FF20 0000 Reserved System Standard x FF20 0004 Reserved eer x FF20 0018 CPCO_PCIBAR Base Address Reg for Bridge Registers 9 23 x FF20 001C to x OFFF Reserved Device Specific x FF20 1000 CPCO_PCIENB PCI BAR Enable Register 9 25 Configuration Space x FF20 1004 to x1FFF Reserved 1 Read Only Register write is ignored System Standard Configuration Registers can only be accessed with 60x bus configuration cycles directed to a specific PCI bridge Both of the CPC710 PCI bridges must be configured before any PCI configuration cycles can be issued The registers provide a mechanism for firmware to assign a 1MB PCI Bridges 7 1 address space in the system memory map for the location of the PCI bridge facilities PCPO_PCIBAR register For detailed descriptions of these registers refer to the following e CPCO_PCIBAR on page 9 23 e CPCO_ABCNTL on page 9 10 7 3 System PHB Registers The PCI bridge logic follows the PowerPC PCI Host Bridge PHB Architecture including the enhanced error detection and error reporting features The logic deviates from PHB Architecture only in its ability to recover from PCI errors 7 4 PCI Bus Commands The following table describes the subset of PCI bus commands su
51. is corrected Address Crossing 4K Boundary 17 0 4K address crossing detection on PCI address Anticipated Snoop cycle not used 1 4K address crossing detection on Anticipated Snooping Address save one cycle DD2 0 ERRATA 7 correction for address comparison Mode must be left to 0 if bit 2 is not set to 1 18 0 ERRATUM is not corrected 1 ERRATUM is corrected 19 Reserved Must be left to 0 20 31 Reserved Read Only Register Summary 9 111 PCILx_SIBAR System Base Address for PCI I O Reset Value x 8000 0000 Address CPCO_PCIBAR x 000F 7FCO Access Type Read Write PCI Base Address Reserved 4 vy 4 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description System Base Address 0 11 This register contains the upper bits of the SYSTEM address that PCI I O is mapped to Note Address must be aligned on boundary equal to size specified in PCI I O Size register 12 31 Reserved Note Address is decoded only if the Master Enable bit in the PCI Command Register is on 9 112 CPC710 User s Manual PCILx_SMBAR System Base Address for PCI Memory Reset Value x A000 0000 Address CPCO_PCIBAR x 000F 7F80 Access Type Read Write System Base Address Reserved A Y y D 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description System Base Address This register contains the upper bits of the SY
52. is never used as address during CAS phase 6 9 Memory Controller Registers 6 9 1 SDRAMO_MCCR Register The Memory Controller Control Register contains all the parameters to fit the Memory Controller to the Synchronous DRAM components used The following table describes how to program this register described in SDRAMO_MCCR on page 9 116 Table 6 11 SDRAM Control Register Programming Bit s Description Global System Memory Address Space Enable 0 The CPC710 will not respond to addresses specified in Memory Configuration Extent Register o SDRAMO_MCERx 1 System memory address space enabled Memory Controller 6 11 Table 6 11 SDRAM Control Register Programming Bit s Description Diagnostic Mode This bit is used to control presentation of double bit ECC errors to the system This bit is primarily intended for use in memory testing at power on time Software can use this bit when testing memory and or ECC logic in order to avoid 1 the hardware generating a machine check for double bit ECC errors The error however is still logged into the SDRAMO_MEAR O Normal Mode Multi bit ECC error will generate Machine Check 1 Diagnostic Mode Multi bit ECC does NOT generate Machine Check logged in SDRAMO_MEAR amp SDRAMO_MESR SDRAM Initialization Status read only 2 0 SDRAM initialization is not completed 1 SDRAM initialization is completed ECC Mode This field provides software with a mean
53. its queue to the controller DMA Controller 8 5 8 6 CPC710 User s Manual Chapter 9 Register Summary The registers for the CPC710 are specified in three regions Except for the Standard PCI Configuration Space which uses indirect addressing all the registers can be defined in the upper 16 MB of the 4 GB address range Each of these registers is described in Alphabetical List of Registers on page 9 9 9 1 System Register Space The upper 16 MB of the 4 GB address range OxFFOO 0000 to OxFFFF FFFF is reserved for system support functions Table 9 1 on page 9 3 describes the System Space Registers supported These registers are defined as Big Endian unless otherwise noted If the processor is operating in Little Endian mode software must issue Load Store reverse instructions to access these registers The CPC710 responds to all addresses listed in Table 9 1 on page 9 3 with a minimum granularity of 4K blocks Accesses to these registers must be single word accesses on word boundaries or unpredictable results may occur Shaded address ranges indicate areas where CPC710 will respond with TEA addressing error is detected and logged in the System Error Status Register CPCO_SESR x FFO00 1060 bit 15 or bit 22 Register Summary 9 1 x FFFF EFFE x FFEO 0000 CPCO_PCIBAR x 000F 9810 CPCO_PCIBAR x000F 6110 CPCO_PCIBAR x 000F 6110 OU x FF20 1000 x FFOO 0000 x 0000 0000
54. master on the 60x has started an address tenure and the address bus and transfer attribute signals are valid For address tenures that require a data transfer this signal also indicates a request for the data bus 1 0 SYS_ADDRO0O0 31 SYS_ADDRP0 3 SYS_TT0 4 Address Bus Output Represents the physical address of a cache operation that should be snooped by devices on the 60x bus A 0 is the most significant address bit Input Represents the physical address for the current transaction Address Parity Output Represents one bit of odd parity for each of the four bytes of the address bus Odd parity means that an odd number of bits including the parity bit are driven high The signal assignments correspond to the following APO AO 7 AP1 A8 15 AP2 A16 23 AP3 A24 31 Input Represents one bit of odd parity for each of the four bytes of the address bus A checkstop is generated if bad parity is detected and bit 8 is 1 in the error control register Transfer Type Output Indicates the type of transfer in progress The values are programmable according to the PowerPC type and stored in the CPCO_ATAS register Input Indicates the type of transfer in progress 1 0 1 0 1 0 SYS_TSIZO 2 SYS_TBST SYS_GBL SYS_AACK Transfer Size Output signals and the TBST signal Indicate the data transfer size of the operation The CPC710 sets these signals to a value stored in the CPCO_ATAS register for the
55. not written back to memory but forwarded to the requesting logic 4 When Chip Programmability Register CPCO_PGCHP bit 17 1 a Machine Check is performed to signal the processor that it could rewrite correct data to memory Software must write zeros to the SDRAMO_MESR to clear this error If more than one single bit ECC error occurs before the SDRAMO_MESR clears only the first error is recorded When a double bit ECC error or an address error occurs the software overwrites the SDRAMO_MESR and SDRAMO_MEAR 6 10 2 Single Bit ECC Error Special Case For non burst write transactions that do not span an entire aligned double word the Memory Controller performs a read modify write sequence to memory If the read portion of the sequence results in a single bit ECC error the error is not logged into the SDRAMO_MESR and SDRAMO_MEAR for both the diagnostic and normal modes However the memory controller automatically writes corrected data to memory 6 10 3 Invalid Address Error An Invalid Address error is detected by the Memory Controller when an address does not match one of the eight configuration extents The hardware procedure for this error is 1 If no hard errors are in the SDRAMO_MESR register set the invalid address error bit 2 If no hard errors are in the SDRAMO_MEAR register store the address 3 In diagnostic mode the Memory Controller responds with dummy data and indicates an Invalid Address error to the requesting logic T
56. operations it initiates Input signals and the TBST signal For normal memory accesses indicate the data transfer size of the operation For the DMA instructions eciwx and ecowx they indicate the 4 bit Resource ID PCICx_REVID of the DMA operation TBST TSIZO TSIZ2 Transfer Burst Output signal and the TSIZ signals Indicate the data transfer size of the operation The CPC710 sets this signal according to the bit in the CPCO_ATAS register for operations it initiates Input signal For normal memory accesses indicates a burst transfer is in progress For DMA instructions eciwx and ecowx the input signal and the TSIZ signals indicate the 4 bit Resource ID PCICx_REVID of the DMA operation TBST TSIZO TSIZ2 Global Always asserted by the CPC710 for transactions that it initiates to indicate that all devices on the 60x bus must snoop the transaction Since the CPC710 asserts this signal only when it is PowerPC bus address master no contention is possible with PowerPC 750 or 7400 input output GBL signal connected to SYS_GBL Address Acknowledge Indicates the address tenure is complete and the ARTRY sampling window ends on the following bus cycle Address bus and transfer attribute signals must go to tri state on the next bus cycle 1 0 1 0 O D Signal Summary 11 1 Signal Name SYS_ARTRY Description Address Retry Output indicates that the CPC710 detects a condition that requires a
57. programmed in 3 different modes e PREP PowerPC REference Platform based on PREP specification e CHRP Common Hardware Reference Platform based on CHRP specification e FPHB Flexible PCI Host Bridge Mode The FPHB Mode provides an address map that is highly programmable and allows for configuration of select internal PCI configuration registers such as PCIC1_INRESET PCIC1_ITADDSET PCIC1_PSBAR from external PCI bus agents on the PCI32 and PCI64 interfaces The type of address map can be selected by programming bits 0 3 of CPCO_PGCHP on page 9 26 The following restrictions must be observed when programming the CPC710 e The upper 16 MB is reserved for ROM system configuration DMA controller etc See System Register Space on page 9 1 for the definition of this address space Only PCI Memory spaces are allowed to overlap this area However they are not forwarded to the PCI bus Atleast 1MB of system memory must be available at address 0 Minimum granularity of DIMMs is 16MB e System memory cannot be located above 2GB Access in the upper 2GB is not checked by the CPC710 and result is unpredictable e Avoid overlapping system memory extents with PCI extents Hang conditions and unpredictable results can occur if a processor accesses an address contained in two different extents A 16 MB range not forwarded to PCI bus 4GB A FFFF FFFF 16MB A Area to map PCI Memory Spaces Area to map PCI I O spaces 2
58. that dummy zeros are returned for loads and write data is ignored PCI Bridges 7 9 7 10 CPC710 User s Manual Chapter 8 DMA Controller 8 1 Introduction The data transfers between the system memory and the PCI buses can be performed either by the DMA controller or by a PCI master on one of the PCI buses which can access in Read or Write the System memory See the PCI section The DMA is initiated either by a PowerPC specific instruction or by writing to the DMAO_XTARx register The DMA is defined with one channel and with several type of mode of operations To signal the end of the DMA operation the External interrupt IT2 is raised 8 2 Mode of operation of the DMA A complete DMA transfer can be done in the following modes that can be programmed in the DMA Global Control Register DMAO_GSCRx e Elementary e Extended Mode e Chained e Skip of Cache line The DMA controller runs with an elementary block of up to 4 KB of data to transfer In the Extended Mode an automatic address increment is performed at the end of each elementary DMA transfers Up to 65 000 iterations or loops of elementary DMA s can be programmed with address increments to transfer up to 256 MB of data in a single DMA The end of transfer DMA interrupt IT2 is raised only after completion of the multiple elementary DMAs loops The chained DMA permits with one single command to have several DMA with different lengths different starting and ta
59. the DMA is initiated by a write to the DMAO_XTAR register set these bits to x 0001 During an Extended DMA contains the number of loops remaining 9 46 CPC710 User s Manual DMAO_XCLRx DMA Cache Line Increment Register Reset Value x 0000 0000 Address User x FF1C 0030 Privileged x FF1E 0030 Access Type User Read Write Privileged Read Write DMA Increment Extended DMA Increment y A y y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description DMA Increment 0 15 This field specifies cache line increment associated with each successive cache line transfer 16 31 Extended DMA Increment This field specifies cache line increment between successive extended DMA Register Summary 9 47 DMAO_XPARx DMA Transfer PCI Address Register Reset Value x 0000 0000 Address User x FF1C 0070 Privileged x FF1E 0070 Access Type User 0 3 Read Only 4 31 Read Write Privileged 0 3 Read Write 4 31 Read Only PCI Address y y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 PCI Address CPU Contains the adapter I O address for the DMA transfer operation 9 48 CPC710 User s Manual DMAO_XSCRx DMA Transfer Control Register Reset Value x 0000 0000 Address User x FF1C 0040 Privileged x FF1E 0040 Access Type Read Write User
60. will perform fast page access only within a burst operation It will NOT perform fast page accesses for back to back bursts even if they occur to the same RAS page 31 Disable Queue Same Page Override 0 Memory queue ordering can be overridden if an operation is to the same page To avoid hang conditions leave this bit set to 0 See errata listing for more details 1 Memory queue always processed in order received Register Summary 9 119 SDRAMO_MCERO 5 Memory Configuration Extent Registers 0 5 Each one of the six registers SDRAMO_MCERO to SDRAMO_MCERS5 defines one of up to six banks of memory Bank 0 to 5 supported All registers have the same definition and each defines the size and location for the particular bank of memory Reset Value x 0000 0000 Address SDRAMO_MCERO x FFOO 1300 SDRAMO_MCER1 x FFOO 1310 SDRAMO_MCER2 x FFO00 1320 SDRAMO_MCER3 _ x FFO00 1330 SDRAMO_MCER4 x FFOO 1340 SDRAMO_MCER5 x FFOO 1350 Access Type Read Write lt 2 w N lt o gt O D E oon 9 gt c ra 6 bal Lo lt po E o z D uw 2 XI z 2 o 2 amp Reserved Start Address For Bank Extent Size Code For Bank H o y Y vv yy y Y y voy y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Bank Enable 0 O Bank is not present or register initialization is not complete 1 Bank is
61. word is read from memory a new ECC code is generated and compared in the CPC710 to the one that was stored in memory If the two codes are different an error exists in either the data or the ECC word The difference in these ECC codes is called the Syndrome If the Syndrome is zero there is obviously no error Otherwise there is some type of error The Syndrome can be decoded to determine which bit in the word or in the ECC code is incorrect providing it is a single bit error such that it can be immediately repaired by logical inversion Even multi bit errors can be detected however only single bit errors can be corrected Table 6 14 below shows the Error Correcting Code check bit and Syndrome matrix for single bit errors as implemented with the CPC710 memory bus controller Table 6 14 ECC Check Bit Single Bit Error Syndrome Matrix Byte 0 1 2 Data 00000000 00111111 11112222 22222233 33333333 44444444 44555555 55556666 012345 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 67 So 11111111 001 110 10 1 01 Vide hr g Tres A 1 11 0 111 111 0 Tinh S1 111 00 0 11111111 001 110 10 1 01 Vedas I eset de VU 1 11 0 111 0 Visio S2 000111 111 00 0 11111111 001 0110 10 1 01 Je 9 es Ties wl lios S3 2 1 11 00111 111 00 11111111 001 110 10 1 01 1 01 belge AA 5 re S4 001 wld 00111 0 111 00 0 11111111 001 110 10 1 01 1 01 0 ive
62. 0 Address x3D Access Type Read Only Interrupt Pin b 00000000 A A 7 6 5 4 3 2 10 PCICx_INTPN Specifies which particular interrupt pin INTA INTB INTC or INTD is used to generate interrupts Interrupt Pin 7 0 Since the PCI bridge does not generate any interrupts the CPC710 responds with x 00 to reads from this register and ignores writes Register Summary 9 69 PCICx_LATTIM Latency Timer Reset Value x00 Address x 0D Access Type Read Write Latency Timer Y A 76543210 Bit s Description Provides bus masters with a minimum guaranteed time slice on the PCI bus The value programmed into this register is the minimum number of PCI bus clocks that a master can own the PCI bus starting from the cycle that FRAME is activated This register is set to X 00 at reset Maximum number of PCI bus clocks 128 9 70 CPC710 User s Manual Reset Value Address Access Type Maximum Latency b 00000000 x 00 x3P Read Only D 7 6 5 4 3 2 1 0 Specifies h 7 0 ow often the device needs to gain access to the PCI bus in 0 25 us PCICx_MAXLTNCY Maximum Latency The CPC710 has no specific requirements and therefore always responds with x 00 Register Summary 9 71 PCICx_MINGNT Minimum Grant Reset Value x00 Address X3E Access Type Read Only Minimum Grant b 00000000 Y 4 76543210
63. 0 No Error 1 An access occurred to an address that is mapped in two different memory configuration extents 4 23 Reserved 24 31 Single or Double Bit Error Syndrome Used to determine the failing DIMM CPC710 User s Manual SDRAMO_MWPR Memory Write Protection Register SDRAMO_MWPR is used to protect write access to a selected memory space from the PowerPC CPU or a master on a PCI bus This feature is available with the use of the SDQM signals of the SDRAM The CPC710 cannot write to memory space addresses specified in this register To write to the protected memory space the field MWPR 16 27 must be set to Zero Reset Value x 0000 0000 Address xFFOO 1210 Access Type Read Write Q O bal Q 7 Cc BS o w g o S 5 a SO so e E o 2 E 3 o o 2 2 oe S Memory Write Protected Base Address Reserved Memory Write Protected Space Size GER Y y Y y A LL 0 1 2 3 4 5 6 7 8 9 10 11 12 113 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Memory Write Protected Base Address 0 11 This register contains the upper bits of the Memory base address of the write protected Space Note Address must be aligned on boundary equal to size specified in Memory Size register 12 15 Reserved Memory Write Protected Space Size x FFF 1 MB xF FE 2 MB x FFC 4 MB x FF8 8 MB xF FO 16 MB 16 27 x FEO 32 MB xFCO 64 MB x
64. 0 PCILAL INSET EE 9 81 PGIL1ITADDRESE Trono ea eaen E A ave cens cateacs Ae REANA pe 9 82 PEI AGRA 9 83 PGILEXS BAR PP A o DAS ea ead sae aie AE IE A a 9 84 Nee EE 9 85 NEIE e el ET 9 86 PGCIEX BPMDLK ege eto siete ie ee cee en ee ea 9 87 ALERTA EIB WEE 9 88 NEIE EIB ME costra 9 89 PGIEXPO RR 24 A A O ON 9 90 PGILX CSR EE 9 91 Ne en e TUE 9 92 PCILX DEK CTRL end 9 93 NS EI ARTE 9 95 PCIEX_INTACK A Eaa Ea Na aaa ANE 9 96 AAS IOSIZE TEE 9 97 PGIEX lt MSIZE sainia AAA AA 9 98 RI REI E A E A E ea 9 99 PEIEXOPIBAR it AAA ce AAA AA 9 100 POILEPESSR E A E ee hee 9 101 NS ET WE LEE 9 102 PCI POSI ZE TE 9 103 POIL PAR a 9 104 AAA TEE 9 106 PCILX PSRCOR cosita Aa 9 107 PCIEXPSSIZE EE 9 109 PCILX PSWEGOR iii AAA 9 110 Ne SIBA oe ada oe edo 9 112 NEI OS MBA R EH 9 113 RI TIODER coc dt ira 9 114 vi CPC710 User s Manual PCIEXATPMDERK ageseent atte heidi adiede ais dette aden aad age eee re 9 115 Memory Controller RegistersS ooooconocconoconnccononncnoncnnnncnonncnnnnnnc nn nen conc nene rre nene nene 9 116 SDRAMO MOGR rooenis aei A A sve ovarian 9 116 BI De 9 120 SDRAMO MEAR s cec cccsht actin ii 9 123 SDRAMO MES R E 9 124 SDRAMO MWPR sico A A aca 9 125 SDRAMO SIORO E 9 127 SDRAMO SIORT aenertia then cee ENEE EE ENEE EES 9 128 Chapter 10 Timing Diagrams oia 10 1 CPU O Memory Tran A NS ii eed a ae ee aise 10 1 GPU Access to the BOOT R OM tab 10 6 PCI64 External Master Accessing SDRAM Memory 10 7 Chapter 11
65. 0 31 Writeback Address Register DMAO_XTARx FF1C 00A0 0 31 R FF1E 00A0 0 31 R Translated Address Register The steps for executing a DMA transfer with software are 1 Initialize DMAO_XSCRx to indicate length and direction of transfer 2 Initialize DMAO_XPARx with the PCI address The PCI logic takes the address in the DMAO_XPARx register and applies the translation as described in CPU to PCI Addressing Model on page 2 2 3 Initialize DMAO_XWARx with the address to which the device writes to indicate status following transfer 4 Clear cache line status in memory at address specified in DMAO_XWAR x 5 Execute the ecowx instruction or eciwx if read only page to start transfer 6 Wait until an End of DMA transfer interrupt IT occurs then read the status on the memory address specified in XWAR Reset bit 4 of the DMAO_GSCRx register to acknowledge the IT Alternatively perform cache polling to the memory address specified in DMAO_XWARx and wait until the cache status flag changes from x 00 to x FF 8 4 1 DMA Transfer Status Cache Line Descriptor for Chained DMA s The following table shows the definition of the 64 bit of status stored in main memory at the address defined by the DMAO_XWARx register Only bits 32 63 of the second double word of the Write Back Status cache line are valid All other bytes in the cache line must be ignored Table 8 2 DMA Transfer Status Cache Line Definition Bit s De
66. 00 l Ses e ec Up to 133 MHz 64 60x System Bus 2 5 Volt D gt Optional Optional Optional 4th CPU 3rd CPU 2nd CPU PC710 133 0 2 4 SS PCI 64 Bus 66 MHz D gt I sl DMA e IIe 72 Memory Controller Ja ja a j PCI Bridges l l Bi System UO Pair 0 gt ie d 1 3 5 a ECC PCI 32 Bus 33 MHz lt gt iy dE 72 ay Ma A xevr fi es SDRAMs up to 4GB poly Flash gt PD Regs The CPC710 is designed to interface with 60x system bus definition It can also directly interface to 1 4 PowerPC 750 7400 processors Figure 1 1 System Block Diagram Overview 1 3 1 4 60x Bus Interface Logic JTAG Controller 60x Address Address Endian ess nese Queueing Arbiter Decodes Translation Configuration nierace ogic Posted Internal CPC710 Interface Clock Logic Store Buffers Memory DMA PCI32 PCI64 CACHE OP INTE SDRAM Memory Controller Q O SDRAM g Command 18 en g Memory Eege E 60 DMA Controller Logic Interface 2 5 PCI32 Control Logic Internal CPC710 Interface o 60x MEMORY PCI32 PCI64 ECC Correction e PCl64 S DMA Data Buffers System UO Control PCI32 Bus Interface PCI64 Bus Interface Q 8 DMA DMA 2 External Registers Ss Ls PCI Bus L PCI Bus Interface 60x 3 Master Slave 60x Master Slave e P Logic 2e E Logic S S L S g a PCl64 5 g POR E r
67. 00000 CPCO_SESR Oxff001060 write 0x00000000 CPCO_SEAR O0xff001070 write 0x00000000 CPCO_PGCHP Oxff 001100 write 0x00000000 Memory Interface registers setup Jk SDRAMO_MESR 0xff001220 write 0x00000000 SDRAMO_MEAR 0xff001230 write 0x00000000 MCERO Oxf 001300 write 0x800080c0 Initialization 5 5 MCER1 0xf 001310 write 0x808080c0 SDRAMO_MCCR 0xff001200 write 0x83b06000 PCI64 and PCI32 Interfaces Configuration mode setup Jk Enable configuration mode for PCI64 CPCO_PCICNER Oxff00000c write 0x80000003 CPU SYNC SYNC OP CPCO_PCIBAR 0xff200018 write 0xf 400000 CPCO_PCIENB 0xff201000 write 0x80000000 Enable configuration mode for PCI32 CPCO_PCICNFR Oxff00000c write 0x80000002 CPU SYNC SYNC OP CPCO_PCIBAR 0xf 200018 write Oxf 500000 CPCO_PCIENB 0xf f201000 write 0x80000000 Disable configuration modes CPCO_PCICNER 0xf 00000c write 0x00000000 CPU SYNC SYNC OP PCI64 Interface registers setup SS PCILx PIBAR 0xff4f7800 write 0x5c000000 PCILx_PMBAR write 0x5a000000 PCILx_PR write 0x00008000 PCILx_ACR write Oxff000000 PCILx MSIZE write Oxfc000000 example with 64 MB PCILx_IOSIZE write Oxff000000 example with 16 MB PCILx_SMBAR write 0xe0000000 PCILx_SIBAR write 0x90000000 PCILx_CSR write 0x00000000 PCILx_PLSSR wri
68. 1 FF001100 Processor type 750 on 9 14 CPC710 User s Manual CPCO_AVDG Diagnostic Register The CPCO_AVDG control register has been introduced for verification of the fixes done on the PCI circuits in an early version of the CPC710 This register is no longer necessary in applications using the CPC710 and thus should be left to its Reset value x 0000 0000 Reset Value x 0000 0000 Address x FFOO 1170 Access Type Read Write E o o o 3 o 3 Q a Q a a 255 Sas ceases o lt n Z 0 O lt n Z v o S 200 8 ZS 2 oo 8 re 28 8a 8 28 8a 8 Sz a ce Sz E O 8 NN N N QA XA Y Y Y st N00Q000o0 KT E 0 DO p 2 Q Reseved 9 SH Q OC Reserved Reserved EE NEE ee ee oe ee E E y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI32 Counter Disable O TRDY IRDY PCICx_DISCNT Counters are not activated The MSB is always at 1 0 the PCICx_DISCNT counter is programmable see CPCO_AVDG on page 9 15 1 TRDY IRDY PCICx_DISCNT Counters are ACTIVATED PCI32 Master Abort 1 O Window of Master Abort is reduced to one cycle avoid parasitic master abort detection 1 Window of Master Abort is not reduced PCI32 Target Abort 2 O The CPC710 detects Target abort The Frame output is taken 1 The CPC710 never detects Target Abort but retry indefinitely accesses PCI32 DEVCNT 3 O Stop the
69. 1 64 PCI Cycles 9 110 CPC710 User s Manual PCILx PSWCR PCI Slave Write Control Register Bit s Description Turbo WRITE mode Only for the PCI64 and available only if bit 0 is set to 1 If selected the CPC710 make two consecutive anticipated snoop cycle and so reduce the number of wait states 4 between data cache line 0 Disable 1 Enable Twin Buffer mode Only for the PCI64 and available only if bit O and 4 are set to 1 If selected the CPC710 use two additional 64 bytes buffers to increase memory bandwidth 5 Note The PCILx_PSWCR 4 5 2b 01setting is not supported 0 Disable 1 Enable 6 Reserved Read Only Fair PCI Write Access to Memory Control When enabled re arbitration for access to system memory will occur after a cache line 32 byte transfer is com pleted Re arbitration will be among the PCI32 PCI64 DMA controller and the 60x bus interface This allows for 7 memory writes to take place during long burst read operations on PCI 0 No PCI disconnect Retry of a Long burst Read in progress 1 PCI Disconnect Retry of a Long burst Read in progress instead of wait on PCI bus when CPC710 s internal buff ers are full 8 11 PCI WRITE Command C BE for Filtering option if enabled with bit 1 J See C BE 3 0 in the PCI section for supported Commands 12 15 Reserved Read Only DD2 0 ERRATA 7 correction for general case must be left to 0 if bit O is not set to 1 16 0 ERRATUM is not corrected 1 ERRATUM
70. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI To Memory Error Address Contains the address present on the PCI bus when an error occurs during a PCI transfer 9 106 CPC710 User s Manual PCILx_PSRCR PCI Slave Read Control Register This register exists on PCI32 and PCI64 and it controls the PCI to Memory Long Burst Read access This register permits to improve performance for an I O device master on the PCI bus when it is reading to the system memory through the CPC710 The normal mode of burst transfer from a PCI Master to the Memory is 32 Bytes The setting of bit O permit to have Long Burst of up to 4K Bytes with no Disconnect RETRY during the Burst Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8260 Access Type Read Write wn me o ke D 5 D gt dD E E a gt Se o Q t 6 8 E YO 4u go ES 533 5 E 2 o o 2 5 D gt Sc a Vc 5 oO cf 68s dp al on LeLggg E 3585238 ek GE E 3 fo o p VOLO OS oO SS OO FO o 5 53 5 o oC Oo D be oo ee ob 5 Dor Ze D E o 5533523 9 O R d 22 lt lt XEB co oa eserve error y dy yy yy y 0 1 2 3 EA 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Long Burst READ Enable 0 0 Maximum burst size of 32 Bytes in this case all following bits must be left to 0 1 Maximum burst size of 4 KBytes No Disconnec
71. 2 bus o a buffers and any CPU access to PCI is being SYS_ARTRYed Memory Request Indicates a PCI device accessing system memory has a potential P_MEMREQ deadlock and requests the CPC710 to flush all posted CPU to PCI buffers and ARTRY all PCI32 bus transfers from the 60x bus P_PAR Parity Bit 1 0 P_GNT0 3 PCI32 B P_GNT4 6 G_GNT5 7 PRE Busanan S PCI32 Bus Requests P_REQ2 is sampled at Reset to select arbitration on the PCI B5 GEARRA 32 bus The arbitration can be made by the CPC710 P_REQ2 1 or by external cir P_REQO 3 ee 3 P REOS6IG REO57 cuit P_REQ2 0 In case of external arbitration the request is send to PCI from Le Sa P_GNT1 and the grant from the external arbiter is received on pin P_REQ1 Extended Flash is available only when the CPC710 is the PCI32 arbiter P_RST PCI32 Bus Reset O P_PERR PCI32 Data Parity Error 1 0 P_SERR PCI32 System Parity Error Reports parity errors on address special cycle data or vO systems P_STOP Stop Asserted by the target to request the master to stop current transaction 1 0 P_TRDY Target Ready Asserted by the target when ready to receive data 1 0 PCI64 Interface PCG_CLK Main clock input for the PCI64 bit bridge maximum 66 MHz l 11 4 CPC710 User s Manual Signal Name Description UO 32 bit Multiplexed Address Data Higher Part In the address phase when G_REQ64 is G ADH31 00 asserted these bits are the upper
72. 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 23 Reserved System Base Address 24 31 Contains the upper bits of the system Base address that Memory is mapped to Register Summary 9 85 PCILx_BIODLK Bottom of Peripheral I O Space with Deadlock Avoidance Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8220 Access Type Read Write Bottom of Peripheral I O Space Reserved y Y y y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Bottom of Peripheral lO Space 0 9 Contains the bottom address for the CPU to PCI IO access with potential deadlock 10 31 Reserved 9 86 CPC710 User s Manual PCILx_BPMDLK Bottom of Peripheral Memory Space with Deadlock Avoidance Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8200 Access Type Read Write Bottom of Peripheral Memory Space Reserved D vy y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Bottom of Peripheral Memory Space 0 9 Contains the bottom address for the CPU to PCI MEMORY access with potential deadlock 10 31 Reserved Register Summary 9 87 PCILx_CFGADDR Configuration Address This Little Endian register along with the PCICx_CFGDATA register provides software with a means to configure the PCI bus The CPC710 implements Configuration Mech
73. 3 Table 6 3 External MUX Controller for Memory Data Signal Name Toggle for Reads Toggle for Writes MUX_CLKEN1B No 1 b MUX_CLKEN2B No 1 b MUX_CLKENA1 Yes MUX_CLKENA2 Yes MUX_OEA No 0 b MUX_OEB No 1 b IR E High for EVEN DH ae MUX_SEL Low for ODD DL Notte Table 6 4 Memory Address Bit Definition for Non Row Column Addressing Bits Adaress Bit Definition 0 1 Interleaving Bit 0 Even DIMMs 0 2 4 or 6 1 Odd DIMMs 1 3 5 or 7 00 Base address of memory Table 6 5 SDRAM Subsystem Signals Signal Name Type Comments BSO SDRAM Bank Select BS1 SDCS 0 11 Chip Select See the following table for connections up to 4 pins for load purposes SDDQM 0 3 Data Mask see bit 14 and 15 of SDRAMO_MCCR Register up to 2 pins for load purposes SDRASIO 1 ROM nog ese Strobe see bit 14 of SDRAMO_MCCR Register up to 2 pins for load purposes SDCASIO 1 Gol umniAddress Strone see bit 14 of SDRAMO_MCCR Register A up to 2 pins for load purposes WE 0 1 wea see bit 14 of SDRAMO_MCCR Register SDCKE 0 9 Clock Enable 10 pins for load purposes Table 6 6 SDRAM DIMM Chip Select Connections Example 6 4 CPC710 User s Manual Signal Name DIMM and DIMM Bank SDCSI0 DIMM 0 Bank A SDCS 1 DIMM 1 Bank A SDCS 2 DIMM 0 Bank B SDCS 3 DIMM 1 Bank B Table 6 6 SDRAM DIMM Chip Select Connections Example
74. 34 E E BEE 9 35 ALA EE 9 38 AAA EE 9 40 E E EE 9 41 CROO SRS TR pea eee Ee ere e a e RT ort Bere CE e Ere ELE MET Ber ere Cec eee eee 9 42 OPEO RE 9 43 DMA E EE 9 45 DMAO_GSCRP DMAO_GSCRU he eeeeceeeceeseeeneeeeeeneeeeeceaeeeaeceneseaeeeaeeeaeeeaeeeaeeeaeeeaeseaeeeaeeeaeeeaeeeaeees 9 45 DMAO XGLRP DMAO lt XGER oca 9 47 DMAO XPARP DMAO XPA RU ee cari dicta tia ti ei loas cl td e tds a ADO 9 48 DMAO XSCRP DMAO XSGRU ees eegen lich atetiedesreatentanetiedbares Sich celebrates een Sich anetsedeareaineeuenia 9 49 DMAO XSSRP DMAO XSSRU ds cio ele alana lel alla ln 9 50 DMAO X TARP DPMAO OCTARUL o iter ed 9 52 DMAO XWARP BA A OR WE 9 53 NS Ee eil tee NEIE aiii aa 9 54 PECO DLE RETR ant Sections cer cele ial ee EE 9 54 PGIGALINTRESET ere Air viel eee lat eee eal he ae eee ee ee he ed eee ae ead ae ee 9 55 Contents v Ee WR BIR 9 56 Nee WEE 9 57 Nee EE 9 58 PCICX BIST specced A ad ea SRR La 9 59 PCIEX BUSN O ET 9 60 PCICX CAGHELS EE 9 61 PICK EE 9 62 PCICX GMD ici a 9 63 PCIEXDEMID WEE 9 65 PEICADISEN Tita AAA A aa 9 66 PEICA ADA PE e dado e ae a chat Ges 9 67 PCICX IN TEN ii AAA AE 9 68 P GIGX INTPN MET 9 69 POICG X ART NEE 9 70 ARANA NS TEE 9 71 Nell HR 9 72 P CIGX AIRED RY EE 9 73 NEE Ee A UR WEE 9 74 GIG STATUS A o have besa a chase a 9 75 PCICX SUBNO AA a a eai ai 9 77 Rtl MENDID uerg tiers deeg eege ER age ey ul deg gege EE eege CAE ee 9 78 PCI Wie Re e EE 9 79 Se EAR PPBAR ca Ar 9 79 PGILO PSBAR KEE 9 8
75. 5232 x o e e oe 2 O Hh GH Zo o o o ce er 2 3 CS ESe S SS SZ ZE es H az EC 2 SUE Ba E E s e EE doses 825588888 o o Hd 5 Oo n a 5 O no O e 2 O a SZ o SS oa a HO d M d e S 28S 8 S805 geo os E ate t GC S Reserved aAezg oetetAACLZOAOH GG o Reserved EA y yy Very t tt debe dt teddy y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 1 Reserved Checkstop Error 0 No Error 2 1 CPC710 initiated checkstop occurred Flash Write Error 0 No Error 3 1 Write to flash occurred when not enabled DMA Controller Access Error 0 No Error 4 1 Access performed to DMA Controller when not enabled see DMAO_GSCRP DMA0O_GSCRU on page 9 45 Access to Disabled System I O Address Space Error 0 No Error 5 1 Access performed to System l O address space that is not enabled Register Summary 9 35 CPCO_SESR System Error Status Register Bit s Description 6 12 Reserved Address Bus Parity Error O No Error 13 1 60x bus address parity error detected by the CPC710 Data Bus Parity Error O No Error 14 1 60x bus data parity error detected by the CPC710 Addressing Error Detected for CPU 0 or CPU 2 0 No Error 1 Addressing error This bit is set when the following conditions are true 15 CPC710 is not selected by the current CPU access SYS_L2_HIT signal is not driven active after AACK by any agent on the system bus CPCO_ERR
76. 6 and if FPHB mode or CHRP mode is selected in CPCO_PGCHP register bits 0 3 Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8110 Access Type Read Write 8 a o Q 5 o i o E Reserved di Reserved Other Address Space Size H Viv vy y 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 6 Reserved Enable Memory or lO Space 7 O Memory Space 1 IO Space 8 23 Reserved Additional Address Space Size xFP 16 MB xFE 32 MB x FC 64 MB xF8 128 MB 24 31 SEO 256 MB xE0 512 MB SCD 1 GB x 80 2 GB x 00 Access disabled Register Summary 9 103 PCILx PR Personalization Register This register provides additional programmability of the PCI Bridge logic Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 7F20 Access Type Read Write PCI ISA Bridge Deadlock Avoidance Disable Grant Active To Frame Active Time out Disable gt lt PCI Master to Memory Address Translation in PREP Mode lt 3 S o 3 S no O Tox C O Xx o 9 Oo o E a 27 2 X D 2 O e A oO E Cc Te o 5 D x D 5 3 bel 2 5 oe o o AT oO z gt 2 E O O lt 15 gt gt D I D O x E CO gt 0 z O D D se Ss oc E i E So E O o 8 8 ha o a 3 z as lt E B Reserved Pr rvvy Ai y y Y y y y yy y 0 1 2 3 5 6 7 8 9 10 11 12 13 14 15 1
77. 6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Parking Control Ox Bus is parked on CPC710 0 1 10 MRU algorithm for parking 11 Park specified ARB level below in bits 5 7 Deadlock Avoidance Signal Selection PCI32 Bridge Only To avoid deadlocks with PCI ISA bridges on the PCI 32 bit bridge the bridge must indicate to the CPC710 that a PCI access is about to occur before the P_GNT signal is activated Any posted PCI 32 bit bus transfers must be flushed prior to activating the P_GNT signal and any accesses to the PCI 32 bit bus must be disabled after the GNT is given and continue disabled until the PCI access is complete and the P_GNT signal is removed The PCI ISA bridge must not grant the secondary ISA bridge until the CPC710 has activated the P_GNT signal This bit should always be set to 1 2 The CPC710 provides two input signals for this purpose that are selectable with this bit 0 Selects the P_REQI5 signal P_GNT 5 indicates buffers flushed and any PCI Transfers will be disabled on the 60x bus until the P_REQ 5 signal is deactivated 1 Selects the P_MEMREQ signal P_MEMACK indicates buffers flushed and any PCI Transfers will be dis abled on the 60x bus until the P_MEMREQ signal is deactivated Machine Check Processor If an error is detected as a target during a PCI access operation the CPC710 generates a Machine Check to the pro 3 cessor specified by the value of this register 0 PCI bridge logic machine checks p
78. AS1_ and WEI outputs by Multiplexing 15 Second Multiplexing Control of SDRAM Signals SDQM 1 SDQM signals are using PCG_ARB outputs by Multiplexing SDRAM Type 00 Standard modules SDRAM 16 17 01 Registred DIMMs SDRAM mode 2 not available for future use 10 Registred DIMMs SDRAM mode 1 11 Reserved unpredictable result 18 Reserved Must be left to 0 Registered DIMMs extra clock cycle 1 Following signals are shifted by one Clock cycle 19 MUX_CLKEN1B_ MUX_CLKEN2B_ MUX_SEL_ 20 Reserved Must be set to 1 91 Registered DIMMs Write extra cycle 1 Data to be written to the SDRAM Memory is maintained one more cycle Registered DIMMs extra clock cycle 1 Following signals are internal shifted by one Clock cycle SDCKE and SDCS signals must be external shifted by one Clock cycle MUX_CLKENA2 MUX_OEB_ SDRAS_0 22 SDRAS_1 SDCAS_0 SDCAS_1 WE_0 WE_1 MADDRO_ODD MADDRO_EVEN MADDR1 13 BSO and BS1 23 Reserved Must be left to 0 Extend CAS Latency CL 24 O CAS Latency programmed to 2 cycles 1 CAS Latency programmed to 3 cycles Extend RAS Precharge tRP 25 O RAS Precharge programmed to 2 cycles 1 RAS Precharge programmed to 3 cycles Extend RAS to CAS Delay tRCD min 26 O RAS to CAS Delay programmed to 2 cycles ale RAS to CAS Delay programmed to 3 cycles Extend RAS Active Pulse Width tRAS min 27 O Programmed to 5 cycles 1 Programmed to 6 cycles Mutibanking Enable 28 O Multibanking Not active 1 Multibanking is active
79. BW Single Beat Write SBR Single Beat Read 4 3 Data Gathering The 60x logic gathers data for CPU store transfers to the PCI bus bridges During data gathering single beat stores of up to 32bytes from the CPU are gathered before being sent to the PCI bus bridge unit Data gathering reduces asynchronous boundary crossings and facilitates data bursting on the PCI bus 4 10 CPC710 User s Manual A If there are store buffers that PCI logic went idle m Idle gt have not been transferred to PCI send to PCI logic Single beat store to PCI Memory Space No If there are store buffers that have not been transferred to PCI send to PCI logic Is address gatherable or first Yes Is there a store buffer available Yes Save address for compare e SYS_TA the data off 60x bus and place in buffer Wait for buffer to empty Is PCI bridge logic busy No Is this the last location in the buffer Yes No Y Initiate command to send Reset first flag store buffer data to PCI Figure 4 3 Data Gathering Algorithm 4 4 SYNC and EIEIO When a processor executes a SYNC instruction a SYNC address only tenure is broadcast on the 60x bus to notify the system that a software placed barrier is present The system is responsible for ensuring all previously exec
80. Bit error the controller indicates the error to the requesting logic through the response bus instead of using DAT_ERR If this occurs in diagnostic mode the error is logged into SDRAMO_MESR and SDRAMO_MEAR but not reported through the response bus 6 10 6 Overlapping Memory Extents Overlapping Memory Extents are not detected until an access occurs to an address mapped to two different configuration extents When an overlap condition is detected the hardware follows the following procedure 1 Set the Overlapping Memory Extent error bit in SDRAMO_MESR if no hard errors exist 2 Store the address in SDRAMO_MEAR if no hard errors exist 3 The Memory Controller responds with dummy data for reads ignores write data and indicates an Invalid Address error to the requesting logic To enable further error logging the software writes zeros into the SDRAMO_MESR When a Single bit or a hard error occurs after an Overlapping Memory Extent the error is not logged into SDRAMO_MESR and SDRAMO_MEAR 6 10 7 ECC Check bit and Syndrome The Error Checking and Correction ECC provides double bit error detection and single bit error correction for a 64 bit double Word When a double word is stored in memory and 8 bit ECC check code is generated by the CPC710 and stored with the data Therefore the data width on the memory bus is 72 bit 64 bit data and 8 ECC check bits Memory Controller 6 17 6 10 7 1 Single Bit Error Correction When a double
81. C 8 is set to 0 See CPCO_ERRC on page 9 17 The CPC710 will signal an addressing error by generating TEA or MCP on the system bus dependent on program ming of CPCO_PGCHP 26 See CPCO_PGCHP on page 9 26 CPU to PCI Bus Access Error for CPU 0 or CPU 2 0 No Error 16 1 Error occurred on PCI32 or PCI64 bus while servicing processor load store request PCI32 Bus Master Error O No Error 17 1 Error occurred during PCI master initiated operation PCI64 Bus Master Error O No Error 18 1 Error occurred during PCI master initiated operation DMA Error for CPU 0 or CPU 2 0 No Error 19 1 Error occurred during DMA transfer Data Bus Timeout Error O No Error 20 1 Indicates that the CPC710 has detected a 8ms time out between DBG to last SYS_TA or SYS_TEA In this case of error the CPC710 activates also the CHKSTOP signal CPU Access to Memory Error for CPU 0 or CPU 2 0 No Error 21 Error occurred during an access by the CPU to memory Error logged in SDRAMO_MESR and SDRAMO MEAR Addressing Error Detected FOR CPU 1 or CPU 3 O No Error 1 Addressing error This bit is set when the following conditions are true 22 CPC710 is not selected by the current CPU access SYS_L2_HIT signal is not driven active after AACK by any agent on the system bus CPCO_ERRC 8 is set to 0 See CPCO_ERRC on page 9 17 The CPC710 will signal an addressing error by generating TEA or MCP on the sys
82. CERx Note DIMMO Bank1 and DIMM1 Bank1 SDRAMO_MCERO DIMMO Bank2 and DIMM1 Bank2 SDRAMO_MCER1 DIMM2 Bank1 and DIMM3 Bank1 SDRAMO_MCER2 DIMM2 Bank2 and DIMM3 Bank2 SDRAMO_MCER3 DIMM4 Bank1 and DIMM5 Bank1 SDRAMO_MCER4 1 DIMM4 Bank2 and DIMM5 Bank2 SDRAMO_MCER5 1 1 When using SDRAM and Data Mask Mode is active see SDRAMO_MCCR bit 11 and the CPC710 can support only up to four bank To configure contiguous address spaces with different bank sizes software must put the largest bank sizes at the lowest addresses and continue in order to the smallest bank sizes To set up the SDRAMO_MCERx registers software must read the PD bits and the ID bits for each 6 14 CPC710 User s Manual DIMM These bits are located in the System I O registers see SDRAMO_MCERO 5 on page 9 120 The following table describes how to initialize these registers DIMM Description Table 6 13 SDRAMO_MCERx Register Initialization Device Bank Size MB If SDRAMO_MCCR 8 1 If SDRAMO_MCCR 8 Number of Am Bara enn A9 Monen seg og 2 1 4 Not equipped off x3FF off 4 2 4 4 x3F3 x3FF x3FF 4 1 8 Not equipped x3FE off 8 2 8 8 x 3E3 x 3FE x 3FE 8 1 16 Not equipped x 3FC off 16 2 16 16 x 3C3 x3FC x3FC 16 1 32 Not equipped x 3F8 off 32 2 32 32 x 383 x 3F8 x 3F8 32 1 64 Not equipped x3F4 off 64 2 64 64 x 303 x3F4 x3F4 64 1 128 Not equipped x 3F0 off 128 2 128
83. CLK100MHz SYS_ADDR SYS_DATA MUX_MDATA MEM_DATA DH MEM_DATA DL MADDRESS SDDQM SDCKE SDRAS SYS_TS SYS_TA SDCAS WE CPC710 User s Manual 10 2 HULU 3 z ne 4 1 2 EE GHGs WGA a Gaia Wil eas EE O_o By A WW BB WO D WE O 4 AS ARA Y J Aa Di AAA A ds E Geet O O A A A WE E BEEM A E be aves PENE o T a NN S WENDEN WW II el SE o NA U WEED A EN EM EN EE BEE AAA EEA N C EE L JEL JEL EL eb ye eee ee wile Su ye a S CO Bye _j HBB Lk Jeb Je O E Leb ye ee 4 A ee A ae lo a NEE WW IW A RE H GH E DEE EE WE E E E ELAN A x A H A ER EEN A D E ee Sh AEE AA a Ao d A A bie be bal A E SE E ke Beles city N A SE A BBR EL Jeb EM EE EN EE BEE EEH nc ot eee Na H AAA EEN A ee ee EES ep EE BEEN dl en o NS 2 H E A O O EE E WE E EE BEE EE e A o e MO WEN Ben Wen BEE E EE BEE E EE o N Wb H WE Men D ll Select E le tele Dt dee EE H WEE e E F FEE at 4 F 4 LARA ss Lo 1 SEI H MAMPARAS ep A A A ss 2 a A A x e 52 st Ch CBee erry QS
84. Cx_INTPN 9 69 PCICx_LATTIM 9 70 PCICx_MAXLTNCY 9 71 PCICx_MINGNT 9 72 PCICx_REVID 9 74 PCICx_STATUS 9 75 PCICx_SUBNO 9 77 PCICx_VENDID 9 78 PCILO_PPBAR 9 79 PCILO_PSBAR 9 80 PCIL1_ITADDRESET 9 82 PCILx_BARPS 9 85 PCILx_BIODLK 9 86 PCILx_CFGADDR 9 88 PCILx_CFGDATA 9 89 PCILx_CRR 9 90 PCILx_CTRLW 9 92 PCILx_DLKCTRL 9 93 PCILx_DLKDEV 9 95 PCILx_INTACK 9 96 PCILx_IOSIZE 9 97 PCILx_MSIZE 9 98 PCILx_PCIDG 9 99 PCILx_PIBAR 9 100 PCILx_PLSSR 9 101 PCILx_PMBAR 9 102 PCILx_PPSIZE 9 103 PCILx_PR 9 104 PCILx_PSEA 9 106 PCILx_PSRCR 9 107 PCILx_PSSIZE 9 109 PCILx_PSWCR_ 9 110 PCILx_SIBAR 9 112 PCILx_SMBAR 9 113 PCILx_TIODLK 9 114 PCILx_TPMDLK 9 115 SDRAMO_MCERO 5 9 120 SDRAMO_MEAR 9 123 SDRAMO_MWPR_ 9 125 SDRAMO_SIORO 9 127 SDRAMO_SIOR1 9 128 S SDRAMO_MCERO 5 9 120 SDRAM0_MEAR 9 123 SDRAM0_MWPR 9 125 SDRAMO_SIORO 9 127 SDRAMO_SIOR1 9 128 X 2 CPC710 User s Manual Revision Log Revision Summary for Fourth Edition September 2002 Chapter 4 8 9 Description 4 6 Deadlock Avoidance Most of this section two pages replaced by new content 8 1 and 8 3 INT2 signal name changed to IT2 as in CPC710 datasheet Table 9 3 renamed Deadlock Control register to Deadlock Avoidance Control register Edited CPCO_PGCHP register Edited CPCO_SESR register Edited CPCO_SIOCO register Edited DMAO_GSCRx register Edited DMAO_XSSRx register Edited PCILx_DLKDEV register Edited PCILx_PCIDG register Edited PCILx_PR register Ed
85. D8 16 23 DIMM Pair 2 Presence Detect Pins PD1 PD8 24 31 DIMM Pair 3 Presence Detect Pins PD1 PD8 Please see SDRAMO_MCERx Register Initialization on page 6 15 for device supported values Register Summary 9 127 SDRAMO_SIOR1 System l O Register 1 Address x FFOO 1420 Access Type Read Only User Defined y 4 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 User defined The read of this register results in the assertion of the PRES_OE1 signal and a Read cycle through the PCI32 A D lines That permits a read of the outside buffers containing the presence detect bits Bit 0 of this register correspond to bit 31 on the PCI A D lines 9 128 CPC710 User s Manual Chapter 10 Timing Diagrams 10 1 CPU to Memory Transactions A A A EE E E IN EE Pe E GE 01112 3 1415 16 17 18 19 1101141121 131 141151161171 181191201211 221 23 24 25 26 27128 291 30 31 32 BF aise tie Si SI E a Sipe i te ae A Sar cigar ite OS GE EES exome ihiihi SYS_ADDR T E SYS TA EPR AO A L SYS CAA rr A 3 a MUX_MDATA MEM_DATADH INN DT
86. DMA Chaining Enable 31 When set to 1 it indicates that the DMA chaining is enabled and all registers for the next DMA will be loaded with the values stored in memory descriptor at the address given by bits 0 26 Register Summary 9 53 PCICO_DLKRETRY PCI32 DeadLock Retry Counter Reset Value x00 Address x57 Access Type Read Write DLKPCICx_RETRY D 4 76543210 Available only for the PCI32 this 8 bit counter is used to limit the number of Retries in the case of an access in a 7 0 deadlock area space defined with the PCILx_BPMDLK PCILx_TPMDLK or PCILx_BIODLK PCILx_TIODLK regis ters 9 54 CPC710 User s Manual PCIC1_INTRESET PCI64 Reset Interrupt Resets one of the posted interrupt G_INTA G_INTB G_INTC G_INTD on the PCI 64bit bus Reset can be done from the PCI 64 or from the CPU in configuration mode The CPU can only execute the SET of INTA INTB INTC INTD when writing in Register INT_SET at address CPCO_PCIBAR x 000F 8310 Reset Value x 0000 0000 Address x68 Access Type Read Write Reset_INT M y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Y 4 3 Bit s 31 4 Reserved RESET_Interrupts 0 No action Description 1 Resets the bit corresponding to one PCI64 interrupt Bit 0 G_INTA Bit 1 G_INTB Bit 2 G_INTC Bit 3 G_INTD Register Summary 9 55 PCIC1_ITADDSET Set PCI64 In
87. DRAMO_MWPR 16 27 OxFFF PCILO_PPBAR 24 31 0x24 PCILO_PPSIZE 24 31 OxFE SDRAMO_MWPR 30 1 9 126 CPC710 User s Manual SDRAMO_SIORO System UO Register 0 This register is user defined However it has been introduced in the PowerPC chip support to provide the memory DIMM presence detect pins for all four pairs of DIMM sockets The CPC710 supports a maximum of four pairs or eight DIMMs The DIMM pairs must be of exactly the same type and therefore only one DIMM presence detect pin of each pair are read in from this register The read of this register results in the assertion of the PRES_OEO0 signal and a Read cycle through the PCI32 A D lines That permits a read of the outside buffers containing the presence detect bits Bit O of this register correspond to bit 31 on the PCI A D lines Reset Value x 0000 0000 Address x FFOO 1400 Access Type Read Only User Defined y y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 User defined Example of usage DIMM Pair 0 DIMM Pair 1 DIMM Pair 2 DIMM Pair 3 Presence Detect Pins Presence Detect Pins Presence Detect Pins Presence Detect Pins M y A y y y A 4 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 7 DIMM Pair 0 Presence Detect Pins PD1 PD8 8 15 DIMM Pair 1 Presence Detect Pins PD1 P
88. DR_LAT FLASH_OE gt OE FLASH_WE gt WE Strap for Flash write i EE OS a protection O LJ Y CE SS A app F_AD 18 0 512 K x 8 BOOT FLASH Fasa cel 1 Boot Flash Enable FLASH_CE des gt gt ADD BCT245 F_AD 28 0 REG gt OE PRES OFT PDbits 0 WE PRES_OE1 gt WE REG1 0 31 EXTENDED FLASH PDbits 1 0 31 up to 256 MB PRES OE0 gt Presence Detect REGO 8 bits Bank Note There is no output enable control for the LVT245 drivers All control is done by the Direction control bit on signal XCVR_RD For a Read of the Boot ROM Extended Flash data the XCVR_RD signal is at Up level 1 such that the Data is transferred from the A Side Flash to the B Side CPC710 PCI32 AD bus The 245 Buffer is recommended to limit the loading on the PCI 32 bus Figure 3 1 Connection of Boot ROM and System UO Registers to Device System I O Interface 3 3 3 4 CPC710 User s Manual Chapter 4 60x Interface The 60x interface ties the CPC710 to the PowerPC 60x system bus It performs the following functions e Arbitration e Configuration e Processor load store address decoding e PCI to Memory access Snoop operations e Sync EIEIO processing e Endian translation e Reset logic operations e Time base functions 4 1 Endian Support The Data in a system built with the CPC710 are in the following mode e System Memory Big Endian e PCI space Little Endian Bytes are always swapped inside the CPC710 e PowerPC Pr
89. GB x 7FFF FFFF Area to map System Memory 16 MB y x Figure 2 1 Memory Map Addressing Model 2 1 2 2 CPU to PCI Addressing Model 2 2 1 PREP and FPHB Modes Programmable registers described in Specific PCI Host Bridge Registers on page 9 8 map PCI Memory and PCI I O address spaces into the 4 GB System address space Each PCI bridge in the CPC710 contains a set of these registers allowing firmware to program PCI address spaces anywhere in memory rather than at fixed PCI address spaces Processor View PCI UO Space PCI Memory Space 4GB 4GB16MB n Peripheral PCILx_MSIZE a QQ o Da 2 io E PCILx_SMBAR PCI Memory ke 2 E PCILx_PMBAR gt S PCILx JOSIZE Peripheral a UO Space PCILx_SIBAR PCI I O PCILx_PIBAR gt IMB raisses 0 Figure 2 2 CPU to PCI Addressing Model PREP and FPHB Modes As the above figure shows the CPC710 monitors addresses on the processor bus to determine whether a CPU address falls within the ranges specified by the following PCILx_SMBAR PCILx_MSIZE and PCILx_SIBAR PCILx_IOSIZE registers e PCILx_MSIZE on page 9 98 e PCILx_SMBAR on page 9 113 e PCILx_IOSIZE on page 9 97 e PCILx_SIBAR on page 9 112 If the address falls within one of these ranges the 60x interface logic passes the address and command to the appropriate PCI bridge lo
90. HP register 0 DLK see below DLK O Deadlock Asserted when processor range of address is out of the non deadlock zone An address SYS_ARTRY is sent to the PowerPC when DLK is set Programmed by setting bit 20 of the CPCO_PGCHP register 0 NODLK see below NODLK Deadlock Disable Used only when the deadlock address range checking is programmed Asserted 0 deadlock checking is disabled If tied high 1 deadlock checking can be performed External Transfer Acknowledge Hit A transition from high to low of this signal results SYS_TA_HIT in the generation of the SYS_TA output signal in the following system clock cycle Must be tied to Vpp 3 3V when unused SDRAM Interface BS1 0 Internal Bank Select O MDATA00 63 Memory Data 1 0 MDATA64 71 Memory Data ECC bits 1 0 MADDRO_ODD Memory Address bit O for odd DIMMs O MADDRO_EVEN Memory Address bit 0 for even DIMMs O MADDR13 1 Memory Address bits 13 to 1 13 is msb O SDCS00 11 SDRAM Chip Select O SDCKE0 9 SDRAM Clock Enable Ten signals with same shape for buffering issues O Memory Write Enable two signals with same shape for buffering issues WE1 can be WEO 1 converted in a Chip Data Mask SDDQM by setting bit 14 of the SDRAMO_MCCR O register SDRAM Row Address Strobe two signals with same shape for buffering issues SDRASO 1 SDRAS1 can be converted in a Chip Data Mask SDDQM by setting bit 14 of the O SDRAMO_MCCR register SDRAM Column Address Strobe SDCAS0 1 two signals with same s
91. Internal node for Debug Must be left to 0 SYS_ADDR32 SYS_ADDR33 SYS_ADDR34 SYS_ADDR35 SYS_ADDRP4 1 By multiplexing CPC710 Internal nodes are on the I O pins 31 Internal node for Debug Must be left to 0 SYS_SRESET2 SYS_SRESET3 SYS_MCP2 SYS_MCP3 1 By multiplexing CPC710 Internal nodes are on the I O pins 9 18 CPC710 User s Manual CPCO_GPDIR GPIO Direction Register This register sets the direction of signals input or output on pins GPIOO GPIO1 and GPIO2 Reset Value x 0000 0000 Address x FFOO 1130 Access Type Read Write Cc 9 5 o oan g L o O g 5 Reserved y Y y Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description GPIO 0 Pin Direction 0 0 Input 1 Output GPIO 1 Pin Direction 1 0 Input 1 Output GPIO 2 Pin Direction 2 0 Input 1 Output 3 31 Reserved Register Summary 9 19 CPCO_GPIN GPIO Input Value Register This register stores values of the signal on pins GPIOO GPIO1 GPIO2 if it is defined as input Reset Value x 0000 0000 Address x FFOO 1140 Access Type Read Only oO 5 bal gt E a 5 N o o 2 2 bes o O g 5 Reserved y y y y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 GPIOO Input Pin Value 1 GPIO1 Input Pin Value 2 GPIO2 Input Pin Value 3 31 Reserve
92. MA transfer when any of the following conditions are detected e TLBSYNC operation detected internal commands are completed before termination e Improper DMA transfer setup e Second DMA transfer initiated when one is already in progress e The transfer crosses a page boundary 8 4 DMA Transfer Registers Several registers support the DMA transfer process They are mapped to two different address spaces so the software can mark the x FF1C xxxx range as user space and the FF1E xxxx range as privileged space This provides protection needed to allow the eciwx and ecowx instructions to be executed by application level software The registers are listed in the following table and are described in DMA Registers on page 9 45 Table 8 1 DMA Transfer Register Summary User Privileged Address Mode Address Mode DMA0_GSCRx FF1C 0020 0 31 R FF1E 0020 0 31 R W Global Control Register DMAO_XCLRx FF1C 0030 0 31 R FF1E 0030 0 31 R Cache line increment Register Register Description 8 2 CPC710 User s Manual Table 8 1 DMA Transfer Register Summary User Privileged Description Address Mode Address DMAO_XSCRx FFic 0040 0 31 RW FF1E 0040 0 31 SE Control Regis Register DMAO_XSSRx FF1C 0050 0 31 FF1E 0050 0 31 DMA Transfer Status Register 0 3 0 3 DMAO_XPARx FF1C 0070 FF1E 0070 PCI Address Register 4 31 4 31 DMAO_XWARx FF1C 0090 0 31 FF1E 0090
93. MO_MEAR Return corrected data to PCI device Proceed normally with PCI transaction Set double bit error in SDRAMO_MESR Set error address in SDRAMO_MEAR Set memory error bit in PCILx_CSR register In the case of double bit ECC error after a PCI to Memory access either signal SYS_MCPO or SYSMCP1 will be active depending on the setting of PCILx_PR 3 0 SYS_MCPO signals Machine Check 1 SYS_MCPT signals Machine Check Loads Target abort PCI transfer Set signaled target abort bit in PCI status register Signal Machine Check with SYS_MCP0 1 Stores Signal Machine Check with SYS_MCP0 T Diagnostic Notes Set double bit error in SDRAMO_MESR Set error address in SDRAMO_MEAR Return uncorrected data to PCI device Proceed normally with PCI transaction 1 Normally means that dummy zeros are returned for loads and write data is ignored 7 8 CPC710 User s Manual Table 7 7 PCI Master Error Handling Page 2 of 2 Operation Access to System Memory cont d Access to Device on 2nd PCI Bus Notes Error Invalid Address Detected SERR Active Detected PCI Bus Data Parity Error during PCI Master Store Detected PERR during PCI Master Load Mode Enabled by PCI PCICx_CM D register bit 6 Action Set invalid address error in SDRAMO_MESR Set error address in SDRAMO_MEAR Set invalid memory address bit in PCILx_CSR Loads Target abort PCI transfer Set
94. Mies S5 L xed ee il xe 1 11 00111 111 00 11111111 001 110 10 41 01 1 S6 1 1 01 Jee oak Trg wd 00111 0 111 00 0 11111111 001 410 1 S7 1 110 10 1 01 aro ALL ee deer ll Zaff 1 11 00111 111 00 0 11111111 o 1 Check bits are defined in the table as the XOR in one row of the active 1 s in the 64 bits of data e The single bit error Syndrome for each bit to be repaired by inversion in the CPC710 can be read in each column of the table For example Bit 16 is defective if syndrome is S0 7 x011xxx1 e The other possible nonzero Syndrome values not in the table indicates multiple bit errors Since a multi bit error could cause the same Syndrome bit to be set B 1 as a single bit error further qualifiying is necessary This is done by requiring B 0 s in certain bit positions to distinguish between single bit from multiple bit errors a full decode of the 8 syndromes bits is not necessary For example a single bit error has occurred for Data bit zero if syndrome bits 0 1 and 5 are B 1 s and bit 2 is a B 0 Even further qualifying of the syndromes may be necessary 6 18 CPC710 User s Manual 6 10 7 2 Additionnal Information for Software The following is a table of data values required to produce certain ECC check bits This is used by software for testing purpose For each of the desired check bits the specified data is just one of the possible value Table 6 15 Data Values Re
95. NGE1 1 11 4 Clock cycles LADRMAX no action if bit 0 is left to 0 Number of system Clock cycles for activation of the signal XADR_LAT from the time where the CPC710 drive the Flash address on the PCI32 bus 26 27 00 3 Clock cycles value used if bit 0 is left to O and PLL_RANGE1 0 01 4 Clock cycles 10 5 Clock cycles value used if bit 0 is left to O and PLL_RANGE1 1 11 2 Clock cycles 28 31 Reserved Register Summary 9 39 CPCO_SIOCA System I O Control 1 This register provides initialization and control of the Extended FLASH devices attached to the CPC710 through the PCI32 interface Reset Value x 0000 0000 Address x FFOO 1090 Access Type Read Write Bit s Description Flash Priority 1 the priority access of the Boot ROM or the Extended Flash versus the PCI agents is increased Flash Size 000 No Optional Flash Space 001 16 MB 18 010 32 MB 011 64 MB 100 128 MB 101 256 MB Other No Optional Flash Space System Base Address 411 This registers contains the upper bits of the System Base address of where FLASH is mapped to The boundary alignment for the FLASH Space must be an integer multiple of the size of the space FLASH DATA BUS SIZE 00 8 bit system FLASH space 12 13 01 16 bit system FLASH space 10 32 bit system FLASH space 11 Reserved 14 31 Reserved Read Only 9 40 CPC710 User s Manual CPCO_SPOR Software Power On Reset Con
96. Organizations The CPC710 is fully compatible with the JEDEC Standard The following table shows a subset of all supported SDRAMs Table 6 7 Supported DIMMs Number Number DIMM SDRAM DIMM SDRAM SDRAM SDRAM of Chips of Chips Wat Row GolBank Mbits x I Os per Bank Mbyte Row Go Bank Mos i per Bank y with ECC y with ECC 8M Geck 11 8 1 11 9 1 Sige ee Dee 11 8 1 1Mx16 441 12 8 1 11 10 1 11 10 1 11 9 1 32M on 11 9 1 Single 12 8 2 11 8 2 13 8 1 12 81 11 10 1 12 9 2 11 1011 64M 12 9 2 KANA Single 13 8 2 12 9 1 13 9 1 13 8 1 12 10 2 16Mx4 E S i 128M 12 10 2 16Mx16 Hae a Single 13 10 1 16Mx4 13 9 1 3 le 13 9 2 16Mx16 A 12 9 2 4 1 12 10 2 16 2 12 10 2 831 Greng 13 10 2 12 10 2 4 1 9 13 10 1 1642 13 9 2 444 512M 13 10 2 8 1 Single ISA We pene 16 Fa 13 10 2 16 2 13 11 2 16 2 Note The number of chips per SDRAMO_MCERx is double the number of chips per DIMM bank Memory Controller 6 6 SDRAM Buffering Requirements The SDRAM interface is designed to run in a 133 MHz environment Because signal loading is critical some outputs connect to four or eight pins The following table lists loads and running frequencies for all SDRAM signals that use the 60x bus clock Table 6 8 SDRAM Input Signal Frequencies Maximum Input Capacitance Signal Name Running Frequency Note SDRAM Note 1 BUS_CLK 5pF 30pF Unbuffered DIMM Note 2
97. PC710 User s Manual CPCO_SESR System Error Status Register This register is the primary error status register for the CPC710 and should be read first after a Machine Check interrupt occurs MCPO MCP1 MCP2 or MCP3 activated by the CPC710 All errors that result from CPU initiated transfers are logged in this register Errors resulting from transfers initiated by a PCI Master or by the DMA controller will result in bits 17 18 or 19 being set and require software to interrogate additional error registers in the PCI bridge logic and the DMA controller logic Bit 16 CPU to PCI Bus error will also require software to interrogate additional error registers in the PCI bridge logic The bits 22 23 24 25 that are available for read after a CPU1 Machine Check interrupt have the same meaning as errors reported on bits 15 16 19 21 for CPUO Software is responsible for writing zeros to this register in order to clear or deactivate the appropriate SYS_MCP0 3 signal Reset Value x 0000 0000 Address xFFOO 1060 Access Type Read Write S a ie uw Z D D o D o a vo S O gt O ODO O D e LA E S o O S oO O o wm zz O o A e Ke a 2 5 m 5 L gt a 070 D ke 2 O ODO O Lo D QO a D T og a SOS e O Subst Pan ote pa 5 5 z 5 5gr6s5s5 a E gt g 2 UguQuas 2 5 D pa aso ak Lr Ze A SC 5 E SEE o S p See eo ele ee ee ee LI L Z2 U gt 220
98. PCIBAR x 000F 7EFO for PCI32 after several PCI clocks 5 3 PLL for Clock System Recommended PLL input controls setting For proper PLL operation it is recommended to set the PLL input control signals as shown in Table 5 1 It is also recommended that the tuning bit inputs be accessible and programmable on the system board to permit the use of other combinations in the case of difficulties to lock the PLL This can adapted to conditions in the system environment Table 5 1 PLL Inputs Control Signal Setting PLL Frequency range selector Loop stability for the System Clock tuning control of the PLL 00 50 MHz to 100 MHz 010101 50 MHz to 100 MHz 01 58 MHz to 114 MHz 010011 58 MHz to 114 MHz PLL_RANGE 1 0 PLL_TUNE 5 0 10 66 MHz to 134 MHz 010011 66 MHz to 134 MHz 11 80 MHz to 160 MHz 010011 80 MHz to 160 MHz PLL_VDDA VDDA is the voltage supply pin to the analog circuits in the PLL Noise on VDDA will cause phase jitter at the output of the PLL To provide isolation from the noisy internal digital Vdd signal VDDA is brought to a package pin If little noise is expected at the board level then VDDA can be connected directly to the digital Vdd plane In most circumstances however it is prudent to place a filter circuit on VDDA as shown below All wire lengths should be kept as short as possible to minimize coupling from other signals The impedance of the ferrite bead should be much greater t
99. PU access to the PCI32 or PCI64 bus when the input NODLK is not active is read as a 1 the access is within the address window defined by the appropriate address registers PCILx_TPMDLK PCILx_BPMDLK PCILx_TIODLK PCILx_BIODLK CPCO_PGCHP 24 is set to 1 The CPC710 will then generate a SYS_ARTRY to the CPU bus logic when the externally generated NODLK signal becomes active is read as a 0 4 7 Error Handling for CPU Initiated Transactions The CPC710 uses Machine Checks to indicate errors This allows software to log errors before the system is shut down In an MP environment the CPC710 activates the Machine Check pin that corresponds to the CPU initiating the transaction 4 7 1 Checkstop Errors The CPC710 generates a checkstop when the following are detected e Address parity error on the 60x system bus if enabled e Data parity error on 60x system bus if enabled e Internal timeout due to no response from slave on load The 60x logic performs the following when generating a checkstop 1 Sets appropriate bit s in CPCO_SESR 2 Drives CHKSTOP active until power on reset The following table describes the error handling performed for CPU initiated transactions The 60x logic drives SYS_MCP0 1 signals not the PCI bridge logic or the memory control logic Table 4 6 CPU Initiated Transactions Page 1 of 5 Operation Error Mode Action Note Disabled No action taken Set No Select error bit in CPCO_SESR Se
100. SDCKE BUS_CLK 5pF 50pF MDATAO 1 BUS_CLK 2 7pF 15pF MADDRO 1 BUS_CLK 2 5pF 50pF BUS_CLK 2 5pF 50pF BUS_CLK 2 5pF 50pF BUS_CLK 2 50pF BUS_CLK 2 50pF BUS_CLK 2 50pF 1 These are usual values for a single SDRAM chip V 3 3V T 25C f 1MHz 2 These are usual values for an unbuffered DIMM 8 x 1M x 16 V 3 3V T 25C f 1MHz 3 Signal is critical runs at full speed 6 7 Typical SDRAM Signals The following figure shows all possible combinations of signals that the CPC710 can generate which are decoded by the SDRAM The normal sequence of operation with SDRAM controlled by the CPC710 is 1 Activation 2 Read or Write 3 Precharge 4 Suspend mode 6 8 CPC710 User s Manual Active Write Read Precharge Refresh Mode NOP DESEL All All Reg Set ee A E EA H cs ALTE Lo Le Lite do Lo q ARS HERE di address i2 11 0 0 Row Bou y Col e Address 10 Row sf E me BS 1 0 _ ba ke ke EZ Lok CKE alge UL FL FL pies ES MSR value BS 0 Address 1 2 0 NUNN O eee eee Neue yy Figure 6 5 SDRAM Commands issued by the CPC710 6 7 1 CKE Clock Enable Signal As shown following the CPC710 memory controller generates signals that have to be sampled by the SDRAM Memory based on the CKE Clock Enable signal This mode of operation is fully compatible with the JEDEC Standard At time TO and T2 in the following
101. STEM address that PCI Memory is mapped Gott P Note Address must be aligned on a boundary equal to the size specified in PCI Memory Size register 12 31 Reserved Note Address is decoded only if the Master Enable bit in the PCI Command Register is on Register Summary 9 113 PCILx_TIODLK Top of Peripheral I O space with Deadlock Avoidance This register exists on PCI32 and PCI64 Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8230 Access Type Read Write Top of Peripheral I O Space Reserved D vv y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Top of Peripheral I O Space 0 9 Contains the top address for the CPU to PCI IO access with potential deadlock 10 31 Reserved 9 114 CPC710 User s Manual PCILx_TPMDLK Top of Peripheral Memory with Deadlock Avoidance Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8210 Access Type Read Write Top of Peripheral Memory Space Reserved D vy Y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description hue Top of Peripheral Memory Space Contains the top address for the CPU to PCI MEMORY access with potential deadlock 10 31 Reserved Register Summary 9 115 SDRAMO_MCCR Memory Controller Control Register This register provides the primary control for the memory controller logic
102. SYS_DBG1 signals are effectively the same they are logically ORed mode to use for L2 lookaside Quadri processor control dd 1 Arbitration of the 60X bus set for 4 CPU SYS_TA High Z Enable 18 0 After pre charge to up level the SYS_TA goes to High Z 1 After pre charge to up level the SYS_TA is maintained to up level This allows the SYS_TA signal in the case of high loading to reach a valid high level in the system clock period following the pre charge Register Summary 9 11 CPCO_ABCNTL 60X Arbiter Control Register Bit s Description 19 31 Reserved 9 12 CPC710 User s Manual CPCO_ATAS Address Transfer Attribute for Snoop Register This register contains SYS_TT SYS_TSIZ and SYS_TBST values that are used during a snoop transaction These values can be changed according to the type of PowerPC processor This register must be set if bit 25 of the CPCO_PGCHP register is programmed to 1 See CPCO_PGCHP on page 9 26 Reset Value x 0000 0000 Address x FFOO 1160 Access Type Read Write Programming Value x 709C 2508 b 0111 0000 1001 1100 0010 0101 0000 1000 This setting is recommended for the PowerPC750 which is not able to perform Cache memory coherency with Kill and Flush operation as the PowerPC 604 Leg S S z z o 2 c c 2 z k S S S w c 5 2 e g o w w gd S 8 w O Ss D g o be 2 3 2 E 5 Ga o D e bi o o bei o
103. Space Size Reset Value x FFFO 0000 Address CPCO_PCIBAR x 000F 7F40 Access Type Read Write PCI Memory Address Space Size Reserved Additional Address Space Reserved y Y y Y y y y A 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI Memory Address Space Size x FFF 1 MB x FFE 2 MB x FFC 4 MB xFF8 8 MB x FFO 16 MB x FEO 32 MB 9 11 x FCO 64 MB x F80 128 MB x F00 256 MB x E00 512 MB x C00 1 GB x 800 2 GB x 000 4 GB 12 15 Reserved PCI Memory additional Address Space Size CHRP Compliance Ignored in other modes SEET 16 MB X FE 32 MB x FC 64 MB SEO 128 MB 16 23 xFO 256 MB SEO 512 MB Dieu 1 GB x 80 no additional window x 00 no additional window 24 31 Reserved 9 98 CPC710 User s Manual PCILx_PCIDG PCI Diagnostic Register This register contains two mode bits that are used for special modes of operation Reset Value PCI32 x 4000 0000 PCI64 x C000 0000 Address CPCO_PCIBAR x 000F 6120 Access Type Read Write o o 2 a S S o Jo g E 5 lt 3 a Reserved Must Leave at 0 INN y 01 2 34 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 64 bit Mode Enable only for PCI 64 Operates only when the CPC710 is PCI64 bus master 0 Operates as a 32 bit bridge G_REQ64 never activated by the CPC710
104. T pa C9 8 R11 BSO RI0 RO C7 cole 13 1011 61001 R12B51 C8 R11 BSO At0 RO C7 coll 437972 0 default Ca pa bel C8 A11 BSO R10 RO C7 co 13110 2 0 default Ca pa bel C8 A11 BSO R10 Ro C7 co T3 11 2 0 default Ca ous bel C8 A11 BSO R10 RO C7 co 1312 2 0 default Ri3 R12 BS1 Cs R11 BSO R10 Ro C7 co 14 9 2 D1101 Ca ous bel C8 A11 BSO R10 Ro C7 CO 14 10 2 D1110 C9 R12 BS1 C8 R11 BSO R10 RO C7 CO 14 1172 Em R13 Ca ous bel C8 A11 BSO R10 RO C7 co 1412 2 0 default 1 The Memory Controller interleaves with only one memory address bus To handle critical word load individual control of the LSB column address bits is required for the DIMMs MADDRO_ODD is used for the LSB address of the even and odd DIMMs 2 Bit 10 is never used as address during CAS phase The following table is similar to the previous one but it gives correspondence between the bit address on the SDRAM interface and the bit address on the PowerPC bus Table 6 10 SDRAM Address Mapping MADDR Organization BS1 BSO 13 12 110 9 8 7 6 6 4 3 2 4 Ol Row ColBank 26251 Row Address E Kee 11 8 1 b 1010 Row Address A0 A4 A7 A9 Ai0 ATi A AS Aid ME AIG Ai7 M8 AiO y viol See Col Address 0 Au A2 A3 A7 A20 A21 A22 A23 A24 A25 A2 A27 Row Address AD A4 A7 AQ A10 Alt AIS Aid Al AE ME Al AS Ato Col Address 0 Au A2 A3 A6 A20 A21 A22 A23 A24 A25 A2 A27 A 11 8 2 b 0001 Row Addre
105. The Boot ROM interface logic satisfies burst read requests from the processor by concatenating multiple bytes from the Boot ROM The CPC710 is designed to interface with 512 K 1 Mb 2Mb x8 3 3 V Flash memory with 80 to 120 ns access time The following figure shows Boot Flash with the bits used for Address and Data on the PCI32 bus AD lines PCI AD bits 20 0 are used for Flash Address LSB starts at bit 0 Bits 15 8 of the PCI32 bus AD lines are used for the 8 bit data The Boot Flash is accessed under control of the device s PCI32 controller to generate non PCI cycles with FRAME not asserted Flash is read and written by setting bit 4 R W in the CPCO_UCTL Register The PCI access with Frame asserted has the maximum priority The Boot Flash or Extended Flash access to the PCI 32 bus can be increased by setting biit 0 of the CPCO_SIOC1 Register System I O Interface 3 1 During the Flash access the PCI bus is clocked by the System Clock 3 3 2 Extended Boot Flash In addition to the 2MBytes of boot Flash it is possible with the same type of operation to access to 16 32 64 128 or 256 MBytes of Extended Flash The Extended Flash can be Read write by setting the bit 7 R W in the CPCO_UCTL Register FFOO 1000 The pin FLASH_CE_ Extended Flash Chip Enable controls the access of the Boot flash when 1 or the Extended Flash when 0 This signal is set to 0 after that the CPC710 decodes an address in the Extended Flash Space For a
106. The PCILx_BIODLK PCILx_TIODLK space is valid for PCI IO Access 1 The PCILx_BIODLK PCILx_TIODLK space is valid for PCI MEMORY Access DLK_ Output Activation 6 0 This output is never activated 1 This output is activated for read or write access in the potential deadlock space selected DLK_ Output Configuration 7 0 DLK_ output signal is used for PMDLK Space 1 DLK_ output signal is used for IODLK Space 8 11 Reserved Must be left to 0 Timeout Value for CPU to PCI Read Access 12 15 Defined as the number 2 n of events for the timeout counter Bit 17 is used to select the root event for the timeout count Deadlock management on PCI Configuration Access Retry Activation 0 No deadlock Space for the PCI Configuration space x 1 The Deadlock space for the PCI Configuration space is defined by the PCILx_DLKDEV register see PCILx_DLKDEV on page 9 95 Event Root Select for timeout 0 Only retried CPU access to the PCI space which has activated the deadlock avoidance mechanism are used for S Se of timeout 1 All retried CPU access are used for the counter of timeout 18 27 Reserved Read Only DD2 0 ERRATA 9 correction 27 0 ERRATUM is corrected 1 ERRATUM is not corrected DD2 0 ERRATA 8 correction 28 0 ERRATUM is corrected 1 ERRATUM is not corrected ARTRY and Deadlock avoidance circuit improvement recommended value is 0 29 1 The ARTRY is generated for all access except on the access to the main memory when the checking of a Read is already in progr
107. X_CLKENA2_ MUX_OEB_ SDRAS_0 SDRAS_1 22 SDCAS_0 SDCAS_1 WE_0 WE_1 MADDRO_ODD MADDRO_EVEN MADDR1 13 BSO and BS1 23 Reserved Must be left to 0 Extend CAS Latency CL 24 0 CAS Latency programmed to 2 cycles 1 CAS Latency programmed to 3 cycles Extend RAS Precharge tRP 25 0 RAS Precharge programmed to 2 cycles 1 RAS Precharge programmed to 3 cycles 9 118 CPC710 User s Manual SDRAMO_MCCR Memory Controller Control Register Bit s Description 26 27 28 29 Extend RAS to CAS Delay tRCD min 0 RAS to CAS Delay programmed to 2 cycles 1 RAS to CAS Delay programmed to 3 cycles Extend RAS Active Pulse Width tRAS min 0 Programmed to 5 cycles 1 Programmed to 6 cycles Multibanking Enable 0 Multibanking desactived 1 Multibanking is active Shifted Refresh Cycles In normal operation the refresh of all the populated DIMMs is performed at the same time If the 8 DIMMs are fully pop ulated this could produce a high current load all SDCS_ activated at the same time Setting bit 29 to 1 enables the controller to perform successive Refresh only 2 SDCS_ activated at the same time in return the refresh cycle last longer depending on the number of populated DIMMs 0 All banks are refreshed in the same cycle 1 Banks are refreshed one after one 30 Disable Page Mode 0 Memory controller will perform fast page accesses for back to back operations if appropriate 1 Memory controller
108. YS_MCP0 1 Terminate CPU transaction normally Notes 1 A dummy 0 is returned for read operation For write data is ignored 60x Interface 4 17 Table 4 6 CPU Initiated Transactions Page 4 of 5 Detected target abort Set received target abort bit in PCI Status register Set PCI error bit in CPCO_SESR Set error address in CPCO_SEAR register If CPCO_PGCHP 26 0 Loads Signal Machine Check with SYS_TEA Stores Signal Machine Check with SYS_MCP0 T If CPCO_PGCHP 26 1 Signal Machine Check with SYS_MCP0 1 Terminate CPU transaction normally Operation Error Mode Action Note Continue transfer on PCI bus to completion Activate the PERR signal Set data parity error bit 8 in PCI Status register Set data parity error bit 15 in PCI Status register Enabled by Set PCI error bit in CPCO_SESR bit 6 in Set error address in CPCO_SEAR register 4 Pelox cm If CPCO_PGCHP 26 0 D register Loads Signal Machine Check with SYS_TEA oe nica data par Stores Signal Machine Check with SYS_MCP0 1 If CPCO_PGCHP 26 1 Signal Machine Check with SYS_MCP0 1 Terminate CPU transaction normally Disabled by bit 6 in Set parity error bit 15 in PCI Status register PCI Proceed normally with PCI transaction PCICx_CM Proceed normally with CPU transaction D register Continue transfer on PCI bus to completion Set data parity error bit 8 in PCI Status register Set data parity error bit 15 in PCI Status register Access to
109. a aa a el ee adas 2 9 Chapter 3 System UO Interface cccccseeeeeeeseeeeeeeseeeeeeeseeneeenseeneeeesseneeeeesseeeeeeesseeeeeenseees 3 1 Rente ee IEEE O O EEN 3 1 System UO Registers Application Presence Detect Bits eseeeeseeseeeeeeerresresiierrrerinsrrnerrnerrnsirnsrnnsiensieesrenne 3 1 AE AA NN 3 1 BOOt ROM E 3 1 Extended Boot Flash iii cl gevetessagnuehsueseutes AANA AENA AENA sdanetesctepiaes sgepetessaeesneeearays 3 2 Byte ordering in the Boot amp Extended Flash for 8 bit DUS size oo eee cece cence cence eect eeeeeeeeeeeeeaeeeeaeeeeaaees 3 2 Chapter 4 BOX Iter aCe iii edie este eater ack tet a eect 4 1 Endian Support 4 27 E Sabena oia 4 1 PowerPC Processor Behavior Mode eeesecescceeseceeeececeenersnereseeeeeeeeesenecanesenenssaeessanestanesseneneeaeeeneners 4 4 Processor Behavior in LE Mode ooooocnccccnocccoconcnonnconononanonononcnnnn corno nn nan nn ran n rra n rra rra rn rn nn nr n rra rr nna rra 4 4 Endian Ce 4 4 60x Bus Arbiter Description oo eee ee cece e cence eeeeeteaeeeeeeeeeseeeeaeeseaeeseaeessaeeseaaeeseaeeseaeeseaeessaeeseseeeseaeessaeeeeaeeeseees 4 5 Rotating Priority Resolution oooononccnnncnnnoccnoncnnonnncnnncnnnn conocio non cnn cnn nono nn rre 4 6 Address Bus Pipelining A 4 6 Arbiter te lu CHE 4 6 Internal ABBA sa 4 6 Qualified SYS_BG Equation oooocnocccnncccnonncononcnannnononnnnon nn non cnn n rra rra r ener rn rra rene n rr rn rien ninas 4 6 ASMA WEEN 4 7 SYS BR Negat
110. and Privileged E E E 9 S oa D E ZG o E wp O 22 5 g Reserved Transfer Length Reserved oe 2 Reserved E y y y Y y Y y Jo yy y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 2 Reserved Transfer Length 3 15 Contains the number of Bytes to be transferred in a Loop maximum is 4 K A value of 0 will transfer 0 bytes 16 20 Reserved Global Transfer 21 0 No snoop operations required for accesses to system memory 1 Accesses to system must be coherent 22 Reserved Address Increment 23 0 Do NOT increment I O address during DMA transfer 1 Increment I O address during DMA transfer 24 29 Reserved 30 31 Byte Offset Specifies the byte offset associated with the DMA transfer real address Register Summary 9 49 DMAO_XSSRx DMA Transfer Status Register Reset Value x 0000 0000 Address User x FF1C 0050 Privileged x FF1E 0050 Access Type Read Only User and Privileged S wi Y A 8 5 3 wi S S x SZ 5 E O E gt uu lt H v S 528 E 9 D Sou E s 3 ie E e S 3 Q 3 D 2 5 lt 22 S58 sega amp ow Ws Ka o o SO TS R REEEBEESE B 2060502027050 S SH ES SS og OH DB Reserved Transfer Length Reserved e SE fs ok eo 2 yo yy vy tery LIV 1 yyy 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
111. anism 1 as specified in the PCI Local Bus Specification See heading Configuration Cycles on page 7 4 for additional details Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8000 Access Type Read Write o Q oO D ke 5 2 ZS E Q E E gt E 2 5 3 zZ Ka e 5 D 5 3 e 2 8 i S 3 3 S S 6 Reserved Bus Number a E Zz y y vy yy vy vy vv y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11110 9 8 7 6 5 4 3 2 1 0 Bit s Description Configuration Enable 31 0 Disabled 1 Enabled accesses to the CPCO_CFGDATA register result in CPC710 executing a configuration access to itself or to the PCI bus 30 24 Reserved 23 16 Bus Number Specifies which PCI bus is being configured The CPC710 checks this field to determine the appropri ate configuration action Device Number Selects a particular device to be configured on a PCI bus Device 0 is the CPC710 15 11 Function Number For devices that implement more than one function this field specifies which function to configure within a device E 0000 Access to the CPC710 PCI Configuration Space registers 1111 Special Cycle command issue to the PCI bus device 31 7 2 Register Number Specifies which register out of the 256 byte PCI Configuration header to access 1 0 Always b 00 9 88 CPC710 User s Manual PCILx_CFGDATA Configuration Data Register Reset Value x
112. ansfer cross a doubleword boundary the CPC710 will truncate the transfer size to avoid crossing a doubleword boundary 4 8 CPC710 User s Manual Table 4 4 Burst Transactions SYS_TBST 0 00xxx 16 byte transfer beginning on 32 byte boundary 01xxx 16 byte transfer beginning on odd doubleword boundary Di 10xxx 16 byte transfer beginning on odd 16 byte boundary 11xxx 16 byte transfer beginning on odd doubleword boundary 00xxx 32 byte transfer beginning on 32 byte boundary 01xxx 32 byte transfer beginning on odd doubleword boundary 010 Yes 10xxx 32 byte transfer beginning on odd 16 byte boundary 11xxx 32 byte transfer beginning on odd doubleword boundary 1 3 1 For transfers that cross a 32 byte boundary the CPC710 will wrap to the beginning of the 32 byte block to satisfy the data transfer 2 Unpredictable results will occur if this transfer size is attempted on the processor bus 3 Not supported on store operations Table 4 5 Transfer Types Page 1 of 2 TT O 4 Operation Transaction SE Support as Slave 00000 Clean Sector Address only Yes NOP 00001 LARX Reservation Set Address only No NOP 00010 Write with Flush SBW or Burst No Yes 00011 Reserved arbiter will assume address only transaction 00100 Flush Sector Address only Yes NOP 00101 Reserved arbiter will assume address only transaction 00110 Write with Kill Burst No Yes treated as 00010 00111 Rese
113. ately following a data bus grant At the end of a data bus tenure a slave does not perform a precharge which requires a slave in the next data bus tenure to drive SYS_TA in the first cycle of the tenure The CPCO_ABCNTL 13 mode bit as described in CPCO_ABCNTL on page 9 10 forces the CPC710 to do a precharge if a slave on the 60x bus does not support this function Half Cycle Precharge not Required on SYS_TEA The arbiter does not grant the data bus for two bus cycles following assertion of SYS_TEAs This allows a slave to perform a full cycle precharge on SYS_TEAs 4 2 4 3 SYS ARTRY_PREV in QDBG Equation Eliminated When SYS_ARTRY is asserted the arbiter negates all bus grants in the cycle following SYS_ARTRY This supplants the requirement for masters to qualify associated bus grants by asserting SYS_ARTRY in a previous cycle 4 2 5 60x Bus Transfer Types and Sizes The following tables describe the transaction types supported by the CPC710 on the processor bus The CPC710 supports the PowerPC 604 critical double word burst transactions Table 4 3 Non Burst Transactions SYS_TBST 1 SYS_TSIZ 0 2 A 29 31 Definition 000 000 111 8 byte transfer 001 000 111 1 byte transfer 010 000 111 2 byte transfer 011 000 111 3 byte transfer 100 000 111 4 byte transfer 101 000 111 5 byte transfer 110 000 111 6 byte transfer 111 000 111 7 byte transfer 1 For transfers where the number of bytes to tr
114. ation Space sein 9 6 Read Page Hit from PowerPC CPU to SDRAM 0 0 eeeeeeeeeeeeeeeeeeeeaeeeeaeeeeaeeseeneeteaeeseeeeneees 10 1 Read Page Miss from PowerPC CPU to SDRAM 0 ceseeeeneeeeeeeeeeeseeeeeeneeseaeeseaeeeneees 10 2 Write Burst Page Hit from PowerPC CPU to SDRAM 000 eee eee eeeeeeeeeeeeeeeeeeaeeeeeeeeneeeeeneeees 10 3 Write Burst Page Miss from PowerPC CPU to SDRAM ou eee eeeceeeeeeeeneeeeneeeeaeeseeeeenneeeeneenes 10 4 Write One Byte to Memory from CPU Read Modify Write A 10 5 Read of One Byte from the Boot ROM ooo ee eee eeeeeeneeeeeeeeeeeeeeeneeeeaeeseaeeseeeseeeeeeeaeeseneeeeaees 10 6 Write of One Byte to the Boot Flash ooooocccinccccoccccooccononcnann conan cnnnn conan nncn nn nan n conan rro nn nnnnnrnn cnn 10 6 Read 32 Bytes from SDRAM by a PCI Master on a 66MHz PCI64 bus cooooccccccocccconccccccccnnccnnn 10 7 Write 32 Bytes to SDRAM from a PCI Master on the 66MHz PCI64 bus neccen 10 8 Figures ix CPC710 User s Manual Tables Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 5 1 Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 6 5 Table 6 6 Table 6 7 Table 6 8 Table 6 9 Table 6 10 Table 6 11 Table 6 12 Table 6 13 Table 6 14 Table 6 15 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 7 7 Table 8 1 Table 8 2 Table 9 1 Table 9 2 Table 9 3 Processor Little Endian Address Modification 0 0 0 eeceesseeeseeeeseeeeeeeeee
115. biter Control Register bit 9 at the same time the processor HID register bit is updated If the processor is operating in BE mode bit 9 must be set to 0 to prevent the CPC710 from unmunging or byte swapping the processor s data If the processor is operating in LE mode bit 9 must be set to 1 to unmunge the address as specified in Processor Little Endian Address Unmunge Equations below and to swap the data bus bytes as specified in Processor Data Bus Byte Swap for Little Endian below Table 4 2 Processor Little Endian Address Unmunge Equations Transfer Size Equation to Convert to Address 1 Byte ADDR 29 31 XOR 111 2 Byte ADDR 29 31 XOR 110 and 1 31 1 3 Byte ADDR 29 31 XOR 101 4 Byte ADDR 29 31 XOR 100 8 Byte none Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 A B C D E F G H 60x Data Bus LIAA T 0 78 15 16 23 24 31 0 78 15 16 23 24 31 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Internal H G F E D C B A Data Bus AAA OA ON AA A ANA 0 78 1516 23 24 31 0 78 1516 23 24 31 Figure 4 2 Processor Data Bus Byte Swap for Little Endian 4 2 60x Bus Arbiter Description The arbiter in the CPC710 has the following characteristics Arbitration for three devices two levels for external masters and one for internal CPC710 requests No half cycle precharge required for SYS_TA SYS_TEA ABB and DBB Highly programmable address
116. c Representation Figure 6 1 DIMM Bank Configuration 6 2 3 Interleaved Banks An Interleaved Bank consists of two interleaved DIMM Banks The two DIMM Banks are called Odd and Even As shown in the following figures SDRAMO_MCERx registers must be programmed 6 2 CPC710 User s Manual according to the DIMM Bank configuration used Since the CPC 710 works in an interleaved way the minimum equipment required is two Single or Dual DIMM Banks g Y S Interleaved 2 o Bank 1 ES empty oe DIMM Bank A 2 CH Interleaved 1 gt lt Bank 0 2 programmed gt Single Bank DIMM Odd Single Bank DIMM Even Y SDRAMO_MCERO for Interleaved Bank 0 must be programmed SDRAMO_MCER1 for Interleaved Bank 1 must be empty or bit 0 set to 0 All unused SDRAMO_MCERx locations must be empty Figure 6 2 Programming with Single Bank DIMMs Sege E gt DIMM Bank B DIMM Bank B O boda A Ss an Q e g programmed DIMM Bank A DIMM Bank A ol x Interleaved SQ lt Bank0 is E A programmed Q Ro Dual Bank DIMM Odd Dual Bank DIMM Even SDRAMO_MCERO and SDRAMO_MCER1 for Interleaved Banks 0 and 1 must be programmed Figure 6 3 Programming with Dual Bank DIMMs 6 3 Memory Signal Connections Table 6 2 SDRAM Common Signals Signal Name Type MDATA 0 71 72 bit Data MADDR 13 1 MADDRO_ODD Address MADDRO_EVEN Memory Controller 6
117. ce BIM to TPMO 16 MB range so that this address range becomes 0 to 16 MB 1 in the PCI Memory Space System Memory Alias Enable This bit is used in CHRP mode only for PCl initiated transactions to System Memory S 0 No reponse for PCI access in the System memory alias space 1 Translate an address in the System memory alias space BIM to TPMO 16 MB range so that this address range becomes 0 to 16 MB 1 in the System Memory Space Processor Hole Enable This bit is used in CHRP mode only for Processor initiated transactions a 0 Forwards processor initiated transactions in the range 640 KB to 768KB 1 to the System Memory Space T Forwards processor initiated transactions in the range 640 KB to 768KB 1 to the PCI Memory Space 10 Hole Enable This bit is used in CHRP mode only for PCl initiated transactions 7 0 Untranslate an address in the range 640 KB to 1 MB 1 and then send to System Memory Space le No response to PCI access in range 640 KB to 1 MB 1 Emulation Mode 8 This bitis Read Only and indicates that the CPC710 doesn t support the optional emulation mode of the CHRP mode O CHRP Emulation Mode not supported External Arbiter on PCI64 Enable Read only status bit 9 O Internal arbiter is activated 1 Internal arbiter is deactivated PCI32 Host Bridge Synchronisation Mode 10 12 001 Fast synchronisation xx0 Double synchronisation PCI64 Host Bridge Synchronisation Mode 13 15 001 Fast synchronisation xx0 Double sy
118. counter down when devsel is detected 1 Do nat stop the counter down PCI32 Access Completion 4 O The completion is activated when device is master and not during external exchange 1 The completion appears when the data is not the last one 5 7 Reserved PCI64 Counter Enable 8 O TRDY IRDY PCICx_DISCNT Counters are not activated the MSB is always at 1 PCICx_DISCNT counter is programmable see PCICx_DISCNT on page 9 66 1 TRDY IRDY PCICx_DISCNT Counters are ACTIVATED Register Summary 9 15 CPCO_AVDG Diagnostic Register Bit s Description PCI64 Master Abort 9 0 Window of Master Abort is reduced to one cycle avoid parasitic master abort detection 1 Window of Master Abort is not reduced PCI64 Target Abort 10 0 The CPC710 detects Target abort The Frame output is taken 1 The CPC710 never detects Target Abort but retry indefinitely accesses PCI64 DEVCNT 11 0 Stop the counter down when devsel is detected 1 No stop the counter down PCI64 Access Completion 12 0 The completion is activated when device is master and not during external exchange 1 The completion appears when the data is not a last 13 15 Reserved 16 Reserved Must be left to 0 17 31 Reserved 9 16 CPC710 User s Manual CPCO_ERRC Error Control Register This register controls how the 60x interface logic responds when detecting an error Reset Value x 0000 0000 Address xFFOO 1050 Access Type Read Write
119. ctions oooonccnoccononcninanonannnnnononannnonnn nn narco nnn nn nan n rra n nn nn n nr nn rnn nn 4 15 Checkstop Errors a A A 4 15 Ch apter 5 Initializati n nd ii das 5 1 CPC710 Power Up Sequence ssccceten ced Rese Se ad be cee Sek tad Se Seeded ete ced ee eld eee cbt END EES 5 1 POWERGOOD Power On Reset escceessecesrecesneeeeeeeeeeeeceececsaneesonereseesaeecanessenessneeseaeeeseeestanestenesenneneraes 5 1 PLL for Clock SyStemM id 5 2 Initialization of the SDRAM AE 5 3 Reset e ERR 5 4 Reset in Multiprocessor mode ceeeceeessrecesnecesnereeneeesaceceaneceanerseneseeneeseaeecsanessanessaneeseaeessaeesnaneseenerennenesaes 5 4 Typical Register Setup Sequence AE 5 5 Chapter 6 Memory Controller sccccssseeeceeeeeeeeeeseseeeeesesnneeeeenseeneeensseneeeessneneeeessseneesenseees 6 1 OVEIVIOW e Ee IA 6 1 Bank DESTINOS erasia Ee AE Ee 6 2 SDRAM Banks 2 ee EE e E toes iria 6 2 RO ORT 6 2 Interleaved Banks ici iii 6 2 Memory Signal Connections A 6 3 SDRAM Subsystem Overview A 6 6 Supported SDRAM Organizations 0 0 0 eee eeeceeeseeeeeeeeeeaeeeeaeeeeaeeeeeneeeeaeeseaeeseaeeseaeeseaeessaeeseaeeseseeeseneeseneeenaees 6 7 SDRAM Buffering Requirement AAA 6 8 Keele EE 6 8 CKE Glock Enable Signal eet Eege sts a 6 9 Mapping of System address to SDRAM Memory address with the CPC710 ooo eee eeeeeeeneeeeneeeeeeeeneeeeeee 6 9 Memory Controller ee E CN 6 11 SDRAMO MGGCR Register TE 6 11 SDRAMO_MCERx RegisterS a
120. d 9 20 CPC710 User s Manual CPCO_GPOUT GPIO Output Value Register This register stores values of signal on pins GPIOO GPIO1 GPIO2 if defined as output Reset Value x 0000 0000 Address x FFOO 1150 Access Type Read Write 3 bal gt Cc an 5 6 O 5 O z Reserved y y y Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 GPIOO Output Pin Value 1 GPIO1 Output Pin Value GPIO2 Output Pin Value 3 31 Reserved Register Summary 9 21 CPCO_MPSR Multiprocessor Semaphore This register is used by the IPL boot code to facilitate bring up of processors in an MP environment It pro vides a first access bit BIT 31 that allows a method for processors to determine which processor is the master since both processors are active after power on BIT 31 contains a value of O after power on reset When the first processor read occurs to this register BIT 31 returns a value of 0 All subsequent reads of this register return a value of 1 for BIT 31 In addition to the First Access Bit bits O and 1 provide sema phores for use by the firmware during boot time and are utilized until system memory has been initialized and tested Reset Value x 0000 0000 Address x FFOO 1010 Access Type Read Write Reserved y 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lt Multi proc
121. d Maximum Minimum Interrupt Interrupt Latency Grant Pin Line Disconnect Subordinate Bridge Reserved Counter Bus Numb Bus Numb Reserved GE WE Dead Lock Retry Retry Counter Reserved PCIC1_ITADDSET for PCI64 only PCIC1_INTRESET for PCI64 only Reserved Figure 9 2 PCI Configuration Space 9 3 Standard PCI Configuration Registers The following registers are defined as Little Endian LE ordering Therefore for software running in Big Endian BE mode any access to these registers that is not a single byte access must utilize the 9 6 CPC710 User s Manual load store byte reversal instructions when accessing these registers Software running in LE mode can use the normal load and store instructions There is one set of registers for the PCI 32 bit and one set for the PCI64 bit The relative address or register number of these registers is specified in the PCILx_CFGADDR Configuration Address Two registers PCIC1_PSBAR and PCIC1_PPBAR can be accessed and configured by the CPU or the PCI64 bus through configuration cycles Table 9 2 Standard PCI Configuration Registers 00 to 01 PCICx_VENDID Vendor ID Register 1 PCICx_DEVID PCI Device ID Register 02 to 03 04 to 05 PCICx_CMD PCICx_STATUS 9 65 1 9 63 Command Register Status Register PCICx_REVID 06 to 07 08 PCICx_CLS 9 75 Revision ID 9 74 PCI base class subclass standard programming interface PCICx_CACHELS
122. d PCILx_CFGDATA registers The configuration target address is first written into PCILx_CFGADDR and then an access is made to PCILx_CFGDATA to generate a configuration transfer Each PCI bridge has a separate set of these registers When each decodes an access to its PCILx_CFGDATA register it performs different operations depending on the values stored in PCILx_CFGADDR 7 4 CPC710 User s Manual Table 7 4 PCI Configuration Cycle Matrix CONFIG_ADDRESS Register Fields Action Device Function Register y 2 S F Configuration not enabled Returns 0 s on loads and ignores write data Invalid Bus in PCILx_CFGADDR BUS lt 7 PCIGx_ BUSNO Returns 1 s on loads and ignores store data No access made to PCI Bus Access to PCI Bridge configuration space Read Write to PCI Bridge configuration regis ters Configuration access to device on PCI Bus TYPE 0 configuration cycle on PCI bus BUS PCICx_BUSNO Not supported TYPE 0 configuration cycle with no IDSELs on Returns 1s on loads and ignores store data Special cycle command Special cycle command issued to PCI Bus BUS gt E l PCICx_BUSNO Configuration access to bridge on PCI Bus BUS lt TYPE 1 configuration cycle on PCI Bus PCICx_SUBNO Den SE Invalid bus PCILx_CFGADDR GE D x x Returns 1s on loads and ignores store data PCICx_SUBNO No access made to PCI Bus 1 Firmware must insure the SUBNO register in the PCI header is greater than or
123. d the 60x logic performs the same steps except that the 60x logic internally sends a DMA Transfer Read command to the DMA Controller and waits for a dummy read data response The dummy read data is then placed on the processor bus to complete the eciwx transfer on the processor bus The internal flag for special handling of TLBSYNC is set during the eciwx address bus tenure on the processor bus After the DMA Controller receives the DMA Transfer command it issues a Load Pointer command on the internal command bus to the appropriate PCI bus bridge logic unit This transfers the address in DMA0_XPARx to the PCI bus bridge pointer register The DMA Controller then issues a series of Blit commands or internal Elementary Commands from the DMA Controller to the PCI logic to the same PCI bus bridge logic unit that transfers the data The first Blit command contains the memory address stored in the DMAO_XTAR x register The PCI bus bridge logic receives the Blit commands and then executes the transfer For Blit Reads the DMA Controller first determines whether the read from memory requires a snoop transaction If the read is coherent the controller issues a snoop command to the 60x logic If the snoop fails the controller retries the snoop until it passes Once the snoop passes a Blit Read command is transmitted to the PCI bus bridge logic The PCI Bridge logic executes the command and then increments the value in its pointer register by the size of the t
124. d in registers PCILx_TPMDLK PCILx_BPMDLK PCILx_TIODLK PCILx_BIODLK will generate a SYS_ARTRY signal on the CPU bus For read operations that fall in the deadlock avoidance window the CPC710 takes the CPU request and then generates the SYS_ARTRY and performs a delayed read For write operations the first write in the address window is not retried if the PCI bus is busy If the deadlock avoidance circuit is not programmed the SYS_ARTRY will not appear This is what will happen if the PCI bus agent is smart enough to buffer its transactions in the case that resources are not free and allowing for a PCI retry operation to occur If system PCI agents support this type of operation then use of the CPC710 s internal deadlock avoidance is not necessary For monitoring purposes the DLK signal can be enabled PCILx_DLKCTRL 6 1 and observed Sequence of operation with the Deadlock avoidance internal circuit 1 CPC710 detects that the CPU to PCI access is in the range of addresses defined in registers 2 CPU to PCI access is flushed 3 SYS_ARTRY is generated on the 60X bus by the CPC710 4 Execute PCI master Read Write access to System Memory with Snoop 5 End of the PCI master operation 6 CPU access to the PCI 4 14 CPC710 User s Manual 4 6 2 Deadlock Avoidance Operation with External Logic This mode of operation requires the use of external logic to generate the CPC710 input NODLK The CPC710 will generate the output DLK for a C
125. d is 2 way interleaved to allow the memory to burst data on every CPU bus cycle at 133 MHz 1 1 2 1 after initial latency using only one memory address bus To handle critical word load individual control of the LSB column address bits is required for the DIMM pair This interleaved implementation allows the CPC710 s memory controller to run all the memory control except SDCKE and SDCS_ and address signals at half the System Frequency The Data signals between the Multiplexors and the SDRAM also run at half the 60x bus frequency This is a main advantage for the board designer allowing Time Of Fly for those signals up to 1 system cycle The CPC710 133 supports buffered unbuffered and Registered SDRAM DIMMs The controller supports up to six dual DIMMs banks of interleaved 72 bit memory 64 bit Data 8 bit ECC To reduce pin count the controller requires a Texas Instruments Tl ALVCH162268 MUX or alternative IDT MUX to externally multiplex the 144 bit data to 72 bits for device input Programmable parameters allow a variety of memory organizations and timings ECC protection is provided for all 64 bits of the data bus detecting and correcting single and double bit errors Programmable parameters allow for a variety of memory organizations SDRAM Subsystem Overview on page 6 6 and different kind of SDRAM organizations can be mixed The SDRAM must comply with the following requirements compatible with the PC133 Specification 1
126. dress tenure cannot be negated by SYS_ARTRY from a subsequent address tenure 4 2 3 6 High Impedance After SYS_TEA Masters and slaves must execute all data bus signals as high impedance within two bus clocks from SYS_TEA assertion 4 2 3 7 SYS _DRTRY Assertion Slaves are not allowed to drive SYS_DRTRY active The CPC710 arbiter does not receive SYS_DRTRY 4 2 3 8 Slave Data Bus Determination To determine whether the data bus is currently in use by a previous address tenure a slave must sample DBB from its master during the TS active cycle If DBB is active the slave must wait for DBB to go inactive in a one level pipeline mode for at least one cycle before providing read data or accepting write data 4 2 3 9 SYS L2 Hit Assertion For the CPC710 to determine whether an addressing error has occurred all slaves on the 60x bus must assert SYS_L2_ HIT when selected by an address on the 60x bus Warning The SYS_L2_HIT signal is subject to timing constraints 60x Interface 4 7 4 2 4 Bus Enhancements 4 2 4 1 DBB not Required by Masters Masters do not require DBB The arbiter does not grant the data bus to a requesting master if the bus is currently in use The CPC710 does not drive DBB since it acts as an address only bus master 4 2 4 2 Half Cycle Precharge not Required on SYS TA The CPC710 can be programmed so the precharge of SYS_TA is not required This requires all slaves to initially drive SYS_TA active or inactive immedi
127. e E El ZI ede E Z Data E 2 Data 5 Memory Buffers Memory amp Buffers CPC710 Clocked at System Bus Speed Clocked at PCI32 Bus Speed 33 MHz Clocked at PCI64 Bus Speed 33 66 MHz Dual Clocked Logic Figure 1 2 Component Block Diagram CPC710 User s Manual 60x Bus 60x Bus Interface Logic Y m gt 1 0 lt v LE BE LE Byte Swap Byte Swap f gt y 64 Bytes wi System Bus Clock A A A A A 66 MHz CLK PCI64 Bus A 4 Y 64 Bytes Memory Bus System Bus Clock y lt k VO A S A 64 Bytes W A p gt 64 Bytes a y vo gt 64 Bytes PCI64 Bridge Logic A dt 64 Bytes PCI32 Bridge Logic 32 Bytes SO pt 64 Bytes Command Queue y pe E WO Rotating priority 64 Bytes W A new arbitration A after each 32 Bytes P Cache line 32 Bytes Memory Control Logic A 33 MHz CLK A PCI32 Bus System Bus Clock gt DMA Controller Figure 1 3 Internal Buffering and Data Flow Overview 1 6 CPC710 User s Manual Chapter 2 Addressing Model 2 1 Address Maps The CPC710 address spaces can be
128. e 10 5 Write One Byte to Memory from CPU Read Modify Write TLL SLU ULL q o0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4d 41 42 43 44 45 Data 3 1 Ou q Figure 10 7 Write of One Byte to the Boot Flash FFF05555 FFFOZAAA FHFO5555 FFFO2000 1 1 1 1 1 1 CLK100MHz SYS_ADDR SYS_TSIZ SYS_TS SYS_TA SYS_DATA PCI_AD 10 2 CPU Access to the Boot ROM Ne ee ET TE sa D ne u GER Figure 10 6 Read of One Byte from the Boot ROM i Code 1 aes SES E EE A Ei IELE Y MEN Write of the Data in the flagh after the 4th WE 20 E O Goa OOo a oa EE Code 1 31 0 XADR_LAT 31 0 XADR_LAT XCVR_RD XCVR_RD SYS_TS SYS_TA SYS_DATA PCI_AD FLASH_OE CLK100MHz SYS_ADDR FLASH_WE SYS_TSIZ CPC710 User s Manual 10 6 10 3 PCI64 External Master Accessing SDRAM Memory CLK100MHz LILLE UU MDATA SDRAM_DH SDRAM_DL MADDR RAS CAS WE
129. e address in system memory e PCI64 Configuration by external PCI Agent This flexible FPHB mode allows the configuration by an external PCI agent of some of the CPC710 registers of the PCI 64 bus bridge such as the PCIC1_PSBAR PCIC1_PPBAR PCIC1_ITADDSET and PCIC1_INTRESET registers See Standard PCI Configuration Registers on page 9 6 System Memory Space PCI Space Memory or I O 4GB Space is selected by Extended bit 7 of PCILx_PSSIZE System Memory Programmable Optional E Registers N PCILx_BARPP PCI Memory PCILx_PPSIZE or System PCI I O PCIC1_PPBAR PCI64 Memory paws ee lt lt PCILO_PPBAR PCI32 Y PCILx_BARPS or PCI I O PCIC1_PSBAR PCI64 PCICO_PSBAR PCI32 PCI Memory PCILx_PSSIZE lt Figure 2 7 PCI to System Addressing Model FPHB Mode 2 8 CPC710 User s Manual 2 3 3 CHRP Address Map The PCI64 Host Bridge and the PPCI32 Host Bridge differs only by one feature Only the PCI64 can access Alias and Hole Memory space I O Space Memory Space System Control Area Peripheral WO Space 1 Peripheral UO Space 0 Peripheral Memory 1 16 MB Alias Memory Space 16 MB Alias Peripheral Memory 0 System Memory 16 MB processor hole System Memory Lane den 192 DOLE EE Figure 2 8 CHRP Address Ma
130. e for Size Bank defined in SDRAMO_MCER 16 25 bit field 8 1 Normal mode 4 MB to 1GB available 0 Extended mode 4 MB to 4GB available 9 Reserved Must be Left to 0 10 Reserved Must be set to 1 for SDRAM Chip Select duplicated Mode 1 11 1 SDCS_ 0 3 signals are using SDCS_ 4 7 outputs by Multiplexing Chip Select duplicated Mode 2 12 1 SDCS_ 0 3 signals are using SDCS_ 8 11 outputs by Multiplexing 13 Reserved Must be set to 0 First Multiplexing Control of SDRAM Signals SDQM 14 1 SDQM signals are using SDRAS1_ SDCAS1_ and WE1_ outputs by Multiplexing Register Summary 9 117 SDRAMO_MCCR Memory Controller Control Register Bit s Description Second Multiplexing Control of SDRAM Signals SDQM i 1 SDQM signals are using PCG_ARB outputs by Multiplexing SDRAM Type 00 Standard modules SDRAM 16 17 01 Registred DIMMs SDRAM mode 2 not available for future use 10 Registred DIMMs SDRAM mode 1 11 Reserved unpredictable result 18 Reserved Must be left to 0 Registered DIMMs extra clock cycle for CAS 3 1 Following signals are shifted by one Clock cycle 19 MUX_CLKEN1B_ MUX_CLKEN2B MUX_SEL_ 20 Reserved Must be set to 1 Registered DIMMs Write extra cycle j 1 Data to be written to the SDRAM Memory is maintained one more cycle Registered DIMMs extra clock cycle for CAS 2 1 Following signals are internal shifted by one Clock cycle SDCKE and SDCS signals must be external shifted by one Clock cycle MU
131. e low order address bits to create a BE address equivalent The processors do not issue unaligned LE transfers on the bus Instead they take an alignment interrupt However the PowerPC 604 processor does issue unaligned LE transfers as long as they do not cross word boundaries The following table describes the addresses generated by the processor for LE transfers 4 1 1 2 Endian Behavior PREP architecture requires data to be stored in the same Endian mode as the processor Therefore the CPC710 implements logic to unmunge the address and byte swap the data bus as it comes from the processor before sending it to memory or to the PCI bridges See CPC710 Endian Logic shown previously Table 4 1 Processor Little Endian Address Modification Transfer Size bytes Processor s Internally Generated LE Effective Address 1 2 gl 4 52 6 72 8 SS Resulting Processor Big endian Address 29 31 0 7 6 53 4 0 1 6 53 43 2 5 4 3 4 4 3 2 18 0 5 2 19 08 6 1 0 7 0 1 The PowerPC 604 does not support 3 byte transfers in LE mode however these transfer sizes will result from an unaligned 4 byte access to an odd address These transfer sizes are not supported by any of the processors 3 These cells apply only to the PowerPC 604 which performs unaligned LE transfers N 4 4 CPC710 User s Manual Because the CPC710 cannot determine the processor s Endian state software must write to the Ar
132. eaeeeeaeeeeeeseeeeeseneeeeaes 4 5 Data Gathering Algorithm oo eee eee e cece eeenee cece cece eeneeeeaeeseaeeesaeeseeaeesaeeseaeeseaeesesneeseaeeseeeeneees 4 11 Deadlock avoidance circuits in the CC 10 4 14 Power Wp SCGUENCE eege Ee EE Ee EE eege eegen ESA 5 1 PLE RESO EE 5 3 Arbitration to support of 4 Way Multiprocessing with the CPC710 0 eee eeceeeeeeeeneeeeneeeeneees 5 5 DIMM Bank Configuration ooooncconccnnoccconcncnonncnnononnnncnnnn ccoo nn nn nn nan nn nan nn rana rr nan nr nn nn ran n nr nn arena nnnnn nenes 6 2 Programming with Single Bank DIMMS ooooooocccnocccncocccnoncnonnnononccnnonononcn nan n cnn no nn nn nn nn rar nnrnnn cnn 6 3 Programming with Dual Bank DIMMS 0oooocccocccnoccccooncnancnononnnnnn conan conan nn ran rca n nr non nc n nn rnr nn nn 6 3 SDRAM Interface Block Diagram 6 6 SDRAM Commands issued by the CPC710 ioccccccccccnooncnannnononcnnonnnnnnnnnan nn nan nn nnnnnnnn anna aran nnnrnnnnnnns 6 9 Use of the CKE signal for SDRAM Control 6 9 PCI Memory Read State Diagram ooooonccconoccconcccnonncnnononancnnnnnncnnn cnn nn cnn nn rnn nn nana r rre n nn nn rra 7 3 PCI Memory Write State Diagram ooooocccinncccnocccnooncnonncnnrnnnnonnnnon nn nn nono nn ran nn nan n nr anar n nr rr cnn cnn 7 4 PCI Address Data Bus for Type 0 Configuration Cycles oooococncccnnncccoocccnonnnannonancnnno conan nono ncnnnnr 7 6 CPC710 Register Address Map a E a aaa ea e a arar eaa none rn nn nn aaie ea iE ais 9 2 PCIContig r
133. ed Flash Write Disable 7 0 Indicates that writes are allowed to extended FLASH space 1 Writes to extended FLASH space are inhibited Resource ID 8 11 This 4 bit field contains the Resource ID that device uses to determine whether or not it is the target of a DMA transfer operation initiated by a ecowx or eciwx operation The Resource ID is encoded on the SYS_TBST and SYS_TSIZ 0 2 signals during this cycle Time Base Enable 12 0 The Time Base Enable signal to the CPU is deactivated CPU real time clocks halted 1 The Time Base Enable signal SYS_TBE to the CPU is activated CPU real time clocks enabled 13 14 Reserved 15 Reserved R W Register Summary 9 43 CPCO_UCTL Universal System Control Bit s Description Kill Snoop Operation Must set to 0 for the PowerPC 750 16 O The CPC710 issues Kill address only transaction types for full cache line invalidates 1 The CPC710 issues Flush address only transaction type for full cache line invalidates Workaround of the 604 errata Kill snoop bug 17 23 Reserved CPC710 EC LEVEL Read only Bit 24 Always at one Bits 25 to 27 Main Engineering changes Bits 28 to 31 Sub Engineering changes 24 31 9 44 b 1000 0000 x 80 for CPC710_100 b 1001 0000 x 90 for CPC710_100 b 1010 0000 x AO for CPC710_133 CPC710 User s Manual DMAO_GSCRx DMA Global Control Register Reset Value x 0000 0000 Address Us
134. eeeeeneeseaeeseaeeeeseeeeeeeeeeaeeeeaes 4 4 Processor Little Endian Address Unmunge Equations ooooocccnoccccoccccoccccnonnnnnn conan conan nnnno nora ncnnncnnnno 4 5 Non Burst Transactions SYS_TBST 21 4 8 Burst Transactions SYS_TBST DI 4 9 Transter Types Page 1 Of 2 a ied vast e A ae ee eee ee ie 4 9 CPU Initiated Transactions Page 1 Of 5 cccscceeeeenceeeeseceeeeeeaeeeeeeeaeeeeesaeeseeeeeeeeseeeeeesneeeeeees 4 15 PLL Inputs Control Signal Gettmg narco non nn nan nn cnn rra nn rn nr n rn 5 2 Memory Performance for Cache Line Operations ECC Active oooooocccconncccccnnocccccnonccccnnnnncnnonnncnnnns 6 1 SDRAM COMMONS Saa 6 3 External MUX Controller for Memory Data ooooooonoccnnncccicoccnonncnnoncnnnnnononcnnnn cn nan nnnnnnncnn anna a nn nnn nn rancia 6 4 Memory Address Bit Definition for Non Row Column Addressing Dis 6 4 SDRAM subsystem SONAS 6 4 SDRAM DIMM Chip Select Connections Example ooooocoocccnocccnocnccooncnnrnnnnnn conan nn nnn coran nn cnn cra nnnnn nn 6 4 Supported DIMMS ET 6 7 SDRAM Input Signal Frequencies oocooocccnocccnnoncnonnncnnncnnnnnnnnn nono conan nn cnn nn nano rra nr nn nn nr errar nn 6 8 System Address MappiNOruiciiasc aia 6 10 SDRAM Address Mapping seri iia EE Ee 6 10 SDRAM Control Register Programmimg 6 11 SDRAMO_MCERx to Program Functions of DiMMs conan cn nna no nancnnnnnnnnns 6 14 SDRAMO_MCERx Register Initialization nc nnn nc nnn cn rnn nn 6 15 ECC Check Bit Single Bit Err
135. ehave normally Writes to this register are restricted in that software cannot set any bit in this register only reset Additionally to reset a bit software must write a 1 to the corresponding bit location For example to reset only bit 14 software must write 0100 0000 0000 0000 b to this register Reset Value x0280 Address x 06 Access Type Read Write D 3 SZ D 3 Oo o E BS e ZS 2 e Q EG lt 1 d 2 2 lt O x 83 3 2 SS 2 A a sic ere E gt t E O o o E ZOO ou o o B L gt a 2 o P H zs Ke El S e S 8 D L Do 2 ZK Geo o aft Reserved A A AAA EL LA y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Description Parity Error 15 0 No Error 1 PCI Bridge has detected a parity error bit set even if parity checking is disabled Signaled System Error P G_SERR 14 0 No Error 1 PCI Bridge has asserted SERR due to an address parity error Signaled Master Abort 13 0 No Error 1 PCI Bridge has issued a master abort Received Target Abort Master 12 0 No Error 1 PCI Bridge has detected a target abort for one of its transactions Signaled Target Abort Slave 11 0 No Error 1 PCI Bridge as a slave has issued a target abort DevSel Timing Read Only 10 9 01 PCI Bridge responds with Medium timing on P G_DEVSEL signal Register Summary 9 75 PCICx_STATUS PCI Status Bit s Description Data Parity Detected
136. eii 8 1 DMA Transfer ROOS O S a A a a aa di 8 2 DMA Transfer Status Cache Line Descriptor for Chained DMA S 0 0 eee eecceeeseeeneeeeeeeeeseeeeeneeteaeeeeaeeeeanees 8 3 DMA Procedure td 8 4 Special Boundary Conditions ooooconocccnoccccnoncnannnonononnno nono nc non conan cnn n rra cnn rn nn rra n cnn 8 5 Chapter 9 Register Summary canica Seed ENEE 9 1 e ERR ee EE 9 1 Standard PCI Configuration Space oo ee eee cesceeeseeeeeeeeeeeeeeeneeseaeeeeaeeseaeeesaaeeseaeessaeeesaeessaeeseeeeseeaeeseaeeesneeeeeees 9 5 Standard PCI Configuration Registers A 9 6 Specific PCI Host Bridge Registers 0 0 eessseesseceenecesneeeeneeseneeeseeeceenersenerssneneeaeeesanecsanessanesseneeenneteeeeeeseners 9 8 Alphabetical List of Registers 3 tegt eieiei 9 9 Chip Coni Ol ROHS OS eli sec tbel ah eee a EE EE AE 9 10 E Eer VR RE 9 10 E E ER 9 13 CRG OPAV O EE EE 9 15 CRCO ERR arica better esata 9 17 GPGO GPDIR Ee tit halla oie an ee id oie la ee lid oie las Ballin 9 19 CPGOSGPIN neat eee ete el Ste teh Sale ate Ste seh Slat Mate Seat wale Sl A Slat 9 20 CGO GPO WS EE 9 21 CRCGOMASA eet dene oaths Sevens aha otitis teeta e Deve EE 9 22 CPGOSPGIBAR gedd O di 9 23 E E Eed E 9 24 CPOO EE 9 25 CRCOURGGHIR ti e sitet lee do 9 26 EPGOUPIDA costat e o Balla hs alates Sallie o Nailed loo iO e Malling 9 29 E NET 9 30 CPRGEOGRGBAN Isis sl el hak peel llo el o o seek bidet bay antl O led ioe Lab aad 9 31 GRC ORS UR gene ta id ee 9 32 CP GOR TBR EE 9 33 E EE 9
137. equal to the PCICx_BUSNO register in the PCI header Unpredictable results can occur if this is not true 2 The PCI Bridge performs a compare of the BUS NUMBER field in the PCILx_CFGADDR register and the BUS NUMBER field in the bridge s 256 byte PCI header 3 The PCI Bridge performs a compare of the BUS NUMBER field in the PCILx_CFGADDR register and the SUBORDINATE BUS NUMBER field in the bridge s 256 byte PCI header If there is no response to a configuration cycle no DEVSEL detected the CPC710 Master Aborts the cycle sets the Master Abort bit in the PCI Status register and completes the processor cycle normally by returning all ones on reads and ignoring data on writes PCI Bridges 7 5 7 4 3 1 Type 0 Configuration Cycles During a TYPE 0 configuration cycles the CPC710 provides on the AD 31 11 lines the IDSEL of the device to be configured on the PCI32 or PCI64 bus as described in the PCI 2 1 specification 31 30 24 23 1615 1110 87 210 PCILx_CFGADDR Register E Reserved Bus Number Device Function Register No 0 0 Decoded in the CPC710 PCI Addr Data Bus Only One 1 Function Register No 0 0 in configuration phase 31 11 10 0 Device 1 000000000000000000001 Device 2 000000000000000000010 PCI Addr Data Bus Device 3 000000000000000000100 Et icn Figure 7 3 PCI Address Data Bus for Type 0 Configuration Cycles 7 4 3 2 Type 1 Configuration Cycles For Ty
138. er x FF1C 0020 Privileged x FF1E 0020 Access Type User Read Only Privileged Read Write x Q 2 jo 2 Q Q g lt 5 UI 2 y 2a 5 se Es Ka GE 2 o s a Dee E SS ZS S se 855885 2 25 2 Reserved Number of DMA Transfer Loops to Do ee ee yyy y y Y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description DMA Transfer Enable 00 Reset DMA Controller to default power up mode 0 1 10 DMA Controller chained mode suspended The Chained mode is back after writing 11 11 DMA Controller is enabled 2 Reserved R W Interrupt Enable When set generates an interrupt at the completion of a DMA transfer 3 0 IT2 disabled 1 IT2 enabled Interrupt Status 0 End of DMA transfer interrupt IT2 not asserted 4 1 End of DMA transfer interrupt IT2 asserted Software must write a 0 to Reset the IT2 Interrupt 5 Reserved R W Direction for DMA 6 0 PCI to MEMORY 1 MEMORY to PCI Deadlock Avoidance with DMA Write to PCI 0 Disabled 7 1 Enabled Set this bit to 1 to avoid bus hangs on PCI interface 8 15 Reserved RO Register Summary 9 45 DMAO_GSCRx DMA Global Control Register Bit s Description Number of DMA Transfer Loops to Do The Data Byte length transferred in a Loop is defined by bit 3 15 of the DMAO_XSCRx register 16 31 If not equal to 0 these bits specify the number of loops to do During an Extended DMA these bits contain the number of loops remaining If
139. eset for Fourth Processor 9 32 Reserved D 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Reset For First Processor 0 0 SYS_HRESETO signal is active 1 SYS_HRESETO signal is inactive Reset For Second Processor 1 0 SYS_HRESET1 signal is active de SYS_HRESET1 signal is inactive Reset of the internal PCI 32 Bus Bridge of the CPC710 2 0 Reset active 1 Reset inactive Reset of the internal PCI64 Bus Bridge of the CPC710 3 0 Reset active 1 Reset inactive Reset For Third Processor 4 0 SYS_HRESET2 signal is active i SYS_HRESET2 signal is inactive Reset For Fourth Processor 5 0 SYS_HRESETS signal is active de SYS_HRESETS signal is inactive 6 31 Reserved CPC710 User s Manual CPCO_RTBR Refresh Time Base Register This register permit to control timers clocked from the PCI32 clock Reset Value x 8022 4470 Address x FFOO 0020 Access Type Read Write Bit s Description 0 9 Time Base for DRAM refresh 10 15 Time Base for Soft Reset Controled by CPCO_SRST Register 16 19 Time Base for Software Power On Reset Controled by CPCO_SPOR Register 20 23 Time Base for Bus Timeout 24 27 Time Base for Sdram Initialisation Phase 28 31 Reserved Programming example The times shown below are obtained with the PCI 32 clock at 33MHz with the register CPCO_RTBR 0 31 set at 32 h80224470 With other PCI32 frequency
140. ess in the Deadlock avoidance logic circuit 0 Modification not effective Processor ID and Deadlock avoidance circuit improvement recommended value is 0 30 0 Processor ID is taken into account in the DEADLOCK avoidance logic circuit 1 Modification not effective MEMREQ MEMACK and Deadlock avoidance circuit improvement recommended value is 0 31 0 The Deadlock avoidance logic using MEMREQ MEMACK and the Deadlock avoidance logic using DLK NODLK 9 94 are masked 1 Modification not effective CPC710 User s Manual This register exists on PCI32 and PCI64 PCILx_DLKDEV Deadlock Device Register Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8250 Access Type Read Write Deadlock device D 4 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Deadlock Device The Bit n corresponds to the PCI Device n During a PCI CONFIG access the deadlock management is activated for the selected PCI devices This operating mode is possible only if the bit 16 of PCILx_DLKCTRL is set to 1 see PCILx_DLKDEV on page 9 95 Example of coding 0 31 x00000000 No potential deadlock on the PCI configuration space x00000002 device 2 is potentially in deadlock on the PCI CONFIG access x00000004 device 3 is potentially in deadlock on the PCI CONFIG access x00000008 device 4 is potentially in deadlock on the PCI CONFIG access x00000006 de
141. essor Synchronization Bit 0 lt Multi processor Synchronization Bit 1 lt Multi processor First Access Bit Bit s Description 0 Multi processor Synchronization Bit 0 Used for communication between processors at IPL time 1 Multi processor Synchronization Bit 1 used for communication between processors at IPL time 2 30 Reserved Multi processor First Access Bit Read Only Set after read 31 0 Initial power on value Indicates first read of this register 1 Indicates that this register has been read at least once previously 9 22 CPC710 User s Manual CPCO_PCIBAR PCI Base Address Register This register is written by software to indicate to the PCI bridge where its register space is located in the 4 GB system addressing space There are no restrictions placed on the value of this register other than it must not overlap other extents defined for the system Reset Value x 0000 0000 Address x FF20 0018 Access Type Read Write Upper Bits of 1MB Address Bridge Register Space Reserved Y vy Y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 11 Upper Bits of 1 MB Address for Bridge Register Space 12 31 Reserved Assumed to be X 0 0000 Note The start address is assumed to be on a 1 MB boundary Register Summary 9 23 CPCO_PCICNFR Connectivity Configuration Register CPCO_PCICNFR sup
142. ft Reset Control for ARB Level 1 1 0 Writing 0 to this bit has no effect 1 Writing 1 to this bit will initiate a pulse on the SYS_SRESET1 signal Soft Reset Control for ARB Level 2 2 0 Writing 0 to this bit has no effect 1 Writing 1 to this bit will initiate a pulse on the SYS_SRESET2 signal Soft Reset Control for ARB Level 3 3 0 Writing 0 to this bit has no effect di Writing 1 to this bit will initiate a pulse on the SYS_SRESET3 signal 6 31 Reserved 9 42 CPC710 User s Manual CPCO_UCTL Universal System Control This register is used to enable address ranges to be decoded by the CPC710 and processor related oper ations Reset Value x 0008 00A0 Address x FFOO 1000 Access Type Read Write 2 O be C Lu 3 o a Q Q oO o 0 2 gg 2 2 Q 2 S ees S 2 3 ES g S 2 ZS 5 o S ke Q Coon D a O E o Ss 3 8 4 8 p 2 a O Dt 2 a 2 2 8370 8 22 Reserved BA o ResouceID Gs Reserved EC Level Yo vid y y yy y y y 0 11 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 T 0 3 Reserved Boot Flash Write Disable 4 0 Indicates that writes are allowed to Boot FLASH space 1 Writes to Boot FLASH space are inhibited and an error is generated DMA Transfer Address Space Enable 5 0 Accesses to DMA Address Range allowed 1 Accesses to DMA Address Range inhibited 6 Reserved R W Must be left to 0 Extend
143. g per arbitration level is enabled two outstanding addresses allowed Two level pipelining per arbitration level is enabled three outstanding addresses allowed One level pipeline enabled across both arbitration levels Selected this mode for operation with an L2 look aside controller Address Bus Parking Control Parking Disabled 2 3 Parking enabled for Arbitration level 0 only Parking enabled for Arbitration level 1 only MRU parking enabled Last arbitration level active is parked 64 Byte Cache Line 0 Arbiter will grant the address bus as normal 4 1 Arbiter will grant a second address bus tenure to the current arbitration level if the current arbitration level is again requesting the address bus and if first access is a burst transaction Normal round robin grant sequence will resume after each pair of grants Data Gather Control for CPU to PCI32 bus write Ox Not enabled 5 6 10 Enabled for accesses to incrementing addresses only 11 Enabled for accesses to incrementing and same addresses NOT RECOMMENDED 9 10 CPC710 User s Manual CPCO_ABCNTL 60X Arbiter Control Register Bit s Description Data Gather Control for CPU to PCI64 bus write Ox Not enabled 7 8 10 Enabled for accesses to incrementing addresses only 11 Enabled for accesses to incrementing and same addresses NOT RECOMMENDED Endian Mode of the PowerPC CPU 9 0 60x logic interprets data from 60x in Big Endian mode 1 60x lo
144. gic for execution using the translation specified by the following PCILx_PMBAR or PCILx_PIBAR registers 2 2 CPC710 User s Manual e PCILx_PIBAR on page 9 100 e PCILx_PMBAR on page 9 102 2 2 2 CHRP Mode PCI Memory and PCI I O address spaces are mapped into the 4GB System address space with the use of several programmable registers contained in Specific PCI Host Bridge Registers on page 9 8 These registers provide firmware a means to program PCI address spaces anywhere in memory as opposed to having fixed PCI address spaces and each PCI bridge inside the CPC710 contains a set of these registers 4GB Processor View ORO POSO OOO RRS 4GB 16MB POLLS LLOSA A TPM 16 MB Alias MSIZE Peripheral Memory Space ce Y amp _SMBAR BPM MA D Oo S UI TIO l Es g Peripheral UO Space Es cc Oo O ke S PIBAR SE PCI UO Space PCI MEMORY Space PCI MEMORY PCI I O 16 MB Figure 2 3 CPU to PCI Addressing Model CHRP Mode As the above Figure shows the CPC710 will monitor addresses on the processor bus and determine if a CPU address falls within the ranges specified by the PCILx_SMBAR PCILx_MSIZE or PCILx_SIBAR PCILx_IOSIZE registers e PCILx_MSIZE on page 9 98 e PCILx_SMBARP on page 9 113 Addressing Model 2 3 e PCILx_IOSIZE on page 9 97 e PCILx_SIBAR on page 9 112 If the
145. gic interprets data from 60x in Little Endian mode Eieio Retry Disable 10 0 The CPC710 will always SYS_ARTRY an EIEIO operation until every command in 60x queues has been dis patched to the logic units inside the CPC710 1 The CPC710 will not SYS_ARTRY an EIEIO operation DBG Park Control O DBG signals are not parked when bus is idle KR 1 DBG signals are parked when bus is idle mode to use for 0 wait state L2 look aside Bit 13 must be set to zero or this bit is ignored Disable ARTRY and SHD Signals Pre Charge 12 0 These signals are precharged by CPC710 1 These signals are not precharged by CPC710 Activate TA Signal Pre charge 13 0 These signals are precharged by CPC710 1 These signals are not precharged by CPC710 CPU Bus Hang Correction 0 No correction same as DD2 14 1 Correction of DD2 errata 11 is enabled The time base used is the one defined for the SDRAM refresh If a BR BG pair remains active during the time defined by the time base then all input BR are masked during one CPU cycle such that an arbitration can be done and thus ensure that the CPC710 can take ownership of the 60x bus and perform any pending snoop cycles Parking Control If MRU parking mode is enabled bits 2 3 set to b11 this bit allows the 60X address bus to be parked on the last Ge requestor for faster snoop operation 0 CPC710 Parking disabled d CPC710 Parking enabled DBG Control 16 0 SYS_DBGO and SYS_DBG1 signals are driven separately 1 SYS_DBGO and
146. han that of the capacitor at frequencies where noise is expected Many applications have found that a resistor instead of a ferrite bead does a 5 2 CPC710 User s Manual better job of reducing jitter The resistor should be kept to a value lower than 10 Ohms Experimentation is the best way to determine the optimal filter design for a specific application FB Murata BLM31A700S or equivalent or resistor below 10 Q Digital Vdd yl VW YN PLL_VDDA to PLL Bypass via at board C 0 1 uF Clock 2 3 to 2 7 V HUT p to internal Ge GND Phase Charg vco piv ewu HO Detect Pump E e gt SYS_CLK 7 Buffer p PLL_LOCK lt PLL_RESET e o oy PLL_TUNE 5 0 TUNE S 0 PLL_RANGE 1 0 CPC710 133 Figure 5 2 PLL Reset The RESET signal serves two purposes First it holds the PLL in a reset state by forcing the VCO to operate at its minimum frequency Second it puts the PLL in bypass mode such that PLL Output will be buffered versions of Input SYS_ Clock RESET should be held active high during power on until all of the following condition are met 1 All PLL inputs are stable and at their final values 2 SYS_CLK is stable at or below the target frequency 3 Any gating in the feedback path is removed 4 VDDA and Vdd are at their final values Failure to hold the PLL in reset RESET high during power on may result in VCO run away In this mode output clocks a
147. hape for buffering issues SDCAS1 can be converted in a O Chip Data Mask SDDQM by setting bit 14 of the SDRAMO_MCCR register Signal Summary 11 3 Signal Name Description UO SDDQM Data Output Mask same shape signal available on I Os WEI SDRAS1 SDCAS1 or o G_ARB after setting bits 14 15 of SDRAMO_MCCR register MUX_OEA B Output Enable of Data to Port A or B O MUX_CLKEN1B Clock Enable of Data sent to the Memory two signals with same shape for buffering o MUX_CLKEN2B issues MUX_CLKENA1 Clock Enable of Data sent to the CPC710 On Clock A1 the first part of the data is O MUX_CLKENA2 stored in the external MUX controller and on clock A2 full transfer is done MUX_SEL Control the MUX circuit of the external MUX controller O PCI32 Interface PCI_CLK Main clock input for the PCI32 bit bridge maximum 33 MHz l P ADL31 00 32 bit Multiplexed Address Data A write operation is defined as the transfer of data 1 0 from the PCI bus master to a PCI slave device on the PCI Bus P_CBE3 0 Bus Command Byte Enable 1 0 P_DEVSEL Device Select 1 0 P FRAME Cycle Frame Driven by the current master to indicate the beginning and duration of 1 0 Es an access P_IRDY Initiator Ready 1 0 P LOCK Lock Used to establish maintain and release resource locks on PCI32 Reserved for future use Tying up this signal is recommended P MEMACK Memory Acknowledge Indicates that the CPC710 has flushed all CPU to PCI3
148. ic Byte accesses allowed WO Write Only Register Range that IBM Dual Bridge and Memory Controller responds to is programmable Register Summary 9 3 Table 9 1 System Registers List Address Name Use Page Notes x FFOO 1210 SDRAMO_MWPR Memory Write Protect Register x FFOO 1220 x FFOO 1230 SDRAMO_MESR SDRAMO_MEAR Memory Error Status Register Memory Error Address Register x FFOO 1300 x FFOO 1310 SDRAMO_MCERO SDRAMO_MCER1 Memory Configuration Extent Register O Memory Configuration Extent Register 1 x FF00 1320 x FF00 1330 SDRAMO_MCER2 SDRAMO_MCER3 Memory Configuration Extent Register 2 Memory Configuration Extent Register 3 x FFOO 1340 SDRAMO_MCER4 Memory Configuration Extent Register 4 Memory Configuration Extent Register 5 Xx FFOO 1350 SDRAMO_MCER5 x FF00 1360 Reserved Reserved x FF00 1370 x FFOO 1400 SDRAMO_SIORO SIO Register 0 DIMM PDs Reserved x FFOO 1410 x FFOO 1420 SDRAMO_SIOR1 x FFOO 1424 to x FFOO SIO Register 1 Planar DIMM CPU etc Reserved x FFOO 2000 to FF17 1FFF EFFE DMA Registers User Privilege Reserved x FF18 0000 to x FF1C 001F x FF1C 0020 DMA0_GSCRU Reserved Global Control Register user x FF1C 0030 x FF1C 0040 DMAO_XCLRU DMA0_XSCRU DMA Cache Line Increment Register
149. ignal Machine Check with SYS_TEA Stores Signal Machine Check with SYS_MCP0 1 If CPCO_PGCHP 26 1 Signal Machine Check with SYS_MCP0 1 Terminate CPU transaction normally Notes 1 A dummy 0 is returned for read operation For write data is ignored 60x Interface 4 19 4 20 CPC710 User s Manual Chapter 5 Initialization 5 1 CPC710 Power Up Sequence e time 100mS All PLL inputs are stable and at their final values See following recommended set ting for PLL _TUNE and PLL_RANGE input signals SYS_CLK is stable at or below the target frequency VDDA and Vdd supply are at their final values POWERGOOD input is de asserted Low for Reset PLL_RESET input is asserted active Low PCI clocks inputs PCI_CLK and PCG_CLK are stable at the target frequency e time 0 PLL_RESET input is de asserted inactive High PLL_LOCK output goes down up to the time that clock are locked to the PLL then is asserted active High indicating the PLL is locked e time 500 us minimum POWERGOOD input is asserted High HRESET output de asserted by the CPC710 High Bus transactions may begin Boot can begin Note 1 Chip reset is only controlled by the SYS_CLK SYS_CLK TUU UU UU UU ON OU UU UU gt 100 mS PLL_RESET In AA T lock lt 500 uS 1 e gt 500 uS for PLL Lock PLL_LOCK Out POWERGOOD In SYS_HRESET Out Boot CPU
150. iiis nenien iee iaire iana nen nan rn nene T RR RR A anat aaeeea nene 6 14 igela elate O ET 6 15 Single Bit ECC Error General Cason aeiiae ra aeaa aapa eaaa nA aA VANERNE NAE E ERE TEEPA ENAERE ERE ASSE 6 16 Single Bit ECC Error Special Case rear arae aoea a aana ean oa E An EEA NA E EEEE EEE EEA E EEAS E EEEN ETERA ASEE 6 16 nyald Address Entre Tae eee O O 6 16 Double Dn ECC Error General Case coccccccccccccccccncconnnnnnnonnnnnononnnnnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnonnnonnnnnnnnnnnnnnninin 6 16 Do ble BIt EGG tele EI 6 17 Overlapping Memory Extents vicario crsiencslevsescecdscedeodivindcacaseeesscanteasachsseusacivecesaunseetralapiaasagustuatelenieinaees 6 17 AA ELLAS A O aaaea iiaiai a EAa 6 17 A O O O 6 18 Additionnal Information for Software oooonncnnccnnnccncoccnonnnnnoncnnnn conan nnnnn cn nan corno nn rana nro nn nn rra nena 6 19 Chapter 7 e RN EE 7 1 Address Maa 7 1 System Standard Configuration Registers A 7 1 system PHB Registers iii A ia 7 2 PGI Bus COM eee cane Se ee eee ee 7 2 PCI Master Memory Read Cycles AA 7 2 PCI Master Memory Write Cycles EE 7 3 Configuration Cycles a e edo Vel ges 7 4 Type 0Gonfigurati n Cycles tii aid 7 6 iv CPC710 User s Manual Type 1 Configuratio Cyc EE 7 6 PCI Performance EEN 7 6 PCI Master Error Hang sica E EA A A A E E 7 7 Chapter 8 DMA Controller coin iia 8 1 ItPOGUCTION tr A soap h Aaeed ices step nae ote 8 1 Mode of operation of the D MA eeh iii 8 1 starting the DMA
151. in other operating environ ments may vary THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document IBM Microelectronics Division 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 6351 The IBM home page can be found at http www ibm com The IBM Microelectronics Division home page can be found at http www ibm com chips ii CPC710 User s Manual Contents PD OUR TMS E xiii Chapter Ba ET 1 1 Est e he Meret sheets lali tas 1 1 60X BUS INEA atan ira A EE 1 1 Memory Controller ee 1 2 PGI 32 and PCl64 Bus Bridges EE 1 2 Chapter 2 Addressing Model coccion 2 1 Address Maps ia 2 1 CPU to PCI Addressing Model isiru iriaren aaaea iaae a i ia iaaa EE 2 2 PREP and FPHB dE 2 2 CHRP Mode se viccieceaheaixtielancnendeachan adhesin AE aia 2 3 Peripheral I O Address Translation eeescsssesesneeeseceseececeanecenersaeeseacecsanecanerseseeeeaeecsanessenesseneeeeanessaness 2 4 PCI to System MEM Ory eserine ran enean aa ad aa 2 5 PowerPC Reference Platform PREP Mode 2 6 PCI Master Address Operation 2 6 Translation Enabled in PREP Mode hia araa aaa aaa aa ara nene nen cren ataata eta iiaa 2 6 Translation Disabled in PREP Mode cirian arao aoaaa aa a aaa 2 7 Flexible PCI Host Bridge FPHB Mode r ra a raaa a aeaa aaa i a aa ea 2 8 GHRPAddr esssMap a i a a a aa a
152. ing PCI32 x0156 PCI64 x0156 example Address x 04 Access Type Read Write EI Q bal C LU ge Cc bal E E S 8 g 2 2 B D 2 2 ae fr 3032 30 Le 2 SS o a gt 63 E 8 gt oe 8 oO A CS Y UI D gt 3 2520 oe 5 oe e Sees SER E Sfe2e s F588 o ul 2 mg gt qu oa oo S ep 6 SS 2 OQ E et E O o Q 20 Soo e Sg S Reserved UK d a tS soau wu y yyy tee bedi 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Bit s Description 15 10 Reserved Fast Back to back Enable 0 Disabled 9 1 PCI Bridge issues fast back to back transfers without regard to which target is being addressed providing that the previous transaction was a write Note This bit should be set if all slaves on the PCI bus support this capability SERR Enable 8 0 PCI Bridge will not assert P G_SERR upon detecting an error 1 PCI bridge will assert P G_SERR for PCI address parity error 7 Add Wait States Read Only Always returns 0 Device does not support address data stepping PCI Bus Parity Enable 6 0 Device will disable all parity checking on the PCI bus 1 Device will detect and report parity errors on the PCI bus 5 VGA Palette Snoop Read Only Always returns 0 Device is not VGA compatible Memory Write amp Invalidate Command Enable 4 0 Device does not generate this type of cycle 32 byte transfers use the Memory Write command 1 Device generates this cycle as a master for any 32 byte transfer Register Summary 9 63 PCICx_CMD PCI Command
153. ion ii AA Re RE 4 7 Qualified SYS_DBG Equation ocooccnncccnconcnonnnnnonnnnonconon cn non nnnnn nn rnn nro n rra n nena rre nr nr n nine n nana 4 7 High Impedance After SYS_TEA ooocccccnocccnocccnonnononcnnnnnncnnn ccoo nc non nn nnn nn nan n rra nr anar n nn nn ran n rr nn arena nnnnn ne nnnnnnnns 4 7 SYS EN ASSCMION EE 4 7 Slave Data Bus Determination isie ee annei aeaiee a ea aeaaea naaa a ia oaa ieaiao aaeei 4 7 SYS L2 Ht AS Serion EE 4 7 B s Emhancements 2 25 a e a a a a a aa a aa a ee ened eel ta eae 4 8 DBB not Required e OAI TC 4 8 Half Cycle Precharge not Required on GyG TA 4 8 SYS_ARTRY_PREV in QDBG Equation Eliminated cccccccccceeeeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 4 8 60x Bus Transfer Types and Sizes EEN 4 8 Contents iii RER ln e HEET 4 10 SYNG and EIEIO NEE 4 11 Address Retry SYS ART RETTEN 4 12 Precharging SYS_ARTRY and SYS_SHD ooo cece ceneeeneeeeeeeeeeeeeseneeseaeeseaeeseaeessaeeseaeeseaeeeeeeeeeeaeeeeaes 4 12 SYS ERR EE e 4 12 Recommended SYS_ARTRY Procedure ccccceessscceeeeeessesnaeeeeeeeeessenaeeeeeeeesseseaseeeeeeesseesnaeeeeeeesseesaes 4 12 Deadlock ee le 4 13 Deadlock Avoidance Operation with Internal Logic ooonocconnnccinnccinoncnoncnnannnononnnnnnncnnn conan nn rar nnnnrn rra nn 4 14 Deadlock Avoidance Operation with External Logic oooonocccnonccinnccnnoconacccnnrncnnonnnnnn cn nan conan nn nn nnnnrnnrnnn nn 4 15 Error Handling for CPU Initiated Transa
154. is performed to determine whether the access is back to the same bridge If it is the PCI bridge will not respond to the PCI master The PCI bridge logic also forwards the access to system memory If this address does not match a memory configuration extent the memory controller logic returns an invalid address error thus ensuring that PCI masters do not access system facilities 2 3 1 2 Translation Enabled in PREP Mode If translation is enabled the PCI bridge logic translates addresses before presenting them to system memory as shown in the following figure However not all addresses are presented The translation is enabled by PCILx_PR 4 at address CPCO_PCIBAR Ox000F 7F20 2 6 CPC710 User s Manual System Memory Space Translation Upper Complement Address bit 0 PCI Memory Space 4GB Complement Upper 12 Address Bits No Translation Not Forwarded Upper 12 Complement Address Bits 2GB PCI Memory PCILx_MSIZE A PCILx_PMBAR 0 Figure 2 5 Address Translation Enabled in PREP Mode 2 3 1 3 Translation Disabled in PREP Mode If translation is disabled the PCI bridge does not translate addresses before presenting them to the system as shown in the following figure System Memory Space Direct mapping No Translation PCI Memory Space No Translation PCI
155. is register contains a value of x 00 9 60 CPC710 User s Manual Reset Value x 08 Address x 0C Access Type Read Only Cache Line Size b 00001000 D y 7 65 43 2710 Specifies the cache line size in units of 32 bit words PCICx_CACHELS Cache Line Size 7 0 The CPC710 always responds with x 08 for reads to indicate that device will always disconnect from any PCI master burst operation that crosses a 32 byte boundary Register Summary 9 61 PCICx_CLS PCI Class Register Reset Values x 060000 Address x 09 Access Type Read Only Base Class Code Sub Class Code Programming Interface A y y y y y 23 16 15 8 7 0 Bit s Description Classifies the type of function this device performs 23 16 The CPC710 always responds with x 06 for reads to indicate a Bridge device Specifically identifies a particular function of the Base Class Code register 15 8 The CPC710 always responds with x 00 for reads to indicate a HOST type of bridge device Defines a specific register level programming interface 7 0 The CPC710 always responds with x 00 for reads from this register 9 62 CPC710 User s Manual PCICx_CMD PCI Command This register provides control over PCI bridge behavior Reset Value PCI32 x 0000 PCI64 x 0000 programm
156. ister Specific System Registers x FFOO 1000 CPCO_UCTL Universal Control Register x FFOO 1010 x FF00 1020 CPCO_MPSR CPCO_SIOCO Multi Processor Semaphore Register System UO Control 0 x FFO00 1030 x FFOO 1040 CPCO_ABCNTL CPCO_SRST 60x Arbiter Control Register CPU Soft Reset Register x FFOO 1050 x FFOO 1060 CPCO_ERRC CPCO_SESR Error Control Register System Error Status Register x FFOO 1070 x FFOO 1080 CPCO_SEAR System Error Address Register Reserved x FFOO 1090 x FFOO 1100 CPCO_SIOC1 CPCO_PGCHP System I O Control 1 Chip program Register x FFOO 1110 x FFOO 1120 CPCO_RGBANO CPCO_RGBAN1 Free Register 0 Free Register 1 x FFOO 1130 x FFOO 1140 CPCO_GPDIR CPCO_GPIN GPIO Direction Register GPIO Input Register x FFOO 1150 x FFOO 1160 CPCO_GPOUT CPCO_ATAS GPIO Output Register Address Transfer Attribute for Snoop Reg X FFOO 1174 to xFFOO x FFOO 1170 11FP CPCO_AVDG Device Diagnostic Register Reserved x FFOO 1200 SDRAMO_MCCR Memory Controller Control Register ONOARON RO Read Only Register All bits can be read Only bits 4 31 can be written All bits can be read Only bits 0 3 can be written Four beat burst read operations allowed to this address space Single byte writes only Not decoded by system log
157. ited PCILx_PSWCR register Edited SDRAMO_MCCR register Revision Log R 1 R 2 CPC710 User s Manual Copyright International Business Machines Corporation 2002 All Rights Reserved IBM and the IBM logo are registered trademarks of the IBM Corporation All information contained in this document is subject to change without notice The products described in this document are NOT intended for use in implantation life support space nuclear or military applications where malfunction may result in injury or death to persons The informa tion contained in this document does not affect or change IBM product specifications or warran ties Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties All information contained in this document was obtained in specific environments and is presented as an illustration The results obtained in other operating environments may vary THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS In no event will IBM be liable for any damages arising directly or indirectly from any use of the information contained in this document IBM Microelectronics Division 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 6531 The IBM home page can be found at http www ibm com The IBM Microelectronics Division home page can be found at http www chips ibm com Document No SA14 2571
158. k EE d Reserved m lt PCI Bus Address Parity Detected lt G P_SERR Detected gt lt Invalid Memory Address lt PCI Bus Time out on IRDY Reserved Memory Error al o A ak o 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 1 Reserved PCI Bus Address Parity Detected 0 No Error 1 PCI Bridge detected address parity error SERR Detected 0 No Error 1 PCI Bridge detected G P_SERR during transaction Invalid Memory Address 0 No Error 1 PCI access occurred to invalid system memory address Reserved Memory Error 0 No Error 1 Double bit ECC error occurred during memory access Bus Time out 0 No Error 1 PCI Bridge detected bus time out no IRDY detected see PCICx_DISCNT on page 9 66 10 11 15 16 31 Reserved Arbitration Level Encoded arbitration level of PCI device when error occurred Reserved Register Summary 9 91 PCILx_CTRLW PHB Configuration Register This register is primarily used by software to program the CPC710 for a particular address translation mode Reset Value x 0200 0000 Address CPCO_PCIBAR x 000F 7FDO Access Type Read Write S O OH 2 O 2 oO a Ss a 2 o ZA 38 o 2 E c OS 288 2S gt Sr 2 a 3S a a e 8 S 2 2 250 o Go E o o 2 03 AE
159. l generate the normal ECC code when writing to memory and check ECC when reading 01 ECC check disabled Byte lane 0 routed to from ECC check field Data byte 0 forced to all zeros This mode is provided to allow software direct read write access to the ECC byte that is associated with every double word of data stored in memory and also provide a mechanism to verify the memory controller s ECC generation and checking logic In this mode byte lane 0 data MSB of a double word is written to the ECC byte instead of the normal ECC code byte Data byte 0 will be forced to all zeros For reads byte 0 will contain the byte stored in the ECC byte not the data at byte 0 ECC checking is not enabled for reads in this mode This mode also allows firmware write single bit and multi bit errors into memory to allow for ECC logic testing The device will still generate normal ECC codes when writing to memory 10 ECC check disabled Normal routing of data and normal ECC code generation The device will still generate normal ECC codes when writing to memory 11 Reserved Row Cycle Time for SDRAM Auto refresh tac Allows to fit the delay between the Refresh Command and the next Activation This delay has to be at least the tRCmin value specified in the SDRAM datasheet 000 5 bus cycles 001 6 bus cycles 010 7 bus cycles 5 7 011 8 bus cycles 100 9 bus cycles 101 10 bus cycles 110 11 bus cycles 111 12 bus cycles Selection of Bank Size Definition Select the encoding cod
160. lds see below but uses values depending of the PLL_RANGE1 input 1 The CPC710 use values programmed in FONT LATMAX and LADRMAX fields see below Boot Flash Size 000 2 0 MB The CPC710 initiates FLASH access for addresses x FFEO 0000 to xFFFF FFFF 1 3 001 1 0 MB The CPC710 initiates FLASH access for addresses x FFFO 0000 to x FFFF FFFF 011 0 5 MB The CPC710 initiates FLASH access for addresses x FFFO 0000 to FFF7 FFFF 111 Reserved 4 8 Reserved 9 11 Reserved These bit should be left to zero FCNT Flash output delay no action if bit 0 is left to 0 Number of system Clock cycles from signal XADR_LAT falling edge to signal FLASH_OE_ or FLASH_WE_ if write rising Edge 000 12 Clock cycles value used if bit O is left to O and PLL_RANGE1 0 19 14 001 13 Clock cycles 010 14 Clock cycles 011 15 Clock cycles 100 16 Clock cycles value used if bit 0 is left to O and PLL_RANGE1 1 Others 12 Clock cycles 15 Reserved 16 23 Reserved 9 38 CPC710 User s Manual CPCO_SIOCO System I O Control Bit s Description LATMAX no action if bit 0 is left to 0 Number of system Clock cycles needed for the CPC710 from driving FLASH address on the PCI32 bus to the resyn chronisation with the PCI32 Clock 24 25 00 5 Clock cycles value used if bit 0 is left to 0 and PLL_RANGE1 0 01 6 Clock cycles 10 7 Clock cycles value used if bit O is left to O and PLL_RA
161. mmon register that are associated with the deadlock avoidance logic Internal Deadlock avoidance circuit control setup PCILx_DLKCTRL PCILx_DLKDEV Internal Deadlock avoidance address window definition PCILx_TPMDLK PCILx_BPMDLK PCILx_TIODLK PCILx_BIODLK External Deadlock signal control common for PCI32 and PCI64 CPCO_PGCHP 24 should be set to O when using the internal deadlock logic 60x Interface 4 13 Ch ARTRY CPU 64 f Snoop i 3 Internal Deadlock External avoidance circuit P l Deadlock PCILx_DLKCTRL Wer Memory i management PCILx_DLKDEV AA circuit y EJ PCILx_TPMDLK PCILx_BPMDLK will be EE PCILx_TIODLK in removed PCILx_BIODLK future version E CPCO_PGCHP 24 PCI PCI PES ats bridge PAL q 21 2with ext NODLK F Deadlock Assist PCI32 Bus orak op p EMEMACK with ext PME gets P_MEMREQ Deadlock Assist gt l I Figure 4 4 Deadlock avoidance circuits in the CPC710 4 6 1 Deadlock Avoidance Operation with Internal Logic The Deadlock avoidance internal circuit is enabled when any one of the bits 0 1 or 16 of the Deadlock avoidance control register PCILx_DLKCTRL is set to 1 An access from the CPU to PCI that hits in the range of addresses defined as the deadlock avoidance window as programme
162. n address tenure to be retried Input When asserted in response to a CPC710 cache operation the CPC710 assumes the cache line is modified and or present in a CPU or L2 cache The CPC710 then retries the operation on the PCI bus and address tenure is not rerun until the device on the PCI bus reruns its transfer The pre charge logic is always signaled to initiate the pre charge sequence UO 1 0 SYS_SHD SYS_L2 HIT SYS_DBGO 3 SYS_DATA00 63 Shared Output Not applicable The CPC710 only pre charges the signal Input Instructs the pre charge logic to initiate a pre charge sequence L2 Hit Indicates an external slave has been addressed by the current master The CPC710 arbiter uses this signal to confirm positive selection of an address tenure on the 60x bus Warning This signal is subject to timing constraints Must be tie to Vpp 2 5V when unused Data Bus Grant Indicates the device associated with this signal may with the proper qualification assume mastership of the data bus Data Bus Byte 0 D O 7 DH 0 7 Byte 1 D 8 15 DH 8 15 Byte 2 D 16 23 DH 16 23 Byte 3 D 24 31 DH 24 31 Byte 4 D 32 39 DL 0 7 Byte 5 D 40 47 DL 8 15 Byte 6 D 48 55 DL 16 23 Byte 7 D 56 63 DL 24 31 1 0 VO SYS_DATAP0 7 SYS_TA Data Parity Bus Represents one bit of odd parity for each of the eight bytes of the data bus Odd parity means that an odd number of bits including the parit
163. nal on the PowerPC bus and so avoids locking the bus Reset Value Address x 0000 0000 CPCO_PCIBAR x 000F 8240 Access Type Read Write DLK out Reserved CPU to PCI Read Access Timeout Timeout select Retry Reserved Y y Deadlock Avoidance Options o CPU PCI Write CPU PCI Read m lt Timeout w MCP a lt PCI Mem space lt DLK out Config a lt PCI I O space De lt o lt s 18 19 20 21 22 23 24 25 26 sk N k oo ek A k al are 9 10 11 27 28 29 30 31 Bit s Description Deadlock checking on CPU Write Access to PCI 0 No Deadlock checking 1 Management of Potential Deadlock Deadlock checking on CPU Read Access to PCI 0 No Deadlock checking 1 Management of Potential Deadlock Timeout Enable for CPU to PCI Read access 0 Timeout activation with the value defined in bits 12 15 for the event root defined in bit 17 1 No timeout activation recommended value MCP Activation 0 Machine Check MCP is active on TIMEOUT 1 No MCP activation PCI MEMORY Space Selection 0 The PCILx_BPMDLK PCILx_TPMDLK space is valid for PCI MEMORY Access 1 The PCILx_BPMDLK PCILx_TPMDLK space is valid for PCI IO Access Register Summary 9 93 PCILx_DLKCTRL Deadlock Avoidance Control Register Bit s Description PCI IO Space Selection 5 0
164. nchronisation External Arbiter on PCI32 Enable Read only status bit 16 0 Internal arbiter is activated 1 Internal arbiter is deactivated Machine Check Detected Signal When ECC Single Bit Error 17 0 SYS_MCP signal not driven 12 SYS_MCP signal is driven only if CPCO_PGCHP 26 1 SYS_TEA Control Disable TRAS4 Active for SDRAM access only 18 0 trasmin 9 clock 1 trasmin 4 clock Register Summary 9 27 CPCO_PGCHP Chip Programmability Register Bit s Description Local Reset Enable 19 0 PCI64 Signal G_RESETOUT is not driven 1 If external arbiter on PCI64 bus then G_RESETOUT is driven DLK and NODLK Signal Control must be left as 0 S 0 DLK and NODLK are enabled PCI 64 REQ GNT 5 signal multiplexing with PCI 32 REQ GNT 4 control 21 1 G_REQ5 becomes P_REQ 4 G_GNT_5 becomes P_GNT_ 4 PCI 64 REQ GNT 6 signal multiplexing with PCI 32 REQ GNT 5 22 ale G_REQ 6 becomes P_REQ 5 G_GNT_6 becomes P_GNT_5 PCI 64 REQ GNT 7 signal multiplexing with PCI 32 REQ GNT 6 23 1 G_REQ 7 becomes P_REQ_6 G_GNT_7 becomes P_GNT_6 Auto Retry Enable must be left as 0 if internal Deadlock avoidance circuit is enabled 24 0 SYS_ARTRY is not always driven 1 SYS _ARTRY is always driven when the access is in Peripheral Memory or I O space with potential deadlock and CPC710 input NODLK 1 This setting permits use of external circuit control with DLK and NODLK PowerPC Processor Type see CPCO_ATAS on page 9 13 25
165. ndard 32 bit 33MHz PCI bus for standard and native I O The other PCI bridge supports a 64 bit 33 66MHz PCI bus for high data throughput applications such as graphics and high speed communications Who Should Use This Book This book is for system hardware and software developers The audience should understand embedded processor design embedded system design operating systems RISC processing and design for testability How to Use This Book This book contains the following chapters Contents Figures Tables Chapter 1 Overview Chapter 2 Addressing Model Chapter 8 DMA Controller Chapter 3 System I O Interface Chapter 4 60x Interface Chapter 5 Initialization Chapter 6 Memory Controller Chapter 7 PCI Bridges Chapter 8 DMA Controller Chapter 9 Register Summary Chapter 10 Timing Diagrams Chapter 11 Signal Summary Index Revision Log About This Book xiii Conventions and Notation The use of overbars for example RESET designates signals that are active low All signals are active high unless shown with an overbar Decimal hexadecimal and binary numbers are used throughout this document and are labeled as fol lows Decimal 1234 56 Hexadecimal x ABCD Binary b 0101 Example Hexa Binary A 1010 1011 1100 1101 1110 1111 In Little Endian mode bits and by
166. ne per master The arbiter continues to grant the address bus to a specific master until there are as many as three outstanding address tenures waiting for a data bus tenure to complete or begin Since the CPC710 supports two masters on the sys tem bus there can be as many as six address tenures on the 60x system bus that have not completed or begun a data bus tenure The arbiter stops granting the address bus to a particular master after its third address tenure The CPC710 can also drive a seventh address only tenure onto the bus to satisfy a DMA snoop operation 0 1 01 The arbiter maintains a one level pipeline per master The CPC710 stops granting the address bus to a master after it has two outstanding address tenures waiting for a data bus tenure to complete With two masters in the system there could be as many as four outstanding address tenures waiting for a data bus tenure to complete or begin and a fifth CPC710 generated address only tenure 00 Pipelining is completely disabled Even with two masters in the system there will only be one address tenure waiting for a data tenure to complete SE Implemented to accommodate slave devices like an L2 lookaside that can only support one level pipeline regardless of the number of masters on the 60x bus 4 2 3 Arbiter Requirements 4 2 3 1 Internal ABB All devices on the 60x bus must generate an internal ABB Because the arbiter may grant the address bus to a requesting de
167. ns Supports 60x bus configuration cycles 1 1 2 Memory Controller Supports 100 and 133 MHz SDRAM including PC 100 and PC133 and Registered SDRAM Up to 4GB 2 way interleaved SDRAM with ECC external MUX to reduce pin count Supports 16 64 128 and 256 Mb SDRAMs Programmable timing parameters Up to 6 dual bank DIMM Up to 4 banks supported for Multibanking SDRAM Access command queue with look ahead override option for CPU PCl s and DMA Access based on 32 byte cache line reload Three separate dual 32 byte load buffers PCI 32 PCI64 60x 1 1 3 PCI 32 and PCI64 Bus Bridges Two independent PCI bus bridges with parking PCI revision 2 1 compliant PCI32 3 3V Compliant with 5 0 V PCI signalling PCI64 3 3V Runs async logic to 60x and memory controller PCI64 arbitration can be disabled Dual 32 byte buffers in each PCI bus bridge Round robin PCI arbiter Coherency for memory access through DMA controller or through PCI master Noncontiguous byte enable transfer to memory The CPC710 is single load on all PCI signals 1 2 CPC710 User s Manual I E 8 Po L2 Cache L Cache L2Cache i L2 Cache Poy ha 8 Po Po b 4 fe oan i l PowerPC PowerPC PowerPC PowerPC 604 750L i D A d l 750CX 74
168. o enable further error logging the software writes zeros into the SDRAMO_MESR When more than one address error occurs before the SDRAMO_MESR clears only the first error is recorded No Single or Double Dn ECC errors are logged into the SDRAMO_MESR and SDRAMO_MEAR if they occur after the Invalid Address error 6 10 4 Double Bit ECC Error General Case The hardware procedure for this error is 6 16 CPC710 User s Manual 1 Set the Double Bit error bit in SDRAMO_MESR if no hard errors are present 2 Store the syndrome in SDRAMO_MESR and the address in SDRAMO_MEAR if no hard errors are present 3 In normal mode indicate the error to the requesting logic with DAT_ERR for the appropriate double word that failed in memory 4 In diagnostic mode do not indicate Double Bit errors with DAT_ERR 5 Software must write zeros to the SDRAMO_MESR to clear errors 6 If more than one Double Bit error occurs before the SDRAMO_MESR clears only the first error is recorded 7 A Single Bit error is not logged into SDRAMO_MESR and SDRAMO_MEAR when it occurs after a Double Bit error 8 If an Address error occurs after a Double Bit error it is not be logged into SDRAMO_MESR and SDRAMO_MEAR 6 10 5 Double Bit ECC Error Special Case For non burst write transactions that do not span an entire aligned double word the Memory Controller performs a read modify write sequence to memory If the read portion of this sequence results in a Double
169. ocessor Big Endian However the Little Endian mode is also supported for the processor but the CPC710 internally swap bytes and unmundge address before sending it to the memory or the PCI bus 60x Interface 4 1 PowerPC Big Endian CPU Little Endian option A 60x BUS Address Data y Y PCI64 Bridge Logic Unmunge and Byte Swap 64 Little Endian On gt Byte Bytes pr ES s Swap Buffer PCI64 BUS Big Endian 64 Bytes PCI32 Bridge Logic Memory Data Buffers 4 Byte Ge Swap y DIETER Address Buffer PCI32 BUS Memory lt gt 32 lt gt Control lt gt Bytes ay 64 ROM Data Buffer Little Endian CPC710 Figure 4 1 CPC710 Endian Logic The following listing shows how the data are transmitted from the CPU to the PCI32 bus for various size of bytes Access CPU to PCI32 in Write TSIZE 1 Byte 0 11 00 00 00 00 00 00 00 1 00 11 00 00 00 00 00 00 2 00 00 11 00 00 00 00 00 3 00 00 00 11 00 00 00 00 4 00 00 00 00 11 00 00 00 5 00 00 00 00 00 11 00 00 6 00 00 00 00 00 OO 11 00 7 00 00 00 00 00 00 00 11 b amp b BB OOO oO pa pa o o o o o o o pa pa pa TSIZE 2 Bytes O 11 22 00 00 00 00 00 00 00 00 22 11 1100 1 00 11 22 00 00 00 00 00 O 00 22 11 00 1001 o 4 2 CPC710 User s Manual uo TSIZE TSIZE 00 00 11 22 00 00 00 11 00 00
170. ode Enabled 2 3 PCI to System Memory Two types of address mapping modes are available e PowerPC Reference Platform PREP Mode e Flexible PCI Host Bridge FPHB Mode Addressing Model 2 5 To select a mode program bit CPCO_PGCHP 0 1 for the PCI32 or bit CPCO_PGCHP 2 3 for the PCI64 in CPCO_PGCHP on page 9 26 2 3 1 PowerPC Reference Platform PREP Mode In PREP Mode access from the PCI to the system can be performed with or without PCI address translation When translation is used the most common method is to translate addresses by complementing the upper 12 bits PCI addresses ranging from x 8000 0000 to xFFFF FFFF are translated to system memory addresses x 0000 0000 to x 7FFF FFFF In this mode only PCI access to Memory are decoded by the CPC710 Configuration and I O are not decoded 2 3 1 1 PCI Master Address Operation Whenever the PCI bridge logic identifies addresses coming from ISA Masters when the P_ISA_MASTER signal is active 1 they are passed directly to system memory Otherwise the untranslated addresses are checked to determine whether they fall within a bridge s PCI memory address range by comparing the PCI address to the following registers e PCILx_PMBAR on page 9 102 e PCILx_MSIZE on page 9 98 If there is no match and if translation is enabled by software the PCI address is translated to a system address bit 4 PCILx_PR on page 9 104 A series of checks
171. ogic detects an ecowx or eciwx transaction on the processor bus If the PCICx_REVID bits in the CPC710 and the CPCO_UCTL register match the PCICx_REVID bits on the SYS_TBST and SYS_TSIZ 0 2 lines the 60x logic accepts the transfer If the instruction is an ecowx the 60x logic SYS_ TAs the bus for dummy write data and sends a DMA Transfer Write command to the DMA Controller The internal address bus associated with the Transfer Write command contains the address from the processor bus This address is placed in the DMAO_XTARx register by the DMA Controller During the processor address tenure the 60x logic sets an internal flag to indicate special handling of TLBSYNC operations on the processor bus If the flag is not set the 60x logic ignores all TLBSYNC operations on the processor bus If the flag is set a TLBSYNC operation on the bus causes the 60x logic to place a one cycle pulse on the UX6_TLB_SYNC line to the DMA Controller The 60x logic continuously SYS_ARTRYs the TLBSYNC bus operation until it receives a one cycle pulse on the internal 8 4 CPC710 User s Manual UXI_XFER_DONE line from the DMA Controller This pulse also resets the 60x logic s internal flag to perform special handling of the TLBSYNC operations Note Since the PowerPC601 processor does not issue TLBSYNC operations the 60x logic must treat any SYNCs following a TLBI as a TLBSYNC operation when operating with a PowerPC601 processor When the eciwx instruction is use
172. omplete Cache line not 8 modified in CPU Retry PCI cycle Place memory read data on PCI bus to Y complete PCI transfer FLUSH data in buffers J Figure 7 1 PCI Memory Read State Diagram 7 4 2 PCI Master Memory Write Cycles When the CPC710 receives a memory write bus cycle to system memory it first initiates a FLUSH cache operation to the processor bus Processor accesses to this cache line will be SYS_ARTRYed until the memory write is finished If the cache line is determined to be stale in memory the PCI bus PCI Bridges 7 3 cycle is retried The following sequence describes the states the CPC710 follows when executing a PCI memory write cycle Idle je PCI Memory Write to system memory Initiate FLUSH cache op to the processor bus and start SYS_ARTRY of CPU access to this cache line Cache line Wait for is modified cache operation to complete Cache line not modified in CPU Receive memory write data from PCI bus Y Stop SYS_ARTRY of CPU accesses Initiate write to system memory and stop SYS_ARTRY of CPU accesses to this line Retry PCI cycle Figure 7 2 PCI Memory Write State Diagram 7 4 3 Configuration Cycles The CPC710 implements Configuration Mechanism 1 as specified in the PCI Local Bus Specification 2 This mechanism uses an indirect addressing model with the PCILx_CFGADDR an
173. operation setting should be made such that the times are matching closely with these values Bits Type of timing Value Clocking Period Time 0 9 SDRAM refresh time 10 0000 0000 33MHz PCI32 clock 512 x 30ns 15 360 us 10 15 Soft reset time 100010 33MHz PCI32 clock 34x 30ns 1 020 us 16 19 Software power on reset time 0100 33MHz PCI32 clock 4 x2 16x 30ns 7 86432 ms 20 23 Bus Timeout 0100 33MHz PCI32 clock 4 x2 16x 30ns 7 86432 ms 24 27 SDRAM init phase counter 0111 33MHz PCI32 clock 7 x 1024 x 30 ns 215 us Register Summary 9 33 CPCO_SEAR System Error Address Register This register contains the CPU address associated with the error that is logged in the SESR register described previously This register is only updated for errors that are due to CPU initiated transfers The address for errors that result from transfers initiated by PCI masters or DMA controller are located in error registers contained in the PCI bridge logic or the DMA controller logic In the case of dual processor implementation this register will contain only the address of the first error detected Reset Value x 0000 0000 Address x FFOO 1070 Access Type Read Write Address Associated with Error Contained in CPCO_SESR 4 4 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Address Associated with Error Contained in CPCO_SESR 9 34 C
174. or Syndrome Matrix AA 6 18 Data Values Required for Check Bits oooooonoconnnccnnnccnonccnoncnnnnennnncnornrnnnnnnn none nnnno nn rnn nn ren nnnennnnns 6 19 PCI32 Bus Device Physical Connection Example oooooccconocccnocccnooncnancnnnnnnonancnnnn nn nnn nn nnn roca nncnn rca 7 1 PCI Bus Bridge Configuration Address Map 7 1 Supported PC Commande cccoocccnoccccnoncnoncnononcnnnn conan nn non conan n cnn nn nan nn rn nn rr n nn rana r anar n nn ren rn rra rra 7 2 PCI Configuration Cycle Mats 7 5 PCI to Memory Sustained Throughput oooccnccccoccccnonnnnnnnonancnnnnncnnn ccoo cono nn nn nn nan nn caen cra nn rnnn nn nn ncnnns 7 6 CPU to PCI Sustained Throuohbput conc cnnnn conan nn rn n crac a rr nn nn rre nr rra 7 7 PCI Master Error Handling Page 1 Of 21 7 8 DMA Transfer Register Gummanm conan o nono nn nana nn nan nr nn nn nn nn nana n rana rear nnnn nace 8 2 DMA Transfer Status Cache Line Definition ooonnnnnnncnnccinnncnnnccnnonnnanncnnrnnnnrn nn nnn conan conan nnnnn cnn 8 3 System Registers Det geesde BER AA ee Se eee 9 3 Standard PCI Configuration Heoisters A 9 7 Specific PCI Host Bridge Registers a ea a aara aa r a a p EN e EE aE rene 9 8 Tables xi xii CPC710 User s Manual About This Book This book describes the IBM CPC710 PCI bridge and memory controller a highly integrated host bridge device that interfaces a PowerPC 60x bus with SDRAM based system memory and two PCI ports One PCI bridge supports a sta
175. p Addressing Model UO Space 2 9 2 10 CPC710 User s Manual Chapter 3 System UO Interface The CPC710 implements a 2 MB ROM space from address 4G 2M to 4 GB and an Extended Flash of up to 256MB 3 1 Configuration There is no configuration requirement for SIO logic These areas are hard wired in the upper 16 MB of real memory 3 2 System I O Registers Application Presence Detect Bits The device provides Output Enables signals and read cycles for two external 32 bit registers The read of the SDRAMO_SIORO or SDRAMO_SIOR1 results in a read of bits O to 31 of these register which correspond respectively to the data present on the line 31 and 0 of the PCI 32 bit A D during the read cycle For descriptions of these registers refer to e SDRAMO_SIORO on page 9 127 controls PRES_OEO signal e SDRAMO_SIOR1 on page 9 128 controls PRES_OE1 signal e SDRAMO_MCCR Register on page 6 11 for the device s supported values 3 3 Flash Interface 3 3 1 Boot Rom The CPC710 s Boot ROM base address is fixed at x FFEO 0000 Accesses to the architected Boot ROM space within the size limit defined in CPCO_SIOCO on page 9 38 are decoded as valid Boot ROM accesses If the ROM Size parameter is larger than the actual amount of installed Boot ROM the data will wrap An access within the architected Boot ROM space but outside the size limit CPCO_SIOCO x FFOO 1020 results in a bus timeout Machine Check error
176. part of 64 bit address AD63 32 During data phase 1 0 e i an additional 32 bits of data are transferred when G_REQ64 and G_ACK64 are both asserted G ADL31 00 32 bit Multiplexed Address Data Lower Part A write operation is defined as the 1 0 a f transfer of data from the PCI bus master to a PCI slave device on the PCI Bus G_ACK64 Acknowledge 64 bit transfer 1 0 G_REQ64 Request 64 bit transfer External pull up required 1 0 G_PAR64 Parity upper double word 1 0 G_CBE7 0 Bus Command Byte Enable 1 0 G_DEVSEL Device Select 1 0 G_IDSEL Initialization Device Select Used as chip select during configuration l G_FRAME Cycle Frame 1 0 G_IRDY Initiator Ready 1 0 G LOCK Lock Used to establish maintain and release resource locks on PCI64 Reserved for future usage It is recommended to tie up this signal G_PAR Parity bit WO G_GNT0 4 G_GNT5 7 P_GNT4 6 Bus Grants 9 Bus Requests G_REQ 2 is sampled at Reset to select arbitration on the PCI64 bus ere The arbitration can be made by the CPC710 G_REQ2 1 or by external circuit G_REQ0 4 SE G REO5 7IP DECHE G_REQ2 0 In case of external arbitration the request is send to PCI from E 6 G_GNT1 and the grant from the external arbiter is received on pin G_REQ1 G_REQ5 7 are programmed by setting bits 21 23 of the CPCO_PGCHP register Reset PCI64 Bus External pull up required G_RST Input Replicated on G_RESETOUT when programmed no internal use 1 0 Output Activated by the CPC710 at power up o
177. pe 1 configuration cycles the CPC710 directly copies the contents of the PCILx_CFGADDR register to the Address Data signals on the PCI bus However Address Data 1 0 contains 01 to indicate a Type 1 configuration cycle 7 5 PCI Performance Estimates Table 7 5 PCI to Memory Sustained Throughput Units MByte sec PCI64bit 66 MHz 16 1 1 1 1 1 1 1 3 6 1 PRAL S 12 1 1 1 1 1 1 1 5 1 PRAL 66MHz PCI Cycles Assumptions 4KBytes Burst e PCI Master parked on PCI bus No other activity present Adapter supports fast back back transfers for stores to memory No L1 or L2 cache hits PARL PCI Rearbitration Access Latency min 1 cycle 7 6 CPC710 User s Manual Table 7 5 PCI to Memory Sustained Throughput Read Write Units 130 130 MByte sec PCI32bit 33 MHz 11 1 1 1 1 1 1 1 1 PRAL 11 1 1 1 1 1 1 1 1 PRAL 33MHz PCI Cycles Assumptions 4KBytes Burst e PCI Master parked on PCI bus No other activity present Adapter supports fast back back transfers for stores to memory NoL1 or L2 cache hits PARL PCI Rearbitration Access Latency min 1 cycle Table 7 6 CPU to PCI Sustained Throughput Loads 100 MHz Bus Stores 100 MHz Bus SES PCI32bit PCle4bit PCI32bit PCI64bit Units 33 MHz 66 MHz 33 MHz 66 MHz Burst 32 bytes 71 194 194 MB s Single 8 bytes 30 67 67 MB s Single 4 bytes 17 33 33 MB s Assumptions CPU is pa
178. pipeline control Data streaming capability for external devices Programmable address bus parking capability Programmable timing on SYS_AACK Rotating address bus request priority scheme 60x Interface 4 5 4 2 1 Rotating Priority Resolution The CPC710 s 60x arbiter implements an algorithm that rotates priorities when the address bus is granted to a master When multiple masters request the bus the arbiter grants the bus to the master with the highest priority during the arbitration period then downgrades that priority to the lowest level for the next period The arbitration period occurs during the SYS_AACK assertion cycle If two masters continuously request the bus they receive alternate control This logic is satisfactory unless a master implements a 64 byte cache line and needs to issue two 32 byte burst transfers to fill the cache In this case the CPC710 has a programmable mode whereby the arbiter allows one bus master to perform a pair of back to back address tenures even if another master requests the bus This mode allows the CPC710 s memory controller to remain in page mode for these accesses Without this mode another master could insert a memory transaction to take the memory controller out of page mode 4 2 2 Address Bus Pipelining Pipelining is controlled by bits 0 and 1 of the 60x Arbitration Control register CPCO_ABCNTL Bit Description 10 If enabled by software the arbiter maintains up to a two level pipeli
179. ports the initialization and configuration of the PCI bridge facilities CPCO_PCIBAR register This register provides the unique setup signal required to insure that only one device will respond to configuration addresses at a time Software must adhere to the following restrictions for configuration e A write to the CPCO_PCICNFR register must be followed by a SYNC operation or a read of the register Reset Value x 0000 0000 Address x FFOO 000C Access Type Read Write o 2 D C oO W D S 5 T T 5 5 E E 3 Reserved 8 y y y y y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Configuration Enable 0 0 Disable Configuration access 1 Enable Configuration access defined as described in bits 30 31 1 29 Reserved Configuration Field Ox No action 30 31 10 Configuration access directed to PCI32 bus 11 Configuration access directed to PCI64 bus 9 24 CPC710 User s Manual CPCO_PCIENB PCI Base Address Register Enable Register This register provides a mechanism for software to disable the PCI bridge logic from decoding the address space pointed to by CPCO_PCIBAR This register is primarily used at power on time when the CPCO_PCIBAR has not been initialized Reset Value x 0000 0000 Address x FF20 1000 Access Type Read Write o O oO o Ro E e O O a 2 3 ig Reserved Reserved Reserved y y y
180. pported by the CPC710 Table 7 3 Supported PCI Commands C BE 3 0 Command Support as Initiator Support as Target 0000 Interrupt Acknowledge Yes No 0001 Special Cycle Yes No 0010 1 0 Read Cycle Yes No 0011 1 0 Write Cycle Yes No 0100 Reserved 0101 Reserved 0110 Memory Read Yes Yes 0111 Memory Write Yes Yes 1000 Reserved 1001 Reserved 1010 Configuration Read Yes Yes PCI64 only 1011 Configuration Write Yes Yes PCI64 only 1100 Memory Read Multiple No Yes 1101 Dual Address Cycle No No 1110 Memory Read Line Yes Yes 1111 Memory Write and Invalidate Yes Yes 7 4 1 PCI Master Memory Read Cycles When the CPC710 receives a memory read bus cycle from system memory it first initiates a CLEAN cache operation to the processor bus Processor accesses to this cache line are SYS_ARTRYed until the memory read is finished If the cache line is determined to be stale in memory the PCI bus cycle 7 2 CPC710 User s Manual is retried The following figure shows the states the CPC710 follows when executing a PCI memory read cycle Idle lt PCI Memory Read from system memory Initiate clean cache operation to the processor bus and start SYS_ARTRY of CPU access to this cache line Initiate read from system memory and stop SYS_ARTRY of CPU accesses to this line Cache line Wait for is modified for operations to c
181. present and decoded by the CPC710 1 3 Reserved R W 4 14 Start Address For Bank Bits 0 10 Defines the beginning address of this bank Contains upper bits 0 10 of the 32 bit real address Address restricted to a boundary equal to the size of the bank 15 Reserved R W 9 120 CPC710 User s Manual SDRAMO_MCERO 5 Memory Configuration Extent Registers 0 5 Bit s Description Size Code For Bank The encoding code depends of the programmed bit 8 of the Memory Controller Control Register SDRAMO_MCCR If SDRAMO_MCCR 8 1 the size code is defined as below x3FF Reserved x3FB Reserved x3F3 4 MB x3E3 8 MB x 3C3 16 MB x 383 32 MB x 303 64 MB x 203 128 MB x003 256 MB bes x 002 512 MB x 000 1 GB If SDRAMO_MCCR 8 0 the size code is defined as below X 3FF 4 MB x3FE 8 MB x3FC 16 MB x3F8 32 MB x3F0 64 MB x 3E0 128 MB x 3C0 256 MB x 380 512 MB x 300 1 GB x 200 2 GB x 000 4 GB Register Summary 9 121 SDRAMO_MCERO 5 Memory Configuration Extent Registers 0 5 Bit s Description SDRAM Addressing Organization b 0001 11 8 2 Row Col Bank select Address lines b 0010 11 9 1 b 0011 11 10 1 b 0100 12 8 2 b 0101 12 10 2 b0110 13 8 1 b 0111 13 8 2 b 1000 13 9 1 b 1001 13 10 1 b 1010 11 8 1 26 29 b 1011 12 8 1 b 1100 12 9 1 b 1101 14 9 2 b 1110 14 10 2 b1111 14 11 2 b 0000
182. quired for Check Bits Desired Check Bits C0 C7 Possible Data Value x 55 X AA x00 x 0832 C000 0000 0000 x B2A0 0000 0000 0000 x 6300 0000 0000 0000 x O1 x 2880 0000 0000 0000 x 02 x 04 x 08 x 4880 0000 0000 0000 x DF5C 0000 0000 0000 xBAAO 0000 0000 0000 x 10 x 357C 0000 0000 0000 x 20 x 40 x 80 x 08A0 0000 0000 0000 x 40A0 0000 0000 0000 x 4820 0000 0000 0000 Memory Controller 6 19 6 20 CPC710 User s Manual Chapter 7 PCI Bridges The CPC710 PCI bridges execute load and store operations from the CPU to the PCI buses It also provides an interface for PCI devices to access system memory The PCI Bridge logic fully supports the PCI Local Bus Specification 2 The following table describes the physical connections for PCI devices on the PCI32 bus in a desktop system Table 7 1 PCI32 Bus Device Physical Connection Example Device ARB Level RESET Signal IDSEL Signal PCI SLOT O P_REQO P_GNTO P_RST IDSEL1 PCI SLOT 1 P_REQ1 P_GNT1 P_RST IDSEL2 PCI SLOT 2 P_REQ2 P_GNT2 P_RST IDSEL3 ETHERNET CHIP P_REQ3 P_GNT3 P_RST IDSEL4 SCSI CHIP P_REQ4 P_GNT4 P_RST IDSEL5 ISA BRIDGE CHIP P_REQ5 P_GNT5 P_RST IDSEL6 MPIC Not required POWERGOOD IDSEL7 7 1 Address Map The two PCI bus bridges in the CPC710 both implement the register maps listed in the following table The PCI Host Bridge Standard configuration space
183. r PCI to System Access Only the PCI64 bridge has this register at this location For PCI32 bridge this register is in the Specific PCI32 PCI Bridge Space see page 9 8 Reset Value x 0000 0000 Address x 10 Access Type Read Write Enable UO or Memory Address Reserved i D vv D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Bit s Description PCI Base Address 31 24 Contains the upper bits of the System Base address that memory is mapped to 23 1 Reserved Enable Memory or lO Space copy of the bit 7 of the PCILx_PSSIZE Register 0 O Memory Space 1 IO Space 9 58 CPC710 User s Manual Reset Value x00 Address x0E Access Type Read Only Header Type b 00000000 D A 7 65 43 2 10 PCICx_BIST Header Type Specifies the layout of bytes x 10 through x 3F in the configuration header and whether or not a particular device contains multiple functions The CPC710 always responds with x 00 to reads to indicate Layout 0 Writes to this register are ignored Register Summary 9 59 PCICx_BUSNO Bus Number Reset Value x00 Address x 40 Access Type Read Write Bus Number D 4 7 6 5432 1 0 Bit s Description Contains the assigned bus number for this bridge 7 0 The CPC710 uses this number to determine what action to take for configuration cycles directed to this bridge After reset th
184. r by programming G_PERR Data Parity Error 1 0 G_SERR System Parity Error 1 0 G_STOP Stop Asserted by the target to request the master to stop the current transaction 1 0 G_TRDY Target Ready Asserted by the target when ready to receive data 1 0 G_INTA D Interrupts A D O G ARB Arbiter Asserted when the CPC710 is the PCI64 arbiter Can be converted in a Chip o Data Mask SDDQM by setting bit 15 of the SDRAMO_MCCR registe r G_RESETOUT Local Reset Asserted by PCI64 reset and special conditions O D SIO Interface Extended Flash Chip Enable This signal goes to 0 after the CPC710 has decoded an access to the Extended Flash EAU PE address range PEASREGE 1 Boot Flash Enabled S 0 Extended Flash Enable This signal must be used on card to insure that Boot Flash and Extended Flash cannot be accessed at the same time FLASH_OE Output Enable Flash ROM O FLASH_WE Write Enable Flash ROM O PRES_0EO0 1 Output Enable Presence detect PD buffer O or buffer 1 O XADR_LAT Latch Signal For SIO address register O XCVR_RD Address Direction SIO address bus O Signal Summary 11 5 Signal Name Description UO JTAG Interface TDI Test Data In l TMS Test Mode Select l TDO Test Data Out O TCK Test Clock l TRST Reset l System Interface System Reference Clock Used as 1 60X bus clock SYS_CLK 2 Attached proccesor clock 3 Synchronous SDRAM signals This clock is not synchronized with the PCI 32 and the PCI64 clocks
185. ransfer unless the Address Increment field in the Load Pointer command is set to No Increment Blit Write commands are handled in same way except the transfer is from I O to System Memory Note The DMA Controller should wait a minimum of eight cycles before reissuing snoop commands after a snoop fail response After the transfer is complete the controller signals the 60x logic by activating UXI_XFER_DONE for one cycle The controller then issues a Write with Kill to the address specified in DMAO_XWARx register to indicate to software that the transfer is complete The controller issues a Kill Cache to the 60x logic and upon receiving a clean response issues a Write command to system memory The write to memory need only be a single beat write to the bytes reserved for DMA transfer status 8 5 1 Special Boundary Conditions Due to queueing in the 60x logic a pulse could be placed on the TLBSYNC line to the DMA Controller before the controller receives an ecowx or eciwx In this case the controller waits until it receives an ecowx or eciwx and then immediately terminates the DMA transfer When two DMA transfers overlap the controller ignores the TLBSYNC pulse if a DMA transfer is nearly complete However because the 60x logic could have an eciwx or ecowx queued the controller would have to remember the TLBSYNC pulse to terminate the second DMA transfer properly To do this the 60x logic indicates the presence of an eciwx or ecowx instruction in
186. re not present and the PLL can be recovered only by pulsing the RESET or VDDA pins 5 4 Initialization of the SDRAM To Initialize the SDRAM during the system boot it is necessary to first set all the registers of the CPC710 Memory controller and then start an automatic initialization phase by programming bit 0 of the SDRAMO_MCCR Memory Controller Control Register The MRS Mode Register Set cycle runs only when CPC710 register SDRAMO_MCCR bit 0 is set In the initialization phase the CPC710 executes the following sequence 1 Pause 200 us 2 Precharge all cycle 3 8 refresh cycles 4 MRS cycle When the initialization phase is completed the bit 2 of the SDRAMO_MCCR register is set to 1 such that a polling of this bit permits to go ahead with the initialization of the others features of the CPC710 e Examples of Programming type of SDRAM Initialization 5 3 CAS Latency 2 or 3 The CAS Latency is set in the SDRAM Mode register according to SDRAMO_MCCR 24 Registered mode There is no need to program the SDRAM registered mode because most of the SDRAM memory interface signal works with 2 CPU cycles which permits to handle signals on cycle late In the case of Registered SDRAM the timings on Reading data from the SDRAM will be more critical because the data will have only one cycle to reach the Multiplexor 5 5 Reset Individual Devices The Connectivity Reset Register CPCO_RSTR at the address xFFOO 0010 provides a mean
187. rget addresses operations to be performed in a single operation To have a chained DMA the bit 31 of the DMA Transfer Write Back Address Register DMAO_XWARx have to set to 1 to enable the chaining at the completion of the first DMA operation The chained DMA descriptors are stored in the memory cache line at the address defined in the DMAO_XWARx The Skip of Cache line mode is a way to fill table with one elementary cache line out of n ina DMA operation The Cache line increment is defined in the DMAO_XCLRx register 8 3 Starting the DMA e Write in the DMAO_XTARx register The write in the DMAO_XTARx register results in the start of a DMA operation e eciwx or ecowx instruction DMAs are initiated by either a eciwx read Data from Memory to PCI or ecowx write PCI to Memory instruction from the processor and ended by an External Interrupt command The controller uses an elementary burst of 32 Bytes on the PCI bus to facilitate interleaved PCI bus operations The eciwx and ecowx instructions use the processor s internal address translation logic to present real DMA Controller 8 1 addresses on the system bus This eliminates the need for external hardware to translate virtual addresses and for software to calculate real addresses Because the DMA is virtual no software overhead is required for pinning system memory that would otherwise be needed if the DMA operated in real address mode Execution of an eciwx or ecowx instruction invol
188. rite For system designs requiring high I O bandwidth the device contains two PCI host bus bridges One bridge supports a standard 32 bit 33 MHz PCI bus for standard and native I O The other bridge supports a 64 bit 33 66 MHz PCI bus for high data throughput applications such as graphics and high speed communications A DMA controller provides high speed capability for large data transfers between memory and I O Store gathering enhances CPU to I O performance 1 1 Features e Up to 133 MHz PowerPC 60x 64 bit bus e 2 5 volts 60X PowerPC bus e Supports 100 and 133 MHz SDRAM including PC100 and PC133 e Up to 2 MB flash Boot ROM support e 32 bit 33 MHz 64 bit 33 66 MHz async dual bus e Reads two external 32 bit registers e PreP and CHRP compliant design e One channel chained DMA controller e Up to 256 MB Extended Flash support e 3 3 volts 5 2 5 volts 2 5 e 40 to 85 C junction temperature e Power dissipation 2 1 watts typical at 3 3 volts 100 MHz e FC PBGA package 729 pins 1 27mm pitch 35x35mm e CMOS SA 12E 0 25um technology e PLL to reduce on chip system clock skew e JTAG controller LSSD design 1 1 1 60x Bus Interface e Supports PowerPC 750L 750CX 750CXe processors e up 133 MHz external bus operation e Supports four processors or L2 lookaside cache e Dual 32 byte store back buffers e High bandwidth 2 way arbiter e Little Endian mode PowerPC Overview 1 1 Supports SYNC EIEIO ordering operatio
189. rked on 60x bus 1 Level Pipeline CPC710 parked on PCI bus No other activity present 7 6 PCI Master Error Handling For PCI bus errors detected on CPU initiated transfers refer to Error Handling for CPU Initiated Transactions on page 4 15 The following table describes the error handling performed for PCI master errors PCI Bridges 7 7 Table 7 7 PCI Master Error Handling Page 1 of 2 Operation Mode Action Notes Enabled by PCI PCICx_CM Drea Address Parity Error o GN Any PCI Bus Transfer Save encoded arb level in PCILx_CSR register Set Address parity error detected bit in PCILx_CSR regis ter Set Parity error detected bit 15 in PCI status register Place PCI address in PCILx_PSEA register Activate SERR signal if enabled by bit 8 PCI PCICx_CMD register Set Signalled SERR bit in PCI Status register if enabled Target abort PCI transfer if address matches Set Signaled target abort bit in PCI status register Signal Machine Check with SYS_MCP0 1 Disabled Set Parity error detected bit 15 in PCI status register Complete PCI transfer normally if address matches Detected SERR Active PCI Bridge Logic Idle Set Detected SERR active bit in PCILx_CSR register Save encoded ARB level in PCILx_CSR register Signal Machine Check with SYS_MCP0 1 Single Bit Error Access to System Memory Normal Double Bit Error Set single bit error and syndrome in SDRAMO_MESR Set error address in SDRA
190. rmit to the connected CPU to read the CPCO_PIDR register such that this CPU identifies if he is a Master or a slave In the case the CPU 1 slave get access first the boot code can put him in a pooling mode until the Master complete the I O and Memory initialization One way is to write in the Register CPCO_RSTR 4 Way Multiprocessor The CPC710 handles up to 4 CPU 5 4 CPC710 User s Manual PowerPC750CX PowerPC750CX PowerPC750CX PowerPC750CX CPUO CPU 1 CPU 2 CPU 3 BRO BGO BR1 BG1 BR2 BG2 BR3 BG3 CPC710 133 60X Bus Arbitration 4 way SMP Figure 5 3 Arbitration to support of 4 Way Multiprocessing with the CPC710 5 7 Typical Register Setup Sequence Many deviations from the proposed following example of set up are possible However it is important to keep the basic operations in the same sequence order as described below BRR KKK KH HK KKK KK HK KKK KK HH KKK KK HK KKK KK A Typical CPC710 100 registers setup sequence from model simulation 11 17 99 BRK e He e He e He e He e KH HK KKK KK e He e He e He e KKK He He He He HK He He He He e He e He e He e He e He ke ke ke ke ke ke ke ke k ke k kkk kk k Begin CPC710 100 registers setup sequence a 60X Interface registers setup A SS CPCO_RSTR Oxff000010 write 0xf0000000 CPCO_UCTL Oxff001000 write 0x32f 80000 CPCO_ABCNTL 0xff001030 write 0xb0000000 CPCO_ERRC 0xff001050 write 0x00c
191. rocessor 0 1 PCI bridge logic machine checks processor 1 9 104 CPC710 User s Manual PCILx PR Personalization Register Bit s Description PCI Master to Memory Address Translation in PREP Mode 4 0 PCI Master addresses are always translated before being presented to system memory see CPCO_PCIBAR on page 9 23 1 PCI Master addresses are NOT translated and sent directly to system memory ARB Level To Park 5 7 Contains the encoded arbitration level to park when bus is idle level 000 is for agent 0 level 001 for agent 1 and so on IRDY Count 8 11 Contains the number of PCI clocks times 8 that the CPC710 waits before detecting a time out condition A value of zero disables the time out check TRDY Count 12 15 Contains the number of PCI clocks times 8 that the CPC710 waits before detecting a time out condition A value of zero disables the time out check PCI Queue Enable CPU to PCI Access 16 0 PCI logic does not queue requests 1 PCI logic queues up to two operations PCI ISA Bridge Deadlock Avoidance Disable 0 PCI ISA Bridge is present in the system Therefore the CPC710 will 17 1 NOT deactivate P_GNT 5 even if other REQs become active other REQs internally gated 2 not activate P_GNT 5 until 60x bus has flushed all posted PCI 32 bit bus transfers 1 PCI ISA Bridge is NOT present in system so CPC710 treats the P_REQ 5 signal like any other PCI bus REQ signal Grant Active
192. rupt IT1 Addressed Register 9 82 4 CPCO_PCIBAR Set of G_INTA G_INTB G_INTC G_INTD on x 000F 8310 PCIL1_INTSET PCI64 9 81 4 CPCO_PCIBAR i x000F 9800 PCILx_CSR Channel Status Register 9 91 EE PCILx_PLSSR Processor Load Store Status Register 9 101 1 Read Only Register write is ignored 2 Little Endian registers 3 Only for PCI32 4 Only for PCI64 9 5 Alphabetical List of Registers This section lists the chip control and peripheral interface registers available in the CPC710 Register Summary CPCO_ABCNTL 60X Arbiter Control Register This register provides extensive control over the 60x bus arbiter operation For a detailed description of the 60x bus arbiter see 60x Bus Arbiter Description on page 4 5 Reset Value x 0000 0000 Address x FFOO 1030 Access Type Read Write 5 SE s 8 a a ZG 3 N o 9 o S D o o 5 O O Oe san 3 5 S a a A o 5 Diets e el D o D e d a 3 lt o o o o e oO SH 5 Z Xx E e 5 o ES aa E 2 D et 3 z UI 5 a e 8 8 2 5 Et 5 a oN 2 2 3 3 5 oO oR Ye 6 280 62 a ga 0 Ss 2 5 326 oo eg es o Ed bg ag bd o n 0 2 8 2 0 GO 5 e a 2 S ZS a Ss 3 f 8 E 238252308380 3 33 a O una lac Reserved ZA EA 2 rr rd vr vv vyvvv vr y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s 60X bus Pipeline Control Pipelining Disabled 0 1 One level pipelinin
193. rved arbiter will assume address only transaction 01000 SYNC No Yes 01001 TLBSYNC Address only No Yes 01010 Read SBR or Burst No Yes Yes See 01011 RWNITC Read with no Intent to Cache CPCO_ATAS Reg Yes treated as 01010 SBR or Burst ister 01100 Kill Sector Address only Yes NOP 01101 ICBI Address only No NOP Yes See 01110 RWITM Read with Intent to Modify CPCO_ATAS Reg Burst ister Yes treated as 01010 01111 Reserved arbiter will assume address only transaction 10000 EIEIO Address only No Yes 10001 Reserved arbiter will assume address only transaction Note SBW Single Beat Write SBR Single Beat Read 60x Interface 4 9 Table 4 5 Transfer Types Page 2 of 2 TT 0 4 Operation Transaction Sipe Support as Slave 10010 Write with Flush Atomic No Yes treated as 00010 10011 Reserved arbiter will assume address only transaction 10100 ECOWX Graphics Write SBW No Yes 10101 REESEN Reserved arbiter will assume address only transaction 11000 TLB Invalidate Address only No 11001 Reserved arbiter will assume address only transaction 11010 Read Atomic No Yes treated as 01010 11011 Reserved arbiter will assume address only transaction 11100 ECIWX Graphics Read SBR No Yes 11101 Reserved arbiter will assume address only transaction 11110 RWITM Atomic Burst No Yes treated as 01010 11111 Reserved arbiter will assume address only transaction Note S
194. s Compare on Successive Long Burst Writes 2 p lt 5 5 lt 5 S e S gt o 8 O S O Oo gt 5 5 5 EBS lt D 2 5 2 3 2 2 G O o e o a g D n kel X E Q E o y UI We o o o 8 o T d 2 2 3 a 3 lt E Ss oz o Ss 2 o E 9 5 o 8 8 e p p Of LP o o o 9 aspas 5 o 3 PPseseERE os 9 9 2 Y E ep g Reserved i 2 Reserved Ley sive y Y Vids d IN REES 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Long Burst WRITE Enable 0 0 Maximum burst size of 32 Bytes in this case all following bits must be left to 0 1 Maximum burst size of 4 KBytes No Disconnect PCICx_RETRY after 32 Bytes Filtering of the type of WRITE converted in Long Burst Mode available only if bit 0 is set to 1 1 0 All access are in Long Burst mode 1 Only the access with the PCI Command defined in bits 8 11 are in Long Burst mode Address Comparison On Successive Long Burst WRITE available only if bit 0 is set to 1 0 No Address Comparison made 1 Latency for the first Data is reduced if the address has been already snooped in the previous Long Burst access This is true if the new access is begun in the time window defined as below Window opportunity for Address Comparison The anticipation mode is possible only if there is at least a number of PCI clock cycles between the end of one 3 access and the start of the next access 0 8PCI Cycles
195. s in CPCO_SEAR if CPCO_PGCHP 26 0 Loads Signal Machine Check with SYS_TEA Stores Signal Machine Check with SYS_MCP0 1 If CPCO_PGCHP 26 1 signal Machine Check with SYS_MCP0 1 Set double bit error in SDRAMO_MESR Set error address in SDRAMO_MEAR Return uncorrected data to CPU Signal Machine Check with SYS_MCP0 1 if write less than 8 bytes Notes 1 A dummy 0 is returned for read operation For write data is ignored 4 16 CPC710 User s Manual Table 4 6 CPU Initiated Transactions Page 3 of 5 Operation Error Mode Action Note No DEVSEL received Master abort the PCI transaction Set master aborted bit 13 in PCI Status register Set Devsel error bit 3 in PCILx_PLSSR register Set PCI error bit in CPCO_SESR Set error address in CPCO_SEAR register If CPCO_PGCHP 26 0 Loads Signal Machine Check with SYS_TEA Stores Signal Machine Check with SYS_MCP0 1 If CPCO_PGCHP 26 1 Signal Machine Check with SYS_MCP0 1 Terminate CPU transaction normally Access to PCI bus Detected SERR active dur ing PCI transaction Master abort the PCI transaction Set master aborted bit 13 in PCI Status register Set SERR detected error in PCILx_PLSSR register Set PCI error bit in CPCO_SESR Set error address in CPCO_SEAR register If CPCO_PGCHP 26 0 Loads Signal Machine Check with SYS_TEA Stores Signal Machine Check with SYS_MCP0 1 If CPCO_PGCHP 26 1 Signal Machine Check with S
196. s this register when acting as a target device as a time out mechanism in burst operations The value written to this register is multiplied by four and used to determine when the bridge should assert STOP After reset this register contains x 00 which disables the timer This counter is enabled only if bit O for PCI 32 or bit 8 for PCI 64 of CPCO_AVDG Register is set see CPCO_AVDG on page 9 15 When time out occurs the bit 9 of the PCILx_CSR Register is set see PCILx_CSR on page 9 91 9 66 CPC710 User s Manual Reset Value x00 Address x0E Access Type Read Only Header Type b 00000000 D A 7 65 43 2 10 PCICx_HDTYPE Header Type Specifies the layout of bytes x 10 through x 3F in the configuration header and whether or not a particular device contains multiple functions The CPC710 always responds with x 00 to reads to indicate Layout 0 Writes to this register are ignored Register Summary 9 67 PCICx_INTLN Interrupt Line Reset Value x00 Address x3C Access Type Read Only Interrupt Line b 00000000 Y A 76543210 Indicates interrupt routing information for devices that implement an interrupt The PCI bridge logic does not gener ate interrupts and therefore this register is not implemented The CPC710 responds with x 00 to reads from this register and ignores Writes 9 68 CPC710 User s Manual Reset Value x 0
197. s to individually reset devices on the 60x bus Bits O and 1 directly control SYS_HRESETO and SYS_HRESET1 respectively The remaining two bits control and Reset the PCI 32 and PCI64 internal logic of the CPC710 The bits 0 of the CCR O register controls the PCI 32 or PCI64 reset signals that are outputs of the CPC710 e PCI32 bus example When bit 2 of register CPCO_RSTR is asserted low the PCI32 internal circuit of the CPC710 goes to reset After the reset when the bit 2 is deasserted Returns to high level 1 it takes 250ns before the PCI 32 bus can be used for normal accesses 5 6 Reset in Multiprocessor mode The sequence of Power On Reset in Multiprocessor is the same as for a Single CPU on the 60X bus Simultaneously the HRESETO and HRESET1 signal goes up after the POWERGOOD signal goes up One of the two CPU get the PowerPC bus through SYS_ BRO or SYS_BR1 and get granted to access the Boot ROM at address FFFF 0100 It can be decided for example that the CPU 0 is the Master and the CPU 1 the slave with the CPU 0 in charge of running the code to configure the CPC710 bridge The Master slave configuration is defined with the help of registers CPCO_PIDR amp CPCO_RSTR CPCO_PIDR Physical Identifier Register When BRO BGO signal pair is set bit 31 is set to 0 BR1 BG1 signal pair is set bit 31 is set to 1 e CPCO_RSTR Connectivity Reset Register permit to reset CPUO or CPU1 The first action of the boot code is to pe
198. s to control ECC generation and checking b 01 is provided to allow software direct read write access to the ECC byte that is associated with every doubleword of data stored in memory and also provide a mechanism to verify the memory controller s ECC generation and check ing logic In this mode byte lane 0 data MSB of a double word is written to the ECC byte instead of the normal ECC code byte Data byte 0 will be forced to all zeros For reads byte 0 will contain the byte stored in the ECC byte not the data at byte 0 ECC checking is not enabled for reads in this mode This mode also allows firmware write single bit and multi bit errors into memory to allow for ECC logic testing 00 Normal generation and checking of ECC codes 3 4 The CPC710 will generate the normal ECC code when writing to memory and check ECC when reading 01 ECC check disabled Byte lane 0 routed to from ECC check field Data byte 0 forced to all zeros This mode is provided to allow software direct read write access to the ECC byte that is associated with every doubleword of data stored in memory and also provide a mechanism to verify the memory controller s ECC generation and checking logic In this mode byte lane 0 data MSB of a double word is written to the ECC byte instead of the normal ECC code byte Data byte 0 will be forced to all zeros For reads byte 0 will con tain the byte stored in the ECC byte not the data at byte 0 ECC checking is not enabled for reads in
199. scription Status Double word 0 0 63 Reserved Status Double word 1 0 63 Undefined Status Double word 2 0 63 Undefined Status Double word 3 0 31 x 0000 0000 DMA Controller 8 3 Table 8 2 DMA Transfer Status Cache Line Definition Bit s Description Poll Status Cache Line Valid Flag 32 39 x 00 Initial value set by software Indicates status cache line is not valid x FF Written by hardware to indicate that the status cache line has been updated and is valid Transfer Complete 40 0 Transfer is not complete 1 Transfer is complete TLBSYNC Detected 41 0 No TLBSYNC Detected 1 TLBSYNC detected during DMA transfer Transfer 42 Reserved Page Crossing Error 43 1 Page Crossing detected during DMA transfer 44 Second DMA Transfer Halt 1 DMA transfer operation in progress was halted due to start of second DMA transfer operation 45 Unaligned ecowx eciwx Address 1 Address associated with ECOWX ECIWX is not word aligned 46 Unaligned Transfer Error 1 Address alignment error 47 Address Increment Alignment Error 1 Improper alignment of addresses when Address Increment bit is off 48 Invalid PCI Address 1 DMAO_XPARXx did not match any PCI extents 49 50 Reserved Transfer Length ates This field contains the number of bytes remaining when the transfer was completed or aborted 8 5 DMA Procedure The DMA transfer process begins when the 60x l
200. signaled target abort bit in PCI status register Signal Machine Check with SYS_MCPO 1 Stores Signal Machine Check with SYS_MCPO 1 Set SERR detected error bit in PCILx_CSR register Save encoded ARB level in PCILx_CSR register Target abort PCI transfer Set signaled target abort bit in PCI status register Signal Machine Check with SYS_MCP0 1 Activate the PERR signal Set parity error bit 15 in PCI Status register Complete PCI transfer however Flush store data do not write to memory Notes Disabled Set parity error bit 15 in PCI Status register Proceed normally with PCI transaction Proceed normally with PCI transaction Received Master Abort PCI Bus Timeout IRDY Count Expired Internal Response Bus Contains PCI Error Status Proceed normally with PCI transaction Target abort PCI transfer Set signaled target abort bit in PCI status register Set PCI bus time out error in PCILx_CSR register Save encoded ARB level in PCILx_CSR register Signal Machine Check with SYS_MCP0 1 2nd PCI bridge logs errors same as CPU initiated 2nd PCI bridge does NOT drive SYS_MCP0 1 pin Set PCI PCI error bit in PCILx_CSR register Save encoded ARB level in PCILx_CSR register Save PCI address in PCILx_PSEA register Loads Target abort PCI transfer Set signaled target abort bit in PCI status register Signal Machine Check with SYS_MCP0 1 Stores Signal Machine Check with SYS_MCP0 1 1 Normally means
201. sor associated with BR2 and BG2 pins x 03 Indicates processor associated with BR3 and BG3 pins Register Summary 9 29 CPCO_RGBANO Free Register O This register contains data coming from the CPU Reset Value x 0000 0000 Address x FFOO 1110 Access Type Read Write Data from CPU 4 4 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Data from CPU 9 30 CPC710 User s Manual CPCO_RGBAN1 Free Register 1 This register contains data coming from the CPU Reset Value Address Access Type x 0000 0000 xFFOO 1120 Read Write Data from CPU y A 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 Data from CPU Register Summary 9 31 CPCO_RSTR Connectivity Reset Register This register provides a means to individually reset devices on the 60x bus Bits 0 1 4 and 5 directly control SYS_HRESETO SYS_HRESET1 SYS_HRESET2 SYS_HRESET3 respectively The remaining two bits 2 and 3 control reset signals that are internal to the CPC710 Reset Value x CC00 0000 Address xFFOO 0010 Access Type Read Write o lt Reset for First Processor lt Reset for Second Processor w lt Reset for PCI32 Bus Bridge w Reset for PCI64 Bus Bridge 4 lt Reset for Third Processor lt R
202. ss A0 A A7 AQ A10 Ait AT2 AS Aid ME AT A7 A8 ml mE on Col Address 0 Au A2 A6 A7 A20 A21 A22 A23 A24 A25 A2 A27 Row Address AD A4 A7 AS A10 Ait At Ata Aid AE E Ai DE AiO y een Sg Col Address 0 Au A2 A3 AG A20 A21 A22 A23 A24 A25 A2 A2 Row Address A0 A4 A7 AQ AiO Att AIS Ai3 Al AE ME Ai Au M Col Address 0 Au A2 AS AG A20 A21 A22 A23 A24 A25 a Aer H AB 12 9 1 SE 6 10 CPC710 User s Manual Table 6 10 SDRAM Address Mapping Row Address AO A4 A7 AQ A10 A11 A12 A13 A4 AIS Al6 At7 A8 A19 ColAddress 0 At A2 A3 A6 A20 A21 A22 A23 A24 A25 A26 A27 6 1282 0 0199 Row Address AD A6 A7 AQ A10 Ati A12 Ais Aid Ais Ale Ai A8 M9 q EEN Se Col Address 0 At A2 A3 AG A20 A21 A22 A23 A24 A25 A26 A27 RowAddress AO A4 A7 AQ AiO Alt AIS Al3 Aid AS Al6 A AS A Col Address 0 Au A2 A3 A6 A20 A21 A22 A23 A24 A25 A2 Aer JP 1292 O Gefault Row Address AD A6 A7 A9 AiO Ati A12 Ais Aid Ais ME Ai M ATO pp aan Soe Col Address 0 At A2 A3 AG A20 A21 A22 A23 A24 A25 A26 A27 Row Address A0 A5 A7 AQ A10 Ati A12 AfS Aid MS ME Ai7 vm ml oe SS Col Address 0 Al A2 A3 AG A20 A21 A22 A23 A24 A25 A26 A2 Row Address A0 A4 A7 AQ AlO Alt A12 Ala Aid AE Al Al AE A l Col Address 0 Au A2 A4 A6 A20 An A22 A23 A24 A25 A26 A27 DP 12 10 2 b 0101 Row Address AD A4 A7 AQ A10 ATi A12 AfS Aid AIS ME AMC vm ml an Sen Col Address 0 Au A2
203. t PCICx_RETRY after 32 Bytes Filtering of the type of READ converted in Long Burst Mode available only if bit 0 is set to 1 1 0 All access are in Long Burst mode 1 Only the access with the PCI Command defined in bits 8 11 are in Long Burst mode Address Comparison On Successive Long Burst READ available only if bit 0 is set to 1 0 No Address Comparison made 1 Latency for the first Data is reduced if the address has been already snooped in the previous Long Burst access This is true if the new access is begun in the time window defined as below Register Summary 9 107 PCILx_PSRCR PCI Slave Read Control Register Bit s Description Window opportunity for Address Comparison The anticipation mode is possible only if there is at least a number of PCI clock cycles betweeen the end of one access and the start of the next access 0 8 PCI Cycles 1 64 PCI Cycles 9 108 Turbo Read mode Only for the PCI64 and available only if bit O is set to 1 If selected the CPC710 use two additional 32 bytes buffers to increase memory bandwidth 0 Disable 1 Enable Higher PCI Loads Support Only for the PCI64 If selected the CPC710 responds with an additional wait state on TRDY to avoid internal critical timing budget 0 Disable 1 Enable Reserved Read Only PCI READ Command C BE for Filtering option if enabled with bit 1 See C BE 3 0 in the PCI section for supported commands Reserved Read
204. t error address in CPCO_SEAR CPCO_PGCHP 26 0 Signal Machine Check with Enabled SYS TEA Addressing Error Access not directed SYS 2 HIT not driven to the CPC710 active CPCO_PGCHP 26 0 Signal Machine Check with SYS_MCP0 1 Notes 1 A dummy 0 is returned for read operation For write data is ignored 60x Interface 4 15 Table 4 6 CPU Initiated Transactions Page 2 of 5 Operation Error Mode Action Note Access to CPC710 Access to internal CPC710 facilities Access to system memory Disabled Inhibit timer no action taken Bus Time out Time expired from SYS_AACK active to first SYS_TA Enabled Access to a reserved or non implemented address Alignment or size Store to read only register Load from write only regis ter Single bit error Don t care Set bus time out error bit in CPCO_SESR Set checkstop generated bit in CPCO_SESR Set error address in CPCO_SEAR Signal Checkstop Terminate CPU transaction normally Set single bit error and syndrome in SDRAMO_MESR Set error address in SDRAMO_MEAR Return corrected data to CPU If CPCO_PGCHP 17 1 and CPCO_PGCHP 26 1 Set memory error bit in CPCO_SESR Set memory error address in CPCO_SEAR Signal Machine Check with SYS_MCP0 1 Normal Double bit error Diagnostic Set error in SDRAMO_MESR Set error address in SDRAMO_MEAR Set memory error bit in CPCO_SESR Set memory error addres
205. t s Description ARB Level 0 Enable correspond to signal pair G_REQO G_GNTO on PCI64 or P_REQO P_GNTO on PCI32 0 O ARB level is ignored de ARB level is enabled 1 ARB Level 1 Enable 2 ARB Level 2 Enable 3 ARB Level 3 Enable 4 ARB Level 4 Enable 5 ARB Level 5 Enable 6 ARB Level 6 Enable 7 ARB Level 7 Enable Not supported in 32 bit PCI bridge 8 31 Reserved Register Summary 9 83 PCILx_BARPP System Base Address for PCI to System Extended Access The definition is the same for 32 bit PCI and 64 bit PCI This register must be used if extended memory space is used see bit 27 of CPCO_PGCHP register and if FPHB mode is selected this register as no action in CHRP mode or PREP mode Reset Value Address Access Type x 0000 0000 CPCO_PCIBAR x 000F 8130 Read Write PCI Base Address e A y 4 0123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s 0 23 24 31 Reserved System Base Address Contains the upper bits of the PCI Base address that PCI is mapped to Description 9 84 CPC710 User s Manual PCILx_BARPS System Base Address for PCI to System Access The definition is the same for 32 bit PCI and 64 bit PCI Reset Value x 0000 0000 Address CPCO_PCIBAR x 000F 8120 Access Type Read Write Reserved System Base Address D y y A 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
206. te 0x00000000 PCI64 Command register setup PCILx CFGADDR 0xff4f8000 write 0x04000080 PCILx CFGDATA 0xff4f8010 write 0x5601 PCI32 Interface registers setup VR PCILx PIBAR Oxf 5 7800 write 0x1c000000 PCILx_PMBAR write 0x1a000000 PCILx_PR write 0x0000c000 PCILx_ACR write Oxfe000000 PCILx MSIZE write Oxfe000000 example with 32 MB PCILx IOSIZE write 0Oxff800000 example with 8 MB PCILx_SMBAR write 0xc0000000 PCILx_SIBAR write 0x80000000 PCILx_CSR write 0x00000000 5 6 CPC710 User s Manual PCILx_PLSSR write 0x00000000 PCILx_BPMDLK write 0xc0400000 PCILx_TPMDLK write 0xc0800000 PCILx_BIODLK write 0x80400000 PCILx_TIODLK write 0x80800000 PCI32 Command register setup PCILx CFGADDR 0xff5f f8000 write 0x04000080 PCILx CFGDATA 0xff5f8010 write 0x5601 Wait for SDRAM initialization is complete gt SDRAMO MCCR 2 goes to a 1 Release external reset to PCI32 bus agents PCILx CRR Oxff5f7ef0 write Oxfc000000 Release external reset to PCI64 bus agents PCILx_CRR Oxff4f7ef0 write 0xfc000000 End of CPC710 100 registers setup sequence Initialization 5 7 5 8 CPC710 User s Manual Chapter 6 Memory Controller 6 1 Overview The CPC710 memory controller controls processor and I O interactions with the memory system The memory controller supports SDRAM an
207. tem bus dependent on program ming of CPCO_PGCHP 26 See CPCO_PGCHP on page 9 26 CPU to PCI Bus Access Error for CPU 1 or CPU 3 0 No Error 23 T Error occurred on PCI32 or PCI64 bus while servicing processor load store request DMA Error for CPU 1 or CPU 3 O No Error 24 de Error occurred during DMA transfer CPU Access to Memory Error for CPU 1 or CPU 3 O No Error 25 1 Error occurred during an access by the CPU to memory 9 36 CPC710 User s Manual CPCO_SESR System Error Status Register Bit s Description CPU to PCI32 Read Timeout 0 No Error z 1 Error occurred during an read access in a deadlock area CPU to PCI64 Read Timeout 0 No Error ad 1 Error occurred during an read access in a deadlock area 28 31 Reserved Register Summary 9 37 CPCO_SIOCO System I O Control This register provides initialization and control of the Boot FLASH and the Extended FLASH devices to which the CPC710 interfaces Reset Value x 0000 0000 Address x FFO0 1020 Access Type Read Write me Lo S Flash Flash Flash P g Boot Flash Output 9 PCI32 CI32 Size Reserved Reserved Delay Reserved Synch Set Up Reserved A LA d yr AE yyy vy vv yy y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Flash Timing Control 0 The CPC710 does not use values programmed in FONT LATMAX and LADRMAX fie
208. terprocessor Interrupt This is a Virtual Register When addressed the interrupt signal INT1 is set goes to 0 The SET can be done from the PCI 64 or from the PowerPC CPU in configuration mode Only the PowerPC CPU can reset the interrupt INT1 by writing a 1 in the PCIL1_ITADDRESET interrupt reset register Reset Value x 0000 0000 Address x 64 Access Type Write Only Reserved Set_add_it A y y y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit s Description 31 8 Reserved Set_add_it 7 0 1 Writing a 1 in one of these 8 bits SETS the interrupt signal INT1 0 No action 9 56 CPC710 User s Manual PCIC1 PPBAR PCI64 Base Address for PCI to System Extended Access Only the PCI64 bridge has this register at these location For PCI32 bridge this register is in the Specific PCI32 PCI Bridge Space see page 9 8 This register must be used if extended memory space is used see bit 27 of PGCHP register and if FPHB mode is selected this register as no action in CHRP mode or PREP mode Reset Value x 0000 0000 Address x 14 Access Type Read Write PPBAR y y 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Bit s Description PCI Base Address 31 0 Contains upper bits of the System Base address that memory is mapped to Register Summary 9 57 PCIC1_PSBAR PCI64 Base Address fo
209. tes are numbered in descending order from left to right The most signif icant bit MSB has the highest number and the least significant bit LSB has the lowest number MSB LSB 31 24 23 16 15 8 7 0 In Big Endian mode bits and bytes are numbered in ascending order from left to right The most signifi cant bit MSB has the lowest number and the least significant bit LSB has the highest number MSB LSB 0 7 8 15 16 23 24 31 Related Publications The following publications contain related information CPC710 PCI Bridge and Memory Controller Data Sheet SA14 2572 00 IBM PowerPC 750CX 750C Xe RISC Microprocessor User s Manual CPC700 Memory Controller and PCI Bridge Data Sheet CPC700 Memory Controller and PCI Bridge User s Manual Xiv CPC710 User s Manual Chapter 1 Overview The CPC710 133 is a highly integrated host bridge device that interfaces a PowerPC 60x bus with SDRAM based system memory and two PCI ports It provides arbitration for one up to four processors and supports two levels of pipelining per processor along with 64 byte buffers The CPC710 133 memory controller supports SDRAM allowing the memory to burst data on almost every bus cycle at 100 or 133 MHz 1 1 2 1 after initial latency on Read and 1 1 1 1 on w
210. tes that the CPC710 has detected a non recoverable error condition and has entered checkstop state 11 2 CPC710 User s Manual 1 0 3 state O D Signal Name Description UO Hard Reset Indicates the device or card associated with this signal must initiate a SYS_HRESET0 3 complete hard reset All outputs should be released to tri state Duration of reset O except for device hardware system reset is controlled by software Soft Reset Indicates the processor connected to this signal will take a reset SYS_SRESETO 3 exception Occurs following a write to the CPU soft reset register CPCO_SRST that O has the appropriate bit set SYS TBE Timebase Enable Indicates the processor time bases should continue counting o Reflects bit 12 of the CPCO_UCTL12 register 0xFF001000 Normal operation when up 1 POWER D S SES General system reset when down 0 Interrupt 1 Generated after writing 1 in the PCIC1_ITADDSET interrupt register This TT interrupt can be used by an external interrupt controller The writing can be made from o the CPU in configuration mode or from the PCI64 bus Only the PowerPC CPU can reset the interrupt by writing 1 in the PCIL1_ITADDRESET interrupt reset register TTZ Interrupt 2 Indicates the end of the DMA data transfer Corresponds to assertion of bit o 4 in the DMAO_GSCRx status register GPIO0 2 General purpose UO signals 1 0 Programmed by setting bit 20 of the CPCO_PGC
211. this mode This mode also allows firmware write single bit and multi bit errors into memory to allow for ECC logic testing The CPC710 will still generate normal ECC codes when writing to memory 10 ECC check disabled Normal routing of data and normal ECC code generation The CPC710 will still generate normal ECC codes when writing to memory 11 Reserved Row Cycle Time for SDRAM Auto refresh trc Allows to fit the delay between the Refresh Command and the next Activation This delay has to be at least the tRC min value specified in the SDRAM data sheet 000 5 bus cycles 001 6 bus cycles 5 7 010 7 bus cycles 011 8 bus cycles 100 9 bus cycles 101 10 bus cycles 110 11 bus cycles 111 12 bus cycles Size Code Encoding Type For Bank 8 Select the encoding code for Size Bank defined in SDRAMO_MCERx 16 25 bit field 1 Normal mode 4 MB to 1GB Size available 0 Extended mode 4 MB to 4GB Size available 9 Reserved Must be Left to 0 10 Data Pacing Mode Must be set to 1 for SDRAM 11 Chip Select duplicated Mode 1 1 SDCS_ 0 3 signals are using SDCS_ 4 7 outputs by Multiplexing 12 Chip Select duplicated Mode 2 1 SDCS_ 0 3 signals are using SDCS_ 8 11 outputs by Multiplexing 13 Reserved Must be set to 0 6 12 CPC710 User s Manual Table 6 11 SDRAM Control Register Programming Bit s Description 44 First Multiplexing Control of SDRAM Signals SDQM 1 SDQM signals are using SDRAS1_ SDC
212. trol Register This register provides a mechanism for software to initiate a hard reset to the system The CPC710 will activate resets to all processors SYS_HRESETO to 3 and PCI devices Reset Value x 0000 0000 Address x FFOO 00E8 Access Type Write Only Generate Hard Reset 4 Y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Definition Generate Hard Reset 0 31 A write to this register will initiate a power on reset Register Summary 9 41 CPCO_SRST CPU Soft Reset Register This register provides software with a mechanism to issue soft resets to each of the processors When the CPC710 detects a write to this register the corresponding SYS_SRESET signal is driven active for a min imum time depending on the setting of bit 10 to 15 of the RTBR register see CPCO_RTBR on page 9 33 Reset Value x 0000 0000 Address x FFOO 1040 Access Type Write Only Reserved y Y 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Soft Reset Control for ARB Level 0 lt Soft Reset Control for ARB Level 1 lt Soft Reset Control for ARB Level 2 w lt Soft Reset Control for ARB Level 3 Bit s Description Soft Reset Control for ARB Level 0 0 0 Writing 0 to this bit has no effect 1 Writing 1 to this bit will initiate a pulse on the SYS_SRESETO signal So
213. ual 4 6 Deadlock Avoidance Potential Deadlock Potential deadlock situations can occur when the CPU attempts to access read or write a PCI master while at the same time the PCI master attempts to access a cacheable main memory address The PCI to memory access generates a snoop cycle on the processor bus and if that results in a cache hit the PCI master s memory access will get retried If the PCI master typically a PCI PCI PCI ISA or PCI VME bridge does not have enough internal buffering to support incoming as well as outgoing transactions or uses prioritization that requires the outgoing transaction to complete before servicing the incoming CPU s read or write a deadlock will occur Deadlock Avoidance with the CPC710 There are three ways to implement deadlock avoidance 1 For the PCI32 bus only external logic can be used with P_MEMREQ and P_MEMACK signals not recommended for new designs 2 External logic can be used with the DLK and NODLK signals not recommended for new designs 3 Use of CPC710 internal deadlock avoidance logic This is the preferred solution as it can be managed by software The DLK and NODLK pins may not be supported in future revisions and should not be used The internal deadlock avoidance circuit is active when at least one of the bits 0 1 and 16 of the CPCO_ DLKCTRL register are set to 1 and CPCO_PGCHP register bit 24 is set to 0 For each PCI bus there are six unique registers and one co
214. ul inel vu Hj ul TLT CPC710 PCI Bridge and Memory Controller User Manual SA14 2571 02 Fourth Edition September 2002 This edition of the IBM CPC710 PCI Bridge and Memory Controller User Manual applies to the IBM CPC710 PCI bridge and memory controller until otherwise indicated in new versions or application notes Copyright International Business Machines Corporation 2002 All Rights Reserved Printed in the United States of America September 2002 The following are trademarks of International Business Machines Corporation in the United States or other countries or both IBM IBM Logo CoreConnect PowerPC PowerPC logo PowerPC Architecture RISCTrace RISCWatch Other company product and service names may be trademarks or service marks of others All information contained in this document is subject to change without notice The products described in this docu ment are NOT intended for use in implantation life support space nuclear or military applications where malfunction may result in injury or death to persons The information contained in this document does not affect or change IBM product specifications or warranties Nothing in this document shall operate as an express or implied license or indem nity under the intellectual property rights of IBM or third parties All information contained in this document was obtained in specific environments and is presented as an illustration The results obtained
215. user Transfer Control Register user xFF1C 0050 x FF1C 0070 DMA0_XSSRU DMA0_XPARU Transfer Status Register user Transfer PCI Address Register user xFF1C 0090 x FF1C 00A0 DMAO_XWARU DMA0_XTARU Transfer Write Back Address Register user Transfer Translated Address Register user x FF1E 0020 XFF1E 0030 DMA0_GSCRP DMAO_XCLRP Global Control Register priv DMA Cache Line Increment Register priv x FF1E 0040 DMA0_XSCRP Transfer Control Register priv ONDAN 9 4 RO Read Only Register All bits can be read Only bits 4 31 can be written All bits can be read Only bits 0 3 can be written Four beat burst read operations allowed to this address space Single byte writes only Not decoded by system logic Byte accesses allowed WO Write Only Register CPC710 User s Manual Range that IBM Dual Bridge and Memory Controller responds to is programmable Table 9 1 System Registers List Address Name Use Page x FF1E 0050 DMA0_XSSRP Transfer Status Register priv x FF1E 0070 DMA0_XPARP x FF1E 0090 DMA0_XWARP Transfer PCI Address Register priv Transfer Write Back Address Register priv x FF1E 00A0 DMA0_XTARP x FF1E 00A4 to x FF1F FFFF Transfer Translated Address Register priv Reserved System Standard Configuration Registers x FF20 0000 Reserved x
216. uted load and store operations are complete and all resultant actions are 60x Interface 4 11 visible to the system The CPC710 satisfies this requirement by SYS_ARTRYing the SYNC operation until all of its store buffers are empty all reads have been executed and all data have been placed in internal CPC710 buffers for requests issued by the same processor issuing SYNC When a processor broadcasts an EIEIO on the 60x bus the system is responsible for ensuring all previous transactions are complete before executing operations The CPC710 does not SYS_ARTRY the EIEIO because the 60x logic dispatches bus transactions to the logic units in the order in which they occur on the system bus and each logic unit executes its commands in the order received For diagnostic purposes the CPC710 can be programmed to SYS_ARTRY the EIEIO in the same manner as SYNC see bit 10 of CPCO_ABCNTL on page 9 10 The logic units are system memory PCI 32 bus bridge PCI64 bus bridge system I O logic and DMA controller logic EIEIO operations are valid for transfers to and from the same logic unit but execution order of load and store operations to different logic units cannot be guaranteed For example a store to the PCI 32 bus bridge followed by a PCI64 store could be presented to the respective PCI buses in reverse order if a bus is busy To preserve the order among logic units software must issue a SYNC instead of an EIEIO 4 5 Address Retry SYS_ARTRY
217. ves the same sequence as a normal cache inhibited load and store with a few exceptions The processor calculates an effective address translates it and presents the resulting real address to the system bus as normal However this address bus does not select the slave The address is passed to the slave to be used on a subsequent transfer The slave is selected by a 4 bit Resource ID PCICx_REVID that is placed on the SYS_TBST and SYS_TSIZ 0 2 signals by the processor The device is selected for these transactions when the PCICx_REVID on the bus matches Configuration Register bits 8 11 in the device s System Control Register The bus transaction is always a single beat regardless of the SYS_TBST signal setting While the DMA is occurring the device monitors the bus for a TLB Sync resulting from normal page maintenance by the OS kernel to terminate the transfer Software can then restart the transfer at the faulting address The DMA Controller transfers data between system memory and PCI only It cannot perform memory to memory transfers DMA operation is transparent to the PCI adapter which behaves as a PIO slave device Although eciwx and ecowx both initiate DMA the preferred instruction is ecowx because it writes to the system bus eciwx is provided to avoid access violation errors on pages marked read only Software ensures proper implementation of the DMA operation including address alignments and page boundaries The device aborts a D
218. vice while another master is active the requesting master must generate an ABB based on SYS_TS and SYS_AACK The current master does not provide an ABB 4 2 3 2 Qualified SYS_BG Equation Use the following equation to detect a qualified bus grant using positive logic QBG SYS_BG ABB SYS_ARTRY where ABB represents the interval between SYS_TS and SYS_AACK active Bus Request SYS_BR need not be active to detect a qualified bus grant parked case 4 6 CPC710 User s Manual 4 2 3 3 SYS TS Assertion All master devices must drive SYS_TS active in the cycle immediately following a qualified address bus Otherwise the address tenure is aborted and another master is free to drive the address bus 4 2 3 4 SYS BR Negation All master devices must negate SYS_BR for at least one bus cycle immediately after receiving a qualified bus grant 4 2 3 5 Qualified SYS _DBG Equation The equation for qualified SYS_DBG using positive logic is QDBG SYS_DBG ARTRY DBB is unused because the arbiter does not issue a SYS_DBG when DBB is active The arbiter monitors transaction sizes to determine the end of a data bus tenure and waits until the previous data tenure is complete before issuing a SYS_DBG to the next master Note QDGB can only be negated by an SYS_ARTRY of the address tenure associated with the QDBG data bus tenure Therefore once the SYS_ARTRY window has passed for an address tenure the data bus tenure associated with that ad
219. vices 2 and 3 are potentially in deadlock on the PCI CONFIG access etc Register Summary 9 95 PCILx_INTACK Interrupt Acknowledge Cycle A read to the INTACK register generates an Interrupt Acknowledge Cycle on the PCI bus An Interrupt Acknowledge Transaction has no addressing mechanism and is implicitly targeted to the interrupt control ler in the system The vector is returned by the interrupt controller when TRDY is asserted on the PCI bus to the CPU waiting the Read Data Address CPCO_PCIBAR x 000F 7700 Access Type Read Only INTACK D y 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 31 This register is a port through to the PCI bus Writes to this register are ignored 9 96 CPC710 User s Manual PCILx_IOSIZE PCI I O Address Space Size Reset Value x FFFO 0000 Address CPCO_PCIBAR x 000F 7F60 Access Type Read Write PCI I O Address Space Size Reserved y Y y v 012 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description PCI UO Address Space Size X FFF 1 MB X FFE 2 MB x FFC 4MB xFF8 8 MB x FFO 16 MB x FEO 32 MB 0 11 xFCO 64 MB x F80 128 MB x FOO 256 MB x E00 512 MB x C00 1 GB x 800 2 GB x 000 4GB 12 31 Reserved Register Summary 9 97 PCILx_MSIZE PCI Memory Address
220. y bit are driven high The signal assignments correspond to the following DP 0 Data 0 7 DP 4 Data 32 39 DP 1 Data 8 15 DP 5 Data 40 47 DP 2 Data 16 23 DP 6 Data 48 55 DP 3 Data 24 31 DP 7 Data 56 63 Transfer Acknowledge Output Indicates a single beat of data transfer between the CPC710 and a master on the 60x bus For read transfers indicates the data bus is valid with read data and the master must latch it in For writes indicates that the CPC710 has latched in write data from the data bus The CPC710 asserts the signal for each beat in a burst transfer Input Indicates a single beat of data transfer has occurred The CPC710 arbiter uses this signal and the address transfer attribute signals to determine the end of the data bus tenure 1 0 1 0 SYS_TEA SYS_MCP0 3 CHKSTOP Transfer Error Acknowledge Output Indicates that the CPC710 has detected an error condition and that a machine check exception is desired Assertion of this signal terminates the current data bus tenure The CPC710 can be set up to transform any SYS_TEA to normal SYS_TA with machine check condition signaling on SYS_MCPO SYS_MCP1 SYS_MCP2 or SYS_MCP3 Input Informs the CPC710 60x bus arbiter that the current data bus tenure has been terminated Machine Check Indicates that the CPC710 has detected an error condition and a machine check exception is desired External pull up is required Checkstop Indica
221. y y y y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description Enable PCI Control Space 0 PCI Bridge only responds to configuration cycles The other access to CPCO_PCIBAR are Inhibited Normal mode 1 PCI Bridge responds to address space specified in the CPCO_PCIBAR register PCI configuration phase 1 3 Reserved 4 31 Reserved Register Summary 9 25 CPCO_PGCHP Chip Programmability Register The bits in this register are used to disable certain errata fixes and also allow for selection of additional functions such as the PCI mapping in Flexible PREP or CHRP mode Reset Value x 0000 0000 Address x FFOO 1100 Access Type Read Write 5 wi m 2 2 3 3 5 a Q 3 2 o c Q o gt vo E o gt gt c c lt lt o z E E S S oS g E S 3 2 o 2 w w 2730 5 Pi 3 2 o ce 2 2 bs E EE o a E 96 o W S S Wa o 2 vn 3 o o UI o A O vo o EC D mn E ny ZS S oo e es 8 O O ul 2 0 5 2 SS A o o bd o 0 E gt bi gt gt BOB x o o o 5 a O gt gt O o n E Ee vo go Z lt x lt x lt s 8 oo n a 2 o o 2 O 2L zs Oo D gt e 2c o o co 120 CG SH Zoe D D o uw c O D D oO DG H Te O lt 0 O o a D ED o Bs 3 ES 2 s 5 a ZS Ka EE E E 2 o S E E 2 g Suwa ai gt 05833 E ES Ss E 2 e ss FE G c e O oO O o Gi Gi Z oo ts BE G D 6 Dm be a LI D e e
222. z o D O c Ka is o Es o S 2 a Le 3 S 3 2 o Bi 2 a o a g 5 a g 5 a g 5 S 3 o S E o S 3 o E 4 E gt d E E N gt as y gt g gt S N No o N N 2 X Y D E o o o E D o E o o D E E GR e is ES x H G v om vn 2 o o nm g om o o E gt gt gt 8 gt gt gt gt gt gt 2 o o no Zo oa on a o Zo Go or y LE ALL yr yyy yr yo y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit s Description 0 4 SYS_TT 0 4 Values for flush operation 5 7 SYS_TSIZ 0 2 Values for flush operation 8 SYS_TBST Value for flush operation 9 Reserved 10 14 SYS_TT 0 4 Values for kill operation 15 17 SYS_TSIZ 0 2 Values for kill operation 18 SYS_TBST Value for kill operation 19 Reserved 20 24 SYS_TT 0 4 Values for clean operation 25 27 SYS_TSIZ 0 2 Values for clean operation 28 SYS_TBST Value for clean operation 29 31 Reserved Register Summary 9 13 CPCO_ATAS Address Transfer Attribute for Snoop Register Programming the CPCO_ATAS Address Transfer Attribute for Snoop Register When the CPC710 100 generates the following snoop cycle with TT signal on the 60x bus the PowerPC 750 takes no action In contrast to the PowerPC604 the PowerPC 750 does not handle cache system memory coherency TT 0 4 OperationAnswer from the PowerPC750 TT 0 4 Operation Answer from the 750 00000 Clean Sector No action 00100 Flush Sector No action

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