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Service Manual - EVDT Model 4309

1. T3 i SELECT UNOZELINE ATTRIBUTE POSITION LINE 9 JMFB SS SS ed A dM B pi L L JMP9 OPEN v SELECT Ou BOAKC BATTERY LUMPS C2 0 SELECT EXTERKAL BATTERY 8070 59 Figure 6 2 logic Diagram Main Logic Board PCBA Sht 1 of 12 903385 Rev A C i in C BFISD 8070 Table 6 2 EVDT to Serial Printer Interface Signals I O Port B continued CONN PIN SIGNAL SOURCE DESCRIPTION GND EVDT Printer Signal Ground common return RTS EVDT Request to Send Indicates to printer that data is ready to be transmitted Printer Clear to Send Indicates that printer is ready to accept data from EVDT 6 33 34 BFISD 8070 IXP penn ae e ko BE A END je 7 36 2 PeP ga 4 STS 36 26 xA i NM Figure 5 2 Logic Diagram Main Logic Board PCBA Sht 2 of 12 903385 Rev A C PRO ie 13 Th PD BFISD 8070 ADA par Hi L QZ L app 799788 pwa t ERTE TALSSAB 2 PR FAS ADC 3 SIOE 13 app pog A CTEEZ p a 1 pos Is LIS Pp PAT i n poe Nc pe Poz PAG id E NG PAS 908 gt NC Isi seLect FAB gsT ppo LINTEN PA KEYLD WIDB CINELD MOCTS BRITLD PDS Floran ATTLO
2. 2 40 BFISD 8070 Table 2 14 Character Size Attributes continued HEX ATTRIBUTE ESCAPE SEQUENCE DESCRIPTION Double High ESC F 5 Top Half 46 35 The escape sequence ESC F 5 or Line ESC F D Bottom 46 44 ESC F D causes the line with the Half active cursor position to become the top or bottom half respec tively of a double high line The escape sequences must be used in pairs on adjacent lines as the same character output is sent to both lines to form the double high character Double High Line Alter nate Method Double high characters can alternately be generated from normal size or double wide char acters after the characters have been entered The following sequence is an example of how to generate double high double wide characters using the alternate method ESCAPE F 3 Double Wide then Desired Characters then ESCAPE m Double High 2 10 5 Function Key Programming The Programmable Function Keys Fl thru Fl4 and F15 thru F28 when SHIFTed may be individually programmed to store user selected commands in continuous memory The stored commands are executed by pressing the key selected for each command The Programmable Function Keys are associated with a 300 character data buffer which allocates a maximum of 77 characters to each key Commands with char acter strings exceeding 77 characters may be stored under two or
3. AND ARE USED WITH KEY TO CONTROL DISPLAY BRIGHTNESS SHIFTS NUMERIC KEYPAD FOR USE OF te AE OMT Lone zs IS DISPLAYED ON STATUS LINE WHEN f LOCK PAD EIO OA ee a AND SET F ARE USED WITH THE FUNCIKEY TO SHIFTS ENTIRE 0 STORE CHARACTER STRING COMMANDS FOR THE PROGRAMMABLE ET 28 AND TO EXAMINE THE CASE SF SHIFT LOCK IS DISPLAYED FON NIS ESO tae ON STATUS LINE CTRL USED WITH OTHER KEYS TO GENERATE TRANSMITTABLE CONTROL CODES USED BACKSPACE CAUSES CURSOR TO MOVE ONE P ALSO TO PRODUCE LOCAL CURSOR CONTROL RESTE CAUSES ANY CHARACTER THAT EXISTE AUX CHAR IS NON FUNCTIONAL AND WILL EMIT AUDIBLE CODES AND TO INVOKE TERMINAL SELF IN THAT POSITION ERROR TONE WHEN PRESSED TESTS SPACE BAR ADVANCES CURSOR ONE SPACE TO I CARRIAGE RETURN OR CR DEPRESSION THE RIGHT EACH TIME BAR 15 TYPED ANY OF THIS KEY INDICATES THAT ENTRY OF A PARTICULAR CHARACTER UNDER CURSOR IS REPLACED BY A PIECE OF INFORMATION HAS BEEN COMPLETED UPON SPACE HOLDING BAR DOWN PRODUCES A CERTAIN CONDITIONS RETURN MUST BE PRESSED BEFORE CONTINUOUS STRING OF SPACES UNTIL RELEASED THE COMPUTER ACCEPTS DATA TYPED ON THE KEYBOARD IN RESPONSE TO PROMPTS AND QUESTIONS DISPLAYED ON THE SCREEN THIS KEY MAY USED TO INDICATE THAT SHIFT MUST BE HELD DOWN WHILE AFFECTED THE USER CHOOSES THE DEFAULT VALUE KEY IS TYPED ENABLES UPPER CASE ALPHA CHARACTERS AND SYMBOLS AS WELL AS
4. COLE ge i 00 8070 67 x I Figure 6 2 logic Diagram Main Logic Board PCBA Sht 9 of 12 903385 Rev A BFISD 8070 PO vi BLINKEK 226 225 Ze LK 2 2 NC 224 RETRACE 208 VEYMEZ 2 7405393245 1 ue FAB D 227 FAB BEITLO FONCK XPE 03 3 VIDIN 23 8 14886 746 URAR HEX IE 2v 2 3 202222 LED BLINKCK 13 Ed m sA OPTIONAL sun 1732 1 AER ATE VID 3 Di Qs BEA 4 22 z JE ME 2 24 ad COMP VIREO SEE OPTIONAL goner als AY yp ak D ab z 22 HEINT 2 492 ry VIP 33 wc L L uc 5594 52 74596 74586 5 Sy 7445273 74518 dcte SvMCYC if CLK 3 4 e 74 S94 ROWLE gt CA fe n Fae t QU UMP TAR HR MN SNOW 8070 68 Figure 6 2 Logic Diagram Main Logic Board PCBA Sht 10 of 12 903385 Rev A 8070 69 2 74 9 393 ADET 57 BA L K The POL S548 Evae DEZE 5V KEYOUT II KEYBOARD CONNECTOR TOROID BiG EE 7415165 zr ommo Figure 6 2 BFISD 8070 1 Logic Diagram Main Logic Board PCBA Sht 11 of 12 903385 Rev A 6 25 26 BFISD 8070 22 GNO
5. Screen Memory lt au a a a o Screen Memory Arbitration Logic MPU Access Timing Typical Video Display Format au a a a a gt Vertical and Horizontal Timing Relationship Character Generation e e w a a a e au a a a o Parallel To Serial Conversion e s lt a w a n Single Height Character Timing e e s a au a a e n Double Height Character Timing e e au au a e a e Double Width Timing e e e e a a w w a a gt Composite Sync e e s e a a a o Keyboard Matrix Code Transmission a a a a n DART Block Diagram e e s gt o X e e e e e e o Matrix Code Demodulation Timing e a a a n Simplified Firmware Flowchart a a e a a n POSTI e sbs ba NO NNNNRNNNIN ER Ut A 0 CO Co OF NN I l l Py BFISD 8070 LIST OF ILLUSTRATIONS continued Figure Page 4 1 Troubleshooting Flowchart e e e a a a 4 3 4 2 DC Voltage at Connector Jl e e s w w 4 26 4 3 Location of Monitor Board Controls e ao 4 8 4 4 CRT Yoke Adj stmettSs e e e s e s e s s e s o o 4 10 4 5 Monitor Board Waveforms e a a e a e 4 12 5 1 EVDT Video Display Assembly e w a e un 5 8 5 2 EVDT Keyboard Assembly s a e e e e e 5 10 5 3 Main Logic Board PCBA e s lt de mo woe o w 5 12 5 4 Monitor Board PCBA e e s ses s s e oe
6. o o s o o o o os 3 30 6 8 1 Character Generators e w w s s o 3 32 6 8 2 Parallel To Serial Conversion e e e 3 32 6 8 3 Line Scan Counter e lt lt 4 yo 3 33 6 8 4 Line Attribute Buffer e e e e e lt s ae 3 34 6 9 Composite Sync and Video Circuits 3 38 6 10 Keyboard Interface e e e e eooo oo e o 3 41 6 11 Counter Timer Circuit CTC e s 3 43 6 12 Dual Asynchronous Receiver Transmitter DART 3 44 6 13 Keyboard Logic e s lt s s e we a a so o o o 3 48 6 14 System Firmware a w lt a a a a a w os 23 50 iv BFISD 8070 TABLE OF CONTENTS continued Page SECTION IV MAINTENANCE Introduction e e e e e e e e e Preventive Maintenance e e a a a a a a a a a a Trouble Analysis e e e e 4 1 4 1 4 2 4 1 4 3 4 1 4 3 1 Troubleshooting Procedures e e lt w a a e 472 4 3 2 Troubleshooting Guide e w w a a 474 4 3 3 Fault Isolation e lt lt e vee e e e e e e e o 476 A 3 3 1 DC Voltage Checks a 4 39e wo eue ve BRO 4 3 3 2 Monitor Board Video Adiustucdbs UE ah eae GET 4 3 3 3 Monitor Board Signal Tracing e w a e 4 11 4 3 3 4 EVDT Diagnostic Test e a a a au a a u 411 4 3 3 5 BASS System Level Diagnostic Tests e
7. zc2 Sy A DART ze GN 653 a m 18 EKETE 8 2 fV TXDA pTEX KTSA T6A PTRA PCPA expe BELL Figure 6 2 Logic D xc8 iagram Main Logic Board PCBA Sht 4 of 12 903385 Rev A 6 11 12 8070 63 FAIZ PAG PAB BuT PAG FAS PA4 FAZ PAR PRO 22020 17 09 io IB 1507 14 13 15 ii 03 1 012 2300 E meee PCO mses 2 ED users 8020 0 PROGRAM ROM 2132 t1 4x4 S J ns 07 De os p3 BI 9c 745288 Y 448 R22 CA 828 cre i L IN4162 Tape 8 6v CRIA iN 4B 2582222 2 7 I 2 BFISD 8070 4 5 RESET 741514 7 94 LZK z 1820 F 4 ce W O 94 waz o He ta i2 23 11 DG PA 21 9 vecX 28 ig A9 24 22 L FAS 15 23 vec 24122 PAT 3 Fa A 2 HMeheLP4 12 C4 zem GE vas T PAL 4 11709 ES fA3 5 Te Ga pe PAZ 8 6 1507 DS PAL 9 i4 06 6 08 VI PAR 1202 D PRD 22 10 9 0 D Figure 5 2 Board PCBA see EN ann Logic Diagram Main Logic Sht 5 of 12 903385 Rev 6 13 14 BFISD 8070 oppe lt lt lt MO gt gt p P gt
8. 0 when Program Memory is selected PMSEL 0 as in an instruction fetch The internal logic devices do not use the Bus Request input to the MPU BUSREQ Consequently BUSREQ remains high since it is tied to 5V and BUSAK cannot be activated However the Bus Request and Bus Acknowledge signals are connected to the Expansion Connector J4 such that if an external device for example a DMA Controller were to share control of the buses the signals would be activated accordingly A non maskable interrupt NMI occurs when NMI goes low Sheet 9 This occurs at the start of each character line raster line when so enabled by the MPU LINTEN l line interrupt enable It is inhibited during the frame flyback period retrace by VSYNC and when the line scan counter overflows i e when it produces a ripple carry output The MPU is interrupted INT goes low by either the CTC 5C or the DART 4C Both devices are shown on schematic Sheet 1 The interrupt priority is deter mined by the daisy chain configuration In this case the CTC has higher priority since it is the first device to have its Interrupt Enable In IEI line tied to 5 volts In turn its Interrupt Enable Out IEO line provides the IEI line to the DART which is the next lower priority device The DART IEO line is routed to the expansion connector J4 Sheet 12 When an interrupt condition occurs in the CTC its INT output goes low and its IEO line goes low preventing
9. 1W Z1 5 23 BFISD 8070 213 6 ie d sz Keyboard PCBA Figure 5 6 5 24 BFISD 8070 Table 5 6 Keyboard PCBA REFERENCE PART NUMBER DESCRIPTION DESIGNATION 65 02547 001 Keyboard PCBA International 65 02547 002 Keyboard PCBA Domestic 32 00333 004 Cl C2 C4 C6 C8 C9 Cll C17 Capacitor 0 03 uF 27 00220 006 Capacitor 22 pF C3 28 00470 004 Capacitor 47 pF C5 28 00102 004 Capacitor 470 pF C7 28 00221 004 Capacitor 220 pF 32 00106 010 Capacitor Electrolytic 10 uF 39 00585 000 Connector Keyboard Cable Resistor Pack 33K 8 places Resistor 11K RI Resistor 62K R2 Resistor 680 ohms R3 Resistor 3 3K R4 R5 R6 R R8 Resistor 82 ohms Resistor IK R9 7404 003 IC Hex Inverter 74LS04 Z1 7400 003 Z2 IC Quad Nand Gates 74LS00 74123 003 IC Dual Monostable Multivibrator Z3 7415123 7493 003 IC 4 Bit Binary Counter 74LS93 Z4 7474 003 IC Dual D Type Flip Flop 74LS74 AD 22 00900 000 IC Proprietary Z6 22 04051 000 IC Proprietary Z7 74164 003 IC 8 Bit Serial to Parallel Shift 28 Register 7415164 5 25 BFISD 8070 Table 5 6 Keyboard PCBA continued REFERENCE PART NUMBER DESCRIPTION DESIGNATION 74138 003 IC 3 to 8 Line Decoder 7415138 29 710
10. 2 24 i26 7415273 D TALSSAI id 27 adio 7425 38 B ie MH ade y TALS273 26 Ad 74 C T 4 7405773 wp 3 7asies 8 l B 749 68 8 ie LL dM 745157 8 ie 8 745 87 8 fl 4 fast 7 v fia 51 7732 7764 10 4 tid 7415273 iQ 20 SE 73 1168 12 4 14 18 28 7737 9764 GE HMelle 12 1 74 5745 74 5941 Ka 74 5773 745273 i 72 19 26 BAT 2d Te 7415313 i HL 1 ALS 1 GNO 41 12 i t4 VUMPER TABLE FUNCTION iZ OPTIDMAL PAGING RAM VCC 4AcHAD JMPI 2 3 i Nok OPTIONAL PAGING RAM VCC AA MAD 2 a GAK OPTIONAL PAGING RAMAVDD 4 JMPT 2 3 ie K OPTICHAL PAGING EAM VOP AA TIA we iz G4K OPTIONAL PAGING RAM VEB MAA JMPS 3 OPTIONAL PAGING KAM YEB AA LIA JMP 4 1 7 SELECT AK CMOS NON VOLATILE KAM GE 7 3 wo SELECT ZK CMOS NON VOLATILE RAM GE JMPS 3 2 4 SELECT ZKriMOS SCREEN RAM 46 4 LOCATION L MET t GND dieg i MPS _11 3 3 4 SELECTA i MOS SCREEN RAM 146 141 IMPE we y ZTO CHARACTER GENERATOR EFROM ide L osdPe 3 TG CHARACTER GENERATOR EPEOM UME T SELECT UURERUINE ATTRIBUTE FOSITIOU UME d
11. 24 x 80 character display on non glare green phosphor CRT screen Easy to read 6 x 9 dot matrix characters with tenth dot for lower case decenders 18 key numeric keypad with cursor control keys Block Mode editing and transmission control using ESCAPE FUNCTION and standard typewriter keys Selectable display attributes for characters line or lines and or full page reverse video blinking underlined reduced intensity and com binations thereof Business graphics characters 44 line graphics characters Special function keys used with FUNCTION key to control display con figure terminal options program function keys and to change terminal mode of operation Self test functions tests ROMs RAMs and LSI device registers keyboard selectable Personality modification escape and control sequences modifying default value of control characters used in terminal operation Designated protected fields character fields are displayed at reduced intensity and cannot be overwritten N key rollover protection Programming troubleshooting display modes text from keyboard or host CPU displayed with control characters permits simplified data insertion and monitoring All EVDT data entry display and input output operations are performed under microprocessor control Data is transmitted from and received by the host CPU via serial device I O controllers PCBAs installed in the CPU card cage BFISD 8070 1 2 EVDT DESCRIPT
12. 400436 001 Keycap Kit Italian 400437 001 Keycap Kit French 400438 001 Keycap Kit Swedish 400439 001 Keycap Kit German 400440 001 Keycap Kit Norwegian 400441 001 Keycap Kit Danish 400447 001 Keycap Kit Domestic 400448 001 Keycap Kit Spanish 61 04031 001 Keyswitch Domestic RETURN Key Right Side with pad no spring 61 04031 002 Keyswitch Domestic RETURN Key Left Side with standard spring no pad 61 04024 001 Keyswitch Standard 92 Places 45 00053 030 Spring Keyswitch SPACE Bar 45 0005 3 070 Spring Keyswitch ESCAPE CLEAR and PRINT Keys 45 00053 015 Spring Standard 88 Places Domestic 89 Places International 5 26 BFISD 8070 SECTION VI REFERENCE DATA Logic Diagram Keyboard PCBA Logic Diagram Main Logic Board PCBA Schematic Diagram Monitor Board PCBA Input Output Diagram Power Supply PCBA EVDT to DCE Host CPU Interface Signals I O Port A EVDT to Serial Printer Interface Signals I O Port B 6 1 2 BFISD 8070 JGOAZI ON9 JOASG JGOAZI V82d AlddNS u3MOd NOILISOd JWAOZI OO NMOHS 33 I NI dWAC Input Output Diagram Power Supply PCBA Figure 6 4 6 31 8070 58 BFISD 8070 45V ENABLE dk PU po 53 28 00470 004 tB asec vil 3
13. 925 vist oa 9157 2 G Cram J Ca Caz aa u Car 4 STO 26157 925 EEES 1 ncm onn ca want i 1187 sis ET 21157 AW 0 Can an w a es 992 5 L d a CA sann Cas Cos st d 3 2 aka Caen oe 2E42 Ce LI ann 9157 6 257 31 4257 4 59151 E 2 k s plat Lisa E 9 LJ 4 9 4 6 o L 2e 971 MADE IN USA PCB 904733 001 REV 8070 54 Main Logic Board PCBA Figure 5 3 5 12 PART NUM 9033 13 001 101709 101710 101541 101316 101711 101712 101672 101714 101741 101657 101719 1611 14 001 161112 001 161023 161013 161028 101613 101612 162002 002 162001001 161105 001 162035 001 101537 165C16 001 161107 001 101656 101543 101629 101673 101783 101633 101642 101721 161066 001 165017 001 161113 001 161110 001 161109 001 132014 001 111000 107 111000 048 111000 008 111000 052 111000 011 111000 060 111000 030 119001 003 103000 004 104007 001 u UJ Un Po aue D m m O O Q UA AN ge deo pas 209 ne N P lt w Table 5 3 Parts List Main Logic Board PCBA PART DESCRIPTION am OP x AD GN CEP s Qe Qm SERED sta Qs aa UO aE eS ame Qm s lt m a LCGIC T4LS00 QUAD 2 IN NAND T4LSO2 QUAD 2 IN NOR T4SU4 INVERTER HEX 74
14. In the case of a Write operation SWR is activated by the control ROM and information on the Data Bus PD7 PDO is written into the selected location When SMCYC goes low the second flip flop is cleared and MPU access operation terminates The default condition is with both flip flops cleared in which case screen memory is addressed from the outputs of the Address Generator SAl1 SA0O The Q output of the second flip flop is now high and remains high until the MPU selects Screen Memory again In this condition SWR cannot be generated since the control ROM does not activate a write enable pin 6 low During screen refresh operations only read cycles are enabled When SMCYC goes high the information read from the addressed location is clocked into buffer registers 12G and 12J Both data and attribute memory are read simultaneously during a refresh opera tion such that SBCEO and SACEO or SBCEl and SACEl are activated by the control logic SMCYC loads the data and attribute information into the two registers 12G and 12J 3 22 BFISD 8070 CKCPU 0 15 PMREQ PRD SMSEL SMCYC SMCYC 14C 5 SMWAIT 14C 6 14C 9 14C 7 Figure 3 9 Screen Memory Arbitration Logic MPU Access Timing 3 6 6 CRT Controller The CRT Controller CRTC is a Model 6845 CRTC manufactured by Motorola The pin out list is provided in table 3 2 and the CRTC is shown on Logic Diagram Sheet 10 The CRTC is used in a lim
15. cursor moves to HOME or next unprotected position on screen Line Feed Moves cursor to next lower line in same column position or to next unpro tected position in new line or next line if necessary Up Line Moves cursor to previous line in same column position or to next unprotected position moving from left to right in new line or next line if necessary Forespace Moves cursor right to next un protected position on same line or on next lower line moving from left to right Return Moves cursor to first unprotected position in line containing the cursor In dicates that data entry or data transmission is complete Turns line over to host Escape EVDT code extension character must be followed by otherwise displayable char acter s to invoke a specific terminal oper ation Also used preceding a control code to cause the control code to be displayed instead of acted upon HOME Moves cursor to first character posi tion on screen If HOME is protected cursor moves to first unprotected positon on Screen New Line Causes a combined Return CR and Line Feed LF to be executed Moves cur sor to first unprotected position on next line BFISD 8070 2 9 3 Self Test Control Codes The EVDT uses some otherwise standard control codes as internal self test control codes The self test control codes may be generated at the keyboard only and only when the EVDT is in the Block Mode The Self Test Mo
16. er zi jes Bu ee a eT 7 HB UEM PUN Ye NS 624 GZB a A 62 Gib C 8 A L5138 21D 5138 2 Oy Sume o EAN bo ct 20 4 o8 3 004 Q S wo 43 Te Ta n 9 H5 13 n2 E E 7 iis u 2 LI 528 1 40121 153 zo EJ BABE ze i i ye mn 452 180 e3 7 91 zy Ni Mo 17394189 5 59 24177 4 100142 90 FN Sky Soor LILI e5 29 84 30 48 85 vl de gu pl INE 87134 74 155 89 5 4 lez 2 58123 25 si do eoim B5 16 ken m en ezite s an mE l s fas ot W Hi H ee m z m 92 uu par d TIE de d nxt f BIK AK CAD LOO Dese BG aw Cua RA G33uF SK 32 00333 004 Ipo 6 e V mE AT T Ces 59 CA Epler E 9 LG LS DHT i EMO T Ji THIS DIAGRAM I REVISION LEVEL a W i i Logic Diagram Keyboard PCBA 6 3 BFISD 8070 Table 6 1 EVDT to DCE Host CPU Interface Signals I O Port A CONN PIN SIGNAL SOURCE DESCRIPTION None PROT EVDT DCE Host Protective chassis ground GND J5 2 TXD EVDT Transmitted Data Serial data transmitted to DCE Host J5 3 RXD DCE Host Received Data Serial data received by EVDT J5 4 RTS EVDT Request to Send always true In dicates to DCE Host that data is ready to be transmitted Clear to Send Indicates that DCE Host is ready to accept data from EVDT EVDT DCE Host Signal Ground common return DCE Host Data Ca
17. the 5 volt output is supplied to the keyboard assembly The mounting bracket for the Power Supply PCBA includes a male power cord receptacle and a power on off switch both of which are accessible at the rear of the EVDT 1 3 SPECIFICATIONS Specifications for the Model 4309 EVDT are listed in table 1 1 Table 1 1 Specifications Model 4309 EVDT PARAMETERS CHARACTERISTICS PHYSICAL Video Display Assembly Height 12 inches 30 5 cm Width 16 inches 40 6 cm Depth 13 8 inches 35 1 cm CRT Screen Size 12 inch 30 5 cm diagonal measure Keyboard Assembly Height 1 5 inches 3 8 cm Width 17 8 inches 45 2 cm Depth 7 6 inches 19 3 cm Shipping Weight 26 pounds 11 8 kg Keyboard and Display Assembly AC POWER Voltage 100 120 VAC or 220 240 VAC ranges jumper selectable Current 1 0A 100 120 VAC 0 5A 220 240 VAC BFISD 8073 BFISD 8070 Table 1 1 Specifications Model 4309 EVDT continued PARAMETERS CHARACTERISTICS AC POWER cont d Frequency Power DC POWER Voltage Tolerance Current Noise and Ripple ENVIRONMENTAL Temperature Humidity GENERAL Data Terminal Type Microprocessor Main Memory Firmware Memory Continous Data Memory Display Memory Screen Memory Attribute Memory Character Generator Memory Display Format 50 60 Hz 40 watts maximum 12 VDC 12 VDC and 5 VDC includes 5 volt battery backup for CMOS RAM 10 12V and 5 5V 1 2A 12 VDC 0
18. underlined Blinking reverse video Reverse video blinking underlined Reduced intensity Underlined reduced intensity Blinking reduced intensity Underlined blinking reduced intensity Reverse video reduced intensity Reverse video underlined reduced intensity Blinking reverse video reduced intensity Reverse video blinking underlined reduced intensity 0 1 2 3 4 5 6 7 8 9 A B D E F 2 10 4 Selecting Character Size Attributes The available character size attributes and the escape sequences required for their implementation are listed and described in table 2 14 Table 2 14 Character Size Attributes HEX ATTRIBUTE ESCAPE SEQUENCE CODE DESCRIPTION Double High ESC F 7 Top Half 46 37 The escape sequence ESC F 7 or Double Wide ESC F F Bottom 46 46 ESC F F causes the line with the Line Half active cursor position to become the top or bottom half respec tively of a double high double wide line The escape sequences must be used in pairs on adjacent lines as the same character out put is sent to both lines to form the double high double wide character The use of this fea ture reduces the number of char acters per line by half Double Wide Line ESC F 3 46 33 The escape sequence ESC F 3 causes the line with the active cursor position to contain double wide single height char acters The use of this feature reduces the number of characters per line by half
19. 0 ROM 1 select Font l ROM Font 1 The line scan counter bits CAO CA3 are constant for the duration of a complete horizontal line scan whereas the data bits 500 506 from screen memory change eighty times during the same period assuming the MPU is not accessing screen memory As the ROM address changes the new information appears at the ROM outputs noting that the outputs of the ROMs are connected together on a bit for bit basis OR connection The information is transferred from the ROM outputs to the parallel to serial converter 3 6 8 2 Parallel To Serial Conversion The parallel data from the character generator dot matrix code is converted into a serial bit stream by the shift registers 7G and D type flip flop 4G The shift register is parallel loaded by CWRLD 0 coincident with the next DOTCLK When CWRLD goes high the register is enabled for shift operations which ocur coincident with the positive going edge of DOTCLK The data bits are shifted out via pin 13 Q The serial input to the register is tied to ground so that as data bit is shifted out a zero bit is shifted out The bits are shifted out in descending order most significant first least sign ificant last which happens to be the most significant output of the character generator D7 The output flip flop 4G effectively inverts the data output from the shift register noting that if the output is zero the flip flop is immediately cleared and if the output
20. 18 which depicts a matrix code of alternate ones and zeros The MPU places the matrix code on the data bus and performs an I O operation to the keyboard interface whose address is decoded by KEYLD When KEYLD goes low the matrix code is parallel loaded into shift register 10B which functions as a parallel to serial converter When KEYLD goes high the first of flip flops 13C is clocked into the set state The second flip flop is held in the clear state during the time that counter output 12C QD is low and cannot be clocked into the set state until 12C QD goes high When this occurs the next positive going edge of counter 12C QC sets the second flip flop which immediately clears the first flip flop The second flip flop remains in the set state for the remaining period that 12C QD is high This allows 8 CKC80 clocks to be gated through And gate 11G 11 as shown in figure 3 18 If the output of the shift register is a one bit 10B9 1 then Nand gate output 10J 6 goes low for one half CKC80 clock period as shown If the out put of the shift register is a zero bit 10B 7 1 then Nand gate output 10J 12 goes low otherwise 10J 8 is low This output is inverted twice to provide KEYOUT the serial data output to the keyboard logic The first in version is used to clock the shift register which coincides with the negative or high to low transition of KEYOUT The serial bit pattern shown in figure 3 18 which represents alternate ones and z
21. AC outlet Figure 2 3 Keyboard Cable Connection Model 4309 EVDT 2 6 BFISD 8070 4 Verify that the POWER ON OFF switch on the display assembly rear panel is in the OFF position see figure 3 4 Connect the EVDT power cord from the receptacle on the display assembly rear panel to the designated AC outlet 5 Connect the appropriate interface cable table 2 1 from PORT A figure 2 4 to the serial I O controller PCBA or I O connector at the host CPU see figures 2 5 2 6 or 2 7 and 2 8 6 From PORT B figure 2 4 connect the interface cable table 2 1 to the serial printer I O connector figures 2 5 2 6 or 2 7 and 2 8 Figure 2 4 Video Display Assembly Rear Panel Model 4309 EVDT 2 7 BFISD 8070 801C AUTODIAL OUT J9 NE es MODEM 907115 XXX 50 60HZ MOD 4309 906274 VAR 60HZ SERIAL EVDT E 906694 VAR 50HZ PRINTER SEVEN 7 EVDT PORTS J3 RS 232 l 907115 XXX 50 60HZ MOD 4309 5 906274 VAR 60HZ SERIAL J7 EVDT 906694 VAR 50HZ PRINTER N8 WAY CONTROLLER 38 PCBA I REMOTE MODEM DEVICE 8070 07 Figure 2 5 EVDT to System 810 Interface Cable Connections 906041 VAR 60HZ MOD 4309 906274 VAR 60HZ SERIAL 906993 VAR 50HZ EVDT 906694 VAR 50HZ PRINTER EIGHT n 8 evot J 99 PORTS J4 RS 232 8 CHANNEL TERMINAL 906041 VAR 60HZ MOD 4309 906274 VAR 60HZ SERIAL CONTROLEER 37 906693 VAR 50HZ
22. AC line is not subject to voltage variations greater than 107 or frequency variations greater than 0 27 The AC power outlets are within the proper voltage range 100 120 VAC 50 60 Hz or 200 240 VAC 50 60 Hz as applicable and near enough to the equipment so that power extension cables are not necessary Re fer to paragraph 2 3 3 2 3 2 Ground Checks 1 Verify that power is not applied and the line is not connected before making the following checks CAUTION Only three wire electrical outlets and three pronged plugs with the third wire connected to earth ground are acceptable electrical connectors NO two wire outlets or plugs with or without connection to a conduit ground are to be used Unstable equipment operation may result Check that the AC line includes a third wire earth ground that meets or exceeds the requirements of the National Electrical Code This can be checked as follows ae Locate the circuit breaker that is to supply power to the EVDT With a digital voltmeter set to measure 20 volts AC and the circuit breaker turned ON measure the drop between the green and white wires at the power source wall outlet The measured voltage must be less than 1 8 volts AC Set the source circuit breaker to OFF Measure the resistance between the green and white wires at the wall outlet The resis tance must be less than the value shown below for the circuit breaker rating Circuit Breaker Rating
23. Active low input from MPU If RD is active a memory or I O read operation is in progress Receive Data Inputs High one bit low zero bit Reset input active low Disables both receivers and transmitters forces T X DA and T X DB marking high Forces modem controls high and disables interrupts Request to Send Active low outputs When the RTS bit is set in the associated Write Register RTS goes low It is used to interrogate the receiving device at the end of the communication line in noti fication of a pending transmission If the outer device is ready it activates its DTR output Data Terminal Ready which appears at the DART end of the line as CTS Clear to Send Transmitter Clocks Inputs from CTC Transmit data changes on the falling edge of T X C Clocks may be 16 32 or 64 times the data rate however they must be the same as the receive clocks Note that T X CB pin 27 is also the R X CB input Transmit Data Outputs High one bit or marking low zero bit or start bit Wait Ready Outputs Not used 3 47 BFISD 8070 3 6 13 Keyboard Logic The keyboard logic is drawn on a single diagram which is provided in Section VI The diagram shows the key matrix consisting of eight rows YO Y7 and 10 columns X0 X9 two strobe clock generators U3 the timer Ul the serial parallel converter U5 the BCD decimal decoder U4 the row scanner U6 and the output latch U7 Pulse width modulated data mat
24. BUSINESS f CURSOR GRAPHICS DATA MM 7 Bou L READ DISPLAY I CURSOR 2 PERSONALITY E DOES d m n 1 Multiple Characters Required 2 Initiated From Host Only Figure 2 20 EVDT Escape Sequences 2 29 BFISD 8070 2 9 5 Special Function Codes and Operating Modes Special function codes are those modified ASCII codes or control signals generated when using the key with any key designated as a special function key Several of the special function keys bear legends according to their special additional function These include PAD EXAM F SET F CLEAR BRITE and DIM as described in figure 2 11 Other special function keys bear no legend as such These include the numeric keypad key used_to invoke the Setup Mode the key used to invoke the Block Mode and the S key used to invoke the Conversation Mode default condition at powerup The operating modes selected through use of special function keys are summarized in table 2 5 Additional special function keys that bear no legend are those keys used for data editing transmission and printing operations These operations each of which is described in subsequent paragraphs use the special function codes listed in tables 2 6 thru 2 8 NOTE The use of the special function keys listed in tables 2 6 thru 2 8 is enabled by the escape sequence ESCAPE CLEAR 5 To enable only those special function keys discussed in para graph 2 9 5 en
25. Board adjustments are performed Rotate BRIGHTness control VR clockwise until raster is visible on the screen see figure 4 3 Adjust from back side of Monitor Board Back off BRIGHTness control until raster on screen decreases to a faint image Rotate contrast CTRS control for desired brightness level of letters on the screen Adjust from back side of Monitor Board 4 7 BFISD 8070 ADJUSTMENT FROM FRONT SIDE ALL OTHER ADJUSTMENTS TO BE MADE FROM BACK SIDE VR5 VR3 The KORIZ VERT d bw CENTER HEIGHT VERT LINEARITY Q EARITY CONTRAST VR7 BRIGHTNESS L3 HORIZ LINEARITY VIDEO BOARD FRONT SIDE INSIDE VIEW OF TERMINAL VR4 VERT VR1 LINEARITY O CONTRAST VR7 O BRIGHTNESS VR6 O FOCUS L2 HORIZ WIDTH L3 HORIZ LINEARITY VIDEO BOARD BACK SIDE OUTSIDE VIEW OF TERMINAL Figure 4 3 Location of Monitor Board Controls 4 8 10 ll 12 13 14 15 16 17 BFISD 8070 Rotate horizontal H CENTER control VR5 to center the video horizontally in the raster Adjust from front of Montior Board Loosen yoke locking screw see figure 4 4 Turn the yoke for horizontal alignment of the display no tilt Tighten yoke locking screw Adjust the two deflection centering tabs on the back of the yoke rotate either direction to center the raster on the screen Decrease the BRIGHTness control VR7 until the raster just dis app
26. CRT anode to ground Disconnect power supply cable from logic board Remove screws securing power supply bracket assembly to plastic chassis Remove the power supply PCBA up through the top of the chassis To replace a power supply PCBA use the foregoing procedure in reverse order Refer to Section IV for Power Supply DC voltage checks BFISD 8070 5 3 6 Logic Board Removal and Replacement The logic board contains ICs that are extremely sensitive to static discharge Always discharge the body to ground by hand contact before re moving handling or replacing a logic board Do not allow the logic board to contact any of the CRT deflection circuits the yoke or CRT anode even if the anode is grounded l Turn off power and disconnect power cord from outlet and video display assembly 2 Disconnect the keyboard 3 Remove rear housing from the video display assembly paragraph 5 2 1 4 Discharge CRT anode to ground 5 Disconnect power supply connector Jl from logic board 6 Disconnect monitor board connector J3 from logic board 7 Carefully slide logic board out of chassis 8 To replace a logic board use the foregoing procedure in reverse order 5 4 ILLUSTRATED PARTS LIST This portion of Section V provides information on the assemblies and component parts of the Model 4309 EVDT Each parts list is supported by an illustration figure that locates the respective assemblies and or parts The illustra tions may be us
27. CURSOR CONTROL KEYS DISABLES SHIFT LOCK MODE IF IN SHIFT LOCK POSITION WITH Figure 2 11 Layout and Keyswitch Functions Domestic Keyboard E GS ron Ad dede BFISD 8070 E E EN j An APA CLEAR SLET PUSH ya a ya 1 EUH D PRE I HOR LN PE a LIE Jel Figure 2 12 Keyboard Layout Danish i ia M Ti ka a An Li ye LU po C TS ANNUL Y AP re AEE TTE ES Figure 2 13 Keyboard Layout French CLEAR Y IE TID D DEEST TUA T ALPHA e PIU EAE EE EEAEAES AA AL AN NOTE CHARACTER ACQUISTION amib SSD 3 CHARACTER KEYS CAPS LOCK CAPS LOCK ON OFF SHIFT OFF Figure 2 14 Keyboard Layout German 2 23 BFISD 8070 m Fi Fi la Fi Fi la la ia lal E la Ma Ea i CLEAR T LOE CHAR TTD EL PE nan Det Figure 2 15 Keyboard Layout Italian Jl 91 al ja ud 81 jel ugs l 8 Ig ES CLEAR Saa aye eet T a p J C p H Dj Figure 2 16 Keyboard Layout Norwegian awa Wa N TELOR LEHHVETT T L peu Figure 2 17 Keyboard Layout Spanish BFISD 8070 Jo DAZE BIB EI past Figure 2 18 Keyboard Layout Swedish 2 9 2 Standard Control Cod
28. CURSOR OR CHARACTERS PROGRANA TLE ISPLAYABLE CHARACTERS TO INVOKE A SPECIFIC AND FTE THRU TERNINAL OPERATION WHICH MAY EMULATE OR BE IN ET eee en ERI ADDITION TO REGULAR TERMINAL OPERATION E G WHEN PRESSED WITH KEY TRANSMIT EDIT FUNCTIONS GRAPHICS TRANSMISSION CONTROL PRINT ACTIVATES PRINTER IN BLOCK MODE AND CAUSES USER SELECTED CHARACTER STRINGS AS a ALL SCREEN DATA FROM HOME POSITION UP TO BUT NO PROGRAMMED FOR Che KEY OPERATIONS WHEN PRESSED WITH FUNC KEY OPERATIONS WHEN PRESSED WITHUUNCI KE INCLUDING CURSOR POSITION TO BE TRANSMITTED TO THE TAB ADVANCES CURSOR TO FIRST SERACTERS FROM THE DISPLAY PRINTER ESCAPE SEQUENCE MAY BE USED TO PRINT POSITION OF NEXT UNPROTECTED SINGLE LINES OF UNPROTECTED DATA FIELD OR NEXT TAB STOP WHEN PRESSED WITH SHIFT KEY CURSOR BACK TABS TO FIRST re DL POSITION OF PREVIOUS UNPROTECTED FA V V WV NV V V WTW DL E p 2 3 7 0 ki t uS Sg CAPS LOCK PAB SHIFTS ONLY LOWER CASE ONAN NON NY AN AN AN VOE ALPHA CHARACTER INTO UPPER CASE ed m t RETURN IS DISPLAYED QN STATUS LINE TO SET 2 LOC l Ww NM VY V Y V V ui N PRESS CAPS LDCK PAD ONCE TO RELEASE LET ED CONTROL BARS THRU ARE USED TO CONTROL THE CURSOR AS DEFINED BY AN APPLICATION PROGRAM IF NOT DEFINED BY PROGRAM THE CONTROL BARS FUNCTION AS RETURN OR HOME KEYS
29. DO NOT scratch the CRT b DO NOT strike the CRT with hard or sharp objects c DO NOT handle the CRT by the neck Use both hands to hold the CRT across the widest dimension d DO NOT rest the CRT on the neck Stand the CRT face down on a clean flat surface e DO NOT allow a hot soldering iron to touch the CRT 4 Store defective CRTs in original shipping container 5 Replacement spare CRTs should be kept in their shipping containers until needed PO BFISD 8070 5 3 2 Disposal of Defective CRTs Defective CRTs which are to be destroyed should be tightly packed and sealed in a strong cardboard container The CRT should be pierced through the con tainer using a sharp instrument This method of disposal prevents accidents occurring to unsuspecting disposal collection personnel 5 3 3 CRT Removal and Replacement 1 11 12 Turn off power disconnect power from outlet and video display assembly Disconnect the keyboard Remove rear housing from the video display assembly paragraph 5 2 1 Discharge CRT anode to ground Remove front bezel Disconnect connector on rear of CRT neck Disconnect the green ground wire connecting the CRT grounding spring to the monitor board Remove the CRT anode cap Disconnect the CRT yoke assembly cable at the monitor board Remove the corner mounting hardware which secures the CRT to the plastic chassis and carefully remove the CRT through the fron
30. Filter Choke Coil Assembly Choke Coil Electrolytic 470 uF Transistor NPN SD467 Transistor Power Transistor PNP Thermistor 4 ohms 104 Resistor Carbon Film 330K 54 1 2W Resistor 55 1W Metal Oxide Film 220 ohms Resistor 5 1 2W Metal Oxide Film 33 ohms Resistor Carbon Film 1K 5 1 4W Resistor 1 4W Carbon Film 27 ohms 54 Resistor Carbon Film 68 ohms 54 1 4W 5 22 BFISD 8070 Table 5 5 Parts List Power Supply PCBA MM783010 continued REFERENCE PART NUMBER DESCRIPTION DESIGNATION Resistor Carbon Film 10 ohms 57 1 4W Resistor Metal Film 0 75 ohms 45 1W Resistor Metal Film 1 ohm 55 1W Resistor Carbon Film 5 6 ohms 5 1 4W Resistor Carbon Film 68 ohms 54 1 4W Resistor Carbon Film 270 ohms 54 1 2W NOTE Resistor Carbon Film 8 2 ohms 54 R17 1 4W All Part No s are TBD Resistor Carbon Film 560 ohms 5 R18 1 4W Resistor Carbon Film 56 ohms 54 R19 R20 1 4W Resistor Carbon Film 12K 5 1 4W R21 Resistor Carbon Film 470 ohms 54 R22 1 4W Resistor Metal Film 4 7K 2 1 4W R23 Resistor Carbon Film 68K 54 1 4W R24 Resistor Metal Film 22K 2 1 4W R25 Resistor Metal Film 2 7K 24 1 4W R26 Resistor Carbon Film 12 ohms 54 R27 1 4W SCR C122U SCRI Common Mode Transformer Assembly TI Power Transformer Assembly T2 Control Transformer Assembly T3 Diode Zener 5 6V 54
31. L E 906694 VAR 50HZ PRINTER 8070 08 Figure 2 6 EVDT to Fixed Media Disk CPU Interface Cable Connections BFISD 8070 906274 VAR 60HZ MOD 4309 906274 VAR 60HZ SERIAL 906694 VAR 50HZ EVDT 906694 VAR 50HZ PRINTER 906274 VAR 60HZ 4309 906274 VAR 60HZ SERIAL EVDT 906694 VAR 50HZ PRINTER 1 0 PANEL Figure 2 7 EVDT to Removable Disk CPU Interface Cable Connections E a POWER RS 232 ON OFF PORT B __ PORT A EA B TIE SHIELDS AT CONNECTOR MOUNTING SCREW TO PRINTER TO CPU 8070 10 Figure 2 8 EVDT Cable Grounding BFISD 8070 2 6 EVDT POWER UP Perform the initial EVDT power up as follows 1 Press the rear panel POWER ON OFF switch to the ON position The EVDT will automatically perform a power up self test At the com pletion of the test an audible tone beep will sound indicating that the self test ran successfully After approximately 20 seconds the cursor and the EVDT status line should appear on the display 2 Perform the Keyboard Master Reset by pressing the CONTROL SHIFT FUNCTION and CLEAR keys at the same time Data will be ersed from the screen and the status line clock will be reset to 1 01 AM This keyboard operation resets all programmable EVDT parameters to their default settings assuring that only those parameters modified in the Setup Mode or their default settings will affect EVDT operation 3 Refer to paragraph 2 7 and select the paramete
32. Parts List Monitor Board PCBA MM780020 continued REFERENCE PART NUMBER DESCRIPTION DESIGNATION 150021 001 Diode RGP10J 150023 001 Diode RGP10G 150024 001 Diode Zener 1N4752A 33V 490002 001 Fuse 2A 250V Fast Blow 452003 001 Inductor 4 7 uH 54 463001 001 Inductor Variable WIDTH 463002 001 Inductor Variable HORIZONTAL LINEARITY 170014 001 IC TDA1170N 22245 3304 Resistor 33 ohms 5 1 2W 22225 1003 Resistor 10 ohms 5 1 4W 22225 1023 Resistor 1K 5 1 4W 23265 8216 Resistor 820 ohms 54 2W 22245 2214 Resistor 220 ohms 5 1 2W 22225 3323 Resistor 3 3K 5 1 4W 22225 4723 Resistor 4 7K 5X 1 4W 22225 1043 Resistor 100K 5 1 4W 22225 1843 Resistor 180K 5 1 4W 22225 7543 Resistor 750K 54 1 4W R11 22225 6233 R12 Resistor 62K 5 1 4W 22225 6243 Resistor 620K 5 1 4W R13 22225 5633 Resistor 56K 5 1 4W R14 R15 22225 6833 R16 Resistor 68K 54 1 4W 22225 8233 Resistor 82K 5 1 4W R17 BFISD 8070 Table 5 4 Parts List Monitor Board PCBA MM780020 continued REFERENCE PART NUMBER DESCRIPTION DESIGNATION 22245 1094 Resistor 1 ohm 54 1 2W R18 24146 5083 Resistor 0 5 ohm 105 3W R20 22225 1523 Resistor 1 5K 5 1 4W R21 R27 22225
33. SUSPECT MPU MICROCODE PROMS REPLACE LOGIC BOARD IF NECESSARY NO COMMUNICATION OK VIDEO DISPLAY OK NO SUSPECT UART OR CONTROL NG CRT AND REGISTER REPLACE MONITOR BOARD LOGIC BOARD OK IF NECESSARY NO REPLACE CRT OR KEYBOARD MONITOR BOARD YES AS NECESSARY CONNECTOR OR KEYBOARD REPLACE AS NECESSARY CHECK CRT DISPLAY MEMORY REPLACE LOGIC BOARD AS NECESSARY YES 8070 46 BFISD 8070 RECUR RESUME Y OPERATION NO YES PRINTER CONNECTOR 1 O PORTS LINE MODEM HOST COMPUTER 1 0 PORT CONTROL REGISTER Figure 4 1 Troubleshooting Flow Chart BFISD 8070 4 3 2 Troubleshooting Guide Table 4 1 provides a troubleshooting guide in support of figure 4 1 The table lists fault conditions by symptom possible cause and corrective action Identify the symptom then eliminate the possible causes one by one in the order listed by taking the necessary corrective action The troubleshooting table is not exhaustive and cannot cover all symptoms and possible causes rules Table 4 1 EVDT Troubleshooting Guide Its purpose is to serve as a guide rather than a set of SYMPTOM POSSIBLE CAUSE CORRECTIVE ACTION A No beep upon turn on Beep signifies success ful CPU initiali zation Screen dark no cursor or status line Characters enter ed from keyboard not displayed No AC power B
34. a 4 14 SECTION V REMOVAL REPLACEMENT SPARE PARTS IntroduCctiOns www ceo 6 UC DX 9 SU ROC General Disassembly e a a a w a w e a a w a nn Rear Housing Removal e e au lt lt a a w a a e Keyboard Housing Removal e e a a a a a a a o Removal Replacement Procedures e a w oo CRT Safety Precautions e a a a a a au a a a o Disposal of Defective CRTs lt au w au a a a n CRT Removal and Replacement a a a a o Monitor Board PCBA Removal and Replacement e Power Supply PCBA Removal and Replacement Logic Board Removal and Replacement a a o Illustrated Parts List lt au a au au au a a a a o Un Ui Ui Ui Ul mW CO DW LO CO CO P2 N 1 e DUE WN I To YE NO PAT eee Yi UO Q QO N N N SECTION VI REFERENCE DATA BFISD 8070 vi LIST OF ILLUSTRATIONS Model 4309 Ergonomic Video Display Terminal Major Assemblies and Related Components Model 4309 EVDT w s fk e e e e ooo ooo EVDT Unpacking Repacking lt w e a a a a AC Input Voltage Configurations Power Supply PCBA Keyboard Cable Connection Model 4309 EVDT e Video Display Assembly Rear Panel Model 4309 EVDT EVDT to System 810 Interface Cable Connections EVDT to Fixed Media Disk CPU Interface Cable Connections w au a a a e e a a n EVDT to R
35. an EVDT to the factory repack the unit in its original container using the original packing materials whenever possible Repack the EVDT as shown in figure 2 l 2 3 PREINSTALLATION CHECKS Before connecting the EVDT to site power the following checks should be made to assure proper operation and to prevent electrical damage to the equipment BFISD 8070 MANUAL KEYBOARD SEE NOTE NOTE SAVE ALL PACKAGING MATERIALS FOR FUTURE USE 8070 03 Figure 2 1 EVDT Unpacking Repacking BFISD 8070 Table 1 1 Specifications Model 4309 EVDT continued PARAMETERS CHARACTERISTICS GENERAL cont d Editing and Control Modes cont d Conversation Mode Half duplex data displayed as entered Transmission Control or full duplex data returned for display from host CPU Block Mode Editing Clear display erase line erase page delete line insert line delete char acter insert character set tab and clear tab s Enter Mode Display all control characters along with text as aid in programming and troubleshooting Insert Mode Permits insertion of characters without overwriting existing characters Freeze Mode Stops display from changing while allow ing input to data buffer Protected Field Mode Uses Write Protect and Protect Modes to prevent characters lines or entire display from being overwritten Scroll Mode Smooth or line by line scrolling Setup Mode Display menu of keyboard selectable parameters for word
36. appears from figure 3 17 that while the output from inverter 3G 10 is low HSYNC is inverted this is of no consequence since the reference level is shifted by the bias circuit such that all of the sync pulses are negative i e below the visual threshold level The composite sync signal is algebraically summed with the brightness level from the digital to analog converter and the half intensity signal from 117 This combined signal less video is fed via to J3 pin 4 and from there to the monitor It is also fed via emitter follower Q3 which also functions as a level converter to BNC connector J2 and to J3 pin 8 The brightness level is expressed as a digital value by the MPU on demand from the keyboard This digital value is placed on the data bus by the MPU when the digital to analog D A converter 4L is addressed as an I O device The I O address decode BRITLD clocks the digital value into the internal D A buffer The digital value is converted to a corresponding alalog voltage level which is level converted by one half of the operational amplifier pair 2L The output is then fed to the base of Q3 which acts as the voltage summing node for the brightness intensity and composite sync The Blink generator consists of the four bit binary counter 12C and the D type flip flop 5L which are configured as a 5 bit counter The counter is clocked by the vertical drive such that each count signifies the duration of a com plete frame Th
37. are therefore defined as pro grammable The address register is excluded from the eighteen registers be cause of its special function Of the remaining registers only RO R7 are used The following text briefly describes the function of each utilized register Address Register This is a 5 bit register used as a source destination reference to direct transfers between the MPU and CRTC When RS is low this register may be loaded when RS is high then the internal register selected is the one whose binary identity 00000 00111 is stored in this register RO Horizontal Total 00000 This 8 bit register contains the total number of characters minus one per horizontal line The total is the sum of displayed and non displayed characters as depicted in figure 3 10 The frequency of HSYNC is thus determined by this register Rl Horizontal Displayed 00001 This 8 bit register contains the number of displayed characters per horizontal line reference figure 3 10 which in the case of the EVDT is 80 single width characters or 130 characters option R2 Horizontal Sync Position 00010 This 8 bit register contains the position of HSYNC on the horizontal line in terms of character location number on the line The position of HSYNC determines the left to right location of the displayed text on the screen as a means of adjusting the side margins BFISD 8070 HORIZONTAL TOTAL RO HORIZONTAL porci R1 SC FTH DP TRTCIvTNT
38. at a time Smooth Scrolling is enabled at speeds of over 1200 baud the Xonoff will prevent buffer overflow not yet fully supported by Basic Four software No line feed when RETURN is pressed Line feed when RETURN is pressed Standard 12 hour clock AM PM 24 hour clock military time Status line is not displayed Status line is displayed Keystrokes are not automatically repeated Keystrokes are automatically repeated when the key is held down for more than one second Characters or operations are repeated at a rate of 16 per second No audible click is produced when a code generating key is pressed An audible click is produced when a code generating key is pressed No bell before line end Bell sounds eight characters before end of line for block mode convenience Indicates default setting of setup parameters invokable by Keyboard Master Reset 2 14 BFISD 8070 BFIS 4309 Fz 297 HM Figure 2 10 FUNC with Exam FI Display 21 Type press and hold and type Press and hold and type observe that By is displayed on the screen and that no audible tone is sounded Press and hold while typing 1 observe that Bg Hp and Lp are dis played on the screen 2 9 EVDT OPERATION The following paragraphs provide detailed information on the various operating modes and control codes used by the Model 4309 EVDT Programming information is provided in paragraph 2 10 2 9 1 Keyboard Ove
39. before but DBLH high to provide a P input enable so that the output QA toggles with alternate ROWCK clocks The timing for each mode of operation is shown in figure 3 14 and figure 3 15 3 6 8 4 Line Attribute Buffer The line attribute buffer 10E is loaded from the MPU data bus when the I O address decode LATTID is activated The four least significant bits signify the value of the initial count to be loaded into the line scan counter lOF The four most significant bits have the following significance PD Load one into divide by 2 counter PD6 DBLH 1 double height 0 single height PD5 DBLW 1 double height 0 normal width PD4 DISLIN 0 disable line 1 enable line The functions of loading one into the divide by two counter and single and double height timing have been discussed If DBLW 1 Logic Diagram Sheet 3 shows that the B inputs to multiplexer 8J are selected as outputs Assuming 80 column display is selected the effect is as shown in figure 3 16 Character load still takes place on every eighth dot clock but by comparison with figure 3 7 the time frame between consecu tive CHRLD pulses has been doubled and the dot clock period has been doubled This has the effect of doubling the width of the displayed characters and horizontally lengthening the dot to twice the normal length If DISLIN 0 the line is effectively erased Logic Diagram Sheet 8 shows that DISLIN when low clears the screen data
40. is one the flip flop is clocked into the set state one half clock period later by DOTCLK This has the effect of elongating a one bit which causes thickening of vertical character lines in keeping with the thickness of horizontal character lines The timing data output is depicted in figure 3 13 for a dot matrix character consisting of alternate ones and zeros to emphasize the elongation of a one bit as it appears at VIDOUT 3 32 BFISD 8070 DOTCLK CHRLD LOAD SHIFT SHIFT SHIFT SHIFT SHIFT SHIFT SHIFT LOAD 76 13 VIDOUT Figure 3 13 Parallel To Serial Conversion 3 6 8 3 Line Scan Counter The line scan counter 10F is a 4 bit binary counter with synchronous loading It is parallel loaded from the Line Attribute Buffer four bits whenever the Load input LD is forced low in concurrence with ROWCK It is loaded when the output of gate 4B 13 goes low which occurs each time the character row counter 11C generates a carry output and when VSYNC occurs Note that the character row counter generates a carry output when 12 line scans have been counted and that it also is loaded at the same time as the line scan counter lOF The line scan counter has two counting modes one for single height character generation and the other for double height character generation as described in the following paragraphs Single Height Mode In single height mode th
41. low indicates high priority device CTC is being serviced In this case IGI is IEO from CTC Interrupt Enable Out Active high output forming part of interrupt daisy chain High notifies next device in daisy chain that it may initiate an interrupt low noti fies next device that the DART is being serviced IGO is routed to the expansion connector Interrupt Request Active low output notifies MPU that a device is requesting service Machine Cycle One Active low input from MPU When Ml and RD are both active the MPU is fetching an instruc tion from memory When Ml and IORQ are both active the MPU is acknowledging an interrupt to the device with IEO low PIN BFISD 8070 Table 3 3 DART Pin Out Description continued MNEMONIC IORQ W RDYA W RDYB DESCRIPTION Input Output Request Active low input from MPU Used in conjunction with B A C D CE SIDE and RD to transfer commands and data between MPU and the DART When CE RD and IORQ are all active the channel selected by B A transfers data to the MPU When CE and IORQ are active but RD is inactive the channel selected by B A receives control information or data according to the state of C D Receiver Clocks Inputs from CTC Receive data is sampled on the rising edge of R X C The clock inputs may be 16 32 or 64 times the data rate Note that R X CB pin 27 is both the receive clock and transmit clock input for channel B Read Cycle
42. plate is 12 inches in diagonal measure and has a non glare etch ed viewing surface with green phosphor P31 The CRT deflection angle is 90 degrees The neck of the CRT includes a yoke assembly which is adjustable in part or whole for proper positioning and linearity of the video raster Details on the CRT display matrix are provided in Section III The Monitor Board PCBA accepts TTL level video horizontal drive and vertical drive signals from the Logic PCBA The Monitor Board PCBA also accepts 12 volts DC from the Power Supply PCBA via connections and traces on the Math Logic Board PCBA These inputs are processed by the Monitor Board PCBA to generate the CRT raster scan and the high voltages that permit the display of video information Details of Monitor Board PCBA operation are discussed in Section III 1 2 2 2 Main Logic Board PCBA The Main Logic Board PCBA figure 1 2 contains the microprocessor unit MPU keyboard interface logic main memory display memeory character generator and controller logic character and display attribute logic CRT controller logic composite video logic and communications interface logic These memory and logic elements under control of the MPU receive character coded data from either the keyboard or communications interface The coded data is written into display memory at addresses coinciding with the character cursor position in the display matrix The character generators read the cod
43. printer the associated I O port is suspect If the terminal will operate in Block Mode the CPU video display and host communications interface can be eliminated as the source of the problem If the problem is not a communications malfunction the next determination to be made is whether or not the video display is correct in terms of both format and character content First is the display the correct size 24 X 80 second are the characters formed properly If the display is not the correct size the problem may be the tube itself the CRT controller or the Monitor board If the characters are incorreclty formed the problem may be display memory character generator or composite video circuits If the problem appears to be in the keyboard it may be an open or short cir cuit in the connector in which case the connector should be replaced The problem may also be in the keyboard interface logic on the main logic board for example the parallel serial converter may be bad This can be verified using an oscilloscope by monitoring the serial line to the keyboard and seeing if the matrix code is being transmitted by the interface logic 4 2 START POWER FAILURE OPERATING PROCEDURE NO OK NOT EVDT USE CORRECT PROBLEM PROCEDURE MASTER RESET CLEAR PROBLEM PROBLEM YES FUSES LINE CORD POWER SUPPLY REPLACE AS NECESSARY MORE THAN ONE SYMPTOM YES NO
44. proceed to step 4 4 Enable setting of hours display by entering from list of codes in table 2 10 5 Set value of hours display by entering appropriate ASCII character from list in table 2 11 e g for 11 00 AM or PM 6 Repeat procedure to set value of minutes display and seconds display using codes 6 and 7 in table 2 10 and the ASCII characters in table 2 11 7 The following notations summarize the clock setting procedure Block Mode Clock Control Mode 2 2 2 o lt increment hours for AM PM or 9 set hours 6 45 set minutes 7 Ascr set seconds Table 2 10 Clock Set Command Codes COMMAND IE Time Indicator On EN Time Indicator Off Does not display Time Indicator DESCRIPTION Displays Time Indicator Increment Minute Advances minute display l minute Four bytes are sent to the host com puter when this command is invoked They represent hour minute second and carriage return The hour minute and second are actual values plus 20 hex Real Time Indicator 2 37 BFISD 8070 Table 2 10 Clock Set Command Codes continued CODE COMMAND DESCRIPTION Write Hour The value entered is loaded into the hour display digit minus 20 Refer to table 2 11 Write Minute The value entered is loaded into the minute display digit minus 20 Refer to table 2 11 Write Second The value entered is loaded into the second display digit minus 20 R
45. removing the rear housing of the video display assembly Failure to do so may result in severe shock which can be fatal or may result in serious damage to the equipment Always discharge the CRT anode to ground with a grounding strap before removing any subassemblies 4 3 TROUBLE ANALYSIS Trouble analysis essentially consists of two phases In the first phase troubleshooting procedures are applied to identify the problem In the second phase fault isolation procedures are applied to isolate the source of malfunc tion 4 1 BFISD 8070 4 3 1 Troubleshooting Procedures Before troubleshooting the terminal it is essential to determine that the problem is within the terminal and that the problem is correctly identified Troubleshooting should be approached from a logical process of elimination as outlined in the flowchart in figure 4 1 and as described in the paragraphs that follow The flowchart takes into account failure at the module level and should be used only as a guideline First determine if the fault condition is due to an external power failure no voltage at service outlet or an internal power failure blown fuse bad power supply If the fault condition is not due to a power failure determine if the fault condition is valid not due to operator error As a general rule make sure that all of the unit and module interconnect cabling is properly con nected and that there are no obvious signs of internal short circ
46. vertical size of the displayed text is determined R Vertical Sync Position 00111 This 7 bit register is used to select the character row time at which VSYNC is to occur and is thus used to position the displayed text in the vertical direction top mar gin 3 6 6 2 Vertical and Horizontal Timing The vertical and horizontal timing relationship is shown in figure 3 ll The timing is not drawn to scale and the frame does not reflect the actual dimen sions of the display matrix The timing diagram is intended as an aid to understanding the internal clocking and synchronization of the HSYNC and VSYNC pulse outputs Although the raster line outputs RAO RA4 are shown in relationship to scan line generation they are not used The number of scan lines per character row is a function of the character generator cirucits and is discussed in later text 3 27 BFISD 8070 G3SN LON tvy Ovy TTvS OWS ONASH 318VN3 AV 1dsS1d 3195 I aviasio TVANOZIYON TVLOL T1VLNOZIYOH ANIT NVOS 313 14dWOO L Q3Sn LON INASA INASH 318VN3 AV1dSI0 Q3AV IdSIG TVOILH3A 70101 TWOILYJA AWVYS 3l31dWO2 I 8070 35 Vertical and Horizontal Timing Relationship Figure 3 11 3 28 BFISD 8070 3 6 7 Refresh Address Generation The refresh address generation circuit is shown on Logic Diagram Sheet 9 It consists of the individual binary counters 13E 15E and 14E and buffer registers 1
47. whe e e a a e e e nu PON N N BO B2 PO B2 BO BO BO PO FS FS FS FS FS ES A 2 10 10 2 10 11 2 10 12 2 10 13 2 10 14 II TABLE OF CONTENTS INTRODUCTION General e a au a a n EVDT Description e e a Keyboard Assembly e e o Video Display Assembly e Monitor Assembly e o Main Logic Board PCBA Power Supply PCBA Specifications e Related Documents e a gt INSTALLATION AND OPERATION Introduction e s a a Unpacking Inspection Repacking Preinstallation Checks e o AC Power Requirements o Ground Checks e Power Supply PCBA Input Voltage Systems Interface Requirements EVDT Installation e a EVDT Power Up e s a n Setup Mode Parameter Selection Operational Check a Check of Cursor Control Keys Check of Displayable Character Keys Check of Special Function Keys EVDT Operation e e a Keyboard Overview n Standard Control Codes e Self Test Control Codes Escape Sequences e a au a Special Function Codes and Operating Modes Data Editing Control Operations e e Data Transmission Control Operations Print Transmission Control Operations Business Graphics Mode e e EVDT Programming e o Setting AM PM or
48. 005 01 90 3373 001 907365 03 1831 00 02 1832 00 02 1302 00 907354 04 6501 00 04 7600 00 907352 03 7000 00 907349 5 9 BFISD 8070 iP 27 FOS e WAS N VIA p L S ZAN val KIS SS AN ZS S Y E VIT PUES 05 y ANY 2 5 YU N AD S lt By SR i A Z EVDT Keyboard Assembly Figure 5 2 5 10 BFISD 8070 Table 5 2 Parts List EVDT Keyboard Assembly FIG 5 2 ICN INDEX NO DESCRIPTION DESIGNATION PART NO QTY Keyboard Assembly Domestic MM783020 400433 001 400432 001 Keyboard Assembly German TBD TBD 400435 001 Keyboard Assembly Spanish Housing Keyboard Cable Keyboard 03 7001 00 PCBA Keyboard Refer to 65 02574 XXX table figure 5 6 Base Keyboard 5 11 BFISD 8070 F a s AA Jee ee Ye si J BE SP RSS 10000 zx ESE Os ra RO 2 n i pe tf pa rms exo OU ets Tet vd h Cm38 Cy 3 rw yt 0s0 2 L ont mew PEEL uox cen p 3n HOLIAS ers O s Loc jan a 9 ue L 18 L gt 4 212 092 a ann eas C3 P s 991s e TE uns Kew ns COIS Can CE sesi l Can 05 2 4818 zu TE lJ caw vos 19551 gt ee naoeez SI 981 Cw ANN Goo ogee 19551 251 9251 Vis 95 092 TE pasen rid gets rags 757 no CO 57 ki Can Ca ZON a Can 64251
49. 06 QUAD BUFF ER DRI VER 741508 QUAD 2l NP ANO T4LS10 TRIPLE INPUT NAND GATE T4LS20 POS NANO GATE 71744532 QUAD 2 IN OR T4LS 74 DUAL D TYPE POS EDG TRIG F F T4LS 157 QUAD 2 1 LINE DATA S L EC MUX T4LS138 3 8 LINE DECODER DEM 4 TI PLEX SHIFT REGISTER 8 BIT PARALL TO SERIAL BINARY COUNTER 4 STAGE PRESETIABLE IC IC IC IC IC IC IC T4LS273 OCTAL 0 TYPE FLIP FLCP 7415 373 OCTAL D TYPC LATCH 3 STATE 74LS 393 DUAL 4 BIT BINARY COUNTER MC1488L QUAD LINE ORIVER MC1489L QUAD LINE RECEIVER 280A 8 BIT MICRO P ZBOA CTC COUNTER T IMER CRCT 2 80 DUAL ASYNC RECEI VER TRANSM IT TER IC CRT CONTROLLER Ic IC IC IC IC IC IC IG IC IC IC ic 1 1 74166 8 BIT SHIFT REGISTER 2732 4KXB EPROM 450 NS RAM STATIC 2KX8 150NS 7415 06 HEX INVERTER 74510 GATE TRIPLE 3 INPUT NAND SNT4 ST4 DUAL D TYPE FLIP FLGP 74866 QUAD Z INPUT EXCLUSIVE OR GATE 7415112 DUAL J K EDG TKIG FL IP FLUP SN74S157 QUAD 2 1 LINEDATA S ELECT MUX T4LSi63 BINARY COUNTER SYNC 748163 SYSCHRONOUS BIT CCUATER 744525 OCTAL RUS XC VR 7452 88 32 X 8 OCTAL BUS DRIVER INVERTING 3 S 8 BIT DOUBLE BUFFERED D TO A CONVERTER OP AMP QUAL JFET WIDE BAND IC REGULATOR 5 0V 0 5 TU220 P amp G RES RES RES RES RES RES RES RES CAP CAP CARBON FILM 25W 5 75 OHM CAR BON FILM 25W 54 220 OHM CAKBON FILM 254 5 520 Om CAKBON FILM 25W 58 470 OHM CAKBUN FILM 25W 5 2K OHM CARBUN FILM a25W 58 4 TK CHM CARBO
50. 0C 15C 11D and half of 11 The counters 13G 15E and 14E are connected in series to form a l2 bit counter whose outputs 5 0 5 11 represent a 12 bit screen memory address The counter has a count cycle of 4096 counts corresponding to 4096 RAM locations in screen memory to accommodate 3120 characters and the associated attributes for a 130 X 24 display matrix SAll points to the upper or lower half of the dis play and SAO SA10 11 bits select one of 2K locations The counter is clocked by CHRCLK which as shown in figure 3 7 provides a positive going transition once in every 8 dot clock periods i e every time a character row is scanned and when the next character row is to be displayed The two most significant stages of the counter 15E and 14E are parallel load ed from buffer register 15C on the trailing edge of ROWLD As shown on Sheet 10 ROWLD is derived from the Attribute Control Register 117 and represents the state of the DISP signal from the CRTC sampled at the SMCYC clock rate de layed one SMCYC clock period from ROWCLK which represents the state of DISP as sampled at the SMCYC clock rate This simply means that ROWCLK and ROWLD are generated in synchronization with HSYNC to denote the start of a new horizontal scan see figure 3 11 The least significant stage of the counter is parallel loaded from one half of buffer register 11E coincident with ROWCLK The buffers 10C 1D 15E 11E and 10E are octal D type flip
51. 15A 12 VDC 2 5A 5 VDC 0 20V 12V and O O3V 5V 65 F to 75 F 18 C to 24 C 40 to 60 non condensing Smart microprocessor controlled 1 0 with user programmable keyboard display and interface parameters Zilog Z 80A 8 bit 4MHz 8 ROM 8 CMOS RAM battery backed 2K x 8 RAM total 2K 4 RAM total x 8 ROM total 24 lines x 80 characters with selectable 25th status line BFISD 8070 Table 1 1 Specifications Model 4309 EVDT continued PARAMETERS GENERAL cont d Character Font Character Font Attribute Display Attributes Communication Interface Transmission Format Baud Rates Transmission Modes Conversation Mode Full Duplex Conversation Mode Half Duplex Block Mode CHARACTERISTICS 8 x 12 character cell with 6 x 10 dot matrix including lower case decender Normal double wide double high double wide double high Reverse video reduced intensity blink ing underlined assignable to cursor character line or full screen Asynchronous serial bit per EIA Standard RS 232C 10 or ll bit transmission word consist ing of 1 start bit 7 data bits for domestic and World Trade terminals or 8 data bits for international and Katakana terminals followed optionally by 1 parity bit and 1 or 2 stop bits 50 75 110 134 5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 and 19200 baud Keyboard codes are sent to host CPU and return
52. 25005 004 1 SOCKET IC DIP FOUR LEAF CONT GOLD 16 POS 9C 325005 001 7 SOCKET IC DIP FOUR LEAF CONT GOLD 24 POS 1E 2E 3E 8E 6E 86 106 161108 001 1 IC RAM STATIC 2KX8 CMOS 200NS 6E 315052 001 1 CONTACT SCLOER MOUNT MALE 250X 0u32 16 104003 002 3 CAP CERAMIC XTR 1UF 10 50V C80 77 78 150001 020 1 OSCILLATOR CRYSTAL CLOCK 14 7456 MHZ USC 14 161117 001 1 DINDE ZENER 8 7V 250MW LOW NOISE CR4 t61118 001 1 LEG RED DIFFUSED TIL220 LED 101306 2 TRANS NPN SILICON 2N222 2A 02 3 108022 002 1 CAP ALUM ELECT MINI 220UF 50 102 LOV C 86 331005 001 1 SWITCH SPST DIP 7 POS 6L 180052 001 2 TRANSFORMER BLAUN COIL 2 165016 004 1 1 2732 2KX8 EPROM 250 NS 1 0G 300005 005 1 CONN HOR 045 W LUCK 156 CIS 7 POS Ji 300069 001 1 CONN MODULAR JACK PC BRD MOUNT 6 POS J7 3C0005 0Q13 1 CONN HDR 045 W LOCK 155 CTS 11 POS J3 300052 015 1 CONN HOR 025SQ DBL ROW 100 CTS 50 POS J 313222 003 2 CUNN RT ANG PCB 25 SOCKET J596 161015 L IC 741514 HEX SCHMITT TRIGGER INVERTER 9E 111000 063 1 RES CARBON FILM 25 5 10K OFM R2A 104003 012 1 CAP CERAMIC XIR 04 7UF 20 200V 2 183005 001 i BATTERY NICAD 62 4 VOLT 4F 208000 001 4 KIVET BLIND 1160X 188L ALUM J5 6 907349 001 i PLATE CONNECTOR PCBA 2 CUTUUTS J56 100114 SCREWLOCK FEMALE 4 40 THD 0 TYPE 35 6 221019 001 7 CABLE TIE 0 62 DIA BUNDLE 119004 002 1 RES NTWK SIP LP 10 PIN 9 RES 4 7 OHM RPS 5 14 BFISD 8070 O tu peak C
53. 4323 Resistor 4 3K 5 1 4W R23 22225 1033 Resistor 10K 5 1 4W R24 22225 8223 Resistor 8 2K 5 1 4W R25 22225 2223 Resistor 2 2K 5 1 4W R26 22225 3333 Resistor 33K 5 1 4W R28 24146 8203 Resistor 82 ohms 10 3W R29 22245 1014 Resistor 100 ohms 5 1 2W R30 22245 1594 Resistor 1 5 ohms 54 1 2W R31 22225 2023 Resistor 2K 5 1 4W R32 22225 1853 Resistor 1 8M 5 1 4W R33 22225 1033 Resistor 10K 5 1 4W R34 R35 R38 22225 7533 Resistor 75K 5 1 4W R36 22225 2243 Resistor 220K 54 1 4W R37 22225 1595 Resistor 1 5 ohms 54 R39 22225 3394 Resistor 3 3 ohms 5 1 4W R40 470001 001 Transformer Horizontal Drive Tl 470002 001 Transformer Flyback T2 140017 001 Transistor NPN 2N3904 TR1 140018 001 Transistor NPN 2N3053 TR2 14001 9 001 Transistor NPN 2SC536 TR3 TR4 1400020 001 Transistor NPN 2SC2314 TR5 1400038 001 Transistor NPN 2SD823 TR6 BFISD 8070 Table 5 4 Parts List Monitor Board PCBA MM780020 continued REFERENCE PART NUMBER DESCRIPTION DESIGNATION 251012 001 Potentiometer 500 ohms 20 0 1V VRI CONTRAST 251011 001 Potentiometer 250K 20 0 1V V HEIGHT HOLD VR2 VR3 251009 001 Potentiometer 100K 205 0 1V VR4 V LINEARITY 251013 001 Potentiometer 2 2K 20 0 1V VR5 H CENTER 251010 001 Potentiometer 5M 20 0 25V FOCUS VR6 251009 001 Potentiometer 100K 207 0 1V VR7 BRIGHTNES
54. 5V MAIN LOGIC 712V KEY 5V GND 12V PCBA TOP VIEW D tn I 1234567 J1 Figure 4 2 DC Voltage at Connector Jl 4 3 3 2 BFISD 8070 Monitor Board Video Adjustment Monitor Board adjustments include brightness contrast horizontal centering vertical height horizontal width vertical linearity horizontal linearity and focus All adjustments are made after filling the screen with uppercase Es 1 To clear memory and reset all controls to default values perform the Keyboard Master Reset by entering SHIFT CONTROL FUNCTION ESCAPE CLEAR e The screen will briefly display self test patterns Release all four keys and wait for time of day clock to appear on display status line Enter FUNC A to place EVDT in Block Mode will appear to the left of the time of day clock on the display status line Enter 0 on numeric keypad Press and hold SHIFT and press key numerous times to produce nearly one full line of Es on the screen NOTE Do not completely fill the line with Es The cursor must stop short of end of line Enter FUNC SET F This stores the line of Es into memory for function key FI Press Function key FI enough times to completely fill screen with Es Adjustment of the Monitor Board can now begin A non metallic hexagonal alignment tool and a small insulated screwdriver are required to perform the following adjustments CAUTION Allow terminal to warm up befor Monitor
55. 7 PA6 and PA5 i e the cycle is not an Ml cycle and that IORQ is low That is it is an I O operation and not a MPU interrupt acknowledge 3 15 BFISD 8070 The octal decoder 9D decodes the eight possible combinations of the three least significant address bits PA2 PAl and PAO during I O Write operations as determined by PIORQ and PWR both being low The significance of the decodes are as follows PA2 PAI PAO 0 0 0 RST Reset Row Attribute Registers and Line Attribute Registers Sheet 9 0 0 1 KEYLD Key Load enables transmission of key matrix code 0 1 0 LINELD Line Load loads an 8 bit value into one of the Row Attribute registers 0 1 1 BRITLD Brightness Load loads an 8 bit value into the Analog Digital converter 1 0 0 LATTLD Line Attribute Load loads an attribute value into registers 10E on Sheet 9 1 0 1 LSCNLD Line Scan Load loads an 8 bit value into a second Row Attribute register four bits of which are transferred to the line scan counter 1 1 1 Not used 1 l 1 Unlabelled Decode Loads or clocks an 8 bit value into register 10D Sheet 3 Register 10D determines which of two banks in optional Data Memory is select ed whether 80 or 132 column display is selected whether CTS is to be activat ed for certain communication protocols and whether non maskable line inter rupts are to be enabled 3 6 3 Main Memory Main memory is shown on Logic Diagram Sheets 5 and 6 and consists of the follo
56. 8 8 TINNVHI 91901 T0ULNOJ TVN331NI SAB TVN331NI JILSTITFA 3lluM Qv3u V T3NNVH2 J1901 TOULNOD TVN331NI DART Block Diagram Figure 3 19 45 3 BFISD 8070 PIN MNEMONIC 4 B A bo 3 c D Co SIDE N 0 CLK 0 18 CTSA CTSB M DCDA DCDB DTRA DTRB c T c e mi INT MI Un N Ne Ne Uno t gt xo o 3 46 Table 3 3 DART Pin Out Description DESCRIPTION Channel A or B Select High selects B low selects A Controlled by address bit Al Control or Data Select High selects control low selects data with reference to information on the MPU data bus Controlled by address bit AO Chip Enable Active low input Low enables the DART to accept command or data input from the MPU during a write cycle or to send data to the MPU during a read cycle System Clock Input The DART uses the MPU clock ZCK CKCPU to synchronize internal functions Clear to Send Inputs Active low enables the respective transmitter MPU Data Bus Bi directional three state lines which carry data commands and status between the MPU and the DART Data Carrier Detect Active low inputs which serve as receive enables Data Terminal Ready Active low outputs which follow the state programmed into the DTR bit in Write Register 5 Interrupt Enable In Active high input forming part of interrupt daisy chain High indicates DART can initiate an interrupt
57. A B ou Clock Display Establishing Protected Fields Selecting Display Attributes Selecting Character Size Attributes Function Key Programming e e Using the Enter Mode Using the Insert Mode e a Setting the Limited Screen Mode Remote Cursor Commands o a e Terminal ID Answer Back Message Changing Personality Attributes EVDT Reset Operations Keyboard Enable Disable Title Indicator Modification BFISD 8070 Page Ce ee Pe ON ON WD WD DW 50 i CN O O te iii BFISD 8070 TABLE OF CONTENTS continued av 09 SECTION III FUNCTIONAL DESCRIPTION Introd cti ons x e e e eoe e e WO a A L WO ae Lowe General Design Principles au a e e a on Block Diagrams e lt s lt o lt e e e e e e l Main Logic Board lt lt s e e e e e e e e oo Microprocessor Unit e lt lt e 09 9 e e o e a Main Memory e e s s lt lt e e e e 9 o e e e oo Screen Memory e s lt a e a e e e au w e a e a Character Generation e e e lt lt a w a w e w e a o CRI Controller lt s w e lt lt e e e ee o s Keyboard Interface 4 e e e lt lt e e e 0 e e oo Communication Interface e e a a a a a o Keyboard Logics 4 w lt e e e X ooo e e x Detailed Logic Descripti
58. Basic Four Model 4309 Ergonomic Video Display Terminal Machine Type 4309 BFISD 8070P Service Manual Basic Four Information Systems The information contained herein is proprietary to and considered a trade Secret of Management Assistance Inc Ali rights reserved No part of this publication may be reproduced recorded or stored in a retrieval system or transmitted in any form or by any means whether electronic mechanical photographic or otherwise without prior written permission of the Basic Four Information Systems Division of Management Assistance Inc All Rights Reserved BFISD 8070P Copyright 1979 by Basic Four Corporation Revised September 1979 All specifications are subject to change without notice Basic Four and MAI are registered trademarks of Management Assistance Inc Printed in the United States of America Basic Four Information Systems Division Management Assistance Inc 14101 Myford Road Tustin California 92680 714 731 5100 Basic Four Model 4309 Ergonomic Video Display Terminal Machine Type 4309 Service Manual D 8070P April 1983 SECTION Lp rp e e e 95 es e W N RP DN DN S KH SECTION e e e e e e e e e n e e LON Lm e e LON k e ADAN XO XO XO XO KO XO O Qn KOUV CO CO S C O O O O O O OO Ce e OU P
59. C j from host CPU to verify view the commands stored for function keys 01 thru 12 A display similar to that shown in figure 2 21 will appear on the screen The commands stored for function keys 13 thru 28 may be viewed by entering SHIFT FUNC amp EXAM F 10 Edit the commands stored for any function key by overwriting the com mand as required Store revised commands by moving cursor one posi tion to right of last character in revised command and entering FUNC A F ll To erase commands stored for any function key enter number of func tion key in first two columns of display move cursor one postion to right of numbers and enter FUNC 2 SET F ESC k from host CPU 2 42 BFISD 8070 BFIS 4309 Fz 277 NUMBER OF REMAINING CHARACTER SPACES IN 300 CHARACTER BUFFER CURSOR CONTROL CHARACTER SEQUENCES START LOAD RUN en LIST RELEASE STORED FUNCTION KEY COMMANDS I l Y ETC Figure 2 21 Display of Programmed Function Key Commands Keys 01 thru 12 2 10 6 Using the Enter Mode The Enter Mode permits control characters to be displayed along with incoming data streams This mode of operation is useful in debugging and troubleshoot ing situations where it is desired to examine the incoming data without ex ecuting the control codes The Enter Mode is also useful when entering control codes for the Programmable Function Keys as the ESCAPE CLEAR key need not be pressed before e
60. Dil Ae HHH Z AS P4 283 ag LILI 4 Blan pi SAT 3 SF LI AZ ag DI SAL 7445157 12 AT LLLILI 5 3 as PATRE SAS LIT T l te 4 5V SA4 an Se Bel A coy s PAb 2 kee PAS 026 4 14 PA4 21 GE 22 peels AE ce mnm ESEEENR LI bb nen 021 19 AB var LIT TPP T 24 Z AQ os BAZ 740557 bl li it ian 5 t3 arisk SA zi M AT SAG HH 2 ag FAB 0 5 3 Faz lan 45 PAN coo TE Be 42 HT Ai Ad 27 WE e pep ME IZF 2 AIT i is Heus Einen esl eh ied M Mio a e i Figure 6 2 Logic Diagram Main Logic Board PCBA Sht 7 of 12 903385 Rev A BFISD 8070 PROCESSOR SCREEN MEMORY INTERFACE 2 PDT POS am e 1 7418541 ppa J POZ MEN PD LI TIT POD SCREEN DATA LATCHES 8pT 8 126 19 FINT ap sa 4 e 749273 70 74 5373 Q TA aa Qe D SP zs s BDA LLR os s 5 4 5p BO 1 o4 I9 503 aD 40 2807 as 502 Si 02 5 2 20 2 Eve 2 pi a 3 la
61. E THE ONLY CODES USED BY THE EVDT Figure 2 22 Personality Attribute Codes 2 46 BFISD 8070 Table 2 7 Data Transmission Control Operations Block Mode FROM HEX OPERATION FROM KEYBOARD HOST CODE DESCRIPTION Send Line Unpro FUNC N ESC 4 Sends line of unprotect I i 37 beginning of line and ends at cursor postion Sends line of unprotected and protected data followed by a carriage return CR character to host CPU Transmission starts at beginning of line and ends at cursor position ESC and ESC are transmitted to set and reset Write Pro tect Mode tected ed data followed by car riage return CR char Send Line All ESCAPE CLEAR 6 ESC 6 FUNC ESC 5 acter to host CPU Send Page ESCAPE CLEAR 7 Esc 7 Sends all unprotected data on screen followed by a carriage return CR character to host CPU Transmission starts at HOME position and ends at cursor postion Transmission starts at Unprotected Sends all unprotected and protected data on screen followed by a carriage return CR character to host CPU Transmission starts at HOME position and ends at cursor posi tion ESC and ESC are transmitted to set and reset Write Protect Mode Send Page A11 Partial Send Writes FS code at cursor positon and backspaces cursor to previous FS code or HOME position Transmission starts at beginning of first li
62. ION The EVDT consists of two major assemblies a video display assembly and a separate detachable keyboard assembly These assemblies and their related components are illustrated in figure 1 2 1 2 1 Keyboard Assembly The Keyboard Assembly figure 1 2 consists of a two piece low profile housing that contains a 96 position keyswitch matrix with associated logic elements The keyswitch matrix contains 92 keyswitches that are fitted with sculptured keycaps and arranged in two groups a typewriter style alphanumeric group and a numeric keypad group The 74 keys in the alphanumeric group and the 18 keys in the numeric keypad group include the function and control keys necessary to implement the full range of EVDT capabilities The keyboard assembly is connected to the video display assembly with a detachable telephone style cord The keyboard logic elements receive serial 8 bit data matrix codes from the microprocessor unit MPU in the video display assembly The keyboard logic uses the matrix code input to select columns and rows which are scanned to detect keyswitch closures When a key is pressed the keyboard logic produces an ouput pulse that coincides with the matrix code input for that key The output pulse is returned to the MPU for processing of displayable alphanumeric characters or non displayable control characters Of the 127 ASCII characters in the standard EVDT character set 95 are display able characters and 32 are control
63. K CKCPU by either 16 or 256 The time con stant byte is a binary value from 1 to 256 During operation the individual counter channel counts down from the preset time constant value In counter mode the counter decrements on each of the CLK TRG input pulses until zero count is reache When this occurs the ZC out put is activated and the down counter is automatically reloaded with the time constant value In timer mode time intervals as small as the system clock period CKCPU can be determined The time intervals are generated by dividing the clock ZCK with a prescaler that decrements a preset down counter The time interval is an integral multiple of the clock period the prescaler value 16 or 256 and the time constant that is preset in the down counter A timer is triggered automatically when its time constant value is programmed or by an external CLK TRG input To communicate with the CTC the MPU executes an I O to the CTC and places the device address on the address bus The address is decoded as CTCE and the selected channel is determined by address bits AO Al as follows The MPU also determines if data is being sent to the CTC or being read from the CTC by the state of the RD signal RD high write to CTC output RD low read from CTC input In the case of a write operation the consecutive bytes are sent to the selected channel the control byte followed by the time constant In a read operation the value i
64. N FILM 25W 5 560 OM NTWK SIP 8 PIN 7 RES 4 TK OFM MICA DIPPED 33PF 5 300V CERAMIC 250 DIP 20 SOV BFISD 8070 MM780010 REMARKS 116 78 LOJ 15D 9F 140 124 5L 13C 12E 9J 14F 15F 1 90 9B 1 0B L 4E 1 5 1 LOD si 26 el 23 eh OC eh 3D LOE oi SC al LE sl LIJ 10L 11L L2c 3A 3L TG 2E 4 Ee LE 141 1 4H BF 4 J 46 26 14C TJs BJ 10F 11F al 1C 5J 9 12 130 TL L 2L VR1 R17 R99 10 9183235 7 14 R22 R15 R 13948 2 919 4169 20 92 81 2 11 12 R3 RP4 C73 C3A 3B 2 REQ D 3C 2 REQ 0 8C 411C al 3C 15C 80 14D 1E 2E 3E 9E eh LE 941 SE al 5E o 12F 61 4F 3169 26 36 59 9 73 9 11J 04h 6L 81 10L si 2L 1 00 5 13 BFISD 8070 Table 5 3 Parts List Main Logic Board PCBA MM780010 continued ITEM PART NUM CTY PART DESCRIPTION REMARKS 102004 004 8 CAP TANT 4 TUF 10 50V C64 067s Tl 912083 979 88 90 180051 001 l TRANSFORMER BAL UN COIL 3 108022 001 2 CAP ALUM ELECT MINI 47UF 50 1 LOV C63 89 153002 001 1 TRANSDUCER AUDIO 98D8 BELL 161104 001 5 IC OCTAL BUFFER L INE OR IVER 8C BD 8E BI 9L 111000 039 1 RES CAKBUN FILM 25W 54 22 OHM R5 141007 002 1 TRANS SWITCHING AMPLIF IER 2 906 Q1 101220 4 DIUDE IN4148 SILICON SWITCHING 293 lA 325005 003 4 SOCKET IC DIP FOUR LEAF CONT GOLD 14 POS 38 3 30 325005 010 1 SOCKET IC DIP FOUR LEAF CONT GULD 40 POS TC 3
65. PWR LSCMLD PDS BANK Pon BAN Ki RESET SMCYC 3 5J i4 CKCPUT MC a QA NC fig 745163 o8 c oc fE CKEB 2 3 2 70 op EKETE g 745157 ay gro L Ne t NE 3 p Fra em A eaa ia a i i I 3 eJ 14 1 aj NC A l wc jg 74563 pe B LI 316 746157 4 2da 8 CHECLE 13 5 2 m c 504 i 4 ne gt Hane i Li el og wit 2 lF b EHRLP pra 9 SGaisze I 5v e2d op sol we ay 8 POTELK BE nn 8 a CLK i 4A P EEL 1 MHE A Er L Blag T 81 i DBLW lie i Id cur i L i H Pa Ne ORNO E EN IE IRR NEA EEE E J Figure 6 2 Logic Diagram Main Logic Board PCBA Sht 3 of 12 903385 Rev A 6 9 10 8070 62 8p TALESAI PRD 17 18 PRFSH PMSEL aD 74 5 15 ig pe PS 7 04 73 12 02 15 4 D 000 016 db 8E 74156541 TE TALSZ45 BFISD 8070 FAIS Paid PAS PAZ PAN PAID PAA PAT PAS PAS PAL PRT fpe Pes PDA PD go p7 De DS 4 DA a yo sr 02 SENN pi SERRE DO MF i PHH i EE TR F Q MIT 1 a ORQ De RD anan RESET LLL ACT
66. Resistance 15 Amperes 0 30 Ohms 20 Amperes 0 25 Ohms 30 Amperes 0 15 Ohms If the measurement in either step a or b is not less than or equal to the value given request the customer to provide a power source that meets the given requirements 2 3 BFISD 8070 2 3 3 Power Supply PCBA Input Voltage Range The EVDT Power Supply PCBA is configured by means of a jumper at its AC input to operate within one of two voltage ranges These voltage ranges are 100 120 VAC 50 60 Hz and 220 240 VAC 50 60 Hz Verify that the AC input voltage range selected for the Power Supply PCBA is compatible with includes the AC voltage supplied by the site power source Figure 2 2 illustrates the config uration of the AC input jumper for each of the two PCBA voltage ranges 2 4 SYSTEMS INTERFACE REQUIREMENTS The EVDT systems and serial printer interface cables along with their point to point connections are listed in table 2 1 Interface cable connections are illustrated in the EVDT Installation procedure of paragraph 2 5 which follows Table 2 1 Systems Interface Cables and Connections SYSTEM FROM CABLE DESCRIPTION PART NO 810 EVDT Port 12 Conductor Cable 8 Way N8 Way Controller RS 232 50 Ft Max PCBA Jl thru J7 907115 XXX 50 60 Hz Fixed Disk EVDT Port A 4 Conductor Cable Signal 8 Channel Terminal CPU System 1000 Ft Max 906693 VAR Controller PCBA 200 210 50 Hz JO thru J7 310 or 410 See Note 906041 VAR 60 Hz Re
67. S BFISD 8070 b 6 CD v2 ASTI ol 8070 56 Power Supply PCBA Figure 5 5 5 20 BFISD 8070 Table 5 5 Parts List Power Supply PCBA MM783010 REFERENCE PART NUMBER DESCRIPTION DESIGNATION NOTE All Part No s are TBD Capacitor 0 01 uF 205 250V Capacitor 4700 pF 202 400V Capacitor 0 22 uF 20 250V Capacitor Electrolytic 100 uF 205 250V Capacitor Electrolytic 200 uF 50 105 LOV Capacitor 470 pF 20Z 3KV Capacitor 0 10 uF 205 IKV Capacitor 0 22 uF 20 100V Capacitor 0 022 uF 204 50V Capacitor Electrolytic 1000 uF C16 C17 50 105 25V Capacitor Electrolytic 330 uF C19 100 20 16V Capacitor Electrolytic 4 0 uF 50 10 25V Capacitor 2200 uF 50 10 16V Capacitor 0 22 uF 20 250V Diode Rectifier RGP10A Diode Rectifier RGP10J Diode Rectifier RGP10M Diode Rectifier 1N4001GP Diode 1N4606 Rectifier Assembly Rectifier Assembly Rectifier Assembly Diode Rectifier RGPIOB 5 21 BFISD 8070 Table 5 5 Parts List Power Supply PCBA MM783010 continued REFERENCE PART NUMBER DESCRIPTION DESIGNATION Diode 1N4606 Diode 1N4606 Diode Rectifier Bridge Rectifier KBPIO Fuse 2A 250V IC Regulator Filter Choke Coil Assembly Filter Choke Coil Assembly Base Choke 2 2 uH NOTE Choke 1 5 mH All Part No s are TBD Filter Choke Coil Assembly
68. SC A Execution of the command causes the character content at the current cursor position followed by a carriage return to be transmitted to the host CPU 2 10 10 Terminal ID Answer Back Message The Terminal ID Answer Back Message is transmitted to the host CPU upon recep tion of the sequence ESC d The ID Answer Back Message consists of eight characters followed by a carriage return The eight characters in the identi fying answer back message provide the following information CHARACTER CODED ASCII HEX SEQUENCE INFORMATION CHARACTER CODE 1 F 46 VDT Type 2 3 0 9 30 39 Firmware Rev Level Example V0 09 0 Language in Use Standard French Italian Swedish Spanish Norwegian German Danish ON Qn RON O Reserved Carriage Return 2 45 BFISD 8070 2 10 11 Changing Personality Attributes The codes for the personality attributes exhibited by the EVDT are shown in figure 2 22 These codes may be displayed on the screen by entering ESC o from the keyboard in Block Mode or host CPU The displayed codes are hex codes indentifying the ASCII character that represents a given attribute When the displayed hex code is 00 it represents NULL or a NO OP condition Temporary modifications may be made to personality attributes through the use of personality change codes Any modification made to a personality code will be reset to its default value following a Keyboard Master R
69. T Tests ZVO4 and ZV05 are especially useful in locating intermittent problems Each of the five tests is described as follows 4 14 1 4V0l Keyboard Echo Test This test should be run when it appears that the EVDT keyboard is not operating properly The program informs the operator that it expects a certain character to be entered The entered character is echoed if it is a printable character Two more lines are used to show the hexadecimal equivalent of the input To indicate a sequence break a third line displays an asterisk when ever the entry is not the expected entry 4V02 Control Interaction Test Performs full function test for all Model 4309 7270 7280 EVDT types The initiating display is run through the various function tests and the user is queried as to the nature of the device s reaction to the test If the individual test fails the user may select a retry of the test 4V03 EVDT Exerciser This test checks that all printable characters can be displayed A test line consiting of all printer defined char acters is displayed on every EVDT line 4V04 EVDT Scrolling Test Checks ability of the EVDT to scroll characters without alteration Test should be run in the event that scrolling appears to malfunction It should be run whenever the Screen appears to be dropping or inserting characters A test line consisting of all printer defined characters is scrolled from the bottom line to the top line and then r
70. TO attribute corresponding to the upper half and SRM1 data and ATTI attribute corresponding to the lower half The memory devices are 2K X 8 RAMs four of which are required two for data storage and two for attribute storage One data and one attribute RAM are assigned to the upper half of the screen and the remaining two are assigned to the lower half of the Screen Twelve address bits AO All are required to address 4K memory locations The twelfth bit 11 is a pointer to either the upper or lower 2K of screen memory and is used in combination with other signals to generate the appropriate chip enable CE input to the addressed RAM Since each RAM is 2K X 8 only 11 address bits A0 A10 are needed to address a particular location in the en abled RAM Character coded information is written into screen memory by the MPU The in formation may be derived when the MPU interrogates the keyboard matrix or it may be received from the communications interface by way of data memory op tional data memory Character coded information is read from Screen Memory by either the MPU or automatically by the control logic during a screen refresh operation The MPU reads the information to effect its transfer to a the host computer via the communications interface b optional data memory for temporary storage a peripheral device such as a printer via the communications interface A screen refresh operation does not occur in one full
71. U and others that may be initiated only at the EVDT key board Figure 2 20 shows the escape sequences recognized by the EVDT along their corresponding operations Escape sequences are immediately acted upon by the EVDT unless preceded by an additional ESC character or unless the Enter Mode paragraph 2 10 6 is set These exceptions will cause the escape sequence code to be displayed and not acted upon 2 28 BFISD 8070 LSB o 0 p CLEAR PRINT R UNFORMATTED PAGE ALL INT PRIN 1 A Q a g SET TAB PRINT INSERT PRINT ET BYPASS CHAR LIN INSERT ENABLE 2 R b f CLEAR TAB a a xr BLOCK DISABL 2 MODE 3 5 SET TABS 8 PARTIAL SEND e ALL TABS ENABLE KEYBOARD 2 ETX EOT tk AR LINE URSOR UN BROFECTEDY E INSERT LINE Y 6 F 1 SEN SEND CHAR RESET LINE ALL SIZE 1 CHAR ATTRIBUTES ATTRIBUTE BEL ETB 7 SEND CHAR 1 PAGE ALL ATTRIBUTE LINE SMOOTH SCROLL ENABLE x 3 FEEREEEREE 35s m q AR PAGE OFECTED 2 RESET TERMINAL RASE PAGE 2 RESET MODES BACK TAB r EXAMINE FUNCTION KEYS LEAR TO lunson SPACES UN PROTECTED CLEAR TO SPACES UN PROTECTED pa SET MOVEMENT FUNCTION KEYS INVOKE FUNCTION KEY ALL E d NE A L CURSOR 1 2 ADDRESS PERSONALITY
72. UA a old ETA 6u INC Oa ati Q9 en CUA LHOIJH A 129929 S22 ayo 90 229 S204 il AQ H Monitor Board PCBA Figure 5 4 BFISD 8070 Table 5 4 Parts List Monitor Board PCBA MM780020 REFERENCE PART NUMBER DESCRIPTION DESIGNATION 38195 3913 Capacitor 390 pF 5 50V Cl 28149 4791 Capacitor 4 7 uF 75 10 25V C2 C9 31115 1031 Capacitor 0 01 uF 5 50V C3 C14 C21 31115 1021 Capacitor 0 001 uF 54 50V C4 16 31115 1541 Capacitor 0 15 uF 5 50V 5 31115 1041 Capacitor 0 1 uF 5 50V C6 7 C13 C33 28148 1011 Capacitor 100 uF 50 10 25V C8 38115 3303 Capacitor 33 pF 5 50V 28128 1021 Capacitor 1000 uF 50 10Z 10V Cll 28148 1021 Capacitor 1000 uF 50 10 25V C12 28148 2211 Capacitor 220 uF 50 10Z 25V C15 31115 2221 Capacitor 0 0022 uF 5 50V 017 018 622 28169 1091 Capacitor l uF 475 104 50V C19 28118 2211 Capacitor 220 uF 50 10 6 3V C20 28128 4711 Capacitor 470 uF 50 10 10V C23 33166 2731 Capacitor 0 027 uF 10 630V C24 39587 1038 Capacitor 0 01 uF 20 IKV C25 C26 C27 C29 28198 4701 Capacitor 47 uF 50 10 100V C28 28000 0001 Capacitor 3 3 uF 75 10 250V C30 28449 6891 Capacitor 6 8 uF 20 25V C31 28449 1001 Capacitor 10 uF 20 25V C32 150019 001 Diode 1N4002 Dl D2 150020 001 Diode 182473 D3 D4 D5 150029 001 Diode RGP20B D6 150022 001 Diode RGP20J D7 BFISD 8070 Table 5 4
73. a tions are used since the A4 address input must be low zero bit and the Al address input must also be low IORQ O for the decode to be effective This reduces the actual number of used locations to eight however the use of a Rom is much more economical than using a complex gating structure employing multi plexers and decoders The ROM is functionally labelled IOCE for I O Chip En able which is true in all cases of the ROM outputs each one is a chip enable of one degree or another as follows RDST Read Status It enables the bit configuration of DIP switch 6L onto the data bus in bit positions PD7 PD2 and as shown on Sheet 11 en ables the KEYRET signal onto PDO and the RETRACE signal onto PDI CTCE Counter Timer Circuit Enable Provides the CE input to the Z80A CTC Sheet 4 when the MPU communicates with the device SIOE Serial I O Enable Provides the CE input to the Z80A DART Sheet 4 which contains two serial I O ports The MPU activates SIOE when it outputs configuration information to either port or transfers data to or from either port CRTE CRT Controller Enable Provides the CE input to the CRT Con troller Sheet 10 when the MPU communicates with the controller during transfers of control and status information DO1 Unlabelled ROM Output Provides one of three enables to the octal decoder 9D Note that the conditional requirements for effective decode are that PMl is high in conjunction with PA
74. able Active positive going transition which triggers all data transfers between the MPU and the data controller Active when both IORQ and CRTE are low i n Pas ppc cc RE u uD 22 RS Register Select Used to access internal registers De rived from AO address bus when CRT SEL is low When AO is low RS low writes are permitted into the address register and the status register The contents of the address register is the identity of the register accessed when RS is high E N N N N fow N Co o 2 CE Chip Enable The CRTC is enabled when the CE input is low which is the case when CRTE is low from I O address decode LA 3 24 BFISD 8070 Table 3 2 CRT Controller Pin Outs continued SIGNAL DESCRIPTION FUNCTION 26 33 D7 DO Data Bus The D DO pins are the eight data lines used for transfer of data between the MPU and CRTC D7 DO correspond to PD7 PDO 34 38 RA4 RAO Raster Address Lines not used HSYNC Horizontal Sync Active high output pulse used to deter mine the horizontal position of displayed text HSYNC time position and width are fully programmable VSYNC Vertical Sync Active high output pulse used to determine the vertical position of displayed text VSYNC position and width are fully programmable 3 6 6 1 CRTC Internal Registers There are eighteen registers in the CRTC RO R17 accessible to the MPU that is they may be written into and read from and
75. ach control code is entered The Enter Mode is set with ESC V from the keyboard in Block Mode or host CPU The Enter Mode is reset with ESC v from keyboard or host 2 10 7 Using the Insert Mode The Insert Mode permits characters to be inserted without use of the Insert Character command table 2 6 In this mode all unprotected characters from the cursor positon to the end of the line are moved one position to the right after a character is entered If the line was full before the entry the last character on the line is lost If a protected field is encountered and characters cannot be shifted to the right the Insert Mode will not function The Insert Mode is set with ESC q from the keyboard in Block Mode or host CPU The Insert Mode is reset with ESC r from keyboard or host 2 43 BFISD 8070 2 10 8 Setting the Limited Screen Mode The Limited Screen Mode limits the number of active display lines available to the EVDT operator The number of active lines to which the display is limited and the location of the active lines on the display top middle bottom is at the user s discretion or as commanded by system software To set the Limited Screen Mode enter ESCAPE CLEAR s in Block Mode Then enter the ASCII characters from table 2 15 which correspond to the starting and ending row numbers 1 to 24 of the active display lines An example of setting this mode is ESCAPE CLEAR s s x This escape sequence
76. ad NOTE If Pad Lock or Shift Lock is enabled Pd or Sf is displayed on Status Line the numeric keys on the numeric keypad will not operate Hold FUNCTION key down and press PAD key to disengage Pad Lock hold SHIFT key down and press CAPS LOCK key to disengage Shift Lock Selecting parameters in the Setup Mode is basically the same when using either the single line or full screen SETUP menu To select and change a parameter simply position the block cursor at the box to be changed and enter the appropriate character from the keyboard The O or 1 O thru F for Baud Rate and 0 thru 7 for Cursor and Language are the only valid characters all others will result in a bell tone indicating an attempted illegal character entry Illegal characters will not be accepted Select the desired code characters from table 2 2 The SETUP menu cursor position is changed with the space bar or RETURN key Press the space bar to move the cursor from left to right one box position at a time on the same line The cursor will return to the first box on the same line if advanced from the last position Press the RETURN key to advance the cursor to the first box of the next line The single line SETUP menu is manipulated by using the RETURN key to change lines in the menu for example to change from line 3 to line 4 in ascending numerical order Use the space bar to move to cursor position within a single line To terminate the single line SETUP
77. and attribute latches i e an all zeros dot code is presented for the duration of the time DISLIN remains in the low state and likewise no display attributes are presented 3 34 BFISD 8070 0000 1 0000 QV01 0000 avo1 Single Height Character Timing Figure 3 14 3 35 BFISD 8070 0000 QVO1 OTTO avon 0000 QVO 8070 39 iming Double Height Character T Figure 3 15 3 36 Figure Double Width Timing BFISD 8070 BFISD 8070 3 6 9 Composite Sync and Video Circuits The composite video circuits are shown on Logic Diagram Sheet 10 The circuits consist of the buffer register 117 the digital to analog converter 4L the brightness control circuit associated gates and drivers and the Blink frequency generator The display attribute bits from Screen Memory together with the DISP signal from the CRTC and the Half Intensity signal HFINT from the character data buffer are clocked into buffer register 117 coincident with the positive going edge of SMCYC The buffer outputs provide the control signals that determine the manner in which characters are to be displayed The only signal not buf fered is the composite sync signal which is the Xor of HSYNC and VSYNC VDR as shown in figure 3 17 The VSYNC latch 12E provides an output that converts the duration of VSYNC into a multiple of HSYNC pulses and in so doing syn chronizes the vertical drive pulse with the horizontal drive pulse It
78. baud rate Extension Port not on 3 Cable not connected 4 Pins 2 and 3 reversed in printer cable 4 5 BFISD 8070 4 3 3 Fault Isolation Fault isolation is the follow up process of applying the appropriate mainten ance procedures to isolate the source of malfunction to the assembly or com ponent replaceable in the field These maintenance procedures include perform ing DC voltage checks test point signal tracing circuit adjustments and diagnostic tests in an attempt to locate the malfunction 4 3 3 1 DC Voltage Checks Three non adjustable DC voltages are provided by the Power Supply PCBA They are and 12 volts DC and 5 volts DC These three voltages are measured at connector Jl on the Main Logic PCBA Figure 4 2 shows a top view of connector Jl and the pins at which the voltages are measured The Power Supply PCBA should be replaced if the voltages specified in the following procedure do not fall within their respective ranges WARNING Hazardous voltage is preset within the EVDT en closure Use caution when working with the rear housing removed 1 Remove rear housing of video display assembly as instructed in paragraph 5 2 Section V 2 Locate connector Jl figure 4 2 at the rear edge of the Main Logic PCBA 3 Apply power to the EVDT 4 Check for the following voltages on pins 2 5 and 7 of connector Jl e Pin 2 12VDC 1 55V e Pin 5 5VDC 0 25V e Pin 7 12VDC 1 5
79. ce of the EVDT It is executed only on the EVDT with the serial printer actually configured as a slave printer The printer status is not checked in these tests While the test is being run errors found will be displayed on the video display screen When the test is completed a readout will be displayed printout if requried stating what tests were run errors found and possible fault locations One pass of the EVDT Diagnostic Test takes approximately 15 minutes if no Operator Intervention or Extended Run Time options are selected 4 11 BFISD 8070 4 0 VOLTS SYNC POSITIVE OR NEGATIVE 47 82 Hz TP2 1 0V DIV DC 0 2ms DIV TP3 2V DIV DC 5ms DIV TP4 0 2V DIV AC 5ms DIV TP5 0 IV DIV AC 5ms DIV TP6 10V DIV DC 5ms DIV TP7 5V DIV DC 5ms DIV TP8 0 IV DIV AC 5ms DIV TP9 IV DIV AC 5ms DIV TP10 0 2V DIV AC 5 DIV TP11 2V DIV DC 10uS DIV TP12 5V DIV DC 10uS DIV e Figure 4 5 Monitor Board Waveforms sheet l of 2 4 12 BFISD 8070 TP13 1V DIV DC 10uS DIV TP14 0 5 DIV DC 10uS DIV TP15 2V DIV DC 10uS DIV HH u i TP16 50V DIV DC 10uS DIV TP17 TP20 50V DIV DC 10uS DIV Figure 4 5 Monitor Board Waveforms sheet 2 of 2 4 13 BFISD 8070 4 3 3 5 BASS System Level Diagnostic Tests The five BASS tests which exercise the EVDT directly are 4VOl thru ZVO5 This series of tests typically take less than 30 minutes to perform and can be invaluable in quickly locating problems in the EVD
80. change Write Protect Mode is reset BFISD 8070 Table 2 6 Data Editing Control Operations Block Mode continued FROM HEX OPERATION FROM KEYBOARD HOST CODE 5 Delete Character FUNC X ESC W 7 51 31 NER Insert Character FUNC Z ESC Q RES T 32 ESCAPE CLEAR 1 Esc 1 30 Set Tabs Every Fighth Column Clear All Tabs ESC 0 DESCRIPTION Deletes character under cursor and moves all un protected characters located on right of cur sor one positon to left Protected characters under cursor and those following a Protected character are not affect ed Write Protect Mode is reset All unprotected char acters from cursor posi tion to end of line or current field if Protect Mode is set are moved one positon to right Any character in last position of line or field is lost Protect ed characters under cur sor and those following a protected character are not affected Write Pro tect Mode is reset Sets tab stop for column where cursor is position ed Clears tab stop from column where cursor is positioned Sets tab stops for entire screen at every right column Clears all tab stops for all columns Dr LoD OU U 2 9 6 Data Editing Control Operations The EVDT special function keys permit Block Mode editing of displayed data before transmission to the host CPU or local printer Table 2 6 lists and describes the data
81. character generation logic is shown on Logic Diagram Sheet 9 of the following functional elements e Character Generator Font 0 10G e Character Generator Font 1 8G e Parallel to Serial Converter 7G e Character Line Scan Counter 10F It consists e Line Attribute Buffer one half 11 Before discussing details of character generation it is necessary to explain how a character is formed letter L Figure 3 12 A character row occupies 12 scan lines hexadecimal which is equivalent to binary 0000 1011 depicts the generation of an upper case The lines are numbered O B It follows that a 4 bit binary counter will fulfill the requirement for counting character line scans The line scan occurs across all If the line scan counter is incremented the end of the previous scan after 12 will have been scanned If the counter repeated for the next character row and cal blanking takes place at which time played 80 columns or one horizontal line scan at the beginning of each scan or at such scans a complete character row is re initialized the cycle will be subsequent character rows until verti 24 character rows will have been dis The character generator contains the data necessary to form a charcter on a line by line basis This data is fed serially to CRT so that as the scan passes a particular position in the character matrix the electron beam is in tensified to illuminate that position according t
82. characters All 32 control characters may be generated at the keyboard but only 10 are recognized by the EVDT as opera tional control characters Non operational control characters are displayed as reversed video characters The 10 operational control characters are nor mally not displayed but are acted upon by the EVDT when entered at the key board or received from the host CPU Details of keyboard operation are discussed in Sections II and III International keyboards are available with appropriate keycaps to support the language selected Also available is the Katakana keyboard which produces an additional 64 JIS standard symbols for a total of 159 displayable char acters 1 2 2 Video Display Assembly The Video Display Assembly figure 1 2 consists of a two piece enclosure CRT bezel and rear housing that contains the following components e Monitor Assembly e Main Logic Board PCBA e Power Supply PCBA 1 3 BFISD 8070 KEYBOARD ASSEMBLY DETACHABLE CORD A KEYSWITCH MATRIX MONITOR PCBA LOGIC PCBA VIDEO DISPLAY ASSEMBLY REAR HOUSING REMOVED Figure 1 2 Major Assemblies and Related Components Model 4309 EVDT 1 4 BFISD 8070 1 2 2 1 Monitor Assembly The Monitor Assembly figure 1 2 consists of a CRT that displays the alpha numeric and graphics characters and a Monitor Board PCBA that provides the high voltage video and deflection circuits required for CRT operation The CRT face
83. conds which is considerably faster than an operator making successive key strokes 3 8 BFISD 8070 LNO viva OLX8 XIYLVW QUVO8A3 TOYLNOD ONIWIL 318VN3 MOU NOISYJANODJ TITIVYVA IVIYIS LAdNI 39000 XIYLVW VIVO 1viH3S 8070 28 Block Diagram Keyboard Logic Figure 3 4 3 9 BFISD 8070 3 6 DETAILED LOGIC DESCRIPTION 3 6 1 Microprocessor Unit The Microprocessor Unit MPU is a Zilog Z 80A A block diagram of the MPU architecture is provided in figure 3 5 The pin out table is given in table 3 1 Details of the internal functions of the MPU can be found in the Z 80A Component Data Catalog The MPU is shown on Sheet 4 of the Main Logic Board diagram in Section VI The signal names and pin numbers are as shown and may be referenced to table 3 1 for functional descriptions Logic Diagram Sheet 4 shows that the address bus drivers 8C and 8E are en abled by the inverse of BUSAK such that when BUSAK is high the address bus drivers are enabled The data bus driver ZE is bidirectional One of the enables is tied to digital ground the other is generated from 11G 6 being low for Read operations PD7 PDO to D7 DO and high for write operations D7 DO to PD7 PDO Since BUSAK is considered high BUSREQ is tied to 5V one per manent enable is provided to AND gate 11G 5 The remaining input is high when RD is low write operation when the counter timer CTC is enabled CTCE 0 when the DART is enabled SIOE
84. d and the sequence ends when XMSEL goes high During a memory refresh cycle the MPU activates PMREQ and PRFSH and places a refresh address on PA6 PAO XMSEL is not activated so that the two flip flops are held in the reset state Since the first flip flop is held reset the A inputs to the multiplexers the refresh address appears as A6 A0 PRFSH and PMREQ activate RAS while CAS cannot be activated In other words only the row address is generated during a memory refresh cycle 3 18 BFISD 8070 3 6 4 System Clock Generation The system clock generator is shown on Logic Diagram Sheet 3 It consists of a crystal oscillator 5G a 4 bit binary counter 5J two quad 2 1 line multi plexers 7J and 8J and associated gates Also shown is the optional 132 column clock generator and its associated counter 6J In the following description 80 column display operation is assumed WID80 low and the character clock is for normal width characters DBLW low so that the multi plexers select the A inputs The timing relationship is shown in figure 3 7 The oscillator output is counted down to provide CKCPU2 at 7 3728 MHz CKCPU at 3 6864 MHz CKC80 at 1 8432 MHz and CKCTC at 921 6 KHz CKCPU provides the phase clock input to the MPU and is selected by multiplexer 7J to appear as CKD3 The multiplexer also selects CKCPU2 to appear as CKD2 and CKC80 to appear as SMCYC Screen Memory Cycle Both multiplexers 7J and 8J select the oscillato
85. de is entered by typing the escape sequence ESCAPE CLEAR The specific self test is executed following keyboard entry of the corresponding control code e CTRL ROM Checksum Test e CTRL MPU Scratchpad RAM Test e CTRL Display Memory RAM Test e CTRL D LSI Devices Register Test e CTRL Tests Audible Tone The successful completion of each test is indicated by an audible tone or beep other key pressed in the Self Test Mode will cause the correspond ing character to be displayed at every location on the display matrix thus testing the character generator The Self Test Mode is terminated by pressing ESCAPE CLEAR 2 9 4 Escape Sequences An escape sequence is formed by entering ESCAPE CLEAR or CTRL C and one or more normally displayable ASCII characters Each escape sequence controls a specific EVDT operation Escape sequences can also be used to control the operation of a printer that is connected to the EVDT Many escape sequences emulate EVDT operations that are normally controlled by the host CPU Other escape sequences are peculiar to local operations and effect only keyboard and or display characteristics Some escape sequences control EVDT operations that are one time only operations while others remain functional for as long as power is applied or until terminated by another escape code Finally there are certain escape sequences that may be initiated only from the host CP
86. e 4J such that its output goes high and 3G 8 goes low VIDTTL 0 i e there is no video dot matrix signal If BLANK is low Nand gate 4J 4 is enabled and the output from 2G 6 is inverted by ROWLD 4J 5 which is in effect when the DISP Display Enable signal is low i e video is inhibited for the period DISP is low e g during horizontal and vertical flyback periods Note that VIDTTL is referenced to 5V high and OV low and represents the dot matrix code in one or other of the attribute formats whereas VIDIN is referenced to 12V and 12V and represents composite sync brightness level and intensity level There is no signal combination that represents composite video 3 40 BFISD 8070 3 6 10 Keyboard Interface The keyboard code generator and interface logic is shown on Logic Diagram Sheet ll It consists of the parallel to serial converter 10B the clock counter 12C the timing and synchronization flip flops 13C Nand gates 10J and two inverters 1G The MPU interrogates the keyboard by transmitting a matrix code to the key board logic The matrix code effectively addresses one of 80 keys If the addressed key has been pressed the response from the keyboard is equivalent to a one bit or high level If the addressed key has not been pressed the response is a zero bit or low level In this way the MPU scans all 80 keys matrix positions in less than 12 milliseconds The timing of a single key scan is shown in figure 3
87. e Op Code Fetch cycle of an instruction execution M1 also occurs with IORQ to indicate an interrupt acknowledge cycle During execution of 2 byte op code M1 is generated as each op code byte is fetched from program memory Ml Machine Cycle One MREQ Memory Request Active low tri state output MREQ low signifies that the address bus holds a valid address for main memory or Screen memory IORQ Input Active low tri state output IORQ low signifies that Output Request the lower half of the address bus A0 A7 holds a valid I O address for an I O read or write operation IORQ is also generated with MI when an interrupt is being acknow ledged to signify that an interrupt response vector can be placed on the data bus Acknowledge operations occur during Ml time while I O operations never occur during Ml time RD Memory Read Active low tri state output RD low signals that the CPU wants to read data from memory or an I O device RD is used to enable the transfer of data from the addressed memory or I O onto the data bus WR Memory Write Active low tri state output WR low signifies that the data bus holds valid data to be stored in memory or transferred to the device RFSH Refresh Active low output low signifies that the lower address bits AO A7 hold a refresh address for dynamic memories and that the current MREQ low signal is to be used to perform a refresh read
88. e Read Pin 3 SBCEO Screen Buffer Chip Enable Zero Pin 2 SBCEl Screen Buffer Chip Enable One Pin 1 SACEO Screen Attribute Chip Enable Zero Pin 9 1 Screen Attribute Chip Enable One Pin 6 low Write high output read Note that the ROM is represented functionally as a gating structure to give the reader some idea as to the content of the addressed location 3 6 5 2 Arbitration Logic The Arbitration Logic consists of the dual J K flip flop 14C and various gates 14D and 11G The logic gives priority to the MPU for access to screen memory if the MPU is not addressing Screen Memory then a screen refresh operation is automatically taking place The timing sequence is shown in figure 3 9 with respect to a MPU memory re ference operation When the address specifies screen memory SMSEL goes high and the first of the two flip flops 14C is clocked into the set state If 132 columns are specified WID80 1 a Wait condition is imposed SMWAIT l and a wait period is inserted between Tl and T2 Then when SMCYC goes low the second flip flop is clocked set If 80 columns are specified the second flip flop is preset when SMCYC goes low In either case 14C 7 goes low to select the A inputs to the Address Multiplexer 13F 14F 15F and the MPU address lines select a memory location At the same time the first flip flop is cleared and registers 10L and 11L are clocked to load in the data read from the selected location
89. e a w a a w c a e oo e 3 12 CRT Controller Pin Outs lt lt au a a a e o 3 24 DART Pin Out Description e e lt a a non 3 46 EVDT Troubleshooting Guide e w e e e w 4 4 Parts List EVDT Video Display Assembly a 5 9 Parts List EVDT Keyboard Assembly au 5 11 Parts List Main Logic Board PCBA 780010 5 13 Parts List Monitor Board PCBA MM 80020 e 5 16 Parts List Power Supply PCBA MM783010 ou 5 21 Keyboard PCBA a gt kondo Wo wow sa So 2725 EVDT to DCE Host CPU tate ti Signals ee 6 32 EVDT to Serial Printer Interface Signals 6 32 Il l d l l l t KON na E ra M iO M e N OU FON GON OO OND viii BFISD 8070 PREFACE This manual contains service information for the Model 4309 Ergonomic Video Display Terminal Machine Type 4309 The information is presented as an aid and will enable field service personnel to install operate and maintain the equipment The major topics covered in this manual are Section I Section II Section III Section IV Section V Section VI Introduction Installation and Operation Functional Description Maintenance Removal Replacement Spare Parts WARNING This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions man
90. e by the inter rupting device the MPU goes into the interrupt service routine When the interrupting device has been serviced it reactivates its IEO line The Reset input to the MPU is derived from the Power On Clear signal POC Logic Diagram Sheet 5 shows that POC is generated from the RC circuit consisting of R3 and C71 configured as an integrator When power is first applied C71 draws maximum current such that POC goes low C 1 then charges towards 12V but is limited to 8 6V by Zenor diode The time constant determines how long POC is low but once C71 is charged POC is high and the MPU reset condtion is removed 3 6 2 Memory and I O Address Decode The memory address decode logic is shown on Logic Diagram Sheet 6 and the I O address decode logic is shown on Sheet 3 The logic is quite simple and therefore does not warrant a block diagram In both cases the decode is effected by a 256 bit ROM configured as 32 eight bit words The output of the ROM is determined by the 5 address inputs which include conditional inputs 3 6 2 1 Memory Address Decode Memory as a whole consists of program memory screen memory data memory and the addition of optional data memory four memory segments in all each of which is described in later paragraphs Program memory can only be selected when PMREQ is low MREQ from the MPU Logic Diagram Sheet 5 shows the Memory Address Decoder or Memory Select Rom as device 9C The ROM e
91. e counter output BLINKCK Blink Clock represents 32 frame periods It is low for 16 frame times then high for 16 frame times approxi mately equivalent to a half second off and a half second on When blinking is enabled BLINK 1 the Blink output of buffer 11 provides an enable to Nand gate 4J pins 1 and 2 which then inverts BLINKCK at its output 4J 12 This output provides an alternating enable to Nand gate 4J pins 9 and 10 which then alternately inverts VIDOUT and enables the Nand gate In this way the matrix code is displayed for 16 frame times then inhibited for 16 frame times which give it the appearance of flashing or blinking Note that this function can be accurately controlled by the MPU to include any number of characters If blinking is disabled BLINK 0 4J pins 9 and 10 are held at the high level so that VIDOUT appears inverted at 14J 8 3 38 BFISD 8070 ll I 4 44 21 48 YAA OTI JE 9NASA S 3 I Ot NId 182 JNASA Composite Sync Figure 3 17 3 39 BFISD 8070 If Underlining is specified ULINE 1 the output of buffer 117 pin 6 provides an enable at Nand gate 9F pin l The remaining three inputs to Nand gate 9F are derived from a selected combination of line scan counter outputs either CAO CA or CAl CA2 Reference to figure 3 14 shows the first combination coincides with line 12 the last line in the dot matrix w
92. e line scan counter counts each ROWLD clock appearing as ROWCK i e it counts 12 rows and is then parallel loaded Its outputs CAO CA3 determine the four address bits A0 A3 to the character generator These four address bits represent a 4 bit binary number for the duration of one complete line scan while the other address bits change as the scan passes each character position The line scan counter is enabled for counting in this mode by the QA output of the associated divide by two counter which provides the P enable to the line scan counter The divide by two counter is itself parallel load coincident with the line scan counter so that the QA output is high In this case the P enable to the divide by two counter is low DBLW low so that it cannot count and the QA outputs remains high Note that by default DBLH low single height BFISD 8070 Double Height Mode To double the height of a character row the same line scan is repeated once so that a character row consists of 24 line scans 12 identical pairs To effect double height character the divide by two counter is enabled to count so that the line scan counter counts alternate ROWCK clocks so that CAO CA3 are constant for the dura tion of two line scans The character row counter still generates a carry output at the end of 12 line scans but in effect counts two character rows for each couble height row displayed In this case the divide by two counter is parallel loaded as
93. e not displayed on screen All characters received from printer are passed on to host CPU EVDT keyboard does not respond in Display Bypass mode mode disabled by ESC B from host only BFISD 8070 2 10 12 EVDT Reset Operations Two EVDT reset operations are available Reset Terminal and Keyboard Master Reset Reset Terminal is executed upon reception of ESC z from the host CPU or by entering CTRL FUNC ESCAPE CLEAR at the keyboard This reset operation causes all data on the screen and in the input data buffer to be lost Keyboard Master Reset is executed by entering CTRL SHIFT FUNC ESCAPE CLEAR at the keyboard This reset operation not only causes all data on the screen and in the input data buffer to be lost but also erases the content of all Programmable Function Keys and resets all Personality attributes and Setup Mode parameters to their default values 2 10 13 Keyboard Enable Disable Keyboard disable is executed upon reception of the sequence ESC from the host CPU only All key presses are ignored Kl keyboard lock will appear on the display status line Keyboard enable is executed upon reception of the sequence ESC from the host CPU only 1 will be removed from the display status line 2 10 14 Title Indicator Modification A user definable title with 1 to 10 double width single height characters may be displayed at the left side of the display status line When shipped from the factory
94. e of the EVDT is 24 rows X 80 columns 24 X 80 1920 characters If the character positions are numbered sequentially from left to right row by row in normal reading order the display matrix appears as shown in figure 3 1 The positional arrangement is fixed and is called a page Each position may display a character or it may be blank noting that a blank has a character code 1840 Figure 3 1 Display Screen Matrix 24 X 80 BFISD 8070 In simple terms each numerical position in the display matrix has a corres ponding location in screen memory such that the character code in the loca tion whose address is 0 generates the character that is displayed in matrix position 0 and so on It follows that in a 24 X 80 display matrix there must be 1920 locations in screen memory It is impractical to devise a memory addressing scheme for 1920 locations so the actual screen memory contains 2048 locations In practice the display is split in half in terms of screen memory such that each segment contains 1024 locations which corresponds to 210 in binary notation i e 10 binary digits bits are required to address 1024 memory locations In association with screen memory are two segments of screen attribute memory each containing 1024 locations which have a direct correlation with the corresponding addresses in screen memory Screen attribute memory determines how the display is to appear for a particular character position e g bli
95. eT TeTRTS T VE TT L l tines RES ERUNT s VERTICAL TOTAL R4 VERTICAL DISPLAYED R6 SRA siman gi ui mi misa wm ss misi IL vertica TOTAL ADJUST R5 8070 34 Figure 3 10 Typical Video Display Format 3 26 BFISD 8070 R3 Horizontal and Vertical SYNC Widths 00011 This 8 bit register contains the widths of both HSYNC and VSYNC as follows R3 7 6 5 4 3 2 1 0 VSYNC HSYNC Number of scan lines Number of character clock times VSYNC being a wider pulse is expressed as being as wide as the time it takes to complete N horizontal scans HSYNC which occurs once for each character row is of much shorter duration and its width is expressed as the duration of N character clock periods R4 Vertical Total 00100 The vertical total register is a 7 bit register containing the total number of character rows minus one in the display matrix figure 3 10 This register in conjunction with R5 determines the overall frame rate which is usually close to the line frequency to ensure flicker free appearance R5 Vertical Total Adjust 00101 This is a 5 bit write only register containing the additonal number of scan lines needed to complete an entire frame scan and is intended as a fine adjustment for the video frame time figure 3 10 R6 Vertical Displayed 00110 This 7 bit register contains the number of displayed character rows in each frame In this way the
96. ead by the EVDT under CPU control Altered characters are logged The test line is rotated by one character and the test is repeated until each character of the test line has appeared in the first position 4V05 EVDT Print Test Position Control Checks ability of the EVDT to do 8 position control to any place on screen A full screen image is constructed using the position control for each byte displayed The test pattern is then read on a line by line basis and checked against the target pattern Altered characters are jogged Proper functioning of the scrolling operation is a prerequisite for the test Scrolling errors will cause a failure of this test BFISD 8070 SECTION V REMOVAL REPLACEMENT SPARE PARTS 5 1 INTRODUCTION This section contains disassembly and parts removal replacement procedures for the Model 4309 EVDT This section also contains an illustrated parts list with PC board layouts and exploded views as applicable 5 2 GENERAL DISASSEMBLY The following procedures provide access to the internal subassemblies of the video display assembly and the keyboard assembly 5 2 1 l WARNING Turn off the EVDT power switch and remove the power cord from the ac outlet before removing the rear housing of the video display assembly Failure to do so may result in severe shock which can be fatal or may result in serious damage to the equipment Always discharge the CRT anode to ground with a grounding stra
97. ears Adjust the vertical height of the screen to measure 6 1 2 inches from the top of the display status line BFIS 4309 BK A HH MM SS to the bottom of the last row of Es Rotate vertical V HEIGHT control VR3 from front side of Monitor Board Adjust the horizontal width of screen to measure 8 1 2 inches from first E to last E in a row Using a non metalic hexagonal alignment tool rotate horizontal WIDTH control L2 from back side of Monitor Board Adjust vertical linearity at top and bottom of screen for equal number of rows Es in l inch vertical measure Rotate vertical V LINE arity control VR4 from back side of Monitor Board CAUTION Use care in the following step to avoid dislodging the rotating magnetic core from the housing of hori zontal LINEarity control L3 Adjust horizontal linearity at left and right side of screen for equal number of Es in l inch horizontal measure Rotate horizontal LINE arity control L3 from back side of Monitor Board Adjust video focus for sharp characters Rotate FOCUS control VR6 from back side of Monitor Board 4 9 BFISD 8070 ONIYILNIJ AIISYA 304 31Vl0M Savi 9NIU3IN329 NOIL9391440 1NFWLSNCQY 17111 3804 31109 AT9WISSY 3504 INIWLSNCAY 1111 304 N3S001 MIYIS 5NI3201 3304 ali CRT Yoke Adjustments Figure 4 4 4 10 BFISD 8070 4 3 3 3 Monitor Board Signal Tracing Signal tracing may be used to verify the Monitor Board PCBA as being the source of displa
98. ed the MPU can wait until the port goes idle and then ask the transmitting device usually the host to retransmit the message or infor mation When the terminal has data from transmission the MPU places the first char acter into the transmit buffer of one port in the DART and the DART transmits a formatted character down the line bit by bit On completion of character transmission the DART interrupts the MPU to request replenishing the transmit buffer and transmission continues If the MPU is communicating with the host it turns the port around and waits for a response If the MPU is communicating to an output device it interrogates the device by asking for the device status In this way the MPU can determine if the information was received by the device and if the device malfunctioned BFISD 8070 3 5 KEYBOARD LOGIC The keyboard logic is represented in block diagram form in figure 3 4 The keyboard is functionally arranged as an 8 X 10 matrix as figure 3 4 shows The keys are inductively coupled by means of an auto transformer to the output circuit When a key is pressed a magnetic core is inserted into the coupling such that if a current is flowing through the transformer a current is induced in the pick up winding The induced current is detected as an induced voltage by the output circuit and registered latched as one bit If a key has not been pressed there is no induced voltage and a zero bit is registered by the output circ
99. ed as an aid in parts removal and replacement procedures The parts lists and their associated illustrations are listed in the Illustrated Parts List Index which includes the figure and table number title and page number for each assembly whose parts are listed Assemblies and parts which are recommended for stocking in the Field so as to minimize equipment down time in the event of failure are designated by a Sorbus Inventory Control Number ICN 5 5 6 BFISD 8070 ILLUSTRATED PARTS LIST INDEX TABLE TITLE PAGE EVDT Video Display Assembly EVDT Keyboard Assembly ICN MM783020 Main Logic Board PCBA ICN MM 80010 Monitor Board PCBA ICN MM 80020 Power Supply PCBA ICN MM 83010 Keyboard PCBA 5 7 BFISD 8070 Ex Y EN 4 PLACES Figure 5 1 EVDT Video Display Assembly 5 8 BFISD 8070 Table 5 1 Parts List EVDT Video Display Assembly FIG 5 1 ICN INDEX NO DESIGNATION PART NO QTY EE Rear Shield EMI not shown Bezel PCBA Main Logic Board Refer to table figure 5 3 Cable Assembly Logic Board to Monitor Board PCBA Monitor Board Refer to table figure 5 4 CRT Green P31 12 inch PCBA Power Supply Refer to table figure 5 5 Bracket Power Supply Switch Power On Off Receptacle Power Cord Chassis Subassembly 110 VAC 3 wire Power Cord Plate RS 232 Ports not shown MM780010 MM780020 MM783030 MM783010 05 5006 12 907369 05 5
100. ed data from display memory and output a character code to the composite video logic along with data from the character attribute and character con troller logic The CRT controller generates the horizontal and vertical sync pulses and the cursor signal The cursor signal is used to indicate when the raster scan coincides with the cursor position or display memory address at which point the character is displayed on the screen When data is transmitted to the host CPU or serial printer the MPU retrieves a character from display memory and sends it to the communication interface The communication interface transmits the character bit by bit Start and stop bits as well as the parity bit as specified are included with each character transmitted Details of Main Logic Board operation are discussed in Section III The Main Logic Board PCBA includes two 25 pin data interface connectors DB 25P or equivalent D Type for I O ports A and B The connectors are accessible at the rear of the EVDT for cable connections to the host CPU and a serial printer Also included on the Main Logic Board PCBA is a rechargeable 5 volt backup battery for the CMOS RAM continuous memory 1 5 BFISD 8070 1 2 2 3 Power Supply PCBA The Power Supply PCBA figure 1 2 produces and 12 volts DC and regulated 5 volts DC The 12 and 5 volt outputs are supplied to the Main Logic Board while only the 12 volt output is supplied to the Monitor Board and only
101. ed for display or execution of control function Keyboard codes are displayed or acted upon and are sent to host CPU Data received from host CPU is displayed or acted upon Keyboard codes are displayed or acted upon but not sent to host CPU Data received from host CPU is displayed or acted upon Permits editing of data Requires use of Special Function Keys for Block Mode data transmission BFISD 8070 Table l l Specifications Model 4309 EVDT continued PARAMETERS CHARACTERISTICS GENERAL cont d CRT Monitor Display Size Deflection Angle Refresh Rate Phosphor High Voltage Horizontal Frequency Horizontal Period Horizontal Retrace Time Horizontal Drive Pulse Width Horizontal Video Blanking Time Horizontal Lead Lag Vertical Frequency Vertical Period Vertical Retrace Time Vertical Drive Pulse Width Vertical Video Blanking Time Vertical Lead Lag 8 5 inches x 6 inches 21 6 cm x 15 cm 90 degrees 50 or 60 Hz non interlaced P31 Green 13KV 19 25 KHz 50 60 Hz 51 7 microseconds 6 5 microseconds max 4 23 microseconds 12 microseconds 2 0 microseconds 50 60 Hz 20 milliseconds 50 Hz 16 67 milliseconds 60 Hz 800 microseconds max 0 1 1 2 milliseconds 4 5 milliseconds 50 Hz 1 2 milliseconds 60 Hz None 1 9 BFISD 8070 Table 1 1 Specifications Model 4309 EVDT continued PARAMETERS GENERAL cont d Keyboard Physical Layout Cha
102. editing operations that may be controlled from the EVDT keyboard along the escape sequences permitting their control from the host CPU 2 9 7 Data Transmission Control Operations Special function codes and escape sequences permit selective transmission of displayed data when operating in the Block Mode Table 2 7 lists and describes the data transmission operations that may be controlled from the EVDT keyboard along with the escape sequences permitting their control from the host CPU Additional information on data transmission is provided in Section III 2 9 8 Print Transmission Control Operations Table 2 8 lists and describes the print transmission operations that may be controlled from the EVDT keyboard as well as the escape sequences permitting their control from the host CPU Additonal information on print transmisssion is provided in Section III 2 9 9 Business Graphics Mode The escape sequence ESCAPE CLEAR from the keyboard or ESC lt from the host CPU will place the EVDT in the Business Graphics Mode While in this mode the keys that normally produce alphabetical characters and certain punc tuation characters will instead produce the graphics characters listed in table 2 9 ESCAPE CLEAR gt will disable the Business Graphics Mode 2 10 EVDT PROGRAMMING Several features of the EVDT are software controlled and require keyboard pro gramming to establish or further define their characteristics Examples are di
103. efer to table 2 11 Table 2 11 ASCII Code Conversion Clock Display Values CLOCK DIS PLAY DISPLAY VALUE WAN ON Qn LF WN 00 Ui ON ONKKE lt c rg m g O Z E 8 d i G 1 Vo AN we eu 2 38 BFISD 8070 2 10 2 Establishing Protected Fields Protected fields are those areas on the EVDT display that cannot be over written deleted erased or cleared Any type of form appearing on the dis play especially when originating at the host CPU will usually have its char acters attributes and graphics set in protected fields These fields are easily identified by their reduced intensity characters and by the fact that the cursor cannot be located upon any protected character in the field When protected fields are present Pr Protect Mode is displayed on the status line and the insert line delete line and scrolling functions are disabled Protected fields are established through a four step process First the Write Protect Mode is set from host or keyboard by executing ESC The characters forming the protected field are then entered and are displayed at reduced intensity Next the Write Protect Mode is disabled by executing ESC Finally the Protect Mode is set by executing ESC amp Pr is displayed on the status line and all characters displayed at reduced intensity are established as a protected field The Protect Mode is disabled b
104. emovable Disk CPU Interface Cable Connections e e s s s au a w a a a a n EVDT Cable Grounding e e e s a a a n Full Screen Setup Menu and Status Line a a FUNC with EXAM F Display e s au au au au a Layout and Keyswitch Functions Domestic Keyboard Keyboard Layout Danish lt a a a a n Keyboard Layout French e lt a a au au au a a a a gt Keyboard Layout German e s s e a n Keyboard Layout Italian s lt au a a a a Keyboard Layout Norwegian e e a a a a au a e n Keyboard Layout Spanish e s a a a au a a a an Keyboard Layout Swedish e e a a a a n Displayable Character Set Standard Domestic and EVDT Control Codes e e e e e e e e o o eo eeo EVDT Escape Sequences lt w a a e a n Display of Programmed Function Key Commands Personality Attribute Codes e s lt a a a a o Display Screen Matrix 24 X 80 a w o Character Matrix e e e a a oo Block Diagram Main Logic Board e e a Block Diagram Keyboard Logic a a a a a o MPU Block Diagram e lt lt a au a a a a a o Dynamic RAM Row Column Address Sequence e Clock Timing Dot Clock Timing Clock and Character Load e s e w w a GRO S w en S Block Diagram
105. eros also depicts pulse width modulated data where a one bit is double the width of a zero bit The response from the keyboard appears as KEYIN which is a high level to signify that the addressed key was pressed or conversely is a low level KEYIN appears on the MPU data bus in bit position PDO when the MPU activates RDST the read status decode This is in response to an input operation addressed to the keyboard or CRTC Note that the MPU determines if the dis play scan is in the vertical blanking period by examing the state of the RETRACE signal which appears as PDl 3 41 BFISD 8070 1N0AJX 21 01 TI E80 8070 42 Keyboard Matrix Code Transmission Figure 3 18 3 42 BFISD 8070 3 6 11 Counter Timer Circuit CTC The CTC 5C is shown on Logic Diagram Sheet 4 The CTC is a four channel counter timer programmed by the MPU to provide the baud rate clock for the two serial I O ports in the DART paragraph 3 6 12 and the clock train that drives the Bell latch 5L The CTC has four independent counter timer channels 0 1 2 and 3 Each channel is individually programmed by two bytes a control byte and a time constant byte The control byte selects the operating mode counter or timer enables or disables the channel interrupt and selects certain other operating parameters If timer mode is selected the control byte also sets a prescaler which divides the clock input ZC
106. es The machine type operations executed by the EVDT carriage return backspace horizontal tab etc are controlled by ASCII control codes The control codes may originate at the host CPU or at the EVDT keyboard 11 of the 32 standard control codes may be generated at the keyboard but only those control codes highlighted in figure 2 19 and listed in table 2 4 are recognized by the EVDT as operational control codes Non operational control codes when generated are displayed as reversed video characters Operational control codes are not displayable unless preceded by an ESCAPE character or unless the Enter Mode is set paragraph 2 10 6 Whenever a control code is displayed it will not be acted upon by the EVDT BFISD 8070 MN CONTROL CHARACTERS DISPLAYABLE CHARACTERS pem SKIP HT t j lt _ Krus EVDT CONTROL CODES USE CTRL KEY WITH DISPLAY ABLE CHARACTER KEYS TO PRODUCE EVDT CONTROL CODES 8070 21 Figure 2 19 Displayable Character Set Standard Domestic and EVDT Control Codes BFISD 8070 Table 2 4 Operational Control Codes CONTROL CODES HEX FROM KEYBOARD FROM HOST CODE OPERATION G BEL BEEP Generates audible tone CTRL Back Space Moves cursor left to next un protected position on same line or on previous line moving from right to left Horizontal Tab Skips cursor to next tab set position when Protect Mode is set If no such position
107. eset or power off power on sequence Personality change codes are entered from the keyboard in Block Mode or host CPU by the sequence ESC Control Code from figure 2 21 Selected ASCII Replacement Character For example a sequence of Pss would replace the ERASE CLEAR replacement character SPACE or hex 20 with an asterisk When the personality change is verified by entering all 1920 positions in the display matrix would be filled with asterisks Another example of a personality change sequence would be A era 2 This would add the character to the standard EVDT escape lead in character The EVDT would then respond to either escape character During Send All transmisssions however the character would be sent instead of ESC A final example of a personality change sequence is ESCAPE CLEAR J CTRL o o This would change the standard SOH function lead in character to NUL 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 0D 00 00 00 00 01 00 20 OA GA 00 OO OO 00 00 L PERSONALITY DEFINITION Escape Lead In Character End of Block Character 2nd End of Block Character End of Line Character 2nd End of Line Character Field Delimiter Character Function Lead In Character Parity Error Replacement Character trase Clear Replacement Character RTS ON Delay RTS OFF Delay Polling Addressing Control Transmission Number Limit Reserved BerroxwTOonmooare CODES 0 THROUGH 6 AND 8 AR
108. eter changes while retaining all screen data The single line SETUP menu temporarily displaces the first line of screen data which returns when the Setup Mode is terminated The cursor will also return to the same screen position that it occupied before the single line SETUP menu was invoked BFISD 8070 KEYBOARD PROTECT LOCK MODE STATUS CAP PAD BLOCK LINE LOCK MODE p Pd KI Pr BFIS 4309 Fz Sf C Bk SETUP 1 PORT A BAUDM 8 DATAM 2 STOPM PARITYH EVEN PE 2 PORT BAUDM 8 DATAM 2 STOPMH PARITY EVEN BAUD 0 50 1 75 2 110 3 134 5 4 150 5 300 6 600 7 1200 BAUD 8 1800 29 2000 A 2400 B 3600 C 4800 D 7200 E 9600 F 19200 SECURITY 50 Hz E PORTEM XONOFFM DRT ROLLS SCROLL SMOOTHM 24HREN STATE BELLS REPEATM TACTILEM CURSORMB LANGUAGES Language O standard 1 French 2 Italian 3 Swedish 4 Spanish 5 Norwegian 6 German 7 Danish BFIS 4309 VXXXX C MAI INC FIRMWARE REVISION LEVEL Figure 2 9 Full Screen Setup Menu and Status Line BFISD 8070 To invoke the Setup Mode press and hold the FUNCTION key and press the numeric keypad zero 0 key This operation will display the prompt SETUP Menu Select To view the single line SETUP menu a line at a time press the numeric key 1 thru 5 corresponding with the line of the menu to be displayed The selected line will then appear To view the full screen SETUP menu press the zero key again either on the main keyboard or the numeric keyp
109. f Xonoff is not activated Xonoff is activated and a CONTROL S signals the computer to halt transmission when the terminal buffer is 32 characters short of being full A CONTROL Q signals the host computer to resume transmission when the character buffer is at least half empty Data Terminal Ready feature is not activated Data Terminal Ready feature is activated and will respond by dropping the Data Terminal Ready signal indicating to the host computer that the terminal input buffer is 32 characters from being full This feature complements the Xonoff by providing an alternative to sending CONTROL S and receiving CONTROL Q for input buffer control If both Xonoff and Dtr features are selected a CONTROL S code will automatically be sent prior to dropping the Data Terminal Ready signal Indicates default setting of setup parameters invokable by Keyboard Master Reset 2 13 BFISD 8070 Table 2 2 PARAMETERS Scroll Smooth Setup Menu Parameters and Selection Codes continued SELECTION CODE DESCRIPTION Cursor will not wrap around to the next line Cursor advances to first column of the next line when cursor is advanced from the last column on the right All lines do not move up when the bottom line is filled to the 80th position Additonal data will continue to be written on the bottom line All lines move up when the bottom line is filled to the 80th position Regular Line Scrolling a single line
110. figure 3 21 is that of scanning the keyboard matrix for a pressed key and also checking to determine if a character has been received from a communications port Other tasks control the display memory tracking the cursor position and screen refreshing START PROCESS KEY PROCESS CHARACTER 8070 45 Figure 3 21 Simplified Firmware Flowchart 3 50 BFISD 8070 SECTION IV MAINTENANCE 4 1 INTRODUCTION This section contains informatin that will aid the service representative in maintaining and troubleshooting the Model 4309 EVDT The information is pre sented in two parts and contains general procedures for e Preventive Maintenance e Trouble Analysis 4 2 PREVENTIVE MAINTENANCE The EVDT should be cleaned each time service is performed Clean the exterior housing and lightly dust the EVDT using a soft brush or damp lint free cloth Remove smudges from the exterior housing with conventional spray cleaners Use only a lint free cloth to clean the CRT screen using care not to scratch it As part of System Preventive Maintenance the EVDT should be opened and cleaned using a soft brush to remove dust build up The three DC voltages should be checked to verify proper operation of the Power Supply PCBA The intensity and centering of the display should also be checked and the Monitor Board PCBA ad justed as required WARNING Turn off the EVDT power switch and remove the power cord from the AC outlet before
111. flops Buffer 10C is loaded from the MPU data bus when the I O address decode LINELD is activated This correctly implies that the screen refresh starting address can be controlled by the MPU and that refreshing can occur from any physical loca tion in screen memory and not necessarily from the first character position Similarly buffer 11D is parallel loaded from the data bus when the I O decode LSCND is activated The information in buffers 10C and 11D is transferred to buffer 15C from 10C and to one half of 11 and counter 11C from 11D coincient with the end of the last or bottom line of the character row This synchronization is derived from the output of gate 4B pin 13 occurring when a carry output is generated by counter 11C which in effect counts the horizontal lines in a character row It also occurs at the end of the VSYNC period to denote the first character row of a new frame Note that when so enabled by the MPU LINTEN 1 the foregoing conditions generate a non maskable interrupt NMI 0 The interrupt service routine initiates the loading of the buffer registers Counter 11C is clocked by ROWCK which is derived from the Xor output 26 11 ROWCK is coincident with ROWLD but is not generated during the vertical fly back period as signified when VSYNC is low When VSYNC is high ROWLD is gated through Xor gate 2G as ROWCK Note that ROWCK is not the same as ROWCLK 3 29 BFISD 8070 3 6 8 Character Generation The
112. he SHIFT key the MPU reads the corresponding character code from the look up table and writes that code into its screen memory The subtlety of keeping track of the cursor is a function of the firm ware by having the MPU interrogate the CRT controller 3 4 7 Communication Interface The communications interface consists of a Dual Asynchronous Receiver Trans mitter DART and two Input Output ports The DART is programmed from the MPU which determines line protocol character format number of stop bits and whether or not a parity bit is used and if so whether odd or even parity is enabled One of the ports can be transmitting while the other is receiving One of the I O ports is usually connected via a communications line to a host computer The other port is usually connected to an output device such as a printer which can provide hard copy of displayed data However the second port may be connected to any device which interfaces to a communications line The DART receives data from each line serially It assembles a character and interrupts the MPU to signify that a character is available The MPU in turn relieves the DART of the character which is then free to receive a subsequent character The DART verifies the received character according to the format in use and logs any errors in a status register which is accessible by the MPU The MPU verifies that reception is error free before processing the character If errors are detect
113. hich is normally blank an all zeros dot matrix code By inverting an all zeros code to an all ones code a line would appear This is the function of the first Xor gate 2G The output of Nand gate 9F will be low during the scan of line 12 for the period ULINE is high as controlled by the MPU from informa tion received from the keyboard or the host The output of Nand gate 4J 8 will then appear at 2G 3 remembering that 4J 8 is the inverse of VIDOUT which is the inverse of the parallel to serial converter If underlining is disabled the Nand gate output 4J 8 appears inverted at 2G 3 The second of the Xor gate 2G is the reverse video control gate An Xor gate can provide two functions first as a non equivalence comparator inverter and second as a simple gate Consider the truth table for a 2 input Xor gate If reverse video is specified REVID 1 the output of buffer 11J pin 2 is high 2G 4 so that whatever appears at 2G 5 is effectively inverted at 26 6 If REVID 0 the output 2G 6 follows the input 2G 5 i e there is no inver sion remembering that the output of Nand gate 4J 8 represents the output of the parallel to serial converter of the true state of the dot matrix code The last gate in the video control circuits is the third Nand gate 4J dis counting inverter 3G which is either enabled or disabled by the BLANK attri bute bit If BLANK is high the output of buffer 11J pin 19 is held and is inverted to disable Nand gat
114. htness cannot be adjusted from keyboard or host I Display wavers in Reverse video Printer does not receive data pro perly Baud rate incorrect l Set baud rate Setup Menu 2 Replace character ROM 2 Defective character ROM 3 Defective modem Defective logic board 3 Replace modem Replace Main Logic board One key stuck down Release key Check for free operation Replace if necessary 2 Reposition magnet and glue in position as necessary 2 Magnet on one key slipped down As an aid to identifying the faulty key perform either a 1 power on reset ESCAPE Z command or 2 FUNCTION and CLEAR The char acter then being displayed corresponds to the stuck key Monitor board in l Adjust as necessary correctly adjusted Monitor board in l Adjust as necessary correctly adjusted l Replace Main Logic Board 741 Op Amp or D A Con verter Defective logic Power supply 12Vdc Adjust or replace power defective supply Monitor board 2 Adjust or replace Monitor board 3 Replace logic board 4 Set 50Hz software switch to 0 in SetUp Menu 3 Main Logic board 4 50Hz selected in Set Up Menu l Set correct baud rate on SetUp Menu 2 Set Extension Port to l on SetUp Menu 3 Connect cable 4 Replace with RS 232C cable Incorrect
115. iodically as determined by the MPU so that displayed information appears to be steady The address multiplexer is controlled to select either the screen memory address generated by the MPU or the refresh address from the address generator The CRT controller is pre programmed by the MPU according to the display format and the chacter format and it determines the generation of horizontal and ver tical sync pulses Note that the MPU has access to the address generator via the data bus this allows the MPU to load the address generator with a binary number corresponding to any character position in the display matrix screen memory address 3 5 BFISD 8070 3 4 4 Character Generation The character generators generator l and generator 2 provide the character code that is displayed on the screen Each generator consists of a 2K ROM which functions as a reference table The ROMs store all the character codes in the character repertoire in all of the possible dimensions from single height single width to double height double width A particular location in ROM is addressed in part by the coded data read from screen memory The remaining location data is from information generated by the character control logic The character control logic is itself controlled by the MPU and determines character dimension and brightness The character code 8 bits is read from one of the character generators in parallel and then converted to serial data a
116. ited operational capability in the EVDT in that only some of the functions are used Unused functions are not discussed in the following paragraphs 3 23 BFISD 8070 Table 3 2 CRT Controller Pin Outs PIN SIGNAL DESCRIP TION FUNCTION GND Ground RESET Active low input used to initialize all internal scan counter circuits When RESET is low all internal counters are stopped and cleared all scan and video outputs go to the low state control registers are un affected All scan timing is initiated when RESET goes high RESET can be used to synchronize display frame timing with line frequency c PSTB Light Pen Strobe not used 17 MA0 MA13 Memory Address Lines not used 18 DISP Display Enable Active high output used to indicate when the controller is generating active display information The number of horizontal displayed characters and the number of vertical displayed characters is programmable and are used to generate the DISPLAY signal 9 CURSOR Cursor Position not used Vec 45V input CLK Timing Clock Used as the time base for all internal count control functions 22 R W Read Write Control Derived from Al address bus when CRTE is low When this bit is logic one the requested information is placed on the MPU data bus by the controller in the execution of a read operation When this bit is logic zero the information on the MPU data bus is written into the selected internal register En
117. length stop bits parity baud rate duplex data buffer X ON X OFF protocol refresh rate extension port status line keyboard security scroll mode cursor mode auto repeat linefeed with carriage return tactile feedback end of line bell language and clock select All selected parameters stored in con tinuous memory CMOS RAM Self Test Mode Invoked at keyboard only CONTROL key with standard keys cause individual tests to be executed for ROM checksum MPU scratchpad RAM screen RAM LSI registers and audible tone ROM and RAM tests are also executed at power up BFISD 8070 1 4 RELATED DOCUMENTS The following manuals are recommended as supplementary reference material for field service personnel Ergonomic Video Display Terminal Operator s Guide BFISD 5161 System 810 Service Manual BFISD 8058P System 810 Operator s Guide BFISD 5115 Model 1350 Fixed Media Disk CPU Service Manual BFISD 8065PA supporting Systems 110 210 and 310 with High Speed CPU System 110 Operator s Guide BFISD 5160 System 200 410 Service Manual BFISD 8035A System 200 410 Operator s Guide BFISD 5045 System 210 Operator s Guide BFISD 5109 System 310 Operator s Guide BFISD 5135 2 3 1 BFISD 8070 AC Power Requirements Verify the following AC line requirements 1 The AC line is not shared by devices that cause large transients e g air conditioners heaters welding equipment or equipment with large motors The
118. lown fuse Defective firmware Defective logic Brightness turned off Incorrect adjustment Defective power supply 12V Defective monitor board Cursor is blanked Status line dis abled Defective logic Keyboard connector not plugged into display unit Defective keyboard Magnet on key plunger fallen off Incorrect or defective firmware EPROM s Incorrect or defective ROM s in character generator Foreign objects under key caps Defective logic board Terminal not in Block Mode If in conversation mode problem with host computer l Check for power at out let Replace Replace Replace fuse s firmware EPROM s Main Logic board Adjust brightness Perform ments Replace Replace Perform Perform Replace Connect Replace Install Replace Replace video adjust power supply Monitor board Master Reset Master Reset Main Logic board keyboard keyboard magnet firmware EPROM s character ROM s Remove objects Replace Main Logic board Put terminal in Block Mode Replace Main Logic board BFISD 8070 Table 4 1 EVDT Troubleshooting Guide continued POSSIBLE CAUSE CORRECTIVE ACTION SYMPTOM D Incorrect char acters displayed E Keyboard character or function con stantly repeats F CRT has incorrect vertical position and or linearity G CRT has incorrect horizontal position and or linearity H Screen brig
119. lumn The latch output is a level whch is monitored by the MPU by means of the Read Status decode RD ST If there is a change in the level the MPU knows which key has been pressed because of the matrix code The sequence of events is as follows The MPU sends the matrix code to the keyboard by means of the keyboard function and monitors the response If the level denotes that the addressed key was pressed the MPU sends the same matrix code again but turns on the hysteresis bit If the same response in level occurs from the output latch the MPU is notified that a key was in fact pressed and that the response was not just a glitch The MPU goes to a character look up table and reads the character code corresponding to the matrix code and places the character code in display mem ory at the cursor address If a control function is invoked the MPU branches to the appropriate service routine BFISD 8070 49019 H21v1 300930 NWn109 380415 ZI EN 8 L 9 S t l H3WI1 9NI32012 U31SI93H 14dIHS 3009 XI LVW Matrix Code Demodulation Timing Figure 3 20 3 49 BFISD 8070 3 6 14 System Firmware The operating system firmware consists of a relatively small but sophisti cated multi tasking operating system The firmware is modularized for example PROM O and PROM 1 contain the firmware controlling the EVDT hardware Other PROMs contain the terminal emulating firmware The most basic task
120. menu press ESCAPE twice to terminate the full screen SETUP menu press ESCAPE once The procedure for invoking the Setup Mode and for selecting and or changing EVDT parameters is summarized in table 2 3 Procedures for programming the status line clock establishing protected fields function key programming and selecting display attributes are provided in paragraph 2 10 NOTE The maximum recommended baud rates vs cable length are Oto 250 feet 9600 baud 251 to 500 feet 4800 baud 501 to 1000 feet 2400 baud BFISD 8070 Table 2 2 Setup Menu Parameters and Selection Codes PARAMETERS SELECTION CODE DESCRIPTION Port A baud rate selected from SETUP menu E Port B baud rate selected from SETUP menu A Seven bit word length for I O port Eight bit word length for I O port One stop bit on data word for 1 0 port Two stop bit on data word for 1 0 port No parity on data word for I O port Parity bit on data word for 1 0 port If parity is invoked it will be odd parity If parity is invoked it will be even parity Security Escape sequences uninhibited Selected Escape sequences inhibited Half D Full Duplex Half Duplex 50 Hz 60 Hz for U S operation 50 Hz for foreign operation E Port Extension Port is not activated Extension Port is activated and will pass data from Port A at the selected baud rate to a device connected to Port B such as a serial printer Xonof
121. more function keys and linked together in continuous memory as a single string The stored character string commands may include in addition to user BASIC commands con trol codes and escape sequences for unique program applications 2 41 BFISD 8070 The Special Function Keys amp SET F and L EXAM F are used to store and examine the character strings entered for each Programmable Function Key Program the function keys as follows l Place EVDT in Block Mode FUNC 2 Locate cursor in first column of any line 3 Enter number of function key to be programmed 01 to 28 4 Enter desired character string to be stored 77 characters maximum Control codes may be entered by executing ESCAPE CLEAR CTRL ASCII Escape sequences may be entered by executing ESCAPE CLEAR ESCAPE CLEAR 5 Verify that cursor is one position to right of last character entered 6 Enter FUNC A SET F to store character string ESC k from host CPU 7 If the stored character string is to be linked with a continuation of that string in the next or another function key or a set of com mands are to be linked in sequence enter ESCAPE CLEAR ESCAPE CLEAR N and the number of the function key to which the character string stored in step 6 will be linked 8 Store the continuation of the character string or the next command in the linked set by repeating steps 4 5 and 6 9 Enter FUNC F ES
122. movable EVDT Port A 4 Conductor Cable Terminal I O Panel Con Disk CPU Interface 1 000 Ft Max nector Channel System 510 906694 VAR O thru Channel 7 610 710 or See Note 50 Hz 730 906274 VAR 60 Hz All Systems EVDT Port B 4 Conductor Cable Terminal Serial Printer Interface 1 000 Ft Max 1 0 Port Connector 906694 VAR See Note 50 Hz 906274 VAR 60 Hz NOTE Baud rate constraints apply at longer cable lengths Refer to Setup Mode instructions paragraph 2 7 BFISD 8070 JUMPER CONNECTION FOR 110 120VAC INPUT A 110 120VAC CONNECTION JUMPER CONNECTION FOR 220 240VAC INPUT 220 240VAC CONNECTION Figure 2 2 AC Input Voltage Configurations Power Supply PCBA BFISD 8070 2 5 EVDT INSTALLATION Install the EVDT as follows l Place the pedestal for the video display assembly on the surface of the designated EVDT work station NOTE The area chosen for EVDT operation should not contain equipment that radiates RFI radio frequency interference or strong magnetic fields as these conditions may interfere with EVDT per formance 2 Set the video display assembly atop the pedestal 3 Place the keyboard in front of the display assembly and plug the coiled keyboard cable into the receptacle located below the right side of the display screen see figure 2 3 CAUTION Be sure to perform the preinstallation checks in paragraph 2 3 before connecting the EVDT to an
123. n the down counter is returned to the MPU time remaining to zero BFISD 8070 The significane of the control bytes is as follows D7 Interrupt 1 enable interrupt 0 disable interrupt D6 Mode 1 counter O timer D5 Prescaler 1 256 0 16 timer mode only D4 CLK edge 1 rising edge 0 falling edge D3 Timer Trigger 1 trigger when time constant loaded I O trigger from CLK pulse D2 Time Constant 1 time constant follows control byte no time constant DI Reset continued operation 1 reset by MPU DO Control Vector O vector value 1 control byte Channel 0 is controlled as a counter counting CKCTC clocks It counts down to zero and ACO provides the baud rate clock to the first I O port in the DART Channel 1 is likewise controlled to count down CKCTC clocks its output ZCl provides the baud rate clock to the second I O port in the DART Channel 2 is controlled as a timer that is automatically triggered when the time con stant is loaded Its output provides the clock trigger to the Bev taken 5L Channel 3 is used for internal control timing 3 6 12 Dual Asynchronous Receiver Transmitter DART The DART contains two fully independent serial communications controllers operating in half or full duplex mode Each channel A or B contains six write registers that control operating parameters for the channel and three read registers that provide status information for the channel Each channel is pr
124. nable is tied to digital ground so that the outputs are permanently enabled The five bit address is made up from PMREQ and the four most significant bits from the MPU address bus If PMREQ is low program memory is selected accordingly PMSEL will be low Program Memory Select and one of the associated four select signals MSEL3 MSEL4 MSEL1 MSELO will also be low If PMREQ is high then a memory segment other than program memory is selected as follows XMSEL Extra Memory optional data memory SMSEL Screen Memory DMSEL Data Memory Note that the high order 4 bits of the MPU address specify memory when PMREQ is low and the low order 8 bits specify an I O device when PIORQ is low An I O address cannot be specified in the high order 8 bits of the MPU address bus 3 14 BFISD 8070 3 6 2 2 I O Address Decode A valid I O address appears on the low order half of the address bus PA7 PAO when PIORQ is low PIORQ and are both low when the MPU acknowledges and interrupt so to distinguish between an I O operation and an interrupt acknow ledge PMI must be high when PIORQ is low to signify an I O operation The 1 0 decode logic is shown on Logic Diagram Sheet 3 It consists essential ly of the 256 bit ROM device 13D As shown the output enable of the ROM pin 15 is tied to digital ground such that the outputs are permanently enabled Only five of the data outputs are used and not all of the 32 eight bit loc
125. nd fed into the composite video circuit Other inputs to the composite video circuit are derived from the display attribute logic and the character control logic The display attribute logic determines the manner in which each character is displayed as determined by the attribute segment of screen memory The character contorl logic converts a binary number digital into an analog voltage D A coversion and uses the analog voltage to control amplification of the video signal brightness in the composite video circuit 3 4 5 CRT Controller The CRT controller provides the control interface between the MPU and the CRT display The CRT controller generates the vertical sync and horizontal sync pulses Time positioning of both sync pulses and the respective pulse widths are controlled programmable by the MPU The cursor signal also generated by the controller is used to indicate when the scan coincides with the cursor position The DISPLAY signal display enable is used to indicate when the controller is generating active display information and is synchronized by the control logic to signify the beginning of a character row The DISPLAY signal is inactive during horizontal and vertical flyback periods The screen memory refresh test address is generated by the CRT controller the start address is programmable and the end address is determined by the size of the display matrix i e the number of characters in a row and the number of ro
126. ne following first FS code or at first unprotected character following HOME CR is transmitted at end of message and cursor is returned to position where ESC S was entered ESCAPE CLEAR s BFISD 8070 Table 2 8 Print Transmission Control Operations FROM OPERATION FROM KEYBOARD HOST i i 1 FUNC ESC ESC ESC A Print Line Un protected Print Page Formatted Print Page All Print Page Unprotected ESCAPE CLEAR p Print Page Unformatted Disabled by host only Display Bypass Print 2 34 DE DESCRIPTION Sends line of unprotected data followed by a car riage return CR char acter to serial printer Transmission starts at beginning of line and ends at cursor postion Sends all data on screen line for line to serial printer Transmission starts at HOME position and ends at cursor posi tion If initiated by host ESC P seven byte status message is return ed to host following print operation Send all unprotected data on screen to serial printer Transmission starts at HOME position and ends at cursor posi tion Protected data is sent as spaces Send all data on screen including nulls with no carriage returns or line feeds to serial printer Transmission starts at HOME position and ends at cursor position All characters received from host CPU are passed on to serial printer and ar
127. nking or steady or in reverse video dark on a light background instead of the normal light character on a dark background Each character appears as a contiguous dot pattern called the character matrix The actual character matrix is 8 X 12 dot positions and the normal character size is 6 X 10 dots as shown in figure 3 2 Each character dot is assigned a row and column position in the matrix or character raster Genera tion of the character matrix or raster is controlled by the character gener tor The two unused rows and columns in the matrix provide line spacing and character spacing respectively Figure 3 2 represents the display of an upper case H The MPU synchronizes the vertical sync pulse or retrace period 6 COLUMNS Aka ad di 10 ROWS 12 ROWS d dh dh da A A A A A A A A A 4 8 COLUMNS Figure 3 2 Character Matrix BFISD 8070 3 3 BLOCK DIAGRAMS Section III contains two block diagrams figures 3 3 and 3 4 which depict the Main Logic Board and the keyboard respectively in terms of the principal logic elements and circuits Figure 3 3 shows the MPU with its address and data bus the main memory screen memory CRT controller character generators and character control logic com munications interface and keyboard interface For the sake of clarity cer tain logic circuits are not shown in figure 3 3 These include the clock gen erator and clock signals memory and I O add
128. o e 5715 5 5 Power Supply PCBA sese eooo oo o e 5720 5 6 Keyboard ae amp o o 5724 6 1 Logic Diagram Keyboard PCBA o s p 6 3 6 2 Logic Diagram Main Logic Board PCBA oo 6 5 6 3 Schematic Diagram Monitor Board PCBA 6 29 6 4 Input Output Diagram Power Supply PCBA e e 6 31 vii BFISD 8070 LIST OF TABLES Table i Page 1 1 Specifications Model 4309 EVDT a 1 6 2 1 Systems Interface Cables and Connections e 2 4 2 2 Setup Menu Parameters and Selection Codes 2 13 2 3 EVDT Setup Procedures e s a a a a oo 2 15 2 4 Operational Control Codes e lt au lt a a a e 2 27 2 5 Summary of Special Function Key Operating Mode Selection e w w w w w a w e s e w a a o 2 30 Data Editing Control Operations e e a gt 2 31 Data Transmission Control Operations e e 2 33 Print Transmission Control Operations e 2 34 Business Graphics Characters e lt on 2 36 Clock Set Command Codes wn ASCII Code Conversion Clock Dido lay eo y s nan 2538 Display Attribute Assignment Codes 2 39 Display Attribute Selection Codes e w a a 2 40 Character Size Attributes s a a a 2 40 Row Select and Cursor Positioning Codes 2 44 MPU Pin Outs 4 a a a
129. o the character to be formed The data is stored in the character generator as depicted in figure 3 12 example B The line scan number remains the same for one complete horizontal line scan The data information changes for each character position as determined by the information supplied from screen memory 3 30 BFISD 8070 8 COLUMNS 0 1 2 3 4 5 6 7 12 SCAN LINES W gt O o GO 0c BW N DISPLAY MATRIX UPPER CASE L 00000000 01000000 01000000 01000000 01000000 01000000 01000000 01000000 01111110 00000000 CHARACTER ROM UPPER CASE L Figure 3 12 Character Generation 3 31 BFISD 8070 3 6 8 1 Character Generators The character generators 10G Font 0 and 8G Font l are 2K X 8 ROMs The ROMs store the character information on a line basis Font provides all the standard letters upper and lower case the ten numerical digits punctuation marks and symbols while Font 1 provides foreign language letters and symbols as well as special graphic symbols The address inputs to each ROM are derived from the outputs of the line scan counter CAO CA3 and from the outputs of the screen data buffer SDO SD6 Note that seven data bits are used corresponding to 7 bit ASCII character code The ROMs outputs are permanently enabled since the OE pin is tied to digital ground One or other of the ROMs is selected according to the logic state of Font l as follows 0 Font 1 select Font
130. of RD from the MPU If RD is high a read operation takes place and conversely a write operation takes place BFISD 8070 ce AUU L wi A m a Oo nOo i 9J 5 9J 9 _ 8070 30 Figure 3 6 Dynamic RAM Row Column Address Sequence AO A6 select the row and A7 A13 selection the column The timing sequence is determined by two D type flip flops 9J and the row and column addresses are selected by multiplexers 5B and 8B The timing is shown in figure 3 6 which depicts normal access timing PRFSH is assumed to be high Prior to selection of Optional Data Memory XMSEL is high and its inverse holds both flip flops in the clear state reset When XMSEL goes low the first flip flop is primed for the set state which occurs at the leading edge of the next CKCPU clock as shown The second flip flop clocked set at the leading edge of the next CKCPU2 clock When XMSEL goes high its inverse clears both flip flops and they are held in that state until XMSEL goes low again When the first flip flop is in the reset state the A inputs to multiplexers 5B and 8B appear as A0 A6 the address inputs to data memory When XMSEL goes low RAS goes low and A0 A6 represent the row address When the first flip flop is clocked set the B inputs to the multiplexers appear as A0 A6 to be come the column address when the second flip flop is clocked set and CAS is activated As stated both flip flops are cleare
131. of the addressed location are placed on the direct data inputs to the MPU D7 DO and not PD7 PDO The Write Enable WE input is derived from the MPU Write output PWR When PWR is low Write the data appearing on the direct outputs from the MPU is written into the addressed location The memory device is a 4K X 8 RAM with provision for future design to accommo date an 8K X 8 RAM 3 62323 Optional Data Memory Optional Data memory when installed provides for the storage of up to 16K bytes of information Information from the host may be temporarily stored and then transferred to the display screen or information may be transferred into data memory from screen memory then transferred to the host or a hardcopy de vice printer This memory consists of eight 16K X 1 dynamic RAMS configured as 16K X 8 The RAMS are connected in parallel so that the same single bit cell in each RAM is addressed simultaneously The Data Input DI and Data Output DO are wire ORed together and tied into the MPU data bus PD7 PDO To address 16K locations fourteen address bits are required as specified by PAO PA13 from the address bus BANKO and BANKI are for future expansion of data memory to 64K RAM location is selected by first selecting 7 bit row address then by selecting a bit column address The determination to read from or write into the addressed location is made by the Write Enable WE in put which is derived from RD the inverse
132. ogrammed with set up parameters by the MPU and each channel has the capability of activating a MPU interrupt for service during the execution of an operation according to information in the status registers A block diagram of the DART is given in figure 3 19 and a pin out description is pro vided in table 3 3 The Write Registers contain control information for asynchronous operation and permit selection of 5 6 7 or 8 data bits one one and one half or two stop bits whether or not a parity bit is to be included and if so whether even or odd parity is to be used The Write Registers also contain control information specifying when and under what conditions an interrupt is to be generated usually when the transmit buffer is emptied during transmission and when a received character has been assembled and is available One of the Write Registers contains the interrupt vector address The Read Registers contain status information from which the MPU can determine if transmission or recep tion was successful and if not the nature of the problen e g parity error transmitter underrun receiver overrun framing error etc 3 44 BFISD 8070 AQV3U LIVM SAJOTJ TINNVHO Vivd IVIYIS alu ST10YLNOJ AJHLO YO WIGON VIY 51081402 u3H10 YO WIGON AQVIU LIVM SAJOTI TANNVHO Ylva TVI33S 8 TINNVHO 501015 ONY TOULNOD 31349514 8 TANNVHO 501015 ANY 109109 3139951 V 13NNVHO V T3NNVH9 AJISIIIA 31IuM Qv3
133. on s a a e e a on Microprocessor Unit e e lt lt w e vw gt gt 3 10 Memory and I O Address Decode e oo 3 14 1 Memory Address Decode e au s oo 3 14 2 1 0 Address Decode e e w wo os 3 15 Main Memory s s ska os a oe Ba del 1 Program Memory e s o w e we ooo o o o 3 17 2 Data e Wee an e o o o 3 17 3 Optional Data Memory e a lt a oo e 3 17 System Clock Generation e e w s s w e e 3 19 ON ON Ul Ul Co Co CO i e e a ON ON ON ON ON O ON O ON ON O ON ON ON ON ON Q RF F E F G ka e e o ON Q WD I e e FP CO CO CO P2 S CO UO CO Co CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO OO CO CO CO CO CO CO CO CO 6 5 Screen we o o 3 20 6 5 1 Control Logic lt woo cw wu 3722 6 5 2 Arbitration Logic e e e e e e e e 3 22 6 6 CRT Controller lt lt o e e e s ue 3 23 6 6 1 CRTC Internal Registers w s 3 25 6 6 2 Vertical and Horizontal Timing e e e 3 27 6 7 Refresh Address Generation e e e w w 3 29 6 8 Character Generation e e e e
134. only be read from ROM whereas information can both be written into and read from RAM and can therefore be changed as is the case with screen memory Any logic device on the data bus other than main memory or display memory is addressed as an Input Output 1 0 device 3 4 3 Screen Memory Screen memory as described in paragraph 3 2 and as shown in figure 3 3 con sists of two segments Each segment comprises IK of display information and 1K of attribute information for a total of 2048 storage locations The screen memory consists of RAM elements and therefore can be written into and read from Screen memory is the storage for character codes that eventually are generated into the characters which appear on the screen The MPU receives character coded data from either the communications interface or the keyboard and writes the data into screen memory From screen memory the data is displayed on the screen The coded data remains in screen memory until it is overwritten by new or fresh data or it may be transferred to the data segment of main memory Once the information has been displayed on the screen that same information must continue to be displayed until it is altered or is performed automatically by screen memory The address generator generates a series of screen memory addresses in sequence reading the information character code and attribute and effectively displaying it from position 0 to position 1919 Refreshing occurs per
135. otected or protected characters partial send using Function keys or Escape sequences BFISD 8070 SECTION II INSTALLATION AND OPERATION 2 1 INTRODUCTION This section provides information on the installation and operation of the Model 4309 EVDT The use of the Special Function Escape and Control keys is described in detail as reference for field service and programming personnel 2 2 UNPACKING INSPECTION REPACKING The EVDT is shipped in one carton which contains the video display assembly keyboard keyboard cable power cord and Operator s Guide The shipping car ton is constructed of heavy cardboard and includes specially constructed foam mounting to protect the EVDT from damage The following procedure is recom mended when unpacking the EVDT l Before accepting the EVDT from the carrier inspect the shipping carton for signs of external damage Any indication of external damage must be noted by the carrier and reported immediately to your Basic Four sales office NOTE When unpacking the EVDT save all packing materials and the shipping carton for use at a later date 2 With the shipping carton in its upright position open the carton and carefully remove the EVDT components as shown in figure 2 1 3 Carefully unwrap and inspect all items for indications of shipping damage Check for loose bent broken or otherwise damaged parts Immediately report any damage to your Basic Four sales office 4 When returning
136. p before removing any subassemblies Rear Housing Removal Disconnect the keyboard connector from the front of the video display assembly Move the keyboard out of the immediate work area Dis connect the power cord connector from the video display assembly Place the video display assembly face down on a clean flat surface preferably covered by a soft cloth or clean plastic sheet Use a Phillips screwdriver and loosen but do not remove the four 4 screws securing the rear housing to the frame of the video display assembly Lift the rear housing up and off the display assembly Carefully place the video display assembly in an upright position Discharge the CRT anode 5 1 BFISD 8070 5 2 2 Keyboard Housing Removal l Switch off power at the video display assembly Remove the keyboard connector from the front of the display assembly 2 Turn the keyboard over and remove four 4 screws that secure the housing to the base 3 Remove the housing NOTE Some keyboards have the keyboard assembly mounted on the base with captive nuts protruding through the base 5 3 REMOVAL REPLACEMENT PROCEDURES The following procedures provide detailed instructions for removal and replace ment of the modular subassemblies including the CRT 5 3 1 CRT Safety Precautions 1 ALWAYS discharge the CRT anode to ground before working inside the display unit 2 ALWAYS wear approved safety glasses 3 NEVER handle the CRT roughly a
137. pr d SBROD SMCY an cg SDLCK pes NC e 124 2 r1 av 41 99 7405213 74 07 uc TD ADS 4 15 BLANK LI amp Q zo SEHH 252 4 40 ADI san ID a ZL S ADS iD Q oc c 9L TALS 541 Ld Gi Bd at 8070 66 6 19 20 BFISD 8070 7405 9 PO ia SAN e j B A E POS a Q 68 224 an sa E PDS HH 44 4 E een pou 2 PDI 1 LLL 26 za POD LLLLI iQ IQ esr Ev pe BY AP NE E 46 p eter re e ae ee 3 l DOTCLK 3E ny gie vipeur lees 476 74574 EE I Suse 8 7915 28 an N tot LECMD LINTEN 2 at 74 814 4 500 FONT 9 BY i le 5 ze OE Vee 224 2 se 79 5278 sas ENIE Ko Z732 2732 o 212 Gin pe EQ P oe o ou SAN uMPe E lan i L Blan 42 la TIA GA L 1 20 NE m 5v ane zt 7 ap AIBICOUNT cz pe AP oew pia bis soa eaha lab ao 24 eise aux b 202 lla ps 5 lt CHROLK EDI 3 je po 3 SDE pe ail ck GAZ i I ae ZA 2142 I EA CA Ila i 8l i THCS278 Blan WE i 25 LI a aM u umur au i nan Zap ac S 8 oW c ec qM En e 0277
138. r output to appear as DOTCLK the inverse of Dot Clock Multi plexer 8J selects SMCYC which is inverted to provide CHRCLK Character Clock and also selects CKD3 and CKD2 The output of Nand gate 9F generates CHRLD Character Load which is effectively the inverse of every fourth CKCPU2 clock and occurs once during every eighth dot clock period Other principal timing sequences are discussed when the associated logic operation is describ ed osc DOTCLK cxceuz cxD2 LE LE LE U U LS LILI LS LILI US LU LU LILI cxepu cko3 L J LJ LT LT l F LJ L f l T l T L nn UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUL Re fe Qurpe Hp Hp Figure 3 7 Clock Timing Dot Clock Timing Clock and Character Load 3 19 BFISD 8070 3 6 5 Screen Memory Screen Memory is shown on Logic Diagram Sheet 7 and is shown in block diagram form in figure 3 8 It is functionally divided into two segments data and attribute To accommodate a display matrix of 132 X 24 3 168 characters a 4K data memory and a corresponding 4K attribute memory is required in the formaton of screen memory Each memory segment is divided in half One half corresponds to the upper half of the display screen and the other half corresponds to the lower half of the display screen In the block diagram the two halves are identified as SRMO data and AT
139. racter Sets Programmable Function Keys Fl through F14 F15 through F28 with SHIFT Special Function Keys Control keys Editing and Control Modes Cursor Control Block Mode Transmission Control CHARACTERISTICS 74 key typewriter style alphanumeric keyboard with 18 key numeric keypad Alphanumeric keyboard includes control and special function keys Numeric keypad includes cursor control keys and additional function keys Keyboard selection of domestic stand ard or one of seven international character sets French Italian Swedish Spanish Norwegian German or Danish all contained in standard character ROM Execute user selected character string commands stored in continuous memory Each function key has 77 character buffer Total of 300 characters may be programmed Pressed with FUNCTION key to invoke special functions These include terminal setup block mode conversa tion mode display brightness clear display storing examining data in Programmable Function keys print freeze display Control cursor movement and select character entered for dual character keys CONTROL key with standard keys generate ASCII control characters which are acted upon or displayed ESCAPE key with standard keys emulate host control of EVDT operation Up down forward backward tab back tab home using keypad III key protect mode tab and load read cursor position content Send or print line page of unpr
140. ress decoders and the individual control signals Some blocks in the diagram have sheet numbers for ease of reference i e SH5 means Logic Board Diagram Sheet 5 in Section VI Figure 3 4 shows the keyboard matrix with its column select and row scanner the timing control logic the deserializer serial to parallel converter and the output latch The keyboard logic diagram is a single drawing in Section VI such that no sheet number references are required on the block diagram 3 4 MAIN LOGIC BOARD The following functional descriptions of the Main Logic Board are referenced to figure 3 3 3 4 1 Microprocessor Unit The Microprocessor Unit MPU is a Zilog Z 80A Z 80A is a trademark of Zilog Inc It executes the instructions contained in the Read Only Memory ROM segment of main memory The instructions form the operating system program referred to as the firmware The MPU controls synchronizes and sequences the events that take place in the terminal It communicates with all of the other logic devices including main memory over the 8 bit bidirectional data bus The particular device is addressed selected by means of a unique bit pattern appearing on the l6 bit address bus Once the device is selected by address recognition the MPU either sends data to the device write or takes available data from the device read When a particular device requires service from the MPU the device interrupts the MPU The MPU ackno
141. rix code is fed serially to the serial parallel converter U5 shift register and the positive edges trigger the first half of U3 one shot The duration of this strobe one shot is wider than a zero bit and narrower than a one bit The positive trailing edge of the negative strobe effectively demodulates the signal input as shown in figure 3 20 If a one bit is strobed the serial input is high when the shift register is clocked and a one bit is shifted in The timer counts the number of times the demodulating one shot is triggered It follows that after eight serial shift operations the matrix code character will occupy the shift register The timer triggers the second strobe U3 at this point which then enables the gates U8 09 010 Ull and U12 to provide column selection The first four bits in the shift register represent the BCD value of the col umn 0 9 the four bits are decoded by the BCD decimal decoder U4 to select the column The next three bits scan the particular row by determining which of the inputs to multiplexer U6 will appear as the output The last bit in the shift register is termed the hysteresis bit as will be explained When the second one shot expires the multiplexer output is latched by U7 and the decoder output gating logic is disabled As previously explained when a key is pressed there is an induced voltage inone of the auto transformers TIA TIB through T4A T4B according to the intersection of the row and co
142. rogram counter is saved so that a return can be made to the program that was interrupted Continuous WAIT cycles can prevent the current instruction from ending A bus re quest will override a non maskable interrupt RESET Active low input RESET forces the program counter to zero and initializes the MPU During reset time the address and data buses go to high impedance state and all control output signals go to the inactive state BUSRQ Bus Request Active low input The bus request signal is used to re quest the MPU to relinquish control of the address bus data bus and output control signals which go to the high impedance state as soon as the current machine cycle is terminated When this occurs other devices can control the buses BUSAK Bus Acknowledge Active low output Bus acknowledge is used to notify the requesting device that the MPU has relinquished control of the address and data buses and the control signals The external device is then free to use the buses Single phase TTL level clock which requires only a 330 ohm pull up resistor to 5V to meet all clock require ments 3 13 BFISD 8070 When the interrupting device detects both Ml and IORQ low it places the low order byte of a vector address on the immediate data bus inputs to the MPU D7 DO The high order byte of the vector address is held by the MPU in the I Interrupt register Once this response has been mad
143. rrier Detect Indicates that DCE Host is receiving data transmitt ed by EVDT Data Terminal Ready always true Indicates that EVDT is ready to transmit or receive data Table 6 2 EVDT to Serial Printer Interface Signals I O Port B SIGNAL SOURCE DESCRIPTION None PROT EVDT Printer Protective chassis ground Printer Received Data Serial data received by EVDT EVDT Transmitted Data Serial data trans mitted to printer Printer Data Carrier Detect Indicates that printer is receiving data transmitted by EVDT EVDT Data Terminal Ready Indicates that EVDT is ready to transmit or receive data BFISD 8070 REFERENCE DESIGNATIONS SPARES IC POWER POWER LAST USED MOT USED E dle us NO OF FIM MO DISTRIBUTION CHART FISTRIBUTION CHART SPARES OF SPARES LOCATION TYPE OND r5v 38 1486 JT 5 4 SPS 3 ChE BS SOK 123 TALSI4 489 aspa 7 fa a sie 7453 SE 74S 197 TB T7 i4 BB 487 6 sr TatS20 T i4 S 74858 8 ZF misies 8 fast B 5163 EE 3c 488 7 16 ZBGA DART 3 ou IF TALBIST BOBA CTE 24 7415157 8 TE 29 ise TALSIST 8 io Bc 16 7486 ZG 45886 T 4 i 36 74524 5 1 5 rsy 4G 74574 ipa TO TAN 8 OTF 741574 BG 47 74512 8 2732 7
144. rs required for data transmission and the desired keystroke and or display features 2 7 SETUP MODE PARAMETER SELECTION There are a number of keyboard selectable parameters that may be used to con figure the EVDT for particular operations and individual preferences These parameters fall within two categories parameters that affect the interface with the host CPU and parameters that affect keystroke or display operations Interface parameters control communications to and from the host CPU These parameters must be set correctly or else incorrect data may be sent to or received from the host CPU Interface parameters are selected and set accord ing to requirements of system software hardware and normally will not change unless unique changes are made to the system Keystroke and display parameters allow the EVDT to be configured for individual preferences These parameters affect only the local operation of the EVDT and have no effect on the host CPU Interface parameters and keyboard or display parameters are selected at the keyboard and stored in continuous memory while the EVDT is in the Setup Mode When invoked this mode will place the EVDT in a local condition and display the SETUP menu either as a single line line at a time menu or if desired as a full screen menu See figure 2 9 Invoking the full screen SETUP menu will overwrite any data displayed on the screen invoking the single line SETUP menu however permits param
145. rview Figure 2 11 shows the layout and describes the functions of the domestic EVDT keyboard Figures 2 12 thru 2 18 illustrate the various international key board layouts according to nationality It should be noted that although the international keyboards differ in their keycap designations the keyswitch layout for all keyboards is identical Furthermore those displayable char acters peculiar to each of the international keyboards are derived from trans lation of the standard ASCII code as performed by a programmable universal character generator Programming of the character generator is performed while the EVDT is in the Setup Mode paragraph 2 7 Finally those keyswitch functions captioned in figure 2 11 and all of the keyboard operations des cribed in the following paragraphs apply equally to both domestic and inter national keyboards 2 19 20 BFISD 8070 FUNCIIS PRESSED WITH SPECIAL FUNCTION KEYS TO INVOKE THE BLOCK MODE CONVERSATION MODE AND UPLINE DOWNL INE BACKSPACE FORESPACE SET UP MODE TO CONTROL THE DISPLAY SCREEN AND EXAMINE DATA IN A PROGRAMMABLE FUNCTION KEY AND AND TO PLACE THE NUMERIC KEYPAD IN THE PAD LOCK CURSOR ONLY MODE WITH ESCAPE CLEAR USED IN BLOCK MODE WITH OTHERWISE D MOVES CURSOR IN DIRECTION INDICATED IF NEW POSITION IS PROTECTED CURSOR MOVES TO FIRST UNPROTECTED POSITION IN ROW OR COLUMN FOR BACKSPACE THE NEXT PREVIOUS UNPROTECTED POSITION IS SELECTED CHARACTER UNDER
146. scan of the screen to the exclusion of MPU operations into or out of screen memory The operations are time shared under the control of the arbitration logic which gives precedence to the MPU The MPU addresses screen data memory and attribute memory separ ately while during a screen refresh they are addressed simultaneously The control logic generates the chip enable signals and the read write control signals 3 20 SELECT A B PAO PA11 SA0 SA11 SBCEO PDO PD7 BDO BD6 HFINT SRM1 2K x 8 14H 14G ATTI 2K x 8 14K ADO AD7 WRITE ATT PD0 PD7 9L SELECT A B ARBITRATION LOGIC 14C 14D CONTROL LOGIC 12F Figure 3 8 Block Diagram Screen Memory BFISD 8070 CHAR BUFFER 12G SBCE1 SACE1 ATT BUFFER SMCYC 12J SWH 3 21 BFISD 8070 3 6 5 1 Control Logic The control logic functions are performed by 32 X 8 ROM 12F whose outputs are determined by the state of the address bits SMSEL determines if the MPU is addressing screen memory such that if SMSEL is low a screen refresh is taking place Since the MPU may write into and read from screen memory PRD is used to determine the flow of information and will also determne the state of SWR 12 and All determine which one of the four 2K RAMs is being addressed The significance of the control ROM outputs is as follows Pin 5 SBRD Screen Buffer Read data Pin 4 SARD Screen Attribut
147. splay attributes which are established through keyboard programming and the time of day clock display which is further defined through keyboard pro gramming after Setup Mode selection of the AM PM or 24 hour clock 2 35 BFISD 8070 Business Graphics Characters HEX CODE N m f ir xO r lt O Al m cqa I n Io r lt m of alma NO xO lt O lt O O xO S m m a lt gt lt O ci m Q wn an lt O CO I INIT Ms tL Nn AO r oo lt e m a oem o e on 1 Ta 340 l N N MEME GRAPHICS CHAR ROw AND HE CODE CHAR ka _ E h Ag NS el e N N jo m GRAPHICS 4 12 m B p el zel KA Yi f m 1 ASCII 2 36 BFISD 8070 2 10 1 Setting AM PM or 24 Hour Clock Display Use the following procedure to program set the AM PM 12 hour or 24 hour military time clock display l Place EVDT in Block Mode by entering FUNC at the keyboard 2 Enter ESCAPE CLEAR to enable Clock Control Mode 3 If necessary increment clock display by the hour from AM to PM or from PM to AM by repeatedly entering 2 from the list of codes in table 2 10 If AM PM change is not required
148. t of the chassis NOTE Some terminals have the CRT mounted on the back side of the front corner mounts making it neces sary to remove the CRT through the rear of the chassis In such cases it will be necessary to remove the monitor board before attempting to re move the CRT To replace the CRT use the foregoing procedure in reverse order Refer to Section IV for CRT video adjustment procedures 5 3 BFISD 8070 5 3 4 1 8 Monitor Board PCBA Removal and Replacement Turn off power and disconnect power cord from outlet and video dis play assembly Disconnect the keyboard Remove rear housing from the video display assembly paragraph 5 2 1 Discharge CRT anode to ground Disconnect the following cables or wires a Monitor board to logic board b Monitor board to CRT socket c Monitor board to CRT yoke assembly d CRT anode cap e Green ground wire to CRT ground spring Remove the monitor board by carefully pinching the tip of each corner mounting post and pulling the post out of the mounting hole To replace a monitor board use the foregoing procedure in reverse order Refer to Section IV for monitor board video adjustment procedures 5 3 5 Power Supply PCBA Removal and Replacement l Turn off power and disconnect power cord from ac outlet and video display assembly Disconnect the keyboard Remove rear housing from the video display assembly paragraph 5 2 1 Discharge
149. t word 1 or 2 stop bits odd even or no parity e Terminal security restricted access to keyboard Escape sequences e Full or half duplex operation in Conversation Mode e Display memory refresh rate 50Hz or 60Hz e Extension port activiation I O Port B recieves data from 1 0 Port A e X ON X OFF input data control automatically signals host CPU to stop and start data transmission when input data buffer is almost full and half empty e Cursor display and operating mode blank no cursor cursor underline blinking character at cursor reverse video block cursor roll and combination modes e Standard 12 hour clock AM PM or 24 hour military clock e Scrolling smooth line at a time or disabled e Keyboard operating features tactile feedback with audible click auto line feed with RETURN keystroke auto repeat and end of line bell e Language domestic and international character sets all contained in one character ROM appropriate keycaps provided for language selected BFISD 8070 These keyboard selectable parameters all of which are displayed on a Setup Menu are stored in continuous battery backed memory EVDT general capabilities include 28 programmable function keys stores user selected commands up to 77 characters in length per function key 300 characters maximum Keyboard selection of Block Mode or Conversation Mode 127 ASCII characters 95 displayable characters and 32 control characters
150. tH CHAP PAID S RESET x E3 AS 35 lt P ae 35 EP PD PMREG E TE EIC BUSEQ T XEB 4 GND GND Figure 6 2 Logic Diagram Main Logic Board PCBA Sht 12 of 12 903385 Rev A 6 27 28 BFISD 8070 EE 31 TP1 R6 2204 20 MNIZ10K312 AN dis R21 LSK d o mx TO am mie i 2 wo lt V V V V i i Mr OPERARE NE RS E RR RR S tees ERR PERRA NOTE THIS DIAGRAM IS FOR REFERENCE ONLY REVISION LEVEL WILL NOT BE MAINTAINED 1 Figure 6 3 Schematic Diagram Monitor Board PCBA
151. ter ESCAPE CLEAR See figure 2 20 Table 2 5 Summary of Special Function Key Operating Mode Selection MODE KEYBOARD OPERATION Conversation FUNC s Power up Default Mode STATUS LINE DISPLAY Block FUNC Bk Pad Lock FUNC CAPS LOCK PAD pd Freeze Func F Fz Setup Func 0 Numeric Keypad Zero Key 2 30 BFISD 8070 Table 2 6 Data Editing Control Operations Block Mode FROM OPERATION FROM KEYBOARD HOST CODE DESCRIPTION HE 2 3 5 5 Unprotected data is cleared from display and replaced with space codes Moves cursor to HOME or first unprotected positon Clear Unprotected Display X B B ul 9 52 n FUNC ESCAPE CLEAR ESC ESC ESC T All unprotected data from cursor position to end of line or current field if Protect Mode is set are cleared to Spaces Write Protect Mode is reset All unprotected data from cursor position to end of screen is cleared to spaces Write Protect Mode is reset i I i l i Mi I Imactive in Protect Mode Deletes all data on line in which cursor rests All subsequent lines are moves up one line Write Protect Mode is reset Cursor position does not change Inactive in Protect Mode Line in which cursor rests and all subsequent lines are moved down one line to create blank line Data on bottom line is lost Cursor position does not
152. the DART from generating an interrupt The MPU samples the INT input at the end of each instruction cycle If INT is low the MPU acknowledges the interrupt during the next Ml cycle by forcing IORQ low at the same time as Ml is low in similar manner to an OP code fetch cycle except that MREQ remains high 3 10 BFISD 8070 8 BIT DATA BUS DATA BUS CONTROL INSTRUCTION MPU AND INSTRUCTION DECODE 8 SYSTEM INTERNAL DATA BUS HECISTER CONTROL SIGNALS MPU MPU CONTROL REGISTERS ADDRESS CONTROL Figure 3 5 MPU Block Diagram 3 11 BFISD 8070 Table 3 1 MPU Pin Outs SIGNAL CHARACTERISTICS AO A15 Address Bus AO A15 constitute a l6 bit address bus The address bus is tri state active high The bus provides the address for memory references main memory and the address for 1 0 data exchanges AO is the least significant address bit 1 0 addressing uses the 8 lower address bits to A7 The lower address bits also contain a valid row address during memory refresh time used by dynamic memory DO D7 Data Bus DO D7 constitute an 8 bit bidirectional data bus The data bus is tri state active high The data base is used for all data exchanges with main memory and all de vices classified as I O which includes all logic devices served by the data bus other than main memory and display memory Active low output which signifies that the current machine cycle is th
153. the EVDT displays its model number in the title area see figure 2 21 This title may be changed as described in the following paragraphs To write a new title on the status line enter ESC J then the new title from the keyboard in Block Mode or host CPU If fewer than 10 characters are entered fill the remaining positions with spaces to clear previous data To read the title transmit to host enter ESC n from keyboard in Block Mode or host CPU Read title is terminated by a carriage return only when the EVDT is connected to the host or another terminal 2 47 48 BFISD 8070 SECTION III FUNCTIONAL DESCRIPTION 3 1 INTRODUCTION This section provides a functional description of the Model 4309 EVDT In cluded are a discussion of the general design principles functional descrip tions written to the block diagram level detailed descriptions written to the logic diagram level and a brief description of firmware operation 3 2 GENERAL DESIGN PRINCIPLES The following paragraphs briefly describe the display screen with respect to the display matrix and the display storage Character formation and generation are also described This information is supplied as a prelude to the function al and detailed circuit descriptions to Scquaint the service technician with some of the design requirements The size of the display in accordance with standard industry practice is expressed as a number of characters which in the cas
154. to such memories BFISD 8070 Table 3 1 MPU Pin Outs continued CHARACTERISTICS Active low output HALT low signifies that the MPU has executed a halt instruction and is waiting for a non maskable or maskable interrupt with the mask enabled before MPU operation can resume While halted the MPU executes NOPs to maintain memory refresh activity SIGNAL HALT Halt State WAIT Wait Active low input WAIT low notifies the MPU that the addressed memory or I O device is not ready for data transfer The MPU will continually enter the wait state for as long as this signal is active WAIT allows memory or 1 0 devices of any speed to be synchronized to the MPU INT Interrupt Request Active low input The interrupt request signal is gener ated by the I O devices A request will be honored at the end of the current instruction if interrupts are enabled and if the BUSRQ signal is not active high When the MPU accepts the interrupt an acknowledge signal IORQ during MI time is sent out at the beginning of the next instruction cycle NMI Non Maskable Interrupt Negative edge triggered input The non maskable interrupt request line has higher priority than INT and is always recognized at the end of the current instruction even if the interrupt state is disabled NMI forces MPU to re start location 0066 hex in program memory The p
155. ual may cause interference to radio communications as temporarily permitted by regulation It has not been tested for compliance with the limits for Class A Computing Devices pursuant to Subpart J of Part 15 of FCC Rules which are designed to provide reasonable protection against such inter ference Operation of this equipment in a residential area is likely to cause interference in which case the User at his own expense will be required to take whatever measures may be required to correct the interference Reference Data ix BFISD 8070 8070 01 Model 4309 Ergonomic Video Display Terminal BFISD 8070 SECTION I INTRODUCTION 1 1 GENERAL The Model 4309 Ergonomic Video Display Terminal Machine Type 4309 hereafter referred to as EVDT is a general purpose terminal that provides local data entry and display capabilities for Basic Four Systems 110 through 730 and for System 810 as a 7270 replacement The EVDT figure 1 1 consists of a pedes tal mounted video display assembly and a separate detachable keyboard The EVDT uses an RS 232C asynchronous serial bit interface for bidirectional com munication with the host CPU and a serial printer Separate and independently programmable I O ports are provided for CPU and printer interface connections EVDT capabilities feature keyboard selection programming of the following parameters e Transmit receive baud rate 50 to 19 200 baud e Data word format 7 or 8 bi
156. uit The matrix code sent by the MPU to the keyboard via the keyboard interface consists of 8 bits as follows Bit 7 6 5 4 3 2 1 O Hysteresis Row Column Bit Scan Select Row 0 0 0 O Column 0 0 0 0 0 Row 1 0 0 1 Column 1 0 0 0 1 Row 2 O 1 0 Column 2 0 0 1 O Row 3 0 1 1 Column 3 0 0 1 1 Row 4 1 0 O Column 4 0 1 0 0 Row 5 1 O 1 Column 5 0 1 0 1 Row 6 1 1 O Column 6 0 1 1 O Row 7 1 1 1 Column 7 0 1 1 1 Column 8 1 0 0 O Column 9 1 0 O 1 The matrix code is shifted into a serial parallel converter As each bit is being shifted in a timing input is provided to the timing control logic which generates the clock for the serial parallel converter and the output latch The timing logic also generates the column strobe which occurs when all 8 bits of the matrix code have been shifted into the serial parallel con verter Bits 0 1 2 and 3 according to their binary coded decimal significance scan a particular column Bits 4 5 and 6 according to their binary significance select a particular row Bit 7 enables all the rows simultaneouly Assuming the key with a matrix address 00 row 0 column 0 has been pressed then when row 0 was scanned by the row scanner a one bit would be detected The hysteresis bit and column select signals energize the auto transformer at posi ticn 00 thereby enabling an induced voltage to be generated when the key is presssed A complete scan of all 80 positions in the matrix occurs within 12 milli se
157. uits Always switch off power before removing the rear housing Having determined that the fault condition is not due to an incorrect operating procedure determine if the Master Reset command from the keyboard clears the problem If it does and the problem does not recur the terminal can be con sidered operational If the Master Reset command does not clear the problem the next stage is to identify the problem and troubleshoot accordingly If there are numerous symptoms or what appears to be a combination of pro blems such as improper keyboard operation incorrect display communications problems then it is likely that either the CPU or the microcode PROM s is bad Replacing the main logic board or the CPU should resolve the problem If there is a single symptom such as incorrect display no communications with the host or hard copy printer then troubleshooting should be directed to a single probable source Adjustment of the power supply d c voltages may correct the condition when numerous symptoms appear When a communications problem is encountered it is important to verify that the communication line is operational including the line itself telephone circuits and attached modems and that the host computer is operational Also verify that the terminal can communicate with the hard copy printer If there is no communication with either the host or printer the UART is suspect If communication is possible with either the host or
158. w i Bm 1 5 Lo 12 V B ae M 47 rM i PA 14 FAZ ji PAL pps m PAQ 2 i 22 m i 2 4 29 pots SAN 7 m mL ce ge Aje VAN Ea aa c V CES 3 741574 CKCPUT 3070 65 __ ________ Se NA 2 Figure 6 2 Logic Diagram Main Logic Board PCBA Sht 6 of 12 903385 Rev A i e S bed On BFISD 8070 745788 SMCE WE 1 P CPP TAT At i 4 AB Ad vee i Al VEC GND LWE Oe GPS Ee u i MC LA pay 1209 te 2i WIE an pel 208 Bre 2119 Ae os 501 AS 12421 AQ 4 die Bo4 5 A 2 5 g ADDRESS MULTIPLEXER as a ag HMGIOPS ps EET 44 or nc jart AS On pet II Ev Sy i Aa 4 Bag e O A3 5 25 a SAID ub 7459157 12 3 4 iA A D 38 av mai AZ SAP l 38 B Ai 97 a ve SAB 3lig av 4 f AP 38 ap cup L204 Pall 4 2 2G 22 4A AE SE 11 z A9 2618 FAB Si 2A l PAB 2 ia M EN x Ale di ds NC amm DT Nes 21 WE an De Ti
159. wing storage elements e Program Memory consisting of four EPROMS 1E 2E 3E and 4E e Data Memory consisting of a single static RAM device 6E e Optional Data Memory consisting of eight 16K X l bit dynamic RAMs 4A 5A 6A 7A 8A 9A 10A and 11A configured as 16K X 8 BFISD 8070 3 6 3 1 Program Memory Program memory varies in size according to the required application Four EPROMS are shown on the logic diagram Sheet 5 each EPROM may be a 4K X 8 2732 or 8K X 8 2764 such that program memory may be 4K in total one 2732 or 32K in total 4 2764s Thirteen address bits are used A12 A0 to specify one of a possible 8K loca tions in one of four EPROMS as selected by the individual address decodes MSELO MSEL1 MSEL2 and MSEL3 respectively as described in paragraph 3 6 2 1 The Output Enable OE input to each EPROM is derived from the Read signal PRD from the MPU When PRD is low an instruction is read from the addressed location in the selected EPROM and placed onto the direct data bus inputs to the MPU D7 DO and not PD7 PDO The WE input PWR has no effect on either 4K or 8K EPROM devices 3 6 3 2 Data Memory Data Memory 6E is selected by the address decode DMSEL As shown DMSEL O is inverted by Hex inverter 1G to turn on transistor Q2 which then provides a logic low level to the CE input The Output Enable OE input is derived from the MPU Read output PRD When PRD is low Read the contents
160. wledges the interrupt then determines which device caused the interrupt and responds to the interrupt device The response may be to take a character from the device or to send a character to the device as in the case of the communications interface BFISD 8070 185 ou 6 HS NOISH3ANOO 1 1035 737T1vuvd OT HS 311ISOdWOD J3110H1NOO 104 004 1899 6 HS 1433408 31ng8Iullv AV 1dS1Q TTT HS 30VIG3INI OUVOGAJH 6 HS IIVS OVS 04 004 YOLVYINJD AS A t HS 104 004 sna viva 31n8iu11v H310VHVHO I 7 L _ E SIVd OVd sna ss3ucav 8 m 4 Lava S HS 9 HS v bo TWNO11LdO 3UVMWNI3 180d r SOWO 191 491 38 SIWVNAO wou 30V4H31NI SNOLLVIINNWNWOD L a a o a a ss3uaav 100 A35 71035 NUALIY A33 99708 A3 13NIvUVI 4 DL N Block Diagram Main Logic Board 3 Figure 3 3 4 BFISD 8070 3 4 2 Main Memory Main memory as distinguished from screen memory consists of the operating system program stored in 8K of ROM the data memory provided by 2K of CMOS Random Access Memory RAM and the optional 16K dynamic RAM which expands data memory to 19K The term K normally expresses 1000 decimal but in binary notation is equivalent to 1024 decimal Information can
161. would establish lines 5 thru 12 as the active lines The cursor would appear at the first character position of line 5 and the cursor would be restricted to movement within lines 5 thru 12 Table 2 15 Row Select and Cursor Positioning Codes ASCII HEX ASCII HEX ASCII HEX CHAR CODE COL X CHAR CODE COL X CHAR CODE 20 25 8 38 53 54 ONS O B B TO MO AN JO I gt U Z tN lt x 4 cn g O g O Z E G H Ed ew VIA o 2 44 BFISD 8070 2 10 9 Remote Cursor Commands Three remote cursor commands are available Set Cursor Position Read Cursor Position and Read Cursor Content The Set Cursor Position command is executed upon reception of the four char acter sequence ESC C LY Coordinate LX Coordinate Execution of the command causes the cursor to move to a specific location in the display matrix which corresponds to the codes for the Y row and X column coordinates transmitted by the host No distinction is made concerning protected fields The codes for all possible cursor positions are shown in table 2 15 The Read Cursor Position command is executed upon reception of the sequence ESC Execution of the command causes the codes for the Y row and X column coordinates of the current cursor positon followed by a carriage return to be transmitted to the host CPU The Read Cursor Content command is executed upon reception of the sequence E
162. ws in a frame The MPU informs the controller as to the size of the display the display size is one of the programmable features of the controller The MPU can read the status of the controller by addressing the controller and performing a read operation from the controller 3 6 BFISD 8070 3 4 6 Keyboard Interface The MPU scans the keyboard by polling each key position in the keyboard matrix to determine if the particular key has been pressed The keys are arranged in an 8 X 10 matrix this is a functional not a physical arrary The keyboard interface converts an 8 bit matrix code matrix address into serial data and sends it to the keyboard logic The keyboard re converts the serial data back to 8 bit code The 8 bit code is used to select a column and row in the matrix and thereby select a particular key position When a key has been pressed a voltage is induced in the key s auto transformer The induced voltage is detected by the matrix output circuit latch The output circuit is connected to the interface circuit in the main logic board and the signal is sampled by the MPU to determine if the particular key had been pressed Note that the key does not initiate transmission of a code to the MPU it merely signifies pressed or not pressed When a key has been pressed the MPU is aware of which key it was by means of the matrix code The MPU then generates the code from a look up table If the key was a control key such as t
163. y oriented malfunctions The standard waveforms at the various Monitor Board test points are shown in figure 4 5 sheets 1 and 2 Note that the test points referenced in figure 4 5 are in circuit test points and are shown only on the Monitor Board schematic diagram in Section VI Test point pins designations are not provided on the Monitor Board PCBA 4 3 3 4 EVDT Diagnostic Test The EVDT diagnostic test is a part of the stand alone SILVER Diagnostic System The purpose of the test is to provide the functional analysis of the EVDT and its associated Terminal Controller PCBA The test leads to a conclusion point ing out the malfunctioning parts or confirming the operability of the unit The test is divided into 10 groups The option to execute any given group is provided Group 1 is designed to check extensively the Controller PCBA and EVDT display functions Group 2 thru 8 test extensively the keyboard circuitry both the Extend ed Run Time option and Operator Interventon option must be selected for these groups to operate These tests will check all keyboard types Supported by Basic Four except a Katakana keyboard Group 9 checks the remaining functions of the EVDT namely the CRT dis play ESCAPE CLEAR key the speaker assembly and CRT intensity It also contains the quick and simple keyboard test The Operator Intervention option must be selected in order to execute this group Group 10 checks the printer port interfa
164. y the escape sequence ESC All characters are displayed at full intensity and may be overwritten 2 10 3 Selecting Display Attributes Display attributes are those visual characteristics assignable to a character line or entire display The selection and assignment of display attributes is accomplished through a three character escape sequence Cesc Assignment Code Attribute Code The codes for assigning an attribute to a character line or an entire screen are listed in table 2 12 The codes for selection of the desired display attribute are listed in table 2 13 An example of assigning and selecting a display attribute is Cesc Ga 4 where ESC G assigned the attribute to an entire line and 4 selected the reverse video attribute Table 2 12 Display Attribute Assignment Codes DESCRIPTION Assigns the Attribute from the cursor position to all characters which follow No display positions are used to store the attribute g character Clears the character g Attribute Assigns the Attribute to characters from the cursor position to the end of the line A blank protected character is stored where the Attribute is invoked and where it is reset or altered using G Assigns the Attribute to the entire screen 2 39 BFISD 8070 Table 2 13 Display Attribute Selection Codes ATTRIBUTE No attributes normal display Underlined Blinking Underlined blinking Reverse video Reverse video

Service Manual - EVDT Model 4309

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