Si886xxxISO-EVB User's Guide
Contents
1. SILICON LABS Si886xxISO EVB z JO DHeEWAYIS QAJ OSIXX9881S Z 4 1298815 lt ra 8 z mm zv l a lt Whe gt ON 55 t 5 8 gt ON Od HS AWN gt NCHS t v is L ery i VOSA 1H eal 9 ja 9 4 SNSA i 9L ie S T X VQQA Yada anyo 80384 anyo FE zo 800 i sNsu 99 L L H T L J d vano oz i L i in eist i ame Eldar zis vo 0 T SNSU u Ed ID A zo T gt l viz G am 9H gu anzz nio 9 6L 69 pd 3900 89 Su 8 HNZ v VSOSVSLUES LNOA 4 4 4 4 E 4 4 4 NIA ta 40 02 01 9H pue 32 0 GY eBueuo AEE Jo INOA 104 AS LNOA 01 AVC NIA UOHEJN IJUOJ 19119AU02 SILICON LABS Rev 0 1 Si886xxlSO EVB 5 Si886xxlSO EVB Layout Top Bottom Figure 3 Si886xxlSO EVB Layout Rev 0 1 7 SILICON LABS Si886xxlSO EVB 6 Bill of Materials Table 3 Si886xxlSO EVB Bill of Materials Part Reference Description Manufacturer Manufactu2. VOUT capable of sourcing up to 5 W to an external load connected to terminal block J2 LED D22 above the terminal block J2 illuminates when the dc dc converter is operating VIN and VOUT test points are available along the upper edge of the EVB 1 2 Digital Isolator Supplies The A side power is provided by a regulator circuit referenced to VREGA pin of the Si888621ED IS VIN is stepped down from 24 V to approximately 4 3 V and applied to VDDA pin The B side power is supplied by the output of the dc dc converter through JP 13 1 3 Digital Signals The EVB has a series of header pins for connecting to each digital channel The inside conductor of each 2x1 header is connected to the device pin and the outer conductor is tied to ground through a resistor of 499 Q Connect digital signals to each side of the Si886xxISO EVB through a two row ribbon cable with one row grounded m Channel 1 transmits from A1 JP1 pin 2 to B1 JP4 pin 1 m Channel2 transmits from B2 JP5 pin 1 to A2 JP2 pin 2 Note The digital input signal should not exceed the power supply of the respective side 1 4 Transformer Current Sensing Primary side magnetizing current across the sense resistor R12 can be observed by probing TP20 RSNS with reference to TP33 GNDP 2 Rev 0 1 SILICON LABS Si886xxlSO EVB 2 Alternative Configurations 2 1 Disabling the DC DC Converter The SH FC input U1 pin 7 disables the dc dc converter JP9 controls the
3. 2222LT1 R5 RES 49 9K 1 16W 196 ThickFilm 0603 Venkel CRO603 16W 4992F R6 RES 13 3K 1 16W 1 ThickFilm 0603 Venkel CRO603 16W 1332F R7 RES 100K 1 10W 1 ThickFilm 0603 Venkel CR0603 10W 1003F R8 RES 27 4 0 1 10W 1 ThickFilm 0603 Venkel CRO603 10W 27R4F R12 RES 0 1 Q 1 2W 1 ThickFilm 1206 Venkel LCR1206 R100F R13 RES 4 32K 1 10W 1 ThickFilm 0603 Venkel CR0603 10W 4321F R14 RES 19 6K 1 16W 196 ThickFilm 0603 Venkel CRO603 16W 1962F Rev 0 1 SILICON LABS Si886xxlSO EVB Table 3 Si886xxlSO EVB Bill of Materials Part Reference Description Manufacturer Manufacturer Part Number R15 RES 10K 1 10W 1 ThickFilm 0805 Venkel CR0805 10W 1002F R16 RES 82 0 O 1 10W 1 ThickFilm 0603 Venkel CR0603 10W 82ROF R21 RES 69 8K 1 16W 196 ThickFilm 0603 Venkel CRO603 16W 6982F R22 RES 10K 1 10W 2596 ThickFilm 0603 Venkel CRO603 1OW 103J R24 R25 R28 R29 RES 499 1 10W 4196 ThickFilm 0603 Venkel CR0603 10W 4990F 501 502 503 STANDOFF 1 4 HEX 4 40x3 4 NYLON Keystone 1902D 504 T1 TRANSFORMER Flyback 25 pH Primary UMEC UTBO02205s 500 nH Leakage 3 1 SMT TP1 TP2 TP3 TP4 TESTPOINT BLACK PTH Kobiconn 151 203 RC TP5 TP19 TP20 TP33 U1 IC ISOLATOR DC DC External Switch Freq Silicon Labs Si88621ED IS Control 2 Digital Ch SO20 WB Rev 0 1 9 SILICON LABS Si886xxlSO EVB T Si886xxlSO EVB Ordering Guide
4. SH FC input enabling the converter when pulled low ON and disabling the converter when pulled high OFF To disable the dc dc converter place the jumper in the OFF position on JP9 If interfacing to an external controller through the JP9 header the controller must drive SH low for normal operation and high to disable the dc dc Note When the dc dc converter is disabled the B side can be powered by an active high digital input on the B side Ensure B2 input is tri state or driven low when VDDB is left floating or grounded 2 2 3 3 V DC DC Converter Output To change VOUT to 3 3 V change R5 to 43 2 kO and R6 to 20 0 kO 2 3 Alternate Supply for VDDA To bypass the regulator circuit and supply VDDA from a separate supply remove Q2 and connect positive power supply through JP9 pin 3 and connect the supply return to J1 pin 2 2 4 Alternate Supply for VDDB To supply VDDB from a separate supply remove the jumper on JP13 and supply desired power through JP13 pin 2 and connect the supply return to J2 pin 1 Rev 0 1 3 SILICON LABS Si886xxlSO EVB 3 Quick Reference Tables Table 1 Test Point Descriptions Test Point Description Referenced to TP1 VIN GNDA GNDP TP2 GNDA GNDP N A VOUT GNDB TP4 GNDB N A TP5 SHDN GNDA GNDP TP19 COMP GNDB TP20 RSNS GNDA GNDP TP33 GNDP N A Table 2 Jumper Descriptions Jumper PIN 1 PIN 2 PIN 3 Default Posi
5. Si886xxISO EVB SILICON LABS Si886xxISO EVB USER S GUIDE Description Si886xxlSO EVB Overview This document describes the operation of the Si886xxISO EVB Kit Contents The Si886xxISO Evaluation Kit contains the following items m Si886xxlSO EVB m Si88621ED IS installed on the evaluation board ICON 50 SIBBExxISO EV Rev 0 1 Copyright 2015 by Silicon Laboratories Si886xxlSO EVB Si886xxlSO EVB 1 Hardware Overview and Setup The default configuration of the Si886xxISO EVB demonstrates the digital isolation capabilities of the installed Si88621ED IS as well as its dc dc converter performance In this configuration the dc dc converter is enabled the primary side digital supply is sourced by an external regulator circuit and the secondary side digital supply is sourced by the output of the converter This EVB configuration has a jumper installed at JP9 in the ON position JP13 has a jumper installed and the remaining jumpers not populated Note Do not place jumpers across JP10 or JP11 These are additional test points for VDDA GNDA and GNDB and VOUT respectively 1 1 DC DC Converter Input and Output Supply power to the EVB by applying 24 Vdc to VIN at terminal block J1 LED D21 above terminal block J1 illuminates to show power applied to primary side of the converter The isolated dc dc output VOUT is available at terminal block J2 The populated values for R5 and R6 produce a 5 V output at
6. Table 4 Si886xxlSO EVB Ordering Guide Ordering Part Number OPN Si886xxISO KIT Description Si886xx dc dc digital isolator evaluation board kit 10 Rev 0 1 SILICON LABS Si886xxlSO EVB CONTACT INFORMATION Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 Tel 1 512 416 8500 Fax 1 512 416 9669 Toll Free 1 877 444 3032 Please visit the Silicon Labs Technical Support web page https www siliconlabs com support pages contacttechnicalsupport aspx and register to submit a technical support request Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low power small size analog intensive mixed signal solutions Silicon Labs extensive patent portfolio is a testament to our unique approach and world class engineering team The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice Silicon Laboratories assumes no responsibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed fea tures or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warran ty representation or guarantee r
7. egarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Silicon Laboratories products are not designed intended or authorized for use in applications intend ed to support or sustain life or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders Rev 0 1 11 SILICON LABS
8. rer Part Number C2 CAP 10 pF 50 V 20 X7R 1210 Venkel C1210X7R500 106M C4 CAP 10 pF 10 V 20 X7R 1206 Venkel C1206X7R100 106M C5 C9 C12 C14 CAP 0 1 pF 10 V 10 X7R 0603 Venkel C0603X7R100 104K C6 CAP 0 47 UF 16 V 10 X7R 0805 Venkel C0805X7R160 474K C8 100 pF 50 V 10 X7R 0603 Venkel C0603X7R500 101K C10 22 UF 25 V 10 X7R 1210 Venkel C1210X7R250 226M C11 1 5 nF 25 V 10 X5R 0603 Venkel C0603X5R250 152K C18 0 047 UF 100 V 10 X7R 0805 Venkel C0805X7R101 473K C19 CAP 68 pF 100 V 10 COG 0603 Venkel C0603C0G101 680K D1 DIO SUPER BARRIER 50 V 5 0A SMA Diodes Inc SBRT5A50SA D6 DIO FAST 200 V 1 0A PowerDI 123 Diodes Inc DFLU1200 7 D7 RES 0 1 ThickFilm 0603 Venkel CRO603 16W 000 D20 DIO ZENER 28 V 500 mW SOD123 On Semi MMSZ5255BT1G D21 D22 LED RED 631 nM 20 mA 2 V 54mcd 0603 Lite On LTST C190KRKT J1 J2 CONN TERM BLOCK 2POS 5MM PCB Phoenix Contact 1729018 JP1 JP2 JP5 JP6 JP10 JP11 JP13 Header 2x1 0 1 pitch Tin Plated Samtec TSW 102 07 T S JP9 Header 3x1 0 1 pitch Tin Plated Samtec TSW 103 07 T S JS9 JS13 Shunt 1x2 0 1 pitch Tin plating Samtec SNT 100 BK T MH1 MH2 MH3 HDW Screw 4 40 x 1 4 Pan Head Slotted Richco Plastic Co NSS 4 4 01 MH4 Nylon Q1 TRANSISTOR MOSFET N CHNL 100 V 3 7A Fairchild FDT3612 3W Switching SOT223 Q2 TRANSISTOR NPN 30 V 600 mA SOT23 On Semi MMBT
9. tion Description JP1 GNDA A Not Installed Digital Isolator Connector through 499 0 JP2 GNDA A2 Not Installed Digital Isolator Connector through 499 Q JP5 B1 GNDB Not Installed Digital Isolator Connector through 499 Q JP6 B2 GNDB Not Installed Digital Isolator Connector through 499 Q JP9 GNDA SHDN VDDA Installed DC DC Converter Enabled SHDN GNDA JP10 VIN GNDA Not Installed DO NOT SHORT test points only JP11 GNDB VOUT Not Installed DO NOT SHORT test points only JP13 VDDB VOUT Installed Connects VDDB to VOUT Note Pin numbering is from left to right 4 Rev 0 1 SILICON LABS 51886 150 4 Si886xxISO EVB Schematics 2 JO L 051 988 5 4 2222 Rev 0 1 Wy WWW 1298815 ex 5 D 27 Q S e M l 2 AW HS AW 66v 66v MW og pzs zv Hol AN gar zar seu 66v 66v ANY loni ws we oo AW Eras taf ved lt lt 5 59 5 bar orar in T T OL PIJEA LNON NIA vano Ajddng 3nduj 0 Ajddns jewod ue j2euuoo LON OG SI SIUL 1nO NIA E 4 4 x za 8 69 t a 5 zr OL 2 n 1nOA
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