DCAM Frame Capture Kit Hardware User's Guide
Contents
1. HARDWARE USER S GUIDE Date 17 February 2005 LOO Doc no DCAM_FC_HG iJ Iss Rev 1 00 S orsys Page WW Hardware User s Guide DCAM Frame Capture Kit for the UC1394a 1 Orsys Orth System GmbH Am Stadtgraben 25 88677 Markdorf Germany http www orsys de LO HARDWARE USER S GUIDE GE iJ DCAM FRAME CAPTURE KIT Iss Rev 100 orsys Page 2 Contents 1 ru e 5 1 14 Document trraplratletteegsseupsgeguetzseeggeesegeege eege EeEENESER 5 1 2 Documentation Overview Seene DEENEN ENEE de teed eden 5 1 3 Notatlonal CONVENTIONS eeszuesksedeueskekeEeeREESKESEESEEEEKNEEENE ENEE EEN EE EEE REESEN a 5 L a ee ea E SERA EEEK basse sssaacusscnsie 6 KW VE IN E 6 2 KIT OVERVIEW EG 7 2 1 H Les KT C ae le TB 8 2 2 UC1394a Carrier Board sccccecsccsesciseaescscieccscentexetcatatsseetincnainchiaasuiwestitceraicczaccever ennenen eee 8 2 3 micro line Power Supply Board s s sssesssssesssscsssesesssssersesestsetesseseeraeeeeesetessestanaeeeseesteeseans 9 2 4 Interfaces and e a E E 9 2 4 1 Software un e EE 9 2 4 2 micro line Peripheral Interface 10 2 4 3 IEEE1394 Interface AAA 12 2 4 4 IEEE1394 Data Transfer Methods A 12 24 5 UART IntertaCg eueteut Auberge EEN nen ini Alin nis 15 RT l E 16 2 4 7 MEBSP aal 17 248 BT e len ET 18 DAD C AEA c O csc destinies ica couch de de ape ete eh ee Sede ca 18 2 410 Analog INPUTS seas oie a oe nee cas ee ec cc 18 2AN besen ee Ee 19 2412 ED ee 19 2 4 13 System IMGSEL EE2. reserved n a Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG J DCAM FRAME CAPTURE KIT iss Rev 1 00 orsys Page WEN 4 2 4 Connector C Connector C carries the directly connected data lines of the peripheral interface It is strongly recommended to leave this connector unconnected an to prefer the data lines on the A connector connector pin C1 DATAQ peripheral ES DATA1 interface C1 C2 C4 DATA3 C5 C6 CS DATA reserved Table 20 Pinout for micro line connector C These signals should not be used on this connector Instead the signals on the A connector should be used Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG N DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 32 4 2 5 Connector D Connector D is used for connector pin RS 232 UART interface converted to RS 232 levels power supply reset signals control and interrupt lines of the peripheral interface power supply reserved IORD TxD D8 RESETOUT gien reset D9 reserved n a IC _ DH cz peripheral interface INT D18 INT4 peripheral interface RS 232 CTS IORDY peripheral interface reserved n a Table 21 Pinout for micro line connector D Date 17 February 2005 LN
3. 41 0 32 421 04 00 Fax 41 0 32 421 04 01 E mail sales precidip com http www precidip com Connector type Part number xx number of pins peripheral board 10mm board spacing single row 326 91 1xx 41 001001 peripheral board 10mm board spacing double row 426 91 2xx 41 001001 or from Fischer Elektronik GmbH A Co KG D 58465 L denscheid Germany Phone 49 0 23 51 4 35 0 Fax 49 0 23 51 4 57 54 E mail info fischerelektronik de http www fischerelektronik de Connector type Part number xx number of pins peripheral board 10mm board spacing single row MK13 xxZX1 peripheral board 10mm board spacing double row MK213 xxZX1 carrier board double row thruhole MK201 xxZ carrier board single row SMT not available carrier board double row SMT MK220SMD xx Z carrier board single row thruhole MKO1 xxZ Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 37 or from Mill Max Mfg Corp 190 Pine Hollow Road Oyster Bay NY 11771 USA Phone 516 922 6000 Fax 516 922 9253 E mail sales mill max com http www mill max Com Connector type all types see table for Preci Dip 4 5 Connectors for the Analog Input and Alternative RS 232 Connector Suitable receptacles for the alternative RS 232 connector and the analog input connector are lumberg www lumberg com MICA 10 5 Literature references 1 D
4. connector P 4 2 8 Connector X Connector X carries the DC signals n a IC interface Table 24 Pinout for micro line connector X Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsySs Page 135 4 2 9 Other Connectors Connector pin Table 26 Pinout for the analog input connector 4 2 10 JTAG Connector Signal FPGA_TMS GND FPGA PROM FPGA_TDI GND FPGA_TDO GND FPGA_TCK GND 5 GND not connected B6 Inor connected unused CPU_EMU1 DSP GND CPU TCK_ B9 GND 10 GND 0 not connected CPU TDI CPU_TMS 13 CPU_TRST Table 27 Pinout for the JTAG connector z GA LN HARDWARE USER S GUIDE Date 17 February 2005 d Doc no DCAM EC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 36 4 3 Signal Levels and Loads All digital UO lines on the micro line connector except the RS 232 signals use 3 3 V LVTTL compatible signal levels CAUTION Applying more than 3 6 V to any logic input will damage the device 4 4 micro line Connectors for Customized Hardware For building customized carrier boards and daughtercards standard 0 1 inch breadboards can be used Suitable connectors that fit to the carrier board s micro line connector can be purchased from Preci Dip Durtal SA Rue St Maurice 34 P O Box 341 CH 2800 D lemont Switzerland Phone
5. A suitable receptacle for this connector is listed in chapter 4 5 Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG J DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 19 Connector pin Table 5 Analog input connector 2 4 11 RTC Usage of the DSP RTC is not supported by the default carrier board configuration If RTC usage is required please contact Orsys for further information 2 4 12 LEDs The carrier board provides three LEDs Two of them are controlled by I O pins as described in chapter 2 4 6 A third red LED lights at system startup while the carrier board FPGA isn t configured It must go off after about one second If this LED stays on one of the following reason may prevent configuration of the carrier board FPGA e the PROM with the FPGA code is not correctly programmed e Abus conflict on micro line connectors C1 C8 corrupts the FPGA code during startup Location of the carrier board LEDs is shown in Figure 2 The MCM also has a red LED which is controlled over the MCM s FPGA How to access this LED is described in 1 2 4 13 System Reset The reset signals of the MCM are directly connected to the respective micro line connector On the power supply board the reset input is connected to a pushbutton The reset signals are described in 1 ML Connector pin RESETIN RESETOUT D8 _ _ _ Table 6 C connectors of the carrier board Please note that RESETIN
6. HARDWARE USER S GUIDE Doc no DCAM FC HG LJ DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 33 4 2 6 Connector E Connector E is used for the McBSP signals of port 0 and 1 and for some directly connected control signals of the peripheral interface It is strongly recommended to use leave these control signals unconnected and to use the corresponding signals on the D connector instead connector pin ORDY interface VIOSTRB reserved n a IORD peripheral AORW interface reserved n a DR1 DX1 CLKR1 CLKX1 FSR1 FSX1 McBSP1 reserved DRO DXO CLKRO CLKXO FSRO FSX0 XFOUT 1 04 McBSPO 7 I O pins reserved Table 22 Pinout for micro line connector E These signals should not be used on this connector Instead the signals on the A connector should be used 7 VO 4 should not be used on this connector Instead the signals on the A connector should be used Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG CJ DCAM FRAME CAPTURE KIT iss Rev 1 00 orsys Page 34 4 2 7 Connector P Connector P can be used for supplying power to the IEEE1394 cable micro line Signal Interface connector pin 1 reserved PSs P68 V SOV reserved n a CABLE_GND CABLE POWER IEEE1394 interface IEEE1394 interface Table 23 Pinout for micro line
7. a request that is sent to the destination device and a response that the destination device sends back This enables error checking at the sender Asynchronous transfers are well suited for e data that occurs randomly e g control and status information e transfers where the originator of the transfer must be informed about the status of each single transfer 2 4 4 4 Plug amp Play features of IEEE1394 When devices are connected to or disconnected from the IEEE1394 network node ID s are automatically assigned for the connected devices This is done by the chipset without any software intervention Independent of the node ID most devices provide some more information about themselves There is an area within the IEEE1394 address space that is called configuration ROM The configuration ROM holds information about e the manufacturer of the device e device serial number e software interface of the device The serial number together with the manufacturer form a world wide unique 64 bit ID Using this 64 bit ID the device can be identified independently of the network topology or the currently assigned node ID The next higher level of identification is the protocol level The DCAM frame capture kit identifies itself as a device running a generic protocol specified by Orsys This protocol can be used on a host PC to load appropriate device drivers Customized protocol identification is available from Orsys on request This picture shows
8. isochronous transmit operation which is not used in the DCAM fame capture kit Date 17 February 2005 Ly HARDWARE USER S GUIDE Doc no DCAM_FC_HG or sy S DCAM FRAME CAPTURE KIT Iss Rev 1 00 Page 15 2 4 4 5 Power Distribution Over IEEE1394 The IEEE1394 standard defines a 6 wire cable that allows to supply devices over the cable This is often used for digital cameras To operate the UC1394a 1 powered from the IEEE1394 cable an external voltage regulator is required The IEEE1394 standard allows up to 10W power consumption for a device Figure 7 shows the power supply options that are available for the carrier board in standard configuration Option supplying remote micro line devices over the cable connector P6 IEEE1394 14 P7 porto 2 polyswitch Option2 supplying the kit from IEEE1394 1 se the cable i porti 2 i eed ig regulator Figure 7 IEEE1394 power supply options of the carrier board 2 4 4 6 Isolation The IEEE1394 interface of the UC1394a 1 is directly connected to the remaining circuit There is no galvanic isolation between the IEEE1394 cable and the local power supply In a custom hardware design the VG pin of the 1394 connector must be connected to the GND pins of the UC1394a 1 2 4 5 UART Interface The UC1394a 1 MCM has an UART interface that can be used for standard asynchronous communication Different baud rates are supported as well as RTS CTS handshake Th
9. lists the documentation from Orsys that is shipped together with the DCAM frame capture kit Further documents from other vendors may also be listed in chapter 5 and are referenced throughout the document in square brackets DCAM API User s Guide for UC1394a 1 1 pcam_uc pa Describes the DCAM frame capture API thus the software programming interface of the DCAM frame capture kit DSP Master BSP User s Guide 2 psp_master_psp_uG pdf Describes the DSP Master Board Support Package BSP on which the DCAM frame capture kit is based This includes FPGA register description programming documentation and technical data of the UC1394a 1 MCM micro line Power Supply Kit 3 power supply pat Describes the micro line Power Supply board 1 3 Notational conventions Names of registers bit fields and single bits are written in capital letters Example LLC_VERSION Names of signals are also given in capital letters active low signals are marked with a at the beginning of the name Example RESETIN Configuration parameters function names path names and file names are written in italic typeface Example dev_id Source code examples are given in a small fixed width typeface Example int a 10 Menus and commands from menus and submenus are enclosed in double quotes Example Create a new project using the Create Project command from the File menu The members of a bit field or a group of signals are numbered
10. programming a PROM on the carrier board e temporarily downloading FPGA code to the carrier board FPGA and e temporarily downloading FPGA code to the MCM All JTAG signals are available at the JTAG connector of the carrier board together with the DSP JTAG signals Table 27 lists the pinning of the JTAG connector The FPGA JTAG interface is used with programming hardware such as the Xilinx parallel download cable A JTAG adapter which is included in the DCAM frame capture kit provides a suitable connector ES OPRESTE IEIS Sannnnnnnnnng 5858858858858888 A B 33V GD TCK TDO TD TMS FPGA JAG connector D g DP JAG connector fits T emulator POD o o CEE top view Figure 12 JTAG Adapter with FPGA JTAG signals shown FPGA development for the MCM or the carrier board is available as a separate product 2 4 16 Power Supply Input The UC1394a 1 MCM requires a single regulated 3 3 V power supply The carrier board generates this voltage from the power input of the micro line connectors which is 5 V nominal The micro line power supply board supplies 5V to the micro line connector from a switching regulator It allows unregulated power input of 9 V 12 V The power supply board can be supplied from a usual AC adapter which must be capable of delivering 9 V 18 V and AN Optionally connected IEEE1394 devices can be supplied over the cable In turn power from the cable is also available at micro line connector P Please
11. the MCM loads the FPGA and then enters a main loop The main loop waits for a constant delay and then toggles the MCM s LED The carrier board LEDs are not used in this example After loading and starting this example the MCM s LED is blinking This application example can also be used as a rudimentary test to check if the kit or the MCM is working properly 3 3 UART hello The UART example shows how to set up and use the UART First the MCM is set up and the FPGA is loaded Then the UART is initialized for 115200 baud and hardware RTS CTS handshake Then an output message is assembled using the stdio function sprintf The output message contains some information about the MCM The output message is sent to RS 232 by accessing the UART registers Finally the main loop is entered In the main loop the UART interface is checked for incoming characters Whenever a character comes in it is simply echoed COM1_115200_8_N_1_HW HyperTerminal Datei Bearbeiten Ansicht Anruf bertragung 7 Hello world UC1394a 1 200HH2 S H 6753 asdasdasd po Y L Verbunden 01 17 59 1152008 N 1 R E Figure 13 Sample session of the hello example 3 4 Buffered Character I O dbg_out This example uses the UART interface at a slightly higher level of abstraction buffered character I O as provided by the module support library see 1 for details This is an alternative to using the stdio functions such as sprintf sscanf etc dbg
12. 19 2 414 DSP TAG WMC CC ee Geer eege 19 2 4 15 FPGAJTAG EE EEGEN 20 2 4 16 Power Supply Input crea ca ec ce ace te eee cadena eh eee 20 3 APPLICATION EXAMPLES ss sss sss sese seene eenn 21 3 1 Download POCO UGG sssssssssssvsygsszsessst2ssgraczss3syzssyczreseaegsggssyzon gassa sn52sy CS cad ciesnionensdoasans 21 3 2 LED Control toggle ledi ics ict cis esssssssseessssssne seene ennenen ees 22 33 UART TT 22 3 4 Buffered Character I O dbg_out ccccccssssesseeeeeeeeeeeeeeeeneeneeeeeeeeeenaseeeeeneneeseseseeeeeeseeneeees 22 3 5 VO Pins 60 Blues 23 LO HARDWARE USER S GUIDE GE DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys eo 3 6 Peripheral Interface periph HI eeEeEEERRREEEEEEEEEEEEEEREEEEEEEEEREEEEEEEEEEEEEEEEEEEEEEEEEEEEKEEEEEEEEEEEEEEEEE 23 4 TECHNICAL DATA WE 25 4 1 Connector Pinout Summary by Interface ecccessseeeeeeeeeneeeeeeeeneeeeeneeeeeeeeneeeneeeeneeeeneeeeas 25 4 2 Connector Pinout Summary by CONnMme ctl ccccccseeeeeeeeeeneeeeeeeeeeeeeeneeeeeeeeeeeeeeeeeneeeeneeense 28 421 GOMMOCION A EE 28 4 2 2 Connector B eosar ARAE AAEE EAA EENAA EEA ENNEN EEKEREN RREA 29 423 Connector Bb 30 ADA COAneCiOr EE 31 425 COMME CIOM D EE 32 426 Cmo E 33 421 Coneco EE 34 428 Connector X oo eeeceeeeccceececceeeceeecceuecccaeeceueecaaeecaaeeeeaueesaesesaueessaueesaueesaesesaueeseaeeeseeeseeeesneeenas 34 4 2 9 Other Connechors innnan gagang Ta NANEN N ENNAN ENN EN ENEAK IN ENKEN ENEAN
13. 4 power supply options of the Carrier board sss sees eee eee eee eee 15 Figure 8 UART interface block diagram sss eee eee eee 16 Figure 9 lO pin block diagram EE 17 Figure 10 McBSP block diagram sss sese eee eee 18 el 11 JTAG Ee ET 20 Figure 12 JTAG Adapter with FPGA JTAG signals shown seer eee 20 Figure 13 Sample session of the beiloevample ENEE 22 Figure 14 Waveforms generated by the Genoh exvample AAA 24 Date 17 February 2005 Ly HARDWARE USER S GUIDE Doc no DCAM FC HG LJ DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsySs Page 15 1 Preface This document describes the hardware platform for the UC1394a 1 based DCAM frame capture kit It is intended to get an overview of the whole kit and the features provided by the carrier board Detailed information about programming FPGA usage and UC1394a 1 technical data is contained in other documents that will be referenced throughout this document FPGA development is not supported by the DCAM frame capture kit but available as a separate product 1 1 Document Organization This document is organized as follows e Chapter 2 gives a brief overview of the whole system and its interfaces Chapter 3 tells how to do the very first steps Chapter 4 lists technical data of the kit such as pinning Chapter 5 lists documents that contain further information Chapter 6 explains the abbreviations that are used throughout this document 1 2 Documentation Overview This chapter
14. AM FRAME CAPTURE KIT orsys BB1 D19 BB2 D20 BB3 D21 BB4 D22 BB5 E27 C27 E26 C26 CEG n a A13 n a A14 CFG3 n a A15 n a A16 Table 8 I O pin connector pin assignments for the carrier board and the MCM Table 10 McBSP interface pin assignments for the carrier board and the MCM 3 3V signal level Level converter required Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG J DCAM Frame Capture KIT os Pe 1 00 orsys Page 27 micro line connector pin UC1394a 1 pin UC1394a 1 pin Table 12 Analog input pin assignments for the carrier board and the MCM Je pt RESETIN RESETOUT D8 ae Table 13 Reset signal pin assignments for the carrier board and the MCM LEES D5 D ma see D D1 D4 Table 14 Power pin assignments for the carrier board UC1394a 1 pin RESETIN RESETOUT D8 A Table 15 Reset signal pin assignments for the carrier board and the MCM UC1394a 1 pin 8 V 30 V L PR HR CABLE_POWER CABLEGND PQ Table 16 IEEE1394 cable power supply for the carrier board Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG CJ DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 28 4 2 Connector Pinout Summary by Connector The tables in this chapter list the connector pinout for e each micro line connector row e the analog input connect
15. CAM Frame capture API User s Guide Orsys ncam uc paf 2 DSP Master BSP User s Guide for the UC 1394a 1 MCM OrsySs psp_master_BSP_UG 3 User s Guide micro line Power Supply Kit Orsys Power_Supply pdf 6 List of Abbreviations Used in this Document API application programming interface BSP board support package a combination of software and FPGA design that provides a dedicated functionality to the UC1394a 1 MCM CCS Code Composer Studio TI s development environment CPU central processing unit processor DCAM Commonly used as abbreviation for the IIDC 1394 based Digital Camera Specification DSP Digital Signal Processor EMIF external memory interface an interface of the TMS320VC5509 DSP FIFO first in first out a special type of memory firmware software installed on the UC1394a 1 MCM firmly installed software FPGA field programmable gate array FG inter integrated circuit a low speed interface between integrated circuits IIDC 1394 Trade Association Instrumentation and Industrial Control Working Group Digital Camera Sub Working Group specifier of the IIDC DCAM standard KB kilobyte 1024 byte KBps KB per second LED light emitting diode LLC IEEE1394 link layer controller LSB least significant bit or byte MB Megabyte 1204 KB 1048576 byte MBps Megabytes per second Mbps Megabits per second McBSP multi channel buffered serial port a peripheral of the TMS320C6713 DSP MCM multi chip module ML micro
16. ENIN ENAN EENEN San gy 35 4210 JTAG COMEC enaa N 35 4 3 Signal Levels and LoadS sseesssecvessseeeessseeeessreeressseeessereessreennnre esen essere 36 4 4 micro line Connectors for Customized Hardware EE 36 4 5 Connectors for the Analog Input and Alternative RS 232 Connector sssssseeeeeeeeees 37 5 LITERATURE REEERENCES cx sss sss sees eenn ennenen ennenen ennenen ennenen 37 6 LIST OF ABBREVIATIONS USED IN THIS DOCUMENT scsseeteesseeeeeeeenseneeees 37 Date 17 February 2005 Ge reene er ace orsys Page A List of Tables Table 1 Peripheral interface Signals eee eee eee 11 Table 2 Direct connection to some peripheral interface signals eee eee eee eee 12 Table 3 UART Connector pin assignmente eee eneen ee 16 Table 4 1 C connectors of the ratdierfboargd EENS 18 Table 5 Analog INput COnNNECtOrT E 19 Table 6 C connectors of the carrier board 19 Table 7 Connector pin assignments for the peripheral interface eee eee eee eee 25 Table 8 I O pin connector pin assignments for the carrier board and the MCHM eee 26 Table 9 UART interface connector pin assignments for the carrier board and the MCM 26 Table 10 McBSP interface pin assignments for the carrier board and the MOM eee 26 Table 11 IC interface pin assignments for the carrier board and the MCL 27 Table 12 Analog input pin assignments for the carrier board and the MCH sese 27 Table 13 Reset signal p
17. O Ia DATA11 A12 DATA12 A13 DATA13__ A14 DATA T A15 DATA Tag CSL TD CS2 AD1 CS3 JD CS4_ TD CS5_ TDI CS6_ TD EST Jg IORD____ D22 IOWR____ D23 IORW___ D24 IOSTRB__ D25 IORDY___ D30 INT3 D17 interrupts INT4 D18 Table 1 Peripheral interface signals SS chip select lines J control signals e S Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG NAI DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsySs Page 12 DATA C12 control signals HORW Ei i O Table 2 Direct connection to some peripheral interface signals 2 4 3 IEEE1394 Interface The UC1394a 1 MCM has two 400 Mbps IEEE1394 ports These ports are routed to two standard 6 pin IEEE1394 connectors on the carrier board Using these two ports the DCAM frame capture kit can be inserted anywhere in an existing IEEE1394 network Since the IEEE1394 physical layer acts as a repeater no processing power is required for transferring data from one port to the other For transferring data between the DCAM frame capture kit and the IEEE1394 network three transfer methods are available which are described in the following chapter 2 4 4 IEEE1394 Data Transfer Methods IEEE1394 provides three different methods for transferring data e isochronous streaming e asynchronous streaming e asynchronous transactions Asynchronous transactions are handled by the IEEE1394 API whereas is
18. United States and or other countries Hypterterminal is a trademark of Hilgraeve Inc All other brand or product names are trademarks or registered trademarks of their respective companies or organizations 1 5 Revision history 1 0 First public release Replaces uc1394a1_dsp dev_kit_hrg for the DCAM frame capture kit Doc no DCAM EC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 Ey HARDWARE USER S GUIDE Date 17 February 2005 orsys Page 7 2 Kit Overview The DCAM frame capture kit consists of three modules e AnUC1394a 1 MCM soldered on a carrier board for easier handling e AnUC1394a carrier board e Amicro line power supply board Power Supply Board UC1394a Carrier Board RS 232 connector LVTTL Level micro line SN UART converter RS 232Z connector P IEEE 1304 interface IEEE1394 Peripheral Carrier Board port1 interface FPGA DSP JTAG XFOUT JTAG interface VO pins CEO connector FPGA JTAG O 4 0 Configuration interface switches Analog in Carrier Board conector FPGA E 0 00000 McBSP2 McBSP eo amp USB interfaces pais red green LED LED PC McBSPO 1 interface Reset button 5V Cable power option supply Power connector eh 9 V 18 V unregulated AC adapter Figure 1 DCAM frame capture kit block diagram Date 17 February 2005 Ls HARDWARE USER S GUIDE Doc no DCAM FC HG iJ DCAM FRAME CAPTURE KIT I
19. _out prints out the same startup message as hello but the main loop is programmed as a command interpreter This shows how to implement an application that is interactively controlled over RS 232 Pressing the key within the terminal program causes a help page to be displayed Other command keys can easily be added by inserting appropriate case statement in the command switch Below is an example that shows how insert a command that toggles the MCM LED by the t key Date 17 February 2005 Ly HARDWARE USER S GUIDE Doc no DCAM FC HG LJ DCAM FRAME CAPTURE KIT es er 1 00 orsyS Page 22 below is a command switch that could be used in applications that require user interaction over RS_ 232 switch c case s case h DebugOutConstString Debug interface example r n DebugOutConstString h and show this help page r n no other commands keys defined r n break case t toggle the red MCM LED UC1394A SYS CTL UC1394A SYS LED break default DebugOutConstString invalid command 2 shows a help page r n break 3 5 I O Pins io_pin Theo Din example works together with the carrier board LEDs It doesn t generate any output except for the visual feedback through the carrier board LEDs After the usual startup I OO and UO are configured as outputs and WO is configured as an input according to the direction predefined by the carrier board see also Figure 9 In th
20. and FPGA JTAG routing Three LEDs for visual feedback A JTAG connector for DSP software download software debugging and FPGA design download e Aconnector for the MCM s analog inputs e Analternative RS 232 connector not used with the DCAM frame capture kit e An USB connector The carrier board is intended as a development aid which is used in the prototyping stage of a project In the end product the UC1394a 1 MCM will typically be used standalone analog in connector B m UB BB m connector JRG conector n nn Wu wu m RR 55 H 8 Zo S S S mmm atn S S wm S S red LED FPGA not configured Mumm red LED user programmable 855 S N Ne E E Z ey green LED user programmable 88 I 1 a wt Z connectors I mmm configuration DIP switch t S oo E ann a a io STO O EE m D P wm n ere RS 232 Cu connector De EGND on Eu a micro line connectors xP Figure 2 UC1394a carrier board connectors and control elements 1 MCM FPGA development is available as a separate product HARDWARE USER S GUIDE Sf DCAM FRAME CAPTURE KIT orsys Date 17 February 2005 Doc no DCAM EC HG Iss Rev 1 00 Page 9 2 3 micro line Power Supply Board The micro line power supply board acts as a desk carrier board It provides connectors for RS 232 and unregulated power input Further it provides a button for resetting the MCM and the carri
21. e carrier board uses a level converter to convert these signals to RS 232 level How to program the UART interface is described in 1 The distribution media contains an application example for the UART in the hello folder The UART interface uses 2 data lines and 2 handshake lines A detailed description of the UART signals can be found in 1 Date 17 February 2005 HARDWARE USER S GUIDE Doc no DCAM FC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 16 D Power Supply Board 94a Carrier Board 10 pin connector UC1394a 1 micro line with DSP master BSP connector O 9 pin sub D connector converter 00000 QQQ 0 Figure 8 UART interface block diagram The RS 232 signals are available at two connectors e ona 9 pin sub D connector on the power supply board routed via the standard micro line connectors e onan alternative connector located on the carrier board This connector can be used for direct cable connections to the carrier board A suitable receptacle is listed in chapter 4 5 E Cable connection to a remote PC Sub D 9 pin Sub D 9 pin Sub D 25 pin Table 3 UART connector pin assignments 2 4 6 I O Pins Please note With exception of the XF pin all I O pins of the MCM are implemented in the FPGA whereas the on chip GPIO pins of the DSP are not available on the UC1394a 1 The available I O pins are divided into three groups e FPGA I O a part of
22. e main loop the red LED of the carrier board is continuously toggled so that it is blinking The green LED is controlled by the state of I O 3 For testing 1 03 micro line connector pin BB4 can be connected to one of the following connector pins by a 1kQ series resistor a none The green LED is lighting caused by 1O3 s built in pull up resistor b GND pin D1 The green LED is switched off b 1 01 controls the red LED pin BB2 The green LED is also blinking 3 6 Peripheral Interface periph_if This application example has neither any text output nor does it control the LEDs It is mainly intended as a source code example Further the peripheral interface signals can be viewed with an oscilloscope or a logic analyzer After the usual initialization the main loop performs the following sequence e pulse XFOUT as a trigger signal write an all zeros pattern to the first address of CS1 write an all ones pattern to the last address of CS1 repeat the last 2 steps for CS2 through CS7 do a dummy read from the first address of CS1 repeat the last step for CS2 through CS7 repeat the complete sequence Figure 14 shows some waveforms that were generated by this example The left cursor shows the start of the sequence The right cursor shows a common programming issue for the DSP EMIF which is also described in 1 chapter Pipeline The last write operation CS7 highest address pattern OxFFFF is immediately followed by a read
23. er board The power supply board generates a regulated 5 V supply for the carrier board from an unregulated 12 V input power indicator LED micro line connectors DANS S SOS S66066800668050600008660008 o rp S e S q as on ES 6 S e Pn reset button gt EFE H s 5555 l a lt es tt Ki DReeseseeseseseseseseesseesssseess D L 5 Pop P5232 P Sa connector EA N DEA EA N NED ne Se See ee EE S el P mm ee XE oe ooe power input from extemal AC adapter Figure 3 Power supply board connectors and control elements 2 4 Interfaces and Connectors 2 4 1 Software Streaming Software streaming allows to transfer large amount of data between the DSP and IEEE1394 with minimal overhead Data transfers are buffered by a FIFO so that the DSP can operate independent of the IEEE1394 timing Streaming transfers are unidirectional and must be set up for a particular direction before operation is started The maximum transfer rate for streaming is 32 768 000 byte s Software streaming is used for receiving image data from the connected cameras lsochronous streaming is explained in chapter 2 4 3 Programming is described in 1 and in 2 The distribution media contains an example that uses software streaming for capturing images from an IEEE1394 camera Date 17 February 2005 HARDWARE USER S GUIDE Doc no DCAM FC HG or sy S DCAM FRAME CAPTURE KIT Iss Re
24. gh speed serial interfaces They support multiple channels and a lot of different operation modes such as SPI MMC SD or AC97 Using this interface a wide range of peripherals such as codecs ADCs DACs or other DSP s can be directly connected to the UC1394a 1 Details of the McBSP interfaces are described in 1 On the carrier board port 0 and port 1 are directly routed to the respective micro line connectors McBSP2 is not externally available but has a loop back connection within the carrier board FPGA as shown in Figure 10 This loop back connection can be useful for testing McBSP configurations Please note The McBSP pins can also be configured and used as general purpose UO pins Doc no DCAM EC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 ky HARDWARE USER S GUIDE Date 17 February 2005 orsys Page 18 micro line connector E20 E21 E22 E23 E24 E25 Carrier board FPGA Figure 10 McBSP block diagram 2 4 8 USB Interface The USB interface is directly connected to the respective connector of the carrier board It can be used as described in 1 2 4 9 DC Interface The C signals are directly routed to the micro line connector They can be used as described in 1 ML Connector pin X5 SDA TX Table 4 CC connectors of the carrier board 2 4 10 Analog Inputs The analog inputs are directly connected to a 10 pin connector on the carrier board They can be used as described in 1
25. in assignments for the carrier board and the MOM sese 27 Table 14 Power pin assignments for the Carrier board sese eee eee eee 27 Table 15 Reset signal pin assignments for the carrier board and the MOM sees 27 Table 16 IEEE1394 cable power supply for the Carrier hoa 27 Table 17 Pinout for micro line connector A 28 Table 18 Pinout for micro line connector BR 29 Table 19 Pinout for micro line connector BR 30 Table 20 Pinout for micro line connector C L 31 Table 21 Pinout for micro line connector D 32 Table 22 Pinout for micro line connector E 33 Table 23 Pinout for micro line connector B 34 Table 24 Pinout for micro line connector X 34 Table 25 Pinout for the alternative RS 232 conpechor see eee eee eee 35 Table 26 Pinout for the analog REESEN ee eee eee eee tbe eege gegen 35 Table 27 Pinout for the JTAG connector agereechte geed 35 List of Figures Figure 1 DCAM frame capture kit block diagram EEN 7 Figure 2 UC1394a carrier board connectors and control elemente sese 8 Figure 3 Power supply board connectors and control elements sss eee ee eee eee eee eee eee eee 9 Figure 4 Block diagram of the peripheral interface ccccccceecessseeeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeneaes 10 Figure 5 Isochronous data recorded from the IEEE1394 bus with an analyzer ees 13 Figure 6 Isochronous packet assembly sampling at 100kHz 16bit packet size 40 bytes 14 Figure 7 IEEE139
26. is driven for a short period of about 1us in case of a software reset or watchdog reset Note for users of other micro line boards In contrast to micro line CPU modules the non inverted RESETOUT signal on pin D9 is not available on the carrier board If a high active reset is required an inverter must be implemented in the surrounding hardware 2 4 14 DSP JTAG interface The JTAG interface of the DSP is used for downloading and debugging DSP software All JTAG signals are available at the JTAG connector of the carrier board together with the FPGA JTAG signals Table 27 lists the pinning of the JTAG connector The DSP JTAG interface is used with a JTAG emulator such as the TI XDS series which can be connected to the carrier board by an adapter The JTAG adapter is included in the DCAM frame capture kit Usually the JTAG connector is used in conjunction with the JTAG adapter This JTAG adapter provides connectors which are compatible with standard development tools e the Texas Instruments emulator cables such as the XDS510 or compatible Date 17 February 2005 Ly HARDWARE USER S GUIDE Doc no DCAM FC HG iJ DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsysS Page 20 e the Xilinx parallel download cable FPGA JAG connector Hee DP JAG connector fits T emulator POD top view Figure 11 JTAG Adapter 2 4 15 FPGA JTAG interface The FPGA JTAG interface is used for e updating the carrier board FPGA code by
27. line a proprietary quasi standard for micro controller buses defined by Orsys 2 orsys HARDWARE USER S GUIDE DCAM FRAME CAPTURE KIT Date 17 February 2005 Doc no DCAM_FC_HG Iss Rev 1 00 Page 38 MSB n a Phy RAM SDRAM ROM SDK TBC TBD Tl UART most significant bit or byte not available IEEE1394 physical layer transceiver random access memory synchronous dynamic random access memory read only memory software development kit to be changed value not 100 tested and may change in future to be defined value is not yet specified Texas Instruments universal asynchronous receiver transmitter
28. ochronous and asynchronous streaming is only set up by the API and then performed by FPGA register accesses 2 4 4 1 Isochronous Streaming In isochronous streaming data is transferred in regular intervals called cycles In each cycle one data packet can be transferred The size of these data packets determines the maximum data bandwidth which can be calculated as max_bandwidth packet_size 8000 packets_per_second The cycle clock is 8kHz therefore packets get sent every 125 us Before transmission is started the transmitter reserves the necessary amount of bus bandwidth at a central location on the bus the isochronous resource manager This and the fact that isochronous packets have precedence over asynchronous packets guarantees that the bus provides enough capacity for the transfer Isochronous streaming is an excellent solution for transferring image data from a camera Isochronous transfers are multicast transfers which are identified by a channel so there is always Date 17 February 2005 Le HARDWARE USER S GUIDE Doc no DCAM FC HG M DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 13 one talker but there may be one or more listeners The transfer is typically done without any software overhead and is therefore quite fast Error detection is done at the receiver side Isochronous streaming is well suited for e large amounts of data e data distribution to several devices e data that occurs in regular inte
29. operation CS1 Since the write operation needs some pipeline steps to prepare the peripheral access the read operation appears before the write operation Such situations must be avoided as described in 1 Ly HARDWARE USER S GUIDE Jf DCAM Frame Capture KIT orsys Date 17 February 2005 Doc no DCAM EC HG Iss Rev 1 00 Page 24 Tek Bisi 200MS e l e 62 a l TA 1 66545 19 1 665ys xFOUT AOSTRE Ou 5 00V M 250ns Chi Tu 19 jan 2005 5 00 V 14 56 42 chi 5 00V Che Ch3 500v ME Figure 14 Waveforms generated by the periph_if example Ly HARDWARE USER S GUIDE Date 17 February 2005 d Doc no DCAM EC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 125 4 Technical Data 4 1 Connector Pinout Summary by Interface The tables in this chapter list the connector pin assignments for each interface separately The pin assignments show both pinouts for the carrier board and the UC1394a 1 MCM This allows easy migration from the DCAM frame capture kit to a standalone system ML Connector pin Bi B1 B3 B4 B o Q 5 v _ TE O QIO LG es N D22 D24 D25 D30 E2 Table 7 Connector pin assignments for the peripheral interface 7 Directly connected to the MCM Do not use HARDWARE USER S GUIDE Q Date 17 February 2005 Doc no DCAM_FC_HG Iss Rev 1 00 Page 26 DC
30. or e the alternative RS 232 connector separately 4 2 1 Connector A Connector A is used with the peripheral interface It carries the micro line data bus Interface peripheral interface Table 17 Pinout for micro line connector A Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG CJ DCAM FRAME CAPTURE KIT iss Rev 1 00 orsySs Page 29 4 2 2 Connector B Connector B carries the address lines of the peripheral interface and the signal ground micro line Signal Interface connector pin peripheral interface B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 SIGNAL_GND SIGNAL GND SIGNAL GND SIGNAL GND SIGNAL GND reserved power supply Table 18 Pinout for micro line connector B Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG NAS DCAM FRAME CAPTURE KIT iss Rev 1 00 orsys Page 20 4 2 3 Connector BB Connector BB is used for the FPGA UO pins micro line Interface connector pin BB 1 00 I O pins Signal ao O2 TC O3 ooo B BB5 f 4 BB6 O ee Be BB11 BB12 BBS EE Le eee L Se BBI8 BBi9 O Dee O ea D e BB23 BB24 BB25 BB26 BB27 BB29 BB30 L e BB32 Table 19 Pinout for micro line connector BB
31. refer to chapter 2 4 4 5 for details Date 17 February 2005 Ly HARDWARE USER S GUIDE Doc no DCAM FC HG iJ DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsySs Page 21 3 Application Examples The distribution media contains two kinds of application examples e DCAM specific examples e Examples from the DSP master BSP How to use the DCAM specific examples is described in 1 whereas the BSP examples are described in the subsequent sections The examples can either be downloaded to the kit by using a JTAG emulator or they can be programmed to the MCM s flash memory as described in 1 To download an application example to the MCM please proceed as follows Required items e adevelopment PC with the software listed below installed e Texas Instruments Code Composer Studio CCS V2 2x A run time limited version is downloadable from www ti com e aJTAG emulator e aterminal program such as Hyperterminal which is usually part of Windows distributions s a DCAM frame capture kit including a JTAG adapter all cables and a suitable power supply All application examples are provided as a CCS project The project has two available configurations Debug and Release Debug is the default configuration and should be used during development The Release configuration differs from Debug in two points s no debugging symbols are created the code is not suitable for source code debugging but better optimized e The Relea
32. rvals Figure 5 shows a part of an isochronous stream recorded with an analyzer The large blocks are isochronous packets with maximum size 4096 bytes The isochronous packets are preceded by a cycle start packet which indicates the start of a new cycle On the UC1394a 1 MCM packets are only transmitted when enough data is present in the FIFO Otherwise the corresponding cycle will be empty thus no packet is transmitted Figure 6 shows an example for this EA Firespy Recorder i E loj x File Search FireSpy Recorder View eze Tol Sl lge 134189640 TSR lala sane EE EES ine ow als af pid ld PP pt D 1 Packets View packet event size source destination label retry response code Packet Type Strean n PS CycleStart 20 E EE Streaming 4104 Show As Packet Stream DI Zae ee Si Sa Soy EDHE PS CycleStart 20 z EE Streaming 4104 Fields Layout PS CycleStart 20 s EE Streaming 4104 field value PS CycleStart 20 data length 4092 E Streaming 4104 tag 0 E CycleStart 20 channel ited oll tcode Stream Ceo at synchronisation 0 Gesin Se header CRC Ox99FSFE1F cea data 0 Ox09460947 EE CycleStart 20 data 1 0x09480949 E Streaming 4104 data 2 00344094B EE CycleStart 20 data 3 0x094C094D EE Streaming 4104 data 4 Ox094E094F E CycleStart 20 Streaming 4104 sl Acknowledge code none Z Figure 5 Isochronous data recorded from the IEEE1394 bus with an analyzer Da
33. se version of the module support library is used The Release configuration should be used for the final application after development is finished Further all example projects contain a final build step that creates a hex file This file can be programmed to flash memory as described in 1 3 1 Download procedure e connect the kit to the development PC using the JTAG emulator JTAG adapter and the RS 2332 cable power on the system start Code Composer Studio select the Load GEL command from the File menu locate uc1394a 1_master gel from the GEL folder on the distribution media and open it select the Initialization gt CPU_reset_and_init_144Mhz command from the GEL menu select the Load Program command from the File menu locate one of the application examples from the examples folder on the distribution media and open it e g toggle_led out e select the Run command from the Debug menu Please note the application examples do not use the usual printf function Instead where necessary output is sent over the UART interface using 115200 baud and RTS CTS handshake This allows to store the examples in flash memory and then to execute them without the JTAG emulator HARDWARE USER S GUIDE Date 17 February 2005 Ly E Doc no DCAM EC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 l orsys Page 22 3 2 LED Control toggle_led This is the most basic application example It initializes
34. ss Rev 1 00 orsys Page 8 2 1 UC1394a 1 MCM The UC1394a 1 MCM is the heart of the DCAM frame capture kit It provides all of the interfaces shown in Figure 1 and a complete hardware environment for user applications After software development is finished the UC1394a 1 can be easily integrated into a customized hardware environment Its small size and low cost make it an ideal solution for end product usage Further the implementation as a multi chip module MCM allows similar handling as of integrated circuits therefore mass production is supported The MCM is equipped with the DSP master board support package BSP This BSP provides software driven access to IEEE1394 streaming data and a peripheral interface to connect a wide range of peripherals The DSP master BSP is described in 2 2 2 UC1394a Carrier Board The carrier board turns the MCM into a micro line module It provides most of the available interfaces on standard 0 1 inch spaced connectors so that prototypes can easily be built Other connectors are available for use with dedicated cables The carrier board provides the following features e Regulated 3 3 V supply for the MCM e A level converter that converts the 3 3 V LVTTL signal levels of the MCM UART interface to RS 232 levels Two 400 Mbps IEEE1394 ports with standard 6 pin connectors micro line connector for easy connection of external hardware A DIP switch for controlling the configuration inputs
35. starting at zero which is the least significant bit z Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG J DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 6 Example CFG 4 0 identifies a group of five signals where CFGO is the least significant bit and CFG4 is the most significant bit If necessary numbers are represented with a suffix that specifies their base Example 12AB46 is a hexadecimal number base 16 hexadecimal and is equal to 477940 The bit fields of a register are displayed with the most significant bit to the left Below each bit field is a description of its read write accessibility and its default value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C D E F G H J K L N O r w Q r w 0 r w 0 r w 0 r w 0 r w 0 r w 0102 r 0 r wc 0 w r w 0 rc 0 r w 0 r w 0 accessibility and default value legend r bit is readable rc this bit is cleared after a read rw bit is readable and writeable reading yields the previously written value unless otherwise specified W bit is writeable read value is undefined wc writing a 1 to this bit clears it w 0 bitis write only reading always yields 0 0 default value 1 4 Trademarks TI Code Composer DSP BIOS and TMS320C5000 are registered trademarks of Texas Instruments Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
36. te 17 February 2005 S HARDWARE USER S GUIDE Doc no DCAM FC HG LJ DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsys Page 14 one isochronous packet 20 samples one 16 bit sample empty cycles UC1394a 1 Peripheral IEEE1394 i i S interface PSP interface S a H RH l 10us ap gt 125us 7 one isochronous Transfer direction cycle Figure 6 Isochronous packet assembly sampling at 100kHz 16bit packet size 40 bytes 2 4 4 2 Asynchronous Streaming Asynchronous streaming is similar to isochronous streaming Asynchronous streaming uses the same data packets as an isochronous transfer Packets may be sent anytime provided that the bus is free Bus bandwidth is not guaranteed here so the transmission of a packet may be blocked by other transfers on the bus At the receiver side it makes no difference whether isochronous or asynchronous streaming is used Asynchronous streaming should be used when latency requirements don t allow isochronous streaming and bus bandwidth can be guaranteed by system design 2 4 4 3 Asynchronous Transactions Asynchronous transactions are handled by the DCAM API for control of the connected cameras Each data packet that is sent receives a response from the addressed device Asynchronous transfers can occur at any time provided that the bus is free They are point to point transfers so the originator of the transfer must know who to talk to An asynchronous transfer consists of
37. these pins is used as outputs by the carrier board the other part is used as inputs e configuration inputs e external flag XF output of the DSP If further I O pins are required unused McBSP interfaces can also be configured as I O pins Doc no DCAM EC HG DCAM FRAME CAPTURE KIT Iss Rev 1 00 ky HARDWARE USER S GUIDE Date 17 February 2005 orsys Page 17 green red LED LED E N EH FPGA Carrier board micro line UO pins FPGA connector 0 i BB1 R BB2 BB3 BB4 BBS DSP XF output Figure 9 I O pin block diagram Notes for the carrier board environment 1 The FPGA UO pins are routed through the carrier board FPGA Their direction is therefore fixed and can t be changed Application software must set up the FPGA UO pins for the proper direction before using them 2 The CFG inputs are connected to the carrier board s DIP switch and are not externally available Application software can use the CFG inputs for basic configuration of operation 3 I O 4 is also directly connected the micro line pin E27 Please use always 1 04 with micro line pin BB5 to avoid signal contention 4 The green and a red carrier board LED are controlled by I O0 and 1 01 respectively Behavior of the I O pins in stand alone environment without the carrier board and I O pin programming is described in 1 2 4 7 McBSP Interfaces The DSP of the UC1394a 1 provides 3 McBSP ports These interfaces are hi
38. v 1 00 Page 10 2 4 2 micro line Peripheral Interface The micro line peripheral interface allows to connect micro line peripheral boards as well as a wide range of user defined peripherals The micro line peripheral interface is implemented as a parallel bus interface with asynchronous control signals All signals of the peripheral interface of the MCM are routed to the micro line connectors through the carrier board FPGA Additionally some signals are directly routed to the C and E connectors However user defined hardware should only use the default micro line signals routed through the FPGA in order to be compatible with other micro line CPU boards Further the directly connected data lines on the C connector are used at system startup for booting the carrier board FPGA Peripheral Carrier Board interface EE FPGA Figure 4 Block diagram of the peripheral interface micro line connector B1 8 A1 16 D10 16 D22 25 30 D17 18 C1 16 E1 3 5 6 A detailed functional description of the peripheral interface can be found in 1 The standard micro line signals are listed in Table 1 whereas the directly connected signals are listed in Table 2 Date 17 February 2005 LN HARDWARE USER S GUIDE Doc no DCAM FC HG TJ DCAM FRAME CAPTURE KIT Iss Rev 1 00 orsyS Page 11 ADDRO Ti address lines Be ADDR4 data lines DATA9 DATAI
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