University Program Design Laboratory Package User Guide
Contents
1. check the device count JTAG ID code and total instruction length of the JTAG chain A message just above the Detect JTAG Chain Info button reports the information detected by the ByteBlasterMV cable You must manually verify that this message matches the information in the Device Names amp Programming File Names box Click Save JCF to save the current settings to a JCF for future use Type the name of the file in the File Name box and then select the desired directory in the Directories box in the Save JCF dialog box Click OK Click OK to save your changes Click Configure in the MAX PLUS II Programmer Altera Corporation Altera Corporation University Program Design Laboratory Package User Guide Configure Program Both Devices This section describes the procedures for configuring programming both the FLEX 10K and EPM7128S devices in a JTAG chain i e how to set the on board jumpers connect the ByteBlasterMV download cable and set options in the MAX PLUS II software Setting the On Board Jumpers for Configuring Programming Both Devices To configure and program the FLEX 10K and EPM71285 devices in a multi device JTAG chain set the jumpers TDI TDO DEVICE and BOARD as shown in Figure 9 Figure 9 Jumper Settings for Configuring Programming Both Devices TDO DEVICE BOARD Connecting the ByteBlasterMV Download Cable for Configuring amp Programming Both Devices Attach the ByteBlasterMV cable directly to the PC2. devices The MAX PLUS II University software can be freely distributed to students for installation on their personal computers and provides instant access to online help Ls For information on how to install the MAX PLUS II University software on your computer see Software Installation on page ie University Program Design Laboratory Package User Guide UP1 amp UP2 Education Boards The UP1 and UP2 Education Boards are stand alone experiment boards based on a FLEX 10K device and include a MAX 7000 device When used with the MAX PLUS II University software the boards provide a superior platform for learning digital logic design using industry standard development tools and PLDs The boards are designed to meet the needs of instructors and students in a laboratory environment The UP1 and UP2 Education Boards support both look up table LUT based and product term based architectures The EPF10K70 and EPF10K20 devices can be configured in system with either the ByteBlasterMV download cable or an EPC1 configuration device Additional download cables can be purchased separately The EPM71285S device can be programmed in system with the ByteBlasterMV download cable EPF10K70 Device The EPF10K70 device is based on SRAM technology It is available in a 240 pin RQFP package and has 3 744 logic elements LEs and nine embedded array blocks EABs Each LE consists of a four input LUT a programmable flipflop and dedicated sign
3. s parallel port and to the JTAG_IN connector on the UP Education Board For more information on setting up the ByteBlasterMV cable see the ByteBlasterMV Parallel Port Download Cable Data Sheet Setting the JTAG Options in the MAX PLUS II Software for Configuring amp Programming Both Devices The following steps describe how to use the MAX PLUS II software to configure and program both devices in a multi device JTAG chain For more information on how to program or configure a device see the MAX PLUS II Help 1 Turn on the Multi Device JTAG Chain command JTAG menu 2 Choose Multi Device JTAG Chain Setup JTAG menu 3 Select the first target device name in the Device Name list in the Multi Device JTAG Chain Setup dialog box 23 University Program Design Laboratory Package User Guide 4 10 Type the name of the programming file for the device listed in the Device Name box in the Programming File Names box The Select Programming File button can also be used to browse your computer s directory structure to locate the appropriate programming file Click Add to add the device and associated programming file to the Device Names amp Programming File Names box The number to the left of the device name shows the device s order in the JTAG chain The device s associated programming file is displayed on the same line as the device name If no programming file is associated with a device lt none gt is displayed
4. Cable Data Sheet 21 University Program Design Laboratory Package User Guide 22 Setting the JTAG Options in the MAX PLUS II Software for EPF10K70 or EPF10K20 Configuration The following steps describe how to use the MAX PLUS II software to configure the EPF10K70 or EPF10K20 device in a JTAG chain For more information on how to configure a device see the MAX PLUS II Help 1 Turn on the Multi Device JTAG Chain command JTAG menu in the MAX PLUS II Programmer to configure the EPF10K70 or EPF10K20 devices Follow this step even if you are only programming one device Choose Multi Device JTAG Chain Setup JTAG menu Select EPF10K70 or EPF10K20 in the Device Name list in the Multi Device JTAG Chain Setup dialog box Type the name of the programming file for the EPF10K70 or EPF10K20 device in the Programming File Name box You can also use the Select Programming File button to browse your computer s directory structure to locate the appropriate programming file Click Add to add the device and associated programming file to the Device Names amp Programming File Names box The number to the left of the device name shows the order of the device in the JTAG chain The device s associated programming file is displayed on the same line as the device name If no programming file is associated with a device lt none gt is displayed next to the device name Click Detect JTAG Chain Info to have the ByteBlasterMV cable
5. N OE RYA University Program Design Laboratory Package October 2001 ver 2 0 Introduction Altera Corporation A UG UP1 02 0 User Guide The University Program UP Design Laboratory Package was designed to meet the needs of universities teaching digital logic design with state of the art development tools and programmable logic devices PLDs The package provides all of the necessary tools for creating and implementing digital logic designs including the following features MAX PLUS II University development software UP Education Board EPF10K20 device for the UP1 board or an EPF10K70 device for the UP2 board in a 240 pin power quad flat pack ROFP package EPM71285 device for the UP1 and UP2 boards in an 84 pin plastic J lead chip carrier PLCC package E ByteBlasterMV parallel port download cable MAX PLUS II University Software The MAX PLUS II University software contains many of the features of the commercial version of the MAX PLUS II software including a completely integrated design flow and an intuitive graphical user interface This software supports schematic capture and text based hardware description language HDL design entry including Verilog HDL VHDL and the Altera Hardware Description Language AHDL It also provides design programming compilation and verification support for all devices supported by the MAX PLUS II BASELINE software including the EPM7128S5 EPF10K20 and EPF10K70
6. O 9 2 O DSO 2 ae O 3 O DO 3 O D10 4 DEO 4 D140 5 O DBO 5 O D110 6 D7O 6 D150 7 D4O 7 D120 8 D8 O 8 O D160 MAX_DIGIT Display MAX_DIGIT is a dual digit seven segment display connected directly to the EPM71285 device Each LED segment of the display can be illuminated by driving the connected EPM7128S device I O pin with a logic 0 Figure 4 shows the name of each segment Figure 4 Display Segment Name Digit 1 Digit 2 a Decimal Point University Program Design Laboratory Package User Guide Table 4 lists the pin assignments for each segment Table 4 MAX_DIGIT Segment I O Connections Display Segment Pin for 1 Pin for Digit 2 Decimal point MAX_EXPANSION MAX_EXPANSION is a dual row of 0 1 inch spaced holes for accessing signal I O pins and global signals on the EPM71285 device power and ground Figure 5 shows the numbering convention for the holes Figure 5 MAX_EXPANSION Numbering Convention UP Education Board 20OA8D 2 w lt ou gt lt Lu gt lt lt x 0 2 4 6 JA DTE RA o EPM7128S 10 Altera Corporation University Program Design Laboratory Package User Guide Table 5 lists the signal names and the EPM71285 device pins connected to each hole Table 5 MAX_EXPANSION Signal Names amp Device Connections Hole Number Hole Number NoGomect 8 woconen Altera Corporation 11 Universit
7. Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services C ight 2001 Altera C tion All right d opyrig era Corporation rights reserve ES EN 180 900 Altera Corporation
8. EPM71285 device features a socket mounted 84 pin plastic j lead chip carrier PLCC package and has 128 macrocells Each macrocell has a programmable AND fixed OR array as well as a configurable register with independently programmable clock clock enable clear and preset functions With a capacity of 2 500 gates and a simple architecture the EPM71285 device is ideal for introductory designs as well as larger combinatorial and sequential logic functions For more information on MAX 7000 devices go to the MAX 7000 Programmable Logic Device Family Data Sheet ByteBlasterMV Parallel Port Download Cable Designs can be easily and quickly downloaded into the UP1 and UP2 Education Boards using the ByteBlasterMV download cable which is a hardware interface to a standard parallel port This cable sends programming or configuration data between the MAX PLUS II University software and the UP Education Boards Because design changes are downloaded directly to the devices on the board prototyping is easy and multiple design iterations can be accomplished in quick succession For more information on the ByteBlasterMV download cable see the ByteBlasterMV Parallel Port Download Cable Data Sheet University Program Design Laboratory Package User Guide UP Education Board Description The UP1 and UP2 Education Boards contain the features described in this section Figure 1 shows a block diagram of the UP Education Board Figure 1 UP Educa
9. a Sheet Setting the JTAG Options in the MAX PLUS II Software for EPM7128S Device Programming The following steps describe how to use the MAX PLUS II software to program the EPM71285 device in a JTAG chain For more information on how to use the MAX PLUS II software see the MAX PLUS II Help 1 Turn on the Multi Device JTAG Chain command JTAG menu in the MAX PLUS IT Programmer to program a device Follow this procedure even if you are only programming one device 2 Choose Multi Device JTAG Chain Setup JTAG menu 3 Select EPM7128S in the Device Name list in the Multi Device JTAG Chain Setup dialog box 4 Type the name of the programming file for the EPM71285 device in the Programming File Name box You can use the Select Programming File button to browse a computer s directory structure to locate the appropriate programming file 5 Click Add to add the device and associated programming file to the Device Names amp Programming File Names box The number to the left of the device name shows the order of the device in the JTAG chain The device s associated programming file is displayed on the same line as the device name If no programming file is associated with a device lt none gt is displayed next to the device name Altera Corporation Altera Corporation University Program Design Laboratory Package User Guide 6 Click Detect JTAG Chain Info to have the ByteBlasterMV cable check the device count JTAG ID c
10. al paths for carry and cascade functions Each EAB provides 2 048 bits of memory which can be used to create RAM ROM or first in first out FIFO functions EABs can also implement logic functions such as multipliers microcontrollers state machines and digital signal processing DSP functions With 70 000 typical gates the EPF10K70 device is ideal for intermediate to advanced digital design courses including computer architecture communications and DSP applications EPF10K20 Device The EPF10K20 device is based on reconfigurable SRAM elements The EPF10K20 device is available in a 240 pin ROFP package and has 1 152 LEs and six EABs Each LE consists of a four input LUT a programmable flipflop and dedicated signal paths for carry and cascade functions Each EAB provides 2 048 bits of memory which can be used to create RAM ROM or FIFO functions The EABs can implement logic functions such as multipliers microcontrollers state machines and DSP functions With 20 000 typical gates the EPF10K20 device is ideal for introductory digital design courses For more information on FLEX 10K devices see the FLEX 10K Embedded Programmable Logic Family Data Sheet Altera Corporation Altera Corporation University Program Design Laboratory Package User Guide EPM7128S Device The EPM71285 device a member of the high density high performance MAX 7000S family is based on erasable programmable read only memory EEPROM elements The
11. am Design Laboratory Package User Guide Table 11 FLEX_EXPAN_B Signal Names amp Device Connections Hole Number Signal Pin Hole Number 2 No Connect D1I2 92 DEV_0OE 213 NO Te ee ee ee ee ee ee ee ee ee i O11 O11 O1 C1 BR HR HR Bl OI oO NM OINI FIN OI INT AINI OINI BRIM ory 01 oqr A Hh AJAI BR OJOJ olojo AINO OD R M O O O R M O Hole Number Cs _s O N O Altera Corporation 17 University Program Design Laboratory Package User Guide Table 12 FLEX_EXPAN_C Signal Names amp Device Connections Sofiware This section describes how to install the MAX PLUS II University software for the Windows 98 2000 and Windows NT 4 0 operating After installation students can register to obtain an authorization code via the Altera world wide web site at the following URL http www altera com support licensing lic university html 18 Altera Corporation University Program Design Laboratory Package User Guide FOr complete installation instructions refer to the read me file on the MAX PLUS II University CD ROM or see the MAX PLUS II Getting Started manual Windows 98 2000 amp Windows NT 4 0 Follow the below steps to install the MAX PLUS II University software onto a PC 1 Insert the MAX PLUS II University CD ROM into the CD ROM drive 2 Choose Run Start menu 3 Type lt CD ROM drive gt mp2_101se exe and click OK The setup wizard will guide you thr
12. aveforms for the color information with respect to the horizontal and vertical synchronization signals Figure 13 Horizontal Refresh Cycle RED GREEN BLUE C gt lt D gt lt E gt HORIZ_SYNC k B A gt 31 77 us 3 77 us 1 89 us 25 17 us 0 94 us Altera Corporation 27 University Program Design Laboratory Package User Guide Figure 14 Vertical Refresh Cycle 480 Horizontal Refresh Cycles enm_ RED GREEN BLUE T j lt Q k R gt i S gt VERT_SYNC KP O gt The frequency of operation and the number of pixels that the monitor must update determines the time required to update each pixel and the time required to update the whole screen The following equations roughly calculate the time required for the monitor to perform all of its functions T 1 fc k 40 ns pixel Trow A B C D E Tyixe X 640 pixels row guard bands 31 77 us pixel p 8 Tocreen O P Q R4 5 Trow X 480 rows guard bands 16 6 ms Where Tpixe Time required to update a pixel fck 25 175 MHz Trow Time required to update one row aes Time required to update the screen B C E Guard bands P Q S Guard bands The monitor writes to the screen by sending red green blue horizontal synchronization and vertical synchronization signals when the screen is at the expected location Once the timing of the horizontal and vertical synchr
13. ch pixel can display various colors depending on the state of the red green and blue signals Figure 12 VGA Monitor lt q 640 pixels ______ _ 480 pixels 640 480 Each VGA monitor has an internal clock that determines when each pixel is updated This clock operates at the VGA specified frequency of 25 175 MHz The monitor refreshes the screen in a prescribed manner that is partially controlled by the horizontal and vertical synchronization signals The monitor starts each refresh cycle by updating the pixel in the top left hand corner of the screen which can be treated as the origin of an X Y plane see Figure 12 After the first pixel is refreshed the monitor refreshes the remaining pixels in the row When the monitor receives a pulse on the horizontal synchronization it refreshes the next row of pixels This process is repeated until the monitor reaches the bottom of the screen When the monitor reaches the bottom of the screen the vertical synchronization pulses causing the monitor to begin refreshing pixels at the top of the screen i e at 0 0 VGA Timing For the VGA monitor to work properly it must receive data at specific times with specific pulses Horizontal and vertical synchronization pulses must occur at specified times to synchronize the monitor while it is Altera Corporation University Program Design Laboratory Package User Guide receiving color data Figures 13 and 14 show the timing w
14. g to the right is positive moving to the left is negative moving up is positive and moving down is negative The magnitude of the movement is a function of the mouse s rate of movement The faster the mouse moves the greater the magnitude Altera Corporation 29 University Program Design Laboratory Package User Guide NOTE PAo 101 Innovation Drive San Jose CA 95134 408 544 7000 http www altera com University Program university altera com Literature Services 888 3 ALTERA lit_req altera com 30 ge we Printed on Recycled Paper Altera MAX MAX PLUS MAX PLUS II MAX 7000S EPM7128S FLEX FLEX 10K EPF10K20 EPF10K70 ByteBlasterMV EPC1 and AHDL are trademarks and or service marks of Altera Corporation in the United States and other countries Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product NSAI or service described herein except as expressly agreed to in writing by Altera
15. he UP Education Boards The boards provide power and ground to the ByteBlasterMV download cable Data is shifted into the devices via the TDI pin and shifted out of the devices via the TDO pin Table 1 identifies the JTAG_IN pin names when the ByteBlasterMV is operating in Joint Test Action Group JTAG mode Table 1 JTAG_IN 10 Pin Header Pin Outs JTAG GND Jumpers The UP Education Boards have four three pin jumpers TDI TDO DEVICE and BOARD that set the JTAG configuration The JTAG chain can be set for a variety of configurations i e to program only the EPM71285 device to configure only the FLEX 10K device to configure and program both devices or to connect multiple UP Education Boards together Figure 2 shows the positions of the three connectors C1 C2 and C3 on each of the four jumpers University Program Design Laboratory Package User Guide Figure 2 Position of C1 C2 amp C3 Connectors Pas Tel cal Table 2 defines the settings for each configuration Table 2 JTAG renee Settings only Configure FLEX 10K C2 amp C3 C2 amp C3 C1 amp C2 C1 amp C2 device only Program configure both C2 amp C3 C1 amp C2 C2 amp C3 C1 amp C2 devices 1 Connect multiple boards C2 amp C3 OPEN C2 amp C3 together 2 Notes to Table 2 1 The first device in the JTAG chain is the FLEX 10K device and the second device is the EPM7128S device 2 The first device in the JTAG chain is the FLEX 10K dev
16. ice and the second device is the EPM7128S device The last board in the chain must be set for a single board configuration i e for programming only the EPM71285 device configuring only the FLEX 10K device or configuring programming both devices The last board cannot be set for connecting multiple boards together During configuration the green CONF_D LED will turn off and the green TCK LED will modulate to indicate that data is transferring After the device has successfully configured the CONF_D LED will illuminate Ls For information on how to program or configure EPF10K20 EPF10K70 or EPM71285 devices see Programming or Configuring Devices on page 19 6 Altera Corporation Altera Corporation University Program Design Laboratory Package User Guide EPM7128S Device The UP1 and UP2 Education Boards provide the following resources for the EPM71285 device Socket mounted 84 pin PLCC package Signal pins that are accessible via female headers JTAG chain connection for the ByteBlasterMV cable Two momentary push button switches Two octal dual inline package DIP switches 16 LEDs Dual digit seven segment display On board oscillator 25 175 MHz Expansion port with 42 I O pins and the dedicated global CLR OE1 and OE2 GCLK2 pins Pins from the EPM71285 device are not pre assigned to switches and LEDs but are instead connected to female headers With direct access to the pins students can concentrate on desig
17. ing the connected FLEX 10K device I O pin with a logic 0 See Figure 4 on page 9 for the name of each segment Table 7 lists the pin assignment for each segment Table 7 FLEX_DIGIT Segment I O Connections Display Segment Decimal point VGA Interface The VGA interface allows the FLEX 10K device to control an external video monitor This interface is composed of a simple diode resistor network and a 15 pin D sub connector labeled VGA where the monitor can plug into the boards The diode resistor network and D sub connector are designed to generate voltages that conform to the VGA standard Information about the color row and column indexing of the screen is sent from the FLEX 10K device to the monitor via five signals Three VGA signals are red green and blue while the other two signals are horizontal and vertical synchronization Manipulating these signals allows images to be written to the monitor s screen Ls See VGA Driver Operation on page 26 for details on how the VGA interface operates Table 8 lists the D sub connector and the FLEX 10K device connections Altera Corporation 13 University Program Design Laboratory Package User Guide 14 Table 8 D Sub Connections D Sub Connector Pin FLEX 10K Pin i 37 RED A No Connect Mouse Connector The mouse interface is a six pin mini DIN connector that allows the FLEX 10K device to receive data from a PS 2 mouse or a PS 2 keyboard The board pro
18. lti device JTAG chain set the jumpers TDI TDO DEVICE and BOARD for all boards except the last board in the chain as shown in Figure 10 Figure 10 Jumper es for All Boards Except the Last Board in the Chain TDO DEVICE BOARD The last UP Education Board in the chain can configure and program one or both devices However the BOARD jumper must be set as shown in Figure 11 Figure 11 Jumper Settings for the Last Board in the Chain The TDI TDO and DEVICE settings depend on which configuration is used TDO DEVICE BOARD Connecting the ByteBlasterMV Download Cable for Connecting Multiple UP Education Boards Together Attach the ByteBlasterMV cable directly to your PC s parallel port and to the JTAG_IN connector on the UP Education Board For more information on setting up the ByteBlasterMV cable see the ByteBlasterMV Parallel Port Download Cable Data Sheet 25 University Program Design Laboratory Package User Guide VGA Driver Operation 26 Setting the JTAG Options in the MAX PLUS II Software for Connecting Multiple UP Education Boards For information on how to set the JTAG options in the MAX PLUS II software see Setting the JTAG Options in the MAX PLUS II Software for Configuring amp Programming Both Devices on page 23 A standard VGA monitor consists of a grid of pixels that can be divided into rows and columns A VGA monitor contains at least 480 rows with 640 pixels per row as shown in Figure 12 Ea
19. n fundamentals and learn about the programmability of I O pins and PLDs After successfully compiling and verifying a design with the MAX PLUS II University software students can easily connect the assigned I O pins to the switches and LEDs using a common hook up wire Students can then download their design into the device and compare their design s simulation to the actual hardware implementation EPM7128S Prototyping Headers The EPM71285 prototyping headers are female headers that surround the device and provide access to the device s signal pins The 21 pins on each side of the 84 pin PLCC package connect to one of the 22 pin dual row Q 1 inch female headers The pin numbers for the EPM7128S device are printed on the UP1 and UP2 Education Boards an X indicates an unassigned pin Table 3 lists the pin numbers for the four female headers P1 P2 P3 and P4 The power ground and JTAG signal pins are not accessible through these female headers University Program Design Laboratory Package User Guide Table 3 Pin Numbers for Each Prototyping Header Note 1 Note to Table 3 Inside refers to the row of female headers closest to the device outside refers to the row of female headers furthest 1 from the device MAX_PB1 amp MAX_PB2 Push Buttons MAX_PB1 and MAX_PB2 are two push buttons that provide active low signals and are pulled up through 10 KQ resistors Connections to these signals are easily made by inserti
20. next to the device name Repeat steps 3 through 5 to add information for each device in the JTAG chain Click Detect JTAG Chain Info to have the ByteBlasterMV cable check the device count JTAG ID code and total instruction length of the multi device JTAG chain A message just above the Detect JTAG Chain Info button reports the information detected by the ByteBlasterMV cable You must manually verify that this message matches the information in the Device Names amp Programming File Names box Click Save JCF to save the current settings to a JCF for future use Type the name of the file in the File Name box and then select the desired directory in the Directories box Click OK Click OK to save the changes Click Configure in the MAX PLUS II Programmer to configure all FLEX 10K devices in the JTAG chain Then click Program to program all EPM71285 devices in the JTAG chain Connect Multiple UP Education Boards Together in a Chain This section describes the procedures for connecting multiple UP Education Boards together i e how to set the on board jumpers connect the ByteBlasterMV download cable and set options in the MAX PLUS I software 24 Altera Corporation Altera Corporation University Program Design Laboratory Package User Guide Setting the On Board Jumpers for Connecting Multiple UP Education Boards Together To configure program EPM71285S and FLEX 10K devices on multiple UP Education Boards connected in a mu
21. ng one end of the hook up wire into the push button female header The other end of the hook up wire should be inserted into the appropriate female header assigned to the I O pin of the EPM71285 device MAX_SW1 amp MAX_SW2 Switches MAX_SW1 and MAX_SW2 each contain eight switches that provide logic level signals These switches are pulled up through 10 KQ resistors Connections to these signals are made by inserting one end of the hook up wire into the female header aligned with the appropriate switch Insert the other end of the hook up wire into the appropriate female header assigned to the I O pin of the EPM71285 device The switch output is set to logic 1 when the switch is open and set to logic 0 when the switch is closed Altera Corporation University Program Design Laboratory Package User Guide Altera Corporation D1 through D16 LEDs The UP Education Boards contain 16 LEDs that are pulled up with a 330 Q resistor An LED is illuminated when a logic 0 is applied to the female header associated with the LED LEDs D1 through D8 are connected in the same sequence to the female headers i e D1 is connected to position 1 and D2 is connected to position 2 etc LEDs D9 through D16 are connected in the same sequence to the female headers i e D9 is connected to position 1 and D10 is connected to position 2 etc See Figure 3 Figure 3 LED Positions Female Female Header Header Position LEDs Position LEDs 1 O D1O 1
22. ode and total instruction length of the JTAG chain A message just above the Detect JTAG Chain Info button reports the information detected by the ByteBlasterMV cable This message must be manually verified to match the information in the Device Names amp Programming File Names box 7 Click Save JCF In the Save JCF dialog box type the name of the file in the File Name box and then select the desired directory in the Directories box to save the current settings to a JTAG Chain File jcf for future use Click OK 8 Click OK to save changes 9 Click Program in the MAX PLUS II Programmer EPF10K70 amp EPF10K20 Configuration This section describes the procedures for configuring only the EPF10K70 or EPF10K20 devices i e how to set the on board jumpers connect the ByteBlasterMV download cable and set options in the MAX PLUS II software Setting the On Board Jumpers for EPF10K70 or EPF10K20 Configuration To configure only the EPF10K70 or EPF10K20 device in a JTAG chain set the jumpers TDI TDO DEVICE and BOARD as shown in Figure 8 Figure amp Jumper at for Configuring Only the FLEX 10K Device TDO DEVICE BOARD Connecting the ByteBlasterMV Download Cable for EPF10K70 or EPF10K20 Configuration Attach the ByteBlasterMV cable directly to the PC s parallel port and to the JTAG IN connector on the UP Education Board For more information on setting up the ByteBlasterMV cable see the ByteBlasterMV Parallel Port Download
23. onization signals is accurate the monitor only needs to keep track of the current location so it can send the correct color data to the pixel 28 Altera Corporation University Program Design Laboratory Package User Guide Mouse You can connect a mouse to the UP Education Board via the 6 pin mini DIN connector The data is sent using a synchronous serial protocol Interface and the transmission is controlled by the CLK and DATA signals During Op eration en CLK is at logic 1 and DATA can be either logic 0 or ogic 1 Each transmission contains one start bit eight data bits odd parity and one stop bit Data transmission starts from the least significant bit LSB i e the sequence of transmission is start bit DATAO through DATA7 parity and stop bit Start bits are logic 0 and stop bits are logic 1 Each clock period is 30 to 50 psec the data transition to the falling edge of the clock is 5 to 25 psec Table 13 shows the data packet format Table 13 Data Packet Format Note 1 Packet D7 Number Pot tf wef x s s 1 0 R E Note to Table 13 1 Where L Left button state 1 left mouse button is pressed down R Right button state 1 right mouse button is pressed down X0 X7 Movement in X direction Y0 Y7 Movement in Y direction XS YS Movement data sign 1 negative XV YV Movement data overflow 1 overflow has occurred The mouse operates on a Cartesian coordinate system i e movin
24. ough the installation procedure Prog rammin g Programming or configuring the devices on the UP Education Boards requires setting the on board jumpers and the JTAG programming or Confi guring options in the MAX PLUS II software and connecting the ByteBlasterMV Devices download cable to the PC s parallel port and to the JTAG_IN connector on the UP Education Boards This section describes how to set these options Program only the EPM71285 device Configure only the EPF10K20 or EPF20K70 device Configure program both devices Connect multiple UP Education Boards together in a chain EPM7128S Programming This section describes the procedures for programming only EPM7128S devices i e how to set the on board jumpers connect the ByteBlasterMV download cable and set options in the MAX PLUS II software Setting the On Board Jumpers for EPM7128S Programming To program only the EPM71285 device in a JTAG chain set the jumpers TDI TDO DEVICE and BOARD as shown in Figure 7 Altera Corporation 19 University Program Design Laboratory Package User Guide 20 Figure 7 Jumper an for Programming Only the EPM7128S Device TDO DEVICE BOARD Connecting the ByteBlasterMV Download Cable for EPM7128S Programming Attach the ByteBlasterMV cable directly to the PC s parallel port and to the JTAG_IN connector on the board For more information on setting up the ByteBlasterMV cable go to the ByteBlasterMV Parallel Port Download Cable Dat
25. tion Board Block Diagram gJ A Z O MAX_EXPANSION Z EPF10K20 or EPF10K70 OOOO0O000 OOOO0O000 OJO OjO O O OjO O O OjO O O OjO FLEX_SWITCH FLEX_EXPAN O olD4 0O O ee DC_IN amp RAW Power Input The DC_IN power input accepts a 2 5 mm x 5 55 mm female connector The acceptable DC input is 7 to 9 V at a minimum of 350 mA The RAW power input consists of two holes for connecting an unregulated power source The hole marked with a plus sign is the positive input the hole marked with a minus sign is board common On Board Voltage Regulator The on board voltage regulator an LM340T regulates the DC positive input at 5 V The DC input consists of two holes for connecting a 5 V DC regulated power source The hole marked with a plus sign is the positive input the hole marked with a minus sign is board common A green light emitting diode LED labeled POWER is illuminated when current is flowing from the 5 V DC regulated power source Altera Corporation Altera Corporation University Program Design Laboratory Package User Guide Oscillator The UP Education Boards contain a 25 175 MHz crystal oscillator The output of the oscillator drives a global clock input on the EPM71285 device pin 83 and a global clock input on the FLEX 10K device pin 91 JTAG_IN Header The 10 pin female plug on the ByteBlasterMV download cable connects with the JTAG_IN 10 pin male header on t
26. vides power and ground to the attached mouse or keyboard The FLEX 10K device outputs the DATA _CLOCK signal to the mouse and inputs the data signal from the mouse Table 9 lists the signal names and the mini DIN and FLEX 10K pin connections Ls See Mouse Interface Operation on page 29 for details on how the mouse interface operates Table 9 Mouse Connections Mouse Signal FLEX 10K Pin 30 ee Toan FLEX_EXPAN_A FLEX_EXPAN_B amp FLEX_EXPAN_C FLEX EXPAN A FLEX EXPAN B and FLEX EXPAN C are dual rows of 0 1 inch spaced holes for accessing signal I O pins and global signals on the FLEX 10K device power and ground Figure 6 shows the numbering convention for these holes Altera Corporation University Program Design Laboratory Package User Guide Altera Corporation Figure 6 FLEX_EXPAN_A FLEX_EXPAN_B amp FLEX_EXPAN_C Numbering Convention UP Education Board 1513119 7531 oo0oo0oo0oo0oo0o0o0 eee 20 0 OC0O000 161412108 6 4 2 FLEX _EXPAN_C N_B eee NAO FLEX_EXPAN_A 24 6 810121416 OOCO0000 HOOOOOC OCs LLS 13579111315 FLEX_EXPAN_ MAOO Tables 10 through 12 list the signal name and the FLEX 10K device pin connected to each hole 15 University Program Design Laboratory Package User Guide Table 10 FLEX_EXPAN_A Signal Names amp Device Connections Hole Number auni Hole Number 1 gt s v o o r Neconmest s o ee a 16 Altera Corporation University Progr
27. y Program Design Laboratory Package User Guide 12 FLEX 10K Device The UP1 and UP2 Education Boards provide the following resources for the FLEX 10K device The pins from the FLEX 10K device are pre assigned to switches and LEDs on the board JTAG chain connection for the ByteBlasterMV cable Socket for an EPC1 configuration device Two momentary push button switches One octal DIP switch Dual digit seven segment display On board oscillator 25 175 MHz VGA port Mouse port Three expansion ports each with 42 I O pins and seven global pins FLEX_PB1 amp FLEX_PB2 Push Buttons FLEX_PB1 and FLEX_PB2 are two push buttons that provide active low signals to two general purpose I O pins on the FLEX 10K device FLEX_PB1 connects to pin 28 and FLEX_PB2 connects to pin 29 Each push button is pulled up through a 10 KQ resistor FLEX SW1 Switches FLEX_SW1 contains eight switches that provide logic level signals to eight general purpose I O pins on the FLEX 10K device An input pin is set to logic 1 when the switch is open and set to logic 0 when the switch is closed Table 6 lists the pin assignment for each switch Table 6 FLEX_SW1 Pin Assignments FLEX SWITCH 2 a a E Altera Corporation University Program Design Laboratory Package User Guide FLEX_DIGIT Display FLEX_DIGIT is a dual digit seven segment display connected directly to the FLEX 10K device Each LED segment on the display can be illuminated by driv
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