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STiC2 User Guide

1. O LADDER INPUTBIAS value provide DACs low input Z marked O DAC TTHRESH 0 15 Set timing threshold increases proportionally with this threshold green 3 2 and also increases the hysteresis O DAC TBIAS 0 15 It controls the range of O DAC_TTHRESH O_DAC_EBIAS 0 15 Set energy threshold The energy threshold increases proportion ally with this DAC O_DAC_ETHRESH 0 15 It controls the range of O DAC_ETHRESH Copy of 0 16 Copy the current configuration to the specified channel number can be range i j or discrete i j k need to push apply to execute syntax Chip Channel number Channel 0 16 only the selected channel is configured Chip 0 3 Select the chip you want to configure Bottom Update all Update all ASICs with the selected DACs configuration frame marked Update ASIC Update the selected chip only blue 3 2 Open configuration Save configuration Upload configuration file Save current configuration to a file e T fine fine counter value of the time improved resolution for the time information e E_CCM coarse counter master value for the energy measurement e E_CCS coarse counter slave value for the energy measurement e E_badhit bad hit flag for the energy measurement e time time information of the rising edge e energy time over threshold value Software 15 e errors the flag indicates if the corresponding event stored is good for analysis or not has errors The output root file is used fo
2. The second window is used for setting a specific channel for different thresholds masking etc The full functionality of this GUI is summarized in Table 3 2 Every time any DAC parameter is changed to a different value the parameters must be loaded into the chip by pressing Update all updates all chips or Update ASIC to configure only the selected chip IMPORTANT The GUI does not show any error messages However if the configuration does not reach STiC however one can check that the GUI is working by checking the Old value shown beside every parameter box If the Old parameter changes to the new one Software 12 Table 3 1 GUI list function for selection of general amp TDC Frame Name Value range Function Default value Generate IDLE Select Generates sync signal con tinuously between data frames Flags TDCtest Select Select Enables the direct TDC in put on channel 15 marked yellow 3 1 Disable coarse Select Disable the coarse counter TEMP12_BIT_DAC 0 4095 Bias for the latches in the 1500 TDC 400 mV internal O INDAC 0 63 Internal bias DAC 0 O DAC PFC 0 63 Internal bias DAC 0 O CML DAC 0 63 Internal bias DAC 0 VN D2C 0 63 Internal bias DAC 0 DACs VNCntBuffer VPCntBuffer 0 63 Internal bias DAC 0 marked green 3 1 VNCnt VPCnt 0 63 Internal bias DAC 0 VPCP VCascP 0 63 Internal bias DAC 0 VNVCODelay 0 63 Internal bias DAC 0 VNVCOBuffer 0 63 Internal bias DAC 0 VNHitLogic VPHitLogi
3. JTAG Cable Type 3rd Party Cable Xilinx Plug in Port A Frequency S Other Options cable type xilinx_plugin modulename digilent_plugin JTAG Device Chain k 9 Automatically Discover Devices on JTAG Chain Manual Configuration of JTAG Chain FPGA Device Name D Code IR Length Cancel OK Figure 4 5 The JTAG configuation menu Step by step 22 Select the button Program FPGA You should see the window in Figure 4 6 Select the Program FPGA Specify the bitstream and the ELF files that reside in BRAM memory I Hardware Configuration Hardware Specification home vekos1 stic2test_yonathan stictest stic2 mblaze SDK_codes xps_projects_hw_platform system xml Bitstream home vekos1 stic2test_yonathan stictest stic 2 mblaze SDK_codes xps_projects_hw _platform system bit BMM File home vekos1 stic 2test_yonathan stictest stic2 mblaze SDK_codes xps_projects_hw _platform system_bd bmm Software Configuration Processor ELF File to Initialize in Block RAM o microblaze_O Figure 4 6 The FPGA program menu following Go to the Run menu and select Now you basically saved all the environment and next time you upload the xsdk in this setup you will have under the Run green button your run option with the selected name and you can just run it Next step is to setup a new wired connection manually in y
4. clock for the PLL The detail connection is listed in A Table A 7 2 2 Main board The main board allows to connect a maximum of 4 STiC boards which are synchronized through the main board The layout of the board is shown in Figure 2 4 Figure 2 4 Main board layout In this Figure the different connectors to STiC and the location of the different blocks on the board are presented The functionality of the different connectors are the following e J14 J17 digital interface connectors to STiC Have the same pin layout as J6 see A 3 e J20 J22 J23 J25 power connectors to STiC Have the same pin layout as J31 see A 2 J8 J9 J10 J11 TDC clk input connectors 622 MHz clock J42 J43 connectors used for testing purposes e J12 J13 connectors to the FPGA board The pin layout is not required for the user System overview 8 e_J41 input bias voltage for the SiPMs connected to STiC typically 70 V e J32 power connector 12 Vpc 2 3 FPGA The FPGA in the package is the Avnet Spartan 6 FPGA LX9 MicroBoard The pin layout of the FPGA is shown in Figure 2 5 LX9 MicroBoard BOTTOM 10 100 ETHERNET SWITCH v2 a RESET J4 2 v JTAG 3 3V S op 3 3V HEADER GND Z GND F18 E18 F17 O w E16 K13 oo Im G13 K12 Nli H12 3NOG F VCC tool VCC sense MB LED3 F5 EE LEDs CA LED L6 MEEN 3 3V Ro 3 3V GND lon GND D18 3 4 C18 Ey DIP1 B3 D1
5. this example the mean value from the fit is 1 194 x 10 So the period is 1 194 x 10 x 50 2 x 10712 tde count is 50 2 ps 599 4 ns Important if the your period is not correct that is probably because the PLL is not locked The procedure for locking the PLL is the following Step by step 27 reer CPROO Sessions Sd 0 DocumentsiGoogle Drive 1ca D Documonis Cooglo Drve KlF Bai L L f i AE Form Germany mae mo neo ne nO na BRO Al Files C Figure 4 11 Root fast analysis a step 1 b step 2 c step 3 d step 4 monitor Entries 25635 3000 2500 Mean 1 194e 004 2000 RMS 4 541 1500 1000 11860 11880 11900 11920 11940 11960 11980 Figure 4 12 Fit to the period histogram Now repeat the measurement describe above and check the period is the correct one Step by step 28 Now when you are sure that everything is working correctly you can start your measurements with your detector 4 5 CTR measurement For CTR measurement we will use the same setup as in the previous section with a few modifications Instead of the pulse generator signal we will connect directly two MPPCs to two channels in the flex connector When using a detector the capacitor is not needed any more The setup now will look like in Figure 4 13 Detector 1 o U M Figure 4 13 Setup for CTR measureme
6. 21 C C mblaze_top asic_readout daq_application cc Xilinx SDK File Edit Source Refactor Navigate Search Run Project Xilinx Tools Window Help ri a a a gv ev a I ovrarlnlam ele e el ion a xj B 8 meine a spi methods h a dag methods h a daq application cc es y gt de Inknown type n r Na Y string Go Int gt Bxps_projects_hw platform Y lwipferrh Open in New Window d pbuf so we don t run out of phufs MU iwip udp h Copy cree u daq methodsh Paste cri DAG_PORT Delete Delete DAG _MINPACK Mov DAO_MAXPACK Rename F2 4 tdd cerdda pbut spayload dag pb _dataT chart daq_pbuf gt payLoad daq_pbu TAIR iaxpack Export e o RN E Clean Project FS es Terminal 1 xD Console 2 A WYN Make Targets gt index 0 sa Show in Remote Systems view Run As gt Ll Ll Debug As gt a ih standatone bsP 0 profile As gt Figure 4 4 The SDK main window on the picture are marked the buttons and menus that are been used Next step is to set JTAG it is important to check that you have the correct permission to talk with the USB port Go to You should see the window as in Figure 4 5 Here type the following selections Configure JTAG Settings Specify the JTAG cable to use for communication and JTAG Device Chain configuration of the target board These settings affect how XMD connects to the FPGA
7. 7 O wm C17 Bi A3 G14 ol F16 E DIP3 B4 CD pipa A4 F14 gt a F15 Direct USB Programming Figure 2 5 Spartan 6 FPGA LX9 MicroBoard pin layout The FPGA will be connected directly to the STiC test board and will be used for the configuration of STiC and also for readout of STiC output System overview 9 A detail description of the FPGA can be found in http opencores org websvn filedetails repname openmsp430 path 2Fopenmsp430 2Ftrunk 2Ffpga2Fxilinx_avnet_l1x9microbard 2Fdoc 2FXilinx_Spartan 6_LX9_MicroBoard_Rev_B2_Hardware_User_Guide pd f Chapter 3 Software There are two software in this package one is the Graphical User Interface GUI and the second is the Data Acguisition DAO The GUI is used in order to change the different parameters of the STiC for example changing the thresholds for each channel The DAO software is used for running the STiC to collect data running the online monitoring and saving the data into root files 3 1 GUI The STiC can be connected to the PC in two ways e using an Ethernet cable interface through the micro SPARTAN6 board and a HUB switch e directly using USB through the main board not available at the moment Please make sure you use the appropriate version of files according to your inter connection method The two Figures 3 1 3 2 show the window of the GUI with some default DAC values one for general amp TDC and the second for C
8. GA can also power the FPGA The user can choose between this connection to No 4 power cable for low voltage High Voltage HV cable software package Figure 1 1 shows the different package components 1 2 System reguirements In order to control the FPGA and the STiC2 chip with your personal computer a dedicated Graphical User Interface GUI was developed The system reguirements are What s in the package 3 Figure 1 1 The different package components The numeration corresponds to the list in the text e linux machine with Debian 6 0 or newer version recommended version 7 0 gtk 3 0 already embedded e ISE design suite Xilinx for using SDK kit 14 5 build SDK_P 58f download from http www xilinx com products design tools ise design suite If you are using older version you may need to install digilent adept plugin for xilinx The package can be found in digilent website Digilent Adept runtime and utility http www digilentinc com Products Detail cfm NavPath 2 66 828 amp Prod ADEPT2 Digilent Plugin for Xilinx Tools http www digilentinc com Products Detail cfm NavPath 2 66 768 amp Prod DIGILENT PLUGIN e ROOT version 5 34 00 used for building the output data online monitoring and analysis can be download from http root cern ch drupal These are the recommended requirements if using different versions the software package will need to recompile In addition also the user will need a
9. HUB switch for connecting the FPGA and the PC to the same network The recommended HUB is DES 1008D from D Link Before starting please check the all the above system requirements are fulfilled Chapter 2 System overview If you already familiarize with the system you can go directly to Section 4 The DAO system demonstrator for the STiC is based on three printed circuits boards the STiC test board the main board and the FPGA board 2 1 STiC2 test board The STiC chip is bonded directly to a 5 cm x 5 cm 6 layers test PCB which provides adequate interface connections to the outside world Figure 2 1 shows the PCB connections Figure 2 1 6 layers test PCB used for STiC Table 2 1 lists the relevant connection to the test board System overview Table 2 1 STiC test board PCB connections Function Reference Description Input connector J32 Connector to plug the analog inputs signals from the 16 detectors Each detector can be connected either in single ended or differential mode Interface connector J6 Connector for digital signals to the FPGA board that provides the data readout and the SPI configuration Power connector J31 Connector for the power voltages 3 3 V digital 1 8 V analog and 1 8 V digital TDC test input J25 Input of the TDC only for testing purposes Analog channel input J19 Input to the 16th channel which is only analog without TDC Analog channel output J24 Connector to read
10. KIRCHHOFF HEIDELBERG INSTITUTE SS NC rorruysics STiC2 User Guide Version 3 Authors Alejandro Gil amp Yonathan Munwes March 4 2014 Contents 1 What s in the package 2 11 Package i e s og a estea A a A a a 2 1 2 System requirements gue so a de ir a e REG HS 2 2 System overview 4 2 1 ies test hoard seais cid ss YW ee A 4 2 2 Main board gt e e sws paewai RR bb Bob ee Ay WR Yb a e a dy mud T o aganna a He ee Be RH a OE OR NEF ES eG ANF 8 3 Software 10 QU ed we ee ae Ge ee Odd ee Gog se Gee ee See ee G 10 a DAQ ee A a e RS EG eye YW WDD e eee Bae Ee 13 4 Step by step 17 dll EMS Wier co esa e e DESY ERE RA ROR ERE ES 17 4l Hardware ath oe eS nh oe Hh YY O ag ce ee ca aoe ee 2 17 ALA Softwarea sa s soe wea Bh ee a a E ee BES EA 18 ALA FPGA POE dara be oe A RR EES A BN 19 42 Runmne the DAQ con eh nok Se ew OE ON a asa 23 a Meme ore Be Erk Oe Y he ee ee UWD UE RES oe EW 24 LA Pulso Ie On test es sa sora eS Ow ESS Oe a eRe EEE Re ERS 24 45 CTR Measurement gs s le eb ere OR aa 28 A Test board connectors 30 B Technical specification 33 Chapter 1 What s in the package 1 1 Package description In the package you received the following components 1 2 3 T 8 STiC test board main board FPGA board USB mini USB cable for connecting the FPGA to the PC the FPGA is powered by the USB USB a male to a female extension cable to configure the Avnet Spartan 6 LX9 FP
11. ata output will lose its linear relation with the input energy System overview 6 H V Rbias differential single ended a b Figure 2 2 STiC operational modes in a single ended mode b differential mode locked If it is not locked the signal will have a distribution around the correct value The J25 connectors can be seen in A Table A 4 For the analog channel we use input connector J19 and output connector J24 Please note J24 has 2 differential outputs This part is used only for testing and it has only one channel see A Table A 5 A 6 In Figure 2 3 an example of the use of the analog chaanel is presented The red signal shows the analog signal applied to the input of the analog channel using charge injection The blue signal is the trigger signal from the pulse generator synchronized with the input signal The yellow signal is the timing signal generated by STiC This way one can check that the STiC output is generating the expected output Y f baa rra ee ee i Mia aatan Men ae PAGE PICO Pbmawct PeryoemCa Ps Pm v y62 mr 6 fang Yg re S30 Xte 7759808 Figure 2 3 Scope screen shot of the analog channel used for testing STiC In red analog signal applied in to the input analog channel blue trigger signal from pulse generator and in yellow the signal generated by STiC System overview 7 The last connector is the TDC CLK input connector J30 It is input reference
12. c 0 63 Internal bias DAC 0 O TESTCML DAC 0 63 Internal bias DAC 0 Chip Data Reset Channel Data Reset Chip 0 3 Select the chip you want to configure Reset Logic Update all Update all ASICs with the marked blue 3 1 Update ASIC Open configuration Save configuration selected DACs configura tion Update the selected chip only Upload configuration file Save current configuration to a file after pressing the Update button then the GUI is working and STiC is getting the values correctly If the Old value does not change or is set to any other value different to the one set then STiC is not getting the parameters In this case check the connection and make sure that STiC is powered on the FPGA board programmed and the connection from STiC to the FPGA is correct Also check that the cable USB or Ethernet is connected to the computer Software 13 gui_1x9_enet k Channel General Vmon ctrl Imon ctrl O NONE O NONE Old O Old O Channel DACs O_LADDER_DAC O_LADDER_INPUTBIAS O LADDER ICOMP gt a i a Old O as ad iai Old O a r Old O Threshold DACs O_DAC_TBIAS O_DAC_TTHRESH O_DAC_EBIAS O_DAC_ETHRESH 9 i Old O IE Old O 3 dd Old O ay aa i e Old O Copy configuration of channel 0 9 to channels 0 1 16 Chip O General amp TDC O Channel 9 a Update all Update ASIC Open configuration Save configuration Figure 3 2 GUI screenshot for Channel option 3 2 DAQ The da
13. ce This is the environment where all the folders and files of the package are in To create a workspace directory in the desired place type mkdir workspace cd workspace Step by step 19 Copy all the package folders from the CD to the workspace Now when typing ls you should see the following folders The script init stic sh is used to compile all the different part of the code in all the folders you should do it only in the first use or if you change some of the codes To run the script type It is important to check that there are no errors in the compilation 4 1 3 FPGA program Now open a new shell for running the SDK program from Xilinx This program is used in order to configure the FPGA Type A new window should open for the Xilinx software A pop up window asks you to select a workspace folder You should select the folder named SDK_codes under stic2 mblaze folder If it is the first use you should close the welcome window The software has two main windows see Figure 4 2 On the left window named Project Explorer Now on the left window you will have all the folders that are in the SDK codes folder Before we build all projects it is recommended to clean all the projects Step by step 20 C C Xilinx SDK File Edit Source Refactor Navigate Search Run Project Window Help a Js oda 5 0 es will be used Project Run bu
14. ch histogram can be scaled during the run using the coarser to shift the axis The Monitor GUI can be seen in Figure 3 4 is where the user selects what he wants to display on the Readout monitor from the following options e E shows the energy spectra Time Over Threshold of the input signal according to the actual thresholds e TSINGLE combination of TSINGLE FINE TSINGLE_CM 50 2ps bin e TSINGLE FINE fine counter histogram 50 2ps bin Software 16 Monitor GUI MODE CH 1 CH2 Figure 3 4 Screen shot of the online monitor GUI e TSINGLE_CM coarse counter histogram 1 6ns bin CHANNEL histogram with the number of hits per channel e BADHIT shows the bad hits the rejected ones PERIOD it allows checking the period of the events in a specified channel This is especially useful for testing purposes with pulse generator to check that the PLL really locks at the right freguency e T time difference between the two specified channels In addition there is a reset button at the bottom of the Monitor GUI This will only reset all displayed histogram it will not affect the integrated data collected to this point Chapter 4 Step by step This part of the user guide is a step by setp instruction from first installation until receiving an output file that is ready for analysis In addition at the end of this chapter there are hints for doing the analysis Before you continue please c
15. g the daq all data collected will be saved to ROOT file named dump root see details in Section 3 2 4 3 Using GUI To run the GUI just type Step by step 24 The window of the GUI should appear Important please check inside the file start gui sh that the IP address is the same as you selected by default 192 168 0 2 Now the GUI is running and you can test if everything is connected correctly Go to Section 3 1 for all the details about the different functions of the GUI 4 4 Pulse Injection test This part is not mandatory but is highly recommended Before starting doing measurements with your detector it is better to check that the system is working properly with a known signal For this purpose additional connection is reguired to connect the pulse positive signal to the STiC input signal connector J32 in the STiC test board The flex print connector for this use is shown in Figure 4 8 When using a pulse generator the signal should pass it through a a b Figure 4 8 Flex connector for the testing a upper side b bottom side Step by step 25 capacitor 100 pF recommended to the positive input of a channel and connect it also to one of the GNDs connector J31 in STiC test board see Figure 4 9 for the exact setup Figure 4 9 The setup for pulse injection measurement For testing you could upload setup file from the GUI Open configuration choose the file named STiC2Co
16. hannel can be chosen from the bottom frame of the GUI marked red on the Figures NOTE After switching on a reset must be applied to the chip for proper opera tion via button Chip Data Reset The first window is used for setting the TDC DACs which is common for all channels Table 3 1 summarize all the window functions 10 Software 11 gui_1x9_enet Y Generate IDLE TDCtest Select Disable coarse Old O Old O Old O TEMP12_BIT_DAC O_INDAC O_DAC_PFC a Old O ie Old O uu Old O O_CML_DAC VN D2C VN CntBuffer VPCntBuffer i ia Old E Old O T Old O VNCnt VPCnt VPCP V CascP VNVCODelay E Old a Old O i e Old O VNVCOBUffer VNHitLogic V PHitLogic O_TESTCML_DAC i lia Old rr Old O Old O Reset Log Chip Data Reset k Channel Data Reset Chip O O General amp TDC Channel 9 Update all Update ASIC Open configuration Save configuration Figure 3 1 GUI screenshot for general amp TDC option It is important to select General amp TDC settings and press the button Chip Data Reset and or Channel Data Reset at least one time after switching on the chip Sometimes these buttons can help to recover the normal functionality of the chip when it does not seem to behave correctly i e after a power supply cut or setting very wrong DAC values After setting all the different DACs it is recommended to save your settings using the Save configuration button for later use
17. heck that your PC meets all the reguirements that are listed in Section 1 2 4 1 First installation 4 1 1 Hardware 1 Connect the FPGA to the STiC J35 STiC to J4 FPGA and J36 STiC to J5 FPGA 2 Connect the FPGA to to the HUB using Ethernet cable better to use the recommended HUB 3 Connect the HUB to the PC using Ethernet cable 4 Connect the computer and FPGA to the same network by connecting both Ethernet cables from computer and FPGA to a network switch 5 Connect STiC to the main board J6 J30 and J31 STiC to one of the option connection in the main board for example J17 J9 and J25 6 apply power to STiC 17 Step by step 18 a If using STiC standalone use connector J31 The power consumption should be around 250 mA for 1 8 V and 80 mA for 3 2 V After connecting to the FPGA it will be around 1 8 V 390 mA 3 2 V 90 mA b If using the Mainboard for power apply 12 V via connector J32 on the Mainboard The current consumption should be about 370 mA when supplied with 11 V 7 Connect the FPGA power via the USB to the PC not the microUSB connector 8 If needed connect HV cable to J41 main board it will give the HV through connector J6 STiC to the SiPMs The system connected should look like Figure 4 1 when using the spartan6 1x9 microboard Figure 4 1 Connection scheme of the FPGA STiC and the main board 4 1 2 Software First you need to setup the workspa
18. ive signal 2 Analog GND 3 4 Output energy positive signal 5 Output energy negative signal 6 Table A 7 Details of J30 input TDC clk signal Input Pin Input PLL negative 1 Digital Ve 3 3 V 2 Input PLL positive 3 Digital GND 4 Appendix B Technical specification Table B 1 STiC2 technical specification Parameter Value Units Condition Charge injection jitter analog lt 30 ps O 3 pC input charge C 33 pF channel using Tektronix AWG7102 Charge injection jitter full chain 43 pso 6 6 pC input charge C 33pF using Tektronix AWG7102 DAC range 0 7 V Charge response Linear For input charge larger than 3 pC Power consumption 19 mW ch room temperature SPTR single ended mode 180 ps O Using a fast laser system PI LAS PiL063SM and Hamamatsu MPPC S10362 11 100 1x1mm 100m x 100m pixel SPTR differential mode 180 ps o Using a fast laser system PI LAS PiL063SM and Hamamatsu MPPC S10362 11 100 1x1mm 100m x 100m pixel Energy resolution 11 CTR differential 220 ps FWHM T 18 C using crystal LSO 3 1x3 1x15mm Na source Hamamatsu SiPM ref S10362 33 050C Bias operation volt age 74 V Single Pixel Time Resolution 2Coincidence Time Resolution 33
19. nfig test _charge txt For this configuration we used a pulse with the following setup e period 599 47 ns amplitude 408 mV pulse width 200 ns edge time 5 ns 20 cycles e burst period 10 ms e capacitor of 120 pF For this setup you should see the distributions plotted in Figure 4 10 You can verify that the period is the same as generated by the pulse generator remember that each TDC count is 50 2 ns Step by step 26 PERIOD CHANNEL manto Far E Entries 48741 a 4541 8 8 8 8 8 8 epee L Trai TSINGLE_FINE E i E 38888 ogi 88 pu so oF 4 ot a E a st Figure 4 10 Online monitoring view for the pulse injection test 33338 After closing the online monitor of the DAQ a root file is saved it s recommend to close the online monitor via File Quit Root to void error during closing the DAQ In this file you can find also the different plots of the online monitoring which you can preformed on them a fast analysis in order to check that the system is working properly You can open the file using ROOT whith the following commands The fit result for the period is shown in Figure 4 12 The period must be confirmed with the input injected signal In
20. nt On the the MPPC cover the recommended V is written In our case when using the STiC chip it is recommended to set the HV around 1 V higher For finding the optimum HV value you should repeat the following measurement for different HV values HV scan Now you should set the different DACs values until you see a good energy spectrum in the histogram and that all other distributions are ok After you collect all the required data you could do the CTR measurement In our example we searched for coincidence between two detectors and we fill the histogram with the values of t1 t2 arrival time difference between the two detectors Because we aim to measure the coincidence of the 511 keV electron we will use the energy spectrum in order to select only events that are around this region Step by step 29 In Figure 4 14 the two detectors energy spectrum are plotted with the corresponding energy selection Also plotted is the results for the CTR measurement for testing two 3 x 3mm MPPCs with HV of 73 5 V TOT1 TOT2 totT tot2 tf mo BOE oe att ali Es el Es 1000F 700 600E 800F E t 500E 600 4005 a00F 300F E 200F 200 E i bla 100F ouh one eee ee ee ee Qt AAA AA 0 50 100 150 200 250 300 350 400 450 O 50 100 150 200 250 300 350 400 450 TOT 1 6ns TOT 1 6ns CTR timediff g 80 Entries 965 Q Mean 1 794 92160 X I nd
21. our PC different than the one of the FPGA but with the same subnet For this go the network settings in your PC and define Step by step 23 TN EDA File dr Source Refactor Naegww Searen E project etime Tosia Window Help ras n i ei era er CHFN gy gy 5 o e Has 7 Run Configurations ed az bee Create manage and run configurati N run History gt i q B A mainc daq_applicationce E eno m Ma t eT al Ran fs Sie aM Bo Ff op Configure Launch settings from this diatog 7 Prese the New burton to create a configuration of tne selected type rieu hw platform ve don t run out of puts dog methoesh DAG PORT DAO MINPACK DAO MAXPACK uration by selecting it launch perspective settings from the Perspectives preference page p Filter matched 6 of 6 items o cose Jen ar tna poo Figure 4 7 SDK run menus a run configuration option b create mange and run configurations a new connection with the given IP different instructions depending on the system you are running Please check that the connection is ok by typing in the shell If data is streaming it is ok continue to the next stage 4 2 Running the DAQ Now we can run the DAQ software for this purpose go back the previous shell different than the one running SDK This will start the DAQ software When endin
22. out the signals energy and time di rectly from the analog LVDS differential output channel number 16 TDC clk input J30 622Mhz clock which is used as a coarse counter for each TDC Direct connection to FPGA J35 Connection to FPGA J4 see Figure 2 5 Direct connection to FPGA J36 Connection to FPGA J5 see Figure 2 5 The connector used on the board for the input for the 16 channels J32 is SAMTEC FLE 123 01 G DV A possible mate for this connector is the SAMTEC FTS 123 01 F DV The detail input connection is listed in A Table B 1 STiC is designed to work with positive signal current flowing into the chip connected to the positive input terminal STiC allows two possible readout modes single ended and differential In Figure 2 2 the two diagram for the two modes are presented where the typical values for discrete Hamamatsu MPPCs are Rbias 10 K and Crias 100 nF The arrangement of the power connector J31 is listed in A Table A 2 The interface connector J6 is a 24 pin double row generic 2 55 mm pitch header connector used for readout of the digital data slow control test signal outputs and analog channel outputs See its detail connection in A Table A 3 The connector J25 is used only for testing the TDC The way to test is to inject input signal and check if the output signal has the same value for all pulses this test checks if the PLL is INegative input is also possible but the energy d
23. r analysing the data Most of the branches listed above are used only in the DAO software For analysis purpose only the branches named channel time energy and errors are used When running the DAQ software the online monitoring tool is being opened automatically The online monitoring has two windows Readout Monitor and Monitor GUI Readout Monitor Elle Edit View Options Tools TSINGLE_CM monitor monitor2 Entries 324 418 Mean 1 5868 04 RMS 9436 lean 10 E RMS 42 42 fi Liviu Ly il TWW 5000 4000 3000 2000 1000 0 1000 2000 3000 5000 10000 15000 20000 25000 30000 E TSINGLE_FINE monitor4 E ies 431 Entries 435 00 Mean 76 95 Mean 16 7 RMS 7 976 a 8 amp 8 20h e 8 9 TTTT TTTTTTTTT TTTTTTTTT TTTT Y 8 E o Figure 3 3 Screen shot of the online monitor histograms The Readout Monitor presents 4 histograms which the user can choose The histograms are being updated with the arrival of new data only after selecting parameters from the Monitor GUI options the histogram starts to fill An example can be seen in Figure 3 3 Ea
24. t 425714 140 Constant 168 8 8 1 Mean 0 952 0 102 120 Sigma 2 079 0 110 100 FWHM 245 32 ps 80 60 40 20 0 60 40 20 0 20 40 60 time Diff 50 2ps Figure 4 14 CTR measurement results Top two plots are the energy spectrum for the two detectors The red lines correspond to 1 50 around the 511 keV peak The bottom plot is the CTR distribution for the related energy Appendix A Test board connectors Table A 1 Details of J32 input connector Input Pin Pin Input Analog GND 1 24 Analog GND Channel 15 negative 2 25 Channel 15 positive Channel 13 negative 3 26 Channel 13 positive Channel 11 negative 4 27 Channel 11 positive Channel 9 negative 5 28 Channel 9 positive Analog GND 6 29 Analog GND Channel 14 negative 7 30 Channel 14 positive Channel 12 negative 8 31 Channel 12 positive Channel 10 negative 9 32 Channel 10 positive Channel 8 negative 10 33 Channel 8 positive Analog GND 11 34 Analog GND Channel 6 negative 12 35 Channel 6 positive Channel 4 negative 13 36 Channel 4 positive Channel 2 negative 14 37 Channel 2 positive Channel 0 negative 15 38 Channel 0 positive Analog GND 16 39 Analog GND Channel 7 negative 17 40 Channel 7 positive Channel 5 negative 18 41 Channel 5 positive Channel 3 negative 19 42 Channel 3 positive Channel 1 negative 20 43 Channel 1 posi
25. ta acquisition software is used for operating the STiC It collects the data and stores it to disk space and run and configure the online monitoring tool The data is stored in ROOT file format named dump root which contains a TTree with all the data received from the STiC If you are not familiar with the TTree class the full class documentation is in http root cern ch root html TTree html The TTree contains the following branches e packet_number packet ID the event was transmitted in e frame number frame number of the event for debug channel channel number e T CCM time coarse counter master value e T_CCS time coarse counter slave value T_badhit bad hit flag for the time measurement Software 14 Table 3 2 GUI list function for selection of Channel Frame Name Value range Function Mask Select Selected channel masked Channel Vmon ctrl 0 8 Activate the monitoring of 0 NONE 1 T bias 2 T threshold General 4 E bias 8 E threshold marked Imon ctrl 0 2 Activate the monitoring of 0 NONE 1 icomp_mon 2 ibias_mon yel low 3 2 O DAC 0 63 SiPM bias tuning 700 mV in the range 100 800 mV Vinput must be larger than 200 mV to operate properly O LADDER DAC 0 63 Timing and energy scaling DAC O_LADDERINPUTBIAS 0 63 DAC for the input stage Reducing this DAC value will increase the tail current and shrinks the energy spectrum Channel O LADDERJICOMP 0 63 Setting this DAC value
26. tive Analog GND 21 4 Analog GND Digital GND 22 45 Digital GND HV GND 23 46 HV GND 30 Test board connectors 31 Table A 2 Details of J31 input power connector Input Pin Voc 1 8 V analog 5 7 Vcc 1 8 V digital 1 3 Vcc 3 3 V digital 9 11 Digital GND 2 4 10 12 Analog GND 6 8 Table A 3 Details of J6 interface connectors Input Pin Pin input Digital GND 24 23 Digital GND Do_FIFO_EMPTY debug only 22 21 Dummy DO_ANY_DREADY debug only 20 19 DO FIFO FULL debug only Digital GND 18 17 Digital GND Serial clock SPI 16 15 Digital reset Digital GND 14 13 Serial data output SPI Digital GND 12 11 Digital GND Readout clock input positive 10 9 Readout clock input negative recommended 160 MHz recommended 160 MHz Digital GND 8 7 Digital GND Serial data input SPI 6 5 Chip select Cs data transmission Txd_N 4 3 data transmission Txd_P not used 2 1 Digital GND Table A 4 Details of J25 input TDC test signal Input Pin Time positive Time negative Energy positive Energy negative OJ Nj e Analog GND Test board connectors 32 Table A 5 Details of J19 input analog test signal Input Pin Input positive signal 1 Analog GND 2 Input negative signal 3 Table A 6 Details of J24 output analog test signal Input Pin Output time positive signal 1 Output time negat
27. tton Program FPGA explorer button window Here you can edit the different project files Maa al a n en No consoles to display at this time mw O items selected Figure 4 2 The SDK main window Buttons and menus that are being used are marked Import Import Projects A Select a directory to search for existing Eclipse projects 4i cs la fee O Select archivefile Browsen Projects Select Select All j Create new projects from an archive file or directory 4 Deselect All Select an import source 4 9 General 3 E Archive File 2 sc uz cons scene crane Fate s ps projecto arfon Yesteraayat 15 25 E Existing Projects into Workspace File System O Copy projects into workspace Preferences Working sets y Suc EE a reject to working sets El C C Executable e Hi a CH Project Settings Warking sets c selecto Selec oot or etary ofthe projects ta impart 0 z2eck Next cancer Finch o lt Back J next gt canca L Einen a b c Figure 4 3 SDK import menus a general option b browse window c folder selection menu We need to choose the IP address for the FPGA In the Project Explorer go to the file main cc in mblaze_top src You can define the IP in lines 111 113 default value 192 168 0 2 Now let s build the project Step by step

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