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Xilinx LOGICORE UG144 User's Manual

1. rgmii rx ctl 3 352 R 4 300 R not rgmii rx clk bufg 4 938 0 661 R 0 284 R rgmii rx clk bufg 0 938 rgmii rxd 0 3 384 R 4 332 R not_rgmii_rx_clk_bufg 4 938 0 629 R 0 316 R rgmii rx clk bufg 0 938 rgmii rxd 1 3 348 R 4 296 R not rgmii rx clk bufg 4 938 0 665 R 0 280 R rgmii rx clk bufg 0 938 rgmii_rxd lt 2 gt 3 360 R 4 308 R not_rgmii_rx_clk_bufg 4 938 0 653 R 0 292 R rgmii rx clk bufg 0 938 rgmii_rxd lt 3 gt 3 428 R 4 382 R not_rgmii_rx_clk_bufg 4 938 0 585 R 0 366 R rgmii rx clk bufg 0 938 Virtex 5 devices with delayed Data Control Setup and Hold results for the RGMII input bus can be found in the data sheet section of the Timing Report The results are self explanatory and it is easy to see how they relate to Figure 9 3 Following is an example for the RGMII report from a Virtex 5 device Each Input lists two sets of values one corresponding to the ve edge of the clock and one to the ve edge The first set listed corresponds to ve edge which occurs at time 0 ns The implementation requires 0 818 ns of setup to the ve edge and 0 794 ns to the ve edge This is less than the 1 ns required so there is slack The implementation requires 0 946 ns of hold to the ve edge and 0 972 ns to the ve edge This is less than the 1 ns required so there is
2. This document uses the following conventions An example illustrates each convention The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Courier bold pier commen yone ngdbuild design_name a syntactical statement Variables in a syntax See the Development System statement for which you must Reference Guide for more supply values information Italic font References to other manuals See the User Guide for details If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol the two nets are not connected I h Dark Shading Jens nat a S HppDHeo This feature is not supported or reserved An optional entry or Square brackets parameter However in bus ngdbuild option_name specifications such as design_name bus 7 0 they are required Bude 6 A list of items from which you Toupie eisn stt must choose one or more Separates items in a list of Verticalbar choices lowpwr on off L t Vertical ellipsis Re i Sdn 2 ae Repetitive material that has 7 been omitted Xs 11 lock block Horizontal ellipsis Omitted repetitive material S one cok Ree ane loci loc2 locn The prefix 0x or the suffix h Aicadpraddpess ges 0x00112975 returned indicate hexadecimal notation Notations 45524943h a
3. 0 0000 119 Ethernet Statistics Core 0 00 00000 re 119 Connecting the Ethernet Statistics Core to Provide Statistics Gathering 119 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com UG144 April 24 2009 DISCONTINUED PRODUCT EZ XILINX Chapter 12 Implementing Your Design Pre implementation Simulation 0 00 0c cece eee eee 123 Using the Simulation Model 0 0 0 0 ooo cence eens 123 cyan APRENDE 123 XSI VHDL i d ERES AE RED RETARA REE EEEE CU ER eee eK 123 XSI VenlOg se ek CREER a KEA E REP uere eor a ges erre 124 Implementation cud o Duda ied ripa oed Un Rasen doe Ra bdo a Rep iue RICH 124 Generating the Xilinx Netlist 0 0 0 2c ene 124 Mapping the IDesi oii cu eroe en ie as secs ain etnies ose auth etnig tee tia ak 124 Placing and Routing the Design 6 666 neces 125 Static Timing Analysis cede coe petet eee DH paciens Ree Caer cera 125 Generating a Bitstream 6 cent ia ee tani nnas 125 Post Implementation Simulation tuus eee eee 125 Generating a Simulation Model 2 0 0 eens 125 Using the Model es me manta hie epe e t pe eee eben e te ede quee quere 126 Other Implementation Information usse eese 126 Appendix A Using the Client Side FIFO I terfaces ue RE EU IIR DLE I RES Lew eee REA XU Re RES 128 Transmit OD T PIE 128 Receive EIBQU dee ree bd Fi a dede e odi oe at Ween ed Re eile 129 O
4. 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 27 UG144 April 24 2009 DISCONTINUED PRODUCT x XILINX Chapter 2 Core Architecture Management Interface Optional Table 2 4 describes the optional signals used by the client to access the management features of the GEMAC core See Using the Optional Management Interface on page 77 Table 2 4 Optional Management Interface Signal Pinout Signal Direction Glork Description Domain host_clk Input n a Clock for the Management Interface must be 10 MHz or above host_opcode 1 0 Input host_clk Defines operation to be performed over MDIO interface Bit 1 is also used as a read write control signal for configuration register access host_addr 9 0 Input host_clk Address of register to be accessed host_wr_data 31 0 Input host_clk Data to write to register host rd data 31 0 Output host clk Data read from register host miim sel Input host clk When asserted the MDIO interface is accessed When not asserted the configuration registers are accessed host req Input host clk Used to signal a transaction on the MDIO interface host_miim_rdy Output host_clk When high the MDIO interface has completed any pending transaction and is ready for a new transaction MAC Unicast Address Optional Table 2 5 describes the alternative method of access to the unicast address registers when the opti
5. 11 1oQpB sssssm 13 Preface About This Guide Guide Contents 00 0 0 0000 ccc ccc eee cence rs 15 Conventions occu epe RI ed oath elie gegen diced Dine eee as nte ace ales 16 Typographical 5 tecs win ethos ep bere erede Wave es eoe duced pace os edid ed eid es 16 Online Doct ment 22io ecce beet ce eec toe pd ec eese aces accio es 17 Listof Acronyms cocer Geek cei eet Rech he orte cet ie gabe des rol on iet 17 Chapter 1 Introduction About the Cote 3424008 ete hyo 85 e084 hd iere tr EUER E e sa eg 19 Recommended Design Experience sisse sees 19 Additional Core Resources eesssssee ee 19 Related Xilinx Ethernet Products and Services Luuuuuuuuuuuuuu 19 SPecCliiCaNONG M 20 Technical SHpporb iiio stes epa exe Ee e EX E Veo edes ada 20 Feedback oberen rbd dubie tutte tee perds UR EET 20 GEMAGC COT i pp REPE ERU he Sine Yee eee p den kata Vae Ya 20 Beige PP 20 Chapter 2 Core Architecture System Overview 41d cest rep tea PERO CE ACE Re iof ance doin a dace d ad 21 Core Components ia ou veo REV ev va ede ves Pau e de bu repite 22 Cote Interfaces uoce coo i RCRUM Rol e oe Rd on RACIO ER e rd o Ke RI Rel D 23 GMAC Core with Optional Management Interface 2 0 60 eee eee eee 23 GMAC Core Without Management Interface and With Address Filter 24 GEMAC Core Without Mana
6. Tx FIFO Rx FIFO Figure A 1 Typical 10 Mbps 100 Mbps 1 Gbps Ethernet FIFO Implementation 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 127 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Appendix A Using the Client Side FIFO Interfaces Transmit FIFO Table A 1 describes the transmit FIFO client interface For more information on the MAC client interface see Transmitting Outbound Frames on page 47 Table A 1 Transmit FIFO Client Interface Signal Direction pleck Description Domain tx_clk Input N A Transmit clock used by MAC tx_reset Input tx_clk Synchronous reset tx_enable Input tx_clk Clock enable for tx_clk Tie to logic 1 when using GEMAC tx_data 7 0 Output tx_clk Data presented t o MAC for transmission tx_data_valid Output tx_clk Valid signal for data tx_ack Input tx_clk Ack signal from MAC tx_underrun Output tx_clk Underrun signal to MAC tx_collision Input tx_clk Collision indication from MAC Tie to logic 0 when using GEMAC tx_retransmit Input tx_clk Retransmit request from MAC Tie to logic 0 when using GEMAC Table A 2 describes the transmit FIFO LocalLink interface For more information on the LocalLink interface see Overview of LocalLink Interface on page 130 Table A 2 Transmit FIFO LocalLink Interface Signal Direction Bees Description tclLclock In
7. D DC Clock 112 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 XILINX DISCONTINUED PRODUCT Chapter 11 Interfacing to Other Cores Ethernet 1000Base X PCS PMA or SGMII Core The GEMAC core can be integrated in a single device with the Ethernet 1000BASE X PCS PMA or SGMII core to extend core functionality to provide the following 1000BASE X Physical Coding Sublayer PCS logic designed to the IEEE 802 3 specification with either 1000BASE X Physical Medium Attachment PMA using a device specific RocketlIO transceiver Virtex8 5 SXT and LXT devices use RocketIO GTP transceivers e Virtex 5 FXT devices use RocketIO GTX transceivers After the first introduction of a device specific RocketIO transceiver all subsequent references use the generic term RocketIO transceiver 1000BASE X parallel Ten Bit Interface TBI for connection to external SERDES Alternatively the Ethernet 1000BASE X PCS PMA or SGMII core can function as a GMII to Serial GMII SGMII bridge meaning that this can be used to provide the GEMAC core with an SGMII for serial connection to appropriate PHYs A description of the latest available IP Update containing the Ethernet 1000BASE X PCS PMA or SGMII core and instructions for obtaining the IP Update can be found on the Ethernet 1000BASE X PCS PMA or SGMII product page A full description of the Ethernet 1000BASE X PCS PMA or SGMII core is out
8. fupe Morak 000 MDC 1 Clock Divide 4 0 x 2 The frequency of mdc given by this equation should not exceed 2 5 MHz to comply with the IEEE 802 3 2005 specification for this interface To prevent mdc from being out of specification the Clock Divide 4 0 value powers up at 00000 While this value is in the register it is impossible to enable the MDIO interface For details of the register map of PHY layer devices and a detailed description of the operation of the MDIO interface itself see IEEE 802 3 2005 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Using the Optional Management Interface XILINX Figure 8 8 shows access to the MDIO interface through the Management Interface host_clk host_miim_sel host_req host_opcode1 0 host_addr9 0 host_wr_data15 0 host_rdy host rd data 15 0 Il If a read transaction is initiated the host rd data bus is valid at the point indicated If a write transaction is initiated the host wr data bus must be valid at the indicated point Simultaneous read and write is not permitted Figure 8 8 MDIO Access through Management Interface For MDIO transactions the following applies host miim selis l host opcode 1 0 maps to the OP opcode field of the MDIO frame host addr maps to the two address fields of the MDIO frame PHYAD is host addr 9 5 and REGAD is hos
9. 17 EZ XILINX 18 DISCONTINUED PRODUCT Preface About This Guide Acronym Spelled Out NCD Native Circuit Description NGC Native Generic Circuit NGD Native Generic Database ns nanoseconds PCB Printed Circuit Board PCS Physical Coding Sublayer PHY physical side interface PMA Physical Medium Attachment PMD Physical Medium Dependent RGMII Reduced Gigabit Media Independent Interface SGMII Serial Gigabit Media Independent Interface VHDL VHSIC Hardware Description Language VHSIC an acronym for Very High Speed Integrated Circuits VCS Verilog Compiled Simulator VLAN Virtual LAN Local Area Network www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 1 Introduction The 1 Gigabit Ethernet MAC GEMAC core is a fully verified solution that supports Verilog HDL and VHDL In addition the example design provided with the core is provided in both Verilog and VHDL This chapter introduces the GEMAC core and provides other related information including recommended design experience additional resources technical support and ways to submit feedback to Xilinx About the Core The GEMAC core is a Xilinx CORE Generator IP core included in the latest IP Update on the Xilinx IP Center For detailed information about the core see the GEMAC product page For information about licensing optio
10. DISCONTINUED PRODUCT LogiCORE IP 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 XILINX DISCONTINUED PRODUCT XILINX Xilinx is providing this product documentation hereinafter Information to you AS IS with no warranty of any kind express or implied Xilinx makes no representation that the Information or any particular implementation thereof is free from any claims of infringement You are responsible for obtaining any rights you may require for any implementation based on the Information All specifications are subject to change without notice XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE Except as stated herein none of the Information may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx 2004 2009 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries The PowerPC name and log
11. gmii_rx_clk_bufg 0 000 gmii_rxd lt 0 gt 6 149 R 7 484 R gmii_rx_clk_bufg 0 000 gmii_rxd lt 1 gt 6 152 R 7 486 R gmii_rx_clk_bufg 0 000 gmii_rxd lt 2 gt 6 206 R 7 532 R gmii_rx_clk_bufg 0 000 gmii_rxd lt 3 gt 6 207 R 7 533 R gmii rx clk bufg 0 000 gmii rxd 4 6 134 R 7 476 R gmii rx clk bufg 0 000 gmii rxd 5 6 134 R 7 476 R gmii rx clk bufg 0 000 gmii rxd 6 6 170 R 7 506 R gmii rx clk bufg 0 000 gmii rxd 7 6 170 R 7 506 R gmii rx clk bufg 0 000 SsSesesssess 4 4 4 4 The implementation requires 6 134 ns of setup Figure 9 2 illustrates that this represents a figure of 1 866 ns relative to the following rising edge of the clock since the IDELAY has acted to delay the clock by an entire period when measured from the input flip flop This is less than the 2 ns required so there is slack 100 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Required Constraints DISCONTINUED PRODUCT XILINX The implementation requires 7 554 ns of hold Figure 9 2 illustrates that this represents a figure of 0 446 ns relative to the following rising edge of the clock since the IDELAY has acted to delay the clock by an entire period when measured from the input flip flop This is less than the 0 ns required so there is slack GMII_RX_CLK ff J A Ke GMII RXD 7 0 GMII RX DV GMII RX ER 8
12. FROM config to rx TO rx clock TIG INST gmac core BU2 U0 MANIFGEN MANAGEN CONF TX OUT TNM config to tx INST gmac core BU2 U0 MANIFGEN MANAGEN CONF FC OUT 30 TNM config to tx TIMESPEC TS config to tx FROM config to tx TO tx clock TIG 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 95 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 9 Constraining the Core Timespecs for Reset Logic within the Core Internally the core is divided into clock reset domains that group elements with common clock and reset signals The reset circuitry for one of these domains is illustrated in Figure 10 5 This circuit provides controllable skews on the reset nets within the design The following UCF syntax identifies the relevant reset logic and groups them together Timing constraints are then applied to constrain the skews on the reset nets INST gmac_core BU2 U0 SYNC_RX_RESET_I RESET_OUT TNM reset_dist_grp INST gmac_core BU2 U0 SYNC_TX_RESET_I RESET_OUT TNM reset_dist_grp INST gmac_core BU2 U0 G_SYNC_MGMT_RESET SYNC_MGMT_RESET_HOST_I RESET_OUT TNM reset_dist_grp TIMESPEC TS_reset_dist FROM reset_dist_grp 6100 ps Note The third line in the preceding UCF syntax is only required when the optional Management Interface is used Constraints when Implementing an External GMII The constraints defined in this section are implemented in the UCF for the example design d
13. GMII IOB input flip flops Fixed phase shift is applied to the DCM with the example UCF for the example design See Appendix C Calculating DCM Phase Shifting IOB LOGIC eats ete rr 1 BUFG IBUFG DCM gmii_rx_clk gmii rx clkO CLKIN id CLKO IPAD 1 Gigabit Ethernet MAC LogiCORE FB d gmii rx clk 4 gmii_rx_clk_bufg IOB LOGIC IBUF gmii_rxd 0 gmii_rxd_reg 0 gmii rxd 0 A 4 4 IBUF gmii rx dv gmii rx dv reg gmii rx dv IBUF gmil rx er gmii rx er gmii rx er reg Figure 7 2 External GMII Receiver Logic for Spartan 3 Spartan 3E and Spartan 3A Devices 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 63 UG144 April 24 2009 XILINX 64 DISCONTINUED PRODUCT Chapter 7 Using the Physical Side Interface DCM Reset circuitry A DCM reset module not illustrated in Figure 7 2 is also present and is instantiated in the example design next to the DCM Since this logic must be reliable whatever the reset locked status of the DCM the module requires a reliable reference clock In the example design for GMII the global transmitter clock is therefore used gtx_clk_bufg from Figure 7 1 This reset circuitry will generate an appropriate reset pulse based on the family for the receiver DCM under the following conditions e The locked signal from the DCM is constantly monitored Following a high to low transition on this signal indicating tha
14. In the example designs for Virtex 4 families the 200ms reset pulse from the DCM reset module is NOT connected directly to the DCM this signal must be connected when implementing the core in real hardware The reason why the 200ms input is not routed directly to the DCM is so that simulations can occur in a timely manner The 200ms reset pulse takes the signal name reset 200ms in the example design HDL files It is routed from the DCM reset module instantiation up through all levels of hierarchy to the top level It is then left unconnected in the example design instantiation from within the demonstration test bench Furthermore an accompanying signal reset 200ms in is routed down from the top level of the example design hierarchy to the DCM instantiation where it is connected to the DCM reset From the demonstration test bench this reset 200ms insignalis driven for a short duration to enable fast simulation start up However to re iterate when implementing the design in real hardware the DCM reset signal must be connected correctly www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Implementing External RGMII XILINX e This can be achieved by connecting the reset 200ms signal to the reset 200ms in signal at any level of example design HDL hierarchy IOB LOGIC Tx uU E NIU ue Al BUFG l IBUFG rgmil_rxc 1 Gigabit Ethernet MAC Core gmii_rx_clk_bufg g
15. VLAN Tagged Frames Figure 5 4 illustrates the reception of a VLAN tagged frame if enabled The VLAN frame is passed to the client so that the frame may be identified as VLAN tagged This is followed by the Tag Control Information bytes V1 and V2 More information on the interpretation of these bytes may be found in IEEE 802 3 2005 standard rx_data 7 0 Aaa sa vean lur hk paa tag rx_data_valid J rx_good_frame J rx_bad_frame a Figure 5 4 Reception of a VLAN Tagged Frame 42 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Receiving Inbound Frames XILINX Maximum Permitted Frame Length The maximum legal length of a frame specified in IEEE 802 3 2005 is 1518 bytes for non VLAN tagged frames VLAN tagged frames may be extended to 1522 bytes When jumbo frame handling is disabled and the core receives a frame which exceeds the maximum legal length rx_bad_frame is asserted When jumbo frame handling is enabled frames which are longer than the legal maximum are received in the same way as shorter frames For more information about enabling and disabling jumbo frame handling see Configuration Registers on page 78 Length Type Field Error Checks Enabled Default operation is with the length type error checking enabled see Receiver Configuration on page 79 In this mode the following checks are made on all frames received If ei
16. tolerance this allows all combinations of the example designs to pass timing However these should be tightened in a real customer design as per the following syntax Manual adjustments to IDELAY values or DCM phase shift requirements may be required to meet these constraints see the following family specific sections for details TIMEGRP IN GMII OFFSET IN 2 ns VALID 2 ns BEFORE gmii rx clk Spartan 3 Spartan 3E Spartan 3A and Virtex 4 Devices The GMII design uses a DCM on the receiver clock domain for Spartan 3 Spartan 3E Spartan 3A and Virtex 4 devices Phase shifting is then applied to the DCM to align the resultant clock so that it will correctly sample the 2 ns GMII data valid window at the input flip flops 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 97 UG144 April 24 2009 EZ XILINX 98 DISCONTINUED PRODUCT Chapter 9 Constraining the Core The fixed phase shift is applied to the DCM using the following UCF syntax INST gmii interface gmii rxc dcm CLKOUT PHASE SHIFT FIXED INST gmii interface gmii rxc dcm PHASE SHIFT 0 The value of PHASE SHIFT is preconfigured in the example designs to meet the setup and hold constraints for the example GMII pinout in the particular device The setup hold timing which is achieved after place and route is reported in the data sheet section of the TRCE report created by the implement script For customers fixing their own pinout th
17. 141 R gmii rx clk bufg 0 000 gmii rxd 3 1 525 R 0 135 R gmii rx clk bufg 0 000 gmii rxd 4 1 515 R 0 125 R gmii rx clk bufg 0 000 gmii rxd 5 1 515 R 0 125 R gmii rx clk bufg 0 000 gmii rxd 6 1 520 R 0 130 R gmii rx clk bufg 0 000 gmii rxd 7 L 520 R 0 130 R gmii rx clk bufg 0 000 Virtex 5 devices with Delayed Data Control Setup and Hold results for the GMII input bus can be found in the data sheet section of the Timing Report The results are self explanatory and it is easy to see how they relate to Figure 9 1 Here follows an example for the GMII report from a Virtex 5 device The implementation requires 1 962 ns of setup this is less than the 2 ns required so there is slack The implementation requires 0 008 ns of hold this is less than the 0 ns required so there is slack 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 99 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 9 Constraining the Core Data Sheet report All values displayed in nanoseconds ns Setup Hold to clock gmii_rx_clk 2 4R 4 4 4 c Setup to Hold to Clock Source clk edge clk edge Internal Clock s Phase 2 4R 4 4 4 c gmii rx dv 1 955 R 0 017 R gmii rx clk bufg 0 000
18. 5s cv9h0ivyidiny i sti bye eer ie ER ae 39 Normal Frame Reception 0 0 0 6c 39 rx good frame rx bad frametiming 0 0 e eee eee ee 40 Frame Reception with Errors 0 0 eens 41 Client Supplied FCS Passing 2 0 6 6 cece ehe rns 42 VLAN Tagged Frames ceret eeee eee a ee tee Fed Ve eee ae de EAs 42 Maximum Permitted Frame Length 2 ccc eee ees 43 Length Type Field Error Checks 00 0 ees 43 Address PIU ss euntes tad tea Boe b buceo br ost ipae e Mittin es 44 Receiver Statistics Vector iiis csid se eec ee ee aer Rea a RT dor aan 44 Transmitting Outbound Frames 0 0 eon eee 47 Normal Frame Transmission s s uas cece ccc en 47 Padding s scite toss svewdowes sehr chaser beg iibi dees rie d apa teeta 47 Client Supplied FCS Passing sssssssseeeessees e 48 Client Underr n ica e rw yx Rr HU y eR gar EY T Y 48 VLAN Tagged Frames see so eee be sees eid ees E Re eyes 49 Maximum Permitted Frame Length 0 6 ccc nee 49 Inter Frame Gap Adjustment 2 2 0 066 ccc nen nnn ee 49 Transmitter Statistics Vectori ressorton tenets 50 Chapter 6 Using Flow Control Overview of Flow Control 2rd rrr Rr Rara acted a 53 Flow Control Requirement ssssssssesee ee 53 Flow Control Basics Ra rre hr Rr rex ERES EE Ip P p YE EN 54 Pause Control Frames ssscerke rer emp E EES bee ie eerie bres 55 Flow Control Operation of the GEMAC 0 56
19. 6 06666 c cece 55 Figure 6 3 Pause Request Timing 06 6 6 cece eee e 56 Figure 6 4 Flow Control Implementation Triggered from FIFO Occupancy 59 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com UG144 April 24 2009 EZ XILINX 10 DISCONTINUED PRODUCT Chapter 7 Using the Physical Side Interface Figure 7 1 External GMII Transmitter Logic 0 nananana arenen 62 Figure 7 2 External GMII Receiver Logic for Spartan 3 Spartan 3E and Spartan 3A Devices is dass trir RI A PENA RPG x LEER REFERO EPI Y 63 Figure 7 3 External GMII Receiver Logic for Virtex 5 Devices unanunua 65 Figure 7 4 External RGMII Transmitter Logic 0 occ cece eee eee 66 Figure 7 5 External RGMII Transmitter Logic in Virtex 4 Devices 68 Figure 7 6 External RGMII Transmitter Logic in Virtex 5 Devices 69 Figure 7 7 External RGMII Receiver Logic sssssseeeeseeeeeeeee 71 Figure 7 8 External RGMII Receiver Logic for Virtex 4 Devices issus 73 Figure 7 9 External RGMII Receiver Logic for Virtex 5 Devices 74 Figure 7 10 RGMII Inband Status Decoding Logic 75 Figure 7 11 Creating an External MDIO Interface 000005 76 Chapter 8 Configuration and Status Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 6 Configuration Register Write Tim
20. 7 Table 8 7 Management Configuration Word Default Bits Value Description 4 0 All 0s Clock Divide 4 0 This value enters a logical equation which enables the mdc frequency to be set as a divided down ratio of the host_clk frequency 5 0 MDIO Enable When this bit is 1 the MDIO interface can be used to access attached PHY devices When this bit is 0 the MDIO interface is disabled and the MDIO signals remain inactive 31 6 n a Reserved Address Filter Configuration Table 8 8 through Table 8 12 describe the registers used to access the Address Filter configuration when the GEMAC core implemented with an Address Filter The register contents for the two unicast address registers are found in Table 8 8 and Table 8 9 Table 8 8 Unicast Address Word 0 Default Bits Value Description 31 0 All 0s Address filter unicast address 31 0 The address is ordered so the first byte received is the lowest positioned byte in the register for example a MAC address of AA BB CC DD EE FF would be stored in Address 47 0 as OXFFEEDDCCBBAA Table 8 9 Unicast Address Word 1 Default Bits Value Description 15 0 All Os Address filter unicast address 47 32 31 16 N A Reserved 82 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Using the Optional Management Interface EZ XILINX The Address Filter can be programmed to respond to four separate additional addresses st
21. Configuration set to 1 the transmitter allows the Word bit 27 transmission of VLAN tagged frames 57 Transmitter gtx clk Transmitter Enable When this bit is 1 the Configuration transmitter will be operational When it is 0 Word bit 28 the transmitter is disabled 58 Transmitter gtx_clk Transmitter In Band FCS Enable When this Configuration bit is 1 the MAC transmitter will expect the Word bit 29 FCS field to be pass in by the client When it is 0 the MAC transmitter will append padding as required compute the FCS and append it to the frame 59 Transmitter gtx_clk Transmitter Jumbo Frame Enable When this Configuration bit is 1 the MAC transmitter will allow Word bit 30 frames larger than the maximum legal frame length specified in IEEE 802 3 2005 to be sent When set to 0 the MAC transmitter will only allow frames up to the legal maximum to be sent 60 Transmitter n a Transmitter Reset When this bit is 1 the Configuration MAC transmitter is held in reset This signal Word bit 31 is an input to the reset circuit for the transmitter block 61 Flow Control gtx_clk Transmit Flow Control Enable When this Configuration bit is 1 asserting the pause_req signal Word bit 29 causes the GEMAC core to send a flow control frame out from the transmitter When this bit is 0 asserting the pause_req signal will have no effect 1 Gigabit Ethernet MAC v8 5 Us
22. Degree of Difficulty for Various Implementations Device Family Difficulty Spartan 3A 3AN 3A DSP platforms Difficult Spartan 3E platform Difficult Spartan 3 device Difficult Virtex 4 device Easy Virtex 5 device Easy Keep it Registered To simplify timing and increase system performance in an FPGA design keep all inputs and outputs registered between the user application and the core This means that all inputs and outputs from the user application should come from or connect to a flip flop While registering signals may not be possible for all paths it simplifies timing analysis and makes it easier for the Xilinx tools to place and route the design Recognize Timing Critical Signals The UCF provided with the example design identifies the critical signals and timing constraints that should be applied See Chapter 9 Constraining the Core Use Supported Design Flows The core is pre synthesized and delivered as an NGC netlist The example implementation scripts provided use XST 11 1 as the synthesis tool for the HDL example design Other synthesis tools may be used for the user application logic The core is always unknown to the synthesis tool and should appear as a black box For post synthesis only ISE 11 1 tools are supported Make Only Allowed Modifications 38 The GEMAC core should not be modified by you Any modifications may have adverse effects on system timing and protocol compliance Support
23. Engine Transmitter Interface o S E Flow Control Ss 5 To Physical o o Sublayers Client Receive Engine Receiver Interface Optional Address Filter Optional Management Client Management Configuration Interface Figure 2 1 Block Diagram 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 21 UG144 April 24 2009 DISCONTINUED PRODUCT x XILINX Chapter 2 Core Architecture Core Components Transmit Engine The Transmit Engine accepts Ethernet frame data from the Client Transmitter Interface adds the preamble field to the start of the frame adds padding bytes if required to ensure that the frame meets the minimum frame length requirements and adds the frame check sequence when configured to do so The transmitter also ensures that the inter frame spacing between successive frames is at least the minimum specified The frame is then converted into a format that is compatible with the GMII and sent to the GMII Block Receive Engine The Receive Engine accepts Ethernet frame data from the GMII Block removes the preamble field at the start of the frame removes padding bytes and Frame Check Sequence if required and when configured to do so The receiver also performs error detection on the received frame using information such as the frame check sequence field received GMII error codes and legal frame size boundaries Flow Control The Flow Control block is designed to clause 31 of the IEEE 802 3 2005
24. FCS Enable When this bit Configuration is 1 the MAC receiver will pass the FCS Word 1 bit 29 field up to the client When it is 0 the MAC receiver will not pass the FCS field In both cases the FCS field will be verified on the frame 52 Receiver gmii_rx_clk Receiver Jumbo Frame Enable When this bit Configuration is 0 the receiver will not pass frames longer Word 1 bit 30 than the maximum legal frame size specified in IEEE 802 3 2005 At 1 the receiver will not have an upper limit on frame size www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Access without the Management Interface EZ XILINX Table 8 13 Configuration Vector Bit Definition Continued Configuration Bit s Register cross Clock Description reference 53 Receiver n a Receiver Reset When this bit is 1 the Configuration receiver is held in reset This signal is an input Word 1 bit 31 to the reset circuit for the receiver block 54 Transmitter gtx clk Transmitter Interframe Gap Adjust Enable Configuration If 1 then the transmitter will read the value Word bit 25 of the tx ifg delay port and set the interframe gap accordingly If 0 the transmitter will always insert at least the legal minimum interframe gap 55 n a n a This input is unused 56 Transmitter gtx_clk Transmitter VLAN Enable When this bit is
25. Package and Speedgrade Selection 0 000 cece eee eee eee 93 I O Location Constraints 0 0 000 e rs 93 Placement Constraints 2 212i 9 4p a a yer E ER ERA cade e Ra ced io ded d 93 Timing Constraints sssaaa e A E E EEE EE n nn 93 Constraints when Implementing an External GMII ssssssseeseees 96 Understanding Timing Reports for GMII Setup Hold Timing 99 Constraints when Implementing an External RGMII sssseeseeess 101 Understanding Timing Reports for RGMII Setup Hold timing 105 Chapter 10 Clocking and Resetting Clocking the Core oe ii ob ore EPOR Hel dace eie ado ait aces 109 With Internal GMII iesierzitRXTFer 434g gr e REPRE CE EH e oe RR dn 109 With External GMII corradii i aA EEE err Rete ee eC EE EE RET 109 With RGMIE eeiece RR ERR HERE UR DR ange 6 tend HOS RR RR ede Rer 110 Multiple CORES s hee vireed dde ed oe eed Qi bia i baw UE T IE EH Et doled 110 With External GMIL eseeeeeeeeeeeeeeee e hh haee 110 EON Ue trace 8 PU nara late ceca EE ete aw E EE E A 111 Reset CoOmmitions sci cis icdin reor CROIRE Ee EA HEAR RE OR toed 112 Chapter 11 Interfacing to Other Cores Ethernet 1000Base X PCS PMA or SGMII Core s esses 113 Integration to Provide 1000BASE X PCS with TBI 0 0000s 114 Integration to Provide 1000BASE X PCS and PMA using a RocketIO Transceiver 115 Integration to Provide SGMII Functionality
26. Transmitting a PAUSE Control Frame 2 2 ence eee 56 Receiving a Pause Control Frame 0 666 57 Flow Control Implementation Example 0 0 0 0 e cece eee eee 58 Chapter 7 Using the Physical Side Interface Implementing External GMIL iid cccceeedecinn aie deer RAE REFER VER KEEN RA 61 GMI Transmitter Logic 0 0 2 ete 61 GMIERecetver LO GIG eee epe been hd cree healed acere reise 63 Implementing External RGMII sess 66 RGMII Transmitter LOGIC ssesesee sere hebr mehr b a akon nb dede 66 RGMII Receiver Logic 6 IH eens 70 RGMII Inband Status Decoding Logic 6 6 6 6 cece eh 75 Using the MDIO interlace aii is eese een annur rruen EC ER ER ines 76 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide DISCONTINUED PRODUCT 7 XILINX Connecting the MDIO to an Internally Integrated PHY 005 76 Connecting the MDIO to an External PHY sess 76 Chapter 8 Configuration and Status Using the Optional Management Interface susssslsssseseeeesess 77 Host Clock Frequency 23 ez e cbe tbe Ree eaa ERE EEE E E E E a 77 Configuration Registers cnore e E EE E ER EE RE 78 MDIO Intertace kesr cnis sce nS ade Y Rr RE Ea e PE da reges 86 Access without the Management Interface 00 00 e cece eee 90 Chapter 9 Constraining the Core Required Constraints us ouo o he Coen ARE Kenner BRI T E d en E E db ica 93 Device
27. Tri state buffer to create a bi directional mdio signal suitable for connection to an external PHY 30 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 3 Generating the Core The GEMAC core is generated through the Xilinx CORE Generator using a graphical user interface GUI This chapter describes the GUI options used to generate and customize the core Graphical User Interface Figure 3 1 shows the main GEMAC core user GUI screen Gigabit Ethernet MAC lagi PE Gigabit Ethernet MAC MIL TXD 7 0 Component Name gig eth mac v8 5 GMII TX EN Options GMII TX ER V Use Management Interface T GMII RX CLK TX_IFG_DELAY 7 0 GMII RXD 7 0 TX UNDERRUN GMII RX DV TACK GMII RX ER Example Design will implement IEEE802 3 clause 35 Gigabit Media Independent Interface GMII TX STATISTICS VECTOR 21 0 TX STATISTICS MALID Address Filter Options Physical Interface om O Remi v Use Address Filter RX DATA 7 0 RX DATA MALID RX GOOD FRAME RX BAD FRAME RX STATISTICS VECTOR 2 0 RX STATISTICS NALID Number of Address Table Entries 4 Range 0 4 PAUSE REO PAUSE VAL 1 0 HOST CLK HOST OPCODE 1 0 HOST ADDR 0 HOST WR DATA 1 0 HOST MIIM SEL Datasheet Generate Cancel v HOST_REQ Figure 3 1 1 Gigabit Ethernet MAC Main Screen For general help starting an
28. UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 10 Clocking and Resetting This chapter describes clock management considerations that are associated with implementing the GEMAC core It describes the clock management logic for all implementations of the core and how clock management logic can be shared across multiple instantiations of the core The reset circuitry within the core is also described Clocking the Core With Internal GMII When the GMII style interface of the core is used as an internal interface for example with an internally connected PHY core it is likely that gtx_clk and gmii_rx_clk willbe derived from the same clock source See Chapter 11 Interfacing to Other Cores for an example With External GMII Figure 10 1 illustrates the clock management used with an external GMII interface All clocks illustrated have a frequency of 125 MHz The clock gtx c1k must be provided to the GEMAC core This is a high quality clock that satisfies the IEEE 802 3 2005 requirements It is expected that this clock will be derived from an external oscillator and connected into the device through an IBUFG as illustrated in Figure 10 1 When an external GMIL gmii rx clk will usually be derived from a different clock sourcetogtx clk Inthiscase gmii rx clkisreceived through an IBUFG This clock is then usually routed onto a global clock network by connecting it to a BUFG The resulting global clock is used
29. are copied into the following descriptions to provide examples These examples should be studied in conjunction with the HDL source code for the example design 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 93 UG144 April 24 2009 XILINX 94 DISCONTINUED PRODUCT Chapter 9 Constraining the Core PERIOD Constraints for Clock Nets gtx_clk The clock provided to gtx_c1k must be constrained for a clock frequency of 125 MHz The following UCF syntax shows the necessary constraints being applied to the gtx clk bufg signal which is routed to the gtx c1k port of the core Set the Transmitter clock period constraints please do not relax NET gtx clk bufg TNM NET clk tx TIMEGRP tx clock Clk tx TIMESPEC TS tx clk PERIOD tx clock 8000 ps HIGH 50 gmii_rx_clk for GMII Example Designs The clock provided to gmii rx clk must be constrained for a clock frequency of 125 MHz The following UCF syntax shows the necessary constraints being applied to the clock signal which is routed to the gmii rx clk port of the core Set the Receiver clock period constraints please do not relax NET gmii rx clk TNM NET gmii rx clk TIMESPEC TS gmii rx clk PERIOD gmii rx clk 8000 ps HIGH 50 TIMEGRP rx clock gmii rx clk rgmii rxc for RGMII Example Designs The receiver clock provided by the RGMII must be constrained for a clock frequency of 125
30. by all MAC receiver logic Some families contain a DCM on the gmii rx clk path to meet GMII setup and hold requirements see Spartan 3 Spartan 3E Spartan 3A and Virtex 4 Devices 1 Gigabit Ethernet MAC IBUFG BUFG BUFG IBUFG gmii rx clk Figure 10 1 Clock Management Logic with External GMII 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 109 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 10 Clocking and Resetting With RGMII Standard Clocking Scheme Figure 10 2 illustrates the clock management used with an external RGMII interface All clocks illustrated have a frequency of 125 MHz The gtx_c1k clock must be provided to the GEMAC core This is a high quality clock that satisfies IEEE 802 3 2005 requirements It is expected that this clock will be derived from an external oscillator and connected into the device through an IBUFG as illustrated in Figure 10 2 This clock is used as the input clock to a DCM from where phase shifted clock signals are generated for use in the RGMII transmitter logic The zero phase shifted clock is used as the input gtx_c1k to the GEMAC core The receiver clock rgmii rxc is usually derived from a different clock source to gtx_clk In this case rgmii rxc will be received through an IBUFG This clock is routed into a DCM where it is used to generate phase shifted clock signals for use in the RGMII receiver logic A fixed phase shift value is applied to the DCM
31. consume core packets and how to operate the Management Interface Chapter 9 Constraining the Core describes the constraints associated with the core Chapter 10 Clocking and Resetting discusses special design considerations associated with clock management logic including the Gigabit Media Independent Interface GMII and Reduced Gigabit Media Independent Interface RGMITI options Chapter 11 Interfacing to Other Cores describes how to interface the 1 Gigabit Ethernet MAC core to the Ethernet 1000BASE X PCS PMA or SGMII core and the Ethernet Statistics core Chapter 12 Implementing Your Design provides instructions for how to set up synthesis simulation and implementation environments and how to generate a bitstream through the design flow Appendix A Using the Client Side FIFO describes the FIFO provided in the example design that accompanies the GEMAC core Appendix B Core Verification Compliance and Interoperability describes how the core was verified and certified for compliance Appendix C Calculating DCM Phase Shifting provides information about how to calculate the system timing requirements when using DCMs with the core Appendix D Core Latency describes the latency of the core 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 15 UG144 April 24 2009 EZ XILINX Conventions 16 DISCONTINUED PRODUCT Typographical Preface About This Guide
32. core into your VHDL source After your entire design is complete create e An XST project file top_level_module_name prj listing all the user source code files e An XST script file top_level_module_name scr containing your required synthesis options 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 123 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 12 Implementing Your Design To synthesize the design run xst ifn top level_module_name scr See the XST User Guide for more information on creating project and synthesis script files and running the xst program XST Verilog A module declaration for the GEMAC core is provided in the CORE Generator project directory component name example design component name mod v Use this module to help instance the GEMAC core into your Verilog source After your entire design is complete create e An XST project file top 1evel module name pr j listing all the user source code files Make sure you include XILINX verilog src iSE unisim comp v and component name example design component name mod v as the first two files in the project list e An XST script file top 1evel module name scr containing your required synthesis options To synthesize the design run xst ifn top level module name scr See the XST User Guide for more information on creating project and synthesis script files and running the xst program Implementati
33. create a Timing Report file TWR derived from static timing analysis of the Physical Design file NCD The analysis is typically based on constraints included in the optional PCF file An example of the trce command is trce o top level module name twr top level module name ncd top level module name pcf Generating a Bitstream To create the configuration bitstream BIT file based on the contents of a physical implementation file NCD the bitgen command must be executed The BIT file defines the behavior of the programmed FPGA An example of the bitgen command is bitgen w top level module name ncd Post Implementation Simulation The purpose of post implementation simulation is to verify that the design as implemented in the FPGA works as expected Generating a Simulation Model Run the netgen command to generate a chip level simulation netlist for your design VHDL netgen sim ofmt vhdl ngm top level module name map ngm tm netlist top level module name ncd top level module name postimp vhd Verilog netgen sim ofmt verilog ngm top level module name map ngm tm netlist top level module name ncd top level module name postimp v 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 125 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 12 Implementing Your Design Using the Model For information about setting up your simulator to use the
34. critical for sampling high speed source synchronous signals such as RGMII For statically aligned systems the DCM output clock phase offset as set by the phase shift value is a critical part of the system as is the requirement that the PCB is designed with precise delay and impedance matching for all the GMII RGMII receiver data bus and control signals You must determine the best DCM setting phase shift to ensure that the target system has the maximum system margin to perform across voltage temperature and process multiple chips variations Testing the system to determine the best DCM phase shift setting has the added advantage of providing a benchmark of the system margin based on the UI unit interval or bit time System margin is defined as the following System Margin ps Ul ps working phase shift range 128 Finding the Ideal Phase Shift Xilinx cannot recommend a singular phase shift value that is effective across all hardware platforms and does not recommend attempting to determine the phase shift setting empirically In addition to the clock to data phase relationship other factors such as package flight time package skew and clock routing delays internal to the device affect the clock to data relationship at the sample point in the IOB and are difficult to characterize Xilinx recommends extensive investigation of the phase shift setting during hardware integration and debugging The phase shift settings pro
35. frame length requirements as the GEMAC core will not perform any padding of the payload See Configuration Registers on page 78 tx_data 7 0 a a ore tx_data_valid tx_ack J tx underrun 7 7 Figure 5 7 Frame Transmission with Client supplied FCS Client Underrun Figure 5 8 illustrates the timing of an aborted transfer An example of this situation is a FIFO connected to the client interface that empties before a frame transfer is complete When the client asserts tx underrun during a frame transmission the GEMAC core inserts an error code to corrupt the current frame and then falls back to idle transmission It is the responsibility of the client to re queue the aborted frame for transmission When an underrun occurs tx data valid may be asserted on the clock cycle after the tx underrun assertion to request a new transmission tx data 7 0 pa sa ur hk AA tx_data_valid tx_ack J tx underrun 7 7 J Figure 5 8 Frame Transmission with Underrun www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Transmitting Outbound Frames XILINX VLAN Tagged Frames Figure 5 9 illustrates transmission of a VLAN tagged frame if enabled The handshaking signals across the interface do not change however the VLAN type tag 81 00 must be supplied by the client to signify that the frame is VLAN tagged The client also supplies t
36. gmii rxd reg 7 TNM rgmii rising INST rgmii interface gmii rx er reg TNM rgmii rising TIMESPEC TS rgmii falling to rising FROM rgmii falling TO rgmii rising 3200 ps 104 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Required Constraints XILINX Understanding Timing Reports for RGMII Setup Hold timing Non Virtex 5 Devices Setup and Hold results for the RGMII input bus can be found in the data sheet section of the Timing Report The results are self explanatory and it is easy to see how they relate to Figure 9 3 Following is an example for the RGMII report from a Virtex 4 device Each Input lists two sets of values one corresponding to the ve edge of the clock and one to the ve edge The first set listed corresponds to ve edge which occurs at time 4 ns The implementation requires 0 648 ns of setup to the ve edge and 0 661 ns to the ve edge This is less than the 1 ns required so there is slack The implementation requires 0 300 ns of hold to the ve edge and 0 316 ns to the ve edge This is less than the 1 ns required so there is slack Data Sheet report All values displayed in nanoseconds ns Setup Hold to clock rgmii rxc Setup to Hold to Clock Source clk edge clk edge Internal Clock s Phase
37. gmii tx clk willoccur in the centre of the data valid window therefore maximizing setup and hold times across the interface 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 61 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 7 Using the Physical Side Interface IOB LOGIC FDDRRSE IOB LOGIC l BUFG o l gt gtx_clk_bufg i i OBU l gmii tx clk OPAD gtx clk i r IBUFG o BUF gmii txd 0 l ii i ii txd 0 gmii txd 0 gmii txd int 0 I B gmii txd reg O CTS gt l gmii_tx_en gmii_tx_en_reg i o I c m gmii tx on gmii tx en int gmii_tx_er i gmii tx er int gmii tx er reg gmii tx er ai OPAD gt l Figure 7 1 External GMII Transmitter Logic l y 62 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Implementing External GMII XILINX GMII Receiver Logic Spartan 3 Spartan 3E Spartan 3A and Virtex 4 Devices A DCM must be used on the gmii rx clkclock path as illustrated in Figure 7 2 to meet the input setup and hold requirements for GMII This is performed by the example designs delivered with the core all signal names and logic match Figure 7 2 This DCM circuitry may optionally be used in other families Phase shifting may then be applied to the DCM to fine tune the setup and hold times at the
38. pre implemented model see the Xilinx Synthesis and Verification Design Guide included in your Xilinx software installation Other Implementation Information For more information about using the Xilinx implementation tool flow including command line switches and options see the Xilinx ISE software manuals 126 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 XILINX DISCONTINUED PRODUCT Appendix A Using the Client Side FIFO The example design provided with the GEMAC core contains a FIFO used on the client side of the core The source code for the FIFO is provided and may be used and adjusted for user applications The 10 Mbps 100 Mbps 1 Gbps Ethernet FIFO is designed for use with the GEMAC and Tri Mode Ethernet MAC TEMAC cores The FIFO directly interfaces to the MAC client interface providing a buffer between the MAC and the user s logic The FIFO implements a LocalLink user interface see Overview of LocalLink Interface on page 130 allowing a direct connection to other LocalLink modules or the user s logic The 10 Mbps 100 Mbps 1 Gbps Ethernet FIFO consists of independent transmit and receive FIFOs embedded in a top level wrapper Figure A 1 shows how the FIFO fits into a typical implementation LocalLink Interface Client Interface GMII RGMII Xilinx FPGA 10 Mbps pum 100 Mbps 1 SUUM MAC 1 Gbps org Ethernet FIFO 1000BASE T Switch or PHY bs opper Pair
39. see Flow Control Configuration on page 81 Any type of control frame can be transmitted through the core through the client interface using the same transmission procedure as a standard Ethernet frame see Transmitting Outbound Frames on page 47 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Flow Control Operation of the GEMAC XILINX Receiving a Pause Control Frame Core Initiated Response to a Pause Request An error free control frame is a received frame matching the format of Figure 6 2 It must pass all standard receiver frame checks for example FCS field checking In addition the control frame received must be exactly 64 bytes in length from destination address through to the FCS field inclusive this is minimum legal Ethernet MAC frame size and the defined size for control frames Any control frame received that does not conform to these checks contains an error and is passed to the receiver client with the rx_bad_frame signal asserted Pause Frame Reception Disabled When pause control reception is disabled an error free control frame is received through the client interface with rx_good_frame asserted see Flow Control Configuration on page 81 In this way the frame is passed to the client logic for interpretation see Client Initiated Response to a Pause Request on page 57 Pause Frame Reception Enabled When pause control recepti
40. standard The MAC may be configured to send pause frames and to act upon their reception These two behaviors can be configured independently Address Filter The Address Filter checks the address of incoming frames into the receiver If the Address Filter is enabled the device will not pass frames that do not contain one of a set of known addresses to the client Management Interface The optional processor independent Management Interface has standard address data and control signals It may be used as is or you can apply a logical shim to interface to common bus architectures See Chapter 8 Configuration and Status This interface is used to access the following blocks e Configuration Register After power up or reset the client may reconfigure the core parameters from their defaults Configuration changes can be written at any time e MDIO Interface The Management Interface is also used to access the MDIO interface of the GEMAC core this interface is typically connected to the MDIO port of a physical layer device PHY to access its configuration and status registers The MDIO format is defined in IEEE802 3 clause 22 GMII Block This implements GMII style signaling for the physical interface of the core and is typically attached to a physical layer device PHY either off chip or internally integrated 22 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Core I
41. stored or pre set addresses in the Address Filter If the Address Filter is omitted from the core or is configured in promiscuous mode this line is held high 26 Reserved Always at logic 0 25 Length Type Out of Range If the length type field contained a length value that did not match the number of MAC client data bytes received and the length type field checks are enabled then this bit is asserted This bit is also asserted if the length type field is less than 46 and the frame is not padded to exactly 64 bytes This is independent of whether or not the length type field checks are enabled 24 Bad Opcode Asserted if the previous frame was error free and contained the special control frame identifier in the length type field but contained an opcode that is unsupported by the MAC any opcode other than Pause 23 Flow Control Frame Asserted if the previous frame met all the following conditions e error free e contained the special control frame identifier in the length type field e contained a destination address that matched either the MAC Control Multicast Address or the configured source address of the MAC e contained the supported Pause opcode e was acted upon by the MAC 22 Byte Valid Asserted if a MAC frame byte DA to FCS inclusive is in the process of being received This is valid on every clock cycle Do not use this as an enable signal to indicate that data
42. the remainder of the data for the frame The end of frame is signalled to the GEMAC core by taking tx data validlow For maximum flexibility in switching and routing applications the Ethernet frame parameters destination address source address length type and optionally FCS are encoded within the same data stream that the frame payload is transferred upon rather than on separate ports This is illustrated in the timing diagrams Definitions of the abbreviations used in the timing diagrams are defined in Table 5 1 DA SA l L T DATA itx data valid tx_ack BEN M tx underrun S e E Figure 5 6 Normal Frame Transmission When fewer than 46 bytes of data are supplied by the client to the GEMAC core the transmitter module will add padding up to the minimum frame length The exception to this is when the GEMAC core is configured for client passed FCS in this case the client must also supply the padding to maintain the minimum frame length See Client Supplied FCS Passing for more information 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 47 UG144 April 24 2009 DISCONTINUED PRODUCT Chapter 5 Using the Client Side Data Path Client Supplied FCS Passing The transmission timing depicted in Figure 5 7 shows the GEMAC core configured to have the FCS field passed in by the client In this case it is the responsibility of the client to ensure that the frame meets the Ethernet minimum
43. to interface the GEMAC core to the Ethernet 1000BASE X PCS PMA or SGMII core when used in 1000BASE X mode with PMA using the device specific RocketIO transceiver brefclkp IBUFGDS brefclkn 125MHz component name block Block Level from example design 1 Gigabit Ethernet Ethernet 1000BASE X MAC PCS PMA or SGMII LogiCORE LogiCORE Virtex 5 GTP RocketlO TXOUTCLKO gmii rx clk 4 TXUSRCLKO gmii_txd 7 0 TXUSRCLK20 gmii_tx_en RXUSRCLKO gmii_tx_er userclk2 y RXUSRCLK20 gmii_rxd 7 0 gmii_rxd 7 0 gmii_rx_dv gmii_rx_dv ii rX gmii rx er RocketlO I F mdio tri no mdio tri connection Figure 11 3 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS and PMA using a RocketlO transceiver Figure 11 3 illustrates the following e Direct internal connections are made between the GMII interfaces between the two cores e If the GEMAC has been generated with the optional Management Interface the MDIO port can be connected to that of the Ethernet 1000BASE X PCS PMA or SGMII core to access its embedded configuration and status registers See Using the Optional Management Interface 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 117 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 11 Interfacing to Other Cores e Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE X PCS PMA or SGMII core the entire GMII is synchronous to a single clock do
44. to meet RGMII setup and hold requirements See Appendix C Calculating DCM Phase Shifting The zero clock is used as the input gmii rx clktothe GEMAC core 1 Gigabit Ethernet DCM BUFG MAC Core BUFG DCM gtx clk gmii rx clk lt gtx_clk rgmii_rxc RGMII Tx Logic RGMII Rx Logic Figure 10 2 Clock Management with External RGMII Multiple Cores With External GMII Figure 10 3 illustrates how to share clock resources across multiple instantiations of the core when using the optional GMII gtx c1k may be shared between multiple cores as illustrated resulting in a common transmitter clock domain across the device A common receiver clock domain is usually not possible as each core will receive an independent receiver clock from the PHY attached to the other end of the GMII As illustrated in Figure 10 3 this results in a separate receiver clock domain for each core 110 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Multiple Cores XILINX Note Although not illustrated if the optional Management Interface is used host_c1k can also be shared between cores 1 Gigabit Ethernet MAC IBUFG BUFG IBUFG BUFG gmii_rx_clk1 1 Gigabit Ethernet MAC BUFG IBUFG gtx_clk gmii rx clk gmii rx clk2 Figure 10 3 Clock Management Logic with External GMII Multiple Cores With RGMII Figure 10 4 illustrates sharing clock resources across m
45. 101 UG144 April 24 2009 XILINX 102 DISCONTINUED PRODUCT Chapter 9 Constraining the Core The RGMII v2 0 is a 1 5 volt signal level interface The 1 5 volt HSTL Class I SelectIO standard is used for RGMII interface pins Use the following constraints with the device IO Banking rules The IO slew rate is set to fast to ensure that the interface can meet setup and hold times INST rgmii txd IOSTANDARD HSTL I INST rgmii tx ctl IOSTANDARD HSTL I INST rgmii rxd IOSTANDARD HSTL I INST rgmii rx ctl IOSTANDARD HSTL I INST rgmii txc IOSTANDARD HSTL I INST rgmii rxc IOSTANDARD HSTL I INST rgmii txd SLEW FAST INST rgmii tx ctl SLEW FAST INST rgmii txc SLEW FAST In addition the example design provides pad locking on the RGMII for several families This is provided as a guideline only there are no specific I O location constraints for this core RGMII Input Setup Hold Timing Figure 9 3 and Table 9 2 illustrate the setup and hold time window for the input RGMII signals This is the worst case data valid window presented to the FPGA device pins RGMII_RXC 0N Ao RGMII RXD 3 0 RGMII_RX_CTL setur thoro thoro Figure 9 3 Input RGMII Timing The 2 ns data valid window which is presented across the RGMII input bus must be correctly sampled on both clock edges by the FPGA devices Table 9 2 Input RGM
46. 144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 6 Using Flow Control This chapter describes the operation of the flow control logic of the GEMAC core The flow control block is designed to clause 31 of the IEEE 802 3 2005 standard The MAC may be configured to transmit pause requests and to act on their reception these modes of operation can be independently enabled or disabled See Flow Control Configuration on page 81 Overview of Flow Control Flow Control Requirement Figure 6 1 illustrates the requirements for Flow Control Client Logic Link Partner MAC 125MHz 100ppm c 2 2 foo 2 a 2 lt 125MHz 100ppm Figure 6 1 Requirement for Flow Control 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 53 UG144 April 24 2009 EZ XILINX DISCONTINUED PRODUCT Chapter 6 Using Flow Control The user MAC on the left side has a reference clock slightly slower than the nominal 125 MHz The link partner MAC on the right side has a reference clock slightly faster than the nominal 125 MHz As a result the user MAC receives data at a faster line rate than that at which it can transmit The MAC on the left is shown performing a loopback implementation which results in the FIFO filling up over time Without Flow Control this FIFO will eventually fill and overflow resulting in the corruption or loss of Ethernet frames Enabling Flow Control in the MAC provides a mechanism to s
47. 384 0x387 Unicast Address Word 1 if Address Filter is present 0x388 0x38B Address Table Configuration Word 0 if Address Filter is present 0x38C 0x38F Address Table Configuration Word 1 if Address Filter is present 0x390 0x393 Address Filter Mode if Address Filter is present www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Using the Optional Management Interface Receiver Configuration UG144 April 24 2009 The register contents for the two receiver configuration words are shown in Table 8 3 and Table 8 4 Table 8 3 Receiver Configuration Word 0 Default ae Bit Value Description 31 0 All 0s Pause frame MAC Source Address 31 0 This address is used by the MAC to match against the destination address of any incoming flow control frames It is also used by the flow control block as the source address SA for any outbound flow control frames See Chapter 6 Using Flow Control The address is ordered so the first byte transmitted received is the lowest positioned byte in the register for example a MAC address of AA BB CC DD EE FF would be stored in Address 47 0 as OxFFEEDDCCBBAA Table 8 4 Receiver Configuration Word 1 Default um Bit Value Description 15 0 All 0s Pause frame MAC Source Address 47 32 23 16 n a Reserved 24 0 Control Frame Len
48. AY VALUE 25 INST rgmii interface delay rgmii tx clk DELAY SRC O INST rgmii interface delay rgmii rx ctl IDELAY TYPE FIXED INST rgmii interface delay rgmii rx ctl IDELAY VALUE 20 INST rgmii interface delay rgmii rx ctl DELAY SRC I The value of IDELAY VALUE is preconfigured in the example designs to meet the setup and hold constraints for the example RGMII pinout in the particular device The setup hold timing which is achieved after place and route is reported in the data sheet section of the TRCE report created by the implement script When IDELAY or IODELAY primitives are instantiated with a fixed delay attribute an IDELAYCTRL component must be also instantiated to continuously calibrate the individual input delay elements The IDELAYCTRL module requires a reference clock which is assumed to be an input to the example design delivered by CORE Generator The most efficient way to use the IDELAYCTRL module is to lock the placement of the instance to the clock region of the device where the IDELAY IODELAY components are placed An example LOC constraint for the IDELAYCTRL module is shown commented out in the UCE See the Virtex 5 User Guide and code comments for more information The following constraints are provided in the example design to link the instance of the IDELAYCTRL to the IODELAY components used on the RGMII These constraints aid the Xilinx tools in automatic IDELAYCTRL placement Group IODE
49. Appendix A Using the Client Side PIRE You can synthesize the entire design using any synthesis tool The GEMAC core is pre synthesized and is delivered as an NGC netlist which appears as a black box to synthesis tools Run the Xilinx tools map par and bitgen to create a bitstream that can be downloaded to a Xilinx device Care must be taken to constrain the design correctly and the UCF produced by the CORE Generator should be used as the basis for the your own UCF See Chapter 9 Constraining the Core You can simulate the entire design and download the bitstream to the target device Know the Degree of Difficulty A 1 Gigabit Ethernet MAC implementation is challenging to implement in any technology and all applications require careful attention to system performance requirements Pipelining logic mapping placement constraints and logic duplication are all methods that help boost system performance See Table 4 1 to determine the relative level of difficulty associated with the Spartan and Virtex device families These designs relate to meeting the core required system clock frequency of 125 MHz 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 37 UG144 April 24 2009 XILINX DISCONTINUED PRODUCT Chapter 4 Designing with the Core See also Appendix C Calculating DCM Phase Shifting to meet Spartan 3 Spartan 3E and Spartan 3A device setup and hold requirements for external GMII Table 4 1
50. D6 D4 D2 DO IDLE 32 bits ST OP PHYAD REGAD TA 16 bit WRITE DATA IDLE PRE Figure 8 6 MDIO Write Transaction 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 87 UG144 April 24 2009 EZ XILINX 88 DISCONTINUED PRODUCT Chapter 8 Configuration and Status Read Transaction Figure 8 7 shows a Read transaction this is defined by OP 10 The addressed MMD PHYAD device returns the 16 bit word from the register at REGAD STA drives MDIO MMD drives MDIO 1 1 D D14 D12 D10 D8 D6 D4 D2 DO ST OP PRTAD REGAD TA 16 bit READ DATA IDLE Figure 8 7 MDIO Read Transaction For details of the register map of MMD PHY layer devices and a detailed description of the operation of the MDIO Interface itself see IEEE 802 3 2005 Accessing MDIO With GEMAC More information about MDIO with GEMAC can be found in the following sections of this guide e For the GEMAC port definition of the MDIO see MDIO Interface in Chapter 2 e Connecting the MDIO to an Internally Integrated PHY on page 76 e Connecting the MDIO to an External PHY on page 76 The management interface is also used to access the MDIO interface of the GEMAC core The MDIO interface supplies a clock to the connected PHY mdc This clock is derived from the host clk signal using the value in the Clock Divide 4 0 configuration register The frequency of mdc is given by the following equation
51. E l E IBUF rgmii rx dv red rgmii rx dv ddr rgmii rx cil LE Ls gmii_rx_dv_reg l l rgmii rx ctl reg rgmii rx ctl ddr l l l l l gmii_rx_dv gmii_rx_er_reg gmii_rx_er ras fhe Figure 7 7 External RGMII Receiver Logic 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 71 UG144 April 24 2009 EZ XILINX 72 DISCONTINUED PRODUCT Chapter 7 Using the Physical Side Interface Virtex 4 Devices Figure 7 8 shows using the physical receiver interface of the core to create an external RGMIL ina Virtex 4 device The signal names and logic exactly match those delivered with the example design when RGMII is selected Figure 7 8 also shows that the input receiver signals are registered in the IOBs in IDDR components These components convert the input double data rate signals into GMII specification signals The gmii_rx_er_int signal is derived in the FPGA fabric from the outputs of the control IDDR component To achieve the required setup and hold times across the interface the DCM uses a phase shift to adjust the clock relative to the data See Appendix C Calculating DCM Phase Shifting DCM Reset circuitry A DCM reset module not illustrated in Figure 7 8 is also present and is instantiated in the example design next to the DCM Since this logic must be reliable whatever the reset locked status of the DCM the module requires a reliable reference clock In the exampl
52. ETS MAC CONTROL TRANSMITTED OPCODE TOP TO BOTTOM l MAC CONTROL l l doaTe A Lol o O Ll I i RESERVED I transmitted as zeroes l 4 OCTETS FRAME C UN C UN Figure 6 2 MAC Control Frame Format A pause control frame is a unique type of control frame identified by a defined value placed in the MAC Control opcode field Note MAC Control opcodes other than for pause flow control frames have recently been defined for Ethernet Passive Optical Networks The MAC control parameter field of the pause control frame contains a 16 bit field containing a binary value directly related to the pause duration This defines the number of pause quantum 512 bit times of the particular implementation For 1 Gigabit Ethernet asingle pause quantum corresponds to 512 ns 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 55 UG144 April 24 2009 EZ XILINX DISCONTINUED PRODUCT Chapter 6 Using Flow Control Flow Control Operation of the GEMAC 56 Transmitting a PAUSE Control Frame Core initiated Pause Request If the GEMAC core is configured to support transmit flow control the client can initiate a pause control frame by asserting pause req see Flow Control Configuration on page 81 Figure 6 3 illustrates pause request timing gtx clk pause req N Figure 6 3 Pause Request Timing This action causes the core to construct and transmit a pause control frame on the link wit
53. II Timing Symbol Min Typical Units tsETUP 1 0 2 0 ns HOLD 1 0 2 0 ns For RGMII the lower data bits rgmii_rxd 3 0 should be sampled internally on the rising edge of rgmii_rxc and the upper data bits rgmii_rxd 7 4 should be sampled internally on the falling edge of rgmii_rxc The following constraints are provided in the UCF for RGMII Example Designs These constraints invoke the tools to analyze the setup hold requirements though if failing the tools are NOT capable of fixing them meeting these constraints is a manual process see the following family specific sections for details www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Required Constraints DISCONTINUED PRODUCT EZ XILINX INST rgmii rxd TNM IN RGMII INST rgmii rx ctl TNM IN RGMII TIMEGRP DDR RISING FFS TIMEGRP DDR FALLING FALLING FFS TIMEGRP IN RGMII OFFSET IN 1 1 ns VALID 2 2 ns BEFORE rgmii rxc TIMEGRP DDR RISING TIMEGRP IN RGMII OFFSET IN 2 9 ns VALID 2 2 ns BEFORE rgmii rxc TIMEGRP DDR FALLING The constraints defined in the preceding lines have a built in 1076 tolerance this allows all combinations of the example designs to pass timing However these should be tightened in a real customer design as per the following syntax Manual adjustments to IDELAY values or DCM phase shift requirements may be required to meet these constraints see the following family specific
54. IO interface for 1 Gbps operation and slower speeds is defined in IEEE 802 3 clause 22 This is a two wire interface consisting of a clock mdc and a shared serial data line mdio An MDIO bus in a system consists of a single Station Management STA master management entity and a number of MDIO Managed Device MMD slave entities Figure 8 5 illustrates a typical system All transactions are initiated by the STA entity The GEMAC core implements a STA and can be connected to MMDs PHY devices to access their management registers 86 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Using the Optional Management Interface XILINX STA Figure 8 5 Typical MDIO managed System There are two different transaction types of MDIO for write and read They are described in this section Abbreviations Used The following abbreviations apply for the remainder of this chapter e PRE Preamble e ST Start of frame e OP Operation code e PHYAD PHY address e REGAD Register address e TA Turnaround Write Transaction Figure 8 6 shows a write transaction across the MDIO as defined by OP 01 The addressed MMD PHYAD device takes the 16 bit word in the data field and writes it to the register at REGAD STA drives MDIO d 2 maio HY T3 0 3 1 lz z z as 01 0 1 P4 P3 P2 P1 PORA R3 R2 R1 RO 1 0 p1 D1 D1 D9 D7 D5 D3 O1 ZZ D14 D12 D10 D8
55. LAY and IDELAYCTRL components to aid placement INST gemac block rgmii interface delay rgmii rx clk HIODELAY GROUP HIODELAY RGMII GRP1 INST gemac block rgmii interface delay rgmii rxd HIODELAY GROUP HIODELAY RGMII GRP1 INST gemac block rgmii interface delay rgmii rx ctl HIODELAY GROUP HIODELAY RGMII GRP1 INST gemac block dlyctrl IHODELAY GROUP HIODELAY RGMII GRP1 RGMII DDR Constraints The following constraints are present for RGMII designs in all devices with the exception of Virtex 4 and Virtex 5 devices Due to the use of IDDR and ODDR primitives in the Virtex 4 design these extra clocking constraints are not required The RGMII design requires further clock crossing constraints to ensure timing is met when crossing from rising to falling clock edges and vice versa A stringent time constraint ensures that timing is met with the worst case timing allowed in the RGMII specification INST rgmii interface rgmii rxd reg 4 TNM rgmii falling INST rgmii interface rgmii rxd reg 5 TNM rgmii falling INST rgmii interface rgmii rxd reg 6 TNM rgmii falling INST rgmii interface rgmii rxd reg 7 TNM rgmii falling INST rgmii interface rgmii rx ctl reg TNM rgmii falling INST rgmii interface gmii rxd reg 4 TNM rgmii rising INST rgmii interface gmii rxd reg 5 TNM rgmii rising INST rgmii interface gmii rxd reg 6 TNM rgmii rising INST rgmii interface
56. LUE determines the tap delay value An IDELAYCTRL primitive must be instantiated for this mode of operation See the Virtex 5 FPGA User Guide for more information on the use of IDELAYCTRL and IODELAY components IOB LOGIC IBUFG gmii rx clk 1 Gigabit Ethernet MAC LogiCORE gmii rx clk lt IBUF gmii rxd 0 IODELAY lt gmii_rxd_reg 0 IBUF mii rx dv re gmii rx dv gmii rx dv L9IILDX ev Teg IODELAY E AD gmii rx er reg IODELAY e gmii rx er gmii rx er Figure 7 8 External GMII Receiver Logic for Virtex 5 Devices 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 65 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 7 Using the Physical Side Interface Implementing External RGMII The HDL example design delivered with the core implements an external RGMII when RGMII is selected from the CORE Generator GUI see Chapter 3 Generating the Core For more information about using the example design see the 1 Gigabit Ethernet MAC Getting Started Guide RGMII Transmitter Logic Spartan 3 Spartan 3E Spartan 3A and Spartan 3A DSP Devices Figure 7 4 illustrates how to use the physical transmitter interface of the core to create an external RGMII in a Spartan 3 device The signal names and logic precisely match those delivered with the example design when the RGMII is selected If other families are used equivalent primitives and logic spec
57. MHz The following UCF syntax shows the necessary constraints being applied to the clock signal which is routed to the gmii rx clk port of the core Set the Receiver clock period constraints please do not relax NET gmii rx clk bufg TNM NET clk rx TIMEGRP rx clock elk rx TIMESPEC TS_rx_clk PERIOD rx_clock 8000 ps HIGH 50 host_clk The clock provided to host_c1k must be constrained to the desired frequency within the allowable range see Host Clock Frequency on page 77 The following UCF syntax shows a 100 MHz period constraint being applied to the host clk signal which is routed to the host c1k port of the core Set the Management Clock period constraints relax as required NET host clk TNM NET host clk TIMEGRP host host clk EXCEPT mdio logic TIMESPEC TS host clk PERIOD host 10000 ps HIGH 50 MDIO Logic The MDIO logic see MDIO Interface on page 30 is synchronous to host_clk but data only changes at the mdc output rate as configured in the MDIO Configuration on page 82 Nominally mdc will be set to a frequency of 2 5 MHz Every flip flop in the MDIO logic is clocked with host c1k but is sent a clock enable pulse at the mdc frequency To prevent this logic being over constrained by the host c1k period the relevant flip flops for the MDIO logic can be grouped together and removed from the host clk period constraint This
58. SCONTINUED PRODUCT XILINX Chapter 9 Constraining the Core This chapter defines the GEMAC core constraint requirements An example UCF that implements the constraints defined in this chapter is provided with the HDL example design for the core See the 1 Gigabit Ethernet MAC Getting Started Guide for more information about the CORE Generator output files and detailed information about the HDL example design Required Constraints Device Package and Speedgrade Selection The GEMAC can be implemented in Virtex 4 Virtex 5 Spartan 3 Spartan 3E and Spartan 3A devices with the following attributes e Large enough to accommodate the core e Contains a sufficient number of IOBs e Operates at the following speed grades for Spartan 3 Spartan 3E and Spartan 3A devices 10 for Virtex 4 FPGA e 1 for Virtex 5 FPGA I O Location Constraints No specific I O location constraints are required Placement Constraints No specific placement constraints are required Timing Constraints The core can have up to three separate clock domains gtx_c1k for the transmitter logic gmii rx clk for the receiver logic and host c1k for the optional management logic These clock nets and the signals within the core that cross these clock domains must be constrained appropriately in a UCF The constraints defined in this section are implemented in the UCF for the example design delivered with the core Sections from this UCF
59. TINUED PRODUCT XILINX Chapter 6 Configuration and Status This chapter provides general guidelines for configuring and monitoring the GEMAC core including a detailed description of the client side management interface and registers present in the core It also describes the alternative to the optional management interface which is the Configuration Vector Using the Optional Management Interface The Management Interface is a processor independent interface with standard address data and control signals It may be used as is or a wrapper not supplied may be used to interface to common bus architectures For port definition see Management Interface Optional on page 28 This interface is used for e Configuring of the GEMAC core via the configuration registers e Access through the MDIO interface to the management registers located in the PHY connected to the GEMAC core The Management Interface can be accessed in different ways depending on the type of transaction A truth table showing which access method is required for each transaction type is shown in Table 8 1 These access methods are described in the following sections Table 8 1 Management Interface Transaction Types Transaction host miim sel host addr 9 Configuration 0 1 MIIM access 1 X Host Clock Frequency The Management Interface clock host c1k is used to derive the MDIO clock mdc and for this reason is subject t
60. Table 8 2 Configuration Registers 0 0 78 Table 8 3 Receiver Configuration Word 0 0 79 Table 8 4 Receiver Configuration Word 1 0 0 79 Table 8 5 Transmitter Configuration Word 000s 80 Table 8 6 Flow Control Configuration Word 81 Table 8 7 Management Configuration Word 0 eee 82 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com UG144 April 24 2009 13 DISCONTINUED PRODUCT XILINX Table 8 8 Unicast Address Word 0 nanunua anaana eee eens 82 Table 8 9 Unicast Address Word 1 0 82 Table 8 10 Address Table Configuration Word 0 0 cece eee eee 83 Table 8 11 Address Table Configuration Word 1 0 cece c eee eee eee 83 Table 8 12 Address Filter Mode 0 0 83 Table 8 13 Configuration Vector Bit Definition 0 eee eee 90 Chapter 9 Constraining the Core Table 9 1 Input GMII Timing 0 97 Table 9 2 Input RGMII Timing 0 102 Chapter 10 Clocking and Resetting Chapter 11 Interfacing to Other Cores Table 11 1 Management Interface Transaction Types 0 000 e cece eens 121 Chapter 12 Implementing Your Design Appendix A Using the Client Side FIFO Table A 1 Transmit FIFO Client Interface 0 0000 ccc cece eens 128 Table A 2 Transmit FIFO LocalLink Interface sulle eese 128 Table A 3 Receive FIFO Cl
61. X DISCONTINUED PRODUCT Chapter 7 Using the Physical Side Interface Using the MDIO interface 76 The MDIO interface is accessed through the optional management interface and is typically connected to the MDIO port of a physical layer device to access its configuration and status registers see MDIO Interface on page 86 The MDIO format is defined in IEEE 802 3 clause 22 Connecting the MDIO to an Internally Integrated PHY The MDIO ports of the GEMAC core can be connected to the MDIO ports of an internally integrated physical layer device such as the MDIO port of the Xilinx Ethernet 1000BASE X PCS PMA or SGMII core See Chapter 11 Interfacing to Other Cores for more information Connecting the MDIO to an External PHY The MDIO ports of the GEMAC core can be connected to the MDIO of an external physical layer device In this situation mdio in mdio out and mdio tri must be connected to a tri state buffer to create a bidirectional wire mdio This tri state buffer can be either external to the FPGA or internally integrated by using an IOB IOBUF component with an appropriate SelectIOTM standard for the external PHY illustrated in Figure 7 11 1 Gigabit Ethernet MAC Core IOB LOGIC IOB LOGIC mdio tri IOBUF mdio_out IOPAD MDIO mdio in Figure 7 11 Creating an External MDIO Interface www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCON
62. Y GMII GRP1 INST gemac block gmii interface delay gmii rxd HIODELAY GROUP HIODELAY GMII GRP1 INST gemac block dlyctrl HIODELAY GROUP HIODELAY GMII GRP1 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Required Constraints DISCONTINUED PRODUCT EZ XILINX Understanding Timing Reports for GMII Setup Hold Timing Non Virtex 5 devices Setup and Hold results for the GMII input bus can be found in the data sheet section of the Timing Report The results are self explanatory and it is easy to see how they relate to Figure 9 1 Following is an example for the GMII report from a Virtex 4 device The implementation requires 1 531 ns of setup this is less than the 2 ns required so there is some slack The implementation requires 0 125 ns of hold this is less than the 0 ns required so there is some slack Data Sheet report All values displayed in nanoseconds ns Setup Hold to clock gmii rx clk Setup to Hold to Clock Source clk edge clk edge Internal Clock s Phase gmii_rx_dv 1 531 R 0 141 R gmii rx clk bufg 0 000 gmii rx er 1 531 R 0 141 R gmii rx clk bufg 0 000 gmii rxd 0 1 531 R 0 141 R gmii rx clk bufg 0 000 gmii rxd 1 1 525 R 0 135 R gmii rx clk bufg 0 000 gmii rxd 2 1 531 R 0
63. _11_clock and tx 11 clock are always 125 MHz or faster Receive FIFO The receive FIFO is built around two Dual Port Block RAMs giving a memory capacity of 4096 bytes The receive FIFO takes data from the client interface of the GEMAC core and converts it into LocalLink format See Receiving Inbound Frames on page 39 for a description of the GEMAC receive client interface If the frame is marked as good by the GEMAC that frame is presented on the LocalLink interface for reading by the user If the frame is marked as bad it is dropped by the FIFO If the receive FIFO memory overflows the frame currently being received is dropped regardless of whether it is a good or bad frame The signal rx overflowis then asserted Situations in which the memory may overflow are e The FIFO may overflow if the user is reading data from the FIFO at a slower data rate than data is being written in from the MAC receiver e The FIFO size of 4096 bytes limits the size of the frames that it can store without error If a frame is larger than 4000 bytes the FIFO may overflow and data will be lost For this reason it is recommended that the FIFO not be used with the GEMAC in jumbo frame mode for frames larger than 4000 bytes Transmit FIFO The transmit FIFO is built around two Dual Port block RAMs giving a total memory capacity of 4096 byes of frame data The transmit FIFO accepts frames in LocalLink format and stores them in block RAM for transm
64. acted to delay the clock by an entire period when measured from the input flip flop 106 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Required Constraints XILINX This is less than the 1 ns required so there is slack Equally for the ve edge we have 11 179 ns of setup this edge is at time 12 ns and therefore this equates to a setup of 0 821 ns The implementation requires 8 893 ns of hold to the ve edge Figure 9 4 illustrates that this represents 0 893 ns relative to the following rising edge of the clock since the IDELAY has acted to delay the clock by an entire period when measured from the input flip flop This is less than the 1 ns required so there is slack Equally for the ve edge we have 12 893 ns of hold this edge is at time 12 ns and therefore equates to a hold time of 0 893 ns RGMII_RXD 3 0 RGMII_RX_CTL 8ns ame cK 6 134 ns tsetud 8 7 179 0 821 ns St thon 8 893 8 8 893 ns 0 893 ns E 8 ns lt _ __qm pA l 12 ns 12 ns 11 179 ns 12 893 ns 4 tholo 12 893 12 r 0 893 ns tsetup 12 11 179 0 821 ns Figure 9 4 Timing Report Setup Hold Illustration 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 107 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 9 Constraining the Core 108 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide
65. actly match those delivered with the example design when the RGMII is selected Figure 7 6 also shows that the output transmitter signals are registered in the IOBs in ODDR components These components convert the input signals into one double data rate signal The ODDR outputs are passed through IODELAYs and these can be used to adjust the relationship between the individual signals These signals are then output through OBUFs before being driven to output pads IOB LOGIC IOB LOGIC T OBUF e ee eS ES rgmii txc gtx_clk_bufg gmii_txd 0 gmii_txd_int 0 OBUF rgmii_txd 0 mii tx en int gmii tx en As OBUF rgmii tx ctl gmii tx er IODELA p OPAD l l l l Figure 7 6 External RGMII Transmitter Logic in Virtex 5 Devices 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 69 UG144 April 24 2009 EZ XILINX DISCONTINUED PRODUCT Chapter 7 Using the Physical Side Interface The logic required to forward the transmitter clock is also shown It has matching logic to the data and control signals to provide a known relationship between the signals An IODELAY component is used to phase shift the rgmii_txc clock signal by 90 degrees with respect to gtx_clk_bufg This allows the rising edge of rgmii_txc to occur in the center of the data valid window which maximizes setup and hold times across the interface as specified in the RGMII v2 0 specification The IODELAY comp
66. ansmit data from the client logic into the core See Transmitting Outbound Frames on page 47 The Transmitter Interface is designed to be connected to internal device logic only Attempting to add external ports to this interface will result in a breakdown of the handshaking protocol used by this interface Table 2 1 Transmitter Client Interface Signal Pins Clock Signal Direction Domain Description gtx_clk Input n a Clock signal provided to the core at 125 MHz Tolerance must be within IEEE 802 3 2005 specification This clock signal is used by all of the transmitter logic tx_data 7 0 Input gtx_clk Frame data to be transmitted is supplied on this port tx_data_valid Input gtx_clk Control signal for tx data port tx ifg delay 7 0 Input gtx_clk Control signal for configurable Inter Frame Gap adjustment tx ack Output gtx ck Handshakingsignalasserted when the current data on tx data has been accepted tx underrun Input gtx clk Asserted by client to force GEMAC core to corrupt the current frame tx statistics vector 31 0 Output gtx clk Provides statistical information about the last frame transmitted tx statistics valid Output gtx clk Asserted at end of frame transmission indicating that the tx statistics vector is valid www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Core Interfaces x XILINX Rece
67. at simulations can occur in a timely manner The 200ms reset pulse takes the signal name reset 200ms in the example design HDL files It is routed from the DCM reset module instantiation up through all levels of hierarchy to the top level It is then left unconnected in the example design instantiation from within the demonstration test bench Furthermore an accompanying signal reset 200ms in is routed down from the top level of the example design hierarchy to the DCM instantiation where it is connected to the DCM reset From the demonstration test bench this reset 200ms insignalis driven for a short duration to enable fast simulation start up However to re iterate when implementing the design in real hardware the DCM reset signal must be connected correctly e This can be achieved by connecting the reset 200ms signal to the reset 200ms in signal at any level of example design HDL hierarchy www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Implementing External GMII XILINX Virtex 5 Devices An IODELAY component may be used on the clock data and control paths as illustrated in Figure 7 3 These can be used to either shift the input clock gmii rx clk or the data and control signals to meet the setup and hold requirements of GMII and to allow for any bus skew across the data and control inputs The IODELAY components are used in fixed delay mode where the attribute IDELAY VA
68. available for transmission for example if a frame larger than 4000 bytes is written into the FIFO the FIFO may assert the tx_over flow signal and continue to accept the rest of the frame from the user The overflow frame will be dropped by the FIFO This ensures that the LocalLink interface does not lock up For this reason it is recommended that the FIFO not be used with the GEMAC in jumbo frame mode for frames larger than 4000 bytes Expanding Maximum Frame Size The transmit FIFO size is optimized to allow line rate transmission of maximum size Ethernet frames at 1518 bytes in half duplex operation When using the FIFO in full duplex operation the full block RAM capacity can be utilized at all times As a whole frame must be stored in the FIFO block RAM before being presented to the MAC transmitter the maximum size frame that can be handled is determined by the memory capacity of the FIFO in this case 4000 bytes Both transmit and receive FIFO sizes can be expanded by the user to handle larger frame sizes This can be done by instantiating further block RAMs into the FIFO design expanding the block RAM address signals and adding the necessary control signals The HDL source files provide guidance in the comments on how to achieve this User Interface Data Width Conversion 132 Conversion of the user interface 8 bit data path to a 16 32 64 or 128 bit data path can be made by connecting the LocalLink interface directly to the Para
69. bit is set to 1 the receiver will be reset The bit will then automatically revert to 0 This reset also sets all of the receiver configuration registers to their default values Transmitter Configuration The register contents for the Transmitter Configuration Word are described in Table 8 5 Table 8 5 Transmitter Configuration Word Default ER Bit Value Description 24 0 n a Reserved 25 0 Interframe Gap Adjust Enable If 1 the transmitter will read the value on the port tx ifg delay atthe start of frame transmission and adjust the interframe gap following the frame accordingly 26 n a Reserved 27 0 VLAN Enable When this bit is set to 1 the transmitter will allow the transmission of VLAN tagged frames 28 1 Transmit Enable When this bit is 1 the transmitter is operational When it is 0 the transmitter is disabled 80 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT EZ XILINX Using the Optional Management Interface Table 8 5 Transmitter Configuration Word Continued UG144 April 24 2009 Bit 29 Default Value 0 Description In band FCS Enable When this bit is 1 the MAC transmitter will expect the FCS field to be passed in by the client When this bit is 0 the MAC transmitter will append padding as required compute the FCS and append it to the fram
70. configured in the example designs to meet the setup and hold constraints for the example GMII pinout in the particular device The setup hold timing which is achieved after place and route is reported in the datasheet section of the TRCE report created by the implement script When IDELAY or IODELAY primitives are instantiated with a fixed delay attribute an IDELAYCTRL component must be also instantiated to continuously calibrate the individual input delay elements The IDELAYCTRL module requires a reference clock which is assumed to be an input to the example design delivered by CORE Generator The most efficient way to use the IDELAYCTRL module is to lock the placement of the instance to the clock region of the device where the IDELAY IODELAY components are placed An example LOC constraint for the IDELAYCTRL module is shown commented out in the UCE See the Virtex 5 User Guide and code comments for more information The following constraints are provided in the example design to link the instance of the IDELAYCTRL to the IODELAY components used on the GMII These constraints aid the Xilinx tools in automatic IDELAYCTRL placement Group IODELAY and IDELAYCTRL components to aid placement INST gemac block gmii interface delay gmii rx clk HIODELAY GROUP HIODELAY GMII GRP1 INST gemac block gmii interface delay gmii rx dv HIODELAY GROUP HIODELAY GMII GRP1 INST gemac block gmii interface delay gmii rx er HIODELAY GROUP HIODELA
71. cy of the user system gradually increases over time due to the clock tolerances At point A the occupancy has reached the threshold of 7 8 occupancy This triggers the maximum duration pause control frame request 2 On receiving the pause control frame the link partner MAC ceases transmission 3 After the link partner MAC ceases transmission the occupancy of the FIFO in the user system rapidly empties The occupancy falls to the second threshold of 3 4 occupancy at point B This triggers the zero duration pause control frame request the pause cancel command 4 On receiving this second pause control frame the link partner MAC resumes transmission 5 Normal operation resumes and the FIFO occupancy again gradually increases over time At point C this Flow Control cycle repeats 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 59 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 6 Using Flow Control 60 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 7 Using the Physical Side Interface This chapter provides general guidelines for creating designs using the Physical Side Interface of the GEMAC core The physical side interface implements GMII style signaling and is typically attached to a physical layer device PHY either off chip or internally integrated See Physical Side Interface in Chapter 2 For information about us
72. d control signals The xgmii tx clk clock signal is phase shifted by 90 degrees in the DCM with respect to gtx c1k bufg This means that the rising edge of rgmii txc occurs in the center of the data valid window which maximizes setup and hold times across the interface as specified in the Reduced Gigabit Media Independent Interface RGMID Version 2 0 specification Virtex 4 Devices Figure 7 5 shows using the physical transmitter interface of the core to create an external RGMII in a Virtex 4 device The signal names and logic shown exactly match those delivered with the example design when the RGMII is selected Figure 7 5 also shows that the output transmitter signals are registered in the IOBs in ODDR components These components convert the input signals into one double data rate signal These signals are then output through OBUFs before being driven to output pads 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 67 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 7 Using the Physical Side Interface IOB LOGIC IOB LOGIC BUFGMUX gt rgmii tx clk bufg 4 l D1 OBUF IBUFG gtx_clk l o e o E gtx_clk_bufg pc Boe hase IOBLOGIO l l ODDR 1 Gigabit Ethernet MAC Core gmii_txd 0 amii eo imio D1 OBUF ii T gmii txd 4 gmi d int4 D2 Q lt OPAD l pc wc Lr IOB LOGIC I pecu rl EE l ODDR i gmii_tx_en a D1 obur rgmii_tx FL
73. d using CORE Generator on your system see the documentation supplied with the Xilinx ISE software including the CORE Generator Guide at www xilinx com support software manuals htm 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 31 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 3 Generating the Core Component Name The component name is used as the base name of the output files generated for the core Names must begin with a letter and must be composed from the following characters a through z 0 through 9 and _ Management Interface Select this option to include the optional Management Interface see Using the Optional Management Interface on page 77 If this option is not selected the core is generated with a replacement configuration vector see Access without the Management Interface on page 90 The default is to use the Management Interface Address Filter Select this option to include the optional Address Filter This prevents the reception of frames that are not addressed to this MAC see Address Filter on page 44 The default is to use the Address Filter Number of Address Table Entries The Address Filter can be instantiated with an address table that holds up to 4 additional valid addresses You may select an integer between 0 and 4 to define the number of addresses that are present in the table This option is only available when the Management Inter
74. data_valid tx_ifg_delay 7 0 tx_ack tx_underrun tx_statistics_vector 31 0 tx_statistics_valid pause_req pause val 15 0 gmii_txd 7 0 gmii_tx_en gmii_tx_er gmii_rx_clk domain rx_data 7 0 rx_data_valid rx_good_ frame rx_bad_frame rx_statistics_vector 27 0 rx_statistics_valid gmii rx clk gmii rxd 7 0 H gmii rx dv H gmii rx er configuration vector 67 0 reset Figure 2 4 Component Pinout for MAC without Optional Management Interface or Optional Address Filter 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com UG144 April 24 2009 25 XILINX DISCONTINUED PRODUCT Chapter 2 Core Architecture All ports of the core are internal connections in FPGA fabric An HDL example design is delivered with the core that will add IBUFs OBUFs and IOB flip flops to the external signals of the Gigabit Media Independent Interface GMII or Reduced Gigabit Media Independent Interface RGMID All clock management logic is placed in this example design which allows for more flexibility in implementation for example in designs using multiple cores This example design is provided in both VHDL and Verilog For more information about example designs see the 1 Gigabit Ethernet MAC Getting Started Guide Client Side Interface 26 Transmitter Interface Table 2 1 describes the client side transmitter signals of the GEMAC core These signals are used to tr
75. e 30 Jumbo Frame Enable When this bit is set to 1 the MAC transmitter will send frames that are greater than the specified IEEE 802 3 2005 maximum legal length When this bit is 0 the MAC will only send frames up to the specified maximum 31 Reset When set to 1 the transmitter will be reset The bit will then automatically revert to 0 This reset will also set all of the transmitter configuration registers to their default values Flow Control Configuration Table 8 6 lists the register contents for the Flow Control Configuration Word Table 8 6 Flow Control Configuration Word Default P Bit Value Description 28 0 n a Reserved 29 1 Flow Control Enable RX When this bit is 1 received flow control frames will inhibit the transmitter operation When this bit is 0 received flow control frames will always be passed up to the client 30 1 Flow Control Enable TX When this bit is 1 asserting the PAUSE REO signal will send a flow control frame out from the transmitter When this bit is 0 asserting the PAUSE REO signal has no effect 31 n a Reserved 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 81 DISCONTINUED PRODUCT XILINX Chapter 8 Configuration and Status MDIO Configuration The register contents for the Management Configuration Word are described in Table 8
76. e FIFO rx_overflow Output rx_clk Overflow signal indicates when a frame has been dropped in the FIFO Table A 4 describes the receive FIFO LocalLink interface For more information on the LocalLink interface see Overview of LocalLink Interface on page 130 Table A 4 Receive FIFO LocalLink Interface Signal Direction Scit Description rx ll clock Input N A Read clock for LocalLink interface rx ll reset Input rx ll clock Synchronous reset rx l data out 7 0 Output rx ll clock Data read from FIFO rx ll sof out n Output rx ll clock Start of frame indicator rx ll eof out n Output rx ll clock End of frame indicator rx ll src rdy out n Output rx ll clock Source ready indicator rx ll dst rdy in n Input rx ll clock Destination ready indicator rx fifo status 3 0 Output rx Il clock FIFO memory status 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 www xilinx com 129 DISCONTINUED PRODUCT XILINX Appendix A Using the Client Side FIFO Overview of LocalLink Interface Data Flow Data is transferred on the LocalLink interface from source to destination with the flow being governed by the four active low control signals sof_n eof n src_rdy_n and dst rdy n The flow of data is controlled by the src_rdy_n and dst_rdy_n signals Only when these signals are asserted simultaneously is data transferred from source to destination The ind
77. e design for RGMII a transmitter clock source is therefore used for this receiver DCM This is obtained from the BUFGMUX output which is connected to the DCM CLK90 output of Figure 7 5 The clock selection for this BUFGMUX will ensure that a 125MHz clock is always present on this global clock route even when the RGMII transmitter DCM of Figure 7 5 is held in reset itself This reset circuitry will generate an appropriate reset pulse for the receiver DCM of Figure 7 8 under the following conditions e The locked signal from the DCM is constantly monitored Following a high to low transition on this signal indicating that the DCM has lost lock a reset will be issued e A timeout counter is enabled when the DCM is in the loss of lock state If following the timeout period the DCM has not obtained lock another DCM reset will be issued This timeout counter will time a 1ms interval This timeout functionality is required for DCMs connected to Ethernet PHYs since the PHYs may source discontinuous clocks under certain network conditions for example when no ethernet cable is connected For Virtex 4 families the generated reset from within the DCM reset module must be asserted for a minimum of 200 ms see the Virtex 4 Datasheet Consequently a 200 ms duration timer is also included in the DCM reset module to extend the reset pulse This reset signal is output from the DCM reset module and should be routed to the DCM reset input port Caution
78. e last valid data on rx_data this is not always the case The rx good frameorrx bad frame signals are asserted only after all frame checks are completed This is after the FCS field has been received and after reception of carrier extension if present Therefore either xx good frame orrx bad frame is asserted following frame reception at the beginning of the interframe gap 40 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Receiving Inbound Frames XILINX Frame Reception with Errors Figure 5 2 illustrates an unsuccessful frame reception for example a fragment frame or a frame with an incorrect FCS In this case the rx_bad_frame signal is asserted to the client at the end of the frame It is then the responsibility of the client to drop the data already transferred for this frame The following conditions cause the assertion of rx_bad_frame FCS errors occur Packets are shorter than 64 bytes undersize or fragment frames Jumbo frames are received when jumbo frames are not enabled VLAN frames of length 1519 1522 are received when VLAN frames are not enabled A value of 0x0000 to 0x002D is in the type length field In this situation the frame should be padded to minimum length If it is not padded to exactly minimum frame length the frame is marked as bad when length type checking is enabled A value of 0x002E to 0x0600 is in the type length field but the r
79. e requests are received and decoding in the gmii rx clk domain and must be transferred into the gtx c1k domain to pause the transmitter Therefore whenever gmii rx clk and gtx_clk are derived from different clock sources the following constraints must always be applied Flow Control logic reclocking INST gmac core BU2 U0 FLOW RX PAUSE GOOD FRAME TO TX TNM flow rx to tx INST gmac core BU2 U0 FLOW RX PAUSE PAUSE REQ TO TX TNM flow rx to tx INST gmac core BU2 U0 FLOW RX PAUSE AUSE VALUE TO TX TNM flow rx to tx TIMESPEC TS flow rx to tx FROM flow rx to tx TO tx clock 8000 ps Configuration When the optional Management Interface is used with the core configuration information is written synchronously to host c1k Receiver configuration data must be transferred onto the gmii rx clk clock domain for use with the receiver and into the gtx c1k clock domain for use with the transmitter The following UCF syntax targets this logic and a timing ignore attribute TIG is applied It does not matter when configuration changes take place the current configurations are sampled between frames by both the receiver and transmitter Configuration Register reclocking INST gmac core BU2 U0 MANIFGEN MANAGEN CONF RXO0 OUT TNM config to rx INST gmac core BU2 U0 MANIFGEN MANAGEN CONF RX1 OUT TNM config to rx INST gmac core BU2 U0 MANIFGEN MANAGEN CONF FC OUT 29 TNM config to rx TIMESPEC TS config to rx
80. e setup and hold figures reported in the TRCE report can be used to initially setup the approximate DCM phase shift Appendix C Calculating DCM Phase Shifting describes a more accurate method for fixing the phase shift by using hardware measurement of a unique PCB design Virtex 5 Devices The GMII design uses IODELAY components on the receiver clock data and control signals for Virtex 5 devices A fixed tap delay can be applied to either delay the data and control signals or delay the clock so that the data control are correctly sampled by the gmii rx clk clock at the IOB flip flop meeting GMII setup and hold timing The choice of delaying data control or clock is dependant upon a number of factors not least being the required shift There are trade offs to be made with either choice Delaying the clock is clock period specific as we move the clock to line up each edge with data from the following edge Delaying the data control introduces more jitter which degrades the overall setup hold window The interface timing report in the two cases is also quite different See Understanding Timing Reports for GMII Setup Hold Timing The following constraint shows an example of setting the delay value for one of these IODELAY components Data Control bits can be adjusted individually if desired to compensate for any PCB routing skew INST gmii interface delay gmii rx dv IDELAY VALUE 33 The value of IDELAY VALUE is pre
81. e setup and hold margins The IODELAY components are used in fixed delay mode where the attribute IDELAY_VALUE determines the tap delay value An IDELAYCTRL primitive must be instantiated for this mode of operation See the Virtex 5 User Guide for more information on the use of IDELAYCTRL and IODELAY components www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Implementing External RGMII XILINX RGMII Inband Status Decoding Logic The inband status decoding logic is common to all device families Figure 7 10 illustrates the decoding of RGMII inband status information This information is received through the RGMII interface between frames The signal names and logic shown exactly match those delivered with the example design when the RGMII is selected OBUF f inband_link_status 1 Gigabit Ethernet MAC Core Da CE gt OBUF inband clock speed 0 Co D Q gt OPAD S OBUF i inband clock speed 1 D Q gt oa OBUF inband duplex status oa gt RES E gmi x ck butg o oo eee reer rrr gmii rxd o gmii rxd reg 0 2 gmii rxd 1 rM BE gmii xd 2 gmi md regi2 gmii rxd reg 3 gmii_rxd 3 ii gmii rx dv gmii rx er reg gmii rx er e LEES ei quacum eee cetur ee ee ee ee Figure 7 10 RGMII Inband Status Decoding Logic 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 75 UG144 April 24 2009 EZ XILIN
82. eal length of the received frame does not match this value when length type checking is enabled Any control frame that is received is not exactly the minimum frame length unless control frame length checks are disabled gmii_rx_er is asserted at any point during frame reception An error code is received in the 1 Gigabit frame extension field A valid pause frame addressed to the MAC is received when flow control is enabled Please see Overview of Flow Control on page 53 rx_data 7 0 TPE y e ed L T DATA il rx_data_valid J rx_good_frame a rx_bad_frame 7 7 Figure 5 2 Frame Reception with Error 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 41 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 5 Using the Client Side Data Path Client Supplied FCS Passing If the GEMAC core is configured to pass the FCS field to the client see Configuration Registers on page 78 this is handled as shown in Figure 5 3 In this case any padding inserted into the frame to meet Ethernet minimum frame length specifications will be left intact and passed to the client Even though the FCS is passed up to the client it is also verified by the GEMAC core and rx_bad_frame asserted if the FCS check fails rx_data 7 0 Le pa a sa uT hk pata Fes rx_data_valid rx good frame rx bad frame 7 4 Figure 5 3 Frame Reception with In Band FCS Field
83. ed user configurations of the GEMAC core can only be made by selecting the options in the CORE Generator when the core is generated See Chapter 3 Generating the Core www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 5 Using the Client Side Data Path This chapter provides general guidelines for creating designs using the GEMAC core including a detailed description of each client side data flow interface of the core Definitions of the abbreviations used throughout the remainder of this chapter are defined in Table 5 1 Table 5 1 Abbreviations Used in Timing Diagrams Abbreviation Definition DA Destination address 6 bytes SA Source address 6 bytes L T Length type field 2 bytes FCS Frame check sequence 4 bytes Receiving Inbound Frames Received Ethernet frames are presented to the client logic on the Receiver subset of the Client Side Interface For port definition see Receiver Interface on page 27 Normal Frame Reception Figure 5 1 illustrates the timing of a normal inbound frame transfer The client must be prepared to accept data at any time there is no buffering within the MAC to allow for latency in the receive client Once frame reception begins data is transferred on consecutive clock cycles to the receive client until the frame is complete The MAC asserts the rx good frame signal to indicate that the frame
84. elivered with the core Sections from this UCF are copied into the following descriptions to provide examples These examples should be studied in conjunction with the HDL source code for the example design and with the description Implementing External GMII on page 61 GMII IOB Constraints The following constraints target the flip flops that are inferred in the top level HDL file for the example design constraints are set to ensure that these are placed in IOBs GMII Transmitter Constraints place flip flops in IOB INST gmii interface gmii txd reg IOB true INST gmii interface gmii tx en reg IOB true INST gmii interface gmii tx er reg IOB true GMII Receiver Constraints place flip flops in IOB INST gmii_interface gmii_rxd_reg IOB true INST gmii interface gmii rx dv reg IOB true INST gmii interface gmii rx er reg IOB true The GMII is a 3 3 volt signal level interface which is not the default SelectIO standard Therefore use the following constraints with the device IO Banking rules INST gmii txd IOSTANDARD LVTTL INST gmii tx en IOSTANDARD LVTTL INST gmii tx er IOSTANDARD LVTTL INST gmii_rxd lt gt IOSTANDARD LVTTL INST gmii_rx_dv IOSTANDARD LVTTL INST gmii rx er IOSTANDARD LVTTL INST gmii tx clk IOSTANDARD LVTTL INST gmii rx clk IOSTANDARD LVTTL In addition the e
85. er Guide UG144 April 24 2009 www xilinx com 91 XILINX 92 DISCONTINUED PRODUCT Chapter 8 Configuration and Status Table 8 13 Configuration Vector Bit Definition Continued Configuration Bit s Register cross Clock Description reference 62 Flow Control gtx_clk Receive Flow Control Enable When this bit Configuration is 1 received flow control frames will inhibit Word bit 30 the transmitter operation When at 0 received flow frames are passed up to the client 63 Receiver gtx clk Length Type Error Check Disable When Configuration this bit is set to 1 the core will not perform Word 1 bit 25 the length type field error checks as described in Length Type Field Error Checks on page 43 When this bit is set to 0 the length type field checks will be performed this is normal operation 64 Address Filter gmii rx clk Address Filter Enable When this bit is 0 Mode bit 31 the Address Filter is enabled If it is set to 1 the Address Filter will operate in promiscuous mode 66 65 n a n a This input is unused 67 Receiver gtx_clk Control Frame Length Check Disable When Configuration this bit is set to 1 the core will not mark Word 1 bit 24 control frames as bad if they are greater than the minimum frame length www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DI
86. eshold is implementation specific When the occupancy of the FIFO exceeds this occupancy initiate a single pause control frame from the user MAC with OxFFFF used as the pause_quantum duration OxFFFF is placed on pause val 15 0 This is the maximum pause duration This causes the link partner MAC to cease transmission and the FIFO of the user system will start to empty Choose a second FIFO occupancy threshold 3 4 is used in this description but the choice of threshold is implementation specific When the occupancy of the FIFO falls below this occupancy initiate a second pause control frame from the user MAC with 0x0000 used as the pause quantum duration 0x0000 is placed on pause va1 15 0 This indicates a zero pause duration and upon receiving this pause control frame the link partner MAC immediately resumes transmission it does not wait for the original requested pause duration to expire This pause control frame can therefore be considered a pause cancel command www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Flow Control Implementation Example XILINX Operation Figure 6 4 illustrates the FIFO occupancy over a period of time FIFO occupancy Full 7 8 3 4 5 8 1 2 time p Figure 6 4 Flow Control Implementation Triggered from FIFO Occupancy The following describes the sequence of flow control operation 1 The average FIFO occupan
87. exe omm Us g pc l Figure 7 5 External RGMII Transmitter Logic in Virtex 4 Devices The logic required to forward the transmitter clock is also shown this uses an ODDR register so that the clock signal produced incurs exactly on the same delay as the data and control signals The rgmii_tx_clk clock signal is phase shifted by 90 degrees in the DCM with respect to gtx_clk_bufg This means that the rising edge of rgmii txc occurs in the center of the data valid window which maximizes setup and hold times across the interface as specified in the RGMII v2 0 specification The use of the BUFGMUX shown with one input connected to the DCM CLK90 output is included so that a reliable 125MHz clock source is always provided on global routing when the DCM is held in reset the DCM input clock is instead selected This is required to always provided a reliable clock for the receiver logic DCM see DCM Reset circuitry 68 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Implementing External RGMII XILINX Virtex 5 Devices The same logic that is used in Figure 7 5 can also be used without modification for Virtex 5 devices However an alternative solution has been adopted for the example design delivered with the core Figure 7 6 shows using the physical transmitter interface of the core to create an external RGMII in a Virtex 5 device The signal names and logic shown ex
88. face and Address Filter have been selected The default is to use 4 address table entries Physical Interface Depending on the target Xilinx FPGA architecture it may be possible to select from two different physical interface choices for the core e GMII See Chapter 7 Implementing External GMII e RGMII See Chapter 7 Implementing External RGMII The choice of physical interface determines the content of the example design delivered with the core The external GMII or RGMII is added in the HDL top level design file There is no change in the core netlist for this option The default is the GMII physical interface Parameter Values in the XCO File XCO file parameter names and their values are identical to the names and values shown in the GUI except that underscore characters _ are used instead of spaces The text in an XCO file is not case sensitive Table 3 1 defines the XCO file parameters and values and summarizes the GUI defaults The following is an example of the CSET parameters in an XCO file CSET component_name abc123 CSET physical_interface gmii CSET management_interface true CSET address_filter true CSET no_of_address_table_entries 4 32 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Output Generation DISCONTINUED PRODUCT XILINX Table 3 1 XCO File Values and Default Values Parameter XCO File Values Default GUI Setting component_name ASCII text
89. gement Interface and Without Address Filter 25 Client Side Interface o eee tite et Ret E ere QU oer verae s 26 Physical Side Interface tases cuta d ette DEF er dr eR rq PR eR dede 29 Chapter 3 Generating the Core Graphical User Interface ivc5 6565 csvceuvoi vend FR e e EX EET PREWUAT E Ve En 31 Component Name 5er eh er ins RR Peele RR UR e RR E EE aS 32 Management Interface 0 6 eee 32 Address Filter siterte tens itor drei oie bate ie essct tes a aun teda e ET eSa 32 Number of Address Table Entries 00 000 32 Physical Interface sce ste tune tea tg ition tea petere tee eO eat e Re e eer ddieeeceibst eg 32 Parameter Values in the XCO File usse eese 32 Output Generallan isi edo see the da ers tp esit ade quada ked aede quid 33 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com UG144 April 24 2009 DISCONTINUED PRODUCT EZ XILINX Chapter 4 Designing with the Core UG144 April 24 2009 General Design Guidelines ois voro iu ibd Rr e E pe Eee x Pa ies 35 Desig Steps ees ar bte e eee ed ee dee a doe hte base lees Res 35 Know the Degree of Difficulty sssseeeeeeeeseee e 37 Keep it Registered e eeber tee Eae eai sesta nde t obe RE 38 Recognize Timing Critical Signals 0 66 38 Use Supported Design Flows n 0 ee e 38 Make Only Allowed Modifications 0 606 c ccc cnn 38 Chapter 5 Using the Client Side Data Path Receiving Inbound Fraities
90. gmii rx er 1 962 R 0 031 R gmii rx clk bufg 0 000 gmii_rxd lt 0 gt 1 949 R 0 013 R gmii_rx_clk_bufg 0 000 gmii_rxd lt 1 gt 1 944 R 0 009 R gmii rx clk bufg 0 000 gmii rxd 2 1 947 R 0 012 R gmii rx clk bufg 0 000 gmii rxd 3 1 942 R 0 008 R gmii rx clk bufg 0 000 gmii rxd 4 1 950 R 0 015 R gmii rx clk bufg 0 000 gmii rxd 5 1 962 R 0 026 R gmii rx clk bufg 0 000 gmii rxd 6 1 957 R 0 022 R gmii rx clk bufg 0 000 gmii_rxd lt 7 gt 1 952 R 0 020 R gmii rx clk bufg 0 000 2 4R 4 4 q4 c Virtex 5 Devices with Delayed Clock Setup and Hold results for the GMII input bus can be found in the data sheet section of the Timing Report However depending on how the setup hold requirements have been met it may not be immediately obvious how the results relate to Figure 9 1 The following is an example for the GMII report from a Virtex 5 device where the clock has been delayed to meet the setup hold requirements Data Sheet report All values displayed in nanoseconds ns Setup Hold to clock gmii rx clk queseicercLeqpecdessitemedpnsctcoebeneeeeeLeeipsucieucu Setup to Hold to Clock Source clk edge clk edge Internal Clock s Phase munie suse EREE E is ese e eee cuim mda i Ex e domi enm n aded m asi cen gmii rx dv 6 198 R 7 526 R gmii_rx_clk_bufg 0 000 gmii_rx_er 6 225 R 7 554 R
91. gth Check Disable When this bit is set to 1 the core will not mark control frames as bad if they are greater than the minimum frame length 25 0 Length Type Error Check Disable When this bit is set to 1 the core will not perform the length type field error checks as described in Length Type Field Error Checks on page 43 When this bit is set to 0 the length type field checks will be performed this is normal operation 26 n a Reserved 27 0 VLAN Enable When this bit is set to 1 VLAN tagged frames will be accepted by the receiver 28 1 Receiver Enable If set to 1 the receiver block will be operational If set to 0 the block will ignore activity on the physical interface RX port 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 79 DISCONTINUED PRODUCT XILINX Chapter 8 Configuration and Status Table 8 4 Receiver Configuration Word 1 Continued Default Value Bit Description 29 0 In band FCS Enable When this bit is 1 the MAC receiver will pass the FCS field up to the client When at 0 the client will not be passed the FCS In both cases the FCS will be verified on the frame 30 0 Jumbo Frame Enable When this bit is set to 1 the MAC receiver will accept frames over the specified IEEE 802 3 2005 maximum legal length When this bit is 0 the MAC will only accept frames up to the specified maximum 31 0 Reset When this
92. h the following MAC Control frame parameters Figure 6 2 e The destination address used is an IEEE802 3 globally assigned multicast address to which any flow control capable MAC will respond e The source address used is the configurable pause frame MAC address see Receiver Configuration on page 79 e The value sampled from the pause_val 15 0 portat the time of the pause req assertion will be encoded into the MAC control parameter field to select the duration of the pause in units of pause quantum If the transmitter is inactive at the time of the pause request this pause control frame is transmitted immediately If the transmitter is currently busy the current frame being transmitted is allowed to complete followed by the pause control frame in preference to any pending client supplied frame A pause control frame initiated by this method is transmitted even if the transmitter has ceased in response to receiving an inbound pause request Note Only a single pause control frame request is stored by the transmitter if pause req is asserted numerous times in a short time period before the control pause frame transmission has begun only a single pause control frame is transmitted The most recent value sampled will be the pause val 15 0 value used Client Initiated Pause Request For maximum flexibility flow control logic can be disabled in the core and alternatively implemented in the client logic connected to the core
93. h of the previous frame in number of bytes The count will stick at 16 383 for any jumbo frames larger than this value Control Frame Asserted if the previous frame had the special MAC Control Type code 88 08 in the length type field Underrun Frame Asserted if the previous frame contained an underrun error Multicast Frame Asserted if the previous frame contained a multicast address in the destination address field Broadcast Frame Asserted if the previous frame contained a broadcast address in the destination address field Successful Frame Asserted if the previous frame was transmitted without error www xilinx com 51 EZ XILINX 52 DISCONTINUED PRODUCT Chapter 5 Using the Client Side Data Path Table 5 5 provides conversion information against previous versions of the GEMAC Table 5 5 Tx Statistics conversion to previous core GEMAC core versions Version 8 5 tx_statistics_vector bit s 31 Version 8 4 and earlier tx_statistics_vector bit s 21 Notes Bit 31 is equivalent to bit 21 of all previous core versions 30 20 Bit 30 is equivalent to bit 20 of all previous core versions 29 20 N A Reserved have been inserted into version 8 5 for statistic vector compatibility with the Tri Mode Ethernet MAC LogiCORE 19 0 No differences www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG
94. hapter 7 Using the Physical Side Interface Table 2 8 GMII Interface Signal Pinout Signal Direction Clock Domain Description gmii txd 7 0 Output gtx_clk Transmit data from MAC gmii_tx_en Output gtx_clk Transmit control signal from MAC gmii_tx_er Output gtx_clk Transmit control signal from MAC gmii_rx_clk Input n a Receive clock from external PHY 125 MHz gmii rxd 7 0 Input gmii rx clk Received data to MAC gmii rx dv Input gmii rx clk Received control signal to MAC gmii rx er Input gmii rx clk Received control signal to MAC 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 29 UG144 April 24 2009 DISCONTINUED PRODUCT x XILINX Chapter 2 Core Architecture MDIO Interface Table 2 9 describes the MDIO Interface signals See Using the MDIO interface on page 76 Table 2 9 MDIO Interface Signal Pinout M Clock M Signal Direction Domain Description mdc Output host_clk Management Clock programmable frequency derived from host_clk mdio_in Input host_clk Input data signal for communication with PHY configuration and status Tie high if unused mdio_out Output host_clk Output data signal for communication with PHY configuration and status mdio_tri Output host clk Tristate control for MDIO signals 0 signals that the value on mdio out should be asserted onto the MDIO bus 1 mdio in mdio out and mdio tri canbe connected to a
95. he two bytes of Tag Control Information V1 and V2 at the appropriate times in the data stream More information on the contents of these two bytes can be found in IEEE 802 3 2005 For more information about enabling and disabling jumbo frame handling see Configuration Registers on page 78 tx_data 7 0 L pa h sa VLAN ur hk para tag tx_data_valid J tx_ack J tx underrun MEI MM y Figure 5 9 Transmission of a VLAN Tagged Frame Maximum Permitted Frame Length The maximum legal length of a frame specified in IEEE 802 3 2005 is 1518 bytes for non VLAN tagged frames VLAN tagged frames may be extended to 1522 bytes When jumbo frame handling is disabled and the client attempts to transmit a frame that exceeds the maximum legal length the GEMAC core will insert an error code to corrupt the current frame and the frame will be truncated to the maximum legal length When jumbo frame handling is enabled frames longer than the legal maximum are transmitted error free For more information on enabling and disabling Jumbo frame handling see Configuration Registers on page 78 Inter Frame Gap Adjustment A configuration bit in the transmitter control register see Configuration Registers on page 78 allows you to control the length of the inter frame gap transmitted by the MAC on the physical interface If this function is selected the MAC exerts back pressure on the client interface to dela
96. he previous frame received was error free Table 5 3 provides conversion information against previous versions of the GEMAC Table 5 3 Rx Statistics conversion to previous core GEMAC core versions Version 8 5 bit s 27 rx statistics vector 26 Version 8 4 and earlier rx statistics vector bit s Notes Bit 27 is equivalent to bit 26 of all previous core versions 26 N A Bit 26 reserved has been inserted into version 8 5 for statistic vector compatibility with the Tri Mode Ethernet MAC LogiCORE 25 0 No differences 46 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Transmitting Outbound Frames XILINX Transmitting Outbound Frames Ethernet frames to be transmitted are presented to the client logic on the Transmitter subset of the Client Side Interface For port definition see Transmitter Interface on page 26 Normal Frame Transmission Padding Figure 5 6 illustrates the timing of a normal outbound frame transfer When the client wishes to transmit a frame it places the first column of data onto the tx_data port and asserts a 1 onto tx data valid When the GEMAC core has read this first byte of data and in accordance with flow control requests and interpacket gap requirements it will assert the tx ack signal on the next and subsequent rising clock edges the client must provide
97. here the clock has been delayed to meet the setup hold requirements Data Sheet report All values displayed in nanoseconds ns Setup Hold to clock rgmii_rxc quesesccedtceposestettemenprcsotcobanceexeLeeipsucieucu Setup to Hold to Clock Source clk edge clk edge Internal Clock s Phase Sessesos sess quede SSepe sel See eee eyes Sere ns EN eod mi em o Cede esses Sed rgmii rx ctl 7 178 R 8 880 R rgmii rx clk bufg 0 000 11 178 F 12 880 F rgmii rx clk bufg 4 000 rgmii_rxd lt 0 gt 7 192 R 8 893 R rgmii rx clk bufg 0 000 11 192 F 12 893 F rgmii rx clk bufg 4 000 rgmii_rxd lt 1 gt 7 182 R 8 884 R rgmii rx clk bufg 0 000 11 182 F 12 884 F rgmii rx clk bufg 4 000 rgmii rxd 2 7 180 R 8 882 R rgmii rx clk bufg 0 000 11 180 F 12 882 F rgmii rx clk bufg 4 000 rgmii rxd 3 7 179 R 8 881 R rgmii rx clk bufg 0 000 11 179 F 12 881 F rgmii rx clk bufg 4 000 buesilaoce Qmeeenteeucceqescece eemiteuqereeeecumeeedsnsescpeseesccilc Each Input lists two sets of values one corresponding to the ve edge of the clock and one to the ve edge The first set listed corresponds to ve edge which occurs at time 8 ns as we have delayed the clock to use the following ve edge The implementation requires 7 179 ns of setup to the ve edge Figure 9 4 illustrates that this represents 0 821 ns relative to the following rising edge of the clock since the IDELAY has
98. i cn E ET usr_teof_n is active low active low www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Conventions XILINX Online Document The following linking conventions are used in this document Convention Meaning or Use Example See the section Additional Cross reference link to a Resources for details Blue text location in the current document See Title Formats in Chapter 1 for details Blue underlined text Hyperlink to a website URL Go to www xilinx com for the latest speed files List of Acronyms The following table describes acronyms used in this manual Acronym Spelled Out CLB Configurable Logic Block DCM Digital Clock Manager DDR Double Data Rate FCS Frame Check Sequence FPGA Field Programmable Gate Array GBIC Gigabit Interface Converter Gbps Gigabit per second GEMAC Gigabit Ethernet Media Access Controller GMII Gigabit Media Independent Interface HDL Hardware Description Language IO Input Output IOB Input Output Block IP Intellectual Property ISEG Integrated Software Environment LSW Least Significant Word MAC Media Access Controller MDIO Management Data Input Output MHz Mega Hertz MMD MDIO Managed Device ms milliseconds MSW Most Significant Word 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 www xilinx com
99. ics vector 27 0 rx statistics valid host clk host miim sel host req host addr 8 0 host addr 9 host wr data 31 0 host rd data 31 0 host rd data mac 31 0 host rd data stats 31 0 Ethernet Statistics Example Design tx clik tx statistics vector 31 0 tx statistics valid rx_clk rx_statistics_vector 27 0 rx_statistics_valid host_clk host_miim_sel host_req host addr 8 0 host addr 9 host rd data 31 0 Interfacing the Ethernet Statistics to the 1 Gigabit Ethernet MAC 120 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Ethernet Statistics Core XILINX The management interfaces of the two cores can be shared by avoiding bus conflict as follows e Selecting a different address range for the statistics to that of the MAC configuration registers This is achieved by setting host_addr 9 to logic 0 when reading from the statistics and logic 1 when writing and reading to the MAC configuration registers e Using the host_miim_sel signal to differentiate between a statistical counter read and a MAC initiated MDIO transaction This is achieved by setting host_miim_sel to logic 0 for a statistical counter read and logic 1 for a MAC initiated MDIO transaction Table 11 1 describes the type of host transactions that occur if the host interface is shared as illustrated in Figure 11 5 Table 11 1 Management Interface Transact
100. ient Interface 0 0 0 0 00 ccc eese eee 129 Table A 4 Receive FIFO LocalLink Interface 000 000 c ccc eee ene 129 Appendix B Core Verification Compliance and Interoperability Appendix C Calculating DCM Phase Shifting Appendix D Core Latency 14 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 XILINX DISCONTINUED PRODUCT Preface About This Guide Guide Contents The LogiCORE IP 1 Gigabit Ethernet MAC User Guide provides information about generating the core customizing and simulating the core utilizing the provided example design and running the design files through implementation using the Xilinx tools This guide contains the following chapters Preface About this Guide introduces the organization and purpose of the guide and the conventions used in this document Chapter 1 Introduction describes the core and related information including recommended design experience additional resources technical support and submitting feedback to Xilinx Chapter 2 Core Architecture provides an overview of the core and discusses the Physical Client signal interfaces Chapter 3 Generating the Core describes the graphical user interface options used to generate the core Chapter 4 Designing with the Core through Chapter 8 Configuration and Status describe design parameters including how to initialize the core generate and
101. ific to that family is used in the example design IOB LOGIC IOB LOGIC BUFG rgmii tx clk bufg l l l gtx_clk SBUE rgmii txc l gt I l b gtx clk bufg mm J I l DoS ce a ee ee Ra E ee o zu IOB LOGIC 1 Gigabit Ethernet MAC Core l FDORRSE l l A l gmii_txd 0 gmii txd int O l gt CS rgmii txd o l gmii txd 4 gmii txd int 4 i Q l l l ces s FDDRRSE l l I gmii_tx_en_int E OBUF rgmii tx cti p l gmii_tx_er_int l l l E J Figure 7 4 External RGMII Transmitter Logic 66 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Implementing External RGMII XILINX Figure 7 4 shows that the output transmitter signals are registered on gtx_clk_bufg in the FPGA fabric including the encoded rgmii tx ctl int signal derived from the logicalxorofgmii tx en intandgmii tx er int Thesignalsto be transmitted on the RGMII falling clock edge are then registered on the falling edge of this clock This ensures that the data is presented to the Double Data Rate registers at the correct time Finally the transmitter signals are registered by an IOB output Double Data Rate DDR register before being driven to output pads The logic required to forward the transmitter clock is also shown This uses an IOB output DDR register so the clock signal produced incurs on exactly the same delay as the data an
102. ing ssseeesseeeee eere 84 Configuration Register Read Timing ssuueueseeeeeeeeeeese 84 Address Table Write Timing sss 85 Address Table Read Timing sss 86 Typical MDIO managed System sss 87 MDIO Write Transaction lssessseeeeee e 87 MDIO Read Transaction llllssssssss eee 88 MDIO Access through Management Interface ssssusuuues 89 Chapter 9 Constraining the Core Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Chapter 10 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Inp t GMII Timing ps ressu edd bak etr XU E E ac ey Seca 97 Timing Report Setup Hold Illustration 0000 101 Input RGMII TIMIN eiretie enii rir birnir ere itige eia 102 Timing Report Setup Hold Illustration 00 107 Clocking and Resetting Clock Management Logic with External GMII 0 109 Clock Management with External RGMII 00 00005 110 Clock Management Logic with External GMII Multiple Cores 111 Clock Management Logic with External RGMII Multiple Cores 112 Reset Circuit for a Single Clock reset Domain 112 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT EZ XILINX Chapter 11 Interfacing to Other Cores Figure 11 1 1 Gigabit Ethernet MAC Extended
103. ing 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 35 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 4 Designing with the Core lt component_name gt _example_design Statistics Vectors Interface lt component_name gt _locallink lt component_name gt _block Clock Reset Circuitry 1 Gigabit Ethernet MAC Core Physical 10 Mbps 100 Mbps Client Interface 1 Gbps Ethernet FIFO Interface Tx Client FIFO GMII RGMII Interface Logic IOBs and Clock Rx Client Management FIFO Address Swap Module o o s E c o c R4 a oO o o Management Interface Figure 4 1 1 Gigabit Ethernet MAC Core Example Design Using the example design as a starting point you can do the following e Edit the HDL top level of the example design file to Change the clocking scheme Add remove IOBs as required Replace the client loopback logic with your specific application logic Adapt the 10 Mbps 100 Mbps 1 Gbps Ethernet FIFO to suit your specific application see Using the Client Side FIFO e Synthesize the entire design The Xilinx Synthesis Tool XST script and Project file in the inplement directory may be adapted to include any HDL files you may want to add e Run the implement script in the implement directory to create a top level netlist for the design The script may also run the Xilinx tools map par and bitgen creating a bitstream that can be dow
104. ing an internal interface in conjunction with the Ethernet 1000BASE X PCS PMA or SGMII core see Chapter 11 Interfacing to Other Cores The remainder of this chapter describes how to use the core with an external GMII or RGMII See also Chapter 9 Constraining the Core for a listing of required constraints Implementing External GMII The HDL example design that is delivered with the core will implement an external GMIT when GMII is selected from the CORE Generator GUI see Chapter 3 Generating the Core For more information about the example design see the 1 Gigabit Ethernet MAC Getting Started Guide GMII Transmitter Logic Figure 7 1 illustrates how to use the physical transmitter interface of the core to create an external GMII in a Spartan 3 device The signal names and logic shown in this figure exactly match those delivered with the example design when the GMII is selected If other families are chosen equivalent primitives and logic specific to that family is used in the example design Figure 7 1 shows that the output transmitter signals are registered in device IOBs before driving them to the device pads The logic required to forward the transmitter clock is also shown This logic uses an IOB output Double Data Rate DDR register so that the clock signal produced incurs exactly the same delay as the data and control signals This clock signal gmii tx clk is inverted with respect to gtx_c1k so that the rising edge of
105. ion Types Transaction host_miim_sel host_addr 9 Configuration 0 1 MIIM access 1 X Statistics Read 0 0 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 121 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 11 Interfacing to Other Cores 122 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 12 Implementing Your Design This chapter describes how to simulate and implement your design containing the GEMAC core Pre implementation Simulation A unit delay structural model of the GEMAC core netlist is provided as a CORE Generator output file This can be used for simulation of the block in the design phase of the project Using the Simulation Model For information about setting up your simulator to use the pre implemented model see the Xilinx Synthesis and Verification Design Guide included in your Xilinx software installation The unit delay structural model of the GEMAC core can be found in the CORE Generator project directory Details of the CORE Generator outputs can be found in the 1 Gigabit Ethernet MAC Getting Started Guide VHDL e component name vhd Verilog lt component_name gt v Synthesis XST VHDL A component and instantiation template for the core named lt component_name gt vho is provided in the CORE Generator project directory Use this to help instance the GEMAC
106. is present on rx_data 21 VLAN frame Asserted if the previous frame contained a VLAN identifier in the length type field when receiver VLAN operation is enabled 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 www xilinx com 45 DISCONTINUED PRODUCT EZ XILINX Chapter 5 Using the Client Side Data Path Table 5 2 Bit Definition for the Receiver Statistics Vector rx_statistics_vector bit s 20 Name Out of Bounds Description Asserted if the previous frame exceeded the specified IEEE802 3 2005 maximum legal length see Maximum Permitted Frame Length This is only valid if jumbo frames are disabled 19 Control Frame Asserted if the previous frame contained the special control frame identifier in the length type field Frame Length The length of the previous frame in number of bytes The count will stick at 16 383 for any jumbo frames larger than this value Multicast Frame Asserted if the previous frame contained a multicast address in the destination address field Broadcast Frame Asserted if the previous frame contained the broadcast address in the destination address field FCS Error Asserted if the previous frame received had an incorrect FCS value or the MAC detected error codes during frame reception Bad Frame Asserted if the previous frame received contained errors Good Frame Asserted if t
107. is shown in the previous UCF syntax for host c1k www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Required Constraints XILINX The UCF syntax which follows targets the MDIO logic flip flops and groups them together Reduced clock period constraints are then applied HERRERA HE HE HE HE HE HE HE HE HE HE E FE HE FE FE FE HE HE REE FE FE FE HE FE FE FE HE HE FE FE FE FHE HE HE FE FHE HE HE HE FE FE HE HE HE EE HE MDIO Constraints please do not edit EHE FE FE HE HE HE FE HE HE HE HE HE HE HE HE HE HE E FE HE HE FE AE HE HE FE AE HE HE FE FE FE HE FE FE FE HE FE FE FE FE HE EHH HE FE FE FE HE HE HE E E E HEE Place the MDIO logic in it s own timing groups INST gmac_core BU2 U0 MANIFGEN MANAGEN PHY ENABLE_REG TNM INST gmac core BU2 U0 MANIFGEN MANAGEN PHY READY INT TNM INST gmac core BU2 U0 MANIFGEN MANAGEN PHY STATE COUNT TNM INST gmac core BU2 U0 MANIFGEN MANAGEN PHY MDIO TRISTATE TNM mdc rising mdc rising FFS mdc rising mdc falling INST gmac core BU2 U0 MANIFGEN MANAGEN PHY MDIO OUT TNM mdc falling TIMEGRP mdio logic mdc rising mdc falling TIMESPEC TS mdiol PERIOD mdio logic 400 ns TIMESPEC TS mdio2 FROM mdc rising TO mdc falling 200 ns Timespecs for Critical Logic within the Core Signals must cross clock domains at certain points in the core as described in the following sections Flow Control Paus
108. ission via the GEMAC When a full frame has been written into the transmit FIFO the FIFO will present data to the MAC transmitter On receiving the tx_ack signal from the MAC the rest of the frame is transmitted to the MAC VHDL The generic FULL_DUPLEX_ONLY is provided to allow the removal of logic and performance constraints necessary for half duplex operation when using with the Xilinx Tri Mode Ethernet MAC core This generic can always be set to true when the FIFO is used with the GEMAC 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 131 UG144 April 24 2009 XILINX DISCONTINUED PRODUCT Appendix A Using the Client Side FIFO Verilog The compiler directive FULL_DUPLEX_ONLY is defined to allow for removal of logic and performance constraints that are necessary only in half duplex operation that is when using with the Tri Mode Ethernet MAC core This directive can always be defined when the FIFO is used with the GEMAC The FIFO has two signal inputs specific to half duplex operation tx_collision and tx_retransmit These signals are provided to make the FIFO compatible with both the 1 Gigabit Ethernet MAC and Tri Mode Ethernet MAC cores and should be tied to logic 0 when using the FIFO with the GEMAC core If the FIFO memory fills up the dst_rdy_out_n signal is used to halt the LocalLink interface writing in data until space becomes available in the FIFO If the FIFO memory fills up but no frames are
109. ith the example design included with the GEMAC core see the 1 Gigabit Ethernet MAC Getting Started Guide General Design Guidelines This section describes the steps required to turn a GEMAC core into a fully functioning design integrated with user application logic Not all implementations require all the design steps described in this chapter The following sections discuss the design steps required for various implementations For best results carefully follow the logic design guidelines Design Steps Generate the core from the Xilinx CORE Generator See Chapter 3 Generating the Core Using the Example Design as a Starting Point The GEMAC core is delivered through the CORE Generator with an HDL example design built around the core allowing the functionality of the core to be demonstrated using either a simulation package or in hardware if placed on a suitable board Figure 4 1 is a block diagram of the example design For more information about the example design see the 1 Gigabit Ethernet MAC Getting Started Guide The example design illustrates how to e nstantiate the core from HDL e Source and use the client side interface ports of the core from application logic e Connect the physical side interface of the core GMII or RGMII to device IOBs creating an external interface See Chapter 7 Using the Physical Side Interface e Derive the clock management logic as described in Chapter 10 Clocking and Resett
110. iver Interface Table 2 2 describes the client side receiver signals of the GEMAC core These signals are used by to transfer data to the client See Receiving Inbound Frames on page 39 Table 2 2 Receive Client Interface Signal Pins Signal Direction Clock Domain Description rx data 7 0 Output gmii rx clk Frame data received is supplied on this port rx data valid Output gmii rx clk Control signal for the rx data port rx good frame Output gmii rx clk Asserted at end of frame reception to indicate that the frame should be processed by the MAC client rx bad frame Output gmii rx clk Asserted at end of frame reception to indicate that the frame should be discarded by the MAC client rx statistics vector 27 0 Output gmii rx clk Provides statistical information about the last frame received rx statistics valid Output gmii rx clk Asserted at end of frame reception indicating that the rx statistics vector is valid Flow Control Interface Table 2 3 describes the signals used by the client to request a flow control action from the transmit engine See Using Flow Control on page 53 Table 2 3 Flow Control Interface Signal Pinout Signal Direction Clock Domain Description pause req Input gtx clk Pause request sends a pause frame down the link pause val 15 0 Input gtx clk Pause value inserted into the parameter field of the transmitted pause frame
111. ividual packet boundaries are marked by the so n and eof n signals For more information on the LocalLink interface see to Xilinx Application Note XAPP691 Parameterizable LocalLink FIFO available at direct xilinx com bvdocs appnotes xapp691 pdf Figure A 2 shows the transfer of an 8 byte frame clock V N VY VY VY NY NY NY NY NY data 7 0 C 0 X 1 X 2 X 3 X 4 X 5 X 6 X 7 sini M cea NW i src rdy n N ft L dst rdy n Figure A 2 Frame Transfer across LocalLink Interface Figure A 3 illustrates frame transfer of a 5 byte frame where both the src_rdy_n and dst rdy nsignals are used to control the flow of data across the interface clock N NN NY YY YY YY NY S data 7 0 0 AX 1 2 K 3 K 4 sof n E h WEN 33 WU eof n EHE WEN w A AB si dy Nc l 2L 2 No cL S y deiude Nea oo Figure A 3 Frame Transfer with Flow Control 130 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Functional Operation DISCONTINUED PRODUCT EZ XILINX Functional Operation Clock Requirements The FIFO is designed to work with rx clkand tx_clk running at MAC clock speeds up to 125 MHz The rx_11_clock should be no slower than the xx c1k Thetx 11 clock should be no slower than the clock on the transmitter client interface divided by 2 For this reason it is suggested that the rx
112. l Pins 0 27 Table 2 3 Flow Control Interface Signal Pinout nananana sarran 27 Table 2 4 Optional Management Interface Signal Pinout 05 28 Table 2 5 Optional MAC Unicast Address Signal Pinout 005 28 Table 2 6 Optional Configuration Vector Signal Pinout 00005 29 Table 2 7 Reset Signal ciii ree E Ee Levee Serie hace Pee eee ERE 29 Table 2 8 GMII Interface Signal Pinout 0 eee 29 Table 2 9 MDIO Interface Signal Pinout 0 eee es 30 Chapter 3 Generating the Core Table 3 1 XCO File Values and Default Values 0 0 cece cece ees 33 Chapter 4 Designing with the Core Table 4 1 Degree of Difficulty for Various Implementations 38 Chapter 5 Using the Client Side Data Path Table 5 1 Abbreviations Used in Timing Diagrams 0000 eee 39 Table 5 2 Bit Definition for the Receiver Statistics Vector 000 08 45 Table 5 3 Rx Statistics conversion to previous core GEMAC core versions 46 Table 5 4 Bit Definition for the Transmitter Statistics Vector 04 51 Table 5 5 Tx Statistics conversion to previous core GEMAC core versions 52 Chapter 6 Using Flow Control Chapter 7 Using the Physical Side Interface Chapter 8 Configuration and Status Table 8 1 Management Interface Transaction Types 0 00 e cece ee eens 77
113. ld and any padding is not removed from the frame 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 43 UG144 April 24 2009 EZ XILINX 44 DISCONTINUED PRODUCT Chapter 5 Using the Client Side Data Path Address Filter If the optional Address Filter is included in the core the MAC is able to reject frames that do not contain a known address in their destination address field If a frame is rejected the rx data validsignalis not asserted for the duration of the frame In addition neither rx good frame orrx bad frame are asserted at the end of the frame The statistics vectors are still output with a valid pulse at the end of the rejected frame If the Address Filter is not in promiscuous mode it will reject frames in which the destination address does not meet any of the following criteria e Itis equal to the broadcast address defined in the IEEE 802 3 2005 specification e It is equal to the pause multicast address defined in the IEEE 802 3 2005 specification e The destination address field contains the pause frame MAC source address specified in the Receiver Configuration Word 0 and Word 1 e It is equal to the MAC unicast address When the optional Management Interface is present this is found in the unicast address configuration registers Table 8 8 and Table 8 9 page 82 If the Management Interface is not present the unicast address is input on the mac_unicast_address input e It matches any of the addres
114. linx will provide technical support for use of this product as described in the 1 Gigabit Ethernet MAC User Guide and the 1 Gigabit Ethernet MAC Getting Started Guide Xilinx cannot guarantee timing functionality or support of this product for designs that do not follow these guidelines Feedback Xilinx welcomes comments and suggestions about the GEMAC core and the documentation supplied with the core GEMAC Core For comments or suggestions about the GEMAC core please submit a WebCase from support xilinx com Be sure to include the following information e Product name e Core version number e Explanation of your comments Document For comments or suggestions about this document please submit a WebCase from support xilinx com Be sure to include the following information e Document title e Document number e Page number s to which your comments refer e Explanation of your comments 20 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 2 Core Architecture This chapter describes the GEMAC core architecture including the major functional blocks and all interfaces System Overview Figure 2 1 illustrates a block diagram of the GEMAC core with all the major functional blocks and interfaces Descriptions of the functional blocks and interfaces are provided in the sections that follow Gigabit Ethernet MAC Core Client Transmit
115. ll frames are passed to the receiver client regardless of the destination address Writing and Reading to and from the Configuration Registers Writing to the configuration registers through the management interface is shown in Figure 8 1 When accessing the configuration registers when host_addr 9 1 and host miim sel 0 the upper bit of host opcode functions as an active low write enable signal The lower host opcode bit is a don t care bit 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 www xilinx com 83 DISCONTINUED PRODUCT XILINX Chapter 8 Configuration and Status host_clk host_miim_sel host opcode 1 host addr 8 0 host addr 9 na host wr data 31 0 Figure 8 1 Configuration Register Write Timing Reading from the configuration register words is similar but the upper host opcode bit should be 1 as shown in Figure 8 2 In this case the contents of the register appear on host rd data thehost clk edge after the register address is asserted onto host addr host clk host miim sel host opcode 1 host addr 8 0 host addr 9 ta host rd data 31 0 Figure 8 2 Configuration Register Read Timing 84 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Using the Optional Management Interface XILINX Accessing the Address Table To write to a specific entry in the addre
116. main For this reason userclk2 is used as the 125 MHz reference clock for both cores and the transmitter and receiver logic of the GEMAC core now operate in the same clock domain This allows clock crossing constraints between the gtx c1k and gmii rx clk clock domains to be removed from the GEMAC UCF See Timespecs for Critical Logic within the Core Virtex 5 FXT Devices Figure 11 4 illustrates the connections and clock management logic required to interface the GEMAC core to the Ethernet 1000BASE X PCS PMA or SGMII core when used in 1000BASE X mode with PMA using the device specific RocketIO transceiver DCM CLKIN CLKO brefclkp IBUFGDS FB clkin CLKDV gt brefclkn 125MHz component_name_block Block Level from example design 1 Gigabit Ethernet Ethernet 1000BASE X MAC PCS PMA or SGMII LogiCORE LogiCORE Virtex 5 GTX RocketlO REFCLKOUT gmii rx clk 4 gmii_txd 7 0 gmii_tx_en gmii_tx_er gmii_rxd 7 0 gmii_rx_dv gmii_rx_er mdio tri gmii txd 7 0 gmii tx en gmii tx er gmii_rxd 7 0 gmii_rx_dv gmii_rx_er RocketlO I F mdio_tri Figure 11 4 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS and PMA 118 using the RocketlO transceiver www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Ethernet Statistics Core XILINX Features of this configuration include e Direct internal connection
117. me_block Block Level from example design 1 Gigabit Ethernet Ethernet 1000BASE X MAC PCS PMA or SGMII LogiCORE LogiCORE gtx_clk gmii_txd 7 0 gmii_txd 7 0 gmii_tx_en gmii_tx_en gmii_tx_er gmii tx er gmii_rxd 7 0 gmii_rxd 7 0 gmii_rx_dv gmii_rx_dv gmii_rx_er gmii_rx_er mdio_tri connection 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS with TBI 114 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Ethernet 1000Base X PCS PMA or SGMII Core XILINX Integration to Provide 1000BASE X PCS and PMA using a RocketlO Transceiver Virtex 4 Devices Figure 11 2 illustrates the connections and clock management logic required to interface the GEMAC core to the Ethernet 1000BASE X PCS PMA or SGMII core when used in 1000BASE X mode with PMA using the device specific RocketlO MGT transceiver Virtex 4 brefclkp GT11CLK_MGT 125 MHz MGTCLKP MGTCLKN brefclkn 125 MHz synclk1 125MHz SYNCLK10UT component_name_block Block Level from example design 1 Gigabit Ethernet Ethernet 1000BASE X MAC PCS PMA or SGMII LogiCORE LogiCORE Virtex 4 GT11 RocketlO userclk lt TXOUTCLK1 gmii rx clk lt userclk2 REFCLK1 lt N TXUSRCLK gmii_txd 7 0 TXUSRCLK2 gmii tx en ii Dx j RXUSRCLK gmii tx er RXUSRCLK2 gmii_rxd 7 0 gmii_rxd 7 0 gmii_rx_dv gmii_rx_dv gmii_rx_er gmii_rx_er RocketlO I F mdio tri n
118. meterizable LocalLink FIFO Xilinx Application Note XAPP691 Parameterizable LocalLink FIFO found at direct xilinx com bvdocs appnotes xapp691 pdf www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Appendix B Core Verification Compliance and Interoperability The GEMAC core has been verified with extensive simulation and hardware testing Verification by Simulation A highly parameterizable transaction based test bench not part of the core deliverables was used to test the core Tests include e Register Access e MDIO Access e Frame Transmission and error handling e Frame Reception and error handling e Address Filtering Hardware Verification The GEMAC core has been tested in a variety of hardware test platforms at Xilinx to include a variety of parameterizations including the following The core has been tested with the Ethernet 1000BASE X PCS PMA or SGMII core from Xilinx This follows the architecture shown in Figure 11 2 page 115 A test platform was built around these cores including a back end FIFO capable of performing a simple ping function and a test pattern generator Software running on the embedded PowerPC processor was used to provide access to all configuration status and statistical counter registers Version 3 0 of this core was taken to the University of New Hampshire Interoperability Lab UNH IOL where conformance and inter
119. mii_rx_clk lt IOB LOGIC gmii_rxd_int 0 l l l mii rxd O n g 0 gmii xd int 4 pa rgmii rxd 0 gmii_rxd 4 D i IPAD l l l l l Pe Fee ee ee ee ee IOB LOGIC PP ee M l IDDR l RET gmii rx dv int ai IBUF gmii_rx_er C K Q D d 2 l l l l E E ee es E E ee Figure 7 8 External RGMII Receiver Logic for Virtex 4 Devices 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 73 UG144 April 24 2009 EZ XILINX 74 DISCONTINUED PRODUCT Chapter 7 Using the Physical Side Interface Virtex 5 Devices Figure 7 9 shows using the physical receiver interface of the core to create an external RGMIL ina Virtex 5 device The signal names and logic exactly match those delivered with the example design when RGMII is selected Figure 7 9 also shows that the input receiver signals are registered in the IOBs in IDDR components These components convert the input double data rate signals into GMII specification signals The gmii rx er intsignalis derived in the FPGA fabric from the outputs of the control IDDR component IOB LOGIC 1 Gigabit Ethernet MAC Core gmii rx clk bufg gmii rx clk 4 E gmii rxd int 0 gmii_rxd 0 rgmii_rxd 0 gmii_rxd 4 ii dv_int gmii_rx_dv gmii_rx_dv_in gmii_rx_er Figure 7 9 External RGMII Receiver Logic for Virtex 5 Devices The IODELAY components are used to phase shift the input RGMII clock data and control signals to meet th
120. ncluded in the core The configuration_vector 67 0 input provides the method for configuration of the core and mac_unicast_address 47 0 input provides the method of setting the unicast address used by the Address Filter Client Side Interface Physical Side Interface GMII gtx_clk domain gtx elk tx_data 7 0 tx_data_valid tx_ifg_delay 7 0 tx_ack tx_underrun tx statistics vector 31 0 tx statistics valid pause req pause val 15 0 gmii txd 7 0 gmii tx en gmii tx er gmii rx clk domain rx data 7 0 rx data valid rx good frame rx bad frame rx statistics vector 27 0 rx statistics valid Q gmii rx clk H gmii rxd 7 0 gmii rx dv H gmii rx er mac unicast address 47 0 configuration vector 67 0 reset Figure 2 3 Component Pinout for MAC without Optional Management Interface and with Optional Address Filter 24 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Core Interfaces EZ XILINX GEMAC Core Without Management Interface and Without Address Filter Figure 2 4 shows the pinout for the GEMAC core when the optional Management Interface is omitted and the optional Address Filter is omitted The configuration_vector 67 0 input provides the method for configuration of the core Client Side Interface Physical Side Interface GMII gtx_clk domain gtx_clk tx_data 7 0 tx_
121. nloaded to a Xilinx device SimPrim based simulation models for the entire design are also produced by the implement scripts e Simulate the entire design using the demonstration test bench provided as a template in the simulation directory e Download the bitstream to a target device 36 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT General Design Guidelines XILINX Implementing the 1 Gigabit Ethernet MAC in Your Application The example design can be studied as an example of how to do the following e Instantiate the core from HDL e Source and use the client side interface ports of the core from application logic e Connect the physical side interface of the core GMII or RGMII to device IOBs to create an external interface e Derive the clock management logic After working with the example design you can write your own HDL application using single or multiple instances of the GEMAC core Client side interfaces and operation of the core are detailed later in this chapter For more information see e Clock Management Logic in Chapter 10 Clocking and Resetting e Using the GEMAC core in conjunction with the Ethernet 1000BASE X PCS PMA or SGMII core in Chapter 11 Interfacing to Other Cores e Using the GEMAC core in conjunction with the Ethernet Statistics core in Chapter 11 Interfacing to Other Cores e 10 Mbps 100 Mbps 1 Gbps Ethernet FIFO in
122. ns E M jr A 6 134 ns _ tsetup 8 6 134 1 866 ns At t on 7 554 8 lt 7 554 ns gt 0 446 ns w 8 ns Figure 9 2 Timing Report Setup Hold Illustration Constraints when Implementing an External RGMII The constraints defined in this section are implemented in the UCF for the example design delivered with the core Sections from this UCF are copied into the following descriptions to provide examples These examples should be studied in conjunction with the HDL source code for the example design and with the description Implementing External GMII on page 61 RGMII IOB Constraints The following constraints target the flip flops that are inferred in the top level HDL file for the example design Constraints are set to ensure that these are placed in IOBs The DDR register constraints are not present for a Virtex 4 device or Virtex 5 device where DDR components are instantiated rather than inferred RGMII Receiver Constraints place DDR registers in IOB INST rgmii_interface rgmii_rxd_ddr IOB true INST rgmii interface rgmii rx dv ddr IOB true INST rgmii interface rgmii rx ctl ddr IOB true Inband Status Registers place registers in IOB NST rgmii interface link status IOB true NST rgmii interface clock speed IOB true NST rgmii interface duplex status IOB true HHH 4 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com
123. ns see Chapter 2 Licensing the Core in the 1 Gigabit Ethernet MAC Getting Started Guide Recommended Design Experience Although the GEMAC core is a fully verified solution the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application For best results previous experience building high performance pipelined FPGA designs using Xilinx implementation software and user constraint files UCFs is recommended Contact your local Xilinx representative for a closer review and estimation for your specific requirements Additional Core Resources For detailed information and updates about the GEMAC core see the following documents located on the GEMAC product page e 1 Gigabit Ethernet MAC Data Sheet e 1 Gigabit Ethernet MAC Getting Started Guide After generating the core the 1 Gigabit Ethernet MAC Release Notes are available from the document directory Related Xilinx Ethernet Products and Services See the Ethernet Products and Services page 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 19 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 1 Introduction Specifications e IEEE 802 3 2005 e Reduced Gigabit Media Independent Interface RGMII version 2 0 Technical Support For technical support see support xilinx com Questions are routed to a team of engineers with expertise using the GEMAC core Xi
124. nterfaces Core Interfaces EZ XILINX GMAC Core with Optional Management Interface Figure 2 2 shows the pinout for the GEMAC core using the optional Management Interface The interface is unchanged regardless of whether the optional Address Filter is included Client Side Interface Physical Side Interface GMII gtx_clk domain gtx_clk tx_data 7 0 tx_data_valid tx_ifg_delay 7 0 tx_ack tx_underrun tx_statistics_vector 31 0 tx_statistics_valid pause_req pause val 15 0 gmii_txd 7 0 gmii_tx_en gmii tx er gmii rx clk domain rx data 7 0 rx data valid rx good frame rx bad frame rx statistics vector 27 0 rx statistics valid Q gmii rx clk I gmii rxd 7 0 gmii rx dv gmii rx er host clk domain host clk host opcode 1 0 host addr 9 0 host wr data 31 0 9 host rd data 31 0 host miim sel host req gt host miim rdy mdc mdio in mdio out mdio tri reset Figure 2 2 Component Pinout for MAC with Optional Management Interface 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com UG144 April 24 2009 23 DISCONTINUED PRODUCT EZ XILINX Chapter 2 Core Architecture GMAC Core Without Management Interface and With Address Filter Figure 2 3 shows the pinout for the GEMAC core when the optional Management Interface is omitted and the optional Address Filter is i
125. o connection Figure 11 2 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS and PMA using a RocketlO Transceiver 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 115 UG144 April 24 2009 EZ XILINX 116 DISCONTINUED PRODUCT Chapter 11 Interfacing to Other Cores Figure 11 2 illustrates the following Direct internal connections are made between the GMII interfaces between the two cores If the GEMAC has been generated with the optional Management Interface the MDIO port can be connected up to that of the Ethernet 1000BASE X PCS PMA or SGMII core to access its embedded configuration and status registers See Using the Optional Management Interface Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE X PCS PMA or SGMII core the entire GMII is synchronous to a single clock domain For this reason userclk2 is used as the 125 MHz reference clock for both cores and the transmitter and receiver logic of the GEMAC core now operate in the same clock domain This allows clock crossing constraints between the gtx c1k and gmii rx clk clock domains to be removed from the GEMAC UCF See Timespecs for Critical Logic within the Core www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Ethernet 1000Base X PCS PMA or SGMII Core XILINX Virtex 5 LXT and SXT Devices Figure 11 3 illustrates the connections and clock management logic required
126. o are registered trademarks of IBM Corp and used under license All other trademarks are the property of their respective owners www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Revision History The following table shows the revision history for this document Date Version Revision 09 30 04 1 0 Initial Xilinx release 04 28 05 2 0 Updated to 1 Gigabit Ethernet MAC version 6 0 Xilinx tools v7 1i SP1 01 18 06 3 0 Updated to 1 Gigabit Ethernet MAC version 7 0 Xilinx tools v8 1i 07 13 06 4 0 Updated to 1 Gigabit Ethernet MAC version 8 0 Xilinx tools v8 2i 09 21 06 4 1 Updated to 1 Gigabit Ethernet MAC version 8 1 added support for Spartan 3A platform 02 15 07 4 2 Updated to 1 Gigabit Ethernet MAC version 8 2 Xilinx tools v9 1i 08 08 07 5 0 Advanced core version to 8 3 updated various tool versions and trademarks for the IP1IJade Minor release 03 24 08 6 0 Updated core version to 8 4 Xilinx tools 10 1 04 24 09 7 0 Updated core version to 8 5 Xilinx tools 11 1 The product was discontinued as of August 31 2009 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com UG144 April 24 2009 DISCONTINUED PRODUCT www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Table of Contents Schedule of Figures aaan ccc rererere rrr 9 Schedule of Tables
127. o the following frequency restriction 2 10 MHz Configuring the GEMAC core to derive the mdc signal from this clock is detailed in MDIO Interface on page 86 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 77 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX 78 Configuration Registers Chapter 8 Configuration and Status After a power up or system reset the client may reconfigure the core parameters using their defaults Configuration changes can be written at any time Both the receiver and transmitter logic responds only to configuration changes during inter frame gaps The exceptions to this are the configurable resets that take effect immediately Configuration of the GEMAC core is performed through a register bank that is accessed through the management interface The configuration registers available in the core are listed in Table 8 2 As shown the address has some implicit don t care bits any access to an address in the ranges shown performs a 32 bit read or write from the same configuration word Table 8 2 Configuration Registers Address Description 0x200 0x23F Receiver Configuration Word 0 0x240 0x27F Receiver Configuration Word 1 0x280 0x2BF Transmitter Configuration 0x2C0 0x2FF Flow Control Configuration 0x300 0x33F Reserved 0x340 0x37F Management Configuration 0x380 0x383 Unicast Address Word 0 if Address Filter is present 0x
128. olve this data rate matching problem Flow Control Basics 54 A MAC may transmit a pause control frame to request that its link partner cease transmission for a defined period of time For example the user MAC on the left side of Figure 6 1 may initiate a pause request when its client FIFO illustrated reaches a nearly full state A MAC should respond to received pause control frames by ceasing transmission of frames for the period of time defined in the received pause control frame For example the link partner MAC in Figure 6 1 may cease transmission after receiving the pause control frame transmitted by the user MAC In a well designed system the link partner MAC would cease transmission before the client FIFO experienced an overflow condition This provides time for the FIFO to be emptied to a safe level before normal operation resumes thus safeguarding the system against FIFO overflow conditions and frame loss www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Overview of Flow Control XILINX Pause Control Frames Control frames are a unique type of Ethernet frame defined in clause 31 of the IEEE 802 3 2005 standard Control frames are differentiated from other frame types by a defined value placed in the length type field MAC Control Type code Figure 6 2 illustrates the control frame format 6 OCTETS DESTINATION ADDRESS 6 OCTETS SOURCE ADDRESS FRAME 2 OCT
129. on Generating the Xilinx Netlist To generate the Xilinx netlist the ngdbuild tools are used to translate and merge the individual design netlists into a single design database the NGD file Also merged at this stage is the UCF for the design An example of the ngdbuild command is ngdbuild sd path to core netlist sd path to user synth results uc top level module name ucf top level module name Mapping the Design To map the logic gates of the user design netlist into the CLBs and IOBs of the FPGA run the map command The map command writes out a physical design to an NCD file An example of the map command is map o top level module name map ncd top level module name ngd top level module name pcf 124 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Post Implementation Simulation XILINX Placing and Routing the Design Execute the par command to place and route your design logic components mapped physical logic cells contained within an NCD file in accordance with the layout and timing requirements specified within the PCF file The par command outputs the placed and routed physical design to an NCD file An example of the par command is par top level module name map ncd top level module name ncd top level module name pcf Static Timing Analysis Execute the trace command to evaluate timing closure on a design and
130. on is enabled and an error free frame is received by the GEMAC core see Flow Control Configuration on page 81 the following frame decoding functions are performed e The destination address field is matched against the IEEE 802 3 globally assigned multicast address or the configurable pause frame MAC address see Configuration Registers on page 78 e The length type field is matched against the MAC control type code e The opcode field contents are matched against the Pause opcode If any of the previously described checks are false the frame is ignored by the Flow Control logic and passed up to the client logic for interpretation by marking it with rx good frame asserted It is then the responsibility of the MAC client logic to decode act on if required and drop this control frame If all the previously described checks are true the 16 bit binary value in the MAC Control Parameters field of the control frame is then used to inhibit transmitter operation for the required number of pause_quantum This inhibit is implemented by delaying the assertion of tx_ack at the transmitter client interface until the requested pause duration has expired The received pause frame is then passed on to the client with rx_bad_frame asserted to indicate to the client that the pause frame can be dropped Note Any frame in which the length type field contains the MAC control type should be dropped by the receiver client logic All control f
131. on of byte valid are valid only when tx statistic validis asserted Figure 5 11 Byte valid is significant on every gtx_clk cycle Caution The statistic vectors in this release have been made compatible with the Tri Mode Ethernet MAC core They are not backwards compatible with previous versions of the 1 Gigabit Ethernet MAC core see Table 5 5 for Transmitter Statistic Vector conversion details gtx_clk ix statistic valid N Figure 5 11 Transmitter Statistic Vector Timing 50 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Transmitting Outbound Frames 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT EZ XILINX Table 5 4 Bit Definition for the Transmitter Statistics Vector tx_statistics_vector 31 bit s Name Pause Frame Description Asserted if the previous frame was a pause frame that the MAC itself initiated in response to a pause_req assertion 30 Byte Valid Asserted if a MAC frame byte DA to FCS inclusive is in the process of being transmitted This is valid on every clock cycle Do not use this as an enable signal to indicate that data is present on gmii_txd 29 20 Reserved Always at logic 0 19 VLAN Frame Asserted if the previous frame contained a VLAN identifier in the length type field when transmitter VLAN operation is enabled Frame Length The lengt
132. onal Management Interface is not present Table 2 5 Optional MAC Unicast Address Signal Pinout Signal Direction Description mac unicast address 47 0 Input Used to assess the MAC unicast address registers when the Management Interface is not used Note All bits are registered on input but may be treated as asynchronous inputs 28 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Core Interfaces XILINX Configuration Vector Optional Table 2 6 describes the alternative to the optional Management Interface signals The Configuration Vector uses direct inputs to the core to replace the functionality of the MAC configuration bits See Access without the Management Interface on page 90 Table 2 6 Optional Configuration Vector Signal Pinout Signal Direction Description configuration_vector 67 0 Input Used to replace the functionality of the MAC Configuration Registers when the Management Interface is not used Note All bits are registered on input but may be treated as asynchronous inputs Asynchronous Reset Table 2 7 describes the asynchronous reset signal for the entire core Table 2 7 Reset Signal Signal Direction Clock Domain Description reset Input n a Asynchronous reset for entire core Physical Side Interface GMII Table 2 8 describes the GMII style interface signals of the core See C
133. onent is used in fixed delay mode where the attribute ODELAY_VALUE determines the tap delay value An IDELAYCTRL primitive must be instantiated for this mode of operation See the Virtex 5 User Guide for more information on the use of IDELAYCTRL and IODELAY components RGMII Receiver Logic 70 Spartan 3 Spartan 3E Spartan 3A and Spartan 3A DSP Devices Figure 7 7 shows using the physical receiver interface of the core to create an external RGMII in a Spartan 3 device The signal names and logic exactly match those delivered with the example design when the RGMII is selected If other families are used equivalent primitives and logic specific to that family is used in the example design Figure 7 7 also shows that the input receiver signals are registered in device IOBs on rising and falling edges of gmii rx clk bufg Thesignals are then registered inside the FPGA fabric before a final register stage to synchronize signals to the rising edge clock To achieve the required setup and hold times across the interface the DCM uses a phase shift to adjust the clock relative to the data See Appendix C Calculating DCM Phase Shifting DCM Reset circuitry A DCM reset module not illustrated in Figure 7 7 is also present and is instantiated in the example design next to the DCM Since this logic must be reliable whatever the reset locked status of the DCM the module requires a reliable reference clock In the example design for RGMII a
134. operability testing was performed The core has been tested with an external 1000BASE T PHY device The MAC was connected to the external PHY device using GMII RGMII and SGMII in conjunction with the Ethernet 1000BASE X PCS PMA or SGMII core The core has been tested with the Ethernet Statistics core from Xilinx following the architecture show in Figure 11 5 page 120 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 133 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Appendix B Core Verification Compliance and Interoperability 134 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Appendix C Calculating DCM Phase Shifting DCM Phase Shifting A DCM is used in the receiver clock path to meet the input setup and hold requirements when using the core with an RGMII see Implementing External RGMII on page 66 and with an external GMII implementation in Spartan 3 Spartan 3E Spartan 3A and Virtex 4 devices see Spartan 3 Spartan 3E Spartan 3A and Virtex 4 Devices on page 63 In these cases a fixed phase shift offset is applied to the receiver clock DCM to skew the clock This performs static alignment by using the receiver clock DCM to shift the internal version of the receiver clock such that its edges are centered on the data eye at the IOB DDR flip flops The ability to shift the internal clock in small increments is
135. or Virtex 5 devices A fixed tap delay is applied to the rgmii_txc output clock to move the rising edge of this clock to the centre of the output data window For the receiver clock data and control signals a fixed tap delay can be applied to either delay the data and control signals or delay the clock so that the data control are correctly sampled by the rgmii_rxc clock at the IOB IDDR registers meeting RGMII setup and hold timing The choice of delaying data control or clock is dependant upon a number of factors not least being the required shift There are trade offs to be made with either choice Delaying the clock is clock period specific as we move the clock to line up each edge with data from the following edge Delaying the data control introduces more jitter which degrades the overall setup hold window The interface timing report in the two cases is also quite different See Understanding Timing Reports for RGMII Setup Hold timing The following constraint shows an example of setting the delay value for two of these IODELAY components Data Control bits can be adjusted individually to compensate for any PCB routing skew if desired 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 103 UG144 April 24 2009 DISCONTINUED PRODUCT uis XILINX Chapter 9 Constraining the Core INST rgmii interface delay rgmii tx clk IDELAY TYPE FIXED INST rgmii interface delay rgmii tx clk ODEL
136. ored in an address table in the Address Filter Table 8 10 and Table 8 11 describe how the contents of the address table are set Table 8 10 Address Table Configuration Word 0 Default ze Bits Value Description 31 0 All 0s MAC Address 31 0 The address is ordered so the first byte received is the lowest positioned byte in the register for example a MAC address of AA BB CC DD EE FF would be stored in Address 47 0 as OXFFEEDDCCBBAA Table 8 11 Address Table Configuration Word 1 Default T Bits Value Description 15 0 All 0s MAC Address 47 32 17 16 All Os The location in the address table that the MAC address is to be written to or read from There are up to 4 entries in the table Location 0 to 3 22 18 N A Reserved 23 0 Read not write This bit is set to 1 to read from the address table If it is set to 1 the contents of the table entry that is being accessed by the bits 17 16 will be output on the hostrddata bus in consecutive cycles least significant word first If it is set to 0 the data on bits 15 0 is written into the table at the address specified by bits 17 16 31 24 N A Reserved The contents of the Address Filter mode register are described in Table 8 12 Table 8 12 Address Filter Mode Default echo Bits Value Description 30 0 N A Reserved 31 0 Promiscuous Mode If this bit is set to 1 the Address Filter operates in promiscuous mode A
137. put N A Write clock for LocalLink interface tx ll reset Input tx ll clock Synchronous reset tx Il data in 7 0 Input tx ll clock Write data to be sent to transmitter tx Il sof in n Input tx Il clock Start of frame indicator tx ll eof in n Input tx ll clock End of frame indicator tx l src rdy in n Input tx Il clock Source ready indicator tx ll dst rdy out n Output tx ll clock Destination ready indicator tx fifo status 3 0 Output tx ll clock FIFO memory status tx overflow Output tx ll clock Overflow signal indicates when a frame has been dropped in the FIFO 128 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 Interfaces DISCONTINUED PRODUCT Receive FIFO Table A 3 describes the receive FIFO client interface For more information on the MAC client interface see Receiving Inbound Frames on page 39 Table A 3 Receive FIFO Client Interface EZ XILINX Clock Signal Direction Domain Description rx_clk Input N A Receive clock used by MAC rx_reset Input rx_clk Synchronous reset rx_enable Input rx_clk Clock enable for rx_clk tie to logic 1 when using GEMAC rx_data 7 0 Input rx_clk Data received from MAC rx_data_valid Input rx_clk Valid signal for data rx_good_frame Input rx_clk Indicates if frame is valid and should be accepted by client rx_bad_frame Input rx_clk Indicates if frame is invalid and should be dropped by th
138. r MAC without Optional Management Interface and with Optional Address Filter 0 0 eee 24 Figure 2 4 Component Pinout for MAC without Optional Management Interface or Optional Address Filter 0 n 25 Chapter 3 Generating the Core Figure 3 1 1 Gigabit Ethernet MAC Main Screen esee 31 Chapter 4 Designing with the Core Figure 4 1 1 Gigabit Ethernet MAC Core Example Design 0 36 Chapter 5 Using the Client Side Data Path Figure 5 1 Normal Frame Reception 0 6 6 c ccc eens 40 Figure 5 2 Frame Reception with Error 2 0 6666s 41 Figure 5 3 Frame Reception with In Band FCS Field 02 ec 0u 42 Figure 5 4 Reception of a VLAN Tagged Frame ssseeesse esses 42 Figure 5 5 Receiver Statistics Vector Timing 0666 eee 44 Figure 5 6 Normal Frame Transmission llllssseeeeeeeeese 47 Figure 5 7 Frame Transmission with Client supplied FCS 00 48 Figure 5 8 Frame Transmission with Underrun siusleslessseuses 48 Figure 5 9 Transmission of a VLAN Tagged Frame 000 000005 49 Figure 5 10 Inter Frame Gap Adjustment 0 0 0 eese 50 Figure 5 11 Transmitter Statistic Vector Timing 0 0 e eee eee eee 50 Chapter 6 Using Flow Control Figure 6 1 Requirement for Flow Control 0 c cece eens 53 Figure 6 2 MAC Control Frame Format 0
139. rames are indicated by rx_statistic_vector bit 19 see Receiver Statistics Vector on page 44 Client Initiated Response to a Pause Request For maximum flexibility flow control logic can be disabled in the core and alternatively implemented in the client logic connected to the core see Flow Control Configuration on page 81 Any type of error free control frame is then passed through the core with rx good frame asserted The frame is passed to the client for interpretation It is then the responsibility of the client to drop this control frame and to act on it by ceasing transmission through the core if applicable 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 57 UG144 April 24 2009 XILINX DISCONTINUED PRODUCT Chapter 6 Using Flow Control Flow Control Implementation Example This section provides a basic overview of a Flow Control implementation using Figure 6 1 as a sample To summarize the example the user MAC on the left hand side of the figure cannot match the full line rate of the link partner MAC on the right hand side due to clock tolerances Over time the FIFO illustrated will fill and overflow The goal is to implement a flow control method which will over a long time period reduce the average line rate of the link partner MAC to that of the user MAC 58 Method 1 Choose a FIFO nearly full to occupancy threshold 7 8 occupancy is used in this description but the choice of thr
140. s are made between the GMII interfaces between the two cores e If the GEMAC has been generated with the optional Management Interface the MDIO port can be connected up to that of the Ethernet 1000BASE X PCS PMA or SGMII core to access its embedded configuration and status registers See Using the Optional Management Interface e Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE X PCS PMA or SGMII core the entire GMII is synchronous to a single clock domain For this reason userclk2 is used as the 125 MHz reference clock for both cores and the transmitter and receiver logic of the GEMAC core now operate in the same clock domain This allows clock crossing constraints between the gtx c1k and gmii rx clk clock domains to be removed from the GEMAC UCE See Timespecs for Critical Logic within the Core Integration to Provide SGMII Functionality The connections between the two cores to provide SGMII functionality are identical to the connections required for 1000BASE X PCS and PMA using the device specific RocketlO transceiver The only difference is that the Ethernet 1000BASE X PCS PMA or SGMII core is generated with the SGMII option See Integration to Provide 1000BASE X PCS and PMA using a RocketIO Transceiver for a description of SGMII integration Ethernet Statistics Core The Ethernet Statistics core can be integrated in a single device with the 1 Gigabit Ethernet MAC core Using the Ethernet Statistics core let
141. s you e Count statistics based on the rx statistics vector and tx statistics vector outputs from the MAC e Select 32 bit or 64 bit counters e Specify which statistics are counted and have precise control of the conditions under which the counters are incremented e Read statistics optionally through the host interface of the GEMAC or independently of the MAC A description of the latest available IP Update containing the Ethernet Statistics core and instructions on obtaining the IP update can be found on the Ethernet Statistics product page Connecting the Ethernet Statistics Core to Provide Statistics Gathering The Ethernet Statistics core interfaces directly to the 1 Gigabit Ethernet MAC core The Ethernet Statistics core takes inthe tx statistics vector and rx statistics vector as inputs Statistics values gathered can then be read out through the Statistics core Management Interface that can be shared with the MAC Management Interface 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 119 UG144 April 24 2009 EZ XILINX DISCONTINUED PRODUCT Chapter 11 Interfacing to Other Cores Figure 11 5 illustrates connecting the Ethernet Statistics core to the MAC host_clk host_miim_sel host_req host addr 8 0 host addr 9 host wr data 31 0 host rd data 31 0 Figure 11 5 LogiCORE 1 Gigabit Ethernet MAC gtx clk ix statistics vector 31 0 tx statistics valid gmii rx clk rx statist
142. sections for details TIMEGRP IN RGMII OFFSET TIMEGRP IN RGMII OFFSET IN 1 ns VALID 2 ns BEFORE rgmii rxc TIMEGRP DDR RISING IN 3 ns VALID 2 ns BEFORE rgmii rxc TIMEGRP DDR FALLING Spartan 3 Spartan 3E Spartan 3A and Virtex 4 Devices The RGMII design uses a DCM on the receiver clock domain for all devices except Virtex 5 Phase shifting is then applied to the DCM to align the resultant clock so that it will correctly sample the 2 ns RGMII data valid window at the input flip flops The fixed phase shift is applied to the DCM using the following UCF syntax INST rgmii interface rgmii rxc dcm CLKOUT PHASE SHIFT FIXED INST rgmii interface rgmii rxc dcm PHASE SHIFT 40 The value of PHASE SHIFT is preconfigured in the example designs to meet the setup and hold constraints for the example RGMII pinout in the particular device The setup hold timing which is achieved after place and route is reported in the data sheet section of the TRCE report created by the implement script For customers fixing their own pinout the setup and hold figures reported in the TRCE report can be used to initially setup the approximate DCM phase shift Appendix C Calculating DCM Phase Shifting describes a more accurate method for fixing the phase shift by using hardware measurement of a unique PCB design Virtex 5 Devices The RGMII design uses IODELAY components on both the receiver and transmitter clock domains f
143. ses stored in the MAC address table The address table is only present when the MAC contains the optional Management Interface and the core was built with one or more address table entries Receiver Statistics Vector The statistics for the frame received are contained within the xx statistics vector The vector is driven synchronously by the receiver clock gmii rx c1lk following frame reception The bit field definition for the vector is defined in Table 5 2 All bit fields with the exception of byte valid are valid only when the rx statistics validis asserted This is illustrated in Figure 5 5 Byte valid is significant on every gmii rx clk cycle Caution The statistic vectors in this release have been made compatible with the Tri Mode Ethernet MAC core They are not backwards compatible with previous versions of the 1 Gigabit Ethernet MAC core see Table 5 3 for Receiver Statistic Vector conversion details gmii rx clk rx statistics valid N Figure 5 5 Receiver Statistics Vector Timing www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Receiving Inbound Frames EZ XILINX Table 5 2 Bit Definition for the Receiver Statistics Vector rx_statistics_vector bit s 27 Name Address Match Description If the optional Address Filter is included in the core this bit is asserted if the address of the incoming frame matches one of the
144. side the scope of this document 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 113 UG144 April 24 2009 XILINX Chapter 11 Interfacing to Other Cores DISCONTINUED PRODUCT Integration to Provide 1000BASE X PCS with TBI Figure 11 1 Figure 11 1 illustrates the connections and clock management logic required to interface the GEMAC core to the Ethernet 1000BASE X PCS PMA or SGMII core when used in 1000BASE X mode with the parallel TBI It depicts the following e Direct internal connections are made between the GMII interfaces of the two cores e Ifthe GEMAC has been built with the optional management logic the MDIO port can be connected up to that of the Ethernet 1000BASE X PCS PMA or SGMII core to access its embedded configuration and status registers See Using the Optional Management Interface e Dueto the embedded Receiver Elastic Buffer in the Ethernet 1000BASE X PCS PMA or SGMII core the entire GMII is synchronous to a single clock domain For this reason gtx_cl1k is used as the 125 MHz reference clock for both cores and the transmitter and receiver logic of the GEMAC core now operate in the same clock domain This allows clock crossing constraints between the gtx_clk and gmii rx clk clock domains to be removed from the GEMAC user constraints file UCF See Timespecs for Critical Logic within the Core IOB LOGIC IBUFG BUFG gtx_clk l gtx_clk_bufg 125 MHz component_na
145. slack 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 105 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 9 Constraining the Core Data Sheet report All values displayed in nanoseconds ns Setup Hold to clock rgmii_rxc Setup to Hold to Clock Source clk edge clk edge Internal Clock s Phase rgmii rx ctl 0 810 R 0 933 R rgmii rx clk bufg 0 000 3 214 F 4 959 F rgmii rx clk bufg 4 000 rgmii rxd 0 0 811 R 0 940 R rgmii rx clk bufg 0 000 3 213 F 4 966 F rgmii rx clk bufg 4 000 rgmii_rxd lt 1 gt 0 801 R 0 946 R rgmii rx clk bufg 0 000 3 223 F 4 972 F rgmii rx clk bufg 4 000 rgmii_rxd lt 2 gt 0 818 R 0 929 R rgmii rx clk bufg 0 000 3 206 F 4 955 F rgmii rx clk bufg 4 000 rgmii_rxd lt 3 gt 0 809 R 0 936 R rgmii rx clk bufg 0 000 3 215 F 4 962 F rgmii rx clk bufg 4 000 Virtex 5 Devices with Delayed Clock Setup and Hold results for the RGMII input bus can be found in the data sheet section of the Timing Report However depending on how the setup hold requirements have been met it may not be immediately obvious how the results relate to Figure 9 3 Following is an example for the RGMII report from a Virtex 5 device w
146. ss table you must first write the least significant 32 bits of the address into the Address Table Configuration Word 0 register You then write the most significant 16 bits together with the location in the table bits 17 16 to the Address Table Configuration Word1 register with bit 23 read not write set to 0 This is shown in Figure 8 3 Although it is shown in the figure there is no requirement for the two writes to be on adjacent cycles hostclk hostmiimsel i hostopcode 1 hostaddr 8 0 hostaddr 9 EW ae hostwrdata 31 0 oom BIT31 Pa 1 BITS15 0 ADDR 47 32 BITS17 16 LOCATION BIT23 0 Figure 8 3 Address Table Write Timing As shown in Figure 8 4 you must write to the Address Table Configuration register Word 1 with the location set to the desired table entry and bit 23 set to 1 to read from the address table On the next cycle the least significant word appears on the hostrddata bus One cycle afterwards the most significant 16 bits are output on the lower 16 bits of the bus 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 85 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 8 Configuration and Status hostclk hostmiimsel hostopcode 1 hostaddr 8 0 Ox18C hostaddr 9 hostwrdata 23 hostwrdata 17 16 hostrddata 31 0 81 0 Figure 8 4 Address Table Read Timing TT MDIO Interface Introduction to MDIO The MD
147. starting with a letter and gig_eth_mac_v8_5 based upon the following character set a z 0 9 and _ physical_interface One of the following keywords gmii gmii rgmii management interface One of the following keywords true true false address filter One of the following keywords true true false no of address table Integer in the range 0 4 4 entries Output Generation The output files generated from the CORE Generator tool are placed in the CORE Generator project directory The list of output files includes the following items e Netlist file for the core e Supporting CORE Generator files e Release notes and documentation e Subdirectories containing an HDL example design e Scripts to run the core through the back end tools and to simulate the core using either Mentor Graphics ModelSim Cadence IUS or Synopsys VCS simulators See the 1 Gigabit Ethernet MAC Getting Started Guide for more information about the CORE Generator output files and for details on the HDL example design 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 33 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 3 Generating the Core 34 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 4 Designing with the Core This chapter provides general guidelines for creating designs using the GEMAC core To work w
148. t addr 4 0 host wr data 15 0 maps into the data field of the MDIO frame when performing a write operation The data field of the MDIO frame maps into host rd data 15 0 when performing a read operation The GEMAC core signals the host that it is ready for an MDIO transaction by asserting host miim rdy A read or write transaction on the MDIO is initiated by a pulse on the host_req signal This pulse is ignored if the MDIO interface already has a transaction in progress The GEMAC core then deasserts the host miim rdy signal while the transaction across the MDIO is in progress When the transaction across the MDIO interface has been completed the host miim rdy signal is asserted by the GEMAC core if the transaction is a read the data is available on the host rd data 15 0 bus at this time 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 89 UG144 April 24 2009 XILINX DISCONTINUED PRODUCT Chapter 8 Configuration and Status Access without the Management Interface If the optional management interface is omitted from the core all of the relevant configuration settings described in Table 8 3 through Table 8 6 are brought out of the core as signals These signals are bundled into the configuration_vector 67 0 signal as described in Table 8 13 90 These signals may permanently set by connecting to logic 0 or 1 or may be changed by the user application at any time however with the exception of the rese
149. t and the flow control configuration signals any changes do not take effect until the current frame has completed transmission or reception The Clock heading in Table 8 13 denotes which clock domain the configuration signal is registered into before use by the core It is not necessary to drive the signal from this clock domain Table 8 13 Configuration Vector Bit Definition Configuration Bit s Register cross Clock Description reference 47 0 Receiver gmii rx clk Pause frame MAC Source Address 47 0 Configuration This address is used by the GEMAC core to Word 0 bits 31 0 match against the destination address of any and Receiver incoming flow control frames and as the Configuration source address for any outbound flow control Word 1 bits 15 0 frames The address is ordered such that the first byte transmitted or received is the least significant byte in the register for example a MAC address of AA BB CC DD EE FF will be stored in bite 47 0 as OXFFEEDDCCBBAA 48 n a n a This input is unused 49 Receiver gmii_rx_clk Receiver VLAN Enable When this bit is set to Configuration 1 VLAN tagged frames are accepted by the Word 1 bit 27 receiver 50 Receiver gmii rx clk Receiver Enable If set to 1 the receiver Configuration block is operational If set to 0 the block Word 1 bit 28 ignores activity on the physical interface RX port 51 Receiver gmii_rx_clk Receiver In band
150. t the DCM has lost lock a reset will be issued e A timeout counter is enabled when the DCM is in the loss of lock state If following the timeout period the DCM has not obtained lock another DCM reset will be issued This timeout counter will time a 1ms interval This timeout functionality is required for DCMs connected to Ethernet PHYs since the PHYs may source discontinuous clocks under certain network conditions for example when no ethernet cable is connected Spartan 3 Devices For Spartan 3 families the reset pulse is transferred into the DCM input clock gmii rx c1lk from Figure 7 2 Here it is extended to three DCM clock periods duration and routed to the reset input of the DCM Virtex 4 Devices For Virtex 4 families the generated reset from within the DCM reset module is further complicated Here the DCM reset pulse duration must be asserted for a minimum of 200 ms see the Virtex 4 Datasheet Consequently a 200 ms duration timer is also included in the DCM reset module to extend the reset pulse This reset signal is output from the DCM reset module and should be routed to the DCM reset input port Caution In the example designs for Virtex 4 families the 200ms reset pulse from the DCM reset module is NOT connected directly to the DCM this signal must be connected when implementing the core in real hardware For Virtex 4 FPGA example designs the reason why the 200ms input is not routed directly to the DCM is so th
151. ther of these checks fail the frame is marked as bad e A value in the length type field that is greater than or equal to decimal 46 but less than decimal 1536 a length interpretation is checked against the actual data length received e A value in the length type field that is less than decimal 46 is checked to see that the data field is padded to exactly 46 bytes so that the resultant frame is a minimum frame size of 64 bytes total in length Furthermore if padding is indicated the length type field is less than decimal 46 and client supplied FCS passing is disabled the length value in the length type field will be used to deassert rx_data_valid after the indicated number of data bytes so that the padding bytes are removed from the frame See Client Supplied FCS Passing Disabled When the length type error checking is disabled and the length type field has a length interpretation the MAC does not check the length value against the actual data length received See Receiver Configuration in Chapter 8 A frame containing only this error is marked as good However if the length type field is less than decimal 46 then the MAC will mark a frame as bad if it is not the minimum frame size of 64 bytes If padding is indicated and client supplied FCS passing is disabled then a length value in the length type field will not be used to deassert rx_data_valid Instead rx data validis deasserted before the start of the FCS fie
152. to Include 1000BASE X PCS with TBI 114 Figure 11 2 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS and PMA using a RocketIO Transceiver 0 00000 eh 115 Figure 11 3 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS and PMA using a RocketIO transceiver 00 00000 eee eee eee ee 117 Figure 11 4 1 Gigabit Ethernet MAC Extended to Include 1000BASE X PCS and PMA using the RocketIO transceiver 0 0 eee 118 Figure 11 5 Interfacing the Ethernet Statistics to the 1 Gigabit Ethernet MAC 120 Chapter 12 Implementing Your Design Appendix A Using the Client Side FIFO Figure A 1 Typical 10 Mbps 100 Mbps 1 Gbps Ethernet FIFO Implementation 127 Figure A 2 Frame Transfer across LocalLink Interface 00 130 Figure A 3 Frame Transfer with Flow Control 0 000000 130 Appendix B Core Verification Compliance and Interoperability Appendix C Calculating DCM Phase Shifting Appendix D Core Latency 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 11 UG144 April 24 2009 DISCONTINUED PRODUCT EZ XILINX 12 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Schedule of Tables Chapter 1 Introduction Chapter 2 Core Architecture Table 2 1 Transmitter Client Interface Signal Pins 0 0 cece eee 26 Table 2 2 Receive Client Interface Signa
153. transmitter clock source is therefore used for this receiver DCM This reset circuitry will generate an appropriate reset pulse for the receiver DCM of Figure 7 7 under the following conditions e The locked signal from the DCM is constantly monitored Following a high to low transition on this signal indicating that the DCM has lost lock a reset will be issued e A timeout counter is enabled when the DCM is in the loss of lock state If following the timeout period the DCM has not obtained lock another DCM reset will be issued This timeout counter will time a 1ms interval This timeout functionality is required for DCMs connected to Ethernet PHYs since the PHYs may source discontinuous clocks under certain network conditions for example when no ethernet cable is connected For Spartan 3 families the reset pulse is transferred into the DCM inputclock rgmii rxc from Figure 7 7 Here it is extended to three DCM clock periods duration and routed to the reset input of the DCM www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Implementing External RGMII XILINX IOB LOGIC BUFG rgmii_rxc lt 1 Gigabit Ethernet MAC Core t J gmii_rx_clk_bufg gmii_rx_clk lt IOB LOGIC rgmii_rxd w rgmii rxd ddr 0 IBUF rgmii rxd 0 gmii rxd reg 0 gmii_rxd 0 di lt rgmii_rxd_reg 4 rgmii_rxd_ddr 4 gmii_rxd 4 UI IM m
154. ultiple instantiations of the core using the optional RGMII gtx c1k may be shared between multiple cores as illustrated resulting in a common transmitter clock domain across the device As a general rule a common receiver clock domain is not possible Each core receives an independent receiver clock from the PHY attached to the other end of the RGMII as illustrated in Figure 10 4 This results in a separate receiver clock domain for each core Note Although not illustrated if the optional Management Interface is used host c1k can also be shared between cores 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 111 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 10 Clocking and Resetting DCM BUFG gtx_clk 1 Gigabit Ethernet MAC Core gtx_clk gmii_rx_clk lt rgmii rxc1 RGMII Tx Logic I gtx clk gmii rx clk rgmii_rxc2 RGMII Rx Logic Figure 10 4 Clock Management Logic with External RGMII Multiple Cores RGMII Tx Logic Reset Conditions Internally the core is divided up into clock reset domains that group together elements with common clock and reset signals The reset circuitry for one of these domains is illustrated in Figure 10 5 This circuit provides controllable skews on the reset nets within the design PRE i PRE B PRE i Q Q Q D D i f E PRE Figure 10 5 Reset Circuit for a Single Clock reset Domain reset Configuration reset
155. use the FPGA Editor to generate the required test file set instead of resorting to multiple PAR runs Performing the test on design files that differ only in phase shift setting prevents other variables from affecting the test results FPGA Editor operations can even be scripted further reducing the effort needed to perform this characterization www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Appendix D Core Latency Transmit Path Latency As measured from a data octet accepted on tx data 7 0 of the transmitter client side interface until that data octet appears on gmii txd 7 0 ofthe physical side GMII style interface the latency through the core in the transmit direction is 9 clock periods of gtx clk Receive Path Latency As measured from a data octet accepted on gmii rxd 7 0 of the physical side GMII style interface until that data octet appears on rx data 7 0 of the receiver client side interface the latency through the core in the receive direction is 9 clock periods of gmii rx clk 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 137 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Appendix D Core Latency 138 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009
156. verview of LocalLink Interface usussssesssee cece eens 130 Data EloW ss sc0k 0 os eR bk ERE EE GC RGORR GR iG KAGORR ue ER aoa was 130 Functional Operation igiic ives ceed casdds cad RE REO EVEN wes da ERROR E Vd n oed 131 Clock Requirements zcc csere 209 bees an ratu c eda e ER per rd DE RR 131 Receive FIFO isos ess ee baie ve xg x FEX WP ra prac elu E M EE 131 TransmitELlPO ic zd uere ex erri c Sends gaetedb aba 131 Expanding Maximum Frame Size sceeeeesseee eee 132 User Interface Data Width Conversion 0 cece cece eee ne 132 Appendix B Core Verification Compliance and Interoperability Verification by Simulation ssuussssssssss eee 133 Hardware Verification esses Rn 133 Appendix C Calculating DCM Phase Shifting DCM Phase Shifting sees en 135 Finding the Ideal Phase Shift 640 ees er the ER o Rape m ER Ree e eia 135 Appendix D Core Latency Transmit Path Latency idee guia reden ao dopo Hos Race gat acte Rol eie ani a 157 Receive Path Latency isssssssssssssssssss en 137 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Schedule of Figures Chapter 1 Introduction Chapter 2 Core Architecture Figur 2 1 Block Diagram escono em Ree Ee RU ERAN ee odes ka reda 21 Figure 2 2 Component Pinout for MAC with Optional Management Interface 23 Figure 2 3 Component Pinout fo
157. vided in the example design UCF are placeholders and work successfully in back annotated simulation of the example design 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 135 UG144 April 24 2009 XILINX 136 DISCONTINUED PRODUCT Appendix C Calculating DCM Phase Shifting Perform a complete sweep of phase shift settings during your initial system test Use only positive 0 to 255 phase shift settings and use a test range that covers a range of no less than 128 corresponding to a total 180 degrees of clock offset This does not imply that 128 phase shift values must be tested increments of 4 52 56 60 etc correspond to roughly one DCM tap and consequently provide an appropriate step size Additionally it is not necessary to characterize areas outside the working phase shift range At the edge of the operating phase shift range system behavior changes dramatically In eight phase shift settings or less the system can transition from no errors to exhibiting errors Checking the operational edge at a step size of two on more than one board refines the typical operational phase shift range Once the range is determined choose the average of the high and low working phase shift values as the default During the production test Xilinx recommends that you re examine the working range at corner case operating conditions to determine whether any final adjustments to the final phase shift setting are needed You can
158. was successfully received and that the frame should be analyzed by the client 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 39 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 5 Using the Client Side Data Path rx_data 7 0 Lo ps sa ur hk pata rx_data_valid J Ju rx good frame rx_bad_frame Figure 5 1 Normal Frame Reception Frame parameters destination address source address length type and optionally FCS are supplied on the data bus according to the timing diagram If the length type field in the frame has a length interpretation indicating that the inbound frame has been padded to meet the Ethernet minimum frame size the padding is not passed to the client in the data payload The exception to this is where FCS passing is enabled See Client Supplied FCS Passing When Client Supplied FCS passing is disabled rx_data_valid is equal to zero between frames for the duration of the padding field if present the FCS field carrier extension if present the interframe gap following the frame and the preamble field of the next frame When Client Supplied FCS passing is enabled rx_data_valid is equal to zero between frames for the duration of carrier extension if present the interframe gap and the preamble field of the following frame rx_good_frame rx_bad_frame timing Although the timing diagram Figure 5 1 shows the rx_good_frame signal asserted shortly after th
159. xample design provides pad locking on the GMI for several families This is a provided as a guideline only there are no specific I O location constraints for this core 96 www xilinx com 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 DISCONTINUED PRODUCT Required Constraints XILINX GMII Input Setup Hold Timing Figure 9 1 and Table 9 1 illustrate the setup and hold time window for the input GMII signals This is the worst case data valid window presented to the FPGA device pins P EE MN GMII RXD 7 0 GMII RX DV GMII RX ER lserue a thoro Figure 9 1 Input GMII Timing Observe that there is a 2 ns data valid window which is presented across the GMII input bus This must be correctly sampled by the FPGA devices Table 9 1 Input GMII Timing Symbol Min Max Units tegTUP 2 00 ns tHOLD 0 00 x ns The following constraints are provided in the UCF for GMII Example Designs These constraints invoke the tools to analyze the setup hold requirements though if failing the tools are NOT capable of fixing them meeting these constraints is a manual process see the following family specific sections for details INST gmii rxd TNM IN GMII INST gmii rx er TNM IN GMII INST gmii rx dv TNM IN GMII TIMEGRP IN GMII OFFSET IN 2 1 ns VALID 2 2 ns BEFORE gmii rx clk The constraints defined in the preceding lines have a built in 10
160. y the transmission of the next frame until the requested number of idle cycles has elapsed The number of idle cycles is controlled by the value on the tx ifg delay portseen at the start of frame transmission on the client interface Figure 5 10 shows the MAC operating in this mode Reducing the interframe gap to below the IEEE 802 3 2005 minimum of 12 idles is supported but the MAC will transmit an absolute minimum of 4 idles If the Ethernet Statistics core is used with the MAC then accuracy cannot be guaranteed if the interframe gap adjustment is set to less than 12 idles However the tx statistic vector and rx statistic vector values will always remain correct 1 Gigabit Ethernet MAC v8 5 User Guide www xilinx com 49 UG144 April 24 2009 DISCONTINUED PRODUCT XILINX Chapter 5 Using the Client Side Data Path tx_data 7 0 DA SA DA tx_data_valid tx_ack Gap l gt leen l IFG ADJUST VALUE Next IFG ADJUST VALUE tx_ifg_delay e 13 Idles inserted between the end of frame and the preamble field of the following frame Figure 5 10 Inter Frame Gap Adjustment Transmitter Statistics Vector The statistics for the transmitted frame are contained within the tx statistic vector The vector is driven synchronously by the transmitter clock gtx c1k following frame transmission The bit field definition for the vector is defined in Table 5 4 All bit fields with the excepti

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