Transcend Information TS2GSD150 User's Manual
Contents
1. refer to Figure 4 This type of bus transactions transfer their information directly within the command or response structure In addition some operations have a data token Data transfers to from the SD Memory Card are done in blocks Data blocks always succeeded by CRC bits Single and multiple block operations are defined Note that the Multiple Block operation mode is better for faster write operation A multiple block transmission is terminated when a stop command follows on the CMD line Data transfer can be configured by the host to use single or multiple data lines Transcend Information Inc 3 TS2GSD150 2GB 150x Secure Digital Card from from data from card stop command host card to host stops data transfer to card to host CMO command response ae eee een cess command data block cref jdata block data block Figure 5 Multiple Block read operation The block write operation uses a simple busy signaling of the write operation duration on the DATO data line see Figure 6 regardless of the number of data lines used for transferring the data erc ok response from from data from and busy stop command host card host from stops data trans to card to host to card card fer to host response f a fn response BAT sco oS cos eto ae data block data block busy P CMD Figure 6 Multiple Block write operation Command tokens have the following coding scheme transmitter bit2. 1 host command Command content command and address information or parameter protected by 7 bit CRC checksum start bit pane bit anon A always 1 0 1 conrenr ere total length 48 bits Figure 7 Command token format Each command token is preceded by a start bit 0 and succeeded by an end bit 1 The total length is 48 bits Each token is protected by CRC bits so that transmission errors can be detected and the operation may be repeated Response tokens have four coding schemes depending on their content The token length is either 48 or 136 bits Transcend Information Inc 4 TS2GSD1 50 2GB 150x Secure Digital Card The CRC protection algorithm for block data is a 16 bit CCITT polynomial transmitter bit O card response Response content mirrored command and status infor mation R1 response OCR register R3 response or start bit RCA R6 protected by a 7bit CRC checksum end bit always 0 always 1 mmm ole eon 9 total length 48 bits end bit always 1 o oj conTent ciDorcso CRG 1 total length 136 bits Figure 8 Response token format In the CMD line the MSB bit is transmitted first the LSB bit is the last When the wide bus option is used the data is transferred 4 bits at a time refer to Figure 10 Start and end bits as well as the CRC bits are transmitted for every one of the DAT lines CRC bits are calculated and checked for every DAT line indiv
3. CMD27 CSD bit Name Field Note 127 126 CSD structure CSD_STRUCTURE v1 0 125 120 Reserved 119 112 Data read access time 1 TAAC 80 ms 111 104 Data read access time 2 NSAC 25 5k clocks 103 96 Max bus clock freq TRAN_SPEED 25 MHz 95 84 Card command classes CCC 1 83 80 Max read data block length READ_BL_LEN 512 bytes 79 Partial block read allowed READ_BL_PARTIAL Support 78 Write block misalignment WRITE_BLK_MISALIGN Support 77 Read block misalignment READ_BLK_MISALIGN Support 76 DSR implemented DSR_IMP Not support 75 74 Reserved 73 62 Device size C_SIZE 2 61 59 Max R_curr voo min VDD_R_CURR_MIN 35 mA 58 56 Max R_curr vop max VDD_R_CURR MAX 45 mA 55 53 Max W_curr voo min VDD_W_CURR MIN 35 mA 52 50 Max W_curr vop max VDD_W_CURR_MAX 45 mA 49 47 Device size multiplier C_SIZE_MULT 2 46 Erase single block enable ERASE_BLK_EN Not allowed 45 39 Erase sector size SECTOR_SIZE 3 38 32 Write protect group size WP_GRP SIZE 4 31 Write protect group enable WP_GRP_ENABLE Support 30 29 Reserved 28 26 Write speed factor R2W_FACTOR 25 22 Max write data block length
4. fpp lt 20 MHz Pull up resistance inside card pin1 Rpat3 10 90 kQ May be used for card detection Note that the total capacitance of CMD and DAT lines will be consist of Chost Cgus and one Ccarp only since they are connected separately to the SD Memory Card host Parameter Symbol Min Max Unit Remark Pull up resistance Remo RpaT 10 100 kQ To prevent bus floating Bus signal line capacitance CL 250 pF fpp lt 5 MHz 21 cards Transcend Information Inc 11 TS2GSD1 50 2GB 150x Secure Digital Card e Bus Signal Levels As the bus can be supplied with a variable supply voltage all signal levels are related to the supply voltage V input output high level high level undefined input low level output low level To meet the requirements of the JEDEC specification JESD8 1A the card input and output voltages shall be within the following specified ranges for any Vpp of the allowed voltage range Parameter Symbol Min Max Unit Remark Output HIGH voltage Vou 0 75 Vop V lo 100 UA Vpp min Output LOW voltage VoL 0 125 Vpp V lor 100 UA Vpp min Input HIGH voltage Vin 0 625 Vpp Vop 0 3 V Input LOW voltage Vit Vss 0 3 0 25 Vop V Transcend Information Inc 12 TS2GSD1 50 2GB 150x Secure Digital Card Bus Timing Default lS Shaded areas are not valid Figure 47 Timing diagram data input output reference
5. ground O PP_ Data Out 2GB 150x Secure Digital Card TS2GSD150 Architecture DATO DATI interface driver 3 CD DAT DAT2 OCR 31 0 CID 127 0 U01 99 eP UO J MOd controller reset Card interface E E z g be Z RCAJ15 0 DSR 185 0 CSD 127 0 SCR 63 0 deboch Transcend Information Inc TS2GSD1 50 2GB 150x Secure Digital Card Bus Protocol SD bus Communication over the SD bus is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit e Command a command is a token which starts an operation A command is sent from the host either to a single card addressed command or to all connected cards broadcast command A command is transferred serially on the CMD line e Response a response is a token which is sent from an addressed card or synchronously from all connected cards to the host as an answer to a previously received command A response is transferred serially on the CMD line e Data data can be transferred from the card to the host or vice versa Data is transferred via the data lines from from from host host card to card s to card to host CMD command command response Figure 4 no response and no data operations Card addressing is implemented using a session address assigned to the card during the initializa tion phase The basic transaction on the SD bus is the command response transaction
6. 4 data block f Data Resp busy weet eee eee Data Resp data start Data response and token Husy fro data stop token host to card DataOut response block write operation multiple block write operation data stop operation Figure 13 Write operation After a data block has been received the card will respond with a data response token If the data block has been received without errors it will be programmed As long as the card is busy programming a continuous stream of busy tokens will be sent to the host effectively holding the DataOut line low Transcend Information Inc 7 TS2GSD1 50 2GB 150x Secure Digital Card Card Registers 1 OCR Register The 32 bit operation conditions register stores the VDD voltage profile of the card In addition this register includes a status information bit This status bit is set if the card power up procedure has been finished The OCR register shall be implemented by all cards The supported voltage range is coded as shown in the following table As long as the card is busy the corresponding bit 31 is set to LOW C eo reena ooo CO m vw O e 1 OCR bit 31 is set to LOW if the card has not finished the power up routine 2 Card Identification Register CID The Card IDentification CID register is 128 bits wide It contains the card identification information used during the card identificat
7. TS2GSD150 2GB 150x Secure Digital Card Description Features TS2GSD150 is a 2GB Secure Digital Card of 150X e ROHS compliant product ultra high performance It is specifically designed to e Operating Voltage 2 7 3 6V meet the security capacity performance and small e Operating Temperature 25 85 C form factor requirements in newly emerging audio e Insertion removal durability 10 000 cycles and video consumer electronic devices Based on e Fully compatible with SD card spec v1 1 dual channel technology and high quality SLC Single e Mechanical Write Protection Switch Level Cell NAND flash chip TS2GSD150 is the ideal companion to bring out the most from your high performance electronic devices Placement Transcend 4 aD pA Front Back Pin Definition SD Mode Pin No Hrs Re Description Card Detect Data Line Bit3 2 cmp PP Command Response Supply voltage ground KISMEN Supply voltage 5 ck cox 6 fve s Supply voltage ground Data Line Bit0 8 patt voip Data Line Bit1 9 pate vorp Data Line Bit2 Iranscena inrormation Inc l Support clock frequencies 0 50MHz Support different Bus width x1 x4 Support SD command class 0 2 4 5 7 8 Supports Copy Protection for Recorded Media CPRM for music and other commercial media Form Factor 24mm x 32mm x 2 1mm SPI Mode Name CS chip Select neg true DI Data In S Supply voltage Clock a Suy voltage
8. WRITE_BL_LEN 512 bytes 21 Partial block write allowed WRITE_BL_PARTIAL Support 20 16 Reserved 15 3 3 3 3 3 1 7 7 1 2 3 4 1 5 1 File format group Transcend Information Inc FILE_FORMAT_GRP HD like FAT TS2GSD1 50 2GB 150x Secure Digital Card Copy flag COPY Not copied Permanent write protection PERM_WRITE_PROTECT Not protected Temporary write protection TMP_WRITE_PROTECT Not protected File format FILE_ FORMAT HD like FAT ECC code ECC None CRC Not used always 1 1 Support command class 0 2 4 5 6 7 8 Include Basic Block read write Erase Write protection application command and Lock card Not support 1 3 Include Stream read write 2 4 This field is not a constant value The value will be changed by different flash memory 6 Extended CSD Register EXT_CSD The Extended CSD register defines the card properties and selected modes It is 512 bytes long The most significant 320 bytes are the Properties segment which defines the card capabilities and cannot be modified by the host The lower 192 bytes are the Modes segment which defines the configuration the card is working in These modes can be changed by the host by means of the SWITCH command 7 SD card Configuration Register SCR The CSD register is another configuration register in SD card SCR provides on SD card s special features that were con
9. d to clock Default Parameter Symbol Min Max Unit Remark Clock CLK All values are referred to min Vi and max V1 Clock frequency Data Transfer Mode fpp 0 25 MHz _ C lt 100 pF 7 cards Clock frequency Identification Mode fop 0 400 KHz C lt 250 pF 21 cards The low freq is required for MultiMediaCard compatibility Clock low time two 10 ns C lt 100 pF 7 cards 50 ns C lt 250 pF 21 cards Clock high time twh 10 ns C lt 100 pF 7 cards 50 ns C lt 250 pF 21 cards Clock rise time tty 10 ns C lt 100 pF 7 cards Transcend Information Inc 13 TS2GSD1 50 2GB 150x Secure Digital Card 50 ns C lt 250 pF 21 cards Clock fall time true 10 ns C lt 100 pF 7 cards 50 ns C lt 250 pF 21 cards Inputs CMD DAT referenced to CLK Input set up time tisu 5 ns C lt 25 pF 1 cards Input hold time tin 5 ns C lt 25 pF 1 cards Outputs CMD DAT referenced to CLK Output Delay time during Data Transfer Mode topLy 0 14 ns C lt 25 pF 1 cards Output Delay time during Identification Mode topLy 0 50 ns C lt 25 pF 1 cards Transcend Information Inc 14 TS2GSD1 50 2GB 150x Secure Digital Card e Bus Timing High Speed Mode or rf N fp Db To S i ENE Vin Clock i Vi TRL tre tsu tH Vin Input Vit ai O
10. figured into the given card The size of SCR is 64 bit For SD card only SCR is a read only register sere uan vane Fes OO S vee Note resco Scr anaue fecr STRUCTURE oop vo 150556 4 SD cara spee verson s0_sesc oos vo Data status after erase DATA_STAT_AFTER_ERASE wra 16 Reema e O S Fito ee Ree o o E Transcend Information Inc 10 TS2GSD1 50 2GB 150x Secure Digital Card AC DC Character e General Parameter Symbol Min Max Unit Remark Peak voltage on all lines 0 3 VDD 0 3 V All Inputs Input Leakage Current 10 10 pA All Outputs Output Leakage Current 10 10 HA Power Supply Voltage Parameter Symbol Min Max Unit Remark Supply voltage Vpbp 2 0 3 6 V CMDO 15 55 ACMD41 commands Supply voltage specified in OCR register 2 7 3 6 V Except CMDO 15 55 ACMD41 commands Supply voltage differentials Vss1 Vss2 0 3 0 3 V Power up time 250 ms From Ov to Vpp Min Bus Signal Line Load The total capacitance C the CLK line of the SD Memory Card bus is the sum of the bus master capacitance Cyost the bus capacitance Cgus itself and the capacitance Ccarp of each card connected to this line C Chost Cgus N Ccarp Parameter Symbol Min Max Unit Remark Bus signal line capacitance CL 100 pF fpp lt 20 MHz 7 cards Single card capacitance Ccarp 10 pF Maximum signal line inductance 16 nH
11. idually The CRC status response and Busy indica tion will be sent by the card to the host on DATO only DAT1 DAT3 during that period are don t care Transcend Information Inc 5 TS2GSD1 50 2GB 150x Secure Digital Card SPI bus While the SD channel is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit the SPI channel is byte oriented Every command or data block is built of 8 bit bytes and is byte aligned to the CS signal i e the length is a multiple of 8 clock cycles Similar to the SD protocol the SPI messages consist of command response and data block tokens All communication between host and cards is controlled by the host master The host starts every bus transaction by asserting the CS signal low The response behavior in the SPI mode differs from the SD mode in the following three aspects e The selected card always responds to the command e Two new 8 amp 16 bit response structure is used e When the card encounters a data retrieval problem it will respond with an error response which replaces the expected data block rather than by a time out as in the SD mode In addition to the command response every data block sent to the card during write operations will be responded with a special data response token Data Read Single and multiple block read commands are supported in SPI mode However in order to comply with the SPI industry standard only two u
12. ion phase Every individual flash or I O card shall have an unique identification number The structure of the CID register is defined in the following table a e a A a T T O 8 ___ProductName PNM sss 8 Product Revision PRV____ 3 Driver Stage Register DSR The 16 bit driver stage register is optionally used to improve the bus performance for extended operating conditions The CSD register carries the information about the DSR register usage This register is not implemented Transcend Information Inc 8 TS2GSD150 2GB 150x Secure Digital Card 4 Relative Card Address Register RCA The writable 16 bit relative card address register carries the card address assigned by the host during the card identification This address is used for the addressed host card communication after the card identification procedure The default value of the RCA register is 0x0001 The value 0x0000 is reserved to set all cards into the Stand by State with CMD7 In SD mode the value of this register is generated by random number generator inside the card Please reference to SD specification for detail information 5 Card Specific Data Register CSD The Card Specific Data register provides information on how to access the card contents The CSD defines the data format error correction type maximum data access time data transfer speed whether the DSR register can be used etc The programmable part of the register can be changed by
13. ities surface smoothness lt Shape and form 0 1 mm cm within contour no cracks no pollution fat oil dust etc Minimum moving force of WP witch 40gf WP Switch cycles minimum 1000 Cycles Slide force 0 4N to 5N Above technical information is based on SD1 1 standard specification and tested to be reliable However Transcend makes no warranty either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 17
14. nidirectional signal are used Upon reception of a valid read command the card will respond with a response token followed by a data token of the length defined in a previous SET_BLOCKLEN CMD16 command A multiple block read operation is terminated similar to the SD protocol with the STOP_TRANSMISSION command data from card to host Figure 11 Read operation A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial X X X 1 In case of a data retrieval error the card will not transmit any data Instead a special data error token will be sent to the host Figure 12 shows a data read operation which terminated with an error token rather than a data block Transcend Information Inc 6 TS2GSD1 50 2GB 150x Secure Digital Card from data eror token Next card from card to host Comman to host Aiaia el ee aie Sie ep gs oe rt eres i r A T AA command Gaig eror lt lt ens es een es erence Figure 12 Read operation data error e Data Write Single and multiple block write operations are supported in SPI mode Upon reception of a valid write command the card will respond with a response token and will wait for a data block to be sent from the host CRC suffix block length and start address restrictions are identical to the read operation see Figure 13 data from trom from t host card host to card to host to card Datalir command gt data block f
15. utput VoL tony E toH Shaded areas are not valid Figure 48 Timing diagram data input output referenced to clock High Speed Parameter Symbol Min Max Unit Remark Clock CLK All values are referred to min Vin and max V1 Clock frequency Data Transfer Mode fpp 0 50 MHz Clock low time two 7 ns Clock high time twH 7 ns Clock rise time troy 3 ns Clock fall time true 3 ns Inputs CMD DAT referenced to CLK Input set up time tisu 6 ns Input hold time ty 2 ns Outputs CMD DAT referenced to CLK Transcend Information Inc 15 TS2GSD150 2GB 150x Secure Digital Card Output Delay time during Data Transfer Mode topLy 14 ns Output Hold time tou 2 5 ns Total System capacitance for each line CL 40 pF Transcend Information Inc 16 TS2GSD1 50 2GB 150x Secure Digital Card Reliability and Durability Temperature Operation 25 C 85 C Target spec Storage 40 C 168h 85 C 500h Junction temperature max 95 C Moisture and corrosion Operation 25 C 95 rel humidity Storage 40 C 93 rel hum 500h Salt Water Spray 3 NaCl 35C 24h acc MIL STD Method 1009 Durability 10 000 mating cycles Bending 10N Torque 0 15N m or 2 5 deg Drop test 1 5m free fall UV light exposure UV 254nm 15Ws cm according to ISO 7816 1 Visual inspection No warp page no mold skin complete form no cav
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