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Texas Instruments TMS380C26 User's Manual

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1. Figure 23 Ethernet Timing of RCV Signals Start Of Frame TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 57 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals end of frame NO PARAMETER UNIT Setup time of CRS low before RXC no longer low to determine if last data bit seen on CRSSET previous RXC no longer low see Note 18 321 CRSHLD Hold time of CRS low after RXC no longer low to determine if last data bit seen on previous RXC longer low XTRCYC Number of extra RXC clock cycles after last data bit CRS pin is low see Note 18 NOTE 18 TMS380C26 will operate correctly even with no extra RXC clock cycles providing that CRS does not remain asserted longer than 2 us see timing spec Providing no extra clocks affect receive startup timing see timing spec SAMDLY dis NF NO Xo N Z NZ NZ NZ 320 e gt 4 5 3 KKK KKK KK KKK ene 322 RXD X X Last Data Bit Figure 24 Ethernet Timing of RCV Signals End Of Frame TEXAS 49 INSTRUMENTS 58 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals
2. TWAIT T4 TX 1 2 T3 T4 1 91 62 53 54 S 56 S7 2222da 9 i i 239 gt see Note k 209 gt 210 223R gt 5005 id 239 gt i SLDS 218 9 id 209 gt gt 217 216 gt lt 4 217 4 215 SXAL N 216 e M 218 gt pP e 216 215 4 d 212 212 4 233 206 205 233 4 233 lt gt 214 7 207a SADLO SADH7 SPH SPL Extended Address lt 247t p 207b SDTACK gt 208a see Notes and C 208b SDDIR 237R _ 225R SDBEN see Note A tif parameter 208a is not met then valid data must be present before SDTACK goes low NOTES A Motorola style bus slaves hold SDTACK active until the bus master deasserts SAS B All Vgs pins should be routed to minimize inductance to system ground C Onread cycle read strobe remains active until the internal sample of incoming data is completed Input data may be removed when either the read strobe or SDBEN becomes no longer active Figure 41 68xxx Mode DMA Read Timing 661 HOUVIN Q3SIA3H 666 TIHd V VO LOSMdS dOSS390ddININO9 MYOMLAN 922086511 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode DMA write timing EON mn
3. I MM Setup of asynchronous input SDTACK before SBCLK no longer high to guarantee recognition on this cycle 208b Hold of asynchronous input SDTACK after SBCLK low to guarantee recognition on this cycle 8 Pulse duration SAS SUDS and SLDS high w SCKL zs Delay rom SBGLKiowinT2cyde to SAD 216 Pulse curation SALE andSxALNgh zre Dey snesen S n Hod or SALE or SXAL ater SUBS ara SAS Ez Delay fom SECLK SXAL ewin he or SALE ow nte Tias EEEE 7 eT Detay SECLK low in T4 cycle 1o 5005 5105 and os hoe 25 m 25 rom Seck own Taye 0S8 2297 of SAD afer seck gt o Pulse duration SAS SUDS and SLDS 2tc w SCKH Setup of data valid before SDTACK low if parameter 208a not met T This specification has been characterized to meet stated value NOTE 25 While the system interface DMA controls are active i e SOWN is asserted the SCS input is disabled TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 83 77251 1443 78 10077 SVXAL 391440 1804 SIN3A THISN SYEL PARAMETER MEASUREMENT INFORMATION
4. Delay from SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately 276 4000 ns following access to the SIF 2791 Delay from SIACK high to SDTACK high impedance Delay from SDBEN low to SDTACK low in a read cycle Delay from SIACK low to SDBEN low see TMS380 Second Generation Token Ring User s Guide SPWUODO5 subsection 3 4 1 1 1 provided the previous cycle completed 283R Delay from SIACK high to SDBEN high see Note 21 Pulse duration SIACK high between DIO accesses see Note 21 t This specification is provided as an aid to board design t This specification has been characterized to meet stated value is the later of SRD and SRD or SCS low that indicates the start of the cycle 2 NOTE 21 The inactive chip select is SIACK DIO read and DIO write cycles and SCS is the inactive chip select in interrupt acknowledge cycles TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 79 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS SRSX 5 50 SRS1 Only SCS needs to be Inactive SBHE All Others are Don t Care W 267 SIACK N N 272a lt 286 gt SRNW 1 273a SLDS N N lt 286 a_l SDDIR High 282R gt 4 218 283R SDBEN N 276 gt 275 H 282a SD
5. 165 gt Figure 19 Token Ring Ring Interface Timing TEXAS 49 INSTRUMENTS 54 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION token ring transmitter timing see Figure 20 NO PARAMETER MIN TYP MAX UNIT 159 Delay from DRVR rising edge 1 8 V to DRVR falling edge 1 0 V or DRVR falling edge 1 0 V to 42 DRVR rising edge 1 8 V B 1601 Delay from PXTALIN falling edge 1 0 V to DRVR rising edge 1 8 V seeNote15 1611 Delay from RCLK or PXTALIN falling edge 1 0 V to DRVR falling edge 1 0 V seeNote15 162t Delay from RCLK or PXTALIN falling edge 1 0 V to DRVR falling edge 1 0 V see Note 15 1631 Delay RCLK or PXTALIN falling edge 1 0 V to DRVR rising edge 1 8 V seeNote15 t When in active monitor mode the clock source is PXTALIN otherwise the clock source is either RCLK or PXTALIN NOTE 15 This parameter is not tested to a minimum or a maximum but is measured and used as a component required for parameter 164 2 60 RCLK or PXTALIN 1 50 0 60 2 40 DRVR _ 1 50 0 60 4 9 160 2 40 DRVR BS Cm 1 50 0 60 163 Figure 20 Skew and Asymmetry from RCLK or PXTALIN to DRVR and DRVR TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 55 77251 1443
6. Figure 44 68xxx Mode Bus Release and Error Timing TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 89 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION normal completion with delayed startt Ti T W or 2 T3 T4 TH Ti SBCEK Xy N Z N Wo SDTACK LON SBERR REE SHALT rerun cycle with delayed startt Ti T2 T3 TH THe Ti 2 SDTAGK m SBERR N SHALT N SOWN N T Only the relative placement of the edges to SBCLK falling edge is shown Actual signal edge placement may vary from waveforms shown Figure 45 68xxx Bus Halt and Retry Cycle Waveforms TEXAS 49 INSTRUMENTS 90 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 MECHANICAL DATA JEDEC plastic leaded quad flat package PQ suffix Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within an electrically nonconductive plastic compound The compound withstands soldering temperatures with no deformation and circuit performance characteristics remain stable when the devices are operated in high humidity conditions The packages are intended for surface mounting on solder lands on 0 635 0 025 centers Leads require no additional cleaning or processing when
7. 5380 26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of clock signals NO PARAMETER UNIT CLKPER Cycle time of TXC 95 1000 k 300 gt Figure 21 Ethernet Timing Of Clock Signals ethernet timing of XMIT signals t Delay time from TXC high to TXD valid and XDVLD palay time from TXC high to TXEN high 305 24V TXD 0 45 V 306 306 24V TXEN 0 45 V Figure 22 Ethernet Timing of XMIT Signals TEXAS 49 INSTRUMENTS 56 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals start of frame NO 213 SAMDLY Delay of CRS internally recognized o data sample see Notes 16514117 NOTES 16 For valid frame synchronization one of the following data sequences must be received Any other pattern will delay frame synchronization until after the next CRS rising edge a On 10 11 where n is an integer and n is greater than or equal to 3 b 10n 10 11 17 If a previous frame or frame fragment completed without extra clock cycles XTRCVC 0 then SAMDLY 2 clock cycles 313 gt 314 4 RXC an 111 k 315
8. 208a SDTACK see Notes A and B 208b gt 225W SDDIR 225WH 237W lt jp SDBEN NOTES A All pins should be routed to minimize inductance to system ground B Onread cycle read strobe remains active until the internal sample of incoming data is completed Input data may be removed when either the read strobe or SDBEN becomes no longer active Figure 42 68xxx Mode DMA Write Timing 922086611 661 Q3SIA3H 666 1 4 0105 45 dOSS390ddININO9 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus arbitration timing SIF returns control 2201 Delay from SBCLK low cycle to SAD SPL SPH 5005 and SLDS high impedance bus release 223bt Delay from SBCLK low in 11 cycle to SBHE SRNW high impedance 2401 Setup of SUDS SLDS SANW and SAS contol signal tign impedance SOWN ro tonger ow 5 t This specification has been characterized to meet stated value TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 87 77251 1443 88 10077 SVXAL 1804 SIN3NA THISN SVAL SIF Inputs SBGR SDTACK SIF Outputs SBRQ see Note A SAS SUDS SLDS SRNW SADHO SADHT SADLO SADLT SPH SPL SDDIR SOWN NOTE A In 80x8x mode the system interface deasserts SHRQ on the ris
9. Address In Address In 98 9 99 4 0 90 V V N N N N N N N N NX X XX X X X X X X X X X X X X X X X X X X X XXY MDDIR ARR RAN DA DAA XXX 95 lt 004000 s 5 MACS A Figure 16 Memory Bus Timing External Bus Master Write To TMS380C26 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 51 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing DRAM refresh timing tM is the cycle time of one eighth of a local memory cycle 31 25 ns minimum NO PARAMETER MIN MAX UNIT Setup time of row address on MADLO MADL7 MAXPH and MAXPL before MRAS no longer 15 high 1 5ty 11 5 ns Hold time of row address on MADLO MADL7 MAXPH and MAXPL after MRAS no longer high tM 6 5 Pulse duration of MRAS low 4 51 9 Hold time of MREF high after MCAS high 52 O MADLO MADL7 Refresh Address 46 4 lt 15 19 gt 4 18 MRAS N 73a gt je 73b gt IN MREF Figure 17 Memory Bus Timing DRAM Refresh Cycle TEXAS 49 INSTRUMENTS 52 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION XMATCH and XFAIL timing tM is t
10. POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Terminal Functions wwe wo l UT i 14 EXTINTO EXTINT1 EXTINT2 EXTINT3 Bootstrap The value on this pin is loaded into the BOOT bit of the SIFACL register at reset i e when the SRESET pin is asserted or the ARESET bit in the SIFACL register is set to form a default value This bit indicates whether chapters 0 and 31 of the memory map are RAM or ROM If these chapters are RAM then the TMS380C26 is denied access to the local memory bus until the CPHALT bit in the SIFACL register is cleared Chapters 0 and 31 of local memory are RAM based see Note 1 Chapters 0 and 31 of local memory are ROM based Clock Divider Select This pin must be pulled high Indicates 64 MHz OSCIN see Note 3 Reserved Local memory Address Data and Status Bus high byte For the first quarter of the local memory cycle these bus lines carry address bits AX4 and 0 to for the second quarter they carry status bits and for the third and fourth quarters they carry data bits 0 to 7 The most significant bitis MADHO and the least significant bit is MADH7 Memory Cycle 1Q 2Q 3Q 4Q 4 0 6 Status D0 D7 D0 D7 Local Memory Address Data and Status Bus low byte For the first quarter of the local memory cycle these bus lines carry address bits A7 to A14 for the second quarter they car
11. TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION Address s MROMEN Enable k 32 Data Parity MAXPH MAXPL MADLO MADL7 4 33 gt KM 36 lt 37 gt _ 4 35 gt MRAS lt 38 P 39 40 gt 5 43 45 48 41 4 46 42 gt 47 gt 44 gt 4 48 4 51 50 4 4 k 52a gt MBIAEN N 4 gt 49 gt 51 48 4 52 gt MBEN 50 NES 53 IN gt 54 gt MDDIR N m Figure 9 Memory Bus Timing Read Cycle TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 41 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing write cycle tM is the cycle time of one eighth of a local memory cycle 31 25 ns minimum wA Setup time of MW iow MCAS orgeriow e6 Setup time of adress valid on MAX2 and MROMEN before MWnolongeri m Hod tne rom MEAS low 1o Wino ongeriow TEXAS 49 INSTRUMENTS 42 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFOR
12. TMS380C26 has a bus interface to the host system a bus interface to local memory and an interface to the physical layer circuitry As a rule of thumb in the pin nomenclature and descriptions that follow pin names starting with the letter S attach to the host system bus and pin names starting with the letter M attach to the local memory bus Active low signals have names with overbars e g SCS SADHO System Memory MADHO Interface Interface SADH7 SIP M MADH7 SADL0 MADLO DIO Control DRAM Refresh SADL7 Bus Control Local Bus MADL7 DMA Control Arbitrator SPH Local Bus MRAS SPL Control MCAS SBRLS Local MAXPH SINTR SIRQ Parity Check MAXPL SDDIR Generator MW SDBEN MOE SALE MDDIR SXAL MAL SOWN MAXO SIACK MAX2 SBCLK MRESET SRD SUDS MROMEN SWR SLDS MBEN SRDY SDTACK MBRQ MBGR SHLDA SBGR MACS SBHE SRNW MBIAEN SRAS SAS MREF S8 SHALT SRESET OSCIN SRSO Clock OSCOUT SRS1 Generator MBCLK1 SRS2 SBERR CG MBELK2 Scs SYNCIN SRSX CLKDIV SHRQ SBRQ SBBSY Adapter EXTINTO BTSTRP Support PRTYEN Function NSELOUTO ASF EXTINT3 NSELOUT1 TESTO Interrupts Communications Test Function Processor TEST5 XMATCH XFAIL RCLK RXC Protocol Handler PH FRAQ TXD REDY CRS for Token Ring and NSRT LPBK WFLT COLL Ethernet Interface WRAP TXEN RCVR RXD DRVR PXTALIN TXC DRVR Figure 2 TMS380C26 COMMprocessor Block Diagram TEXAS 49 INSTRUMENTS
13. SBHE 575777 757 216 3 9 PARAMETER MEASUREMENT INFORMATION TX T1 T2 HI Z 212 TWA V IT T3 T4 T1 227R lt 223R lt 231 gt 215 218 217 46 17 217 4 gt lt 226 216 215 gt 216a SALE N N 212 233 gt 207a 205 4 229 212 4 218 233 206 SADHO SADHT7 SADLO SADLT7 SPH SPL see Note C SDBEN see Note A SDDIR Extended Address Low tit parameter 208A is not met then valid data must be present before SRDY goes low NOTES A Motorola style bus slaves hold SDTACK active until the bus master deasserts SAS 2471 208 2080 gt B In 8 bit 80x8x mode SBHE SRNW is a don t care input during DIO and an inactive high output during DMA C In 8 bit 80x8x mode the most significant byte of the address is maintained on SADH for T2 T3 and T4 The address is maintained according to parameter 21 i e held after T4 high Figure 33 80x8x Mode DMA Read Timing Comme 207b 661 Q3SIA3H 666 1 TIHd V VO LOSMdS dOSS390ddININO9 MYOMLAN 922086611 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT I
14. TEXAS 67 77251 1443 89 10077 SVXAL 1 391440 1804 SIN3A THISN dne SVX4L PARAMETER MEASUREMENT INFORMATION User Master Bus Exchange SIF Master i 1 2 TX SIF Inputs n D f 208a 4 1 A SBBSY SHLDA lt gt le 208b SIF Outputs 230 SHRQ I4 212 s Address Valid SPH SPL lt 224c p Write SDDIR Read 4 224 gt SOWN see Note A NOTE A While the system interface DMA controls are active i e SOWN is asserted the SCS input is disabled Figure 32 80x8x Mode Bus Arbitration Timing SIF Takes Control 661 HOUVIN Q3SIA3H 666 TIHd V VO LOSMdS dOSS390ddININO9 922086611 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode DMA read timing 205 Setup of SADLO SADL7 SADHO SADHT SPH and SPL valid before SBCLK in cycle no 15 n longer high Hold of SADLO SADL7 SADHO SADHT SPH SPL valid after SBCLK low in T4 cycle if parameters 207a and 207b not met Hold of SADLO SADL7 SADHO SADHT SPH and SPL valid after SRD high 207b Hold of SADL0 SADL7 SADH0 SADH7 SPH and SPL valid after SDBEN no longer low Setup of asynchronous signal SRDY before SBCLK no longer high to guarantee recognition on this cycle 208b Hold of asynchro
15. gee gez 07 11 If SIF register is ready no waiting 0 35 Delay from SDBEN low to SDTACK low see TMS380 Second Generation Token required T Ring User s Guide SPWUOO5 subsection 3 4 1 1 1 If SIF register is not ready waiting 0 4000 required 282W Delay from SDDIR low to SDBEN low 283W Delay from SUDS SLDS high to SDBEN no longer low Pulse duration SUDS or SLDS high between DIO accesses see Note 21 t This specification is provided as an aid to board design t This specification has been characterized to meet stated value It is the later of SRD and SWR or SCS low that indicates the start of the cycle EE NOTES 21 The inactive chip select is SIACK in DIO read and DIO write cycles and SCS is the inactive chip select in interrupt acknowledge cycles 22 In 80x8x mode SRAS may be used to strobe the values of SBHE SRSX SRS0 SRS2 and SCS When used to do so SRAS must meet parameter 266a and SBHE SRS0 SRS2 and SCS must meet parameter 264 If SRAS is strapped high then parameters 266a and 264 are irrelevant and parameter 268 must be met TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS SRSX 5 50 SRS1 Valid 4 25 M 268 SIACK N 273a gt a 272 273 gt ie SRNW N N 4 gt 272 286
16. gt 5005 SLDS N N see Note A 4 273a gt 4 5 280 lt 281 p lt lt 281a gt SDDIR ow Nf 9 282W 283W 14 PJ SDBENt N 279 gt 276 gt 275 gt 255 SDTACKt HI Z HI Z 263 282b 4 262 SADHO SADHT see Note 36 SADLO SADL7 HI Z 7 SPH SPL T SDTACK is active low bus ready signal It must be asserted before data output t When the TMS380C16 begins to drive SDBEN inactive it has already latched the write date internally Parameter 263 must be met to the input of the data buffers NOTE A For 68xxx mode skew between SLDS and SUDS must not exceed 10 ns Provided this limitation is observed all events referenced to a data strobe edge use the later occurring edge Events defined by two data strobes edges such as parameter 286 are measured between latest and earlier edges Figure 38 68xxx DIO Write Timing TEXAS 49 INSTRUMENTS 78 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx interrupt acknowledge cycle timing 2507 or SAD high impedance ater SACK no longer igh ee Nez o fr 260 Setup of ouput data vaid before SDTACK nolongerhigh s 261a Hod of output data valid alter SOS SACK no tonger tow
17. 27 Ethernet Timing of XMIT Signals TEXAS 49 INSTRUMENTS 60 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x DIO read timing PARAN 2507 SAD high impedance afer SAB iow eeno 260 Setup of SADHO SADH7 SADLO SADLT SPH and SPL vaid biore SROV w o e Hold of ouput data valid aner SAD or SOS igh 268 Hold of SRSO SAS2 vald ater SAD ow isee neza Delay from SRD low to SDBEN low see TMS380 Second Generation Token Ring User s Guide SPWUOO5 subsection 3 4 1 1 1 provided previous cycle completed 283R Delay from SRD high to SDBEN high see Note 21 Pulse duration SRD high between DIO accesses see Note 21 t This specification is provided as an aid to board design It is the later of SRD and SWR or SCS low that indicates the start of the cycle 2 NOTES 21 The inactive chip select is SIACK in DIO read and DIO write cycles and SCS is the inactive chip select in interrupt acknowledge cycles 22 In 80x8x mode SRAS may be used to strobe the values of SBHE SRSX SRS0 SRS2 and SCS When used to do so SRAS must meet parameter 266a and SBHE 5 50 5 52 and SCS must meet parameter 264 If SRAS is strapped high then parameters 266a and 264 are irrelevant and parameter 268 must be met TEXA
18. 81 e a V NV N NA x kX YY YY YY YY YY QD lt 83 Figure 14 Memory Bus Timing TMS380C26 Resumes Control of Bus continued TEXAS INSTRUMENTS 48 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing external bus master read from TMS380C26 tM is the cycle time of one eighth of a local memory cycle 31 25 ns minimum wax ur 25 ime of address on and MAX2 after MBCLKT extemal bus master access m 26 Setup time of vaid adress before 1 edge extemal bus master access tne ot vaid address afer MBCLKT low extemal busmasteraooess s 26 Setup time of address high impedance before MBCLKT fling edge external bus masier reed o Setup time val before 8 2 faling dae external bus masterread 20 time of vaid qata paniy after MBCLKZ ow external bus master reed time of MODIR afier MBCLK2 ow external bus mesterre o 795 ime of MAGS ater MBCLKZ ow extemal bus masterra T This specification has been characterized to meet stated value TEXAS 49 INSTRUMENTS POST O
19. BOX 1443 9 HOUSTON TEXAS 21 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 The Protocol Handler contains many state machines which provide the following features Transmit and receive frames Capture tokens token ring Provide token priority controls token ring Automatic retry of frame transmissions after collisions Ethernet Implement the Random Exponential Backoff algorithm Ethernet Manage the TMS380C26 buffer memory Provide frame address recognition group specific functional and multicast Provide internal parity protection Control and verify the physical layer circuitry interface signals Integrity of the transmitted and received data is assured by cyclic redundancy checks CRC detection of network data violations and parity on internal data paths All data paths and registers are optionally parity protected to assure functional integrity adapter support function ASF The Adapter Support Function ASF performs support functions not contained in the other blocks The features are The TMS380C26 base timer Identification management and service of internal and external interrupts Test pin mode control including the unit in place mode for board testing e Checks for illegal states such as illegal opcodes and parity clock generator CG The Clock Generator CG performs the generation of all the clocks required by the other functional blocks and the lo
20. MEASUREMENT INFORMATION Only SCS needs to be inactive SBHE All others are Don t Care SIACK 7 4 gt 272a lt 273a SWR 3 4 273 gt 9 272a SRD 7 N ik 272a 273a gt sDDIR High 279 p lt 282R b 283R 259 4 260 1 SADHO SADH7 SPH SPL see Note A T SRDY is an active low bus ready signal It must be asserted before data output NOTE A In 8 bit 80x8x mode DIO writes the value placed on SADHO SADHT is a don t care Figure 31 80x8x Interrupt Acknowledge Timing Second SIACK Pulse TEXAS 49 INSTRUMENTS 66 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus arbitration timing SIF takes control Setup of asynchronous signal SBBSY and SHLDA before SBCLK no longer high to guarantee 208a D 15 ns recognition on that cycle 208b Hold of asynchronous signal SBBSY and SHLDA after SBCLK low to guarantee recognition on poet 2 that cycle Delay from SBCLK low to SADHO SADH7 SADLO SADL7 SPH and SPL valid 25 ms zx pee rom S8OLK win oie 6 SOW iow s t This specification has been characterized to meet stated value TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON
21. Se Setup of asynchronous input SDTACK before SBCLK no longer high to guarantee recognition on this cycle 208b Hold of asynchronous input SDTACK after SBCLK low to guarantee recognition on this cycle Pulse duration SAS SUDS and SLDS high to iA w SCKL 217 Delay from SBCLK 201 to SXAL low in the TX cycle or SALE low the T1 cycle Ens belay fom S8CLK ow in T2 aseo saam O pees 222 DelaytromSBOLKhigh OSASIOW Delay tom 88 1 m SAS pulse duration 2to Sci Pulse duration 5005 SLDS ic SCK tw SCKH ds TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 85 77251 1443 98 dp SYEL SIN3A THISN 10077 SVXAL 1804 PARAMETER MEASUREMENT INFORMATION TWAIT i i i T4 i TX T1 i T2 I T3 T4 i T1 i l 222 lt gt 211 gt lt 223W e SAS 4 239 gt 4 209 gt 233a 4 0 SUDS 243 gt SLDS 218 216 gt 211a SRNW 217 lt _ Low a R r rn L L u 215 gt 0 217 SXAL N 218 gt 216 lt P 215 gt 216 SALE N 1 212 4 1 233 a 4 233 ka 221 6 gt 5 219 SADLO SADHT7 SPL SPH Extended Address t
22. automatic frame buffer management These counters control system bus retries burst size and track host and LAN subsystem buffer status Previously these counters needed to be maintained in software By integrating them into hardware software overhead is removed and LAN subsystem performance is improved The TMS380C26 implements a Tl patented Enhanced Address Copy Option EACO interface This interface supports external address checking devices such as the TMS380SRA Source Routing Accelerator The TMS380C26 has a 128 word external I O space in its memory map to support external address checker devices and other hardware extensions to the TMS380 architecture Hardware designed in conformance with TI s Specification for External Adapter bus Devices SEADs can map registers into this external I O space and post interrupts to the TMS380C26 The major blocks of the TMS380C26 include the Communications Processor CP System Interface SIF Memory Interface MIF Protocol Handler PH Clock Generator CG and the Adapter Support Function ASF as shown in Figure 2 The TMS380C26 is available in a 132 plastic quad flat pack and is rated from 0 C to 70 IBM is a registered trademark of International Business Machines Corporation TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 3 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 block diagram and signal descriptions
23. capacitance any input f 1 MHz other pins at 0 V Output capacitance any output or input output f 2 1 MHz other pins at 0 V NOTES 10 For conditions shown as MIN or MAX use the appropriate value specified under the recommended operating conditions 11 The following signals require an external pullup resistor SRAS SAS SRDY SDTACK SRD SUDS SWR SLDS and MBRQ TEXAS 49 INSTRUMENTS 30 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO10A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION Outputs are driven to a minimum high logic level of 2 4 volts and to a maximum low logic level of 0 6 volts These levels are compatible with TTL devices Output transition times are specified as follows For a high to low transition on either an input or output signal the level at which the signal is said to be no longer high is 2 volts and the level at which the signal is said to be low is 0 8 volts For a low to high transition the level at which the signal is said to be no longer low is 0 8 volts and the level at which the signal is said to be high is 2 volts as shown below Therise andfalltimes are not specified but are assumed to be those of standard TTL devices which are typically 1 5 ns 2 V High 0 8 V Low test measurement The test load circuit shown in Figure 4 represents the programmable load of th
24. is internally synchronized to SBCLK During cycles it mustbe asserted before the falling edge of SBCLK in state T2 in orderto prevent a wait state SRDY SDTACK This signal is an output when the TMS380C26 is selected for DIO and an input otherwise H System bus NOT ready L Datatransfer is complete system bus is ready System Reset This input is activated to place the adapter into a known initial state Hardware reset will put most of the TMS380C26 output pins into a high impedance state and place all blocks into the SRESET reset state H No system reset L System reset System Register Select These inputs select the word or byte to be transferred during a system DIO access The most significant bit is SRSX and the least significant bit is SRS1 see Note 1 IN MSb LSb Register Selected SRSX SRSO SRS1 Bus Error Corresponds to the bus error signal of the 68000 microprocessor It is internally synchronized to SBCLK This input is driven low during a DMA cycle to indicate to the TMS380C26 that the cycle must be terminated See Section 3 4 5 3 of the 380 Second Generation Token Ring User s Guide SPWU005 for more information see Note 1 SRS2 SBERR 33 SWR SLDS 40 SXAL 42 SYNCIN 108 S8 SHALT 32 Lower Data Strobe see Note 3 This pin is an input during DIO and an output during DMA This pin Serves as the active low lower data strobe H Not valid data on SADLO SADL7 lines L Valid data on SADLO SADL7 line
25. most significant byte of the address is maintained on SADH for T2 T3 and T4 The address is maintained according to parameter 21 i e held after T4 high Figure 34 80x8x Mode DMA Write Timing 661 HOUVIN Q3SIA3H 666 1 THd V VO LOSMdS dOSS390ddININO9 MYOMLAN 922086511 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus arbitration timing SIF returns control UNT Delay from SBCLK low in cycle to SADHO SADH7 SADLO SADL7 SPL SPH SRD and SWR 35 high impedance 223bt Delay from SBCLK low in 11 cycle to SBHE high impedance Lauf Setup of SAD SWR and SEHE high impedance t This specification has been characterized to meet stated value SIF Master Bus Exchange User Master T3 i T4 1 12 2 SHLDA N SIF Outputs 230 C j SHRQ see Note A 220 wm 240 gt lt 223b gt Z SBHE SIF HI Z 220 4 gt 9 gt 240 SADHO SADHT SADLO SADL7 SIF HI Z SPH SPL 224d lt gt WRITE SDDIR Prn_IL READ 224b 4 SOWN see Note B NOTES A In 80x8x mode the system interface deasserts SHRQ on the rising edge of SBCLK following the 4 state of the last system bus transfer it controls In 68xxx mode the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first
26. no RXC PARAMETER MIN UNIT NORXC Time with no clock pulse on RXC when CRS is high see Note 19 NOTE 19 If NORXC is exceeded local clock failure circuitry may become activated resetting the device CRS 1 Figure 25 Ethernet Timing of RCV Signals No RXC ethernet timing of XMIT signals UNT 340 HBWIN Delay time from TXC high of the last transmitted data bit TXEN is high to COLL 47 cycles sampled high so not to generate a heart beat error COLPUL Minimum pulse duration of COLL high for guaranteed sample 20 ns 1 cycle COLSET Setup of COLL high to TXC high gt 340 lt 341 COLL N 342 e TXEN N Figure 26 Ethernet Timing of XMIT Signals TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 59 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of XMIT signals NO PARAMETER UNIT 350 JAMTIM Time from COLL sampled high TXC high to first transmitted JAM bit on TXD 4 cycles see Note 20 COLSET Setup of COLL high before TXC high COLPUL Minimum pulse duration of COLL high for guaranteed sample 20 ns 1 cycle NOTE 20 The JAM pattern is delayed until after the completion of the preamble pattern The TMS380C26 transmits a JAM pattern of all 1 s 3519 kc 352 gt Figure
27. send the TMS380C16 transmit data to the TMS38054 for driving onto the ring transmit signal pair FRAQ TXD NSRT LPBK PXTALIN TXC Frequency Acquisition Control This TTL output determines the use of frequency or phase acquisition mode in the TMS38054 H Wide range Frequency centering to PXTALIN by TMS38054 L Narrow range Phase lock onto the incoming data RCVINA and RCVINB by the TMS38054 Insert Control Signal to the TMS38054 This TTL output signal enables the phantom driver outputs PHOUTA and PHOUTB of the TMS38054 through the watchdog timer for insertion onto the Token Ring Static High Inactive phantom current removed due to watchdog timer Static Low Inactive phantom current removed due to watchdog timer NSRT Low and Pulsed High Active current output on PHOUTA and PHOUTB Ring Interface Clock Frequency Control see Note 5 At 16 Mbps ring speed this input must be supplied a 32 MHz signal At 4 Mbps ring speed the input signal must be 8 MHz and may be the output from the OSCOUT pin Ring Interface Received Data see Note 5 This input signal contains the data received by the TMS38054 from the token ring Ring Interface Ready This input pin provides an indication of the presence of received data as monitored by the TMS38054 energy detect capacitor RCVR RXD REDY CRS WFLT COLL WRAP TXEN NOTE 5 Pin has an expanded input voltage specification H Not reagy Ignore received data L Ready Re
28. strapped high then parameters 266a and 264 are irrelevant and parameter 268 must be met TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 75 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS SRSX Valid 5850 SRS1 4 gt 267 4 gt 268 SIACK N 273a SRNW 7 N 9 272 273 44 5005 5105 286 SDDIR High lt 279 p lt 282R gt 2838 04 9 SDBEN N N 276 27 5 4 gt SDTACKt HI Z 2823 255 Te 4 261 M 259 gt 260 261a SADHO SADHT SADLO SADL7 HI Z lt lt lt Output Data valid HI Z SPH SPL 1 SDTACK is active low bus ready signal It must be asserted before data output Figure 37 68xxx DIO Read Timing TEXAS 49 INSTRUMENTS 76 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx DIO write timing 258 Hold a register adress valid ater SUBS SLOS no longer low see Nose 5008 0808 Delay from SDTACK low in the first DIO access to the SIF register to SDTACK low in the Delay from SUDS or SLDS high to SDDIR high see Note 21 ais ld of SDDIA tow afer SUBS or SLDS no longer
29. the host system In addition the TMS380C26 supports direct and a low cost 8 bit pseudo DMA interface that requires only a chip select to work directly on an 80x8x 8 bit slave I O interface Finally selectable 80x8x 68xxx type host system bus and memory organization add to design flexibility The TMS380C26 supports addressing for up to two Megabytes of local memory This expanded memory capacity can improve LAN subsystem performance by minimizing the frequency of host LAN subsystem communications by allowing larger blocks of information to be transferred at one time The support of large local memory is important in applications that require large data transfers such as graphics or data base transfers and in heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed by the host The proprietary CPU used in the TMS380C26 allows protocol software to be downloaded into RAM or stored in ROM in the local memory space By moving protocols such as LLC to the LAN subsystem overall system performance is increased This is accomplished due to the the offloading of processing from the host system to the TMS380C26 which may also reduce LAN subsystem to host communications As other protocol software is developed greater differentiation of end products with enhanced system performance will be possible In addition the TMS380C26 includes hardware counters that provide realtime error detection and
30. to place the TMS380C26 into a known initial state Hardware reset will put most of the TMS380C26 output pins into a high impedance state and place all blocks into the reset state DMA bus width selection is latched on the rising edge of SRESET SRESET H No system reset L System reset Rising edge Latch bus width for DMA operation System Register Select These inputs select the word or byte to be transferred during a system DIO SRSA 28 access The most significant bit is SRSX and the least significant bit is SRS2 see Note 1 SRSO 27 SRS1 26 SRS2 SBERR 3 MSb LSb Registered selected SRSX SRSO SRS1 SRS2 SBERR 3 System Write Strobe see Note 3 This pin serves as an active low write strobe This pin is an input during DIO and an output during DMA 0 aE i H Write cycle is not occurring L If DMA data to be drivien from SIF to host bus If DIO on the rising edge the data is latched and written to the selected register System Extended Address Latch This output provides the enable pulse used to externally latch the most significant 16 bits of the 32 bit system address during DMA SXAL is activated prior to the first cycle of each block DMA transfer and thereafter as necessary whenever an increment of the DMA SXAL 42 address counter causes a carry out of the lower 16 bits Systems that implement parity on addresses can use SXAL to externally latch the parity bits available on SPL and SPH for the DMA addre
31. unconnected This pin is ignored when CAF mode is enabled see Note 1 H Address match recognized by external address checker L External address checker armed state XMATCH 81 XMATCH XFAIL Function 0 0 Armed Processing frame data 0 1 Do NOT externally match the frame XFAIL takes precedence 1 0 COPY the frame 1 1 Do NOT externally match the frame XFAIL takes precedence HI Z HI Z Reset state adapter not initialized 18 Positive supply voltage for digital logic All Vp pins must be attached to the common system power 100 supply plane VDDL 34 Positive supply voltage for output buffers All Vpp pins must be attached to the common system power supply plane Ground reference for output buffers clean ground All Vgs pins must be attached to the common 116 system ground plane 41 Ground reference for input buffers All Vss pins must be attached to the common system ground 117 plane NOTE 1 Pin has an internal pullup device to maintain a high voltage level when left unconnected no etch or loads TEXAS 49 INSTRUMENTS 18 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued Ground reference for digital logic All pins must be attached to the common system ground plane Ground connections for output buffers All Vas pins must be attached to system ground plane TEXAS 49 INSTRUMENTS POST
32. 12 Memory Bus Timing TMS380C26 Releases Control of Bus continued TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 45 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing TMS380C26 resumes control of bus the cycle time of one eighth of a local memory cycle 31 25 ns minimum Hold time of MIF output high impedance after 1 rising edge bus resume tM 18 80 Delay time from MBCLK1 high to MIF output vallid bus resume Setup time of MBRQ valid before MBCLK1 falling edge bus resume Hold time of MBRQ valid after MBCLK1 low bus resume O Setup time of MBGR high before MBCLK1 rising edge bus resume TEXAS 49 INSTRUMENTS 46 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION wan N N MOROMEN MAXPH MAXPL MADHO MADHT MADLO MADL7 MCAS 44227 Figure 13 Memory Bus Timing TMS380C26 Resumes Control of Bus TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 47 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION TE Z NN MEER MDDIR MAL N WERE 0 1
33. 3 Pseudo DMA Logic Related to SIFACL Bits i TEXAS 39 INSTRUMENTS 29 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 absolute maximum ratings over operating free air temperature range unless otherwise noted t Supply voltage range Vpp see Note 6 7V Input voltage range see Note 6 0 3 20V Output voltage rang as usus E gay decd 2Vto7V POWEF CISSIDALION ea ghee 1 0 W Operating free air temperature range 0 C to 70 C Storage temperature range 65 C to 150 C t Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE 6 Voltage values are with respect to Vss recommended operating conditions Vpp Supply voltage 4 75 5 5 25 Vss Supply voltage see Note 7 V TTL level signal High level input v
34. AMETER MEASUREMENT INFORMATION memory bus timing clocks MRAS MCAS and MAL to ADDRESS the cycle time of one eighth of a local memory cycle 31 25 ns minimum NO PARAMETER MIN MAX UNIT Setup time of row address on MADLO MADL7 MAXPH and MAXPL before MRAS no longer 15 high 1 5ty 11 5 ns Setup time of column address MADLO MADL7 MAXPH and MAXPL and status 0 5 9 MADHO MADH7 before MCAS no longer high us Hold time of column address MADLO MADL7 MAXPH and MAXPL and status 1 9 after MCAS low M ns Hold time of column address MADLO MADL7 MAXPH and MAXPL and status 25 6 5 MADHO e dL after MRAS no longer high M ER TEXAS 49 INSTRUMENTS 38 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 PARAMETER MEASUREMENT INFORMATION 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Wu X Cre X X MABUSOMADLS 16 gt 26 4 17 4 154 4 gt 19 gt MRAS lt 18 9 21 20 gt M 24 h 4 23 MCAS 1 N F NN O O m IN MAX2 MROMEN 30 MADHO MADH7 Addre lt lt 21 e hr 20 4 22 KEEN 5 saus Address 2 Figure 8 Memory Bus Timing Clocks MRAS MCAS and MAL to ADDRESS TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9
35. APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing clocks MAL MROMEN MBIAEN NMI MRESET and ADDRESS tM is the cycle time of one eighth of a local memory cycle 31 25 ns minimum MAX wr _ 7 s Setup ime oadiresstenabie MAXO 2 and MROMEN before wmo 2 Setuptme otrow adress on WADLO MADLT MAXPH and MAXPL before MBCLKT nolongerhgh Setup time of column address on MADLO MADL7 MAXPH and MAXPL before MBCLK1 no 13 longer low 0 54 9 ns homeo I K s i cT T 49 INSTRUMENTS 36 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION M8 M1 M2 M3 M5 7 MBCLK1 MBCLK2 MROMEN MAXPH MAP Row X c MADLO MADL7 o gt e gt en n gt e 2 129 MAL N 120 Pa gt 121 VOOM i 555555555 AON 00000 gt 126 MRESET X Valid Figure 7 Memory Bus Timing Clocks MAL MROMEN MBIAEN NMI MRESET and ADDRESS TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 37 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PAR
36. DLT7 and 48at MADHO MADH and before MBIAEN no longer high 25 Access time from MBEN low to valid data parity 2 25 Access time from MBIAEN low to valid data parity 21 25 Pulse duration MBEN low 2tM 9 Pulse duration MBIAEN low 21 9 Hold time of valid data parity after MBEN no longer low O Hold time of valid data parity after MBIAEN longer low Hold time of address high impedance MAXPH MAXPL MADH0 MADH7 and MADLO MADLT7 after MBEN high see Note 13 21 15 Hold time of address high impedance MAXPH MAXPL MADHO MADHT7 and 52 MADLO MADL7 after MBIAEN high 21 15 53 Hold time of MDDIR high after MBEN high read follows write cycle 1 5 12 Setup time of MDDIR low before MBEN no longer high 3tM 9 Hold time of MDDIR low after MBEN high write follows read cycle 3tM 12 T This specification has been characterized to meet stated value NOTE 13 The data parity that exists on the address lines will most likely achieve a high impedance condition sometime later than the rising edge of MRAS MCAS MOE or MBEN between MIN and MAX of timing parameter 36 and will be a function of the memory being read Hence the MIN time given represents the time from the rising edge of MRAS MCAS MOE or MBEN to the beginning of the next address and does not represent the actual high impedance period on the address bus TEXAS 49 INSTRUMENTS 40 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443
37. DMA This signal is internally synchronized to SBCLK H The TMS380C26 can hold onto the system bus see Note 1 L TheTMS380C26 should release the system bus upon completion of current DMA cycle If the DMA transfer is not yet complete the SIF will rearbitrate for the system bus t Typical bit ordering for Intel and Motorola processor buses NOTE 1 Pin has an internal pullup device to maintain a high voltage level when left unconnected no etch or loads System Chip Select Activates the system interface of TMS380C26 for a DIO read or write Not selected see Note 1 Selected System Data Bus Enable This output signals to the external data buffers to begin driving data This output is activated during both DIO and DMA 43 81 44 SBHE SRNW 57 30 29 8 H Keep external data buffers in high impedance state L Cause external data buffers to begin driving data TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 13 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued System Interface Motorola Mode SI M L System Data Direction This output provides to the external data buffers a signal indicating the direction in which the data is moving During DIO writes and DMA reads SDDIR is low data direction input to the 380 26 During DIO reads and writes SDDIR is high data direction output from the 380 26 When th
38. ENTS 8 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued System Interface Intel Mode SI M vo System Address Data Bus high byte see Note 1 These lines make up the most significant byte of each address word 32 bit address bus and data word 16 bit data bus The most significant bit is SADHO and the least significant bit is SADH7 Address Multiplexing T Bits 31 24 and bits 15 8 Data Multiplexing T Bits 15 8 System Address Data Bus low byte see Note 1 These lines make up the least significant byte of each address word 32 bit address bus and data word 16 bit data bus The most significant bit is SADLO and the least significant bit is SADL7 Address Multiplexing T Bits 23 16 and bits 7 0 Data Multiplexing T Bits 7 0 System Address Latch Enable This is the enable pulse used to externally latch the 16 LSBs of the address from the SADHO SADH7 and SADLO SADL7 buses at the start of the cycle Systems that implement address parity can also externally latch the parity bits SPH and SPL for the latched address il System Bus Busy The TMS380C26 samples the value on this pin during arbitration The sample has one of 2 two values see Note 1 IN H Not busy The TMS380C26 may become Bus Master if the grant condition is met L Busy The
39. FADR LSB SIFSTS SIFACL LSB SIFADR LSB SIFADX LSB DMALEN LSB DMALEN MSB SDMAADR MSB SDMAADX MSB DMALEN LSB SDMAADR LSB SDMAADX LSB SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB SIFACL LSB SIFADR LSB SIFADX LSB DMALEN LSB Normal Pseudo DMA SRS2 SBHE X SBHE X SDMADAT DMALEN LSB DMALEN MSB SDMAADR LSB SDMAADR MSB SDMAADX LSB SDMAADX MSB SIFACL LSB SIFACL MSB SIFADR LSB SIFADR MSB SIFADX LSB SIFADX MSB DMALEN LSB DMALEN MSB Pseudo DMA Mode Active 0 DMALEN MSB SDMAADR MSB SDMAADX MSB SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB SDMADAT DMALEN LSB SDMAADR LSB SDMAADX LSB SIFACL LSB SIFADR LSB SIFADX LSB DMALEN LSB TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 25 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 SIF Adapter Control Register SIFACL The SIFACL register allows the host processor to control and to some extent reconfigure the TMS380C26 under software control SIFACL dd Bit 0 1 2 5 5 5 SWHLDA ARESET cPHALT SINTEN NSEL OUTO OUT1 01112 RRR W 1 RP p RP 0 RP Read W Write P Write during ARESET 1 only S Set Only n Value after reset b Value on BTSTRP pin p Value on PRTYEN pin Indeterminate Bits 0 2 TEST 0 2 Value on TEST 0 2 pins These bits are read only and always reflect the value on the corresponding device pins This
40. FFICE BOX 1443 9 HOUSTON TEXAS 49 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 Z X Z N MBCLK2 Sin 84 85 e Address In Address In 86 M 87 l pe lt 89 0 91 c 90 MADHO MADHT MADLO MADL7 Address In Address In 92 6 93 ARRI 94 hh K 05 1 9 4 wo ED Figure 15 Memory Bus Timing External Bus Master Read From TMS380C26 EXAS INSTRUMENTS 50 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing external bus master write to TMS380C26 96 Setup time of valid data parity before MBCLK2 falling edge external bus master write Hold time of valid data parity after MBCLK2 low external bus master write 98 Setup time of MDDIR high before MBCLK2 falling edge external bus master write 99 Hold time of MDDIR high after MBCLK2 low external bus master write n MBCLK1 CA Wwe we 27 T In Address In 350008 650000 00000000000000000000 97 MAXPL 6500000000000 XD MAXPL m 600 EOK A numi
41. HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing read cycle is the cycle time of one eighth of a local memory cycle 31 25 ns minimum Access time from address enable valid on MAX2 and MROMEN to valid data parity 23 33 Access time from address valid MAXPL MADHO MADH7 and MADLO MADL7 to valid data parity 6t 23 ns Access time from MRAS low to valid data parity 4 5tM 21 5 Hold time of valid data parity after MRAS no longer low 0 m Hold time of address high impedance on MAXPH MAXPL MADHO MADH7 and 37t MADLO MADL after MRAS high see Note 13 21 10 5 ns Access time from MCAS low to valid data parity 3tM 23 Hold time of valid data parity after MCAS no longer low O n Hold time of address high impedance on MAXPH MAXPL MADHO MADHT7 and 40t MADLO MADL7 after MCAS high see Note 13 21 13 HS Delay time from MCAS no longer high to MOE low tM 13 Setup time of address status high impedance on MAXPH MAXPL MADLO MADLT7 and CENE E Se a ee a Hold time of address high impedance on MAXPH MAXPL MADHO MADH7 and MADLO MADL7 after high see Note 13 2101 15 Setup time of address status high impedance MAXPH MADLO MADL7 and MADHO MADHT before MBEN no longer high Setup time of address status high impedance on MAXPH MAXPL MADLO MA
42. IEEE 802 5 and IBM Token Ring Network Compatible IEEE 802 3 and Blue Book Ethernet Network Compatible Pin and Software Compatible With the TMS380C16 Configurable Network Type and Speed Selectable by Host Software Control Adapter Control Register Selectable by Network Front End Readable from Host Adapter Control Register Token Ring Features 16 or 4 Megabit per Second Data Rates Supports up to 18K Byte Frame Size 16 Mbps Operation Only Supports Universal and Local Network Addressing Early Token Release Option 16 Mbps Operation Only Compatible With the TMS38054 Ethernet Features 10 Megabit per Second Data Rate Compatible With Most Ethernet Serial Network Interface Devices Full Duplex Ethernet Operation Allows Network Speed Self test Expandable Local LAN Subsystem Memory Space up to 2 Megabytes Supports Multicast Addressing of Network Group Addresses Through Hashing Glueless Interface to DRAMs High Performance 16 Bit CPU for Communications Protocol Processing Up to 8 Megabyte per Second High Speed Bus Master DMA Interface network commprocessor applications diagram 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Low Cost Host Slave I O Interface Option Up to 32 Bit Host Address Bus Selectable Host System Bus Options 80x8x or 68xxx Type Bus and Memory Organization 8 or 16 Bit Data B
43. MATION 2 I Address MROMEN Enable MAXPH MAXPL MADHO MADH7 ADD STS I Data Parity Out MADLO MADL7 MRAS CT NAS d Z 46 55 58 5 N 60 65 63 gt lt 64 gt N 17 MW 69 67 gt 66 gt MBEN N 6 72 73 4 9 MDDIR y Y Figure 10 Memory Bus Timing Write Cycle TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 43 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing TMS380C26 releases control of bus tM is the cycle time of one eighth of a local memory cycle 31 25 ns minimum UNT 77 of MEAG ow afer MBCLKTIow 0 gt MROMEN MAXPH MADHO MADHT MADLO MADL7 49 75 MRAS Figure 11 Memory Bus Timing TMS380C26 Releases Control of Bus TEXAS 49 INSTRUMENTS 44 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 I A 5 N N 74a MDDIR MBIAEN 77 4 75 V Y Y Y Y M NEN NE NON NE NEN NE NEN NEMNEM NN NN NOUN M MBGR N Figure
44. NFORMATION 80x8x mode DMA write timing UNT Setup of asynchronous signal SRDY before SBCLK no longer high to guarantee recognition 208a 15 ns on that cycle se e 5 s Delay from SBCLK low in T2 cycle to SWR low 232 Pulse duration SWR low 2lc SCK 30 33 Setup of SADHO SADH7 SADLO SADL7 SPH and SPL valid before SALE SXAL t _ no longer high w SCKL Delay from SBCLK high in T1 cycle to SDBEN low 2 225WH Hold of SDBEN low after SWR SUDS and SLDS high tw SCKL 25 TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 71 77251 1443 eL 10077 SVXAL 391430 1804 SIN3A THISN SVAL PARAMETER MEASUREMENT INFORMATION TWAIT TX TI T2 T3 1 SBCLK 212 5l tse note A HIGH SRD 227W _ y 223W 2 232 216 217 lg 215 p 217 4 y SXAL 216 lt gt 215 216a ler SALE 212 233 4 233 le y 218 do 212 4 218 4 4 1 219 4 SADLO SADHT SADHO SADLT7 SPH SPL see Note B Extended Address 208 SRDY 225W 237W j 5W SDBEN NI 208b j 225WH 7 SDDIR HIGH NOTES A In8 bit 80x8x mode SBHE SRNW is a don t care input during DIO and an inactive high output during DMA B In 8 bit 80x8x mode the
45. OFFICE BOX 1443 9 HOUSTON TEXAS 19 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 architecture The major blocks of the TMS380C26 include the Communications Processor CP System Interface SIF Memory Interface MIF Protocol Handler PH Clock Generator CG and the Adapter Support Function ASF The functionality of each block is described in the following sections communications processor CP The Communications Processor CP performs the control and monitoring of the other functional blocks in the TMS380C26 The control and monitoring protocols are specified by the software downloaded or ROM based in local memory Available protocols include Media Access Control MAC software 9 Logical Link Control LLC software token ring version only and Copy All Frames CAF software The CP is a proprietary 16 bit central processing unit CPU with data cache and a single prefetch pipe for pipelining of instructions These features enhance the TMS380C26 s maximum performance capability to about 4 million instructions per second MIPS with an average of about 2 5 MIPS system interface SIF The System Interface SIF performs the interfacing of the LAN subsystem to the host system This interface may require additional logic depending on the application The system interface can transfer information data using any of these three methods Direct Memory Access Dir
46. OFFICE BOX 1443 9 HOUSTON TEXAS 9 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued System Interface Intel Mode SI M wwe System Data Direction This output provides to the external data buffers a signal indicating the direction in which the data is moving During DIO writes and DMA reads SDDIR is low data direction input to the TMS380C26 During DIO reads and DMA writes SDDIR is high data direction output from the TMS380C26 When the system interface is NOT involved in a DIO or DMA operation then SDDIR is high by default DATA SDDIR DIRECTION DIO DMA H output read write L input write read System Hold Acknowledge This pin indicates that the system DMA hold request has been acknowledged It is internally synchronized to SBCLK see Note 1 H Hold request acknowledged Hold request not acknowledged SHLDA SBGR System Hold Request This pin is used to request control of the system bus in preparation for a DMA transfer This pin is internally synchronized to SBCLK H System bus requested L System bus not requested System Interrupt Acknowledge This signal is from the host processor to acknowledge the interrupt request from the TMS380C26 H System interrupt not acknowledged see Note 1 System interrupt acknowledged the TMS380C26 places its interrupt vector onto the system bus System Intel Motorola Mode
47. S 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 61 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS SRSX SBHE 264 lt 265 gt 268 SRAS 7 N 256 8 266a gt 267 SIACK lt p 272a 3 4 273a p SWR 4 273a 4 272a SRD 273 lt gt 272a 286 High SDDIR 228 282R 4 2838 SDBEN N N lt gt 282a 275 4 2 lt 255 4 260 EN 261 261a SADHO SADHT 259 SPH SPL HI Z AW Output Data Valid 2 see Note B t When the TMS380C26 begins to drive SDBEN inactive it has already latched the write data internally Parameter 263 must be met to the input of the data buffers m NOTES A In80x8x mode SRAS may be used to strobe the values of SBHE SRSX SRS0 SRS2 and SCS When used to do so SRAS must meet parameter 266a and SBHE SRS0 SRS2 and SCS must meet parameter 264 If SRAS is strapped high then parameters 266a and 264 are irrelevant and parameter 268 must be met B In 8 bit 80x8x mode DIO reads the SADHO SADH7 contain don t care data Figure 28 80x8x DIO Read Timing TEXAS 49 INSTRUMENTS 62 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMEN
48. SCS SRSX SRS2 register input signals In a minimum chip system SRAS is tied to the SALE output of the System Bus The latching capability can be defeated since the internal latch for these inputs remains transparent as long as SRAS remains high This permits SRAS to be pulled high and the signals at the SCS SRSX SRS2 and SBHE to be applied independently of the SALE strobe from the system bus SRAS SAS During DMA this pin remains an input High transparent mode Low Holds latched values of SCS SRSX SRS2 and SBHE Falling edge latches SCS SRSX SRS2 and SBHE System Read Strobe see Note 3 Active low strobe indicating that a read cycle is performed on the system bus This pin is an input during DIO and an output during DMA SRD SUDS 61 H Read cyle is not occurring L If DMA host provides data to system bus If DIO SIF provides data to system bus System Bus Ready see Note 3 The purpose of this signal is to indicate to the bus master that a data transfer is complete This signal is asynchonous but during DMA and pseudo DMA cycles it is internally synchronized to SBCLK During DMA cycles it must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state This signal is an output when the TMS380C26 SRDY SDTACK is selected for DIO and an input otherwise H System bus NOT ready L Data transfer is complete system bus is ready System Reset This input signal is activated
49. SNOH 391430 1804 SIN3A THISN SVXAL PARAMETER MEASUREMENT INFORMATION User Master Bus Exchange SIF Master SIF Inputs T4 n 12 TX T1 2 SBCLK ua WE 270 22 1 1 u 208b 1 1 1 Z gt 208a SBGR SBERR SDTACK SBBSY SIF Outputs lt gt 230 230 5 see Note 208a 4 4 p 208b lt p 241 SAS SLDS 5005 Input Output 4 gt 21 READ WRITE UU U 212 4 SADHO SADHT SADLO SADL7 2 SIF SPH SPL 4 224c WRITE SDDIR READ aai e l lt 224a SOWN 241a gt see Note B NOTES A In 80x8x mode the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls In 68xxx mode the System interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls B While the system interface DMA controls are active SOWN is asserted the SCS input is disabled Figure 40 68xxx Mode Bus Arbitration Timing SIF Takes Control 661 Q3SIA3H 666 TIHd V VO LOSMdS dOSS390ddININO9 922086611 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode DMA read timing M Ax UNT
50. Select The value on this pin specifies the system interface mode H Intel compatible interface mode selected Intel interface can be 8 bit or 16 bit mode see S8 SHALT pin description and Note 1 L Motorola compatible interface mode selected System Interrupt Request TMS380C26 activates this output to signal an interrupt request to the host processor SINTR SIRQ H Interrupt request by TMS380C26 L Nointerrupt request System Bus Owned This signal indicates to external devices that TMS380C26 has control of the System bus This signal drives the enable signal of the bus transceiver chips which drive the address and bus control signals TMS380C26 does not have control of the system bus TMS380C26 has control of the system bus System Parity High The optional odd parity bit for each address or data byte transmitted over SADHO SADH7 see Note 1 System Parity Low The optional odd parity bit for each address or data byte transmitted over SADLO SADL7 see Note 1 NOTE 1 Pin has an internal pullup device to maintain a high voltage level when left unconnected no etch or loads TEXAS 49 INSTRUMENTS 10 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued System Interface Intel Mode SI M System Memory Address Strobe see Note 3 This pin used to latch the
51. T INFORMATION 80x8x DIO write timing 2 2s SASK SASO SAS2 ater no longer low eee Note 22 Delay from SRDY low in the first DIO access to the SIF register to SRDY low in the immediately following access to the SIF see TMS380 Second Generation Token Ring User s Guide SPWU005 subsection 3 4 1 1 1 Lama Hold of SDDIR after SWA no longer active see Nez 0 If SIF register is ready no waiting 0 35 Delay from SDBEN low to SRDY low see 7MS380 Second Generation Token Ring required User s Guide SPWUOO5 subsection 3 4 1 1 1 If SIF register is not ready waiting 0 4000 required 282W Delay from SDDIR low to SDBEN low 283W Delay from SCS or SWR high to SDBEN no longer low Pulse duration SWR high between DIO accesses see Note 21 T It is the later of SRD and SWR or SCS low that indicates the start of the cycle t This specification has been characterized to meet stated value This specification is provided as an aid to board design NOTES 21 The inactive chip select is SIACK in DIO read and DIO write cycles and SCS is the inactive chip select in interrupt acknowledge cycles 22 80x8x mode SRAS may be used to strobe the values of SBHE SRSX SRS0 SRS2 and SCS When used to do so SRAS must meet parameter 266a SBHE SRS0 SRS2 and SCS must meet parameter 264 If SRAS is strapped high then parameters 266a and 264 ar
52. TACKt T ue 259 260 4 p lt 261 lap 261a SADHO SADH7 SADLO SADL7 2 Output Data Valid HI Z SPH SPL see Note A 1 SDTACK is an active low bus ready signal It must be asserted before data output NOTE A Internal logic will drive SDTACK high and verify that it has reached a valid high level before three stating the signal Figure 39 68xxx Interrupt Acknowledge Cycle Timing TEXAS 49 INSTRUMENTS 80 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus arbitration timing SIF takes control MAX UNT Setup of asynchronous input SBGR before SBCLK longer high to guarantee recognition on 208a this cycle 15 ns 208b Hold of asynchronous input SBGR after SBCLK low to guarantee recognition on this cycle Delay from SBCLK low to address valid 230 Delay rom right erher SHAG ow sfe 241 Delay rom SBCLK righ in TX ole to SUDS 5008 241 Hold of SUDS SLDS SRNW and SAS high impedance after SOWN low bus acquisition e SCK t5 ns t This specification has been characterized to meet stated value NOTE 24 Motorola style bus slaves hold SDTACK active until the bus master deasserts SAS TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 81 77251 1443 28 10077 SVXAL NOL
53. TMS380C26 cannot become Bus Master System Bus Clock The 380 26 requires the external clock to synchronize its bus timings for SBCLK all DMA transfers System Byte High Enable This pin is a three state output that is driven during DMA and an input at all other times H System Byte High not enabled see Note 1 L System Byte High enabled System Bus Release This pin indicates to the TMS380C26 that a higher priority device requires the system bus The value on this pin is ignored when the TMS380C26 is NOT perfoming DMA This signal is internally synchronized to SBCLK H The TMS380C26 can hold onto the system bus see Note 1 L TheTMS380C26 should release the system bus upon completion of current DMA cycle If the DMA transfer is not yet complete the SIF will rearbitrate for the system bus t Typical bit ordering for Intel and Motorola processor buses NOTE 1 Pin has an internal pullup device to maintain a high voltage level when left unconnected no etch or loads System Chip Select Activates the system interface of the TMS380C26 for a DIO read or write Not selected see Note 1 Selected System Data Bus Enable This output signals to the external data buffers to begin driving data This output is activated during both DIO and DMA 43 81 44 SBHE SRNW 57 30 29 8 H Keep external data buffers in high impedance state L Cause external data buffers to begin driving data TEXAS 49 INSTRUMENTS POST
54. The values in these bits control the output pins NSELOUTO and NSELOUT1 These bits can only be modified while the ARESET bit is set These bits can be used to software configure a multi protocol 380 26 as follows The NSELOUTO and NSELOUT1 pins should be connected to TESTO and TEST1 pins respectively TEST2 should be left unconnected or tied high NSELOUTO should be used to select network speed and NSELOUT1 network type as shown in the table below NSELOUTO NSELOUT1 0 0 Reserved 0 1 16 Mbps token ring 1 0 Ethernet 802 3 Blue Book 1 1 4 Mbps token ring At power up these bits are set NSELOUT1 1 NSELOUTO 0 corresponding to 16 Mbps token ring 28 TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 SIFACL Control for Pseudo DMA Operation Pseudo DMAis software controlled by the use of five bits in the SIFACL register The logic model for the SIFACL register control of pseudo DMA operation is shown in Figure 3 Internal Motorola Mode Host Signals Interface SYSTEM INTERRUPT gt ly SIFSTS Register m SINTR SIRQ gt 5 5 Request SHLDA SBGR T C EL Grant e DMADIR 1 SDDIR SWHLDA SWDDIR SWHRQ PSDMAEN SINTEN SIFACL Register Figure
55. This bit then controls the operation of the MCAS and MROMEN pins 0 ROM PROM EPROM memory in chapters 0 and 31 1 RAM memory in chapters 0 and 31 RESO Reserved This bit must be set to zero TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 27 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Bit 12 Bit 13 Bit 14 15 SINTEN System Interrupt Enable This bit allows the host processor to enable or disable system interrupt requests from the TMS380C26 The system interrupt request from the TMS380C26 is onthe SINTR SIRQ pin The following equation shows how the SINTR SIRQ is driven The table also explains the results of the states SINTR SIRQ PSDMAEN SWHRQ ISWHLDA SINTEN SYSTEM INTERRUPT SYSTEM SWHLDA SINTEN INTERRUPT RESULT SIFSTS Reg Pseudo DMA is active The TMS380C26 generated a system interrupt for a pseudo DMA Not a pseudo DMA interrupt The TMS380C26 will generate a system interrupt The TMS380C26 will not generate a system interrupt The TMS380C26 can not generate a system interrupt t The value on the SHLDA SBGR pin is ignored PEN Adapter Parity Enable This bit determines whether data transfers within the TMS380C26 are checked for parity 0 Datatransfers are not checked for parity 1 Data transfers are checked for correct odd parity NSELOUT 0 1 Network selection outputs
56. allows the host S W to determine the network type and speed configuration If the network speed and type are software configurable these bits can be used to determine which configurations are supported by the network hardware TESTO TESTI TEST2 Description L L H Reserved L H H 16 Mbps token ring H L H Ethernet 802 3 Blue Book H H H 4 Mbps token ring X X 0 Reserved Bit 3 Reserved Read data is indeterminate Bit 4 SWHLDA Software Hold Acknowledge This bit allows the SHLDA SBGR pin s function to be emulated from software control for pseudo DMA SWHLDA value in the SIFACL register cannot be set to one No pseudo DMA request pending Indicates a pseudo DMA request interrupt Pseudo DMA process in progress T The value on the SHLDA SBGR pin is ignored Bit 5 SWDDIR Current SDDIR Signal Value This bit contains the current value of the pseudo DMA direction This enables the host to easily determine the direction of DMA transfers which allows system DMA to be controlled by system software 0 Pseudo DMA from host system to TMS380C26 1 Pseudo DMA from TMS380C26 to host system TEXAS 49 INSTRUMENTS 26 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 SWHRQ Current SHRQ Signal Value This bit contains the current value on the SHRQ SBRQ pin when in Inte
57. cal memory bus clocks This block also generates the reference clock to be sampled by the SIF to determine if the TMS380C26 needs to be placed into slow clock mode This reference clock is free floating in the range of 10 100 kHz user accessible hardware registers and TMS380C26 internal pointers The following tables show how to access internal data via pointers and how to address the registers in the host interface The SIFACL register which directly controls device operation is described in detail NOTE The Adapter Internal Pointers Table is defined only after TMS380C26 initialization and until the OPEN command is issued These pointers are defined by the TMS380C26 software microcode and this table describes the release 1 00 and 2 x software 22 TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Adapter Internal Pointers for Token Ringt 00 FFF8t Pointer to software raw microcode level in chapter 0 00 FFFAt Pointer to starting location of copyright notices Copyright notices are separated by a gt 0A character and terminated by gt 00 character in chapter 0 gt 01 0A00 Pointer to burned in address in chapter 1 gt 01 0A02 Pointer to software level in chapter 1 gt 01 0A04 Pointer to TMS380C26 addresses in chapter 1 Pointer 0 node address Pointer 6 group address Pointer 10 functional addre
58. ceived data Wire Fault Detect This signal is an input to the TMS380C16 driven by the TMS38054 It indicates a current imbalance of the TMS38054 PHOUTA and PHOUTB pins H No wire fault detected L Wire fault detected Internal Wrap Select This signal is an output from the 5380 16 to the ring interface to activate an internal attenuated feedback path from the transmitted data DRVR to receive data RCVR signals for bring up diagnostic testing When active the TMS38054 also cuts off the current drive to the transmission pair H Normal ring operation L Transmit data drives receive data loopback et Ring Interface Recovered Clock see Note 5 This input signal is the clock recovered by the TMS38054 from the Token Ring received data RCLK RXC For 16 Mbps operation it is a 32 MHz clock For 4 Mbps operation it is an 8 MHz clock TEXAS 49 INSTRUMENTS 16 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued Network Media Interface Ethernet Mode TEST1 L TEST2 H RENE These pins have no Ethernet function In Ethernet Mode these pins are placed in their token ring reset FRAQ TXD state of DRVR High DRVR Low NSRT LPBK PXTALIN TXC RCLK RXC Ethernet Transmit Data This output signal provides the Ethernet physical layer circuitry with bit rate from the TMS380C26 Data
59. cessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used 5 publication of information regarding any third party s products or services does not constitute approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
60. connected to DRAMs without additional circuitry This glueless DRAM connection includes the DRAM refresh controller The MIF also handles all internal bus arbitration between these blocks When required the MIF then arbitrates for the external bus The is responsible for the memory mapping of the CPU of a task The memory map of DRAMs 5 Burned in Addresses BIA and External Devices are appropriately addressed when required by the System Interface SIF Protocol Handler PH or for a DMA transfer The memory interface is capable of a 64 Mbps continuous transfer rate when using a 4 MHz local bus 64 MHz device crystal protocol handler PH The Protocol Handler PH performs the hardware based realtime protocol functions for a token ring or Ethernet Local Area Network LAN Network type is determined by the test pins TESTO 2 Token ring network is determined by software and can be either 16 Mbps or 4 Mbps These speeds are not fixed by the hardware but by the software The PH converts the parallel transmit data to serial network data of the appropriate coding and converts the received serial data to parallel data The PH data management state machines directthe transmission reception of data to from local memory through the MIF The PH s buffer management state machines automatically oversee this process directly sending receiving linked lists of frames without CPU intervention TEXAS 49 INSTRUMENTS POST OFFICE
61. d Monitor for the presence of a clock failure 20 TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 On every cycle the system interface compares all the system clocks to a reference clock If any of the clocks become invalid the TMS380C26 enters the slow clock mode which prevents latchup of the TMS380C26 If the SBCLK is invalid any DMA cycle is terminated immediately otherwise the DMA cycle is completed and then the TMS380C26 is placed in slow clock mode When the TMS380C26 enters the slow clock mode the clock that failed is replaced by a slow free running clock and the device is placed into a low power reset state When the failed clock s return to valid operation the TMS380C26 must be re initialized Using DMA a continuous transfer rate of 64 Mbits per second Mbps which is 8 MBytes per second MBps can be obtained For pseudo DMA a continuous transfer rate of 48 Mbps 6 MBps can be obtained when using a16 MHz clock The DIO transfer rate is nota significant issue since the main purpose of DIO is for downloading and initialization For comparison the ISA bus continuous DMA transfer is rated for approximately 23 Mbps memory interface MIF The Memory Interface MIF performs the memory management to allow the TMS380C26 to address 2 MBytes in local memory Hardware in the MIF allows the TMS380C26 to be directly
62. e bidirectional buffer outputs on the MADH MAXPH MAXPL and MADL buses during the data phase This signal is used in conjunction with MDDIR which selects the buffer output direction H Buffer output disabled L Buffer output enabled Reserved Must be left unconnected Burned In Address Enable This is an output signal used to provide an output enable for the ROM containing the adapter s Burned In Address BIA This signal is driven high for any WRITE accesses to the addresses between gt 00 0000 and gt 00 000F or any accesses Read Write to any other address This signal is driven low for any READ from addresses between gt 00 0000 and gt 00 000F Column Address Strobe for DRAMs The column address is valid for the 3 16 of the memory cycle following the row address portion of the cycle This signal is driven low every memory cycle while the column address is valid on MADLO MADL7 MAXPH and MAXPL except when one of the following conditions occurs When the address accessed is in the ROM 200 0000 gt 00 000F When the address accessed is in the EPROM memory map i e when the BOOT bit in the SIFACL register is zero and an access is made between 200 0010 gt 00 FFFF or gt 1F 0000 gt 1F FFFF When the cycle is a refresh cycle in which case MCAS is driven at the start of the cycle before MRAS for DRAMs that have CAS before RAS refresh For DRAMs that do not support CAS before RAS refresh it may be necessary
63. e irrelevant and parameter 268 must be met TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 63 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS SRSX SRSO SRS2 SBHE SRAS 256 SIACK gt 26 4 26 272a amp 273a gt SWR 4 273a lt 272a 286 gt SRD 7 _ 2728 4 273a EN 2 281 ER 80 SDDIR High 281 4 282W lq 2833W 4 SDBEN T N _ 276 gt 279 c 275 4 0 SRDY l 2826 y i HI Z 255 gt HI Z lt gt 263 262 SADHO SADHT SADLO SADL7 2 SPH SPL see Note A t When the TMS380C26 begins to drive SDBEN inactive it has already latched the write data internally Parameter 263 must be met to the input of the data buffers NOTE A In 8 bit 80x8x mode DIO writes the value placed on SADHO SADHT is a don t care Figure 29 80x8x DIO Write Timing TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 64 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x interrupt acknowledge timing first SIACK pulse Pulse duration SIACK high between DIO accesses see Note 21 Pulse durat
64. e shown in Figure 1 132 PIN QUAD FLAT PACK TOP VIEW ECEE Toran OR 2 aoe 82229199319 2 o E ktrEooooaooaoxdoo0xoooooaaooodoiuu 0 2 21 222222222 12 gt gt gt gt gt gt gt gt gt gt Z gt Eu XI LEGI ITI QN CO QN lt Q s CO 04 O oo m TUNE S N N M Ww Ics VDDL V CLKDIV MRAS Vssc MW NSELOUTO MCAS PRTYEN MAX2 BTSTRP MAXO SIACK MDDIR SRESET SRS1 SYNCIN SRSO OSCIN SRSX 5 5 MROMEN SBRLS MACS SBBSY MAL S8 SHALT MREF SRS2 SBERR MBIAEN VDDL V SI M MRESET SINTR SIRQ MBCLK2 SHLDA SBGR MBCLK1 SDDIR OSCOUT SRAS SAS RCVR RXD SWR SLDS RCLK RXC NSETOUT1 SXAL PXTALIN TXC SALE Vss1 SBCLK WRAP TXEN SADL7 DRVR SADL6 DRVR SADL5 WFLT COLL SADL4 NSRT LPBK SADL3 FRAQ TXD VDD5 REDY CRS 0 WN o IBziziziejormvoododoiszow oiuoito0w o dr 20845 2 8 8532883333338 08 88 7555 95025252777 359505 s 2E 4 I 22 nln c o Figure 1 TMS380C26 Pinout Texas W NSTRUMENTS 2 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 description 380 26 is a s
65. e system interface is NOT involved in a DIO or operation then SDDIR is high by default DATA SDDIR DIRECTION DIO DMA H output read write L input write read System Bus Grant This pin serves as an active low bus grant as defined in the standard 68000 interface and is internally synchronized to SBCLK see Note 1 SHLDA SBGR H System bus not granted L System bus granted System Bus Request This pin is used to request control of the system bus in preparation for a DMA transfer This pin is internally synchronized to SBCLK H System bus not requested L System bus requested System Interrupt Acknowledge This signal is from the host processor to acknowledge the interrupt request from the TMS380C26 H System interrupt not acknowledged see Note 1 L System interrupt acknowledged the TMS380C26 places its interrupt vector onto the system bus System Intel Motorola Mode Select The value on this pin specifies the system interface mode Intel compatible interface mode selected Motorola compatible interface mode selected Motorola interface mode is always 16 bits System Interrupt Request TMS380C26 activates this output to signal an interrupt request to the host processor SINTR SIRQ H No interrupt request L Interrupt request by TMS380C26 System Bus Owned This signal indicates to external devices that TMS380C26 has control of the system bus This signal drives the enable signal of the bus transceiver chips w
66. e tester pin electronics which are used to verify timing parameters of TMS380C26 output signals Tester Pin Electronics Output VLOAD Under Test Where loj 2 0 mA DC level verification all outputs 400 all outputs VLOAD 1 5 V typical DC level verification 0 7 V typical timing verification 65 pF typical load circuit capacitance Figure 4 Test Load Circuit TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 31 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION Reference 4 Periods 8 Periods 12 Periods 16 Periods 20 Periods When CLKDIV 1 OSCOUT Y N mekt FON t The MBCLK1 and 2 signals have no timing relationship to the OSCOUT signal MBCLK1 and MBCLK signals can start on any OSCIN rising edge depending on when the memory cycle starts execution Figure 5 Clock Waveforms After Clock Stabilization TEXAS 49 INSTRUMENTS 32 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION timing parameters The timing parameters for all the pins of TMS380C26 are shown in the following tables and are illustrated in the accompanying figures The purpose of these figures and tables is to quantify the timing relationships among
67. ect Input Output DIO or Pseudo Direct Memory Access DMA or PDMA is used to transfer all data to from host memory from to local memory DIO s main uses are for loading the software to local memory and for initializing the TMS380C26 DIO also allows command status interrupts to occur to and from the TMS380C26 The system interface can be hardware selected for either of two modes by use of the SIM pin The mode selected determines the memory organizations and control signals used These modes are The Intel 80x8x families 8 16 and 32 bit bus members Motorola 68000 microprocessor family 16 and 32 bit bus members The system interface supports host system memory addressing up to 32 bits 32 bit reach into the host system memory This allows greater flexibility in using accessing host system memory System designers are allowed to customize the system interface to their particular bus by Programmable burst transfers or cycle steal operations Optional parity protection These features are implemented in hardware to reduce system overhead facilitate automatic rearbitration of the bus after a burst or repeat a cycle when errors occur parity or bus Bus retries are also supported The system interface hardware also includes features to enhance the integrity of the TMS380C26 and the data These features do the following e Always internally maintain odd byte parity regardless if parity is disable
68. etup of SADHO SADH7 SADLO SADLT SPH and SPL vaid vetore s Delay from SCS SUDS SLDS high to SADHO SADH7 SADLO SADL7 SPH and SPL 2611 S 35 ns high impedance see Note 21 Hod of ouput ater SUDS or SDS erger ow ee Noea o 268 of register adress valid after SUDS or SLDS no ongerlow 2 Delay from SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately fol 2761 4000 ns lowing access to the SIF 2791 Delay from SUDS SLDS high to SDTACK high impedance Delay from SDBEN low to SDTACK low 282R Delay from SUDS or SLDS low to SDBEN low see TMS380 Second Generation Token Ring User s 55 Guide SPWU005 subsection 3 4 1 1 1 provided the previous cycle completed 283R Delay from SUDS SLDS high to SDBEN high see Note 21 Pulse duration SUDS or SLDS high between DIO accesses see Note 21 t This specification is provided as an aid to board design t This specification has been characterized to meet stated value 2 NOTES 21 The inactive chip select is SIACK in DIO read and DIO write cycles and SCS is the inactive chip select in interrupt acknowledge cycles 22 In 80x8x mode SRAS may be used to strobe the values of SBHE SRSX SRS0 SRS2 and SCS When used to do so SRAS must meet parameter 266a and SBHE SRS0 SRS2 and SCS must meet parameter 264 If SRAS is
69. f DMA size from SRESET high Intel mode only t This specification is provided as an aid to board design ti parameter 101 or 102 cannot be met parameter 117 must be extended by the larger difference real value of parameter 101 or 102 minus the max value listed NOTE 12 If OSCIN is used to generate PXTALIN the specification for the tolerance of OSCIN is equal to 0 01 TEXAS 49 INSTRUMENTS 34 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 100 Minimun Vpp High Level VDD 103 106 lt 106 lt 105 QQ N NY N 107 le 102 4 y i108 e 110 OSCIN NZ NZ NZ NZ NZ NZ NZ 110 4 109 MBCLK1 LR 7 UT k 111 5 NO 118 117 gt 119 5 SRESET N 288 2 _ _ uoo S8 SHALT NOTE A Inorderto represent the information on one figure non actual phase and timebase characteristics are shown Please refer to specified parameters for precise information Figure 6 Power Up SBCLK OSCIN MBCLK1 MBCLK2 SYNCIN and SRESET Timing TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 35 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A
70. ficant bit is SADH7 Address Multiplexing T Bits 31 24 and bits 15 8 Data Multiplexing T Bits 15 8 System Address Data Bus low byte see Note 1 These lines make up the least significant byte of each address word 32 bit address bus and data word 16 bit data bus The most significant bit is SADLO and the least significant bit is SADL7 Address Multiplexing T Bits 23 16 and bits 7 0 Data Multiplexing T Bits 7 0 System Address Latch Enable This is the enable pulse used to externally latch the 16 LSBs of the address from the SADHO SADH7 and SADLO SADL7 buses at the start of the DMA cycle Systems that implement address parity can also externally latch the parity bits SPH and SPL for the latched address System Bus Busy The TMS380C26 samples the value on this pin during arbitration The sample has one of 2 two values see Note 1 IN H Not busy The TMS380C26 may become Bus Master if the grant condition is met L Busy The TMS380C26 cannot become Bus Master System Bus Clock The 380 26 requires the external clock to synchronize its bus timings for SBCLK all DMA transfers System Read Not Write This pin serves as a control signal to indicate a read or write cycle Read Cycle see Note 1 Write Cycle System Bus Release This pin indicates to the TMS380C26 that a higher priority device requires the system bus The value on this pin is ignored when the TMS380C26 is NOT perfoming
71. he cycle time of one eighth of a local memory cycle 31 25 ns minimum uwr Delay from status bit 7 high to XMATCH and XFAIL recognized Pulse duration of XMATCH or XFAIL high NABI 220 KKB 127 gt 4 128 gt b __ NA Figure 18 XMATCH and XFAIL Timing TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 53 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION token ring ring interface timing No PARAMETER UNIT 153 Period of RCLK see Note 14 16 31 25 4 Mbps nominal 62 5 ns ns 154L Pulse duration of RCLK low 2 4 Mbps nominal 62 5 ns ns 154H Pulse duration of RCLK high Setup of RCVR valid before rising edge 1 8 V of RCLK at 16 Mbps Hold of RCVR valid after rising edge 1 8 V of RCLK at 16 Mbps s 158L Pulse duration of ring baud clock low B s 158H Pulse duration of ring baud clock high 165 Period of OSCOUT and PXTALIN see Note 14 16 Mbps for PXTALIN only 31 25 Tolerance of PXTALIN input frequency see Note 14 NOTE 14 This parameter is not tested but is required by the IEEE 802 5 specification 153 154H 4 4 1541 ied 155 0 158H 4 pl 158L _ N X Z N Sf PXTALIN
72. hich drive the address and bus control signals H TMS380C26 does not have control of the system bus L TMS380C26 has control of the system bus System Parity High The optional odd parity bit for each address or data byte transmitted over SADHO SADH7 see Note 1 System Parity Low The optional odd parity bit for each address or data byte transmitted over SADLO SADL7 see Note 1 Sytem Memory Address Strobe see Note 3 This pin is an active low address strobe that is an input during DIO although ignored as an address strobe and an output during DMA SRAS SAS H Address not valid L Address is valid and a transfer operation is in progress NOTES 1 Pin has internal pullup device to maintain a high voltage level when left unconnected no etch or loads 3 Pin should be tied to with a 4 7 kO pullup resistor TEXAS 49 INSTRUMENTS 14 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued System Interface Motorola Mode SI M L Upper Data Strobe see Note 3 This pin serves as the active low upper data strobe This pin is an input during DIO and an output during DMA H Not valid data on SADHO SADH7 lines L Valid data on SADHO SADH7 lines System Data Transfer Acknowledge see Note 3 The purpopse of this signal is to indicate to the bus master that a data transfer is complete This signal
73. id only for microcode release 2 x TEXAS 49 INSTRUMENTS 24 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 User Access Hardware Registers 808x 16 Bit Mode SI M 1 S8 SHALT 0 t Word Transfers SBHE 0 Byte Transfers SRS2 1 Normal Mode Pseudo DMA Mode Active SBHE 0 SBHE 0 SRS2 0 5 52 0 SBHE 1 SBHE 1 SRS2 0 SRS2 0 SBHE 0 SRS2 1 SRSX 5850 5 51 SRSO SRS1 SIFDAT MSB SIFDAT LSB SDMADAT SIFDAT INC MSB SIFADR MSB SIFCMD SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB t SBHE 1 and SRS2 1 is not defined 808x 8 Bit Mode SI M 1 S8 SHALT 1 SRSX SRSO mox eh m m COO CO thot oh C 68xxx Mode SI M 0 Word Transfers ByteTransters ByteTransters 000 SRSX SRSO SRS1 t 68xxx Mode is always 16 bit SRS1 k Gk GO k ak y 5 y CY k 00 SIFDAT INC LSB SIFADR LSB SIFSTS SIFACL LSB SIFADR LSB SIFADX LSB DMALEN LSB SIFDAT LSB SIFDAT MSB SIFDAT INC LSB SIFDAT INC MSB SIFADR LSB SIFADR MSB SIFSTS SIFCMD SIFACL LSB SIFACL MSB SIFADR LSB SIFADR MSB SIFADX LSB SIFADX MSB DMALEN LSB DMALEN MSB Normal Mode SIFDAT MSB SIFDAT INC MSB SIFADR MSB SIFCMD SIFACL MSB SIFADR MSB SIFADX MSB DMALEN MSB SIFDAT LSB SIFDAT INC LSB SI
74. ing edge of SBCLK following the T4 state of the last system bus transfer it controls In 68xxx mode the system PARAMETER MEASUREMENT INFORMATION SIF Master T2 T3 SIF T4 Bus Exchange n 12 N Z N Z N Z N Z N Z N interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls Figure 43 68xxx Mode Bus Arbitration Timing SIF Returns Control HI Z HI Z User T1 661 HOUVIN Q3SIA3H 666 TIHd V VO LOSMdS dOSS390ddININO9 MYOMLAN 922086511 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus release and error timing Setup of asynchronous input before SBCLK no longer high to guarantee recognition 208b Hold of asynchronous input SBRLS SOWN SBERR after SBCLK low to guarantee recognition Hold of SBRLS low after SOWN high Setup of SBERR low before SDTACK no longer high if parameter 208a not met 6 TWor2 T3 T4 1 2 208a gt SBRLS k 208b see Note A SOWN I 208b Tm 4 208c gt SBERR see Note B 4 236 5 SDTACK NOTES A The System Interface ignores the assertion of SBRLS if it does not own the system bus If it does own the bus then when it detects the assertion of SBRLS it will complete any internally started DMA cycle and relinquish control of the bus If n
75. ingle chip network communications processor commprocessor that supports token ring or Ethernet Local Area Networks LANs Either token ring at data rates of 16 Mbps or 4 Mbps or Ethernet at a data rate of 10 Mbps can be selected A flexible configuration scheme allows network type and speed to be configured by hardware or software This allows the design of LAN subsystems which support both token ring and Ethernet networks by electrically or physically switched network front end circuits The TMS380C26 conforms to IEEE 802 5 1989 standards and has been verified to be completely IBM Token Ring compatible By integrating the essential control building blocks needed on a LAN subsystem card into one device the TMS380C26 can ensure that this IBM compatability is maintained in silicon The TMS380C26 conforms to ISO IEC 8802 3 ANSI IEEE Std 802 3 CSMA CD standards and the Ethernet Blue Book standard The high degree of integration of the TMS380C26 makes it a virtual LAN subsystem on a single chip Protocol handling host system interfacing memory interfacing and communications processing are all provided through the 380 26 To complete LAN subsystem design only the network interface hardware local memory and minimal additional components such as PALs and crystal oscillators need to be added The TMS380C26 provides a 32 bit system memory address reach with a high speed bus master DMA interface that supports rapid communications with
76. internal bus OSCIN should be 64 a MHz signal see Note 5 Oscillator Output With OSCIN at 64 MHz and CLKDIV pulled high this pin provides an 8 MHz output which can be used by TMS3054 for 4 Mbps operation without the need for an additional crystal 18 15 02 99 05 14 15 07 96 CLKDIV OSCOUT L Reserved Reserved H OSCIN 8 if OSCIN 64 MHz then OSCOUT 8 MHz TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 7 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued wwe o Parity Enable The value on this pin is loaded into the PEN bit of the SIFACL register at reset i e when the SRESET pin is asserted or the ARESET bit in the SIFACL register is set to form a default PRTYEN value This bit enables parity checking for the local memory Local memory data bus checked for parity see Note 1 L Local memory data bus NOT checked for parity Network Selection Outputs These output signals are controlled by the host through the corresponding bits of the SIFACTL register The value of these bits signals can only be changed while the 380 26 is reset NSELOUTO NSELOUT1 NSELOUTO NSELOUT1 Description Reserved 16 Mbps token ring Ethernet 802 3 Blue Book 4 Mbps token ring NOTE 1 Pin has an internal pullup device to maintain a high voltage level when left unconnected no etch or loads TEXAS 49 INSTRUM
77. ion SIACK low on first pulse of two pulses NOTE 21 The inactive chip select is SIACK in DIO read and DIO write cycles and SCS is the inactive chip select in interrupt acknowledge cycles SIACK First Second Figure 30 80x8x Interrupt Acknowledge Timing First SIACK Pulse 80x8x interrupt acknowledge timing second SIACK pulse UNT 2507 Hod or SAD high impedance ater SASK 200 Setup of ouput datavaldbefore 8808 Sd 26 Hod of output deta vaid ater SACK high 2 Delay from SRDY low in the first DIO access to the SIF register to SRDY low in the immediately 2761 4000 ns following access to the SIF 279t Delay from SIACK high to SRDY high impedance Delay from SDBEN low to SRDY low in a read cycle Delay from SIACK low to SDBEN low see 7 5380 Second Generation Token Ring User s Guide SPWU005 subsection 3 4 1 1 1 provided previous cycle completed 283R Delay from SIACK high to SDBEN high see Note 21 t This specification is provided as an aid to board design t This specification has been characterized to meet stated value NOTE 21 The inactive chip select is SIACK in DIO read and DIO write cycles and SCS is the inactive chip select in interrupt acknowledge cycles TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 65 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER
78. is table describes the pointers for release 1 00 and 2 x of the TMS380C26 software t This address valid only for microcode release 2 x TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 23 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Adapter Internal Pointers for Ethernett 00 FFF8t Software raw microcode level in chapter 0 00 FFFAt Pointer to starting location of copyright notices Copyright notices are separated by a gt 0A character and terminated by gt 00 character in chapter 0 gt 01 0A00 Pointer to burned in address in chapter 1 gt 01 0A02 Pointer to software level in chapter 1 gt 01 0A04 Pointer to TMS380C26 addresses in chapter 1 Pointer 0 node address Pointer 6 group address Pointer 10 functional address Pointer to MAC buffer a special buffer used by the software to transmit adapter generated MAC frames in chapter 1 Pointer to LLC counters in chapter 1 Pointer 0 MAX SAPs Pointer 1 open SAPs Pointer 2 MAX STATIONs Pointer 3 open stations Pointer 4 available stations Pointer 5 reserved gt 01 0A0C Pointer to 4 16 Mbps word flag If zero then 4 Mbps If nonzero then the adapter is set to run at 16 Mbps data rate gt 01 0A0E Pointer to total TMS380C26 RAM found in Kbytes in RAM allocation test in chapter 1 t This table describes the pointers for release 1 00 and 2 x of the TMS380C26 software t This address val
79. l mode and the inverse of the SHRQ SBRQ pin when in Motorola mode This enables the host to easily determine if a pseudo DMA transfer is requested INTEL MODE SI M pin H MOTOROLA MODE SI M pin L 0 System bus not requested System bus not requested 1 System bus requested System bus requested PSDMAEN Pseudo System DMA Enable This bit enables pseudo DMA operation 0 Normal bus master DMA operation possible 1 Pseudo DMA operation selected Operation dependent on the values of the SWHLDA and SWHRQ bits in the SIFACL register ARESET Adapter Reset This bitis a hardware reset of the TMS380C26 This bit has the same effect as the SRESET pin except that the DIO interface to the SIFACL register is maintained This bit will be set to one if a clock failure is detected OSCIN PXTALIN RCLK or SBCLK not valid 0 The TMS380C26 operates normally 1 TheTMS380C26 is held in the reset condition CPHALT Communications Processor Halt This bit prevents the TMS380C26 s processor from accessing the internal TMS380C26 buses This prevents the TMS380C26 from executing instructions before the microcode has been downloaded 0 5380 26 processor can access the internal TMS380C26 buses 1 The TMS380C26 s processor is prevented from accessing the internal adapter buses BOOT Bootstrap CP Code This bit indicates whether the memory in chapters 0 and 31 of the local memory space is RAM or ROM PROM EPROM
80. nous signal SRDY after SBCLK low to guarantee recognition on this cycle m Delay from SBCLK low to address valid re Delay from SBCLK low in T1 cycle to SADHO SADH7 SADLO SADL7 SPH and SPL high im pedance E ELI 217 Delay SBCL to SXAL TXodewSAE wg eT ade zs Hold of SADHO SADH7 SADLO SADLT SPH and SPL vald after SALE or SKALTow wong 5 zi Dea rom SBCLK ow n Ta SAD gh 7 E n 225A Delay rom 2257 pey SPH Os 227A Delay rom S6CLKioninT2oyoetoSRDOw PSS 529 Hold of SADHO SADH7 SADLO SADL7 SPH and SPL high impedance after SBCLK low in NEC HEFT T1 cycle 231 Pulse duration SRD low 2tc SCK 30 ons Setup of SADHO SADH7 SADLO SADL7 SPH and SPL valid before SALE SXAL no longer 233 tw SCKL 15 ns 237R Delay from SBCLK high in the T2 cyle to SDBEN low Setup of data valid before SRDY low if parameter 208a not met om t This specification has been characterized to meet stated value NOTE 23 While the system interface DMA controls are active i e SOWN is asserted the SCS input is disabled TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 69 77251 1443 04 10077 SVXAL 391430 1804 SINAWNALSN SYEL SBCLK SRAS see Note B SRD see Note A SXAL T4
81. o DMA transfer has internally started then the System Interface will release the bus before starting another B If SBERR is asserted when the System Interface controls the system bus then the current bus transfer is completed regardless of the value of SDTACK If the BERETRY register is non zero the cycle will be retried If the BERETRY register is zero the System Interface will then release control of the system bus The System Interface ignores the assertion of SBERR if it is not performing a DMA bus cycle on the system bus When SBERR is properly asserted and BERETRY is zero however the System Interface releases the bus upon completion of the current bus transfer and halts all further DMA on the system side The error is synchronized to the local bus and DMA stops on the local sides The value of the SDMAADR SDMADDRX and SDMALEN registers in the System Interface are not defined after a system bus error C In cycle steal mode state TX is present on every system bus transfer In burst mode state TX is present on the first bus transfer and whenever the increment of the DMA Address Register carries beyond the least significant 16 bits D SDTACK is not sampled to verify that it is deasserted E Unless otherwise specified for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid the signal is also specified to hold its previous value including high impedance until the start of that SBCLK transition
82. oltage OSCINT RCLK PXTALIN RCVR OSCINt All other High level output current IOL Low level output current see Note 9 TA Operating free air temperature t The minimum level specified is a result of the manufacturing test environment This signal has been characterized to a minimum level of 2 4 V over the full temperature range t The maximum level specified is a result of the manufacturing test environment This signal has been characterized to a maximum level of 0 8 V over the full temperature range NOTES 7 All pins should be routed to minimize inductance to system ground 8 The algebraic convention where the more negative less positive limit is designated as a minimum is used in this data sheet for logic voltage levels only 9 Outputcurrent of 2 mA is sufficientto drive five low power Schottky TTL loads or ten advanced low power Schottky TTL loads worst case VIL Low level input voltage TTL level signal see Note 8 electrical characteristics over full ranges of recommended operating conditions unless otherwise noted TEST CONDITIONS PARAMETER see Note 10 UNIT VoH High level output voltage TTL level signal see Note 11 VDD min max VoL Low level output voltage TTL level signal Vpp min loj max Vpp max Vo 2 4 V lo High impedance output current VDD max Vo 0 4 V IDD Input current any input or input output pin V Vss to Vpp Supply current Vpp max 220 Ci Input
83. on this pin is output synchronously to the transmit clock TXC It is normally connected to the TXD pin of an Ethernet Serial Network Interface SNI chip Loopback This enables loopback of Ethernet transmit data through the Ethernet SNI device to recieve data H Wrap through the front end device L Normal operation Ethernet Transmit Clock A 10 MHz clock input used to synchronize transmit data from the TMS380C26to the Ethernet physical layer circuitry This is a continuously running clock It is normally connected to the TXC output pin of an Ethernet SNI chip see Note 5 Ethernet Receive Clock A 10 MHz clock input used to synchronize received data from the Ethernet physical layer circuitry to the TMS380C26 This clock must be present whenever the CRS signal is active although it can be held low for a maximum of 16 clock cycles after the rising edge of CRS When the CRS signal is inactive it is permissable to hold this clock in a low phase It is normally connected to the RXC output pin of an Ethernet Serial Network Interface SNI chip The TMS380C26 requires this pin to be maintained in the low state when CRS is not asserted see Note 5 Ethernet Carrier Sense This input signal indicates to the TMS380C26 that the Ethernet physical layer circuitry has network data present on the RXD pin This signal is asserted high when the first bit of the frame is received and is deasserted after the last bit of the frame is received H Receiving da
84. release control of the system bus The System Interface ignores the assertion of SBERR if it is not performing a DMA bus cycle on the system bus When SBERR is properly asserted and BERETRY is zero however the System Interface releases the bus upon completion of the current bus transfer and halts all further DMA on the system side The error is synchronized to the local bus and DMA stops on the local sides The value of the SDMAADR SDMADDRX and SDMALEN registers in the System Interface are not defined after a system bus error C In cycle steal mode state TX is present on every system bus transfer In burst mode state TX is present on the first bus transfer and whenever the increment of the DMA Address Register carries beyond the least significant 16 bits D SDTACK is not sampled to verify that it is deasserted E Unless otherwise specified for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid the signal is also specified to hold its previous value including high impedance until the start of that SBCLK transition Figure 36 80x8x Mode Bus Release Timing TEXAS 49 INSTRUMENTS 74 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx DIO read timing uwr 2507 Hod of SAD righ impedance ater SUDS or 260 S
85. ry address bits 4 and to A6 and for the third and fourth quarters they carry data bits 8 to 15 The most significant bit is MADLO and the least significant bit is MADL7 Memory Cycle 10 2Q 3Q 4Q A7 A14 AX4 A0 A6 D8 D15 08 015 Memory Address Latch This is a strobe signal for sampling the address at the start of the memory cycle it is used by SRAMs and EPROMs The full 20 bit word address is valid on MAX2 MAXPL MADHO MADH7 and MADLO MADL7 Three 8 bit transparent latches can therefore be used to retain a 20 bit static address throughout the cycle Rising edge No signal latching Falling edge Allows the above address signals to be latched Local Memory Extended Address Bit This signal drives at ROW address time and it drives A12 at COL address and DATA time for all cycles This signal can be latched by MRAS Driving A12 eases interfacing to a BIA ROM Memory Cycle 1Q 2Q 3Q 4Q 12 12 12 Local Memory Extended Address Bit This signal drives AX2 at ROW address time which can be latched by MRAS and A14 at COL address and DATA time for all cycles Driving A14 eases interfacing to a BIA ROM Memory Cycle 19 49 2 14 14 14 Pin has internal pullup device to maintain a high voltage level when unconnected no etch or loads Pin should be connected to ground 1 2 3 Pin should be tied to with a 4 7 kO pullup resistor 4 Each pin mus
86. s System Extended Address Latch This output provides the enable pulse used to externally latch the most significant 16 bits of the 32 bit system address during DMA SXAL is activated prior to the first cycle of each block DMA transfer and thereafter as necessary whenever an increment of the DMA address counter causes a carry out of the lower 16 bits Systems that implement parity on addresses can use SXAL to externally latch the parity bits available on SPL and SPH for the DMA address extension Reserved This signal must be left unconnected see Note 1 System Halt Bus Error Retry If this signal is asserted along with bus errror SBERR the adapter will retry the last DMA cycle This is the re run operation as defined in the 68000 specification The BERETRY counter is not decremented by SBERR when SHALT is asserted See Section 3 4 5 3 of the TMS380 Second Generation Token Ring User s Guide SPWUOO5 for more information NOTES 1 Pin has internal pullup device to maintain a high voltage level when left unconnected no etch or loads 3 Pin should be tied to Vcc with 4 7 kQ pullup resistor TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 15 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued Network Media Interface Token Ring Mode TEST1 H TEST2 H Differential Driver Data Output These pins are the differential outputs that
87. sed to select the network speed and type to be used by the TMS380C26 These inputs should only be changed during adapter reset TESTO TESTI TEST2 Description Reserved 16 Mbps token ring Ethernet 802 3 Blue Book 4 Mbps token ring Reserved Test Pin Inputs These pins should be left unconnected see Note 1 Module in Place test mode is achieved by tying TEST 3 and TEST 4 pins to ground In this mode all TMS380C26 output pins are high impedance Internal pullups on all TMS380C26 inputs will be disabled except TEST3 TEST5 pins External Fail to Match signal An enhanced address copy option EACO device uses this signal to indicate to the TMS380C26 that it should not copy the frame nor set the ARI FCI in bits in a token ring frame due to an external address match The ARI FCI bits in a token ring frame may be set due to an internal address matched frame If an enhanced address copy option EACO device is NOT XFAIL 80 used then this pin must be left unconnected This pin is ignored when CAF mode is enabled See table given below in XMATCH pin description see Note 1 76 75 74 H No address match by external address checker L External address checker armed state External Match signal An enhanced address copy option EACO device uses this signal to indicate to the TMS380C26 to copy the frame and set the ARI FCI bits in a token ring frame If an enhanced address copy option EACO device is NOT used then this pin must be left
88. ss Pointer to TMS380C26 parameters in chapter 1 Pointer 0 physical drop number Pointer 4 upstream neighbor address Pointer 10 upstream physical drop number Pointer 14 last ring poll address Pointer 20 reserved Pointer 22 transmit access priority Pointer 24 source class authorization Pointer 26 last attention code Pointer 28 source address of the last received frame Pointer 34 last beacon type Pointer 36 last major vector Pointer 38 ring status Pointer 40 soft error timer value Pointer 42 ring interface error counter Pointer 44 local ring number Pointer 46 monitor error code Pointer 48 last beacon transmit type Pointer 50 last beacon receive type Pointer 52 last MAC frame correlator Pointer 54 last beaconing station UNA Pointer 60 reserved Pointer 64 last beaconing station physical drop number gt 01 0A08 Pointer to MAC buffer a special buffer used by the software to transmit adapter generated MAC frames in chapter 1 gt 01 0A0A Pointer to LLC counters in chapter 1 Pointer MAX SAPs Pointer 1 open SAPs Pointer 2 MAX_STATIONs Pointer 3 open stations Pointer 4 available stations Pointer 5 reserved gt 01 0A0C Pointer to 4 16 Mbps word flag If zero then 4 Mbps If nonzero then the adapter is set to run at 16 Mbps data rate gt 01 0A0E Pointer to total TMS380C26 RAM found in Kbytes in RAM allocation test in chapter 1 t Th
89. ss extension NOTES 1 Pinhasan internal pullup device to maintain a high voltage level when left unconnected no etch or loads 3 Pin should be tied to with a 4 7 kO pullup resistor TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 11 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued System Interface Intel Mode SI M H 108 Reserved This signal must be left unconnected see Note 1 System 8 16 bit bus select This pin selects the bus width used for communications through the system interface On the rising edge of SRESET the TMS380C26 latches the DMA bus width S8 SHALT otherwise the value on this pin dynamically selects the DIO bus width H Selects 8 bit mode see Note 1 L Selects 16 bit mode NOTE 1 Pin has an internal pullup device to maintain a high voltage level when left unconnected no etch or loads TEXAS 49 INSTRUMENTS 12 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued System Interface Motorola Mode SI M L vo System Address Data Bus high byte see Note 1 These lines make up the most significant byte of each address word 32 bit address bus and data word 16 bit data bus The most significant bit is SADHO and the least signi
90. system bus transfer it controls 221 B While the system interface DMA controls are active i e SOWN is asserted the SCS input is disabled Figure 35 80x8x Mode Bus Arbitration Timing SIF Returns Control TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 73 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus release timing Setup of asynchronous input SBRLS low before SBCLK no longer high to guarantee recognition 208b Hold of asynchronous input SBRLS low after SBCLK low to guarantee recognition Hold of SBRLS low after SOWN high m TWor2 T3 T4 T1 T2 SBCIK FN CCC VTS 27 22 208 SBRLS p Mh 2085 see Note SOWN ke 208 NOTES A The System Interface ignores the assertion of SBRLS if it does not own the system bus If it does own the bus then when it detects the assertion of SBRLS it will complete any internally started DMA cycle and relinquish control of the bus If no DMA transfer has internally started then the System Interface will release the bus before starting another B If SBERR is asserted when the System Interface controls the system bus then the current bus transfer is completed regardless of the value of SRDY If the BERETRY register is non zero the cycle will be retried If the BERETRY register is zero the System Interface will then
91. t be individually tied to with 1 0 kQ pullup resistor TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 5 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued wwe WO mew Local Memory Extended Address and Parity High Byte For the first quarter of a memory cycle this signal carries the extended address bit AX1 for the second quarter of a memory cycle this signal carries the extended address bit and for the last half of the memory cyle this signal carries the parity bit for the high data byte Memory Cycle 1Q 2Q 3Q 4Q AX1 Parity Parity Local Memory Extended Address and Parity Low Byte For the first quarter of a memory cycle this signal carries the extended address bit AX3 for the second quarter of a memory cycle this signal carries extended address bit AX2 and for the last half of the memory cycle this signal carries the parity bit for the low data byte Memory Cycle 1Q 2Q 3Q 4Q Signal 2 Parity Local Bus Clock1 and local Bus Clock 2 These signals are referenced for all local bus transfers MBCLK1 MBCLK2 lags MBCLK1 by a quarter of a cycle These clocks operate at 8 MHz for a 64 MHz OSCIN MBCLK2 and 6 MHz for a 48 MHz OSCIN which is twice the memory cycle rate The MBCLK signals are always a divide by 8 of the OSCIN frequency Buffer Enable This signal enables th
92. ta L No data on network REDY CRS WFLT COLL WRAP TXEN H Data line currently contains data to be transmitted L No valid data on TXEN NOTE 5 Pin has an expanded input voltage specification Ethernet Collision Detect This input signal indicates to the TMS380C26 that the Ethernet physical layer circuitry has detected a network collision This signal must be present for at least two TXC clock cycles to ensure it is accepted by the TMS380C26 It is normally connected to the COLL pin of an Ethernet SNI chip This signal can also be an indication of the SQE test signal H COLL detected by the SNI device L Normal operation Ethernet Transmit Enable This output signal indicates to the Ethernet physical layer circuitry that bit rate data is present on the TXD pin This signal is output synchronously to the transmit clock TXC It is normally connected to the pin of an Ethernet chip Ethernet Received Data This input signal provides the TMS380C26 with bit rate network data from RCVR RXD the Ethernet front end device Data on this pin must be synchronous with the receive clock RXC It is normally connected to the RXD pin of an Ethernet SNI chip see Note 5 TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 17 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued No 10 Network Select inputs These pins are u
93. ter is set or the SRESET pin is asserted This signal is used for resetting external local bus glue External logic not reset External logic reset ui ROM Enable During the first 5 16 of the memory cycle this signal is used to provide a chip select for ROMs when the BOOT bit of the SIFACL register is zero i e when code is resident in ROM not It can be latched by MAL It goes low for any read from addresses 200 0010 gt 00 FFFF or 1F 0000 gt 1F FFFF when the Boot bit in the SIFACL register is zero It stays high for writes to these addresses accesses of other addresses or accesses of any address when the BOOT bit is one OUT During the final three quarters of the memory cycle it outputs the A13 address signal for interfacing to a BIA ROM This means MBIAEN ROMEN and MAX together form a glueless interface for the BIA ROM H ROM disabled L ROM enabled Local Memory Write This signal is used to specify a write cycle on the local memory bus The data on the MADHO MADH7 and MADLO MADL7 buses is valid while MW is low DRAMs latch data on the falling edge MW while SRAMs latch data on the rising edge of MW MOE OSCOUT NOTE 5 Pin has an expanded input voltage specification H Not a local memory write cycle L Local memory write cycle Non Maskable Interrupt Request This pin must be left unconnected External Oscillator Input This line provides the clock frequency to the TMS380C26 for a 4 MHz
94. the various signals The parameters are numbered for convenience static signals The following table lists signals that are not allowed to change dynamically and therefore have no timing associated with them They should be strapped high or low as required Host processor select Intel Motorola Default bootstrap mode RAM ROM Default parity select enabled disabled 1 For unit in place test timing parameter symbology Timing parameter symbols have been created in accordance with JEDEC standard 100 In order to shorten the symbols some of the pin names and other related terminology have been abbreviated as shown below DR DRVR RS SRESET DRN DRVR VDD VDDB OSC OSCIN SCK SBCLK Lower case subscripts are defined as follows cycle time r rise time d delay time sk skew h hold time su setup time w pulse duration width t transition time The following additional letters and phrases are defined as follows H High 2 High impedance L Low Falling edge No longer high V Valid Rising edge No longer low TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 33 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION power up SBCLK OSCIN MBCLK1 MBCLK2 SYNCIN and SRESET timing 05 Cycle time of OSCIN see Note 12 tsu RST Setup time of DMA size to SRESET high Intel mode only th RST Hold time o
95. to disable MCAS with MREF during the refresh cycle Data Direction This signal is used as a direction control for bidirectional bus drivers The signal becomes valid before MBEN active H TMS380C26 memory bus write L TMS380C26 memory bus read NOTE 4 Each pin must be individually tied to Vcc with a 1 0 kQ pullup resistor TEXAS 49 INSTRUMENTS 6 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 TMS380C26 NETWORK COMMPROCESSOR SPWSO010A APRIL 1992 REVISED MARCH 1993 Terminal Functions continued Memory Output Enable This signal is used to enable the outputs of the DRAM memory during a read cycle This signal is high for EPROM or BIA ROM read cycles PINNAME Disable DRAM outputs L Enable DRAM outputs Row Address Strobe for DRAMs The row address lasts for the first 5 16 of the memory cycle This signal is driven low every memory cycle while the row address is valid on MADLO MADL7 MAXPH and MAXPL for both RAM and ROM cycles Itis also driven low during refresh cycles when the refresh address is valid on MADLO MADL7 1 MRAS 1 DRAM Refresh Cycle in Progress This signal is used to indicate that a DRAM refresh cycle is occurring It is also used for disabling MCAS to DRAMs that do not use a CAS before RAS refresh MREF 1 4 1 4 H DRAM refresh cycle in process L Nota DRAM refresh cycle Memory Bus Reset This is a reset signal generated when either the ARESET bit in the SIFACL regis
96. us on 80x8x Buses Optional Parity Checking Dual Port DMA and Direct I O Transfers to Host Bus Specification for External Adapter Bus Devices SEADs Supports External Hardware Interface for User Defined External Logic Enhanced Address Copy Option EACO Interface Supports External Address Checking Logic for Bridging or External Custom Applications Support for Module High Impedance In Circuit Testing Built in Real Time Error Detection Bring Up and Self Test Diagnostics With Loopback Automatic Frame Buffer Management Slow Clock Low Power Mode Single 5 V Supply 1 CMOS Technology 250 mA Typical Latch Up Immunity at 25 ESD Protection Exceeds 2 000 V 132 Pin JEDEC Plastic Quad Flat Package PQ Suffix Operating Temperature Range 0 C to 70 Transmit lt gt Attached Token Ring or To System TMS380C26 Ethernet Physical Network Bus Layer Circuitry Receive PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 1993 Texas Instruments Incorporated TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 1 77251 1443 5380 26 NETWORK COMMPROCESSOR SPWS010A APRIL 1992 REVISED MARCH 1993 pinout The pin assignments for TMS380C26 132 pin quad flat pack ar
97. used in soldered assembly 4 57 0 180 4 06 0 160 0 76 0 030 NOM 0 254 0 010 NOM 0 635 0 025 NOM gt T JEDEC NO OF A B OUTLINE TERMINALS MIN MAX MIN MAX MIN MAX MO 069 AD 100 22 28 0 877 22 43 0 883 18 97 0 747 19 13 0 753 15 16 0 597 15 32 0 603 MO 069 AE 132 27 36 1 077 27 50 1 083 24 05 0 947 24 21 0 953 20 24 0 797 20 40 0 803 ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES TEXAS 49 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 91 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems ne

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