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Texas Instruments MSP430x11x1 User's Manual

1. See Note 27 EE iE c opel J GND P2IN 5 Bus Keeper E gt e Module XIN p i NN LENT P2IRQ 5 Internal to Basic Clock Module Interrupt Edge P2IFG 5 Select e oq A Interrupt Flag P2IES 5 DCOR P2SEL 5 CAPD 5 NOTE DCOR Control bit from Basic Clock Module if it is set P2 5 Is disconnected from P2 5 pad Direction PnDIR x control from PnOUT x Module X OUT Module X IN PnIFG x PnIES x module Pasels P2DiRs papins p2ours vss _ Pans unused 2 5 pairas P2IEES5 NOTES 27 Optional selection of pullup or pulldown resistors with ROM masked versions 28 Fuses for optional pullup and pulldown resistors can only be programmed at the factory ROM versions only 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 41 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 APPLICATION INFORMATION Port P2 unbonded bits P2 6 and P2 7 P2SEL x P2DIR x 0 Input 1 Output Direction Control From Module P2OUT x Module X OUT P2IN x Node Is Reset With e SQ T r Bus Keeper Module X IN lt pi gt Bsp P2IRQ x Interrupt l Edge P2IFG x Select Interrupt P2SEL x NOTE x Bit identifier 6 to 7 fo
2. OFFFFh SegmentO0 w The flash memory consists of 512 byte segments OFEOOh interrupt Vectors in the main memory and 128 byte segments in the information memory See device memory maps OFCOOh Segmenti for specific device information OFBFFh Segment0 to Segment7 can be erased S individually or altogether as a group OF9FFh semen SegmentA and SegmentB can be erased orate E individually or as a group with segments 0 7 OF7FFh OF600h E The memory in SegmentA and SegmentB is also DESEE i called Information Memory OF400h Segments VPP is generated internally VCC current OF3FFh increases during programming 0F200h ema During program erase cycles VCC must not drop Segment below the minimum specified for program erase operation 010FFh s p 01080h SegmentA z E Program and erase timings are controlled by the 0107Fh EE flash timing generator no software intervention 01000h SegmentB ez is needed The input frequency of the flash timing generator should be in the proper range and must be applied until the write program or erase operation is completed NOTE All segments not implemented on all devices During program or erase no code can be executed from flash memory and all interrupts must be disabled by setting the GIE NMIE ACCVIE and OFIE bits to zero If a user program requires execution concurrent with a flash program or erase operation the program must be executed from mem
3. Read write access to all registers with all instructions 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 digital I O continued The seven registers are Input register 8 bits at port P1 P2 contains information at the pins Output register 8 bits at port P1 P2 contains output information Direction register 8 bits at port P1 P2 controls direction Interrupt edge select 8 bits at port P1 P2 input signal change necessary for interrupt Interrupt flags 8 bits at port P1 P2 indicates if interrupt s are pending Interrupt enable 8 bits at port P1 P2 contains interrupt enable bits Selection Port or Mod 8 bits at port 1 2 determines if pin s have port or module function All these registers contain eight bits Two interrupt vectors are implemented one commonly used for any interrupt event on ports P1 0 to P1 7 and one commonly used for any interrupt event on ports P2 0 to P2 7 NOTE Six bits of port P2 P2 0 to P2 5 are available on external pins but all control and data bits for port P2 are implemented watchdog timer The primary function of the watchdog timer WDT module is to perform a controlled system restart after a software problem has occurred If the selected time interval expires a system reset is generated If this watchdog function is not needed in an application the
4. low power consumption capabilities The various operating modes are controlled by the software through controlling the operation of the internal clock system This clock system provides many combinations of hardware and software capabilities to run the application with the lowest power consumption and with optimized system costs Use the internal clock DCO generator without any external components Select an external crystal or ceramic resonator for lowest frequency or cost Select and activate the proper clock signals LFXT1CLK and or DCOCLK and clock pre divider function Apply an external clock source Four of the control bits that influence the operation of the clock system and support fast turnon from low power operating modes are located in the status register SR The four bits that control the CPU and the system clock generator SCG1 SCGO OscOff and 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 status register R2 rw 0 9 15 8 7 6 5 4 3 2 1 0 Reserved For Future rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 The bits CPUOff SCG1 SCGO and OscOff are the most important low power control bits when the basic function of the system clock generator is established They are pushed onto the stack whenever an interrupt is accepted and thereby saved so that the previous
5. 3 for port P1 P1Se Xx P1SEL x Direction PnDIR x control from PnOUT x Module X OUT PnIN x Module X IN PnIE x PnIFG x PnIES x module VS 1 i P1DIR 1 P1DIR 1 P1OUT 1 Outo signalt P1IN 1 CCIOAT P1IE 1 P1IFG 1 P1IES 1 t Signa from or to Timer A NOTES 27 Optional selection of pullup or pulldown resistors with ROM masked versions 28 Fuses for optional pullup and pulldown resistors can only be programmed at the factory ROM versions only 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 37 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 APPLICATION INFORMATION Port P1 P1 4 to P1 7 input output with Schmitt trigger and in system access features P1SEL x i PIDIR x r gt See Note 27 Direction Control j lo From Module See Note 28 0 eo P10UT x Pad Logic 1 o o 1 4 1 7 Module X OUT See Note 28 L See Note 27 gt T _ j GND TST eS PAIN 1 Bus Keepe nam Lr Module X IN f lt e eel sl TEST P1IRQ x Interrupt Edge Typical Select GND Interrupt 4 use Flag PIES Contoliby JTAG 2 Blow NOTE Fuse not implemented P1SEL x Control in F11x1 EMEN Pix 3 TDO gt Controlled By JTAG a Controlled by JTAG p Lansa NOTE The test pin
6. Flag P2IES 3 P2SEL 3 CCHB Interrupt P2IES 4 P2SELA Flag 4 Interrupt P2IFG 4 Soc N P2IRQ 4 P2IE 4 Select Module X IN Bus Keeper P2IN 4 lt E 1 Vcc SS See Note 27 See Note 28 Module X OUT e 200 4 Pad Logic See Note 28 Direction Control From Module 1 Output L See Note 27 P2DIR 4 0 Input P2SEL 4 GND APPLICATION INFORMATION PnSel x PnDIR x Direction PnOUT x Module X OUT PnIN x Module XIN PnIE x PnIFG x PnIES x control from module P2Sel 3 P2DIR 3 P2DIR 3 P2OUT3 Outi signait P2IN 3 P2IE 3 P2IFG 3 P1IES 3 P2Sel 4 P2DIR 4 P2DIR 4 P20UT 4 Out2signalt P2IN 4 P2IE 4 P2IFG 4 P1IES 4 t Signal from Timer A NOTES 27 Optional selection of pullup or pulldown resistors with ROM masked versions 28 Fuses for optional pullup and pulldown resistors can only be programmed at the factory ROM versions only 35 TEXAS INSTRUMENTS 40 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 Port P2 P2 5 input output with Schmitt trigger and Rosc function for the Basic Clock module P2SEL 5 e dr cx ind we i 0 0 Input Pad Logic P2DIR 5 1 Output 54 See Note 27 Direction Control 1 From Module See Note 28 0 P20UT 5 Q P2 5 1 e gt Module X OUT IT See Note 28
7. The external capture signal triggers the capture event every time when the minimum cycles and time parameters met capture may be triggered with capture signals even shorter than tcap Both the cycle and timing specifications must be met to ensure a correct capture of the 16 bit timer value and to ensure the flag is set internal signals TAx SMCLK at Timer_A PARAMETER TEST CONDITIONS TYP UNIT f IN Input frequency Internal TAO TA1 TA2 ty tL IL ftTAint Timer A clock frequency Internally SMCLK signal applied 2 2 V 3 V Ji TEXAS INSTRUMENTS 30 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued outputs P1 x P2 x TAx PARAMETER TEST CONDITIONS VCC P2 0 ACLK 20 pF 2 2 V 3 V Output frequency TAO TA1 TA2 20 pF Internal clock source SMCLK signal applied see Note 16 fSMCLK fLEXT1 fxT1 40 5 1 fLEXT1 fLF f f 35 P1 4 SMCLK SMCLK LFXT1 LF 22 V 3 V 50 HIE pF fSMCLK LEXT1 n ieee Duty cycle of O P f 2f 22 V 3 V 50 frequency SMCLK DCOCLK 15ns 20 fLEXT1 XT1 40 CL 20 pF fP20 fLFXT1 2 2 V 33 V 30 fp20 fLEXT1 n TAdc TAO TA1 TA2 20pF Duty cyc
8. V V V 2 5 8 76 3 C 35 TEXAS INSTRUMENTS 26 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 recommended operating conditions continued MSP430x11x1 Devices 8 MHz at 3 6V 5 MHz at 2 2 V 2 MHz at system Maximum Processor Frequency MHz 0 1 2 3 4 Vcc Supply Voltage V NOTE Minimum processor frequency is defined by system clock Flash program or erase operations require a minimum Vcc of 2 7 V Figure 6 Frequency vs Supply Voltage 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 27 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted supply current into Vcc excluding external current f system 1 MHz PARAMETER TEST CONDITIONS MIN TYP UNIT TA 40 C 85 C 160 f MCLK f SMCLK 1 MHz 11 1 f ACLK 32 768 Hz TA 40 C 85 C f MCLK f SMCLK f ACLK 4096 Hz Active mode TA 40 C 85 C MCLK f SMCLK 1 MHz Fitxi f ACLK 32 768 Hz BE TA 40 C 85 C TA 40 C 85 C 11 1 f MCLK 0 f SMCLK 1 MHz Low power mode f ACLK 32 768 Hz LPMO TA 40 C 85 C Fllx1 f MCLK 0 f SMCLK 1 MHz f A
9. changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using Tl components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or s
10. enable cannot Nonmaskable neither the individual nor the general interrupt enable bit will disable an interrupt event EONA 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 special function registers Most interrupt and module enable bits are collected into the lowest address space Special function register bits that are not allocated to a functional purpose are not physically present in the device Simple software access is provided with this arrangement interrupt enable 1 and 2 Address 7 6 5 4 3 2 1 0 a Ae wm om we rw 0 rw 0 rw 0 rw 0 WDTIE Watchdog timer enable signal OFIE Oscillator fault enable signal NMIIE Nonmaskable interrupt enable signal ACCVIE Access violation at flash memory Address 7 6 5 4 3 2 1 0 interrupt flag register 1 and 2 Address 7 6 5 4 3 2 1 0 rw 0 rw 1 rw 0 WDTIFG Set on overflow or security key violation or Reset on Vcc power on or reset condition at RST NMI pin OFIFG Flag set on oscillator fault NMIIFG Set via RST NMI pin Address 7 6 5 4 3 2 1 0 Legend rw Bit can be read and written rw 0 Bit can be read and written It is reset by PUC SFR bit is not present in device 35 TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000
11. feature The capture flag finds the start of a character while the compare feature latches the input data stream bit by bit The software hardware interface connects the mixed signal controller to external devices systems or networks 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 21 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 Comparator A The primary function of the comparator module is to support precision A D slope conversion applications battery voltage supervision and observation of external analog signals The comparator is connected to port pins P2 3 CAO0 and to P2 4 CA1 It is controlled via twelve control bits in registers CACTL1 and CACTL2 OV Vcc 2 0 E CAF CAON 05 e Low Pass Filter CCHB P2 3 1 Lo cao 1 TA1 0 _ 0 Sar ope 95 ca 1o lo Q P CAOUT P24 oT Q CA1 1 2 Set CAIFG 0V Vcc OV Flag P2CA1 B t 2 0 us caon P22 4 CAOUT TAO 3 f 1 lo CAREF 05 0 5 x Vcc L 1 20 o L 0o o o 0 25 x Vcc VCAREF 3 0v Figure 5 Block Diagram of Comparator A W T EXAS INSTRUMENTS 22 POST OFFICE BOX 655303 DALLAS TEXAS 75265 Comparator A continued The con
12. masserase operation If the timing generator has completed the operation the BUSY bit is reset by the hardware No program code can be executed from the busy flash memory during the entire program or erase cycle 0 Flash memory is not busy 1 Flash memory is busy and remains in busy state if segment write function is in wait mode Key violation 0 Key OA5h high byte was not violated 1 Key OA5h high byte was violated Violation occurs when a write access to registers FCTL1 FCTL2 or FCTL3 is executed and the high byte is not equal to 0A5h If the security key is violated bit KEYV is set and a PUC is performed Access violation interrupt flag The access violation flag is set when any combination of control bits other than those shown in Table 3 is attempted or an instruction is fetched while a segment write operation is active Reading the control registers will not set the ACCVIFG bit NOTE The respective interrupt enable bit ACCVIE is located in the interrupt enable register IE1 in the special function register The software can set the ACCVIFG bit If set by software an NMI is also executed In the segment write mode the WAIT bitindicates that data has been written and the flash memory is prepared to receive the next data for programming The WAIT bit is read only but a write to the WAIT bit is allowed 0 The segment write operation has began and programming is in progress 1 The segment write operation is ac
13. 0 40 LTE satan f ome oa T 0 004 0 10 0 004 0 10 0 104 2 65 MAX 4040000 D 02 98 NOTES A Alllinear dimensions are in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JEDEC MS 013 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 43 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 MECHANICAL DATA PW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 14 PINS SHOWN 0 15 NOM Gage Plane L L L Em Seating Plane t 20 MAX 0 15 1 0 10 0 05 PINS DIM A MAX A MIN 4040064 F 01 97 NOTES A Alllinear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 153 om 35 TEXAS INSTRUMENTS 44 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make
14. 3V 0 08 0 13 0 16 E Voc 2 2V 0 14 0 19 0 23 f DCO13 DCOR 0 25 M Voc 23V 0 14 0 18 0 22 Voc 2 2 V 0 22 0 30 0 36 Voc 3V 0 22 0 28 0 34 Voc 2 2V 0 37 0 49 0 59 f DCO33 DCOR 0 MHz Voc 3V 0 37 0 47 0 56 Voc 22 2 V 0 61 0 77 0 93 Voc 23V 0 61 0 75 0 9 Voc 22V Voo 22V Voc 22V 2 4 2 9 3 4 Voc 3V 27 32 365 f 25 C Voc 22AN MH 25 2 DCO77 A Vec 3V 4 4 4 9 5 4 Fpco40 Fpco40 FDCO40 f DCO47 Voc 2 2 V 1 7 x2 1 2 5 S Rsel SR fRsel 1 Reel Voc 2 2 V 3 V 1 35 s zd S DCO Spco fpco 1 fpco Voc 2 2 V 3 V 1 07 1 12 1 16 Temperature drift 4 DCO 3 MOD 0 Voc 2 2V 0 31 0 36 0 40 see Note 21 Voc 3V 0 33 038 0 43 Drift with Vcc variation 4 DCO 3 MOD 0 _ S see Note 21 Voc 2 2 V 0 5 10 V NOTE 21 These parameters are not production tested f DC003 MOD 0 DCOR 0 25 C MHz Hz f DCO23 f DCO43 TA 25 C i i B I I N N n N B i I N MHz MHz f DCO73 DCOR 0 25 4 9 E N o BB g lt Max f DCOx7 iin 1 fDCOCLK x Frequency Variance Ma f DCOx0 Min 0 1 2 3 4 5 6 7 2 2V 3V Vcc DCO Steps Figure 13 DCO Characteristics 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 35 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 electrical characte
15. BOX 655303 DALLAS TEXAS 75265 33 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued Figure 11 Power On Reset POR vs Supply Voltage V POR V Temperature C Figure 12 V poR vs Temperature crystal oscillator LFXT1 PARAMETER TEST CONDITIONS TYP MAX UNIT XTS 0 LF mode selected Voc 2 2V 3V nput capacitance XIN P P XTS 1 XT1 mode selected Voc 22V 3V Note 19 XTS 0 LF mode selected 6 Voc 2 2V 3V utput capacitance XOUT XTS 1 XT1 mode selected Vcc 2 2 V 3 V Note 19 NOTE 19 Requires external capacitors at both terminals Values are specified by crystal manufacturers RAM pw GPU hated Note 20 NOTE 20 This parameter defines the minimum supply voltage Vcc when the data in the program memory RAM remains unchanged No program execution should happen during this supply voltage condition Ji TEXAS INSTRUMENTS 34 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued DCO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voc 22V 0 08 0 12 0 15 Vec
16. CIOA oHo Register CCRO CCIOB O Capture GND Mode Output Unit 0 Voc 9 o gt Comparator 0 CCIO CCMO1 CCMOO Capture Compare Register CCR1 CCIS11 12 11 10 1 2 Capture UTI Out 1 CAOUT CCHA E 0 Register CCR1 CCHB 9 Capture GND Mode Output Unit 1 N Voc o 3 1 Comparator 1 CCM CCM11 CCM10 Capture Compare Register CCR2 CCIS21 CCIS20 OM22 OM21 OM20 P1 3 0 Capture F ACLK CCI2A Enc Register CCR2 CCI2B 0 Capture GND Mode Output Unit 2 Voc Comparator 2 CCI2 CCM21 CCM20 Figure 4 Timer A MSP430x11x1 Configuration Two interrupt vectors are used by the Timer A module One individual vector is assigned to capture compare block CCRO and one common interrupt vector is implemented for the timer and the other two capture compare blocks The three interrupt events using the same vector are identified by an individual interrupt vector word The interrupt vector word is used to add an offset to the program counter to continue the interrupt handler software at the corresponding program location This simplifies the interrupt handler and gives each interrupt event the same overhead of 5 cycles in the interrupt handler UART Serial communication is implemented by using software and one capture compare block The hardware supports the output of the serial data stream bit by bit with the timing determined by the comparator timer The data input uses the capture
17. CLK 32 768 Hz TA 40 C 85 C Low power mode LPM2 f MCLK f SMCLK 0 MHz f ACLK 32 768 Hz SCGO 0 TA 40 C 85 C Low power mode LPM3 C113 I i f MCLK f SMCLK 0 MHz f ACLK 32 768 Hz SCGO 1 Low power mode LPM3 F11x1 f MCLK 0 MHz f SMCLk 0 MHz Voc 2 2 V f ACLK 0 Hz SCGO 1 Low power mode LPM4 F11x1 O_o 2 2 V 3 V NOTE All inputs are tied to 0 V or Vcc do not source or sink any current Low power mode LPM4 C11x1 current consumption of active mode versus system frequency C version F version IAM lAM 1 MHz X fsystem MHz current consumption of active mode versus supply voltage C version lam v 105 uAV x Voc 3 V current consumption of active mode versus supply voltage F version IAM las v 120 uA V x Vcc 3 V 35 TEXAS INSTRUMENTS 28 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 Schmitt trigger inputs Port P1 to Port P2 P1 0 to P1 7 P2 0 to P2 5 PARAMETER TEST CONDITIONS UNIT Voc 2 2 V 1 1 1 3 VIT Positive going input threshold voltage Voc 3V 1 5 1 8 Voo 22V Input voltage hysteresis VIT VjT_ 05 Yd cc electrical characteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued Vhys Voc 2 2 V 0 4 0 9
18. CLK for MCLK and SMCLK clock divider for MCLK and SMCLK at default dividing by 1 Timer A Timer A operates in continuous mode with MCLK source selected input divider set to 1 using CCRO and polling of CCIFGO WDT Watchdog timer is halted Interrupt GIE 0 NMIIE 0 OFIFG 0 ACCVIFG 0 Memory allocation and stack pointer If the stack pointer points to RAM addresses above 0220h 6 bytes of the stack are allocated plus RAM addresses 0200h to 0219h Otherwise the stack pointer is set to 0220h and allocates RAM from 0200h to 021Fh NOTE When writing RAM data via bootstrap loader take care that the stack is outside the range of the data being written Program execution begins with the user s reset vector at FFFEh standard method if TEST is held low while RST NMI goes from low to high RST NMI PIN ID UO l II UTP TEST PIN rnvn lx o 0 n H Vcc S lt Reset C ond ition gt User Program Starts POST OFFICE BOX 655303 DALLAS TEXAS 75265 35 TEXAS INSTRUMENTS MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 boot ROM containing bootstrap loader continued Program execution begins with the bootstrap vector at 0OCOOh boot ROM if a minimum of two positive edges have been applied to TEST while RST NM is low and TEST is high
19. Ce sI REC ET Erase one wing wan newrom e Erase all segments 0 to 7 but not the information memory segments A and B Erase all segments 0 to 7 and A and B by writing to any address in the flash memory module NOTE The table shows all valid combinations Any other combination will result in an access violation flash memory timing generator control register FCTL2 Thetiming generator Figure 1 generates allthe timing signals necessary for write erase and mass erase from the selected clock source One of three different clock sources may be selected by control bits SSELO and SSEL1 in control register FCTL2 The selected clock source should be divided to meet the frequency requirements specified in the recommended operating conditions 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 13 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 flash memory timing generator control register FCTL2 continued The flash timing generator is reset with PUC It is also reset if the emergency exit bit EMEX is set Control register FCTL2 may not be written to if the BUSY bit is set otherwise an access violation will occur ACCVIFG 1 Read access is possible at any time without restrictions SSEL1 SSELO Write 1 to PUC EMEX n Reset Divider oie Flash Timing 1 64 Generator BUS
20. EPTEMBER 1999 REVISED JUNE 2000 peripherals Peripherals are connected to the CPU through data address and control buses and can be handled easily with memory manipulation instructions oscillator and system clock Three clocks are used in the system the system master clock MCLK the subsystem master clock SMCLK and the auxiliary clock ACLK Main system clock MCLK used by the CPU and the system Subsystem clock SMCLK used by the peripheral modules Auxiliary clock ACLK originated by LFXT1CLK crystal frequency and used by the peripheral modules After a POR the DCOCLK is used by default the DCOR bit is reset and the DCO is set to the nominal initial frequency Additionally if LFXT1CLK fails as the source for MCLK the DCOCLK is automatically selected to ensure fail safe operation SMCLK can be generated from LFXT1CLK or DCOCLK ACLK is always generated from LFXT1CLK The crystal oscillator can be defined to operate with watch crystals 32768 Hz or with higher frequency ceramic resonators or crystals The crystal or ceramic resonator is connected across two terminals No external components are required for watch crystal operation If the high frequency XT1 mode is selected external capacitors from XIN to VSS and XOUT to VSS are required as specified by the crystal manufacturer The LFXT1 oscillator starts after applying VCC If the OscOff bit is set to 1 the oscillator stops when it is not used for MCLK The clock signal
21. MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 Low Supply Voltage Range 1 8 V 3 6 V Serial Onboard Programming Ultralow Power Consumption Programmable Code Protection by Security Low Operation Current Fuse C11x1 Only 1 3 uA at 4 kHz 2 2 V Family Members Include 160 uA at 1 MHz 2 2 V MSP430C1111 2KB ROM 128B RAM Five Power Saving Modes MSP430C1121 4KB ROM 256B RAM Standby Mode 0 8 uA MSP430F1101 1KB 128B Flash Memory RAM Retention Off Mode 0 1 uA 128B RAM MTP1 256B RAM Available in a 20 Pin Plastic Small Outline Wide Body SOWB Package and 20 Pin 16 Bit RISC Architecture 125 ns Instruction Cycle Time Basic Clock Module Configurations Plastic Thin Shrink Small Outline Package Various Internal Resistors TSSOP Single External Resistor 92 KHz Crystal DW OR PW PACKAGE Crystal TOP VIEW External Clock Source TEST 10 P1 7 TA2 TDO TDI VCC 2 P1 6 TA1 TDI e 16 Bit Timer With Three Capture Compare P2 5 Rosc 3 P1 5 TA0 TMS Registers Vss 4 P1 4 SMCLK TCK Slope A D Converter With External ed 5 a 6 1 2 1 Components RST NMI 7 P1 1 TAO On Chip Comparator for Analog Signal E 8 P1 Compare Function or Slope A D P2 1 INCLK 9 2 4 2 C an P P2 2 CAOUT TAO 1 P2 3 CAO TA1 description The Texas Instruments MSP430 series is an ultralow power microcont
22. Negative going input threshold voltage Voo 3V outputs Port 1 to P2 P1 0 to P1 7 P2 0 to P2 5 PARAMETER A CONDITIONS EET UNIT Tormey S mA 025 iah Voc 2 2 V High level output voltage lOHmax 6 mA Tm 6 Port 1 and Port 2 C11x1 V Port 1 F11x1 Omaj e e psu Vcc 0 25 em Voc 08 l OHmax 1 mA See Note 10 Vcc 0 25 vo Voc 2 2 V High level output voltage 1 34mA See Note 10 Vcc 0 6 vcc y dec KoHmag mA See Note 10 Vcc 025 Voc l OHmax 3 4mA OHmax 3 4mA 4mA See Note 10 Vcc 0 6 I OLmax 1 5 Vss Vgg 0 25 Low level output volt ort 1 and Por x1 E omnet 5 Vss 55 025 xi Moman ema OC 3v Vss TE NOTES 8 maximum total current loHmax and for all outputs combined should not exceed 12 mA to hold the maximum voltage drop specified 9 The maximum total current loOHmax and for all outputs combined should not exceed 48 mA to hold the maximum voltage drop specified 10 One output loaded at a time leakage current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pot P1 P1 x 0 lt x lt 7 Vcc 2 2 V 3 V 450 see Notes 11 12 ns n Port P2 P2x 0 lt lt 5 Vcc 22 V see Notes 11 12 NOTES 11 The leakage current is measured with Vss or Vcc applied to the corresponding pin s unless otherwise noted 12 The leakage of the
23. P2IRQ x Interrupt Edge P2IFG x Select Interrupt NOTE x Bit Identifier O to 2 for port P2 Flag P2IES x P2SEL x Direction PnDIR x control from PnOUT x Module X OUT Module X IN PnIFG x PnIES x module P2Sel 0 P2DIR 0 P2DIR 0 P2OUT 0 ACLK P2IN 0 P2IE 0 P2IFG 0 P1IES 0 P2Sel 1 P2DIR 1 P2DIR 1 P2OUT 1 P2IN 1 INCLKT P2IE 1 P2IFG 1 P1IES 1 P2Sel 2 P2DIR 2 P2DIR 2 P2OUT 2 CAOUT P2IN 2 CCIOBT P2IE 2 P2IFG 2 PilES 2 t Signal from or to Timer A NOTES 27 Optional selection of pullup or pulldown resistors with ROM masked versions 28 Fuses for optional pullup and pulldown resistors can only be programmed at the factory ROM versions only vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 39 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 APPLICATION INFORMATION Port P2 P2 3 to P2 4 input output with Schmitt trigger P2SEL 3 e Voc P2DIR 3 1 9 0 Input Direction Control 1 1 Output See Note 27 From Module r sisa ad Logic P20UT3 See Note 28 P2 3 1 Zr Module X Es OUT See Note 28 See Note 27 Ls P2IN 4 GND a r Module X IN lt p e P2IRQ 3 C P2IE 3 Interrupt Edge P2IFG 3 9 CAPD 3 Select pom m si omparator Interrupt CAREF P2CA CAEX
24. R SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 instruction set continued Computed branches BR and subroutine calls CALL instructions use the same addressing modes as the other instructions These addressing modes provide indirect addressing ideally suited for computed branches and calls The full use of this programming capability permits a program structure different from conventional 8 and 16 bit controllers For example numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control operation modes and interrupts The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy consumption This is achieved by the intelligent management of the operations during the different module operation modes and CPU states The advanced requirements are fully supported during interrupt event handling An interrupt event awakens the system from each of the various operating modes and returns with the RETI instruction to the mode that was selected before the interrupt event The different requirements of the CPU and modules which are driven by system cost and current consumption objectives necessitate the use of different clock signals Auxiliary clock ACLK from LFXT1CLK crystal s frequency used by the peripheral modules Main system clock MCLK used by the CPU and system Subsystem clock SMCLK used by the peripheral modules
25. Y WAIT Figure 1 Flash Memory Timing Generator Diagram FCTL2 DLLILLLLLITEILIIILTI rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 FCTL2read lt 096h FCTL2 write lt 0A5h The control bits are FNO FN5 012Ah bitO 5 These six bits define the division rate of the clock signal The division rate is 1 to 64 according to the digital value of FN5 to FNO plus one SSELO SSEL1 012Ah bit6 7 Clock source select 0 ACLK 1 MCLK 2 SMCLK 3 SMCLK The flash timing generator is reset with PUC It is also reset if the EMEX bit is set flash memory control register FCTL3 There are no restrictions to modify this control register FCTL3 ACCV TTTTTTT EEE PEEP rw 0 rw 1 rw 0 rw FCTL3 read lt 096h gt FCTL3 write lt 0A5h Ji TEXAS INSTRUMENTS 14 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 flash memory control register FCTL3 continued BUSY KEYV ACCVIFG WAIT 012Ch bitO 012Ch bit1 012Ch bit2 012CH bit3 The BUSY bit shows if an access to the flash memory is allowed BUSY 0 or if an access violation occurs The BUSY bit is read only but a write operation is allowed The BUSY bit should be tested before each write and erase cycle The flash timing generator hardware immediately sets the BUSY bit after start of a write segment write erase or
26. capture compare blocks are configured by the application to run in capture or compare mode The capture mode is primarily used to measure external or internal events using any combination of positive negative or both edges of the signal Capture mode can be started and stopped by software Three different external events TAO TA1 and TA2 can be selected At capture compare register CCR2 the ACLK is the capture signal if CCI2B is selected Software capture is chosen if CCISx 2 or CCISx 3 see Figure 4 The compare mode is primarily used to generate timings for the software or application hardware orto generate pulse width modulated output signals for various purposes like D A conversion functions or motor control An individual output module is assigned to each of the three capture compare registers The output modules can run independently of the compare function or can be triggered in several ways 20 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 Timer A 3 capture compare registers continued 32 kHz to 8 MHz Pata 16 Bit Timer SSEL1 SSELO Timer Clock P1 0 tacik ollo 15 Input 16 Bit Timer Mode ee 2 1 INCLK O O Carry Zero Set_TAIFG POR CLR Timer Bus Capture Compare Register CCRO CCIS01 CCISOO OM02 OM01 OMOO P1 1 B Capture iod C
27. digital port pins is measured individually The port pin must be lee for input and there must be no optional pullup or pulldown resistor llkg Px x High impedance leakage current 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 29 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued optional resistors individually programmable with ROM code see Note 13 PARAMETER TEST CONDITIONS Resistors individually programmable with ROM code all port pins Voc 22 V 8 V values applicable for pulldown and pullup NOTE 13 Optional resistors Roptx for pulldown or pullup are not available in standard flash memory device MSP430F11x1 inputs Px x TAx PARAMETER TEST CONDITIONS vec M MAX UNIT Port P1 P2 1 to P2 x lint External interrupt timing External trigger signal for the interrupt flag 22v as sv t cap Timer A capture timing TAO TA1 TA2 see Note 15 aav amp 50 NOTES 14 The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met It may be set even with trigger signals shorter than tint Both the cycle and timing specifications must be metto ensure the flag is set tint is measured in cycles 15
28. ervices might be or are used TI s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
29. imers thereto appears at the end of this data sheet t MTP Multiple Time Programmable PRODUCTION DATA information is current as of publication date Copyright 2000 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments Jj standard warranty Production processing does not necessarily include testing of all parameters EXAS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC PLASTIC 20 PIN SOWB 20 PIN TSSOP DW PW MSP430C11111DW MSP430F11011PW MSP430C11211DW MSP430F11211PW MSP430F11011DW MSP430F11211DW 40 C to 85 C functional block diagram XIN XOUT Voc Vss RST NMI P1 0 7 1 il ACLK 1 2 4 KB ROM Outx Rosc Flash 126 256B 128 256B Power on CCIxA O Port pa MAG y SMCLK Flash INFO RAM Reset 8 l O s All With Interrupt E ROM SMCLK Capabililt F Flash MCLK i MAB 16 Bit MAB 4 Bit CPU _ Test MCB 16 Reg _ JTAG A MDB 16 Bit MDB 8 Bit us a E A TEST TACLK or Watchdog Timer_A Comparator A l O Port P2 t E cc ccn Input Multiplexer 6 l O s All With egiste
30. ing erase cycle see Note 26 MSP430F11x1 ES Write erase cycles MSP430F11x1 retention retention TJ 25 MSP430F11x1 NOTES 23 The power source to blow the fuse is applied to TDI pin 24 Once the JTAG fuse is blown no further access to the MSP430 JTAG test feature is possible The JTAG block is switched to bypass mode 25 f TCK may be restricted to meet the timing requirements of the module selected 26 Duration of the program erase cycle is determined by f FTG applied to the flash timing controller It can be calculated as follows t word write 35 x t f FTG l segment write byte 0 30 x 1 FTG t segment write byte 1 63 20 x t f FTG H Ki mass erase 5297 x 1 f FTG page erase 4819 1 f FTG Ji TEXAS INSTRUMENTS 36 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 APPLICATION INFORMATION input output schematic Port P1 P1 0 to P1 3 input output with Schmitt trigger Voc P1SEL x e PIDIR x 0 B See Note 27 Direction Control 1 o From Module 4 See Note 28 P1OUTx LS Pad Logic P1 0 P1 3 1 gt Module X OUT See Note 28 SSS eee JH See Note 27 P1IN x lt e Module X IN d pi P1IRQ x Interrupt Edge P1IFG x Select Interrupt Flag P1IES x NOTE x Bit identifier 0 to
31. instruction set This design structure results in a RISC like architecture highly transparent to the application development and noted for its programming simplicity All operations other than program flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source and four modes for destination operands 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 short form description continued CPU Program Counter PC RO All sixteen registers are located inside the CPU Stack Pointer SP R1 providing reduced instruction execution time This reduces a register register operation execution Status Register SR CG1 R2 time to one cycle of the processor Constant Generator CG2 R3 Four registers are reserved for special use as a program counter a stack pointer a status register General Purpose Register R4 and a constant generator The remaining twelve registers are available as general purpose General Purpose Register R5 registers Peripherals are connected to the CPU using a data address and control buses and can be General Purpose Register R14 handled easily with all instructions for memory manipulation General Purpose Register R15 instruction set The instructions set for this register register architecture provides a powerful and easy to use assembl
32. le 50 2 2 V 3 V NOTE 16 The limits of the system clock MCLK has to be met MCLK and SMCLK can have different frequencies Comparator A see Note 17 PARAMETER TEST CONDITIONS Voc 2 2V DD CAON 1 CARSEL 0 CAREF 0 CAON 1 CARSEL 0 Refladder CAREF 1 2 3 No load at RefDiode P2 3 CA0 TA1 and P2 4 CA1 TA2 Common mode input voltage Voltage 0 25 Vcc node PCA0 1 CARSEL 1 CAREF 1 No load at P2 3 CAO TA1 and CC P2 4 CA1 TA2 See Figure 5 Voltage 0 5 Vec node PCA0 1 CARSEL 1 CAREF 2 V No load at P2 3 CAO TA1 and CC P2 4 CA1 TA2 See Figure 5 PCA0 1 CARSEL 1 CAREF 3 No load at P2 3 CAO TA1 and P2 4 CA1 TA2 V Ref025 See Figure 5 V V Ref050 See Figure 5 TA 25 Overdrive 10 mV With out filter CAF 0 t response LH TA 25 C Overdrive 10 mV With filler CAF 1 25 Overdrive 10 mV without filter CAF 0 t response HL TA 25 C Overdrive 10 mV with filter CAF 1 NOTES 17 The leakage current for the Comparator A terminals is identical to llkg Px x specification 18 The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements The two successive measurements are then summed together 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 31 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 electrical characteri
33. llator can operate in three modes low frequency LF moderate frequency XT1 and external input mode The LFXT1 crystal oscillator may be switched off when it is not in use DCOCLK is generated from the DCO The nominal DCO frequency is defined by the dc generator and can be set by one external resistor or can be set to one of eight values with integrated resistors Additional adjustments and modulations of DCOCLK are possible by software manipulation of registers the DCO module DCOCLK is stopped automatically when it is not used by the CPU or peripheral modules The dc generator can be shut down with the SCGO bit to realize additional power savings when DCOCLK is not in use NOTE The system clock generator always starts with the DCOCLK selected for MCLK CPU clock to ensure proper start of program execution The software defines the final system clock generation through control bit manipulation digital I O There are two eight bit I O ports port P1 and port P2 implemented 11x1 parts only have six port P2 I O signals available on external pins Both ports P1 and P2 have seven control registers to give maximum flexibility of digital input output to the application All individual I O bits are programmable independently Any combination of input output and interrupt conditions is possible Interrupt processing of external events is fully implemented for all eight bits of port P1 and for six bits of port P2 e
34. memory organization MSP430C1111 MSP430C1121 MSP430F1101 MSP430F1121 FFFFh FFFFh FFFFh FFFFh FFEOh Int Vector FFEOh Int Vector FFEOh Int Vector FFEOh Int Vector FFDFh 2 ROM FFDFh FFDFh 1 KB Flash FFDFh 4KB 1 Main F800h 4KB Fcoon Segmento Flash ROM Segment0 7 Memory F000h 10FFh 128B Flash 1080h SegmentA 10FFh 2x128B information m 0C00h Boot ROM OFFFh Boot ROM DO 02FFh 256B RAM 256B RAM 027Fh i26B RAM 027Fh RAM 0200h 0200h 0200h 0200h OTFFh 46b Per O1FFh 46b Per 1 Per O1FFh 6b Per 0100h 0100h 0100h 0100h 0010h 0010h 0010h 0010h 0000h 0000h 0000h 0000h F000h Memory 02FFh boot ROM containing bootstrap loader The intention of the bootstrap loader is to download data into the flash memory module Various write read and erase operations are needed for a proper download environment The bootstrap loader is only available on F devices functions of the bootstrap loader Definition of read apply and transmit data of peripheral registers or memory to pin P1 1 BSLTX write read data from pin P2 2 BSLRX and write them into flash memory unprotected functions Mass erase erase of the main memory Segment0 to Segment7 Access to the MSP430 via the bootstrap loader is protected It must be enabled before any protected function can be performed The 256 bits in OFFEOh to OFFFFh provide the access key protected functions All protected functions ca
35. mode of operation can be retrieved after the interrupt request During execution of an interrupt handler routine the bits can be manipulated via indirect access of the data on the stack That allows the program to resume execution in another power operating mode after the return from interrupt RETI SCG1 SCGO The clock signal SMCLK used for peripherals is enabled when bit SCG1 is reset or disabled if the bit is set The dc generator is active when SCGO is reset The dc generator can be deactivated only if the SCGO bit is set and the DCOCLK signal is not used for MCLK or SMCLK The current consumed by the dc generator defines the basic frequency of the DCOCLK It is a dc current The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCGO bit is set There are two situations when the SCGO bit cannot switch off the DCOCLK signal 1 DCOCLK frequency is used for MCLK CPUOff 0 and SELM 120 2 DCOCLK frequency is used for SMCLK SCG1 0 and SELS 0 NOTE When the current is switched off SCG0 1 the start of the DCOCLK is delayed slightly The delay is in the us range see device parameters for details OscOff CPUOFff The LFXT1 crystal oscillator is active when the OscOff bit is reset The LFXT1 oscillator can only be deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK The setup time to start a crystal oscillation needs consideration when oscillator off option is used Ma
36. module can work as an interval timer which generates an interrupt after the selected time interval The watchdog timer counter WDTCNT is a 16 bit up counter which is not directly accessible by software The WDTONT is controlled through the watchdog timer control register WDTCTL which is a 16 bit read write register Writing to WDTCTL is in both operating modes watchdog or timer only possible by using the correct password in the high byte The low byte stores data written to the WDTCTL The high byte must be the password 05Ah If any value other than 05Ah is written to the high byte of the WDTCTL a system reset PUC is generated When the password is read its value is 069h This minimizes accidental write operations to the WDTCTL register In addition to the watchdog timer control bits there are two bits included in the WDTCTL register that configure the NMI pin Timer A Three capture compare registers The Timer A module on 11x1 devices offers one sixteen bit counter and three capture compare registers The timer clock source can be selected to come from two external sources TACLK SSEL 0 or INCLK SSEL 3 or from two internal sources the ACLK SSEL 1 or SMCLK SSEL 2 The clock source can be divided by one two four or eight The timer can be fully controlled in word mode since it can be halted read and written It can be stopped run continuously counted up or up down using one compare block to determine the period The three
37. n be executed only if the access is enabled Write program byte into flash memory Parameters passed are start address and number of bytes the segment write feature of the flash memory is not supported and not useful with the UART protocol Segment erase of SegmentO to Segment7 in the main memory and segment erase of SegmentA and SegmentB in the information memory Read all data in main memory and information memory Read and write to all byte peripheral modules and RAM Modify PC and start program execution immediately NOTE Unauthorized readout of code and data is prevented by the user s definition of the data in the interrupt memory locations 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 boot ROM containing bootstrap loader continued features of the bootstrap loader are hardware resources used for serial input output UART communication protocol fixed to 9600 baud Port pin P1 1 for transmit P2 2 for receive TI standard serial protocol definition Implemented in flash memory version only Program execution starts with the user vector at OFFFEh or with the bootstrap loader start vector is at address 0C00h Pins P1 1 and P2 2 for serial data transmission Test and RST NMI to start program execution at the reset or bootstrap loader vector Basic clock module Rsel 5 DCO 4 MOD 0 DCO
38. operations They can also be used externally to bias analog circuitry Voltage current and resistive or capacitive sensor measurements are basic functions The sensors sense physical conditions like temperature pressure acceleration etc 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 peripheral file map PERIPHERALS WITH WORD ACCESS Timer A Reserved Reserved Reserved Reserved Capture compare register Capture compare register Capture compare register Timer A register Reserved Reserved Reserved Reserved Capture compare control Capture compare control Capture compare control Timer A control Timer A interrupt vector Flash Memory Flash control 3 Flash control 2 Flash control 1 Watchdog Watchdog timer control WDTCTL 0120h PERIPHERALS WITH BYTE ACCESS Comparator A Comparator_A port disable Comparator_A control2 Comparator_A control1 System Clock Basic clock sys control2 BCSCTL2 Basic clock sys control1 BCSCTL1 DCO clock freq control DCOCTL Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Function SFR interrupt flag2 SFR inter
39. ory interrupt and security key violation One NMI vector is used for three NMI events RST NMI NMIIFG oscillator fault OFIFG and flash memory access violation ACCVIFG The software can determine the source of the interrupt request since all flags remain set until they are reset by software The enable flag s should be set simultaneously with one instruction before the return from interrupt RETI instruction This ensures that the stack remains under control A pending NMI interrupt request will not increase stack demand unnecessarily 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 ACCV ACCVIFG FCTL1 1 ACCVIE Flash Module IE1 5 Flash Module Clear Flash Module PUC RST NMI POR PUC Y KEYV VCC PUC System Reset Generator POR gt gt NMIRS NMIES TMSEL NMI WDTQn EQU PUC POR A A A o WDTIFG S gt IRQ IFG1 0 Clear WDT Counter OSCFault POR OFIFG IFG1 1 IRQA OFIF TIMSEL WDTIE 1E1 1 Clear IE1 0 NMI_IRQA Clear PUC Watchdog Timer Module IRQA Interrupt Request Accepted Figure 2 Block Diagram of NMI Interrupt Sources 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 17 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C S
40. ory other than the flash memory e g boot ROM RAM In the event a flash program or erase operation is initiated while the program counter is pointing to the flash memory the CPU will execute JMP instructions until the flash program or erase operation is completed Normal execution of the previously running software then resumes Unprogrammed new devices may have some bytes programmed in the information memory needed for test during manufacturing The user should perform an erase of the information memory prior to first use flash memory control register FCTL1 All control bits are reset during PUC PUC is active after Vcc is applied a reset condition is applied to the RST NMI pin the watchdog timer expires a watchdog access violation occurs or an improper flash operation has been performed A more detailed description of the control bit functions is found in the flash memory module description refer to MSP430x1xx User s Guide literature number SLAUO49 Any write to control register FCTL1 during erase mass erase or write programming will end in an access violation with ACCVIFG 1 Special conditions apply for segment write mode Refer to MSP430x1xx User s Guide literature number SLAU049 for details 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 flash memory control register FCTL1 continued Read access is po
41. r y Outx RC Filtered O P interr pt L ACLK CCRO 1 2 CCIx Internal Vref Capabililty ACLK 15 16 Bit 20 1 2 DCOR SMCLK 0 1 CCIx MN c rud P2 0 ACLK P2 5 Rosc P2 1 INCLK P2 4 CA1 TA2 P2 2 CAOUT TAO P2 3 CAO TA1 pulldown resistor of 30 kQ is needed on 11 1 35 TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 Terminal Functions TERMINAL 1 0 DESCRIPTION NAME NO P1 4 SMCLK TCK 17 lO General purpose digital I O pin SMCLK signal output test clock input terminal for device programming and test P1 5 TAO TMS 18 lO General purpose digital I O pin Timer A compare OutO output test mode select input terminal for device programming and test P1 6 TA1 TDI 19 General purpose digital I O pin Timer A compare Out1 output test data input terminal P1 7 TA2 TDO TDIT 20 lO General purpose digital I O pin Timer A compare Out2 output test data output terminal or data input during programming 7 Resetornonmaskableinemuptioput _ O I I esr 1 Sseerertest mode for TAG pins on Pont Must be Ved ow wih less han we e ewe _ _ Mes a unas _ _ XN SOS T or TDI is selected via JTAG instruction short form description processing unit The processing unit is based on a consistent and orthogonally designed CPU and
42. r port P2 without external pins Direction P2Selx P2DIR x control from P2OUT x Module X OUT P2IN x Module X IN P2IE x P2IFG x P2IES x module P2IES 7 NOTE A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags The interrupt flags can not be influenced from any signal other than from software They work then as a soft interrupt JTAG fuse check mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power on reset POR When activated a fuse check current can flow from the TEST pin to ground if the fuse is not burned Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption When the TEST pin is taken back low after a test or programming session the fuse check mode and sense currents are terminated 35 TEXAS INSTRUMENTS 42 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 MECHANICAL DATA DW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 16 PIN SHOWN 0 050 1 27 0 020 0 51 0 014 0 35 16 9 0 010 0 25 0 419 10 65 0 400 10 15 7 59 0 010 0 25 NOM 7 45 i Gage Plane Y t 0 010 0 25 0 050 1 27 0 016
43. re exchanged used to measure and compensate the offset of the comparator Eight additional bits are implemented into the Comparator A module and enable the SW to switch off the input buffer of port P2 A CMOS input buffer would dissipate supply current when the input is not near VSS or VCC Comparator_A port disable control bits CAPDO to CAPD7 are initially reset and the port input buffer is active The port input buffer is disabled if the appropriate control bit is set TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 23 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 Comparator A continued 7 0 CACTL1 CA CA CA 059h CAEX RSEL REF1 REFO CAON CAIES CAIE CAIFG rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 0 CACTL2 CACTL CACTL CACTL CACTL rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 7 0 CAPD 05Bh CAPD7 CAPD6 CAPD5 CAPD4 CAPD3 CAPD2 CAPD1 CAPDO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 NOTE Ensure that the comparator input terminals are connected to signal power or ground level Otherwise floating levels may cause unexpected interrupts and current consumption may be increased slope a d conversion The Comparator A is well suited for use in single or multiple slope conversions The internal reference levels may be used to set a reference during timing measurement of charge or discharge
44. ristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued principle characteristics of the DCO Individual devices have a minimum and maximum operation frequency The specified parameters for to fpcox7 are valid for all devices The DCO control bits DCO1 and have a step size as defined in parameter Spco The modulation control bits MODO to MODA select how often fpco is used within the period of 32 DCOCLK cycles fpco is used for the remaining cycles The frequency is an average fpco x 2MOD 32 The ranges selected by to Rsels to Rseig and Rseig to Rsei7 are overlapping wake up from lower power modes LPMx Vcc 2 2 V 8 V 100 f McLK 1MHz X Vcc 22V3V 2m Vec z2wav s Delay time see Note 22 GEG a RMcLK 3MHz Voc 22V3V 6 NOTE 22 Parameter applicable only if DCOCLK is used for MCLK JTAG programming PARAMETER TEST CONDITIONS TYP MAX UNIT Voo 22V D sf f TCK TCK frequency JTAG test see Note 25 Voo 3V Fuse blow voltage C versions see Notes 23 and 24 Voc 2 2 V 3V 3 5 3 9 Supply current on TDI during fuse blow see Note 24 C11x1 t IB Ig to blow the fuse see Note 24 C11x1 Vcc 2 7 V 8 6 V I DD PGM Current during program cycle see Note 26 MSP430F 1x1 WX Voc 2 7 V 3 6 V I DD ERASE Current dur
45. roller family consisting of several devices featuring different sets of modules targeted to various applications The microcontroller is designed to be battery operated for an extended application lifetime With 16 bit RISC architecture 16 bit integrated registers on the CPU and a constant generator the MSP430 achieves maximum code efficiency The digitally controlled oscillator provides fast wake up from all low power modes to active mode in less than 6 us Typical applications include sensor systems that capture analog signals convert them to digital values and then process the data and display them or transmitthem to a host system Stand alone RF sensor front end is another area of application The I O port inputs provide single slope A D conversion capability on resistive sensors The MSP430x11x series is an ultralow power mixed signal microcontroller with a built in 16 bit timer and fourteen I O pins The MSP430x11x1 family adds a versatile analog comparator The flash memory provides added flexibility of in system programming and data storage without significantly increasing the current consumption of the device The programming voltage is generated on chip thereby alleviating the need for an additional supply and even allowing for reprogramming of battery operated systems Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and discla
46. rupt flag1 SFR interrupt enable2 SFR interrupt enable1 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 25 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 absolute maximum ratingst Voltage applied at Vac to Vss MSP430C11x1 0 3 V to 4 6 V Voltage applied at Vac to Vss MSP430F11x1 0 3 V to 4 1 V Voltage applied to any pin referenced to Vses 0 3 V to Vcc 0 3 V Diode current at any device terminal 2 mA Storage temperature Tstg unprogrammed device 55 C to 150 C Storage temperature Tstg programmed device 40 C to 85 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE All voltages referenced to Vss recommended operating conditions o N NOM UNITS MSP430C11x1 MSP430F11x1 Supply voltage during program erase flash memo
47. ry Vcc MSP430F11x1 Supply voltage Vss Operating free air temperature range TA MSP430x11x1 40 85 450 Supply voltage during program execution Vcc see Note 5 m X o LF mode selected XTS 0 Watch crystal 32768 LFXT1 crystal frequency 8000 f LFXT1 see Note 6 XT1 mode selected XTS 1 Voc 1 8 V d MSP430x11x1 Processor frequency f system MCLK signal Ne eae a Voc 3 6 V MSP430x11x1 O dc dc 57 Flash timing generator frequency MSP430F11x1 2 Cumulative program time segment write see Note 7 Low level input voltage TCK TMS TDI RST NMI Vit excluding XIN XOUT Vee 2 2 V3 V Vss High level input voltage TCK TMS TDI RST NMI VIH excluding XIN XOUT Vcc 2 2 V 3 V 0 8Vcc ss 0 2xVCC V V Input levels at XIN XOUT EDI AUT Voc 2 2 V 3V VIH XIN XOUT 0 8xVCC Vc NOTES 5 The LFXT1 oscillator in LF mode requires a resistor of 5 1 MO from XOUT to VSS when VCC 2 5 V The LFXT1 oscillator in XT1 mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC 2 2 2 V The LFXT1 oscillator in XT1 mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC gt 2 8 V 6 The LFXT1 oscillator in LF mode requires a watch crystal The LFXT1 oscillator in XT1 mode accepts a ceramic resonator or a crystal 7 The cumulative program time must not be exceeded during a segment write operation Vssg 0 6 4 V V V C z 2 Hz 2 S
48. s ACLK and SMCLK may be used externally via port pins Different application requirements and system conditions dictate different system clock requirements including High frequency for quick reaction to system hardware requests or events Low frequency to minimize current consumption EMI etc Stable peripheral clock for timer applications such as real time clock RTC Start stop operation to be enabled with minimum delay 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 oscillator and system clock continued DCOMOD SMCLKGEN I DIVA LFXT1CLK e ACLK xTS Auxiliary Clock XIN ACLKGEN gt SELM DIVM CPUOff LFXT1 OSCILLATOR 4 lt 0 1 xour rj MCLK Main System Clock MCLKGEN Vcc Vcc SCGO DCO MOD SELS DIVS SCG1 Digital Controlled Oscillator DCO SMCLK Modulator MOD Subsystem Clock P2 5 Rosc The DCO Generator is connected to pin P2 5 Rosc if DCOR control bit is set The port pin P2 5 Rosc is selected if DCOR control bit is reset initial state Figure 3 Clock Signals Two clock sources LFXT1CLK and DCOCLK can be used to drive the MSP430 system The LFXT1CLK is generated from the LFXT1 crystal oscillator The LFXT1 crystal osci
49. should be protected from potential EMI puce and ESD voltage spikes This may require a smaller TMS external pulldown resistor in some applications 5 uc E x Bit identifier 4 to 7 for port P1 p During programming activity and during blowing the fuse the pin TDO TDI is used to apply the test Te input for JTAG circuitry Direction PnDIR x control from PnOUT x Module X OUT Module X IN PnIFG x PnIES x module t Signal from or to Timer A NOTES 27 Optional selection of pullup or pulldown resistors with ROM masked versions 28 Fuses for optional pullup and pulldown resistors can only be programmed at the factory ROM versions only 35 TEXAS INSTRUMENTS 38 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 APPLICATION INFORMATION Port P2 P2 0 to P2 2 input output with Schmitt trigger P2SEL x e Vcc P2DIR x 0 Q 0 Input 4 TS e See Note 27 Direction Control Oo 1 Output From Module a m See Note 28 ties o P2 0 P2 2 sS e Module X OUT o See Note 28 SI See Note 27 L PREDA tla emend I J GND 1 Bus Keeper e P2IN x lt L Module X IN lt D e CAPD X
50. sk programmable ROM devices can disable this feature so thatthe oscillator can never be switched off by software The clock signal MCLK used for the CPU is active when the CPUOff bit is reset or stopped if it is set 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 interrupt vector addresses The interrupt vectors and the power up starting address are located in the memory with an address range of OFFFFh OFFEOh The vector contains the 16 bit address of the appropriate interrupt handler instruction sequence INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY WDTIFG Note1 Power up external reset watchdo R OFFFEh 15 highest KEYV Note 1 di NMIIFG Notes 1 and 4 non maskable OFIFG Notes 1 and 4 non maskable OFFFCh ACCVIFG Notes 1 and 4 non maskable NMI oscillator fault flash memory access violation ooromaez 9 gt 7 recht EAH M 3 I O Port P2 eight flags see Note 3 Kip perd OFFE6h NOTES Multiple source flags Interrupt flags are located in the module There are eight Port P2 interrupt flags but only six Port P2 I O pins P2 0 5 are implemented on the 11x1 devices non maskable the individual interrupt enable bit can disable an interrupt event but the general interrupt
51. ssible at any time without restrictions The control bits of control register FCTL1 are FCTL1 SEG ora LLELILILLIILELELELEEIEITI rw 0 rw 0 10 ro rw 0 rw 0 ro FCTL1 read lt 4 096h FCTL1 write lt 0A5h Erase 0128h biti Erase a segment 0 No segment erase will be started 1 Erase of one segment is enabled The segment to be erased is defined by a dummy write into any address within the segment The erase bit is automatically reset when the erase operation is completed MEras 0128h bit2 Mass Erase main memory segments are erased together 0 No segment erase will be started 1 Erase of main memory segments is enabled Erase starts when a dummy write to any address in main memory is executed The MEras bit is automatically reset when the erase operation is completed WHRT 0128h bito Bit WRT must be set for a successful write execution If bit WRT is reset and write access to the flash memory is attempted an access violation occurs and ACVIFG is set SEGWRT 0128h bit7 Bit SEGWRT may be used to reduce total programming time Refer to MSP430x1xx User s Guide literature number SLAU049 for details 0 No segment write acceleration is selected 1 Segment write is used This bit needs to be reset and set between segment borders Table 3 Allowed Combinations of Control Bits Allowed for Flash Memory Access FUNCTION PERFORMED O SEGWwAT WAT Eres Erase BUSY war Lock wewa o o r o fl
52. stics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued 700 A Mean 6 Sigma A Mean 4 Sigma 9 Mean Mean 4 Sigma Q Mean 6 Sigma 650 600 gt o E gt 550 500 450 45 25 5 15 35 55 75 95 Temperature C Figure 7 V RetvT VS Temperature Vcc V C1121 700 A Mean 6 Sigma 650 A Mean 4 Sigma Ej Mean Q Mean 4 Sigma 600 Mean 6 Sigma E gt 550 500 45 25 5 15 35 55 75 95 Temperature C Figure 8 V RefvT VS Temperature Vcc 2 2 V C1121 35 TEXAS INSTRUMENTS 32 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 electrical characteristics over recommended ranges of supply voltage and operating free air temperature unless otherwise noted continued OV Vcc 0 CAF CAON Low Pass Filter gt To Internal Modules Lo 9 CAOUT Set CAIFG Flag t 2 0 us Figure 9 Block Diagram of Comparator_A Module Overdrive VCAOUT t response Figure 10 Overdrive Definition PUC POR TEST CONDITIONS V POR A Vcc 2 2 V 8 V B sv 85 C ae PUC POR Reset is accepted internally 5 TEXAS INSTRUMENTS POST OFFICE
53. tive and data programming is complete 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 15 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 flash memory control register FCTL3 continued LOCK 012Ch bit4 The lock bit may be set during any write segment erase or mass erase request Any active sequence in progress is completed normally In segment write mode the SEGWRT bit is reset and the WAIT bit is set after the mode ends The lock bit is controlled by software or hardware If an access violation occurs and the ACCVIFG is set the LOCK bit is set automatically 0 Flash memory may be read programmed erased or mass erased 1 Flash memory may be read but not programmed erased or mass erased A current program erase or mass erase operation will complete normally The access violation interrupt flag ACCVIFG is set when data are written to the flash memory module while the lock bit is set EMEX 012Ch bits Emergency exit The emergency exit should only be used if the flash memory write or erase operation is out of control 0 No function 1 Stops the active operation immediately and shuts down all internal parts in the flash memory controller Current consumption immediately drops back to the active mode All bits in control register FCTL1 are reset Since the EMEX bit is automatically reset by hardware the software always reads EMEX as 0 flash mem
54. trol bits are CAOUT CAF CAO CAI CACTL2 4 to CATCTL2 7 CAIFG CAIE CAIES CAON CAREF CARSEL CAEX 05Ah bitO 05Ah 05Ah bit2 05Ah 05Ah bit4 05Ah bit7 059h bitO 059h 059h bit2 059h bit3 059h bit4 5 059h bit6 059h bit7 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 Comparator output The comparator output is transparent or fed through a small filter 0 Pin P2 3 CAO TA1 is not connected to Comparator A 1 Pin P2 3 CAO TA1 is connected to Comparator A 0 Pin P2 4 CA1 TA2 is not connected to Comparator A 1 Pin P2 4 CA1 TA2 is connected to Comparator A Bits are implemented but do not control any hardware in this device Comparator_A interrupt flag Comparator A interrupt enable Comparator_A interrupt edge select bit 0 The rising edge sets the Comparator A interrupt flag CAIFG 1 The falling edge set the Comparator_A interrupt flag CAIFG The comparator is switched on Comparator_A reference 0 Internal reference is switched off an external reference can be applied 1 0 25 x VCC reference selected 2 0 50 x VCC reference selected 3 A diode reference selected An internal reference VcAngr selected by CAREF bits can be applied to signal path CAO or CA1 The signal VcAngr is only driven by a voltage source if the value of CAREF control bits is 1 2 or 3 The comparator inputs a
55. when RST NMI goes from low to high The TEST signal is normally used internally to switch pins P1 4 P1 5 P1 6 and P1 7 between their application function and the JTAG function If the second rising edge at TEST is applied while RST NMI is held low the internal TEST signal is held low and the pins remain in the application mode Vcc V V RST NMI PIN ids rs mE rcm EE lr pO P gc Lr Bootstrap loader Starts TEST RERUM PNE IN Internal Test mode can be entered again after TEST is taken low and then back high The bootstrap loader will not be started via the vector in address OCOOh if There were less than two positive edges at TEST while RST NMI is low TEST is low if RST NMI goes from low to high JTAG has control over the MSP430 resources Supply voltage VCC drops and a POR is executed WARNING The bootstrap loader starts correctly only if the RST NMI pin is in reset mode If itis switched to the NMI function unpredictable program execution may result However a bootstrap load may be started using software and the bootstrap vector for example the instruction BR amp OCOOh 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 11 MSP430x11x1 MIXED SIGNAL MICROCONTROLLER SLAS241C SEPTEMBER 1999 REVISED JUNE 2000 flash memory
56. y language The instruction set consists of 51 instructions with three formats and seven addressing modes Table 1 provides a summation and example of the three types of instruction formats the addressing modes are listed in Table 2 Table 1 Instruction Word Formats Dual operands source destination e g ADD R4 R5 R4 R5 gt R5 Single operands destination only e g CALL R8 PC TOS R8 2 PC Relative jump un conditional e g JNE Jump on equal bit 0 Most instructions can operate on both word and byte data Byte operations are identified by the suffix B Examples Instructions for word operation Instructions for byte operation MOV EDE TONI MOVB EDE TONI ADD 235h amp MEM ADD B 35h amp MEM PUSH R5 PUSH B R5 SWPB R5 Table 2 Address Mode Descriptions ADRESS MODE s a SvNTAK Exwme ommon MOV X Rn Y Rm MOV 2 R5 6 R6 M 2 R5 2 M 6 R6 Symbolic PC relative V MOVED TON gt MTONI fabsoute Y vovawew arcos M MEN gt Indret q MOV Pn Y Rm MOV QR10 Tab R6 M R10 5 M Tab R6 v MOV Rn AM wovemes nn sn mo 289 wovexrow Ton ees wow NOTE s source destination Rs Rd source register destination register Rn register number 35 TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 MSP430x11x1 MIXED SIGNAL MICROCONTROLLE

Texas Instruments MSP430x11x1 User's Manual

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