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SMSC USB3280 User's Manual

1. 38 Table 8 10 Attach and Reset Timing Values 40 SMSC USB3280 Revision 1 5 11 15 07 5 DATASHEET Hi Speed USB Device PHY with UTMI Interface E gt SMSE Datasheet Chapter 1 General Description The USB3280 provides the Physical Layer PHY interface to a USB 2 0 Device Controller The IC is available in a 36 pin lead free ROHS compliant QFN package 1 1 Product Description The USB3280 is an industrial temperature USB 2 0 physical layer transceiver PHY integrated circuit SMSC s proprietary technology results in low power dissipation which is ideal for building a bus powered USB 2 0 peripheral The PHY uses an 8 bit bidirectional parallel interface which complies with the USB Transceiver Macrocell Interface UTMI specification It supports 480Mbps transfer rate while remaining backward compatible with USB 1 1 legacy protocol at 12Mbps All required termination and 5 25V short circuit protection of the DP DM lines are internal to the chip The USB3280 also has an integrated 1 8V regulator so that only a 3 3V supply is required While transmitting data the PHY serializes data and generates SYNC and EOP fields It also performs needed bit stuffing and NRZI encoding Likewise while receiving data the PHY de serializes incoming data stripping SYNC and EOP fields and performs bit un stuffing and NRZI decoding Revision 1 5 11 15 07 SMSC USB328
2. 12 Table 5 3 Recommended External Clock Conditions 12 Table 6 1 Electrical Characteristics Supply Pins Note 6 1 13 Table 6 2 DC Electrical Characteristics Logic Pins Note 6 2 13 Table 6 3 DC Electrical Characteristics Analog I O Pins DP DM Note 6 3 14 Table 6 4 Dynamic Characteristics Analog I O Pins DP DM Note 6 4 15 Table 6 5 Dynamic Characteristics Digital UTMI Pins Note 6 5 16 Table 7 1 DP DM Termination vs Signaling Mode 26 Table8 1 Linestate 28 Table 8 2 Operational Modes 29 Table 8 3 USB2 0 Test 29 Table 8 4 Reset Timing Values HS Mode 30 Table 8 5 Suspend Timing Values HS Mode 31 Table 8 6 HS Detection Handshake Timing Values FS Mode 33 Table 8 7 Reset Timing 35 Table 8 8 HS Detection Handshake Timing Values from Suspend 37 Table 8 9 Resume Timing Values HS Mode
3. the SIE must see the appropriate LINESTATE signals asserted continuously for 165 CLKOUT cycles Table 8 8 HS Detection Handshake Timing Values from Suspend TIMING PARAMETER DESCRIPTION VALUE While in suspend state an SEO is detected on the USB HS 0 HS Reset Handshake begins D pull up enabled HS terminations disabled SUSPENDN negated First transition of CLKOUT CLKOUT Usable frequency TO T1 TO 5 6ms accurate to 10 duty cycle accurate to 50 5 Device removes Chirp K from the bus 1 ms minimum width T2 1 0 ms lt lt and begins looking for host chirps TO 7 0 ms CLK Nominal CLKOUT is frequency accurate to 500 T1 lt lt TO 20 0ms ppm duty cycle accurate to 5055 Device asserts Chirp K on the bus T1 lt T2 lt TO 5 8ms SMSC USB3280 Revision 1 5 11 15 07 37 DATASHEET Hi Speed USB Device PHY with UTMI Interface SMSC 8 11 Assertion of Resume In this case an event internal to the device initiates the resume process A device with remote wake up capability must wait for at least 5ms after the bus is in the idle state before sending the remote wake up resume signaling This allows the hubs to get into their suspend state and prepare for propagating resume signaling The device has 10ms where it can draw a non suspend current before it must drive resume signaling At the beginning of this period the SIE may negate SUSPENDN allowing the transceiver
4. DETAILS OF TERMINAL 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED S K ILIEV 12 6 04 MO 36 QFN 6x6 F COPLANARITY ZONE APPLIES TO EXPOSED AND TERMINALS PRINT WITH SCALE TO FIT DO NOT SCALE DRAWING S K ILIEV STD COMPLIANCE 12 6 04 JEDEC MO 220 Figure 9 1 USB3280 AEZG 36 Pin QFN Package Outline and Parameters 6 x 6 x 0 90 mm Body Lead Free RoHS Compliant jeeusejeq eoejielu LA gsn peeds iH Hi Speed USB Device PHY with UTMI Interface Datasheet 61 5 0 1 0 0 mm 2 04 0 05 mm V CARRIER ae 10 mm d 12 0 COVER TAPE HATCHED AREA SECTION A A FEED DIRECTION fm QFN 6x6 TAPING DIMENSIONS AND PART ORIENTATION UNIT MM Figure 9 2 QFN 6x6 Tape amp Reel SMSC USB3280 Revision 1 5 11 15 07 43 DATASHEET Hi Speed USB Device PHY with UTMI Interface Datasheet Country of origin if other than USA 102 0 REF Width at hub See DETAIL 4 Reel Width 2X Width Width 8 0 mm 4010 5 B 13 0 5 20 05 DETAIL A All Dimensions in Millimeters Figure 9 3 Reel Dimensions Note Standard reel size is 3000 pieces per reel Revision 1 5 11 15 07 SMSC USB3280 44 DATASHEET
5. E gt smsc Datasheet Table 4 5 Power and Ground Signals ACTIVE DIRECTION LEVEL DESCRIPTION VDD3 3 N A N A 3 3V Supply Provides power for USB 2 0 Transceiver UTMI V33 Digital Digital I O and Regulators REG_EN Input High On Chip 1 8V regulator enable Connect to ground to disable REN both of the on chip VDDA1 8 and VDD1 8 regulators When regulators are disabled External 1 8V must be supplied to VDDA1 8 and VDD1 8 pins When the regulators are disabled VDDA1 8 may be connected to VDD1 8 and a bypass capacitor 0 1uF recommended should be connected to each pin The voltage at VDD3 3 must be at least 2 64V 0 8 3 3V before voltage is applied to VDDA1 8 and VDD1 8 VDD1 8 N A N A 1 8V Digital Supply Supplied by On Chip Regulator when V18 REG EN is active Low ESR 4 7uF minimum capacitor requirement when using internal regulators Do not connect VDD1 8 to VDDA1 8 when using internal regulators When the regulators are disabled VDD1 8 may be connected to VDD1 8A VSS N A N A Common Ground GND VDDA1 8 N A N A 1 8V Analog Supply Supplied by On Chip Regulator when V18A REG EN is active Low ESR 4 7uF minimum capacitor requirement when using internal regulators Do not connect VDD1 8A to VDD1 8 when using internal regulators When the regulators are disabled VDD1 8A may be connected to VDD1 8 SMSC USB3280 Revision 1 5 11 15 07 11 DATASHEET Hi Speed USB Device PHY with UTMI Interface E gt
6. Input N A Operational Mode These signals select between the OM1 various operational modes 1 0 Description 0 0 0 Normal Operation 1 1 Non driving all terminations removed 0 2 Disable bit stuffing and NRZI encoding 1 3 Reserved LINESTATE 1 0 Output N A Line State These signals reflect the current state of the LS1 USB data bus in FS mode with 0 reflecting the state of LS0 DP and 1 reflecting the state of DM When the device is suspended or resuming from a suspended state the signals are combinatorial Otherwise the signals are synchronized to CLKOUT 1 0 Description 0 0 0 SE0 1 J State 2 K State 3 SE1 SMSC USB3280 Revision 1 5 11 15 07 9 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc Datasheet Table 4 2 Data Interface Signals ACTIVE DIRECTION LEVEL DESCRIPTION DATA 7 0 Bidirectional High Data bus 8 bit Bidirectional mode bus 8 bit Bidirectional mode 7 0 TXVALID Input High Transmit Valid Indicates that the DATA bus is valid for transmit The TXV assertion of TXVALID initiates the transmission of SYNC on the USB bus The negation of TXVALID initiates EOP on the USB Control inputs OPMODE 1 0 TERMSELECT XCVRSELECT must not be changed on the de assertion or assertion of TXVALID The PHY must be in a quiescent state when these inputs are changed 07 TXREADY Output High Transmit Data Ready If TXVALID
7. smsc Chapter 5 Limiting Values Datasheet Table 5 1 Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS pum mex ow UNITS Maximum DP and DM L3 5V 0 3 voltage to Ground Maximum VDD1 8 and VMAX 1 8V 0 3 VDDA1 8 voltage to Ground Maximum 3 3V Supply VMAX 3 3V 0 3 4 0 V Voltage to Ground u Maximum I O Voltage to 0 3 Ground Storage Temperature Temperature Use 00 ESD PERFORMANCE LATCH UP PERFORMANCE Note In accordance with the Absolute Maximum Rating system IEC 60134 Table 5 2 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS UNITS 3 3V Supply Voltage VDD3 3 3 0 VDD3 3 and VDDA3 3 Input Voltage on Digital Pins Voltage on Digital Input Voltage on Digital Pins Vy e Input Voltage on Analog I O Pins DP DM AmbientTemperatue AmbientTemperatue Table 5 3 Recommended External Clock Conditions PARAMETER SYMBOL CONDITIONS UNITS _ Clock Frequency meme driven by the external s clock and no connection at XI 100ppm System Clock Duty Cycle XO driven by the external clock and no connection at XI Revision 1 5 11 15 07 12 SMSC USB3280 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc Datasheet Chapter 6 Electrical Characteristics Table 6 1 Electrical Characteristics Supply Pins Note 6 1 PARAMETER SYMBOL CONDITIONS MN TYP max UNITS Unconfigured Current Device Unconfigured HH
8. 30 8 6 Suspend Detection eee eee nae 31 8 7 HS Detection 32 8 8 HS Detection Handshake FS Downstream Facing Port 32 8 9 HS Detection Handshake HS Downstream Facing 34 8 10 HS Detection Handshake Suspend 0 36 8 11 Assertion of Resume 38 8 12 Detection of Resume 39 AS TDOVICO TAU OUS Qusa rt od were 39 8 14 Application Diagram rrr 41 Chapter9 Package Y UP REOR donate dar oder bor 42 SMSC USB3280 Revision 1 5 11 15 07 3 DATASHEET Hi Speed USB Device PHY with UTMI Interface E gt smsc Datasheet List of Figures Figure 2 1 USB3280 Block 1 7 Figure 3 1 USB3280 Pinout Top View Ae 8 Figure 3 2 USB3280 Pinout Bottom 8 Figure 6 1 Full Speed Driver VOH IOH Characteristics for High speed Capable Transceiver 17 Figure 6 2 Full Speed Driver VOL IOL Charact
9. 35 Figure 8 6 HS Detection Handshake Timing Behavior from Suspend 37 Figure 8 7 Resume Timing Behavior HS Mode 38 Figure 8 8 Device Attach 40 Figure 8 9 USB3280 Application Diagram 41 Figure 9 1 USB3280 AEZG 36 Pin QFN Package Outline and Parameters 6 x 6 x 0 90 mm Body Lead Free RoHS Compliant 42 Figure 9 2 QFN 6 6 Tape amp 43 Figure 9 3 Reel Dimensions 44 Revision 1 5 11 15 07 SMSC USB3280 4 DATASHEET Hi Speed USB Device PHY with UTMI Interface Datasheet List of Tables Table 4 1 System Interface Signals 9 Table 4 2 Data Interface Signals 10 Table 4 3 USB SInalS ace ER 696 24055484 10 Table 4 4 Biasing and Clock Oscillator Signals 10 Table 4 5 Power and Ground Signals 11 Table 5 1 Absolute Maximum 5 12 Table 5 2 Recommended Operating Conditions
10. S s Zaa O Sa b te FAO S SE p 21 7 3 Clock and Data Recovery 22 TA rnm 22 THEE RALO pA SSS S 23 7 0 USB 2 0 TranscelVel Hee oe k usa s 26 7 6 1 High Speed and Full Speed Transceivers 26 7 6 2 Termination 26 7 6 3 Blas he soe 27 7 7 Crystal Oscillator and PLL Rn Rotae 27 7 8 Internal Regulators and 27 7 8 1 Internal Regulators 27 7 8 2 Power On Reset 27 7 8 3 lo O ili ur bos saq TO ew gon Q hukun a a ee a a 27 Chapters Application CREER CO MCI CR AE 28 8 1 EIU nek ae DT CORTO PSS sss 28 AE sl m 29 8 3 Test Mode 29 94 SEQ Handling T ony cate Maddow wa are haa ee Se a Eo ee es as 30 65 jisse D80101 s eee ware a k 2 mau
11. given in table below Time is specified as a percentage of the unit interval Ul which represents the nominal bit duration for a 480 Mbit s transmission rate Datasheet 400mV Differential _ ING I Volts ri ov Level 2 Unit Interval Figure 6 4 Eye Pattern for Transmit Waveform and Eye Pattern Definition VOLTAGE LEVEL D D TIME OF UNIT INTERVAL Level 1 525mV in UI following a transition N A 475mV in all others Level 2 525mV in UI following a transition N A 475mV in all others Oe SMSC USB3280 19 Revision 1 5 11 15 07 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc The eye pattern in Figure 6 5 defines the receiver sensitivity requirements for a hub signal applied at test point TP2 of Figure 6 3 or a device without a captive cable signal applied at test point TP3 of Figure 6 3 The corresponding signal levels and timings are given in the table below Timings are given as a percentage of the unit interval Ul which represents the nominal bit duration for a 480 Mbit s transmission rate Datasheet Level 1 400mV Differential Ee EI ec E L Volt s Differential 400mV Differential umi q Figure 6 5 Eye Pattern for Receive Waveform and Eye Pattern Definition TIME OF UNIT INTERVAL Revision 1 5 11 15
12. is never interpreted as data SMSC USB3280 Revision 1 5 11 15 07 25 DATASHEET Hi Speed USB Device PHY with UTMI Interface E gt SMSC 7 6 USB 2 0 Transceiver The SMSC Hi Speed USB 2 0 Transceiver consists of the High Speed and Full Speed Transceivers and the Termination resistors Datasheet 7 6 1 High Speed and Full Speed Transceivers The USB3280 transceiver meets all requirements in the USB 2 0 specification The receivers connect directly to the USB cable This block contains a separate differential receiver for HS and FS mode Depending on the mode the selected receiver provides the serial data stream through the multiplexer to the RX Logic block The FS mode section of the FS HS RX block also consists of a single ended receiver on each of the data lines to determine the correct FS linestate For HS mode support the FS HS RX block contains a squelch circuit to insure that noise is never interpreted as data The transmitters connect directly to the USB cable The block contains a separate differential FS and HS transmitter which receive encoded bit stuffed serialized data from the TX Logic block and transmit it on the USB cable 7 6 2 Termination Resistors The USB3280 transceiver fully integrates all of the USB termination resistors The USB3280 includes the 1 5kQ pull up resistor on DP In addition the 45 high speed termination resistors are also integrated These integrated resistors require no tuning or trimmin
13. transmit state machine will enter a wait state SIE asserts TXVALID to begin a transmission After the SIE asserts TXVALID it can assume that the transmission has started when it detects TXREADY has been asserted The SIE must assume that the USB3280 has consumed a data byte if TXREADY and TXVALID are asserted on the rising edge of CLKOUT The SIE must have valid packet information PID asserted on the DATA bus coincident with the assertion of TXVALID TXREADY is sampled by the SIE on the rising edge of CLKOUT SIE negates TXVALID to complete a packet Once negated the transmit logic will never reassert TXREADY until after the EOP has been generated TXREADY will not re assert until TXVALD asserts again The USB3280 is ready to transmit another packet immediately however the SIE must conform to the minimum inter packet delays identified in the USB 2 0 specification 7 5 RX Logic This block receives serial data from the CRC block and processes it to be transferred to the SIE on the DATA bus The processing involved includes NRZI decoding bit unstuffing and serial to parallel conversion Upon valid assertion of the proper RX control lines by the RX State Machine the RX Logic block will provide bytes to the DATA bus as shown in the figures below The behavior of the Receive State Machine is described below RX DATA 0 Invalid wa AA DATA f invalid eS xx a RAY ALID Figure 7 4 R
14. 0 6 DATASHEET Hi Speed USB Device with UTMI Interface er smo Datasheet Chapter 2 Functional Block Diagram lt 5 z PWR 1 8V PLL and Control Regulator XTAL OSC Clocking TX LOGIC TX TX State Machine Parallel to Serial HS DATA E RESET Conversion SUSPENDN Bit Stuff HS DRIVE ENABLE XCVRSELECT NRZI HS CS ENABLE 2 Encode TERMSELECT DP 1 0 m LINESTATE 1 0 CLKOUT 9 RX z LOGIC lt DATA 7 0 RX State TXVALID 12 TXREADY Serial to Clock Parallel C on Recovery Unit onversion Clock Bit Unstuff and RXVALID Data NRZI Recovery RXACTIVE Decode Elasticity wu Bandgap Voltage Reference Current Reference YN Figure 2 1 USB3280 Block Diagram SMSC USB3280 7 Revision 1 5 11 15 07 DATASHEET Hi Speed USB Device PHY with UTMI Interface E gt SMSE Chapter 3 Pinout Datasheet 36 RBIAS 35 REG_EN 34 VDD3 3 33 VDDA1 8 VDD1 8 29 VDD3 3 28 RXERROR x gt D XCVRSELECT 1 27 RXVALID TERMSELECT 2 26 DATA 0 TXREADY 3 25 DATA 1 SUSPENDN 4 USB2 0 24 DATA 2 TXVALID 5 USB3280 23 _ DATA 3 PHY IC 22 _ DATA 4 21 _ DATA 5 20 _ DATA 6 19 DATAI7 VDD3 3 10 RXACTIVE 11 OPMODE1 12 OPMODEO 13 CLKOUT 0 14 LINE
15. 07 SMSC USB3280 20 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc Datasheet Chapter 7 Functional Overview Figure 2 1 on page 7 shows the functional block diagram of the USB3280 Each of the functions is described in detail below 7 1 Modes of Operation The USB3280 supports an 8 bit bi directional parallel interface CLKOUT runs at 60MHz The 8 bit data bus DATA 7 0 is used for transmit when TXVALID 1 a The 8 bit data bus DATA 7 0 is used for receive when TXVALID 0 7 2 System Clocking This block connects to either an external 24MHz crystal or an external clock source and generates a 480MHz multi phase clock The clock is used in the CRC block to over sample the incoming received data resynchronize the transmit data and is divided down to 60MHz CLKOUT which acts as the system byte clock The PLL block also outputs a clock valid signal to the other parts of the transceiver when the clock signal is stable All UTMI signals are synchronized to the CLKOUT output The behavior of the CLKOUT is as follows Produce the first CLKOUT transition no later than 5 6ms after negation of SUSPENDN The CLKOUT signal frequency error is less than 10 at this time CLKOUT signal will fully meet the required accuracy of 500 no later than 1 4ms after the first transition of CLKOUT In HS mode there is one CLKOUT cycle per byte time The frequency of CLKOUT does not change when the PHY is sw
16. 2 0 8 1 Linestate The voltage thresholds that the LINESTATE 1 0 signals use to reflect the state of DP and DM depend on the state of XCVRSELECT LINESTATE 1 0 uses HS thresholds when the HS transceiver is enabled XCVRSELECT 0 and FS thresholds when the FS transceiver is enabled XCVRSELECT 1 There is not a concept of variable single ended thresholds in the USB 2 0 specification for HS mode The HS receiver is used to detect Chirp J or K where the output of the HS receiver is always qualified with the Squelch signal If squelched the output of the HS receiver is ignored In the USB3280 as an alternative to using variable thresholds for the single ended receivers the following approach is used Table 8 1 Linestate States STATE OF DP DM LINES LINESTATE 1 0 FULL SPEED HIGH SPEED CHIRP MODE XCVRSELECT 1 XCVRSELECT 0 XCVRSELECT 0 LS 0 TERMSELECT 1 TERMSELECT 0 TERMSELECT 1 ISquelch amp HS Differential Receiver Invalid ISquelch amp IHS Differential Receiver 5 In HS mode 3ms of USB activity IDLE state signals a reset The SIE monitors LINESTATE 1 0 for the IDLE state To minimize transitions on LINESTATE 1 0 while in HS mode the presence of ISquelch is used to force LINESTATE 1 0 to a J state Revision 1 5 11 15 07 28 SMSC USB3280 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc Datasheet 8 2 OPMODES The OPMODE 1 0 pins allow control of the operat
17. ELECT to HS mode and begins the transmission of all O s data which asserts a HS K chirp on the bus T1 The device chirp must last at least 1 0ms and must end no later than 7 0ms after HS Reset TO At time T1 the device begins listening for a chirp sequence from the downstream facing port If the downstream facing port is HS capable then it will begin generating an alternating sequence of Chirp K s and Chirp J s after the termination of the chirp from the device T2 After the device sees the valid chirp sequence Chirp K J K J K J T6 it will enter HS mode by setting TERMSELECT to HS mode T7 Figure 8 4 provides a state diagram for Chirp K J K J K J validation Prior to the end of reset T9 the device port must terminate the sequence of Chirp K s and Chirp J s T8 and assert SEO T8 T9 Note that the sequence of Chirp K s and Chirp J s constitutes bus activity Start Chirp K J K J K J detection Chirp K State Chirp Count Chirp Count 6 amp ISEO Figure 8 4 Chirp K J K J K J Sequence Detection State Diagram The Chirp K J K J K J sequence occurs too slow to propagate through the serial data path therefore LINESTATE signal transitions must be used by the SIE to step through the Chirp K J K J K J state diagram where K State is equivalent to LINESTATE K State and J State is equivalent to LINESTATE J State The SIE must employ a counter Chirp Count to count the number of Chirp K and Chirp J states Not
18. FS Idle Current FS idle not data transfer FS Transmit Current lAVG FSTX FS current during data EN 5 transmit FS Receive Current lAVG FSRX FS current during data f receive HS ide Current 4S rox HS Transmit Current lAVG HSTX HS current during data 62 4 mA transmit HS Receive Current lAVG HSRX HS current during data receive Low Power Mode IDD LPM VBUS 15 pull down and 1 5 pull up resistor currents not included Note 6 1 Vpp33 3 0 to 3 6V Vss TA 40 C to 85 C unless otherwise specified Table 6 2 DC Electrical Characteristics Logic Pins Note 6 2 PARAMETER SYMBOL CONDITIONS m UNITS Low Level Input Voltage C Low Level Output Voltage Level Low Level Output Voltage Voltage Vo j m lo 8mA o 0 5 Note 6 2 Vppa3 3 0 to 3 6V Vss OV TA 40 C to 85 C unless otherwise specified SMSC USB3280 13 Revision 1 5 11 15 07 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc Datasheet Table 6 3 DC Electrical Characteristics Analog I O Pins DP DM Note 6 3 PARAMETER SYMBOL CONDITIONS MN MAX UNITS FS FUNCTIONALITY FUNCTIONALITY Input levels Differential Receiver Input VDIES V DP V DM Sensitivity Differential Receiver 5 Voltage Single Ended Receiver Low VILSE V Level Input Voltage Single Ended Receiver High VIHSE 2 0 V Level Input Voltage Single En
19. FS mode TERMSELECT and XCVRSELECT FS enabled so the behavior for a HS device is identical to that of a FS device The SIE uses the LINESTATE signals to determine when the USB transitions from the J to the K state and finally to the terminating FS EOP SEO for 1 25us 1 5ys The resume signaling FS will be asserted for at least 20ms At the beginning of this period the SIE may negate SUSPENDN allowing the transceiver and its oscillator to power up and stabilize The FS EOP condition is relatively short SIEs that simply look for an SEO condition to exit suspend mode do not necessarily give the transceiver s clock generator enough time to stabilize It is recommended that all SIE implementations key off the J to K transition for exiting suspend mode SUSPENDN 1 And within 1 25us after the transition to the SEO state low speed EOP the SIE must enable normal operation i e enter HS or FS mode depending on the mode the device was in when it was suspended If the device was in FS mode then the SIE leaves the FS terminations enabled After the SEO expires the downstream port will assert a J state for one low speed bit time and the bus will enter a FS Idle state maintained by the FS terminations If the device was in HS mode then the SIE must switch to the FS terminations before the SEO expires lt 1 25 5 After the SEO expires the bus will then enter a HS IDLE state maintained by the HS terminations 8 13 HS Dev
20. Interface SMSE Datasheet Table 6 5 Dynamic Characteristics Digital UTMI Pins Note 6 5 PARAMETER SYMBOL CONDITIONS MN MAX UNITS DATA 7 0 Tpp Output Delay Measured from PHY output to the RXVALID rising edge of CLKOUT RXACTIVE RXERROR LINESTATE 1 0 TXREADY DATA 7 0 Setup Time Measured from PHY input to the TXVALID rising edge of CLKOUT 0 XCVRSELECT TERMSELECT Loos NE 0 Hold time Measured from the rising egde of TeAAD 0 CLKOUT to the PHY input signal edge 0 XcVRSELECT Mo Note 6 5 Vppa4 3 0 to 3 6V Vss OV TA 40 C to 85 C unless otherwise specified 6 1 Driver Characteristics of Full Speed Drivers in High Speed Capable Transceivers The USB3280 uses a differential output driver to drive the USB data signal onto the USB cable Figure 6 1 Full Speed Driver VOH IOH Characteristics for High speed Capable Transceiveron page 17 shows the V I characteristics for a full speed driver which is part of a high speed capable transceiver The normalized V I curve for the driver must fall entirely inside the shaded region The region is bounded by the minimum driver impedance above 40 5 Ohm and the maximum driver impedance below 49 5 Ohm The output voltage must be within 10mV of ground when no current is flowing in or out of the pin Revision 1 5 11 15 07 16 SMSC USB3280 DATASHEET Hi Speed USB Device PHY with UTMI Interface ee smse Datas
21. ROM 1 75 4 25 3 55 3 70 3 85 4 5 05 S K ILIEV ADDED PARAGRAPHS 1 TO 6 IN MAIN SPEC BODY amp DWG AS ATTACHMENT 7 11 05 S K ILIEV EXPOSED PAD 4 pes Lil 4X 45 0 6 OPTIONAL 36X 0 2 MIN s _36X b VIEW BOTTOM VIEW COMMON DIMENSIONS NOTE REMARK OVERALL PKG HEIGH STANDOFF MOLD THICKNESS 4x 0 2 AS 0 20 R A EAD FRAME THICKNESS C Y BODY SIZE DUD SU X Y MOLD SIZ cv X PY EXPOSED PAD TERMINAL LENGT SIDE VIEW b 0 18 0 25 0 30 2 ERMINAL WIDTH TERMINAL COPLANARITY D2 E2 VARIATIONS WAX NOTE CATALOG PART rN USB3280 USB2502 3 D V EWS UNLESS OTHERWISE SPECIFIED THIRD ANGLE PROJECTION DIMENSIONS ARE IN MILLIMETERS AND TOLERANCES ARE 80 ARKAY DRIVE E HAUPPAUGE NY 11788 DECIMAL ANGULAR N USA 1 i 0 05 NOT ES X XXX 0 025 1 ALL DIMENSIONS ARE IN MILLIMETER DIM AND TOL PER ASME 145 1994 DATE OUTLINE 2 POSITION TOLERANCE OF EACH TERMINAL IS 0 05mm AT MAXIMUM MATERIAL CONDITION DIMENSIONS _ DRAWN b APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0 15 AND 0 30 mm FROM THE S K ILIEV 12 6 04 36 TERMINAL QFN 6x6mm BODY 0 5mm PITCH TERMINAL TIP i CHECKED DWG NUMBER REV
22. S OR FOR LOST DATA PROFITS SAVINGS OR REVENUES OF ANY KIND REGARDLESS OF THE FORM OF ACTION WHETHER BASED ON CONTRACT TORT NEGLIGENCE OF SMSC OR OTHERS STRICT LIABILITY BREACH OF WARRANTY OR OTHERWISE WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Revision 1 5 11 15 07 SMSC USB3280 2 DATASHEET Hi Speed USB Device PHY with UTMI Interface Datasheet Table of Contents Chapter 1 General Description aa 6 11 ProductUD asenpltl fi ies ciue de duced oped tes 6 Chapter 2 Functional Block Diagram 7 Chiper d DPP sss Chapter 4 Interface Signal Definition 9 Chapter5 Limiting Values 2 4442 9 isu 12 Chapter 6 Electrical Characteristics 13 6 1 Driver Characteristics of Full Speed Drivers in High Speed Capable Transceivers 16 6 2 High speed Signaling Eye Patterns 18 Chapter 7 Functional 21 71 Modes Ol u u u uy u i puk k wQ ERO 21 Te OV SICMMCIOCKINGs marek
23. SMSC USB3280 SUCCESS BY DESIGN PRODUCT FEATURES Available in a 36 pin lead free RoHS compliant 6 x 6 x 0 90mm QFN package Interface compliant with the UTMI specification 60MHz 8 bit bidirectional interface Only one required power supply 3 3V USB IF Hi Speed certified to USB 2 0 electrical specification Supports 480Mbps Hi Speed HS and 12Mbps Full Speed FS serial data transmission rates Integrated 45 and 1 5kQ termination resistors reduce external component count Internal short circuit protection of DP and DM lines On chip oscillator operates with low cost 24MHz crystal Latch up performance exceeds 150mA per EIA JESD 78 Class Il ESD protection levels of 5kV HBM without external protection devices SYNC and EOP generation on transmit packets and detection on receive packets NRZI encoding and decoding Bit stuffing and unstuffing with error detection Supports the USB suspend state HS detection HS Chirp Reset and Resume Support for all test modes defined in the USB 2 0 specification 55mA Unconfigured Current typical ideal for bus powered applications 83uA suspend current typical ideal for battery powered applications Industrial Operating Temperature 409C to 85 SmS USB3280 USB Hi Speed USB Device PHY with UTMI Interface Datasheet Applications The USB3280 is the ideal companion to any ASIC SoC or FPGA solution designed with a UTMI Hi Speed USB dev
24. STATE1 15 LINESTATEO 16 VDD1 8 17 VDD3 3 18 Figure 3 1 USB3280 Pinout Top View EXPOSED GND PAD Figure 3 2 USB3280 Pinout Bottom View The flag of the QFN package must be connected to ground Revision 1 5 11 15 07 SMSC USB3280 8 DATASHEET Hi Speed USB Device PHY with UTMI Interface eer smsc Datasheet Chapter 4 Interface Signal Definition Table 4 1 System Interface Signals ACTIVE DIRECTION LEVEL DESCRIPTION Input High Reset Reset all state machines After coming out of reset must wait 5 rising edges of clock before asserting TXValid for transmit See Section 7 8 3 XCVRSELECT Input N A Transceiver Select This signal selects between the FS XSEL and HS transceivers 0 HS transceiver enabled 1 FS transceiver enabled TERMSELECT Input N A Termination Select This signal selects between the FS TSEL and HS terminations 0 HS termination enabled 1 FS termination enabled SUSPENDN Input Low Suspend Places the transceiver in a mode that draws SPDN minimal power from supplies Shuts down all blocks not necessary for Suspend Resume operation While suspended TERMSELECT must always be in FS mode to ensure that the 1 5kQ pull up on DP remains powered 0 Transceiver circuitry drawing suspend current 1 Transceiver circuitry drawing normal current CLKOUT Output Rising Edge System Clock This output is used for clocking receive CLK and transmit parallel data at 60MHz OPMODE 1 0
25. USB3280 regulators are designed to generate a 1 8 volt supply for the USB3280 only Using the regulators to provide current for other circuits is not recommended and SMSC does not guarantee USB performance or regulator stability Power On Reset POR The USB3280 provides an internal POR circuit that generates a reset pulse once the PHY supplies are stable Reset Pin The UTMI Digital can be reset at any time with the RESET pin The RESET pin of the USB3280 be asynchronously asserted and de asserted so long as it is held in the asserted state continuously for a duration greater than one CLKOUT cycle The RESET input may be asserted when the USB3280 CLKOUT signal is not active i e in the suspend state caused by asserting the SUSPENDN input but reset must only be de asserted when the USB3280 CLKOUT signal is active and the RESET has been held asserted for a duration greater than one CKOUT clock cycle No other PHY digital input signals may change state for two CLKOUT clock cycles after the de assertion of the reset signal Revision 1 5 11 15 07 27 DATASHEET Hi Speed USB Device with UTMI Interface E gt SMSE Datasheet Chapter 8 Application Notes The following sections consist of select functional explanations to aid in implementing the USB3280 into a system For complete description and specifications consult the USB 2 0 Transceiver Macrocell Interface Specification and Universal Serial Bus Specification Revision
26. YRSELECT T pi at ZEN TERMSELECT TXVALID r SOF DP DM 2 BR Device Chirp No Downstream Facing Port Chirps Figure 8 3 HS Detection Handshake Timing Behavior FS Mode Table 8 6 HS Detection Handshake Timing Values FS Mode TIMING PARAMETER DESCRIPTION VALUE TO HS Handshake begins DP pull up enabled HS 0 reference terminations disabled T1 Device enables HS Transceiver and asserts Chirp TO lt T1 lt HS Reset TO 6 0ms K on the bus T2 Device removes Chirp K from the bus 1ms T1 1 0 ms lt T2 minimum width HS Reset T0 7 0ms TS Earliest time when downstream facing port may 2 lt lt T2 100us assert Chirp KJ sequence the bus T4 Chirp not detected by the device Device revertsto 2 1 0ms lt T4 lt FS default state and waits for end of reset T2 2 5ms Earliest time at which host port may end reset HS Reset T0 10ms Notes occur to 4ms after HS Reset The SIE must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration SMSC USB3280 Revision 1 5 11 15 07 33 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc 8 9 HS Detection Handshake HS Downstream Facing Port Datasheet Upon entering the HS Detection process XCVRSELECT and TERMSELECT are in FS mode The DP pull up is asserted and the HS terminations are disabled The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding XCVRS
27. achine will reenter the RX Wait state and begin looking for the next packet Datasheet The behavior of the Receive State Machine is described below RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT Inthe RX Wait state the receiver is always looking for SYNC The USB3280 asserts RXACTIVE when SYNC is detected Strip SYNC state a The USB3280 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty Strip EOP state a When RXACTIVE is asserted RXVALID will be asserted if the RX Holding Register is full RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time This will occur if 8 stuffed bits have been accumulated The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted RX Data state Figure 7 5 shows the timing relationship between the received data DP DM RXVALID RXACTIVE RXERROR and DATA signals Notes s USB 2 0 Transceiver does NOT decode Packet ID s PIDs They are passed to the SIE for decoding a Figure 7 5 Figure 7 6 and Figure 7 7 are timing examples of HS FS PHY when it is in HS mode When a HS FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time The Receive State Machine assumes that the SIE captures the data on the DATA bus if RXACTIVE and RXVALID are asserted In FS mode RXVALID will only be asserted for one CLKOUT per byte time a In Figure 7 5 Figure 7 6
28. and Figure 7 7 the SYNC pattern on DP DM is shown as one byte long The SYNC pattern received by a device can vary in length These figures assume that all but the last 12 bits have been consumed by the hubs between the device and the host controller CLKOUT REAL TIVE NENNEN EI RXDATA 7 0 RXERROR ZEE Figure 7 5 Receive Timing for a Handshake Packet no CRC Revision 1 5 11 15 07 SMSC USB3280 24 DATASHEET Hi Speed USB Device PHY with UTMI Interface Datasheet RXACTIVE i IER RXDATA 7 0 X DATA DATA p CRC 5 Computation Figure 7 6 Receive Timing for Setup Packet BZAZCAZAIZAZI Ceo Y coma Y sara Y parq 290 FXERROR 4 CRO 16 Computation Figure 7 7 Receive Timing for Data Packet with CRC 16 The receivers connect directly to the USB cable The block contains a separate differential receiver for HS and FS mode Depending on the mode the selected receiver provides the serial data stream through the mulitplexer to the RX Logic block The FS mode section of the FS HS RX block also consists of a single ended receiver on each of the data lines to determine the correct FS LINESTATE For HS mode support the FS HS RX block contains a squelch circuit to insure that noise
29. and its oscillator to power up and stabilize Figure 8 7 illustrates the behavior of a device returning to HS mode after being suspended At T4 a device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high To generate resume signaling FS the device is placed in the Disable Bit Stuffing and NRZI encoding Operational Mode OPMODE 1 0 10 TERMSELECT and XCVRSELECT must be in FS mode TXVALID asserted and all 0 s data is presented on the DATA bus for at least 1ms T1 T2 time SUSPENDN SC VE SELES ES ES TAYVALID __ F8 Idle JJ State Figure 8 7 Resume Timing Behavior HS Mode Table 8 9 Resume Timing Values HS Mode TIMING PARAMETER DESCRIPTION VALUE Internal device event initiating the resume reference process Device asserts FS K on the bus to signal TO lt T1 lt 10ms resume request to downstream port The device releases FS K on the bus However T1 1 0 lt 2 lt T1 15ms by this time the K state is held by downstream port s Downstream port asserts SE0 T1 20ms Latest time at which a device which was 1 33us 2 Low speed bit times previously in HS mode must restore HS mode after bus activity stops Revision 1 5 11 15 07 38 SMSC USB3280 DATASHEET Hi Speed USB Device PHY with UTMI Interface Datasheet E gt smsc 8 12 Detection of Resume Resume signaling always takes place in
30. d control signals Datasheet RAC TIE eu ID E Figure 7 2 FS CLK Relationship to Receive Data and Control Signals 7 3 Clock and Data Recovery Circuit This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer The Elasticity Buffer is used to compensate for differences between the transmitting and receiving clock domains The USB 2 0 specification defines a maximum clock error of 1000ppm of drift 7 4 TX Logic This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit operations These operations include parallel to serial conversion bit stuffing and NRZI encoding Upon valid assertion of the proper TX control lines by the SIE and TX State Machine the TX LOGIC block will synchronously shift at either the FS or HS rate the data to the FS HS TX block to be transmitted on the USB cable Data transmit timing is shown in Figure 7 3 TAVALID BC oat Jona Yonc enc TAREADY para ours enc Y eee Y eor Figure 7 3 Transmit Timing for a Data Packet Revision 1 5 11 15 07 SMSC USB3280 22 DATASHEET Hi Speed USB Device PHY with UTMI Interface er sms Datasheet The behavior of the Transmit State Machine is described below Asserting a RESET forces the transmit state machine into the Reset state which negates TXREADY When RESET is negated the
31. ded Receiver VuvssE 0 050 0 150 Hysteresis Output Levels Levels Low Level Loc NN Voltage VrsoL up resistor on DP 0 3 V RI 155 to Vppa5 High Level Output Voltage VrsoH Pull down resistor on DP 2 8 3 6 V DM 15kO to GND Driver Impedance for ZHSDRV Steady state drive HS and See Figure 6 1 Input Impedance Impedance Zwe Zne TX TX RPU disabled disabled Pull up Resistor Impedance HEISE Bus Idle 900 1 975 Pull up Resistor Impedance 1 425 2 E m3 309 09 Termination Voltage For Pull VTERM 3 0 E 6 up Resistor On Pin DP Input levels HS Differential Input Sensitivity V DP V DM 100 HS Data Signaling Common VcMHS Mode Voltage Range HS Squelch Detection Vusso Squelch Threshold Threshold Differential Output Levels High Speed Low Level VusoL 450 load 10 10 mV Output Voltage DP DM referenced to GND Revision 1 5 11 15 07 14 SMSC USB3280 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc Table 6 3 DC Electrical Characteristics Analog I O Pins Tm iti 6 3 PARAMETER SYMBOL CONDITIONS UNITS High Speed High Level 450 INL Output Voltage DP DM referenced to GND High Speed IDLE Level VoLHs 450 load Output Voltage DP DM referenced to GND Chirp J Output Voltage VCHIRPJ HS termination resistor 700 1100 mV Differential disabled pull up resistor connected 450 load Datasheet Chirp K Output Volta
32. e that LINESTATE does not filter the bus signals so the requirement that a bus state must be continuously asserted for 2 5us must be verified by the SIE sampling the LINESTATE signals Revision 1 5 11 15 07 SMSC USB3280 34 DATASHEET Hi Speed USB Device PHY with UTMI Interface SMSC Datasheet T1 T2 4 TB T7 T8 T8 T3 OPNODE OPMODE 1 XCVRSELECT 7 7 TERMSELECT T ITT TT T7 TXVALID Device K J SED SOF Device Downstream HS Mode Port Facing Part Chirps Chirp DP DM Figure 8 5 HS Detection Handshake Timing Behavior HS Mode Table 8 7 Reset Timing Values TIMING PARAMETER DESCRIPTION VALUE HS Handshake begins DP pull up enabled HS reference terminations disabled Device asserts Chirp K on bus 00000 asserts Device asserts Chirp K on bus 00000 K on the bus TO lt T1 lt lt 1 lt HS Reset 6 0ms Reset lt 1 lt HS Reset 6 0ms 6 0ms Device removes Chirp K from the bus 1 ms TO 1 0ms lt 2 lt minimum width HS Reset TO 7 0ms Downstream facing port asserts Chirp K on the T2 lt lt 72 100us bus 4 Downstream facing port toggles Chirp to Chiro 40us lt T4 lt 60 5 on the bus Downstream facing port toggles Chirp J to Chiro T4 40us lt 5 lt T4 60 5 on the bus Device detects downstream port chip detects downstream port Device detects do
33. e transceiver s oscillator to stabilize The device does not generate any transitions of the CLKOUT signal until it is usable where usable is defined as stable to within 10 of the nominal frequency and the duty cycle accuracy 50 5 The first transition of CLKOUT occurs at T1 The SIE then sets OPMODE to Disable Bit Stuffing and NHZI encoding XCVRSELECT to HS mode and must assert a Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration If CLKOUT is 1096 fast 66MHz then Chirp will be 1 0ms If CLKOUT is 1096 slow 54 MHz then Chirp will be 1 2ms The 5 6ms requirement for the first CLKOUT transition after SUSPENDN ensures enough time to assert a 1ms Chirp K and still complete before T3 Once the Chirp K is completed T3 the SIE can begin looking for host chirps and use CLKOUT to time the process At this time the device follows the same protocol as in Section 8 9 HS Detection Handshake HS Downstream Facing Port for completion of the High Speed Handshake Revision 1 5 11 15 07 SMSC USB3280 36 DATASHEET Hi Speed USB Device PHY with UTMI Interface ee sms Datasheet TO T1 T2 T3 T4 OPMODE 0 OPMODE 1 XCVRSELECT TERMSELECT SUSPENDN TXVALID CLK60 _ j DP DM J PED lt TPu T CLK power up time Device Chirp K Look for host chirps Figure 8 6 HS Detection Handshake Timing Behavior from Suspend To detect the assertion of the downstream Chirp K s and Chirp J s for 2 5us
34. eceive Timing for Data with Unstuffed Bits The assertion of RESET will force the Receive State Machine into the Reset state The Reset state deasserts RXACTIVE and RXVALID When the RESET signal is deasserted the Receive State Machine enters the RX Wait state and starts looking for a SYNC pattern on the USB When a SYNC pattern is detected the state machine will enter the Strip SYNC state and assert RXACTIVE The length of the received Hi Speed SYNC pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end of five hubs As a result the state machine may remain in the Strip SYNC state for several byte times before capturing the first byte of data and entering the RX Data state After valid serial data is received the state machine enters the RX Data state where the data is loaded into the RX Holding Register on the rising edge of CLKOUT and RXVALID is asserted The SIE must clock the data off the DATA bus on the next rising edge of CLKOUT If OPMODE Normal then stuffed bits are stripped from the data stream Each time 8 stuffed bits are accumulated the state machine will enter the RX Data Wait state negating RXVALID thus skipping a byte time SMSC USB3280 23 Revision 1 5 11 15 07 DATASHEET Hi Speed USB Device with UTMI Interface E gt smsc When the EOP is detected the state machine will enter the Strip EOP state and negate RXACTIVE and RXVALID After the EOP has been stripped the Receive State M
35. en the upstream port is asserting a soft SEO and the USB is in a J state indicating a suspend condition By time 4 the device must be fully suspended SUSPENDN L ALNVRSELECT i TERMSELECT Last Soseo 7 2 Device is suspended Figure 8 2 Suspend Timing Behavior HS Mode Table 8 5 Suspend Timing Values HS Mode TIMING PARAMETER DESCRIPTION VALUE HS Reset TO End of last 2 signaling either reset reference or a SUSPE The time at which the device must place itself HS Reset 3 0ms lt T1 lt HS Reset in FS mode bus activity stops 3 125ms SIE samples LINESTATE If LINESTATE T1 100 us lt 2 lt then the initial 5 on the bus 1 had Ti 875us been due to a state the SIE remains in HS mode The earliest time where a device can issue HS Reset T0 5ms Resume signaling The latest time that a device must actually be HS Reset TO 10ms suspended drawing no more than the suspend current from the bus SMSC USB3280 31 Revision 1 5 11 15 07 DATASHEET Hi Speed USB Device with UTMI Interface E gt smsc 8 7 HS Detection Handshake The High Speed Detection Handshake process is entered from one of three states suspend active FS or active HS The downstream facing port asserting an SE0 state on the bus initiates the HS Detection Handshake Depending on the initial state an SE0 condition can be asserted
36. eristics for High speed Capable Transceiver 17 Figure 6 3 Eye Pattern Measurement 18 Figure 6 4 Eye Pattern for Transmit Waveform and Eye Pattern Definition 19 Figure 6 5 Eye Pattern for Receive Waveform and Eye Pattern Definition 20 Figure 7 1 FS CLK Relationship to Transmit Data and Control Signals 21 Figure 7 2 FS CLK Relationship to Receive Data and Control Signals 22 Figure 7 3 Transmit Timing for a Data Packet 22 Figure 7 4 Receive Timing for Data with Unstuffed Bits 23 Figure 7 5 Receive Timing for a Handshake Packet 24 Figure 7 6 Receive Timing for Setup 1 25 Figure 7 7 Receive Timing for Data Packet with 16 25 Figure 8 1 Reset Timing Behavior HS Mode 30 Figure 8 2 Suspend Timing Behavior HS 31 Figure 8 3 HS Detection Handshake Timing Behavior FS Mode 33 Figure 8 4 Chirp K J K J K J Sequence Detection State Diagram 34 Figure 8 5 HS Detection Handshake Timing Behavior HS Mode
37. es as much of the responsibility for timing events on to the SIE as possible and the SIE requires a stable CLKOUT signal to perform accurate timing In case 2 and 3 above CLKOUT has been running and is stable however in case 1 the USB3280 is reset from a suspend state and the internal oscillator and clocks of the transceiver are assumed to be powered down A device has up to 6ms after the release of SUSPENDN to assert a minimum of a 1ms Chirp K 8 8 HS Detection Handshake FS Downstream Facing Port Upon entering the HS Detection process T0 XCVRSELECT and TERMSELECT are in FS mode The DP pull up is asserted and the HS terminations are disabled The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding XCVRSELECT to HS mode and begins the transmission of all 05 data which asserts a HS K chirp on the bus T1 The device chirp must last at least 1 0ms and must end no later than 7 0ms after HS Reset TO At time T1 the device begins listening for a chirp sequence from the host port If the downstream facing port is not HS capable then the HS asserted by the device is ignored and the alternating sequence of HS Chirp K s and J s is not generated If no chirps are detected T4 by the device it will enter FS mode by returning XCVRSELECT to FS mode Revision 1 5 11 15 07 SMSC USB3280 32 DATASHEET Hi Speed USB Device PHY with UTMI Interface SMSE Datasheet T Ti T2 T4 Th OPMODED OPMODE 1 AC
38. from 0 to 4 ms before initiating the HS Detection Handshake These states are described in the USB 2 0 specification Datasheet There are three ways in which a device may enter the HS Handshake Detection process 1 If the device is suspended and it detects an SEO state on the bus it may immediately enter the HS handshake detection process 2 f the device is in FS mode and an SEO state is detected for more than 2 5us it may enter the HS handshake detection process 3 If the device is in HS mode and an SEO state is detected for more than 3 0ms it may enter the HS handshake detection process In HS mode a device must first determine whether the SEO state is signaling a suspend or a reset condition To do this the device reverts to FS mode by placing XCVRSELECT and TERMSELECT into FS mode The device must not wait more than 3 125ms before the reversion to FS mode After reverting to FS mode no less than 100us and no more than 875us later the SIE must check the LINESTATE signals If a J state is detected the device will enter a suspend state If an SEO state is detected then the device will enter the HS Handshake detection process In each case the assertion of the SEO state on the bus initiates the reset The minimum reset interval is 10ms Depending on the previous mode that the bus was in the delay between the initial assertion of the SEO state and entering the HS Handshake detection can be from 0 to 4ms This transceiver design push
39. g The state of the resistors is determined by the operating mode of the PHY The possible valid resistor combinations are shown in Table 7 1 activates the 1 5kO DP pull up resistor EN activates the 450 DP and DM high speed termination resistors Table 7 1 DP DM Termination vs Signaling Mode RESISTOR UTMI INTERFACE SETTINGS SETTINGS RPU DP EN HSTERM EN SIGNALING MODE m o Feud mw e mem eme mem m eme wamak m XCVRSELECT TERMSELECT OPMODE 1 0 Revision 1 5 11 15 07 SMSC USB3280 26 DATASHEET Hi Speed USB Device PHY with UTMI Interface Datasheet 7 6 3 7 7 7 8 7 8 1 7 8 2 7 8 3 SMSC USB3280 E gt smsc Bias Generator This block consists of an internal bandgap reference circuit used for generating the high speed driver currents and the biasing of the analog circuits This block requires an external 12kQ 1 tolerance external reference resistor connected from RBIAS to ground Crystal Oscillator and PLL The USB3280 uses an internal crystal driver and PLL sub system to provide a clean 480MHz reference clock that is used by the PHY during both transmit and receive The USB3280 requires a clean 24MHz crystal or clock as a frequency reference If the 24MHz reference is noisy or off frequency the PHY may not operate correct
40. ge VCHIRPK HS termination resistor 500 mV Differential disabled pull up resistor connected 450 load Leakage Current Port Capacitance Transceiver Input Capacitance Pin to GND Note 6 3 Vpp33 3 0 to 3 61 OV TA 40 C to 85 C unless otherwise specified Table 6 4 Dynamic Characteristics Analog I O Pins DP DM Note 6 4 PARAMETER SYMBOL CONDITIONS MAX UNITS FS Output Driver Timing FS Output Driver Timing Driver Timing Rise Time 5 19 to 90 4 20 ns Fall Time d 10 to 90 of 4 20 ns VoH Output Signal Crossover Vcns Excluding the first 1 3 2 0 V Voltage transition from IDLE state Differential Rise Fall Time FRFM Excluding the first 111 1 Matching transition from IDLE state HS Output Driver Timing HS Output Driver Timing Driver Timing Difer niial Fall Time Driver Waveform pattern of Template 1 Requirements in USB 2 0 specification 6 2 High High Speed Mode Timing High Speed Mode Timing Timing Receiver Waveform Eye pattern of Template 4 Requirements in USB 2 0 specification Figure 6 2 Data Source Jitter and Eye pattern of Template 4 See Receiver Jitter Tolerance in USB 2 0 specification Figure 6 2 Note 6 4 Vppa5 3 0 to 3 6V Vss T4 40 C to 85 C unless otherwise specified SMSC USB3280 15 Revision 1 5 11 15 07 DATASHEET Hi Speed USB Device PHY with UTMI
41. heet Drive High Tout mA Slope 1 49 5 Ohm 6 1 IVOH 10 71 Slope 1 40 5 Ohm 0 0 566 VOH 0 698 VOH VOH Vout Volts Figure 6 1 Full Speed Driver VOH IOH Characteristics for High speed Capable Transceiver Drive Low Tout SI 1 40 5 Oh m A Test Limit 10 71 IVOHI rT slope 1 49 5 Ohm Vout Volts Figure 6 2 Full Speed Driver VOL IOL Characteristics for High speed Capable Transceiver SMSC USB3280 Revision 1 5 11 15 07 17 DATASHEET 6 2 Revision 1 5 11 15 07 SMSC Hi Speed USB Device PHY with UTMI Interface Datasheet High speed Signaling Eye Patterns High speed USB signals are characterized using eye patterns For measuring the eye patterns 4 points have been defined see Figure 6 3 The Universal Serial Bus Specification Rev 2 0 defines the eye patterns in several templates The two templates that are relevant to the PHY are shown below 1 TP2 USB Cable zm Transceiver B Transceiver Connector Hub Circuit Board Device Circuit Board Figure 6 3 Eye Pattern Measurement Planes 18 SMSC USB3280 DATASHEET Hi Speed USB Device PHY with UTMI Interface E gt smsc The eye pattern in Figure 6 4 defines the transmit waveform requirements for a hub measured at TP2 of Figure 6 3 or a device without a captive cable measured at TP3 of Figure 6 3 The corresponding signal levels and timings are
42. ice peripheral core The USB3280 is well suited for Cell Phones Players Scanners External Hard Drives Digital Still and Video Cameras Portable Media Players Entertainment Devices Printers DATASHEET Revision 1 5 11 15 07 Hi Speed USB Device PHY with UTMI Interface smsc Datasheet ORDER NUMBER S USB3280 AEZG FOR 36 PIN QFN LEAD FREE ROHS COMPLIANT PACKAGE USB3280 AEZG TR FOR 36 PIN QFN LEAD FREE ROHS COMPLIANT PACKAGE TAPE AND REEL Reel Size is 3000 pieces SMSE 80 ARKAY DRIVE HAUPPAUGE NY 11788 631 435 6000 FAX 631 273 3123 Copyright 2007 SMSC or its subsidiaries All rights reserved Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications Consequently complete information sufficient for construction purposes is not necessarily given Although the information has been checked and is believed to be accurate no responsibility is assumed for inaccuracies SMSC reserves the right to make changes to specifications and product descriptions at any time without notice Contact your local SMSC sales office to obtain the latest specifications before placing your product order The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others All sales are expressly cond
43. ice Attach SMSC USB3280 Figure 8 8 demonstrates the timing of the USB3280 control signals during a device attach event When a HS device is attached to an upstream port power is asserted to the device and the device sets XCVRSELECT and TERMSELECT to FS mode time 1 Vpus is the power available on the USB cable Device Reset in Figure 8 8 indicates that Vays is within normal operational range as defined in the USB 2 0 specification The assertion of Device Reset TO by the upstream port will initialize the device By monitoring LINESTATE the SIE state machine knows to set the XCVRSELECT and TERMSELECT signals to FS mode 1 The standard FS technique of using a pull up resistor on DP to signal the attach of a FS device is employed The SIE must then check the LINESTATE signals for SEO If LINESTATE SEO is asserted at time T2 then the upstream port is forcing the reset state to the device i e Driven SEO The device will then reset itself before initiating the HS Detection Handshake protocol Revision 1 5 11 15 07 39 DATASHEET Hi Speed USB Device PHY with UTMI Interface Datasheet Vous DeviceReset J XCYRSELECT s J 2299 e TERMSELECT J DP DN HS Detection Handshake Figure 8 8 Device Attach Behavior Table 8 10 Attach and Reset Timing Values TIMING PARAMETER DESCRIPTION VALUE TO Vbus Valid 0 reference T1 Maximum time from Vbus valid to when the device TO 100ms lt T1 m
44. ing modes Table 8 2 Operational Modes MODE 1 0 STATE STATER STATE NAME DESCRIPTION Normal Transceiver operates with normal USB data encoding and decoding Non Driving Allows the transceiver logic to support a soft disconnect feature which tri states both the HS and FS transmitters and removes any termination from the USB making it appear to an upstream port that the device has been disconnected from the bus 10 2 Disable Bit Stuffing Disables bitstuffing and NRZI encoding logic so that 1 s loaded and NRZI encoding from the DATA bus become 5 on the DP DM and 0 s become K s 11 The OPMODE 1 0 signals are normally changed only when the transmitter and the receiver are quiescent i e when entering a test mode or for a device initiated resume When using OPMODE 1 0 10 state 2 OPMODES are set and then 5 60MHz clocks later TXVALID is asserted In this case the SYNC and EOP patterns are not transmitted The only exception to this is when OPMODE 1 0 is set to state 2 while TXVALID has been asserted the transceiver is transmitting a packet in order to flag a transmission error In this case the USB3280 has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also be transmitted to properly terminate the packet Changing the OPMODE 1 0 signals under all other conditions while the transceiver is transmitting or receiving data will generate undefined results Under no ci
45. is asserted the SIE must always TXR have data available for clocking into the TX Holding Register on the rising edge of CLKOUT TXREADY is an acknowledgement to the SIE that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus If TXVALID is negated TXREADY can be ignored by the SIE RXVALID Output High Receive Data Valid Indicates that the DATA bus has received valid RXV data The Receive Data Holding Register is full and ready to be unloaded The SIE is expected to latch the DATA bus on the rising edge of CLKOUT RXACTIVE Output High Receive Active Indicates that the receive state machine has RXA detected Start of Packet and is active RXERROR Output High Receive Error RXE 0 Indicates no error 1 Indicates a receive error has been detected This output is clocked with the same timing as the receive DATA lines and can occur at anytime during a transfer Table 4 3 USB I O Signals ACTIVE DIRECTION LEVEL DESCRIPTION USB Positive Data Pin Positive Data Pin Table 4 4 Biasing and Clock Oscillator Signals ACTIVE DIRECTION LEVEL DESCRIPTION RBIAS Input N A External 1 bias resistor Requires a 12 resistor to ground RB Used for setting HS transmit current level and on chip termination impedance XI XO External crystal 24MHz crystal connected from XI to XO Revision 1 5 11 15 07 DATASHEET SMSC USB3280 Hi Speed USB Device PHY with UTMI Interface
46. itched between HS to FS modes In FS mode there are 5 CLKOUT cycles per FS bit time typically 40 CLKOUT cycles per FS byte time If a received byte contains a stuffed bit then the byte boundary can be stretched to 45 CLKOUT cycles and two stuffed bits would result in a 50 CLKOUT cycles Figure 7 1 shows the relationship between CLKOUT and the transmit data transfer signals in FS mode TXREADY is only asserted for one CLKOUT per byte time to signal the SIE that the data on the DATA lines has been read by the PHY The SIE may hold the data on the DATA lines for the duration of the byte time Transitions of TXVALID must meet the defined setup and hold times relative to CLKOUT TAMALID d DATA DATA TXREADY os Figure 7 1 FS CLK Relationship to Transmit Data and Control Signals SMSC USB3280 Revision 1 5 11 15 07 21 DATASHEET Hi Speed USB Device with UTMI Interface smsc Figure 7 2 shows the relationship between CLKOUT and the receive data control signals in FS mode RXACTIVE frames a packet transitioning only at the beginning and end of a packet However transitions of RXVALID may take place any time 8 bits of data are available Figure 7 1 also shows how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be presented for the full byte time The XCVRSELECT signal determines whether the HS or FS timing relationship is applied to the data an
47. itional on your agreement to the terms and conditions of the most recently dated version of SMSC s standard Terms of Sale Agreement dated before the date of your order the Terms of Sale Agreement The product may contain design defects or errors known as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon request SMSC products are not designed intended authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage Any and all such uses without prior written approval of an Officer of SMSC and further testing and or modification will be fully at the risk of the customer Copies of this document or other SMSC literature as well as the Terms of Sale Agreement may be obtained by visiting SMSC s website at http www smsc com SMSC is a registered trademark of Standard Microsystems Corporation SMSC Product names and company names are the trademarks of their respective holders SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND AGAINST INFRINGEMENT AND THE LIKE AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT INCIDENTAL INDIRECT SPECIAL PUNITIVE OR CONSEQUENTIAL DAMAGE
48. ly The USB3280 can use either a crystal or an external clock oscillator for the 24MHz reference The crystal is connected to the XI and XO pins as shown in the application diagram Figure 8 9 If a clock oscillator is used the clock should be connected to the XI input and the XO pin left floating When a external clock is used the XI pin is designed to be driven with a 0 to 3 3 volt signal When using an external clock the user needs to take care to ensure the external clock source is clean enough to not degrade the high speed eye performance Once the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60 2 clock Internal Regulators and POR USB3280 includes an integrated set of built in power management functions These power management features include a POR generation and allow the USB3280 to be powered from a single 3 3 volt power supply This reduces the bill of materials and simplifies product design Internal Regulators The USB3280 has two integrated 3 3 volt to 1 8 volt regulators These regulators require an external 4 7uF 20 low ESR bypass capacitor to ensure stability X5R or X7R ceramic capacitors are recommended since they exhibit an ESR lower than 0 1 ohm at frequencies greater than 10kHz The two regulator outputs which require bypass capacitors are the pins labeled VDDA1 8 and VDD1 8 Each pin requires a 4 7uF bypass capacitor placed as close to the pin as possible Note The
49. rcumstances should the device controller change OPMODE while the DP DM lines are still transmitting or unpredictable changes on DP DM are likely to occur The same applies for TERMSELECT and XCVRSELECT 8 3 Test Mode Support Table 8 3 USB 2 0 Test Modes USB3280 SETUP XCVRSELECT amp USB 2 0 TEST MODES OPERATIONAL MODE SIE TRANSMITTED DATA TERMSELECT Test Packet State 0 Test Packet data SMSC USB3280 29 Revision 1 5 11 15 07 DATASHEET Hi Speed USB Device PHY with UTMI Interface smsc 84 SEO Handling For FS operation IDLE is a J state on the bus SEO is used as part of the EOP or to indicate reset When asserted in an EOP SEO is never asserted for more than 2 bit times The assertion of SEO for more than 2 5us is interpreted as a reset by the device operating in FS mode Datasheet For HS operation IDLE is a SEO state on the bus SEO is also used to reset a HS device A HS device cannot use the 2 5us assertion of SEO as defined for FS operation to indicate reset since the bus is often in this state between packets If no bus activity IDLE is detected for more than 3ms a HS device must determine whether the downstream facing port is signaling a suspend or a reset The following section details how this determination is made If a reset is signaled the HS device will then initiate the HS Detection Handshake protocol 8 5 Reset Detection If a device in HS mode detects bus inactivity for more than 3ms T1 i
50. t reverts to FS mode This enables the FS pull up on the DP line in an attempt to assert a continuous FS J state on the bus The SIE must then check LINESTATE for the SEO condition If SEO is asserted at time T2 then the upstream port is forcing the reset state to the device i e a Driven SEO The device will then initiate the HS detection handshake protocol ALNVRSELECT TERMSELECT Last Activi y Driven SEQ f Detection Handshake Figure 8 1 Reset Timing Behavior HS Mode Table 8 4 Reset Timing Values HS Mode TIMING PARAMETER DESCRIPTION VALUE HS Reset Bus activity ceases signaling either a reset 0 reference or a SUSPEND Earliest time at which the device may place HS Reset TO 3 Oms lt T1 lt HS Reset TO itself in FS mode after bus activity stops 3 125ms SIE samples LINESTATE If LINESTATE T1 100ys lt T2 lt SEO then the SEO on the bus is due to a T1 875 5 Reset state The device enters the HS Detection Handshake protocol Revision 1 5 11 15 07 30 SMSC USB3280 DATASHEET Hi Speed USB Device PHY with UTMI Interface E gt smsc Datasheet 8 6 Suspend Detection If a HS device detects SEO asserted on the bus for more than 3ms T1 it reverts to FS mode This enables the FS pull up on the DP line in an attempt to assert a continuous FS J state on the bus The SIE must then check LINESTATE for the J condition If J is asserted at time T2 th
51. ust signal attach T2 Debounce interval The device now enters the HS 100ms lt T2 HS Reset TO Detection Handshake protocol Revision 1 5 11 15 07 SMSC USB3280 40 DATASHEET Hi Speed USB Device PHY with UTMI Interface Datasheet 8 14 Application Diagram TXVALID u TXREADY RXACTIVE z RXVALID 755 1 RXERROR JUUUU XCVRSELECT r57 TERMSELECT i SUSPENDN RESET 10000000 OPMODE 0 1 LINESTATE 0 LINESTATE 1 J UU UU UU UU CLKOUT C LOAD 12 USB B 24 MHz Crystal C LoAD 4 7uF Ceramic 4 7uF Ceramic 4 7uF Ceramic Exposed L Pad 0 1uF and or 0 01uF ceramic capacitors are also GND required on power supply pins Figure 8 9 USB3280 Application Diagram SMSC USB3280 Revision 1 5 11 15 07 41 DATASHEET 1L33HSV1VGg O8cEESN ISNS Chapter 9 Package Outline REVISION HISTORY REVISION DESCRIPTION DATE RELEASED BY INITIAL RELEASE 6 13 03 S K ILIEV TERMINAL 1 ADDED PRELIMINARY NOTE 11 6 03 S K ILIEV IDENTIFIER AREA lt P D 2 X E 2 DELETED PRELIMINARY NOTE 6 30 04 S K ILIEV TERMINAL 1 _ l s NEW SMSC DRAWING FORMAT amp ADDING 3 D VIEW 12 7 04 S K ILIEV IDENTIFIER AREA RN UU UU U U AJ AU IO 70 61 11 671 01 2 1 2 L MIN FROM 0 35 TO 0 50 D2 E2 F
52. wnstream port chip Chirp detected by the device Device removes DP ee lt T7 lt T6 500us pull up and asserts HS terminations reverts to HS default state and waits for end of reset Terminate host port Chirp K J sequence Repeating T9 500 5 lt T8 lt T9 100us T4 and T5 The earliest time at which host port may end reset HS Reset TO 10ms The latest time at which the device may remove the DP pull up and assert the HS terminations reverts to HS default state SMSC USB3280 35 Revision 1 5 11 15 07 DATASHEET Hi Speed USB Device with UTMI Interface E gt smsc Notes Datasheet may be up to 4ms after HS Reset TO SIE must use LINESTATE to detect the downstream port chirp sequence Due to the assertion of the HS termination on the host port and FS termination on the device port between 1 and 7 the signaling levels on the bus are higher than HS signaling levels and are less than FS signaling levels 8 10 HS Detection Handshake Suspend Timing If reset is entered from a suspended state the internal oscillator and clocks of the transceiver are assumed to be powered down Figure 8 6 shows how CLKOUT is used to control the duration of the chirp generated by the device When reset is entered from a suspended state J to SEO transition reported by LINESTATE SUSPENDN is combinatorially negated at time TO by the SIE It takes approximately 5 milliseconds for th

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