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MiTAC 8399 User's Manual

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1. 5 z I 3 I Layout Note PI IY T61 03 9 EX GND SHIELDING S W W S 10 8 8 10 mils PHY ADDRESS as short as possible 00000 8V8 LAN CLOSE TO VT6103L 9 R36 1 30 0402 126 90Z 100M C50 u2 SPEED R51 Ql 0402 GND LAN_DATAIO as TXDe 0402 3VS_LAN E te Do 34 TXD DUPLEX R37 1 0 0402 C75 50 10 LAN DCLK TK MDC 80 20 INTHPHYADO ex E22 LAN PD R50 1 2 0402 0402 R34 0603 LAN MTXC 1 0402 8 25 RXIN 80 20 10 LAN OY RX TEST 952 1 A 2 0402 50V 1 LAM LAN MTXDT D 1 20 DATAIO i PJTX 10 MTXD2 TxD2 LEDO LINK Uu LAN DATAIO R87 1 AO 2 0402 881 1s De L21 SPEED 10 MTXD3 TXD3 LED1 SPD100 22 PJTX R64 1 RIKI 06040 LAN_MTXE
2. 5 z 3 I z I 45V P 43 32V P 195 PL14 yi 2012 1 SHORT SMT4 1202 100 02 0 010 0603 50V 10 GND 0010 pon a 10 PC108 oou 4 7 1000P EP loge Us 10 25 20 20 1 al 1 PR65 PR70 NZ GND 22 22 GND 0603 awse 0603 OT23N PR64 PC103 45V P 1 as 0 100 0603 1 TV PC99 1206 J sl 0603 111 109 awu Sov 1000P 080 080 D 0603 4 FUIS 10 SZ pure 10 4422 TORRE 912 E E E G EE LTC3728L 509 e 32 54 HVQFN32 1 WZ As reo oF p 9782948 Lo swg p 9 1 PR73 i PS 7144 1 1 1 4 3 swi 48 i 5a TG1 sw2 O 5V P PL3 27 14 012 t4 M n i 73000 13 PL15 H 2010 5 1205 pee T 10UH 0 012 1 20 ri 1205 212 SENSE1 SENSE2 4 20 1 s 1 sE
3. 5 z I 3 I m E m R339 E MINI PCI 0402 5 0508 AD21 lt Wireless LED PCI INTD INTC REQ2 GNT2 WIRE _LED 99 i WIRE LED xt W DTC144TKA 1 8 14 AD O 31 J22 LAD o 3 1019 LAD O 3 LADO 0404 429 oH m SS abs EH 4 R115 0402 PJ5 1 1 WIRE LED 1 1_ LED2 YELP 1 1 WIRE LEDF 9 MINIPCI PD LED1_GRNN LED2 YELN 14 ADT 2011410 jr R116 0402 LPC NT 4 MINI LPC ADZ gt 8 E RESERVEDO RESERVEDS 22 o GROUNDO 3 3VAUXIO 5 MINI PCI lt ELK CLK 28 MINI_PCIRST 81314 1 31 GROUND F28 34 4 4 4 8 PCI lt lt GNT 20 1 8 o PCI AD31 T GROUNDS MPCI 0402 0402 0402 29 AD 31 PME a5 MINI LPC AD3 gt 9 14 80 20 lt 480 2
4. PDD4 HDD PDD7 IDE PDDS HDD PDDS d IDE PDD6 107 HDD PDD6 2 DA a fee HDD DESC 1 HDD 08 8356 m E kg Du robs HDD PDDS HOD PDDS 006 008 HOD PDDIT 7 HDD 10 HDD_PDD4 005 0010 11 5 HDD PDD11 HDD PDD3 2 000 a Een 11 HDD PDD12 T T T T HDD_PDD12 HDD_PDD2 4 13 HDD_PDD13 1 1 1 1 1 M 1 i HDD PDDi3 HDD PDDi g DD 0013 1 HDD PDDi4 R338 R337 R335 R340 R402 R154 R225 R228 R227 HDD PDDi4 HDD PDDO aw oon HDD 15 GND 330 330 330 330 330 330 330 330 330 HDD PDD15 D EU 0402 0402 0402 0402 0402 0402 0402 0402 0402 RPXS HDD PDDREO Oc 5 5 5 5 5 5 5 5 9 IDE 51 APES 1 0 ig FEDON HDD_PDIOW bows gt R229 9 IDE 00534 2 15 EDD PRS Cows 1 4 13 HDD HDD_PDDACK ip ORY C GE R425 1 AQ 562 0402 2 CLi90G M D507 1 1 HDD PDDREQ HDD iRQ14 Wind Em 0402 5 vel SEE DINE J 11 HDD PDIOW HDD PDAT ap 2005164 32 GND D13 8 DERG 1 10 HDD 18014 HDD 6 Qa 4 HD
5. 5 z I 3 I ADPIN amp Dischrage PWR VDDIN PDS PD6 Ly Pau BAVOLTI BAV7OLT1 PL5 1202 100 2012 Pui 404407 1 PC40 508 Janine 2 DVMAIN PDI PD2 1000 4 Put RLZ24D_NA BZVSSC2lV 0603 2DC S107B200 1 PD 1 lo N p22 14 1 A K i 6 5 22 PLI 5 84 pos 7 mas 22 1 POUP poise 4 1202100 01 lt PRS 002012 gou 1000P 1000P 9010 JACK 2P 8 2012 PC39 2512 r eon 4 7K 4 7K 50V 0603 0603 0603 50V 0603 331910002006 1 EM 0805 0805 10 50V 10 50V 0603 0603 10 PR75 1 1 1 1 50V 50V 1 GND 4 Pats 1 1 100K 0 4407 PR82 0603 568 508 226K GN 0603 1 4 4 J m lt ADEN 19 20 L lie PR76 x do LEARNING a 2N7002 PJOSO1 d 4 PJO4 PR2 T SPARKGAP 6 SPARKGAP 6 Pus 1M Ka DTCHAAWK 4 0603 2 1 RS voc t 5 ns 2700 R OUT 4 1 fats D MAX4073FEUT T 0603 PR31 SOT26 50V NA 7 10 GND
6. aav CONF 7 PDO CONF XLT TV DDR 7 PDI ADDR 7 PD2 D 7 RESETN 1 lt _ 58 7819 TVASET 855 1 4945 2 1 0402 m 2 Poe RSET TV DS R82 1 0402 7 05 PDS 5 RA oe 0402 0402 TV TE R79 1 Jo A 2 0402 5 419 1 040 7 PDB XO FIN TV VDDAT 2 54 TVDi2 R112 1 Jo A 2 0402 CONF XLT TV ADDR 7 Tvs PD9 7 TVD10 PD10 VDDA1 1 T PS TV VDDA2 R113 1 0 A 2 0402 as PD12 VDDA3 TVD13 C395 TVDi4 1 Jo A 2 0402 R80 R83 TVDi4 PDi3 VDDA4 27 ge 10K 10K TVDis 51 pore VODA4 1 3aV 0402 0402 TVDi5 R89 1 A 2 0402 0402 0402 5 5 5 VCC 0 SZ VE 9 7 VSYNC vec_2 SZ 7 VDD 0 GND VDD 1 7 lt P OUT VDD 2 NBEO VOD 3 7 Tv DS 05 GNDAt GNDA2 eee zt wo 7 77 TVCSO C70 10P NA Te BB ME dio 7 E 2 0 SBC vss o H4 o 881
7. 1 5 9 0402 10 0649 1 cas 1 0402 10 NB VCCSUS 18V 0402 10 C652 1 010 9 058 1 010 0402 10 Vocsus 75402 10 0853 1 010 C60 0402 10 10 C656 010 NB_AVDD1 vorar 0402 C656 1 28 vecanx m End GNDARX cate 10 GND 1 2VLDTA NB AVDD2 1 5 1 15 H VOCPLLI VCCPLL2 eau oe GNDPLLI cm Ent GNDPLL2 as gt VCCAGP lt 8 T VCCAGP 2 LO_CADOUT_H 0 15 GABOUT gt LO CADIN H 0 15 2 as READ 5 1 GNDPLL3 Gia qj ROAD T 0402 10 ROADS cup eH M RCADS 10 RCADS 433VDACVDD C130 1 010 95 20 ACAD Cd 10 VCCDAC VCCAGP teh ROADS GNDRGB CIS 1 010 RCADIO GNDDAC oe CAD GNDDAC 12 VCCAGP Xo X RCAD14 RCADIS y i 2 LO_CLKOUT_Ho
8. PLiO O VCC CORE DVMAIN 1 4 DIVMAIN y 4 BEAD 1202 100 4 gi pose 4 Pees 08050 21 Pose 0010 Tx 7243 7243 N52 2027 1000P 0603 0603 1 25V 1 25V 20 225 0603 0603 20 1 20 1 AM 1 50V WZ 7 x 4 PC53 2 PC18 eX ad 2650 278200 010 4000P PC5B 7 TTxB20UMA 25V 0603 718200 45V P 25 16V 10 25V 1 1 1 19 ky 4 J 0603 100 0603 Pas 1208 16 PRI G 20 lt 7 16V 0805 10 085 4 3 VCC CORE PRiB PUS 1 a lt 7 en 1 1 INS lt gt 1 700 UGATE 4 4 5 i 7 E 0603 a 0 68UH PR C 3 1 PO IHLP5050CE 01 0603 alan 416 416 ud P pces 20 1616207 E PN es E 10 1U 508 5 _ 4 0 05 c ees COREFB 2 PR22 16V 1 Pc22 1000 10K 0603 gt 2 0603 0603 10 PR30 2772 DIyMAIN PR 7 PUG 1 1 c 22 PG
9. 5 3 I 3 I z I LVDS Encoder VIA VT 1634 1421 012 1 us E lt 4 A Hes 7 NB_FPDE R193 1 2 32 0402 LVDS DE DE RESERVED H2 Ly RESI 20 rn Soi R182 1 5 2 0402 LVDS CLKIN LVDS CLKIN RESERVED2 0 80 20 95 0402 0402 7 NB_FPCLK 3 CLKIN RESERVED2 1 30 20 80 20 R179 1 2 0402 LVDS CLKIN LVDS_HSYNC 20 80 20 80 20 7 FPCLK HSYNC RESERVED2 2 380 206 50 50 R199 1 L2 0402 LVDS HSYNC LVDS VSYNC 74 R188 7 VSYNC RESERVED2 3 R198 1 amp 2 0402 LVDS VSYNC 4 10K 7 FPVS LVDS DO RESERVED2 4 0402 WZ 1 vos Do LVDS Di 00 RESERVED2 5 GND 5 GND SNB FOY RP10 4 224 0804 LVDS DO LVDS D2 go 01 RESERVED2 6 77 0 3 LVDS Di LVDS D3 91 02 LVDS VREF LVDSGND 7 T LVDS D2 905 04 1 8 7 02 2 1705 03 04 01 2 2 42 5V 7 LVDS 06 6 1 2 1 28 E RPI 4 224 0804 105 04 LVDS 06 ag 05 3 R190 1202 100 7 NB 004 2 LVDS D5 LVDS D7 D6 sa LV AD 10K IN EDO a LVDS 06 LVDS DB 07 A0 VAT 0402 J zl 65 DENS 1 LVDS_D7 LVDS DS 08 M LV A2 5 eue es 0805 at 80 20 RPI2 4 224 0804 LV
10. 5 I 3 I 3 I z I ammer H T amp DD R 1 2 CPU MDjo 63 4 4 MEMADD_A O 13 ia usa MENADO MEMADDA O 2226 GFL CPUCK 10 CLKIN MEMADDATU MEMDATATTI CPU 2 CPUCK CLKIN H L0 CLKIN 10 CLKIN 6 2 MEMDATA 2 CBU MDS e CLKIN L L0 CLKIN Hit X2 TT CEKIN LS LO CLKIN Hi 6 MEMADDA 3 BU MDI O pern n CORE_SENSE L0 CLKIN FX25 EIKIN TI 10 CLKIN 10 6 MEMADDA 4 MEMDATA 4 GBU MDE 25 COREFB H gt 4 COREFB 10 CLKIN CLKOUT LO CLKIN L1 6 MEMADDAIS MEMDATAIS PU MDS 25 COREFB L DERDY COREFB L Lo CLKOUT GLKGUT L0 CLKOUT HO 6 MEMADDA S MEMDATA 6 L0 CLKOUT 28 To CLKGUT LU 10 CLKOUT Hi 6 MEMADDA 7 MEMDATAI7 CPUSMDS ma pBREO L CLKOUT 4229 L0 CLKOUT 10 6 MEMADDAIB MEMDATA 8 m o FBCLKOUT_H LO CLKOUT ern 10 CLKOUT L1 6 MEMADDAI9 MEMDATA S BU MDI 2270787575720 FBCLKOUT L 10 CTLIN CEINE 6 MEMADDA 10 MEMDATA 10 AHS GBU MDN width kevo 1 22 CINIO y MEMADDA 1 MEMDA
11. 5 z I 3 I Audio CODE C VT 1617A E AVDDAD EJ 153 1202 100 1608 145 1202 100 1608 147 120Z 100M 1608 SPKR_ROUT 1 1 1 1 SPKR 1 13 1 t 9 ayes T _Clos to T 1 C186 cies 4 4 154 1202 100 1608 5 C190 C189 3 85205 0400 0402 0402 0402 3 AGNDI 155 1202 100 1608 4 480 20 lt 80 204 80 20 nanne ina 0402 0402 LOUT 1 6 MIB T __ 480 204 480 2095 LOUT 1 1 25 8 4 CLOSE TO CODEC m 101 f HO 91516 SYNC 7 0 sync 45 AG 8 0 4 4 156 1202 100 1608 97 SDIN 162 1 22 0400 Close to L78LOSACU 1 ACSDOUT 1 5 IN 47 EAPD 91516 AC97 SDOUT 12 SDATA_OUT EAPD Pee 915 16 ACS7_RST 1 RESETE Sec soure 291000010410 91516 AC97_BITCLK 8333 1 22 002 6 gr CLK L LINE OUT L 25 4681 R 14 LINE 26 AUX L 15 AUX R o MONO OUT mE 1u 0402 out gt mono_our 16 Cii 1 1 0402 LNLSR OUT L 1 ei 1U 0402 18 voeo 1 NUSR OULS C192 1 TUNA 0402 VIDEO SPDIF OUT 22 VREF QUT 18 CDROM LEFT LEFT BOE 1 0402 5 144 1 10 0402 VREF OUT CDROM RIGHT R172 1 0402 5 T C142 1 107 0402 0
12. SB VIA_VT8235CD 23 25 RTC R324 R329 10K 10K GPIO R347 1 AJ 0402 0402 0402 AKA 5 5 13 IDE 2000 15 lt gt pee SMBCLK 5 ms 8288 8888888888888888888 AC97 BITCLK 15 16 18 SMB CLKO 4 5 2222 m 4242 gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt LIA SDIN 18 207098 Pr R332 4 47 4 PD BOSS ACSDIN1 ACSOINE MDC SDIN 15 16 A 4 pops gt gt ACSDIN2 GPI2 GPO20 U2 Ace pINS m v ACSDNS O PDD4 ACSDINS GPI21 GPO20 LAIKA PDDS ACSYNC R305 1 AAA 2 0802 lt 97_ 15 16 18 PDDS ACSDO RG00 1 AY ab ono 2697 SDOUT 1516 8 PDD7 ACRST AC97 RST amp 15 16 18 PDD8 PDD9 PWROK R301 4 pj 0402 7 PDD10 pwrok pAE2 PWROK R301 1 494922 PDD11 PwRGD AE4 PWROK SB 3 720 emng 322 1 a2 0402 PDD12 PWRBTN SB_PWRBTN 19 20013 RSMRST RSMAST 19 sas M 18 SOE R354 1 AJK 0402 PDD14 RING IGPI3 WAKE UP 19 PDD15 EXTSMI GPI2 19 PME GPI6 SCh 19 D Auto Reboot Mode 13 IDE PDDREQ PDDREQ LID IGPI4 PWROWN 16 13 IDE PDDACK PDDACK BATLOW GPIS id bu To D ssEDe defeulk 18 IDE_PDIOR PDIOR PHOMARDY PHSTROBE SUSST1 GPO3 SUSCLE sussTt 7 406 13 IDE_PDIOW PDIOW PSTOP SUSCLK GPO4
13. 4407 PLig PL20 PDi4 1 La L4 1 1 K 23 ADINP 23 TR 3216FF 3A 08050 4 4 4 33UH 3 00H SSA34 4 142 PCi36 pc139 5 1204 SPC 06703 127 PDi3 002010 g PC134 100 0010 1000 20 100 14030 1000 BZVSSC15VINA dun 9010 1210 0603 0603 1210 0603 100 143 PR102 BZVSSC20 NA EOV 25V 50V 25V 0603 1096 1210 20 29 10 20 X5R 10 PD17 20 X5R 50V 25V 0603 4 20 XSi 0 1 Poet SSA34 MMBT2222A 002010 F NS cp eX 21 4 1 4 BAS32L prio PRI00 9 237K 19 249K 0603 sf 0 1 M Pon DTA144WK 20 2 1 m H A pas G SELL 19 25 4 4 CHARGING 2N7002 CHARGING 2 7002 0 01U 0 19 CHARGING lt 1 PUI9 50V 4 0603 4 1 AD open sifra TET E2 GND c 202 PR89 18 vec eH m t t 13 OUTPUTCTRL 0598 12 REF 2IN 11N aN 16 H 594 5016 4 T L Pc135 PRO PC132 PR90 4 10 100K 1000 10K T 0805 0603 0603 06030 141 0010 10 18V 10 1 124 1 IT 50V 0603 4 0603 1 E PROS PR107 10K 1 0603D 1 7 1 20138 PROG 02 tia 1 1 2512 1 1 1 0603 7 PROG NZ
14. 2515 DDR PL2 1 1 2012 1202 100 Pon IL 100 010 1210 0603 25V 50V 20 04422 508 1 5V_P 12 P 404 8 Pcia NE 1508 p Pcs 1 T ko 120 0603 19V Qum 6 6 3V 50 Pce 100 0603 9 m 100 1206 50V 12 7 12065 16V 50V 63V PRO 0 1U NA 16V 1 acs 20K 0603 iu NA SW T V GND GND PR15 NA 14K GND GND 0603 PU DRVI t ADJt DRV2 9 920 SUSB ADJ2 1 EN2 ud GND Pape j x 0603 0338 003 PRB PSOP10 0 5MM o 4 9090 0603 YW al PRI6 1 GND 00 PRIA 10K 47 0603 Bev 227 4 0603 3 coRE P 25 V 4 16 0603 NA 50V GND GND PR10 i 2 PRI 47K 0603 o 0603 PRi2 gt 1 2VPG 20 0 0603 lt gt Document ev Number Doc Date EHN 20 2004 Bheet 22 of 26 z T DVT 1 ADD PC7 PC9 150U 6 3V 2 ADD PC5 10U 25V change from 272023106701 to 272023106502 3 PR8 change from 10Kto 9 09 for H W 1 57V Mitac 22 PDF created with FinePrint pdfFactory trial version http www fineprint com
15. RP 31 33 34 36 2 5 5 DDR 37 39 40 42 z 68 8 14 18 RP43 R259 R260 RP 32 35 38 41 47 8 4754 47 1 25 MEM RPI9 RP30 68 4 10 8 CPU_MD 0 63 p crt novo MEMADD 0 131 4 U6 DDR BAA BI0 1 DDR DDR 5 CLAWHAMMER CPU CS 0 3 4 CS 0 3 CPU CKEA B DDR_CLK 0 1 4 7 DDR_CLK 0 1 4 7 3VS 3V 3V Q R324 R346 R329 R344 4 10K Q35 10K 10K SMBCLK1 T 2N7002 020 037 South Bridge SMBDATA1 2 2n7002 4 VT8235 ps wu 26 SMB_DATAO SMBDATA_DDR 014 25 SMB_CLKO SMBCLK_DDR CLK GEN 1 5950403 8399 N B Maintenance 8 7 Keyboard Touch Pad Test Error 1 Error message of keyboard or touch pad failure is shown or any key does not work Keyboard or Touch Pad Test Error Check U16 J501 J18 for cold solder Yes Re soldering Is K B or T P cable connected to notebook properly Board level Troubleshooting No eei Check following parts and signals Try another known good Keyboard or Touch pad Parts Signals 016 VDDA 020 KBD 50 014 VDD3 1501 KIO KI7 J18 KO0 KO15 Q17 he EXTSMIZ WAKE UP 262 SW502 CLK KBC Replace Motherboard Replace the faulty Keyboard
16. 71 5 2 VIA K8N800 North Bridge 73 5 3 VIA VT8235CD South Bridge 80 System Block Diagrami 90 7 Diagnostics NENES 91 7 1 REKERERERRESEREVEREQUAFEINERERRESERNENREANATEEREREAFCURELSREPEVATEN AREE ME 91 7 2 Diagn stic Tool for Mint PCI Slot 555555455586 92 7 3 Error n 93 8399 N B Maintenance Contents 5 Trouble Shooting 95 8 1 Base Work Condition usd ee epa 96 8 2 No Power 6 6 2 0 0 0000 00000 0666606666666666 6666 101 8 3 Battery Can not Charged 104 8 4 No Display
17. 43V 9 e R396 10K PCI LOCK amp 67 e 18 52 R397 10K 70 VCCA VCCA US 14 18 30 1 1 1 I VCCA C361 C360 C366 C367 c365 o e 0 1U 0 1U 010 010 R382 R401 0 1U 0 10 e 47K 10K V R304 10K V 136 CCLKRUN 33 1502 wv wwe e 76 77 79 CAD 0 31 2 3 4 VCCA 90 126 gt w 88 99 CCBE 0 3 CCBE 0 742 3V C368 E 010 108 110 CCLK CIRDY CTRDY 19 20 53 ie 020 V U26 105 107 111 CSTOP CDEVSEL CFRAME 49 50 54 E 2 101 104 133 CPERR CSERR 13 14 59 PCI_DEVSEL PCILIRDY PCI_PERR PCI 8 28 29 PCI FRAME PCI TRDY PCI SERR PCI PAR 31 36 106 132 123 CONTE CINTH CREQ 15 16 60 South PCI_REQO 1 Bridge PCMCIA 103 119 CBLOCK CRST CRST 48 58 e PCI_GNTO PCI INTB 260 Controller 143 84 100 R2_D2 R2_D14 R2_A18 32 40 47 PCI AD 0 31 131 117 CVS 1 2 43 57 PCI_AD20 R87 A100 13 PCI 10 31 75 137 CCD 1 2 36 67 CLKRUN 69 SERIRQ 65 43V A 73 74 VCCEN 0 1 12 T 16 74 8 V O 43V R297 22 CARD PCIRST amp 20 66 71 72 0 1 14 15 P14 3 4 11 12 13 43V oo U27 O VCCA 5 6 10 5 gt e O VPPA 2211 ps C367 C369 C371 C373 C364 C374 0 1U 010 010 010 7 0 10 010 014 13 R246 27 PCI CARD CLK 21 4 0 0 0 CLK GEN 1 5950403 V V 130 8399 N B Maintenance 8 16 TV Encoder Test E
18. 123 8 13 Modem Test 125 8 14 Mini PCI Test 127 8 15 Bus amp Reader Test 129 8 10 Encoder Test Erro Wp 131 9 Spare Parts 133 IU System Exploded E Ea 145 LL Circuit 146 L2 Relerence 172 8399 N B Maintenance 1 Engineer Hardware Specification 1 1 Introduction The 8399 motherboard would support the AMD 62W Dublin 32 bit with 256 L2 cache Hammer 64 bit with 1 L2 cache with uPGA Package This system is based on PCI architecture which have standard hardware peripheral interface The power management complies with Advanced Configuration and Power Interface ACPT 1 05 It also provides easy configuration through CMOS setup which is built in system BIOS software and can be pop up by pressing F2 at system start up or wa
19. Z N Z gt gt z N z c to s oa D RI65 R315 R350 R445 R450 f D D f R178 R214 R223 R382 R386 IG gt ta o o 5 6 gt IN Oo 199 gt 2 E e gt 79 o2 e 5 f R101 R107 R61 R66 R77 R78 oa 2 D R224 R26 R29 R353 R4 RO intenance 134 9 Spare Part List 3 Part Number 271071124311 271071131101 271071137271 271071143112 271071151103 271071169011 271071202102 271071202301 271071203101 271071203701 271071204101 271071220101 271071224301 271071226311 271071228301 271071243211 271071249111 271071249311 271071270301 271071272301 271071301311 271071302101 271071330302 271071333301 271071333301 Description RES 124K 1 16W 1 0603 5 RESI30 1 16W 196 0603 SMT RES 13 7K 1 16W 1 0603 SMT RES 14K 1 16W 1 0603 SMT RES 15 1 16W 1 0603 SMT RES 169_ 1 16W 1 0603 SMT 2 1 16W 1 0603 SMT 2 1 16W 5 0603 SMT RES 20K 1 16W 1 0603 5 RES 20K_ 1 16W 1 0603 SMT RES 200K 1 16W 1 0603 5 RES22 1 167 1 0603 SMT RES220K 1 16W 5 0603 5 RES226K 1 16W 1 0603 SMT 2 2 1 16W 596 0603 5 RES24 3K 1 16W 196 0603 5 RES 49K 1 16W 196 0603 5 RES249K 1 16W 196 0603 5 RES27 1
20. 106 8 5 External Monitor No Display 108 8 6 Memory Test Error cae eoe 110 8 7 Keyboard Touch pad Test Error 46 112 8 8 USB Port Test oeeo 114 8 9 Hard Disk Drive Test 4 1 5 9 40 9 5 28609 0000 00066606660 6666 66 116 8 10 CD ROM Test Error 3 118 8 11 Audio Test 9 6 120 8 12 LAN Test Error
21. MEMDATA 44 CEU Mas 0608 IcPucLK 5 LO CADIN NC AHIB MEMDATA 45 2 10 CADIN 1 14 NC AH23 Aliza CPU CKEA AER MEMDATA 46 At GBU MD47 Rise L0 CADIN 1 15 4 CPU CKEA CPU CREB AESH MEMCKEA MEMDATA 47 5 042 185 4 DDR CLKO MEMCKEB MEMDATA 48 CPU MD49 0603 B13 812 4 DDR CLKO 49 CADOUT DDR CLKi 5 CPU 50 1 6 LO_CADOUT_H 0 15 10 CADOUT NC 4 DDR CLKi DDR CLK2 MEMCLK H t MEMDATA SO CPU puck cur 4 8008 L0 CADOUT H 14 NO B19 B19 SIA RESERVE DOR CLKS yar H2 0602 s 10 CADOUT NC_B7 14 538 DDA CLK Ario MEMDATA 52 7 CPU MD53 L0 CADOUT H 12 NCC 1 4 DDR CLK4 DOR CLRS MEMDATA 53 ATTI idth 20 5 5 5 20 0 CADOUT H 1 31 0 ipei joco DDR CIKS Eig MEMCLK MEMDATA 54 8 CPU MDSs Wat h 20 LO CADOUT H 10 NC C15 FOB 1 6 x 55 pias zo c18 SINCHN A 3354 RE 0 sinc 10 CADOUT 4 DDR DDR CIK 010 MEMCLK MEMDATA 56 SEDES
22. Signal Name Pin Signal Description GPOO0 VSUS33 AA3 General Purpose Output 0 GPO1 SUSA Z 2 0 General Purpose Output 1 Rx94 2 1 VSUS33 2 SUSB General Purpose Output 2 94 3 2 1 VSUS33 GPO3 Y3 0 General Purpose Output 3 Rx94 4 1 SUSST1 VSUS33 4 505 AB3 General Purpose Output 4 Rx95 1 1 180833 0 General Purpose Output 5 RxE4 0 1 CPUSTP GPO6 PCISTP AD6 General Purpose Output 6 RxE4 1 1 GPO7 5 R2 General Purpose Output 7 4 2 0 GPOI2 GPII2 General Purpose Output 12 RxE4 4 1 5B 1 0 INTE GPO13 GPI13 E4 0 General Purpose Output 13 RxE4 4 1 5B 1 0 INTF 14 GPI14 General Purpose Output 14 RxE4 4 1 5B 1 0 INTG GPO15 GPII5 General Purpose Output 15 RxE4 4 1 5B 1 0 INTH GPO20 GPI20 ACSDIN2 PCSO 21 GPI21 ACSDIN3 PCS1 SLPBTN 22 GPD2 R22 GHI General Purpose Output 20 RxE4 6 1 5 1 0 General Purpose Output 21 RxE4 6 1 E5 2 0 General Purpose Output 22 RxE5 3 1 PMIO 4C 22 1 General Purpose Outputs Continued Signal Name Pin Signal Description GPO28 GPD8 AC8 OD General Purpose Output 28 RxE5 3 1 PMIO 4C 28 1 GPO29 29 AB9 OD General Purpose Output 29 RxE5 3 1 PMIO 4C 29 1 VRDSLP Note The outp
23. 9 ISA 804 18 104 d X 4 9 505 18 1 05 5 GND R9 GND USB USB 54 C4 9 ISA 506 8 ISA 5 6 560K 560K 1000P 5 18 806 1106 ISA SAT 0402 0402 0402 45V TSA_SAB 1 1 10 5 9 y 0 TSA_SATO ag ISA 9 SA18 C 12 TSR SATS exp 45V 419 USB 2 0 7 ats 8 USBPO UBBPO 1 AYR A 2 80A 2 093 USBPI S usppi 1 vce 16 2 ISA_SA16 9 cae2 71 A17 22 ISA SA17 9 3 A ISA_ROMCS 9 2 Be 82 2 2 24 MENRE 9 2 B4 4 2 10 18 1 ISA_MEMW Y 95Z 00M B4 M YY eoziooM ion vss WE MEMW 9 doses p o 32P PLCC SMT i 1 PLCC32 8 USAPO R o 9603 anpa oos NA ONDA GND SDA0 gt Trasmit Timing control 1470748 3 13 IDE_SDD 0 15 pem Sec soure 331000008090 Jig _ 1 1 ISA SAT e 142 112 ISA SHORT SMT4 TAS IM 20 ISA 4 GND USB GND 2 2 EM ISA SA5 ISA 2 2 _ 7 L 2A4 2v4 25V 1G voc 24 9 ISA_SOE 26 GND 2440 5020 402 10 5 5 u24 Scr 1 1 1 1 1 m ISA SAB MINISMDC110 4 1 2 1v2 HE SAS R28 R27 TSA_SATO ca 10K caes 15022 10K 15 10 0402 010 7T Gav 0402 1A4 1Y4 ISA SA12 0402 1 04
24. LO CLKIN 2 VCCAGP a 2 L0 CLKOUT H1 aek 2 VCCVL 0402 e 2 L0 CTLOUT LO CTLIN HO 2 Jar E24 ncm Ter A22 vp de VCCVL 1 10 CADOUT 10 15 0402 10 2 10 CADOUT 0 15 LO CADIN L 0 15 2 10 15 vec pene MD RCADO TCADO vec En nn RCADI TCADIR VoovL vec ea Mr RCAD2 TCAD2 Mea vec RCAD3 TCADS VoovL vec eeu M RCAD4 TCADAR vec 002 Hen RCADS t TCADS t C658 1 010 VCCVL VCC RCAD6 6 VCCVL one 10 RCAD7 TCAD7 VCCVL vec RCADB TCADB VCCVL vec GND RCADS TCAD9 VCCVL VCC RCADI0K TCADIO VCCVL vec RCADI1 TCADIt vec RCADI2 TCADI2 vec RCAD13 TCADIG GND vec RCAD14 TCADIa GND vec RCADI5 TCADIS GND vec GND vec 2 10 CLKOUT L0 128 brciko LO CLKIN Lo 2 es GND vec 2 LOCLKOUT L1 RCLKI 1 LO CLKIN L1 2 GND vec GND 04022 CTLOUT Lo lt 1 E254 ROTL TCTL gt 10 LO 2 GND vec 2 LDTSTOP_NB AA 1 BH GND vec NB_LDTRST HTAST GND vec 2 0 LDTSTOP gt C28 1 ECC GND vee 02 10 moor RNCOMP VCCHT 1 010 C26 a veg 0402 10 T ER 1 5 VCOAGP 14 1 010 D 0402 10 1502 012 1 2VLDTA GND 1202100 VCCHT GND vec
25. 0603 BATTI GND 2512 1 4 unr 19 Poi24 123 eee 4 0 010 1000 poss 50V 603 10 25V 0805 06030 10 10 V GND 1 xy Sec soure 331000007044 o No TR SFT 10A 4 1202 100 FUSE 2917 129 2012 Puzo 1 B 0603 PL16 19 t 3 FUR ae SVDD3 50V 1202 100 109 Get mec 6 2012 147 10 de E GND RS2 BAT V 19 10 0805 4 77 1085 Miast MSOPB 7 X et SA GND 5 GND 5 4 E 3 B 4 BAT T 19 2 PR92 1 9 19 1 DISCHG 1 X 1 PR108 1 5 10 2 5 7 m nu 0603 TBTD 0070018_7 0805 N GNDB 10V GND GND 4 E891 A 2 0603 C 19 4_ 2 0603 D 19 Sec soure 331000007044 DVT 1 PU20 gt VDD3 change to SVDD 2 ADD PR108 PR109 PUP 3 ADD PR85 li PVT SPARKGAP 6 SPARKGAP 6 1 PJO6 PJO7 take off M 2 PJO1 PJO take off lt Title gt Document Number Doc Roo Date 20 2004 Bheet 23 of 26 5 3 z T PDF created with FinePrint pdfFactory trial version http www fineprint com
26. 5 North V E Brid U40 a ridge 74HCTIGI26 gt CRT VSYNC R422 51 116 yc 1207 100 u a CP2 o V 22P 4 2 0 0 RT RED 112 1207 100 1 CRT e e CRT GREEN 113 1202 100 2 CRT BLUE 7 114 yy 1207 100 3 2 410 C411 C412 CPI 75 4 22P 22P 22P 22p 4 9 3V V V us P9 10K CRT IN RI2 IK 5 U20 South Bridge 100P 6 7 8 10 109 8399 N B Maintenance 8 6 Memory Test Error 1 Either on board or extend SDRAM is failure or system hangs up Memory Test Error 1 If your system installed with expansion SO DIMM module then check them for proper installation 2 Make sure that your SO DIMM sockets are OK 3 Then try another known good SO DIMM Parts Signals modules Board level Troubleshooting Check following parts and signals 3V 1 25 2 5 8 DDR 1 25VSREF Replace the faulty CPU MDY 0 63 SDRAM module CPU DQS O 7 Replace CPU DQM O 7 Motherboard MEMADD A B 0 13 DDR BAA B 0 1 DDR RASA B 0 1 If your system host bus clock DDR WEA B 0 1 running at 100MHZ then make Replace the faulty CPU_CS 0 3 sure that SO DIMM module SDRAM module 22 meet require of DDR 333 11 DDRCLK O0 1 4 7 7 SMBCLK DDR SMBDATA DDR 110 8399 N B Maintenance 8 6 Memory Test Error 2 Either on board or extend SDRAM is failure or system hangs up 1 25
27. m CDROM COMM Ci43 1 1 0402 19 13 CDROM CD GND 9177 817671 cus indie y 4 1 4 4 4 100K 2200P 2 100K 2200P C153 1 3U 042 22 l 1 cies 1 0402 0603 lt 0402 0603 T C157 1 3U 0402 24 UNE NR 31 1000P 0 1U 1U 1U 01 5 5 9 0402 0402 0402 0402 0402 04 a s NC 10 280 206 280 204 8 20 12 ec Nee 40_ GPI3 50V 16V 4 1 16V 1 16 135 1 3U 0400 21 MICZ C141 1 1U 0402 OUT 43 1 147 1 3U 0402 PHONE ann 22 FAL AFLT2 H7 5 AUDIO 14M lt XTAL IN XTAL OUT pus AGND VTi617A nra e M RI9 1 AQ A 2 0402 5 VREF OUT PQFP48 0 5MM 4 AVDDAD R200 1K 596 0402 R428 AC 101 0402 AGND AVDDAD R189 R203 5 22 10K 0402 5 Microphone Jack p L43 6002 100 di Rje4 1 1 BY Ti 148 600Z 100M PCBEEP 1 2 0402 C162 R213 1 1 1608 i ARK 270P J 0407 NA 8403 SB SPKR 0402 C201 820 402 GND 1U R202 50 270 0402 CARDSPK 0402 J 4 JACK SP R A W9 1 6 3V 106 SARDGPKE 14 50 cios ST 28M F60 80 20 04 77 R214 10 331840005013 5 MOTE AGND 47K 47K 0402 CONN JACK 0402 0402 80 20 E 7 AGND 5 77 AGND C AGND 7 8185 AGND GND 1
28. 15 close to MTG8 277777 micso1 ec COE 162 1202 100 i608 C236 1U NA SENA E Sec soure 339115000059 SPKR LoUT lt mo uw L49 06030 80 20 1 BEAD 6002 100 PO 1000 R218 X 16V 1K 477 9v Internal Microphone 0402 AGND ND W 10mils 1 W short as possible Fes 1 BEAD 8002 100 AC GPIS R215 1 2 0402 7 77 0407 a SPKR ROUT q 21 caos aourr 2 Hi SV 6 3V 0402 E 9 152 1202 100 9 0402 57 0603 234 1 1U 1 80 20 Tv H o4 RN 1 ood ons D AGND TP5345 4 pc BEEP C213 C212 C229 C235 77 3 pee a i m 010 010 A 1000 0402 AGND i R219 1 0402 GU 0402 0402 0402 16V 10 151 140 06030 1 R221 4 0402 380 208 5 80 20 CPWX6 6 1 1608 2 2 1 BEAD 6002 100 220 1 ho 0402 T T9 1 i TZ HP SENSE SERT SHUTDOWN 22 SHUTDOWN 5 7 150 TAT 1207 100 1608 AGND AGND GND 1 1608 L39 06030 2 GND USB noo 1 BEAD 007 100 AOUT L C228 iu I case JACK SP R A WO 1 1 5 100P 100P 1 6 3V 0402 LINEN 0402 0402 77 ST 28M F60 C233 1 10 Lour SPKR_LOUT 10 10 AGND_C 331840005014 63 0402 tour 2 SPKR LOUT 50 50 CONN 5 28 60 e AGN
29. pcIRSTH 660000000000000 22253235555525555235552555 BGA451 36 1MM 43V 9 5 UBA PCI RST PCI gt CARD_PCIRST 13 14 15 gt cPu_Pcinst 3 ead 2 gt 5 13 14 15 TSSOPI4 gt IDE_PCIRST 13 14 15 TSBORI 3 8 35 USB 3 9 9 57 NUT 1651 2012 2 1 120211000 1 1 3 4 4 4 4 4 C325 C327 C391 C348 C316 100 050 0402 0402 0805 0402 0402 19 20 e 80 20 80 20 480 209 e 80 20 80 20 R282 R278 10K NA 10K NA 5 0402 0402 5 5 100 101 PCI RST gt LPC_AST 7 1119 R279 R281 10K 10K gt PCIRST amp 7 1119 TSSOPI4 gt PCIRSTH 7 1119 A A C WZ Title Document er Number Doc Date 20 2004 Eni 8 of 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com
30. 23 Kos 4 KOE GPSIFAS GP6S ANS INT10 28 pec vs lt 23 Gi cane BAT 23 BATT_DEAD 6765 1 25 e pe BAT D 23 kHc RSMRST 7 GPST ANTANTI2 0402 0402 POWERBINE rg KOS rubus 380200 480 20 KOio a 1 Ep 1 KON GPI2FATO RESET KBC RESETA KBC_RESET 20 E 9 1 GPS IFA ENS 42 L Jd Kou GP14 FA12 xin ee GND u GPISIFAI3 Zka s Peng Kou GPIG FA14 238 9UT GRHIEATS KBG VREF 8 m ee ke H GP31 PWM10 FCTRL1 box GPS2 ECTRL2 H F 1 GP33 FCTRL3 4 3 3 4 7m 8 amp C304 0303 aypz 57 0 10 x 52 GFSMBANKI vss 0402 0402 0402 FPC FFC AMM 26P 55 GPS6 CE AVSS 16V 110 40 ACES omea 80 20 80 20 7 K 85202 26 05 W83L950D GND GND 05 Sec soure 291000152610 VDD3 5 SVDD3 R280 RP45 10K BAT 0402 m 4avs 1 2 gt 9 gt 9 KBO 945 270 1 2 0402 a17 4 DTC144TKA 1206 ou KBC RSMRST 0402 80 20 FDV301N 50v 50723 BATT_DE
31. System Clock Check 43V 158 1207 100 2 HAAA e e T e e T LIIS C267 C262 C245 C265 C240 C271 10U 10U 0 1U 0 1U 010 010 f 4 GUICLK e R234 22 FSI 48 U12 North Bridge _ SoM AGP R244 33 11 K8N800 C255 242 T 22P T 22 V V U26 21 PCI CARD CLK R246 27 13 PCMCIA T Controller C257 J 22P P19 70 CLK_KBC R262 22 21 U16 KBC Controller 3 i 14 318MHZ FS3 FS2 FSI FSO C24 L L c246 2P T T 27 o 1 1 1 CPU HTT PCI V V 200 40 66 80 33 40 CLK LPC33 R264 22 22 159 y 1202 100 5 10 281 22P V V Clock Generator 1 5950403 3 3VS 3V 3V R329 R344 R346 R324 R251 R310 10K 10K 10K 10K 10K 10K Q37 26 SMB_DATA0 257002 035 25 SMB 4 257002 e e DII e P10 8154148 w 32 ICS_PD R254 0 SUSA gt 1 50 R230 22 14M SB IOSC U20 8 R243 22 SB VCLK South 28 e R258 22 USB CLK Bridge 23 R265 33 PCI SB CLK 45 FS2 R238 22 14M SB APICCLK 9 e C252 C283 R257 22 22 10K SMBDATA DDR V V P4 V J16 amp J17 SMBCLK DDR SO DIMM SLOT N R240 22 AUDIO_14M 2 lt U10 Audio Codec 14 R248 27 MINI PCI 25 Pi
32. THERM reg 5 1 2VLDTA 12V P M qu E 4 25V y 8407 TSSOP14 E Jo 1K 0402 swi 5 u38 NA DEN SMS 7 1 t RESET He gt KBC_RESET 19 1220 n 4 voc GND 2 id gt PWROK 25V 2 OPEN SMT4 TC010 PSS11CET 1 11 R409 V 297040105010 07143 100K TSSOPi4 SW_TCO10 PS11CET 0402 0402 80 20 5 7 10V ER 15 lt 7 GND OPEN SMT4 JO lt Title gt Pus Document Number lt Doc gt Date 20 2004 Bheet 20 of 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com 5 z I 3 I PR58 0 0603 SUSC 1 4 1 2 31 25 DDR P sn EXE if 125 DDR P sur Pres 5 VSENSE 1 25 0603 n JP NET20 s 4 1202 100 0603 Pose 2012 1000 T 0 GND2 89 97 220 PE 0603 1210 9406 4 50V 10V 2996 4 4 4 PCZ7 SO8 GND 4 PC72 PC7B PC74 1500 VY 010 100 1007 7243 GND cp 0603 1208 120
33. LED2 DUPLEX 23 ANE REXT R70 aKa 2 0402 B 841 5 T0 2 VEDSNWAYEN RXIN H Q BS 1 0402 ilaj 16 PJRX LAN COL R54 0402 1 R67 1 0402 n 10 LAN COL coL PEN R7 1 2 0402 4 RDC RXC 40 PJRX LANCE LAN CRS R53 1 0402 18 LAN XI RXIN 186 ona 4402 31 pa LAN BL 1 0402 4 Rot Y LAN XO 7 4 1 10 LAN k RXC xo NCO 2 10 LAN MRXDS LAN 1 224 A 8 0804 45 PHYAD1 RXD3 902 x H ner 52 LAN 2 46 10 MRXD2 2 48 PHYAD2 RXD2 21 FXEN R35 1 SIKNA2 0402 10 LAN PHYAD RXD1 TEST AQ 9 3 xvm LF 10 LAN MRXDO 4 a 48 PHYAD4 RXDO 50 16 Heo pp 24 LAN R45 1 2 0402 PWRDWN 9 1 LAN MBXDV R74 1 0402 3 42 LAN RST WA 2 0403 10 LAN RXDV RST LAN LAN 413 1 0402 128 0402 10 RXER 902 100 80 20 i 50 GNDO VDDO 4 i lt 7 GND1 VDD1 B O 3VS 610 ONDE DD 0402 0402 GNDOSC VbDoSC 80 20 480 2095 i GNDRX VDDRX 398 LAN 10 10 i 0603 GNDTX VDDTX VDDPLL 315 LAN PLL ca GNDPLL 1600 GND R76 6002 100 1808 cb El 1 2 1608 4 H GND GND_45 1 LAN XI 4 j LAN 33 38 LAN 38 LAN PLL R85 600Z 100M 9 3VS 43VS LAN 1202 100 1 cv
34. ev Number lt Doc gt GND Date EHM 20 2004 Bheet 2 of 26 5 I 3 I 3 I z I PDF created with FinePrint pdfFactory trial version http www fineprint com 3 ClawH ammer Power plane 2 2 300 CORE CORE uec VS Ves Lua 1 117 Ha VDD 101 vss 2 vss 118 10 IE VDD 102 58 3 vss 119 020 VDD 103 VSS 4 VSS 120 VDD 3 VDD 104 vss 5 121 024 eura eua age VOD 4 VDD 105 VSS 6 VSS 122 ie 0503 VDD 5 VDD 106 VS8 7 vss 123 HZ wW O22 4 1 VOD 6 VDD 107 VSS 8 VSS 124 2 16 VDD 7 VDD 108 vss 9 VSS 125 ov 291 4 ema VDD 8 VDD 109 58 10 VSS 126 E TU m 2 9 VDD 110 11 VSS 127 EN 808 1 V amp VD 10 VDD 111 VSs 12 VSS 128 E n 9502 1 VDD 112 VSS 13 VSS 129 2171 121 4 gua VD 12 VDD 113 VSS 14 VSS 130 En 10 E 9502 0 13 VDD 114 VSS 15 VSS 131 e ga a 15 425VDDA VSS 16 VSS 132 805 1 116 9 VSS 17 VSS 133 lt 7 lt 7 VDD 16 VDD 117 VSS 18 VSS 134 ab VDD 17 VOD 118 VSS
35. LAN COL LAN CRS LAN MRXDV LAN MRXER LAN XI LAN XO 123 8399 N B Maintenance 8 12 LAN Test Error 2 An error occurs when a LAN device is installed 3VS 1 7 18 5 3VS LAN 32 3VS LAN 253641 36 R36 10K ANE 23 R51 10K SPEED 21 R37 10K DUPLEX 22 R52 10K TEST 20 3VS_LAN R87 1 5K R92 22 LAN_DATAIO 43 R93 22 LAN_DCLK 44 P10 b 4 MTXC R284 22 LAN MTXC 22 9 MRXC R283 22 LAN MRXC R71 22 4 U20 RP524 22 4 LAN MTXDJ0 3 11 14 South LAN MRXDJ0 3 RP6 AA 22 4 45 48 Bridge R59 22 LAN MTXE 10 VT8235 LAN_COL R54 22 15 LAN CRS R53 22 16 LAN MRXDV R74 22 3 MRXER R413 22 5 e P16 02 VT6103L 6 pp 415 5 d 1 650 EM PJTX 1 0 1U 9 PJTX 2 p Y L31 7 TX P16 120nH 16 PJRX 3 EN PJRX 6 7 C75 R78 R77 0 1U RX 49 9 49 9 126 35 TXD 90Z 100M 6 RX TD io PJ4 4 5 iie 4 15 PJ7 18 T TD 2 Y Ys 8 TD R48 gt R49 R47 gt R46 pigs 75 75 75 75 DIE L28 902 100 2d RXIN Then A A Ja C74 R76 45 2 3 1000P T 600Z 100M RD e Y Y R66 R61 rH 49 9 49 9 V C54 b 40 LAN R91 300 XI 39 LAN XO 25MHZ C85 C87 22 22 124 8399
36. 68 CCIBESH CAD25 1 27 6 CAUDIO Mosi MES ON CCBERT 9382 CAD26 9 2 62 CSTSCHG 88 D 1 2 0402 47 CAD27 0 CAD2B C ezsszcsn CC BEOR DAD 30 64 1 0 22222229 5 2 D2 31 65 Tee CAD3T 666606606 CCLKRUNF 15 E 6 CCD 2 1410 1 412 67 i 1 144_0 5 6357 270P GHG 0402 10 50V aD GNDS AG GNDG GND7 27MM 3V NU ACECON SZ GND MF 291000000009 GND L3 hoder 331000000303 u27 5 VOCEN 0 mE 2 SHDN Yoon VODPO 14 VPPENi VCCA o 1 1 t VDDPI 9 m 44 1 t 5 AVCCB 522 m ET 2 4 9 2 4 4 4 4 12v H x 367 C369 C373 can 55 16 4 0402 0402 5 0402 36V 16V 36V 16V 4 1 C364 C363 aruma 124 040024 1206 lt 04024 1200 _ 5 ab 38V 16V ap lt Title gt Pz Document ev Number Doc Date EHM 20 2004 Bheet 14 of 26 5 I I 3 I z I T PDF created with FinePrint pdfFactory trial version http www fineprint com
37. 7 AOLGPI Y4 GPI18 THRM CPU Missing Used to detect the physical presence of the CPU chip in its socket High indicates no CPU present Connect to the CPUMISS pin of the CPU socket The state of this pin may be read in the SMBus 2 registers This pin may be used as CPUMISS and GPI17 at the same time Alert On LAN The state of this pin may be read in the SMBus 2 registers This pinmay be used as AOLGPI and all at the same time Strap Pins for VT8235 Version CE Configuration Signal Name Pin Function Description Note Strap AUTO Auto L Enable Auto Reboot Reboot H Disable Auto Reboot Default SPKR CPU L Enable CPU Frequency Frequency Strapping Strapping Disable CPU Frequency Strapping Default KBCS Internal 1 Disable internal Keyboard H Enable internal KBC Controller Default SDCS1 Eliminate Enable Use external External EEPROM Default LAN H Disable Do not use EEPROM external EEPROM 88 5 3 VIA VT8235CD South Bridge 10 Power and Ground 8399 N B Maintenance Power and Ground Continued Signal Name Pin Signal Description VCC33 see pin P T O Power 3 3V 5 list vcc see pin P Core Power 2 5V 5 This supply is turned on list only when the mechanical switch on the power supply is turned on and the PWRON signal is conditioned high GND see pin
38. DEAD 4 15 D R140 47K LV DUAL 23 26 125 1202 100M BLADJ Controller L6 T LV EDGE 18 DVMAIN 120Z 100M 3538 os Y Y e P10 P8 V 17 19 21 LCD ID 0 2 L c424 C19 U20 0 10 RPI South V 10K 4 Bridge 107 8399 N B Maintenance 8 5 External Monitor No Display 1 There is no display or picture abnormal on CRT monitor but LCD can normally display External Monitor No Display Board level Trouble shooting Check if J2 are cold solder 1 Confirm monitor is good and check the cable are connected properly Re soldering 2 Try another known good monitor Check following parts and signals Display Replace faulty monitor OK Replace Parts Signals Mother board U12 CRT_DDDA U20 CRT_DDCK J2 CRT_HSYNC 05 CRT VSYNC No 06 TED R420 pies CRT_GREEN Lis CRT BLUE U39 CRT IN U40 118 108 8399 N B Maintenance 8 5 External Monitor No Display 2 There is no display or picture abnormal on CRT monitor but LCD can normally display 43V 43V R68 R69 22K 22K Q5 2N7002 CRT DDDA R420 33 115 y y 1202 100 e 12 06 CRT DDCK 2147002 R423 33 118 1207 100 15 e NN e 2 _ p P7 v 45V o J2 U39 UR 74HCT1G126 z CRT HSYNC R421 51 117 1207 100 13
39. LAN 1 16 SE STPCLKF 28 LAN 2 16 0402 5 SB VCLK gt vok MRXD3 16 9 R93 5 2 0402 SB_SLP R318 1 0402 1 SS um um jx Un Bat 1 1915 SB FERR R307 1 XNA 2 0402 R349 1519 LAD3 LAD3 10K NA c Aia EECS EECS 0402 15 LDRQO lt 07 EEDO EEDI 814 5 0 1519 LFRAMERK lt a LFRAME EECK EESK 141519 SERIRQ lt SERIRO E10 sERIRQ SB RAMVCC 43VS SPKR AES 2 S8 BAMVCC 5 18 SB SPKR SPKR 5 14M SB 105 Eg 58 RAMGND BMBCK2GPI27 GP027 ee 6706 apt j SMBDT2 GPI26 GPO26 E SB MOSEL 0102 SB VRDSLP 0402 0402 ya poo SB PLLVCC 1 eo 19 SB_THRM AOLGPI GPI18 THRM PLLVCC 14020 12 LCD 100 CPUMISS GPI7 Et SB VCOMPP R445 1 0402 4 NHBUDEBE ADS INTRUDERWGPIIG 22a SB PLLND LAN MIXE R amp amp 1 K A2 002 UND SEG WSC APICREQ 7 R95 1 2 0402 5 APICDO 1229 APICDO APICOS GPI28 GPO28 APICD1 APICACKIGPI29 GPO29 aav SZ 5 14M SB APICCLK lt APICCLK RTCX2 Ee o LADO zd TADI Ta LREQ 25 1MM EADS 1 E 1 SB VPAR _ R290 1 2 0402 1206 MIXC R2B4 01 0402 MRXC R283 01 0402 LAN 16 4avs 9 9 4VC
40. during runtime Only one of the two will be used the signals associated with the other will not be used GRBF has an internal pullup to maintain it in the de asserted state in case it is not implemented on the master device 8x mode allows only SBA GPIPE isn t used in 8x mode Note AGP 8x signal levels are 0V and 0 8V AGP 8x mode maintains most signals at a low level when inactive resulting in no current flow 74 8399 N B Maintenance 5 2 VIA K8N800 North Bridge 3 V Link Interface Signal Name Description VAD7 AF25 IO Address Data Bus Also used to pass strap information from VAD6 AD24 IO the South Bridge to the North Bridge the actual straps are on VADS AF20 IO the indicated South Bridge pin and that information is passed to VADA 19 IO the North Bridge at reset time via the VAD pins VAD3 AE24 IO VAD2 AF24 IO VADI AD21 IO VADO AD20 IO VPAR 19 IO _ Parity VBE 21 IO Byte Enable UPCMD AF26 I Command from Client South Bridge to Host North Bridge UPSTB UPSTB AF23 I Complement Strobe from Client to Host DNCMD AD23 O Command from Host North Bridge to Client South Bridge DNSTB AF22 Strobe from Host to Client DNSTB AD22 Complement Strobe from Host to Client 12 C Interface Signal Name Pin VO Signal Description SBPLCLK 10 IO 12 Serial Bus
41. 133 9 Spare Part List 2 Part Number 271061103501 271061104501 271061105501 271061106501 271061121501 271061152501 271061203102 271061220501 271061222501 271061300131 271061302101 271061330501 271061331304 271061361101 271061401101 271061464112 271061470501 271061471501 271061472501 271061473501 271061474501 271061499012 271061512102 271061562501 271061564101 Description 1 16W 596 0402 5 RES 100K 1 16W 5 0402 SMT RESIM 1 16W 56 0402 5MT RESIOM 1 16W 596 0402 5 RESI20 1 16W 596 0402 SMT RES 1 5K 1 16W 5 0402 5 RES 20K 1 16W 196 0402 5 RES22 1 16 5 0402 SMT RES2 2K 1 16W 5 0402 5 RES300 1 16W 596 0402 SMT RES3K 1 16W 196 0402 SMT RES33 1 16W 5 0402 SMT RES330 1 16W 5 0402 5 RES360 1 16W 1 0402 SMT RES 402 1 16W 1 0402 SMT RES 4 64K 1 16W 1 0402 SMT 47 1 16W 5 0402 SMT RES470 1 167 5 0402 SMT RESA 7K 1 16W 5 0402 5 RESA7K 1 16W 5 0402 SMT RESA70K 1 16W 5 0402 SMT RES49 9 1 16W 1 0402 SMT RES 5 1K 1 16W 1 0402 SMT RES 5 6K 1 16W 5 0402 SMT RES 560K 1 16W 1 0402 SMT 8399 N B Ma ocation S R112 R113 R117 R13 R145 R146 gt gt zem S 8 e oo e oo gt oa gt c D gt R241 R244 R265 R420 R423 E 2 8 n
42. USB 258 USBPO RP50 1 15K 1206 USBPO AN 4 3 5 1 4 1202100 1415 POLADD 30 SysndzussnsmupUSUSUSUSSRUSSS 202 ng RA ADD 8959589859585895855859559555 5558 25252225225 i 02 gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt 000000000 4 55555555955 loeis USBP4 RP49 1 154 1206 ADS vsus E 25 ig 002 08 USBPST 2 80525 80 20 j 80 20 05 5 4 ADB 5 18 poA 1202 100 9 010 2 1611 2012 ADI2 PLLVDDA 4 b ca 013 PLLVDDA TOU iu 100 014 0805 0805 015 10 80 20 AD16 PLLGNDA el 1 80 20 1 50V 163 4 zor 80 20 AD17 PLLGNDA AD18 019 020 AD21 USBPO AD22 USBPO SB KA20G RP57 1 10 120 AD24 USBP1 SB TROT 2 2 AD25 USBP2 SB ROTZ 2 026 USBP2 AD27 USBP3 AD28 USBP3 AD29 USBP4 AD30 USBPA AD31 USBP5 USBP5 1445 PCI CBEOK 1445 1 14 15 PCI C BER2 CBE2 USBOCOR 14 8 USBOCT PCI_FRAME yapoe PCI_GNT 0 1415 PCI FRAMES 52 gt PCI DEVSELF pag CRAMER USBOC3 POLGNTH PCI MATS gt ag DEVSEL USBOCA PCI_GNT 2 PCI_I
43. 0402 0402 7 E 5 3 5 cb 8 1415 IDE PCIRST 1x Na Ie Q32 DTC144TKA Document Number lt gt Date EHM 20 2004 Bheet 13 of 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com 5 I z I 3 I z I AD20 PCLINTB PCMCIA CONTROLLER amp CARDBUS SCOKET REQO GNTO CARD PCIRST a SIGNAL PCCARD PULL UP VOLT EM s 4 CCDI2 BV CBLOCK 1 CSTOP CARD VCC C377 CDEVSEL CARD_VCC CTRDY CARD VCC 0402 1 33V 80 20 4 dad cys BV 16V CRST 8588 858858 ESEQ CSERR CARD VCC 9 5958 CPERR CARD_VCC 59959 999999 gt one CINTH CARD VCC 555 5 5228 001 16 CIRDY 845 a 8888 2 8505 canes CREQ V
44. ve CS 5 SBPO SBP1 SBP1 SBP2 SBP2 SBP3 SBP3 SBP4 SBP4 5 5 SBP5 SB 0 5 114 8399 N B Maintenance 8 8 USB Port Test Error 2 An error occurs when a USB 1 device is installed U20 South Bridge 78 F2 MINISMDC110 ALBI o S e 7 7 636 C380 C32 R10 P17 1U 10K 0 1U 330U 10K v USB_OC 0 V 5 USB OCHI J3 cio L L R4 1000P T 560K 1000P T 560K USBP0 V B2 USBPI 2 B boo 122 123 90Z 100M 90Z 100M 1 4 4 a E USBP1 05 0 B3 5VS S p MINISMDC110 ALBI 7 Ton C34 R28 C383 C33 mE 1U 10K 0 1U 330U 10K USB 2 V USB_OC 3 R29 C37 L R26 JA 1000 560K 1000P 560K USBP2 B USBP3 a Un 2 3 3 2 5 120 121 gt 902 100 90Z 100M 1 4 ei USBP3 USBP2 B3 1101 5VS 600Z 100M F4 S p MINISMDCI 10 7 t ALBI C84 Ri95 C101 C384 R212 1U 10K 010 3300 10K P17 USB_OC 4 USB 0885 cass R224 c386 R353 J9 1000P T 560K 1000P F 560K USBP4 un USBP5 2 MAS 197 t t 198 90Z 100M 90Z 100M 1 VVY 4 4 E 05 5 USBP4 B3 115 8399 N B Maintenance 8 9 Hard Disk Driver Te
45. 16 O Flat Panel Vertical Sync For port 1 in dual 12 bit mode GSERR 15 Flat Panel Data Enable For port 1 in dual 12 bit mode FPIDET GD8 AF14 I Flat Panel Detect For port 1 in dual 12 bit mode FPICLK GD2 AE18 O Flat Panel Clock For port 1 in dual 12 bit mode 2 0 Flat Panel Clock Complement For port 1 in dual 12 bit mode Compensation Signal Name Signal Description RPCOMP AI Host CPU P Channel Compensation Connect 50 0 1 resistor to GND RNCOMP 026 Host CPU N Channel Compensation Connect 50 0 1 resistor to VCCHT RTCOMP C26 JAI Host CPU Compensation Connect 100 0 1 resistor to VCCHT VLPCOMP ADI9 V Link P Channel Compensation Connect 360 0 1 resistor to ground AGPNCOMP WI AI N Channel Compensation Connect 60 4 51 1 resistor to VCCAGP AGPPCOMP P Channel Compensation Connect 60 4 0 1 resistor to GND Clock Reset Power Control General Purpose I O Interrupts and Test Signal Name I O Signal Description GCLK AGP Clock 66 MHz clock for AGP logic DCLKI Dot Clock Pixel Clock In For spread spectrum DCLKO Dot Clock Pixel Clock Out For spread spectrum RESET Reset Input from the South Bridge chip 3 3V tolerant input When asserted this signal resets the chip and sets all register bits to t
46. 3 1808 10 g ood L105 18506 Sec soure 291000923002 i 400UH ET Protector NA 4 1 i 667 SHORT SMT4 __ 1000P GND GND GND 1808 1 77 ve 10 RING GND MINISMDC110 NA AUDIO CODEC ON MOTHERBD AUDIO CODEC ON DAUGHTER BOARI AE 1 0 5 0402 MiTAC lt Title gt Pze Document Number Doc Roo I I Date 20 2004 Bheet 16 o 26 5 I 3 z PDF created with FinePrint pdfFactory trial version http www fineprint com USB2 0 amp Flash F2 5 8 lo N jo MINISMDC110 4 RH us R10 u25 1 10K caso 1 10K 12 1 ISA_SAO 10 a 042 GU 212300 0402 9 500 14 00 ao TSA SAT 0402 1 0402 20 1 1 Eu 1 10 ISA SA2 ton ene USB lt 9704 gt 8 9 503 11
47. C264 ozu cmi XIR DDR 52 474 0402 16V 0 220 167 0603 Place between the processor and DDR 4 8 0804 243 1 5136 1 XIR eo 114708002 Bestest SO DIMM Nets engri MEMADD B2 C202 1 4m cos to the processor should be MEMADD 0805 0 220 167 0603 B MEMADD B10 4 478 C239 1 XIR 500 1000 1 2 MEMADD_BI0 13 MEMADD 4 RPXB T 0220 16v 1 Sec soure 331660020005 MEMADD PERS DDR BAAI 5 1 C256 1 XIR soure 291000622007 2 DDR BABI m Ag 6 Place a every 1 OS CON OR XR MEMADD AG im inch on VIT trace DDR CLKO MEMADD 4 RPXE between Clawhammer and 2 DDR DDR CLKOF Locate close MEMADD I 2 DDR_CLKO DDR DDR CLK5 X7R MEMADD B1 0 Hier pon CLKSF itors MEMADD A10 9 1 25VTT DDR CLK7 2 DDR DDR_CLK7 C123 1000 1 25 8 MEM MEMADD 12 2 DDR_CLK7 0402 20 MEMADD B9 DDR 206 1 100P MEMADD B5 4478 o oek 0402 BET C272 2 MEMADD 18 B8B 4 RPXB C120 1 100 0805 MEMADD DDR s 0402 109 C247 1 0220 MEMADD B4 6 1 2 DDR E 100P 06030 MEMADD B3 0402 10 MEMADD A5 9 DDR CLK6 C132 1 100 Locae close to DIMMs GND amp Aa E DDR CLK6 63V 0805 MEMADD Aii gt RPTE MiTAC 2 1 10u 4 MEMADD A12 MEE 08
48. 040 104 040 MD40 3 6 6814 CPU 039 6 1206 MD39 039 1206 CPU MD38 5 4 038 MD38 1 C149 1 C222 1 MD35 18 1 AP24 MD35 DOM4 18 1 0402 10 0402 10 prm CPU DOMI 1 108 DOM4 MD35 1 5878 0274 1 0 1U C203 1 CPU MD34 14 RPXE MD34 MD34 714 RPXE 0402 10 0402 10 CPU DOS4 13 4 0054 0054 13 4 C268 1 C215 1 0 1U CPU MD37 31 MD37 MD37 31 5 0402 10 0402 10 CPU MD36 11 amp 036 MD36 11 6 C279 1 0221 1 0 1U CPU MD33 10 MD33 MD33 10 0402 10 0402 10 CPU MD32 9 032 MD32 9 C263 1 C244 1 0402 10 0402 10 CPU MD27 16 1 BP25 MD27 46 1 1 C288 1 C253 1 DDR CLKO DDR CIKI CPU MDSI 1 10 8_ MD27 15 68 8 0402 10 0402 10 DDR_CLKOF DDR CPU MD30 14 RPXS MD30 MD30 14 RPXE C217 1 C280 1 0 1U CPU MD26 13 4 MD26 MD26 13 4 0402 10 0402 10 DDR CKEA DDR CKER DDR CKEB DDR CKEB CPU DOMS 1 DOMS DOMS 1 2 CPU base CPU 0053 11 6 0053 DOSS 11 6 1 MEMADD 11 MEMADD B1 MEMADD B11 CPU MD29 10 MD29 MD28 10 alternating MEMADD 9 MEMADD MEMADD B9 MEMADD B8 CPU MD25 9 25 MD25 9 along V CPU MD28 74 1 RP26_ 028 MD28 4 RP32 MEMADD A7 MEMADD A6 MEMADD B7 MEMADD 024 104 MD24 MD24 3 6 684 MEMADD 5 MEMADD 4 MEMADD B5 MEMADD B4 CPU MD23 6 1206 MD 3 MD23 1206 MEMADD 2 MEMADD B3
49. COVERjHINGE 8599 531020237 KBD 88 ULK080818G1 8599 OPTION 441684111 LCD ASSY IS XGA HYDIS 8399 PART NAME OPTION SEE NOTES TREATMENT 0 6 6 30 30 80 APPR VED MATERIAL AD DRAWING 8399101 75 3 0 1XUIA 1X 926268412002 ROOA 80 180 CONTENTS OF CHANGE 180 315 315 800 MiTAC Technology Corp model name8399_MAIN_ASSY File nameDRW 6399 MAIN ASSY SHEET 1 OF 1 1 SB VT8235CD 3 3 TV Encoder amp Interface 5 I I I MODEL 8399 Revision 03 Contexts Title Page Flean TOUCHPAD COVER SHEET SCREW 1 PE ClawHammer HT amp DDR 1 2 2 LABA AMSZ9SI for miror nne Power plane 2 2 3 DIMM SLOT amp Termination 4 ou T OL PN E 52951 but add Ve between eid s for cost Clock Generator 5 4 is NB VIA K8N800 1 2 6 77 NB VIA K8N800 2 2 7 SB VT8235CD 1 3 8 SB VIA_VT8235CD 2 3 9 rete AbeTe sox j 10 11 LVDS Encoder amp connector 12 4 HDD CD Conntor
50. PLL Reference Clock FBCLKOUT H L O IOD Clock PLL 200 MHz Feedback Clock 72 8399 N B Maintenance 5 2 VIA K8N800 North Bridge 1 AGP Bus Interface Signal Name Pin Signal Description AGP Bus Interface Continued GD 31 0 see pin list IO Address Data Bus Address is driven with GDS assertion for AGP style transfers and with assertion for PCI style transfers GC BE 3 0 GCBE 3 0 for 4x mode ADII ADIS Command Byte Enable Interpreted as GC BE for AGP 2x 4x and GC BE for 8x For AGP cycles these pins provide command information different commands than for driven by the master graphics controller when requests are being enqueued using GPIPE 2x 4x only as GPIPE isn t used in 8x mode These pins provide valid byte information during AGP write transactions and are driven by the master The target this chip drives these lines to 1000001 during return of AGP read data For PCI cycles commands are driven with GFARME assertion Byte enables corresponding to supplied or requested data are driven on following clocks GPAR ACI6 AGP Parity A single parity bit is provided over GD 31 0 and GC BE 3 0 GDBIH GPIPE GDBIL ACS AC4 Dynamic Bus Inversion High Low AGP 8x transfer mode only Driven by the source to indicate whether the corresponding data bit group GDBIH for GD 31 1
51. 10 15 1 0 3 LADS LADO 9284 04 GP45 TXD A20G 8 Au 78 11 LPC GP86 SD6 GP70 SIN2 T DATA 13 8 160 1202 100 1608 LADO 10 15 LERAME 87 807 KBC SB PWRBTN 20 SW 4SVDD3 lt es og H opsovao GP73 SRDY2H INT21 13 H 52 3 e 2023 GPS3 INT40 W GP75 NT41 4 lt 7 susc 921 23 LEARNING GP42 INTO OBFOO 20 KBC_SUSB GP43 INTI OBFO1 GP20 FD0 LPCEN 8 upr S8 10 ER SSL 18 GP46 SCLK1 OBF1 GP2UFDi pate GP22 FD2 SDAT RXD1 Gi 13 GP23 FD3 SCL1 TXD1 BATT R 13 E H i GP76 SDA GP24 FD4 32 13 2 GP77 SCL GP2S FDS 13 FANO GP26 FD6 32 NUM 13 R285 10 1 0402 SB PWRBIN 4501 FANT GPerirD7 13 R293 10K1 0402 WAKE UP AGUNT Bers 10K 0402 EXTSMIY 24 SELL TYPE 13 gpsaionTRo 6 BLADJ 12 pts 13 AC_POWER GPSS CNTRI GP57 DA2IPWM1 t CTRL 24 BAV7OLT1 17 lt 4 GPO PSREF FAO GP6O ANOINTS 1 POWERBTNE POWERBTN 17 J Bei oz 1 1 GP61 AN1 INT6 80 KBC_PWRON_ VDD3 20 on EY GP62 AN2 INT7 28 sar VoLT CHARGING 24 i BAT 4SVDD3 kor GPa FAS 6 BAT TEMP t BAT V 23 lt GP64 AN4 INTO 2
52. 2 gt d gt 140 9 Spare Part List 9 Part Number 333020000008 333025000004 333050000120 335152000044 335152000085 335152000094 335152000100 338536010006 339115000046 340682900001 340682900002 340682900003 340682900004 340682900005 340682900006 340682900009 340682900010 340682900011 340682900015 340682900017 340682900018 340682900021 340682900022 340684100001 340684100003 Description SHRINK TUBE 600V 125 C 02 5mm L SHRINK T UBE 300V 125 I D 2 5 T 0 SHRINK T UBE 600V 105 C D0 8 9MM CFM BAT FUSE THERMAL 98 C FUSE 128 DC 7A 50V 139 C only UC FUSE LR4 900 POLY SWITCH FUSE T HERMAL SF91E 1 94 C 10A 2 BATT ERY LI 3 6V 2 0AH 18650 PANA MICROPHONE 62dB 2dB D6 0 H2 7 HOUSING ASSY LCD 8599 COVER ASSY LCD 8599 HINGE R 8599 HINGE L 8599 HINGE R SZS 8599 HINGE L SZS 8599 BRACKET ASSY T OUCH PAD 8599 SPEAKER ASSY 28 4 3 2 W FENG CHI SPEAKER ASSY 28 4 3 2 W VECO 859 HOUSING ASSY BOT TOM 8599 COVER ASSY CPU 8599 COVER ASSY MINIPCI 8599 SHIELDING ASSY HDD 8599 DVD RW BEZEL ASSY SDW 041 8599 COVER ASSY TOP 8399 SHIELDING ASSY BOTT OM 8399 ocation S C3 cn 399 N B Maintenance 240684100004 HEATSINK ASSY CPUK8 HAMMERMPT 240684100005 pr TsNCASYCUUKPMAMMERANC 340684100006 HAETSINK 55 5 5 839 71 HAETSINK ASSY SYSTEM M B AVC 839 po seme 342502900001 CONTACT PLATE W4L
53. 5 1 05 060 060 5 1 08 010 012 5 1 08 080 090 5 1 08 150 024 8399 N B Maintenance foroen 371102610406 screw staked 371102610607 SCREWAMROL6K HEADNB 373101712351 T SCREW B M1 7 L2 35 K HD 2 NIB 370103010414 SPC SCREW M3L4 KHD NIW NLK DS 3 142 9 Spare Part List 11 Part Number 377244010002 411678100001 411678100002 411684110001 411684110002 411684110003 411684430001 411684430002 412681400001 412684100001 412684110001 413000020433 416268411001 421675400012 421682900001 421682900011 421684100003 421684100005 421684110001 422682900001 422682900002 422682900003 431684110001 441684110001 441684400003 Description STANDOFF 24 40DP3 5H5L5 5 NIW PWA PWA INVERTER BD DA 1A10 A PW PWA PWA INVERTER BD SMT DA 1A10 PWA PWA 8399 MAX MOTHER BD PWA PWA 8399 MAX MOTHER BD T U PWA PWA 8399 MAX MOTHER BD SMT PWA PWA BATT PCB BD LI 4 0Ah BL4 PWA PWA BATT PCB BD SMT 4 0Ah BL PCB ASSY WIRELESS LAN CARD MINI CFM Medion PCB ASSY FAX MODEM 5 FAX MODEM KIT Creatix 8
54. PCI37 PCI40 27 PR103 Sia 10U 0 10 1000P 10U rci L PR102 4 PON 100K 0 1U 20K MMBT2222A V 4 7 2IN m e BAS32L V 24 DTAI44WK 128 PR101 PR100 PR104 0 010 13 7K 249K 23 7K 222 22 TLS CHARGING PQ25 9 m a PR89 From U16 2N7002 KH en 47 L GND PC144 6 010 2 2 OUTPUTCTRL 14 REF J 2IN V 15 2 138 PR96 PROS 141 0 10 10K 0 01U T PCI35 lt PCI32 lt PRIO mes 1U 100K 1000P 10K 133 0 10 V e V PJS501 SHORT SMT3 10 I CTRL V P19 PQ22 U16 79 CHARGING 2N7002 KBC V ll Controller SELL PR84 0 2 27002 105 8399 N B Maintenance 8 4 No Display 1 There is no display on both LCD and monitor after power on although the LCD and monitor is known good No Display Monitor No Replace monitor or LCD module LED Board level OK Troubleshooting Make sure that CPU module DIMM memory are installed Yes Properly Replace Motherboard Using debug card depending on the error codes to make sure which parts maybe faulty 1 Try another known good CPU module DIMM module and BIOS 2 Remove all of I O device FDD HDD CD ROM motherboard except LCD or monitor Using circuit diagram check the faulty parts 1 Replace faulty part Di
55. Primary EIDE Connector J15 MDC Board Connector J16 J17 Extend DDR SDRAM Socket J18 Touch Pad Connector J20 RTC Battery Connector J21 Secondary IDE Connector 6 6 o0 9 22 Mini PCI Socket Pee SW1 H8 Reset Button 68 8399 N B Maintenance 3 Definition amp Location of Connectors Switches 3 2 Mother Board B 58 1501 Internal Keyboard Connector 1502 PCMCIA Card Socket SW501 Power Button 1501 SW502 Touch Pad Up Button SW503 Touch Pad Right Button SW504 Touch Pad Left Button t 0 9 SW505 Touch Pad Down Button 69 8399 N B Maintenance 4 Definition amp Location of Major Components 4 1 Mother Board A U2 VT6103L LAN Controller E a D 03 TV Encoder VIA VT1622 U13 U6 AMD CPU Socket U9 LVDS Encoder VIA VT1634 U9 U10 VT1617A Audio Codec 012 VIA K8N800 North Bridge U13 G1428 Sounder Amplifier U14 ICS950403 Clock Generator U16 KBC W83L950D U20 VIA 8235 South Bridge E 025 LPC BIOS ROM U26 CB1410 PCMCIA Controller 70 8399 N B Maintenance 5 Pin Descriptions of
56. TVD4 DVPOD4 TVD3 DVPOD3 TVD2 DVPOD2 K3 TVD1 DVPODI K2 DVPODO DVPOHS 4 Encoder 0 Horizontal Sync Internally pulled down TVVS DVPOVS N3 TV Encoder 0 Vertical Sync Internally pulled down TVDE DVPODE NI O Encoder 0 Display Enable Internally pulled down TVCLKR DVPODET 4 I TV Encoder 0 Clock Return Input from TV encoder Internally pulled down TVCLK DVPOCLK P3 Encoder 0 Clock Out Output to TV encoder Internally pulled down The above pins may be connected to an external TV Encoder chip such as a VIA VT1622A or VT1622AM for driving set pads for the pins on this page are powered VCCGFX 3 3V I O Analog Power Ground Signal Name Pin 10 Signal Description VCCATX C22 Analog Power for HT Transmit 3 3V 5 Connect through a ferrite bead for isolation of digital switching noise GNDATX C21 Analog Ground for HT Transmit Connect to main ground plane through a ferrite bead for isolation of digital switching noise VCCARX E25 Analog Power for HT Receive 3 3V 5 Connect through a ferrite bead for isolation of digital switching noise GNDARX E26 Analog Ground for HT Receive Connect to main ground plane through a ferrite bead for isolation of digital switching noise AGP Multiplexed Digital Video Port 1 GDVP1 TMDS Interface
57. 0 07 FPD1D07 GD4 AD16 Double data rate each rising amp falling clock FPD06 FPD1D06 GD5 AE16 edge transmits a complete 24 bit pixel 05 FPD1D05 GD6 AF16 3C5 12 4 1 amp 3 5 88 2 0 amp 3x5 88 4 1 FPD04 FPD1D04 GD7 15 Single data rate each clock rising edge FPD03 FPD1D03 GADSTBOF 15 transmits a complete 24 bit pixel FPD02 FPD1D02 15 In dual 12 bit mode FPD01 FPD1D01 GADSTBOS AD13 3C5 12 4 0 amp 3x5 88 2 1 00 FPD1D00 0010 AF13 Each rising and falling clock edge transmits half GD12 12 bits of two 24 bit pixels FPHS GFRAME 9 O Flat Panel Horizontal Sync 24 bit mode or port 0 of dual 12 bit mode FPVS GDEVSEL O Flat Panel Vertical Sync 24 bit mode or port 0 of dual 12 bit mode FPDE GD19 AD9 O Flat Panel Data Enable 24 bit mode or port 0 of dual 12 bit mode FPDET GADSTBIS AF7 I Flat Panel Detect 24 bit mode or port 0 of dual 12 bit mode FPCLK GD21 AF8 O _ Flat Panel Clock 24 bit mode or port 0 of dual 12 bit mode FPCLK GWBF O Flat Panel Clock Complement 24 bit mode or port 0 of dual 12 bit Mode 77 8399 N B Maintenance 5 2 VIA K8N800 North Bridge 6 24 Bit Dual 12 Bit Flat Panel Display Interface Continued Signal Name Name Pin Signal Description FP1HS GD9 AD14 O Panel Horizontal Sync For port 1 in dual 12 bit mode FP1VS GPAR
58. 13 SMBDATA_DDR MEMADD_A7 59 SME DATAO SMBCLK DDR NZ MEMADD Bii 6 lt Title gt 58 SMB_CLKO MEMADD_B7 10 Eze Toocument lev Number lt Doc gt ROO Date 20 2004 Bheet 4 of 26 5 z 3 I z T PDF created with FinePrint pdfFactory trial version http www fineprint com 43 o L58 ura VDDREF 0 cpuciksco 4 i3 1202 1 4 VDDREF 1 CPUCLKSTO 41 15 R247 CPUCLK8C1 0603717 15 R245 R809 100 VDDPCI 0 CPUCLKETI CPUCLK 2 VDDPCI 1 bee 0805 19 13 0603 1 27 _ 8246 PCI CARD 4 VDDPCI 2 PCICLKO 13 06031 27 B248 PCI 14 ON for 15 950403 J 1 Bp 0603 27 R249 RTM360803 R251 V _ cen VDDCPU 1 PCICLK3 58 QE DH 1 R262 1 22 0402 0402 RLS4148 0402 0402 R264 1 22 0402 1 gt CLK_LPC33 ICS PD 254 1 of 380208 280 20 5 lt gt VDDA PCI
59. CD DVD ROM HDD CPU keyboard and battery pack See sections 2 2 8 2 2 6 2 2 5 2 2 4 2 2 3 2 2 2 and 2 2 1 Reassembly 65 8399 N B Maintenance 2 2 12 Touch Pad Disassembly 1 Remove the system board See section 2 2 11 Disassembly 2 Remove the two screws and disconnect the cable then free the touch pad Figure 2 27 Figure 2 27 Free the touch pad Reassembly 1 Replace the touch pad and reconnect the cable 2 Replace the touch pad shielding and secure with two screws 3 Reassemble the notebook See the previous sections Reassembly 66 8399 N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Mother Board A 1 J10 J12 J9 J5 Power Jack PJ2 Battery Connector N O J1 S Video Port J2 External VGA Connector J3 J4 J9 USB Port Connector 15 RJ11 amp RJ45 Connector J6 North Bridge Fan Connector J7 MDC Jump Wire Connector J8 LCD Connector J10 Microphone Jack vun ppp J11 CPU Fan Connector 0 96 J12 Line Out Jack lt To next page PJ2 67 8399 N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Mother Board A 2 L J13 Internal Speaker Connector J14
60. DO 4 PCI Local Bus Specification Revision 2 2 PCI Bus Power Management Interface Specification Revision 1 1 PCI Mobile Design Guide Version 1 1 Advanced Configuration and Power Interface Specification Revision 1 0 PC99 System Design Guide PC Card Standard 8 0 Interrupt Configuration Support parallel PCI interrupts Support parallel IRQ and parallel PCI interrupts Support serialized IRQ and parallel PCI interrupts Support serialized IRQ and PCI interrupts T 8399 N B Maintenance Power Management Control Logic Support CLKRUN protocol Supports SUSPEND Support PCI PME from D3 D2 D1 and DO Support PCI PME from D3 cold Supports D3STATE Power Switch Interface gt Supports parallel 4 wire power switch interface Misc Control Logic Support CLKRUN protocol Support serial EEPROM interface Support socket activity LED Support 5 GPIOs and GPE Support standard Zoomed Video Port Support SPKOUT CAUDIO and RIOUT Support PCI LOCK 32 8399 N B Maintenance 1 3 6 One Slot PC Card Power Interface Switch ENE CP 2211 CP 2211 is single Slot PCMCIA and CardBus power switch It integrates control logic low switching resistance MOSFET over current alarm and over temperature auto shutdown circuits It can deliver 3 3V or 5V to PC Card VCCOUT and 3 3V 5V or 12V to PC Card VPPOUT The output current is up to 1A for VCCOUT and 250mA for VPPOUT Low Switc
61. Ground Connect to primary motherboard ground plane list Strap Pins for North Bridge Configuration Signal Name Pin Function Description Note SDCS3 AF26 NB SDCS3 signal state is reflected Check the Configuratio signal pinVD 7 during power up NorthBridge DS n for North Bridgeconfiguration fordetails SDA2 24 NB SDA2 signal state is reflected on Check the Configuratio signal pinVD 6 during power up NorthBridge DS n for North Bridgeconfiguration fordetails SDAI AC22 NB SDAI signal state is reflected Check the Configuratio signal pinVD 5 during power up NorthBridge DS n for North Bridgeconfiguration fordetails SDAO AF24 NB SDAO signal states is reflected Check Configuratio signal pinsVD 4 during power up NorthBridge DS n for North Bridgeconfiguration fordetails Strap VD3 AC6 NB Strap signal state is reflected Check the Configuratio signal pinVD 3 during power NorthBridge DS n up for North Bridgeconfiguration fordetails Strap VD2 ADS NB Strap VD2 signal state is reflected Check the Configuratio signal pinVD 2 during power NorthBridge DS n up for North Bridgeconfiguration fordetails Strap VDI AES NB Strap VD1 signal state is reflected Check the North Configuratio on signal pin VD 1 during power Bridge DS for details n up for North Bridge configur
62. KM266 P4M266 P4N266 See app note AN222 for non maskable interrupt to the CPU The details VT8235 Version CE generates an NMI when PCI bus SERR is VBE G24 IO Byte Enable asserted I V Link Clock SLP V26 OD Sleep Used to put the CPU to sleep SMI U25 OD System Management Interrupt SMI is asserted by the DNCMD K25 I Command from Host to Client Made CE tothe CPU in response to different Power Management events UPSTB J26 Strobe from Client to Host STPCLK R24 Stop Clock STPCLK is asserted by the VT8235 Version CE UPSTB J24 Complement Strobe from Client to Host to the CPU n processor clock BTE Strobe Hosto mient Note Connect each of the above signals to 150 gU pullup resistors to CMOS see Design Guide DNSTB H24 I Complement Strobe from Host to Client 80 5 3 VIA 8235 South Bridge 2 8399 N B Maintenance Advanced Programmable Interrupt Controller APIC Interface Signal Name Pin Signal Description APICDI T23 Internal APIC Data 1 Function 0 Rx58 6 1 APICDO R25 Internal APIC Data 0 Function 0 Rx58 6 1 APICCLK U23 I APIC Clock CPU Speed Control Interface Signal Description GPI29 GPO29 Voltage Regulator Deep Sleep Connected to the CPU voltage regulator High selectsthe proper voltage for deep sleep mode This pin performs the VRDPSLP function if Function 0 5 3 0 GHE GPD2 R2
63. L0 CADOUT 17 NC R2 4 DDR RASA lt DDR RASBE MEMRASA L MEMDOS 10 L0 CADOUT NC 4 DDR_RASB MEMBESET MEMRASB_L 5 11 10 CADOUT 0402 CPU Tesa O1 910 1 MEMRESET 1 MEMDOS 12 L0 CADOUT RESET L 402 CPU PWROKCZS ru a 1 25VSREF CLA DOR wen MEMDAS 13 L0 CADOUT PWROK as MEMWEA L MEMDQS 14 10 CADOUT 2 TRST HE DDR _WEB F4 MEMWEB L MEMDOS 15 10 TMS Aon TB MEMZN MEMDas 16 L0 CADOUT THERMTRIP EE CPU THERMTRIP amp 20 P8284 2 MEMDOS 17 THERMDC 222 XHERMDA CPU 5 9 THERMDA 422 TDO TUERMDASD GUAM LO R101 1 4941222 0402 T 421 Remove resistors E7 TCK LO CTLIN 11 R107 1 79412 0402 CLAWHAMMER BGA754 SKT V 291000617542 SINCHN R152 1 490 52 2 0402 BOAT BANE R139 1 0402 71 425VS DDR 9 Change to 34 8 Ohm y bene 4 CPU THERMTRIP amp R135 1 0402 R235 1 100 LOTSTOPI R97 amp B 0402 f 2 5VS_DDR J 0402 1 25VSREF_MEM 1 9 1 CPU RESET R148 1 jg A p 042 1 25VSREF_CLAW i 348 1 i MEMZN R180 T 1 1 1 CPU PWROK 25V 161 1 2 0402 SN 10 140 1 348 1 16V R261 C266 cass caso 0805 MEMZP 1 2 R174 100 90470 1000P 4 4 1 7 1 0 220 0603
64. Signal Name Name Pin I O Signal Description GDVP1D11 GC BE3 O GDVP1D10 GD26 AE6 GDVP1D9 GD24 AF6 GDVP1D8 GD30 AE4 GDVP1D7 GD28 5 GDVP1D6 GD29 AF4 GDVP1D5 GSBA4 AF2 GDVP1D4 GD27 ADS GDVP1D3 GSBAS AD3 GDVP1D2 GSBSTBS GDVPIDI GSBSTBF AFI GDVP1D0 GSBA2 ADI GDVP1HS GSBA3 AD2 Sync GDVPIVS GSBAO AC2 O Vertical Sync GDVPIDE GSBAI1 O Data Enable GD31 AD4 I Display Detect If VGA register 3C5 3E 0 1 3C5 1A 4 will read 1 if a display is connected Tie to GND if not used GDVPICLK GSBA6 AE3 O Clock GDVP1CLK GSBAT O Complement GDVP1 Digital Video Port is supported through multiplexing its interface signal pins with AGP pins GDVPI can be configured as either a TMDS transmitter interface port or a TV Encoder interface port see the TMDS Transmitter Interface and TV Encoder Interface pin lists below for details Reference Voltages Signal Name VLVREF Signal Description V Link Voltage Reference 0 625 V 4 resistive voltage divider 3K U to 2 5V and 0 to ground See Design Guide for details 2 derived using a 1 0 Voltage Reference 0 5 0 75V for 2 0 4 transfer mode and 0 23 0 35V for 3 0 8x transfer mode See the Design Guide for additional information and circui
65. lO e Az Qiu O gt a ro e wo d e oo e NS gt D 32 gt gt e D intenance 137 9 Spare Part List 6 Part Number 272625220401 272990100301 273000130001 273000130006 273000130019 273000130038 273000130062 273000150002 273000150013 273000150313 273000500092 273000500115 273000990018 273000990021 273000990127 273000990186 273001050028 273001050127 274011431414 274013276103 281101015001 282574186002 282607408001 282607408002 282674112601 Description 22 4 8P 50V 10 1206 NPO S 10 3000 5 NPO SMT FERRIT E CHIP 1200HM 100MHZ 1608 FERRITE CHIP 6000HM 100MHZ 2A 1 FERRITE CHIP 1200HM 100MHZ 1608 FERRIT E CHIP 6000HM 100MHZ 1608 INDUCTOR 120nH 1094 0603 SMT FERRIET CHIP 1200HM 100MHZ 2012 FERRITE CHIP 1200HM 100MHZ 2012 CHOKE COIL 900HM 100MHZ 20 2012 CHOKE COIL 2 2UH_ 20 16A 3 5MM CHOKE COIL 400uH MIN 120m INDUCT OR 10uH CDRH125 SUMIDA SMT INDUCT OR 33uH CDRH124 SUMIDA SMT INDUCT OR JHLPS050CE 01 0 68uH VI INDUCT OR 3 0UH 30 CDRH6D28 H2 8 XSFORMER 10 100 BASE LF H41S SMT XFMR CI8 5 30T 2150T 300mH SMT o XT AL 14 318MHZ 32PF 50PPM 8 4 5 XTAL 32 768KHZ 20P PM 12 5PF CM20 IC MP1015EM Z CCFL CTRL TSSOP20 IC 74AHCT 1G86 SINGLE XOR S0T23 S IC 74HCT08PW 2 INPUT AND GATE TS IC SN74HCTO08PW 2 INPUT AND GATE IC 74HCT
66. v 1202 100M SPKR_LOUT 155 1202 100 SPKR LOUT 156 1202 100M 15 17 236 100U R215 From front page U10 L51 600Z 100M YN e L C208 T 1U ITT 218 J12 C227 100U 1 50 600Z 100M 5 YY 120Z 100M WA R218 SENSE 222 217 C224 L 223 100 T 100 5 223 100K 1 C230 214 0 10 010 L 228 11 10 e C233 10 C211 1U From front page U10 AOUT R C210 10 0212 GND From front page U10 139 6002 100 5 9 1 122 8399 N B Maintenance 8 12 LAN Test Error 1 An error occurs when a LAN device is installed 1 Check if the driver is installed properly 2 Check if the notebook connect with the LAN properly Board level Check following parts and signals Troubleshooting Dn TE Correct it Check if BIOS setup is ok Replace Motherboard Re test Correct it 3VS 3VS_ LAN PLL 3VS_ LAN TXD TXD RXIN RXIN PJTX PJTX PJRX PJRX LAN_DATAIO LAN_DCLK LAN_MTXC LAN MRXC MTXD O 3 _ 0 3
67. 0 Fo 10 Address Data USBCLK E23 I USB 2 0 Clock 45 2 clock input for the USB interface AET USBOCO C26 I USB 2 0 Port 0 Over Current Detect Port 0 is disabled if low 8 USBOCI Z D24 I USB 2 0 Port 1 Over Current Detect Port 1 is disabled if low Note Connect the LPC interface LPCRST LPC Reset signal to PCIRST USBOC2 B26 I USB 2 0 Port 2 Over Current Detect Port 2 is disabled if low USBOC3 C25 I USB 2 0 Port 3 Over Current Detect Port 3 is disabled if low USBOC4 B24 I USB 2 0 Port 4 Over Current Detect Port 4 is disabled if low System Management Bus SMB Interface I 2 C Bus USBOCS A24 I USB 2 0 Port 5 Over Current Detect Port 5 is disabled if low Signal Name Pin I O Signal Description USBVCC Hs pin E USB 2 0 Port Differential Output Interface Logic Voltage 3 3 V SMBCKI aS ID 5 12 Channel USBGND see pin Pow USB 2 0 Port Differential Output Interface Logic Ground SMBCK2 AC3 IO SMB I2 C Channel 2 Clock Rx95 2 0 list er 127 GPO27 VSUSUSB C24 Pow USB 2 0 Suspend Power 2 5V 5 SMBDTI AB2 IO SMB I2 C Channel 1 Data er SMBDT2 ADI IO SMB I2 C Channel 2 Data Rx95 2 0 VCCUPLL A23 Pow USB 2 0 PLL Analog Voltage 2 5V 5 GPD6 GPO26 B23 er SMBALRT ABI I AF Alert enabled by System Management Bus space GNDUPLL zm USB 2 0 PLL Analog Ground 3 1 When the chip is enabled to allow it assertion generates an IRQ SMI interrupt or a power management
68. 0010 46 ES UM V IUS m PR109 10 I CHG 3 8 75 57 lloum msi 6 3 LL 147 C306 RS2 RSI amp 2 o lU 5 52 V V MAX4377 V PR108 LDISCHG KBC CPUCORE 74 PC145 0307 1U 0 1U 103 8399 N B Maintenance 8 3 Battery Can not Be Charged 1 When the battery is installed but the battery status indicate LED display abnormal Battery can not Charge Board level Trouble shooting notebook connected to power AC adaptor 2 No Connect AC adaptor Check following parts and signals u Mother board nto ADINP PL19 1 Make sure that the battery is good 21 CHANGING 2 Make sure that the battery is installed properly PD16 PALI PQ23 21N PL20 I CTRL PL18 CHARGING PD14 BATT SELL PD17 E PQ24 PQ25 Yes Please replace the 144 faulty Battery 104 8399 N B Maintenance 8 3 Battery Can not Be Charged 2 When the battery is installed but the battery status indicate LED display abnormal ADINP PF2 Aou PL19 PL20 PL18 PD14 From chapter 8 2 1 TR 3216FF 3A DEAD 120Z 100M 3 3 33UH 3 0UH SSA34 BATT IVY VV gt m ar PCI34 142 L PCI36 139 s 0 01U 10U 0 01U 1000P
69. 0402 EH 0402 0402 0402 f 1 10 10 2 R849 2 R850 2 R851 NC_AE23 R104 1 2 0402 NZ 4 16V 50V ATOINB 470 NA gt 470 NA gt 470 N NC R125 1 590 0402 NA 1 GND 0603 0603 0603 0603 NC AF22 R126 1 0402 GND i 1 2VLDTB 1 1 1 1 12 NC AF23 R103 4 0402 GND 11 Place these 442 1 42 58 DDR j TP513 o 1 DBREG 8119 apacitors close to i 10 REF1 R30 9 4 DBRDY 4 818 SA processor pins i 0603 4 1516 i 7 GND H 442 1 4 12512 6 11 6 T 812 10 REFO 1 8100 4 TDi m 816 i 0603 8184 ciso TP537 1 412 100 0 010 aasvsrer 1988 G1 100 i resistor must C40 1 1000 0402 0402 0402 50V 10 1 10 4 4 2544 DDR O 2 2 more than 4 Jw S RES 1 1000mil from C82 1 300p 042 f N ATOIN 470INA gt 470INA 250 0402 50 16 10 4 2545 DDR 0603 0603 WZ ub is Se bu HUE M BPO MiTAC gt gt Bmils 0 010 0330 1000P 1 e i A trace and 0402 0402 0402 0402 0402 1 FPC FFC 12P 0 5MM NA SCANEN 8167 1 222 0402 mil spacin 1 10 80 20 10 10 6239 012 001 800 SCANSHENA R150 2 0402 p 2 4 50 16 16 sov HDT USE SCANSHENB R1591 2 0402 rite i SCANCLK1 R138 1 amp 2 0402 Title SCANCLK2 5052 0402 T
70. 1 ATK A 2 0402 11 CRT HSYNC HSYNC 11 CRT VSYNC VSYNG GERE DP2HS NB FPHS FPHS 12 0402 GIRDY SBCLK CLK LVDS 12 spi 9 5 GTRDY SESBI 1 0402 4 ase SY AGI NB 12 E s SUSSTI R314 1 2 0402 8 BISTIN INTA GSTOP DP3CLK SESRO 1 0024 m D BISTIN GPAR DP3VS AGPGD3 R105 1 na R39 5 2 0402 GREE X NB 11 SPCLK1 GWBF DP2CLK SS ARCS lt 12 9 11 CRT DDCK SPCLK2 GREQ DDCCLK 11 120 DATA SPDATI GGNT DDCDAT Ladi lt gt AGPNCOMP P90 1 904742 0402 11 CRT DDDA SPDAT2 GSERR DP3DE A AGPPCOMP R81 1 AOAI 2 0402 Lo 11 TVDOO DPODOO STRAP GCLKq ALL lt 66 AGP 5 lt 7 11 TVD01 DP0D01 STRAP 11 2 TVDOZ DPODO2 STRAP 2 11 TVDO3 DPODOS STRAP SBA1 DP1DE 2 11 TVD04 DPOD04 STRAP SBA2 DP1D00 S21 11 TVDS TVDOS DPODOS STRAP SBA3 DP1HS AD2 x 11 TVD6 TVDOG DPODOG STRAP SBA4 DP1D05 2 x 11 TVD7 TVD07 DPODO7 STRAP SBAS DP1D03 423 11 TVDB TVDOB DPODO SBAG DP1CLK 11 TVD9 TVD09 DP0D09 SBA7 DP1CLK 11 TVD10 TVD10 DPOD10 STRAP 11 TVD11 DP0D11 SBSS SBS DP1D02 AELx ER 4 SBSF SBS DP1D01 11 TVCLKI 0402 ENAVEE 11 WDS NL AA ENAVDD ENAVEE 12
71. 13 is Cardbus Controller 14 aaa Mini PCI Interface 15 3 For CPU LAN PHY 16 los USB2 0 amp Flash ROM 17 4 Audio CODEC 18 kis fh A KBC W83L950D 19 153010070 bul POWER ON PERPHERIAL CIRCUIT 20 1 25V LP2996 amp 2 5V RT9202 21 1 5 amp 1 2V SC338 22 ADINP amp Discharge 23 For PCMCIA FD501 FD502 FD503 FD504 i i Charging 594 24 2 9 CPU core ISL6559 25 3V 5V LTC3728 26 MTGSO1 MTG502 1D4 5 0D7 0 1D4 5 0D7 0 MTG20 103 0 007 0 MTG118 RD276 30X12 MIS 2 DRAWN DESIGN CHECK ISSUES MiTAC Number 411684100001 Date EHN 20 2004 Bheet 1 o 26 5 z E 2 T PDF created with FinePrint pdfFactory trial version http www fineprint com
72. 161 5 0603 5 RES2 7K 1 16W 5 0603 SMT RES301K 1 16W 1 0603 SMT RES3K 1 16W 1 0603 SMT RES33 1 161 5 0603 SMT 523 1 16W 5 0603 SMT 523 1 16W 596 0603 SMT 8399 N B Ma ocation S R9 Jd Im E es o oo 6 S D R132 E c PR61 PR68 PR9 PR91 168 Fu 2 gt 5 1 PR48 PR65 PR70 R9 ro RIZ 5 lt gt gt A E qe R13 R3 a o 8 intenance 135 9 Spare Part List 4 Part Number 271571000301 271571100301 271571470301 271571680302 271586026101 271591000701 271591220301 271591470301 271591471301 271611100301 271611102301 271611103301 271611153301 271611330301 271611680301 271611750301 271621103302 271621222301 271621472302 272001105403 272001106702 272001106703 272001475403 272001475701 272002105701 Description RP 0 8 16P 1 16W 5 1606 5 RP 10 8 16P 1 16W 5 1606 SM RP 47 8 16P 1 16W 5 1606 SM RP 68 8 16P 1 16W 5 1606 SM RES 02 2W 1 2512 SMT RP 0 4 8P 1 16W 1 0804 SMT RP 22 4 8P 1 16W 5 0804 SMT RP 47 4 8P 1 16W 5 0804 SMT RP 470 4 8P 1 16W 5 0804 SMT RP 10 4 8P 1 16W 5 0612 SMT RP IK 4 8P 1 16W 5 0612 SMT RP 10K 4 8P 1 16W 5 0612 SMT RP 15K 4 8P 1 16W 5 0612 SMT 3384 8P 1 16W
73. 16V 2 49K GND 50 0603 0603 0603 10 1 2 9502 gt OPEN SMTA PJSS01 gt 19 Lore gt SHORT SMT3 D VMAIN 5 003 9 9 5003 T Y p 34 L rciz 3 3K NA 01U NA PR77 0603 0603 590K NA PRB a ej 50v 0603 100 1 0603 2 GND d 125V REF n i Eos 2 gt DEAD P 19 PUI8B 8 56v JL 4 LMV393M NA NA Z SsoPs 122 GND 4 PR78 0 1U NA pata 100K NA 0603 SOT22N PR79 0603 50V SCK431LCSK 5 NA 287 50V 1 0603 DVT ve 1 PC143 change from 1000P to 0 1U 50V 1 2 PR101 change from 1 to 0 1 57 NE GND sZ 1 PR104 change from 24 3K to 23 7K 271071237211 for 8 cell charging voltage 16 9V PJOS SELL 2N700 penp PR81 ORA AA lt Title gt N 7 Brze lev 556 Document Number lt Doc gt Date 20 2004 Bheet 24 of 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com PLO 1 BEAD 1202 100M 08050
74. 19ENBL LCD 102 1 4 1206 470 0402 15 7 C gt R124 06030 23 24 gt GND GND a 1 BEAD 2002 140 G 1 BLADJ 19 8 ENBL SB Leo Ri22 1 AYA A 2 0603 B i GND RIAN 1 0 125 1202 00 1608 16 1202100 608 i enn cats LCD Panel ID R102 0402 ENAVDD IG i 7 IL MAJ5PX2IST 0402 T T T 8106 1 0402 0 10 ACES 000 LCDID2 LCDIDI LCDIDO PANEL ENAVEEST 0402 87216 3002 80 20 sov i HSD150PX14 A Hannstar cio HT15X34 100 Hydis 52 LPNISOXB LO3 Samsung 0402 BISOXGO2 1 AU 480 2054 1 QDISXL06 01 2 QDI 7 LPISOXOS A3 Le Phillips a o X Layout Note MiTAC S W W S 10 8 8 10 mis T as short as possible lt Title gt Document er Number Doc Date EHM 20 2004 Bheet 12 of 26 5 z 3 I z T PDF created with FinePrint pdfFactory trial version http www fineprint com 9 IDE PDD O 15 PDDO 61 HDD PDDi HDD PDD2 HDD PDD3 HDD amp CD ROM Conntor Sec soure 331030044023
75. 1G126GW NON INVERTING BU 8399 N B Ma ocation S N C3 ro L100 L101 L43 L48 L50 L501 L5 L10 L11 L12 L13 L14 L15 L16 L L38 L39 L40 L49 L57 R124 es L2 L24 L27 L29 L3 L30 L32 L33 E 9 L a x az c le _ to das c gt gt _ R Z gt N Te Spy D 120 0 18 X3 X6 ci gt intenance Part Number Description Location S 282674112602 IC SN74AHCT IGI 26DCK NON INVERTIN 282674244004 1 74 2440 TRI ST BUF SOIC 023 024 ficrLasiasexes roptccs2 azso U U U U U U 114 113 138 9 Spare Part List 7 Part Number 286304377001 286306207001 286306559002 286308800007 286308804002 286329513001 286369229301 286387506001 288100014010 288100032013 288100034004 288100054002 288100056003 288100056005 288100056017 288100701002 288101040006 288104148001 288105524003 288110355001 288111544001 288200144003 288200144008 288200301001 288200416001 Description MAX437TF SENSEAMP MSOP8 S ICIISLG207CB PWM DRIVER SO8 SMT IC 1SL6559 MULTI PHASE PWM CTL S IC AME8800DEFT VOL REG SOT89 3P IC AME8804AEEY ADJ 0 3A LDO SOT2 IC A
76. 2 14 o 38 R142 1 AJK 2 0402 ud M PLLVCC BNDPLL 1 x LV R196 A7K jA 2 0402 4 1202 100 PLLGND ds TXOUT2 cate 4 amp TXOUT2 LV RES Ri44 4 47 0402 GNDLVDS 0 2 LA 547 11280 25 GNDLVDS 1 4 amp TXOUTI 80 20 Em 0 10 0 010 GNDLVDS 2 Ate 050 0402 0402 DVDD LVDSGND GNDLVDS t 80 20 80 20 80 20 49 TXOUTO SZ 50V 50V voc 0 0 f 50 TXOUTO GND VCC 1 0 eves voca LVIPSEL R415 1 AJ 0402 LVDSVCC voccs CE H Pye LV DUAL es VCCLVDS 0 VCCPLL 1 AEN DUAL 140 1 AK A 2 0402 PLLGND VCCLVDS 1 mopser 67 P197 1 2 0402 9 LV EDGE R143 0402 1634 va PQFP100 0 5MM 1 2 0603 7 LVOSGND f DUAL pin23 _ Remove R10 lt gt 9 Install 88 GND PLLGND i Remove For two channel panel High Install R10 10 LCD 100 9 LOD 1D1 1 60302 8 1601102 1206 LCD 40 mils LCD 14 330mA 15 800mA 40 mils N3 50723 FET Ja o CLOSE 400 Y 1 nan 3V 3 4 Close ta LC Connecto TXOUT2 6 TXCLK 1 TXOUT2 8 TXCLK M 4 4 1 9 10 4 42 C21 C22 c20 9 TXOUTI it 1 1000P oiu 0 10 TXOUTI 13 14 TXOUTO 0402 0402 0402 1206 0402 PWR VDDIN 10K 1 1 16 1 i 10 80 2094 10 10v 4 16V R32 Di 0603 LCD 100 1 18 b OV _ i LCD 18 0 3 amp diea
77. 335 0 5inch 10 CADOUT NC E18 ee DDR MEMDATA S7 012 CEU MDEE L0 CADOUT C20 205 c NeLK2 goon oos lt DOR CLRTH MEMCLK 5 41S Mbog L0 CADOUT NC Cei C21 4 DDR CLKI MEMCLK MEMDATA 59 517 GU Mber L0 CADOUT NC C22 cikos MEMCLK MEMDATA 60 BH Goo wiper L0 C23 MEMCLK MEMDATA 61 CPU L0 CADOUT NC C24 DDR CLKait DDR CLKSs MEMCLK MEMDATA 62 18 GEH L0 CADOUT H2 NC C3 4 DDR 1 5 DOR CLRGH pa MEMDATA 63 18 L0 CADOUT NC C6 DDR _CLK6 DDR CLK s LH CPU 0080 7 4 10 CADOUT H0 NC 4 DDR_CLK7 MEMCLK L7 NC Di2 MEMDOSIO NC 018 x28 MEMDOS 1 D20 SCANCLKi 6 CADOUT 0 151 L0 CADOUT 115 NC D20 08 MEMDQS 2 10 CADOUT NC 022 4 5 MEMDQS 3 10 CADOUT 03 MEMCS MEMDOS 4 L0 CADOUT 1 12 NC E13 4 CPU 0538 2 28 MEMCS MEMDQS 5 Lo_CADOUT_L 14 4 CPU 52 cpu Csia 28 1 MEMDOS S L0 CADOUT 1 10 F3 CPU 51 cpu Cso ee 111 MEMDOS 7 L0 CADOUT 4 CPU 50 MEMCS MEMDOS 8 CPU DQM 7 4 L0 CADOUT NC Ki DDR RASA ys MEMDOS 9
78. 5 0612 SMT RP 68 4 8P 1 16W 5 0612 SMT 7584 8P 1 16W 5 0612 SMT RP 10K 8 10P 1 32W 5 1206 SMT RP 2 2K 8 10P 1 16W 5 1206 SMT RP 4 7K 8 10P 1 32W 5 1206 SMT CAP IU 10 10V 0805 X7R SMT CAP 10U 6 3V 20 0805 5 5 CAP 10U 10V 80 20 0805 Y5 V SMT CAP 4 7U 10V 1096 0805 XSR SMT CAP 4 7U CR 10V 80 20 0805 CR 16V 20 80 0805 5 8399 N B Ma ocation S RP14 RP15 RP16 RP17 RP18 5 8 E RP10 RP11 RP12 RP52 RP6 RP7 E RP20 RP23 RP26 RP29 2 2 5 7 3 RP32 RP35 RP38 RP41 E gt gt 8 8 R z z f PC145 PC147 P C44 e e e E LA e o2 gt gt e c 2 e gt 2 D gt gt C122 C140 C202 C204 C243 C260 C342 C351 0421 C96 PCI35 PC23 P C33 intenance PC10 PC110 PC13 PC3 PC6 PC6 136 9 Spare Part List 5 Part Number 272072413402 272072683404 272073180401 272073223401 272073392401 272073472301 272075102402 272075102403 272075102501 272075102701 272075103401 272075103401 272075103403 272075103408 272075103702 272075103706 272075104701 272075181301 272075220301 272075222401 272075222701 272075223702 272075330401
79. 5 50 50 Z C397 1 CRT RED 1 1 112 1202100 1608 1 C398 C399 7 CRT RED at i 1 0402 402 z GAC GREEN CRT GREEN 1 1 2 22 0408 a M CRT BLUE 11 114 1202100 1608 1 3 boy 7 CRT BLUE x X 1 5 1319 CRT DDDA R420 1 33 0402 1608 1202100 1 115 6 7 CRT_DDDA FCU ino RAN CON 1608 1202 1008 1 uri ueo 9 2N7002 VSYNC CON 1808 1202100 1 Le T4 o 4 1608 1202100M 1 LiB 1 Blo 4M feof x oH 4 R421 1 5 2 7 CRT HSYNC RAN ora NGA 1206 1206 L100800 100M NA 4 SUYIN 5 74HCTIG125 160 75358 1562 05 9 35705 R13 CONN_SYN7535S_15GT x 10K 331720015071 4 1501 6002 100 0402 X 1 4 1 160 5 M exp 1 R12 1 CRT_IN 7 CRT VSYNC 4 R422 1 ALA 2 0603 77 GND CRT15 GND 15 GND CRT15 K GND_CRT15 AE 4 35705 1 0402 10 va 50V Title CRT DDCK R423 1 33 0404 77 Bie Document lev 7 CRT DDCK A GND CRT15 C Number Doc Roo Date 20 2004 Bheet 11 o 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com
80. 64 LPC_RST 3_g MINI_PCIRST 26 MINI PCI Slot 43V usc ps NB_PCIRST 08 V P 8 13 J 012 IDE PCIRST amp IDERST 2 5 3148021 gt _ Primary amp Secondary U3 19 TV_PCIRST convert to EIDE Connector TV Encoder 99 8399 N B Maintenance 1 No power definition Base on ACPI Spec We define the no power as while we press the power button the system can t leave S5 status or none the PG signal send out from power supply Judge condition gt Check whether there are any voltage feedback control to turn off the power gt Check whether CPU power will cause system can t leave S5 status If there are not any diagram match these condition we should stop analyzing the schematic in power supply sending out the PG signal If yes we should add the effected analysis into no power chapter 2 No display definition Base on the digital IC three basic working conditions working power reset Clock We define the no display as while system leave S5 status but can t get into SO status Judge condition gt Check which power will cause no display gt Check which reset signal will cause no display gt Check which Clock signal will cause no display Base on these three conditions to analyze the schematic and edit the no display chapter Keyword gt S5 Soft Off gt 50 Working For detail please refer 100 8399 N B Maintenance 8 2 No Power 1 When power button is press
81. AVDD1 ER 2 E 48 3 VDACVDD 9 o 9 124 012 012 15 012 12027100 12027100 12624 cae C30 do 0 010 0 010 gens T 00 ces T ode n 4 80 20 p o 80 20 80 20 Te 80 20 500207 10 80 20 80 20 pon Um Xp Bi pocument lev Xo Number lt Doc gt ROO Date EHM 20 2004 Bheet 6 o 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com NB VIA K8N 800 2 2 15 ER 25 U12B PERE ERE PE 2K KK PKK KKK DK DE 3K DE DK DK DK DK KK OKC KK KK KK KKK R156 121 9 NB_FPD10 110 th 10 VAD O 7 060600000090000000000000000000000 GDO DP3D10 j NB 12 E 999999999999999099990990999999999 B S DM NECEPDIT 9999999999999909999990999999999090 9 1 80 20 vapi SSSSSSSSSSSSoesssssssssssssssssss GD2 DP3CLK 520 VAD2 GD3 DP3D09 FPDOS 12 ABRNREE NB VAD3 GD4 DP3D0B FPDOB 12 VAD4 GD5 DP3D07 FPDO7 12 VADS GD6 DP3D06 12 VADG GD7 DP3D05 FPDOS 12 VAD GDB DP3DET nior GD9 DP3HS 10 veer GD10 DP3DO1 tone FPDO1 12 0909 GD11 DP2D11 FPD23 12 tov T GD12DP3D00 FPDOO 12 puse UPSTB GD13 DP2D10 FPD22 12 10 UPS
82. Control Muxed with AGP Signal Name Pin Signal Description ENAVDD GSTI AA Panel VDD Power ENAVEE Enable Panel VEE Power ENABLT GST2 ABI Panel Back Light Note I O pads for all pins on this page are powered by VCC15AGP 1 1 5V FPD23 FPDOD11 GD11 AEI3 O Flat Panel Data For 24 bit or dual 12 bit flat FPD22 FPDOD10 GD13 AD12 panel display modes FPD21 FPDOD09 GD14 AF12 Two FPD interface modes 24 bit and dual FPD20 FPDOD08 0015 AEI2 12 bit are supported FPD19 FPD0D07 GC BE2 ADII Strapping DVPOD4 is used to select the FPD18 FPDOD06 GD16 10 interface mode to LVDS transmitter chip FPD17 5 0017 10 Strap High 3C5 12 4 1 24 bit FPD16 4 GD18 AF10 Strap Low 3 5 12 4 0 Dual 12 bit FPD15 FPD0D03 GD23 AD8 In in24 bitl mode only one set of control pins FPD14 FPD0D02 GD20 AF9 is required However in dual 12 bit mode the FPD13 FPDODOI GD22 AE9 K8N800 Version CD provides two sets of FPD12 FPDOD00 GADSSTBI AE7 control signals that are required for certain 11 FPD1D11 18 LVDS transmitter chips FPD10 1 10 GDI AF18 In 24 bit mode two operating modes are FPD09 FPD1D09 GDO 17 supported FPD08 FPD1D08 GD3 ADI17 3C5 12 4 1 amp 3 5 88 2 0 amp 3x5 88 4
83. Description IRQ1 wil PU MultiFunction Pin Internal mouse controller enabled by Rx51 1 Rx51 2 1 Mouse Clock From internal mouse controller Rx51 2 0 Interrupt Request 1 Interrupt input 1 Signal Name I O Signal Description ACRST 13 AC97 Reset 97 Clock ACSYNC T2 AC97 Sync ACSDO U2 97 Serial Data Out ACSDINO U3 I 97 Serial Data In 0 VSUS33 f ACSDINI V2 I 97 Serial Data In 1 VSUS33 f ACSDIN2 Ul I AC97 Serial Data In 2 RxE4 6 0 E5 1 0 PMIO Rx4C 20 1 GPIO20 PCSO ACSDIN3 97 Serial Data In 3 RxE4 6 0 E5 2 0 Rx4C 21 1 GPIO21 PCS1 SLPBTN Resets Clocks and Power Status MSDT IRQI2 2 KA20G IO I PU MultiFunction Pin Internal mouse controller enabled Rx51 1 Rx51 2 1 Mouse Data From internal mouse controller Rx51 2 0 Interrupt Request 12 Interrupt input 12 MultiFunction Pin Internal keyboard controller enabled by Rx51 0 Rx51 0 1 Keyboard Clock From internal keyboard controller Rx51 0 0 Gate A20 Input from external keyboard controller KBDT KBRC KBCS strap AF10 MultiFunction Pin Internal keyboard controller enabled by Rx51 0 5 0 1 Keyboard Data From internal keyboard controller Rx51 0 0 Keyboard Reset From external keyboard controller for C
84. MB frame buffers using system memory Internal AGP 8x equivalent performance Separate 128 bit data paths between north bridge and graphics core for pixel data flow and texture command access Graphics engine clock up to 200MHz decoupled form memory clock High quality DVD video playback Internal hardware VGA controller with true color high color sprite for hardware cursor implementation 128 bit 2D graphics engine 128 bit 3D graphics engine Floating point triangle setup engine Microsoft DirectX texture compression 4 5M triangles second setup engine 400M texels second bilinear fill rate 8399 N B Maintenance Extensive Display Support 4 CRT display interface with 24 bit true color RAMDAC up to 300MHz pixel rate with gamma correction capability DFP flat panel interface supporting single channel or dual channel LVDS encoders DVI Flat Panel Monitor 12 bit DVI 1 0 compatible interface designed for use with external TMDS encoder AGP 8x functions muxed on DFP DVI pins for optional external graphics controller upgrade module Dedicated 12 bit interface to TV Encoder for NTSC or PAL TV display may be optionally configured as 12 bit DVI 1 0 interface to external TMDS encoder for driving a Flat Panel Monitor DuoView Dual Image Capability e 4 4 Direct Win98 WinME and WinXP multi monitor extended desktop support Independent resolution and color depth for secondary desktop Improved display flexibi
85. MEMADD B2 CPU MDi9 5 4 MD19 MD19 71 MEMADD A1 MEMADD 0 MEMADD B1 MEMADD BO CPU MDi8 1 amp i RPZ7 MDi8 MDi8 16 1 RPS CPU MD22 31 108 MD22 MD22 1 68 8 MEMADD DDR BAAT MEMADD BABT CPU DOM 14 3 8 DQMZ DOM 14 RPXE DDR BAAO DDR RASAT DDR BABO DDR RASBE CPU MD2i 13 4 MD21 MD21 13 n 2 5 3 DDR 42 58 DDR DDR WEAF DDR CASA DDR WEB DDR 52217 CPU 0052 1 0052 0682 71 DDR _CSO DDR CSi DDR 52 DDR 53 B CPU MDI 1 G 017 MDI 11 6 MEMADD B13 CPU 016 10 MD16 MDi6 10 CPU MD20 9 MD20 MD20 0273 1 Ci24 1 032 0402 10 0402 10 MD33 MD37 MD33 MD37 CPU 4g 1 BP2B MDii MDi 18 1 BP34 C330 1 Oi Cies 1 01 CPU 015 71 408 __ 15 010 1 688 0402 10 0402 10 54 DOME 0051 Dawa CPU MD10 14 RPXE MD10 MD15 314 RPXE C196 1 195 1 01 034 MD38 034 038 CPU MD14 13 4 014 MD14 313 n 0402 10 0402 10 2 CPU DOMi 1 DOMI DOMI 1 5 C197 1 ciss 1 01 MSS 74035 14035 7039 CPU MDI3 41 6 MD13 013 11 amp 0402 10 0402 10 MD4O MD44 040 044 b cru CPU DOS 10 0081 DOSI 10 C166 1 cios 1 01 CPU 012 MD12 MDi2 9 0402 10 0402 10 1047 14045 45 CPU MD9 1 AP29 MD9 MD9 4 5 RP3S 168 1 01 0055 DOMS 0055 DOMS 104 MDB 3 amp 68 4 0402 10 CPU MD3 amp 120
86. Major Components 5 1 AMD Mobile Athlon 64 ClawHammer 1 DDR SDRAM Memory Interface Pins DDR SDRAM Memory Interface Pins Continued Signal Name Type Description H L 7 O IOD Differential DDR SDRAM clock to the top of DIMM 0 for unbuffered DIMMs 1 H L 6 O IOD Differential DDR SDRAM clock to the top of DIMM 1 for unbuffered DIMMs 1 MEMCLK H L 5 O IOD Differential DDR SDRAM clock to the bottom of DIMM 0 for unbuffered DIMMs 1 MEMCLK H L 4 O IOD Differential DDR SDRAM clock to the bottom of DIMM 1 for 131 H L 2 unbuffered DIMMs 1 Differential DDR SDRAM clock to DIMM 3 for registered DIMMs 1 Differential DDRS DRAM clock to DIMM 2 for registered DIMMs 1 MEMCIK Differential DDR SDRAM clock to the middle of DIMM 1 for unbuffered DIMMs or DIMM 1 for registered DIMMs 1 101 Differential DDR SDRAM clock to the middle of DIMM 0 for unbuffered DIMMs or DIMM 0 for registered DIMMs 1 MEMCKEA MEMCKEB Clock Enables to DIMMs Used to gate clocks for power management functionality 1 MEMDQS 17 0 DRAM Data Strobes synchronous with MEMDATA and MEMCHECK during DRAM read and writes 1 Signal Name Type Description MEMBANKA 1 0 O IOS DRAM Bank Address Two copies are provided to MEMBANKB 1 0 accommodate the loading of unbuffered DIMMs During precharges
87. N B Maintenance 8 13 Modem Test Error 1 An error occurs when run the modem Modem Test Error 1 if the driver is installed properly 2 Check if the notebook connect with the Board level Troubleshooting phone LAN properly Check following parts and signals Yes 4 5V No 3VS 3V Replace MONO_OUT Replace a known good modem Motherboard AC97_SDOUT AC97_RST AC97 SYNC MDC SDIN 97 BITCLK 1 Re test Yes Correct it OK RING 1 RING 125 8399 N B Maintenance 8 13 Modem Test Error 2 An error occurs when run the modem 43V 21 R342 47K 16 23 AC97_SDOUT R305 22 5V 10 18 25 AC97_RST R300 22 PN 1 9 43VS 17 J15 22 AC97 SYNC R304 22 1 020 C353 C167 T 1U 2124 RIALA 22 MDC SDIN South Bridge V 3 26 R36 A A 22 7 8235 jos 30 R334 22 AC97 BITCLK ah 18 E 5 2 37 1 e U10 C187 1U MONO_OUT 5 Audio Codec TIP Lig 1 C3 400UH 1035 3 251 3 VY Ye 2 m TIP 1 Al 1000 mI TIP 2 MIS 5 R5 0 RING RING A3 P16 Ww RING 1 a4 J5 CA 1 1105 GNDI C666 2 15506 RJA5 8P 3 2 pos 1000P R867 0 RING 1 126 8399 N B Maintenance 8 14 Mini PCI Test Error 1 An error message is
88. Name GPI26 GPO26 SMBDT2 VSUS33 Pin Signal Description General Purpose Input 26 Rx95 2 1 95 3 0 27 GPO27 SMBCK2 VSUS33 General Purpose Input 27 Rx95 2 1 95 3 0 128 28 General Purpose Input 28 5 3 1 4C 28 1 GPD9 GPO29 VRDSLP General Purpose Input 29 RxE5 3 1 PMIO 4C 29 1 GPIO 2 1 General Purpose Input 0 Status PMIO Rx20 0 VSUS33 AC2 I General Purpose Input 1 Status on PMIO Rx20 1 GPD EXTSMIZ AAI I General Purpose Input 2 Status on PMIO Rx20 4 VSUS33 GPI3 RING Y2 I General Purpose Input 3 Status on PMIO Rx20 8 VSUS33 GPI4 LID 1 General Purpose Input 4 Status on PMIO Rx20 11 VSUS33 5 4 1 General Purpose Input 5 Status on PMIO Rx20 12 BATLOW VSUS33 GPI6 AGPBZ AD10 I General Purpose Input 6 Status on PMIO Rx20 5 GPI7 REQS R3 I General Purpose Input 7 RxE4 2 0 GPI12 12 D4 1 General Purpose Input 12 RxE4 4 0 5 1 0 INTE GPI13 4 General Purpose Input 13 RxE4 4 0 5 1 0 INTF 4 14 A3 General Purpose Input 14 RxE4 4 0 5B 1 0 INTG 5 15 General Purpose Input 15 RxE4 4 0 5 1 0 INTH 16 AEI I General Purpose Input 16 Status on PMIO Rx20 6 INTRUDER VBAT 17 1 Gen
89. Quality Support sampling rates up to 96KHz Independent 20 bit ADC and 20 bit DAC SNR Signal to Noise Ratio exceeds 95dB Built in resolution VSR converter Various Output Format 4 Support 8 channel outputs Hardware down mixed 6 channel to 2 channel or 4 channel Center and LFE channel swapping Alternative Line Level outputs at surround output 34 8399 N B Maintenance 96KHz S PDIF output Direct CD input to S PDIF output Added on Functions Integrates headphone amplifier with mute Dual microphones supporting Karaoke mixing Extension Control A 4 61 3D depth control Support EAPD control Supports GPIO pins control Selectable clock sources Driver support Magic 5 1 Convenient Design Flexible Jack detect design Built in accurate PLL for saving an external crystal Built in Smart 5 1 Power Low power consumption mode 35 8399 N B Maintenance 3 3V SV analog 3 3V digital power supply Package 48 LQFP Package 1 3 8 System Flash Memory BIOS 2M bit Flash memory Flashed by 5V only User can upgrade the system BIOS in the future just running flash program 1 3 9 Memory System 64MB 128MB 256MB 512MB x64 200 DDR SDRAM SODIMMs JEDEC standard 200 pin small outline dual in line memory module SODIMM Utilizes 333Mb s 400Mb s DDR SDRAM components 4 64 8 Meg x 64 H 128MB
90. a 14 DOM7 11 amp T 0402 10 T 0402 10 T MDB CPU MD57 1 MD57 MD57 10 c293 1 coss 1 _ 61 1 18 1 0402 10 0402 10 MDS MDS CPU 60 1 20 MD60 060 4 RP3S c294 1 Como 1 0951 DAST MD56 104 MD56 MD56 3 684 0402 10 0402 10 CPU MD55 8 amp 1206 MD55 055 1206 c295 1 coo 1 CPU MD5i 5 4 051 MD51 1 0402 10 0402 10 MDT MDT CPU 1 amp 1 21 50 MD50 16 1 RPS 0296 1 coos 1 CPU MD54 31 10 8 MD54 MD54 1 68 8 0402 10 0402 10 DDR CLKS DDR CPU DOSS 14 RPX8 DOSS 2985 14 6206 1 coo9 DDR_CLKSF DDR_CLKAF CPU DOMS 313 4 DOME DOM6 13 4 0402 10 0402 10 CPU MD53 31 053 53 1 cao 1 CPU 052 11 6 52 MD52 11 amp 0402 10 0402 10 CPU MD49 10 049 MD49 10 c287 1 c20 1 CPU MD48 2 MD48 MD48 0402 10 0402 10 CPU 047 46 1 RP22 MD47 MD47 18 1 RP40 CPU MD43 71 108 MD43 MD43 1 6878 MD46 14 RPX8 MD46 MD46 14 RPXE lt 7 CPU DOMS 313 4 DOMS DOMS 43 4 2 CPU MD42 31 MD42 1 5 PU DOSS 11 amp 0085 0985 11 amp 2 CPU 0085 CPU MD4S 10 MD45 045 10 CPU MD44 a 044 MD44 9 1 25VTT 2 5VS_DDR1 25VTT 2 5VS_DDR CPU MD41 g 1 BP23 MD4i 4 5 APAT
91. i 11 Nt TVHS DPOHS STH DP1D04 ENPATIA ENAVDD 12 11 TWS TWSIDVPOVSINC 48 m N R60 0402 AGPPCOMP 11 lt TVCLKIDPOCLK AGPPCOMP A wi AGPNCOMP FPD4 R108 1 2 0402 me o Agna VREF FPDS R109 1 AJK A 2 0402 GPOUT AGPVREF 1 FPD6 R86 7 0406 DISPDCLKO AGP 8 1 DISPDCLRT DCLKO AGPexpr X2 5GP 9XDER lt Jap 10 FPD8 R4i4 1 47 0402 EERE RAMS 1 AK 204 GDBIH GPIPE lt g FPD7 Bii0 1 AJK A 2 0402 R111 1 AJK A 2 0402 451 110 26 X GND q R434 10K 0402 5 5 ENPBLT 1 1 DENPBLT 12 DTC114TKA 480 209 B 1 RNA 2 0402 50 lt 7 22 0402 5 Ut DISPDCLKO Em vos SPMRA 2 o SP_SRO SP SRT MRA sro 2 Soo st MODOUT vss SSON 508 Title Document lev Number Doc Date Bheet 7 o 26 20 2004 T PDF created with FinePrint pdfFactory trial version http www fineprint com SB VIA VT8235CD 1 3
92. i aH CADIT 815 PCI DEVSEL DE PRAMER DEVSEL cpar 121 GBERRE ja H2 VST 8 15 FRAMES FRAME 125 GSERRE ijs IER CADIS 815 PCI_IRDY IRDY GERE 122 10410 PE CADIS 845 TRDY CREQy 22 H s 45 48 CADIE 815 STOP 106 14 142 as H4 F2 MS 8 5 PCI PAR PAR cunts 188 O 14 148 PIE 845 PCI PERR caLocks 4VCCA AFPA 12 114 48 STOPS 815 POL SERRE SERR CCLKRUN 198 EUNE 15 o 49 8 PCI REG 19 ES R394 1 30K A 2 0402 18 16 CDEVSEL 8 PCI GNTOR GNT panne 43 _ Ree 17 51 205 Re Dia ET 813 15 CARD_PCIRST GARD POSTE RST R2 014 12 52 HE CTRDYE 19 53 3 E 4ok 915 CARD lt GARD Puer 89 RI cvs Hal eS cae 20 54 He 0402 Cvs 75 CD T C365 2 55 CADIS 18 8 lt gt 2 spxr_ouT 25 Ee 2020 2 22 56 CCD2 23 57 Ej 9 15 CLKRUN SLKRUNY 434 042 4 124 8396 1 10K PCI LOCK MES 41 CAD23 amp 25 5979 0402 SERIRG 25 VCCA CAD24 2 0 CCBERS 4222 101519 lt gt
93. loading of unbuffered DIMMs 1 MEMCASA L O IOS DRAM Column Address Select MEMCASA and MEMCASB L are functionally identical Two copies provided to accommodate the loading of unbuffered DIMMs 1 MEMWEA L O IOS DRAM Write Enable MEMWEA L and MEMWEB are MEMWEB L functionally identical Two copies are provided to accommodate the loading of unbuffered DIMMs 1 MEMADDA 13 0 O IOS DRAM Column Row Address Two copies are provided to accommodate the loading of unbuffered DIMMs During precharges activates reads and writes the two copies are inverted from each other except A 10 which is used for auto precharge to minimize switching noise The signals are inverted only when the bus is used to carry address information 1 Note 1 These pins are used in an alternating fashion to compensate R TT by internal comparison to 3 4 VLDT and 1 4 VLDTand compensate R ON by comparison to each other around 1 2 VLDT For proper resistor value see theAMD Athlon 64 Processor Motherboard Design Guide order 24665 2 The unused LO CTLIN H L 1 pins must be properly terminated such that the true pin is pulled High and thecomplement is pulled Low Refer to the AMD Athlon 64 Processor Motherboard Design Guide order 24665 for details 71 8399 N B Maintenance 5 1 AMD Mobile Athlon 64 ClawHammer Processor 2 Miscellaneous Pin Descriptions Signal Name Type Description RE
94. module power status User could use 1 to enable or disable RF 1 4 4 2 Five LED Indicators above Front Side Housing From left to right that indicates CD HDD NUM LOCK CAPS LOCK and SCROLL LOCK 1 4 5 Fan Power on off Management FAN is controlled by Embedded Controller Winbond W83L950D Thermal with hardware monitor to sense CPU temperature and EC control fan on off 1 4 6 CMOS Battery CR20323V 220mAh lithium battery When AC in or system main battery inside CMOS battery will consume no power or main battery not exists CMOS battery life is at lest 10 years Battery was put in battery holder can be replaced 43 8399 N B Maintenance 1 4 7 Port One 3 pins AC power socket One CRT monitor One S Video TV out PAL NTSC Six USB 2 0 ports for all USB devices One MODEM RJ 11 phone jack for PSTN line One RJ 45 for LAN Headphone out Jack Microphone Input Jack One Cardbus Sockets for one type II PC card extension 44 8399 N B Maintenance 2 System View and Disassembly 2 1 System View 2 1 1 Front View 2 1 2 Left side View Lock O Ventilation Openings 45 2 1 3 Right side View eoo occoococe CD DVD driver Line out jack MIC in jack USB port 2 RJ 45 connector RJ 11 connector AC Power Indicator Battery Power Indicator Battery Charge Indicator PC Card slot 2 1 4 Rear View S Video output Ventilation Op
95. or Touch Pad SW503 T_CLK Sw504 XIN XOUT 112 8399 N B Maintenance 8 7 Keyboard Touch Pad Test Error 2 VREF KBC_VDDA 72 C303 0 1U 71 304 0 10 Error message of keyboard touch pad failure is shown or any key does not work 43V 51 47K From U20 South Bridge KI0 KI7 17 24 KO0 KO15 1 16 10530 26 SW502 KBD_CS0 To 1501 Keyboard Connector V VDD3 10531 SW505 R429 9 9 45V 0 NN EXTSMI KBC_EXTSMI 5 E 017 DTCIAATKA WAKE UP amp KBC WAKE UP amp 37 Q27 DTCI44TKA T_DATA T_CLK XIN R262 22 CLK_KBC 70 L67 207 100 XOUT L69 120Z 100M L C341 010 SW504 SW LEFT mm 8MHZ 22P 7 L C328 22 SW RIGHT SW503 0 113 8399 N B Maintenance 8 8 USB Port Test Error 1 An error occurs when a USB I O device is installed USB Test Error Check if the USB device 15 installed properly Including charge board Yes Replace another known good USB device Re test Yes Replace the OK faulty part U20 J3 14 19 2 4 Board level Trouble shooting Signals Replace Check following parts and signals Mother board Parts 5VS CA iG
96. pin USB 2 0 Differential Output Power 3 3V 5 Power list for USB differential outputs USBP0 POG 1 PIG P2 P2E P3 P4 5 P5CE Connect to VSUS33 through a ferrite bead USBGND see pin USB 2 0 Differential Output Ground Connect to GND list through a ferrite bead VCCUPLL A23 P USB 2 0 PLL Analog Voltage 2 5V 5 Connect to B23 VCC through a ferrite bead GNDUPLL C23 P USB 2 0 PLL Analog Ground Connect to GND through a 023 ferrite bead PLLVCC T22 P PLL Analog Power 2 5V 5 Connect to through a ferrite bead PLLGND U22 P PLL Analog Ground Connect to GND through a ferrite bead Note Internal Pullups are present on pins KBCK KBDT MSCK MSDT SERIRQ LAD 3 0 Internal Pulldowns are present on all LAN pins 89 8399 N B Maintenance 6 System Block Diagram J16 amp J17 im DIMM SLOT CLAWHAMMER J502 U26 Card Bus PCMCIA Socket Controller U12 CBI1410 North Bridge p K8N800 U3 vw TV Mini PCI PEAR Card Socket V link Internal MIC MIC Jack Amplifier PCIBUS G1428 02 LAN PHY U20 AC Link iia Internal Speaker VT6103L U13 South Bridge HP Jack anti Lj 8235 gt RJ11 LPC BUS CD ROM Sg ISA BUS Internal KB USB2 0 x6 U16 KBC Touch Pad WS3L950D FAN m 8399 N B Maintenance 7 Maintenance Diagnostics 7 1 Introduction Each time the computer is turned o
97. resume event Connect to a 10K ohm pullup to VSUS33 if not used 5 3 VIA 8235 South Bridge 5 8399 N B Maintenance UltraDMA 133 100 66 33 Enhanced IDE Interface PDIOW PSTOP Y25 Signal Name Pin I O Signal Description PDRDY Y22 I EIDE Mode Primary Channel Ready Device ready PDDMARDY indicator UItraDMA Mode Primary Device DMA Ready PDSTROBE Output flow control The device mayassert DDMARDY to pause output transfers Primary Device Strobe Input data strobe both edges The device may stop DSTROBE to pause input data transfers SDRDY EIDE Mode Secondary I O Channel Ready Device ready SDDMARDY indicator UltraDMA Mode Secondary Device DMA Ready SDSTROBE Output flow control The devicemay assert DDMARDY to pause output transfers Secondary Device Strobe Input data strobe both edges The device may stop DSTROBE to pause input data transfers PDIOR W26 EIDE Mode Primary Device I O Read Device read strobe PHDMARDY UltraDMA Mode Primary Host DMA Ready Primary channel PHSTROBE input flow control Thehost may assert HD MARDY to pause input transfers Primary Host Strobe Output data strobe both edges The host may stop HSTROBE to pause output data transfers SDIOR AF23 O Mode Secondary Device I O Read Device read strobe SHDMARDY UltraDMA Mode Secondary Host DMA Ready Input flow SHSTROBE control The host mayassert HDMARDY to pause input transfer
98. ute 2 5V ERR 4 GOD 1 1 9 508 9 For Lan 508 9 4422 9 4 4 4 26 508 LP2951 02BM NA C420 sores 421 C425 a H 508 22UNA 470 TU T T 1 7 1 1 s 1 0805 0805 0603 2 480 2094 80 20 A 7 i CN 1 Ew 1 1 cx C387 C388 C359 C337 C336 C344 C335 1U 010 100 10 220 346 Lx P 0 10 100 GND 7 7 0402 4 0402 0805 0402 4 0603 0603 63V OR GND GND GND E 8406 1802096 10V lt 48020 8294 50V 0805 480 20 GND 10 0 10 1 10 1 1 452 PWR VDDIN T GND 1 R298 100K 100K GND 0402 R408 0402 R296 5 1K 5 1K 0402 0402 100K 5 5 0603 as 4 a28 E 2N7002 2N7002 2N7002 5 gt 5 s 5088 19 4 ZL caso 4 4 010 0402 80 20 80 20 T t aNd WZ WZ E usD avs av P 25 5 DDR 25y P 9 R134 0402 5 RESET 1 1 V OPEN SMT4 OPEN SMT4 TSSOP14 49527 Jo 1 1 OPEN SMT4 OPEN SMT4 SA Joga Jo 25 GND 4 1 OPEN SMT4 OPEN SMT4 DTC144TKA 288202240001 svs 7 1 25 75 ICPU_THERMTRIP 2 Jo 2 gt ALL_PWROK 25V 3 79 1 1 OPEN SMT4 OPEN SMT4 Jo Joji 25V 1 4 1 aav 9 OPEN SMT4 OPEN SMT4 4040 1 DTC144TKA R410 288202240001 10K 94922 suse C gt OPEN SMT4 008 ome mm dim gt SB 3 7 9
99. 0 222670820003 222671330003 222678500002 224670830002 225600000054 225600000061 225682900001 227615400003 227682900001 227682900002 242600000001 242600000088 242600000145 242600000145 242600000232 242600000378 242600000385 242600000433 Description CARTON NON BRAND 8640C PARTITION IN CARTON 8640C CARD BOARD TOP BTM PALLET 8640C CARD BOARD FRAME PALLET 8640C PARTITION PALLET 8640C PE 50 70 W SEAL COMMON PE BAG 70X100MM W SEAL COMMON PE BAG L560 W345 7521N BAG LCD BRACKET STINGRAY PE BUBBLE BAG BATTERY 280 170 MS PALLET 1250 1080 130 7521N TAPE INSULATING POLYESTER FILM TAPE ADHENSIVE DOUBLE FACE W20 U CONDUCTIVE 8599 PAD K B 8355 END CAP R 8599 END 1 3599 LABEL PAL 20 5MM COMMON LABEL BAR CODE 125 65 COMMON LABEL 10 10 BLANK COMMON LABEL 10 10 BLANK COMMON LABEL 6 6MM GAL BLANK COMMON LABEL 27 7MM HI T EMP 260 C LABEL 27 10 LAN ID BAR CODE LABEL BLANK 1 5MM COMMON 8399 N B Ma ocation S intenance ABELOSGHETEMPCOMMON 242600000452 242600000452 242664800013 ABELCAUTIDNINVERTBDPITO ING 242668300028 LABELSPTNMPOLYESTERHIMHOPE 242669600005 LABEL LOT NUMBERRACE 242670800115 BEMEWORLD 242679900005 o 242684100001 LABLAGNCYGOBALESS 242684100002 LABELBATT 11IVAAHLIPANAB39 Res asw asiast
100. 0 5 Expansion VT8235 Keyboard Mouse Cards LPC Boot Rom PCI 487 BGA IDE Primary and Secondary On board m 97 Link n boar LPC I O SEN e Crystal 1 GPIO Power Control Reset MII Fast Ethernet Interface Figure 1 PC System Configuration Using the VT8233 20 8399 N B Maintenance Inter operable with VIA Host to V Link Host Controller Combine with VT8754 Apollo 4 333 for a complete 533 400 MHz FSB Pentium 4 system Combine with VT8377 Apollo KX400 for a complete 266 200 MHz FSB Athlon Socket A system be used interchangeably with the VT8235CDL Sout h Bridge in most board designs High Bandwidth 533 MB s 8 bit V Link Client Controller Supports 66 MHz V Link Client interface with peak bandwidth of 533 MB sec V Link operates in 2x 4x and 8x modes Full duplex commands with separate Strobe Command Request Data split transaction Configurable outstanding transaction queue for V Link Client accesses Auto Client Retry to eliminate V Link Host Client Retry cycles Intelligent V Link transaction protocol to eliminate data wait state throttle transfer latency all V Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow Highly efficient V Link arbitration with minimum overhead all V Link transactions have predictable cycle length with known Command Data duration Auto connect reconnec
101. 02 20 E zu TSA_SAT3 USB_OCH2 lt __ USB OCH 160204 M 098 4 283 2 1 2 4 2 r Tr GND 829 GND USB USB R26 C37 16 i 560K 560K 1000P ISA_SOE cast 0402 0402 0402 GND 1 1 ej 10 74HCTZA4D 5020 0402 50V 10 30V GND GND USBP2 1 603 USB 2 0 usBPa 8 USBP2 6 1 AA n 2 Ego 5 5 5 5 Bt 1 AL 4 ead Eje 121 B3 B4 d ISA_SAO ISA_SA12 90Z 100M B4 902 100 ISA SAI 21 9 ISA SA4 1 _5 1 2 SA_SA8 ISA MEMR R395 1 AJK A 2 0402 120 diii ISA SAZ 3 ISA SAS ISA SATA 3 1 ISA SAB USBP2 1 1 USBP3 ISA 4 4 1 _ ISA R392 1 7 0402 8 USBP2 X 603 GND2 OKA USBP3 8 1 amp ISA 5 7 51 ISA AKA GND3 T L 4768 1206 478 4PX2 RA TYCO 1470748 18505 e Sec soure 297040100027 Sec soure 297040100027 PrORESMIS Sec soure 331000008090 JB a 20680 es 19 gt lt F4 1101 18 49 4S gg Ao 1 1608 4 1 010 5511 4 mies mad R212 297040105010 TC010 PSS11CET C84 10K 0381 10K SW TCO10 PSHCETN 7 297040105010 GND 10 042 oy SRY 0402 SW 010 611 0402 1 0402 20 1 T MEC 2 8 USB_OCHA lt __ USB OCH 180204 4 e
102. 07 c 80 20 25 409 RESERVEDS 38 PCI PCI AD27 GROUND2 0130 15 PCI 025 41 p ps J 28 GND MINI LPC FRAME 43 44 PCI AD26 PCI 45 HESERVEDI DI26 024 9120 100 0402 8 14 PCL PLADA 4 Fo 0124 Lag 1 PCI AD21 PCI 21 1 2 GROUND10 9 4 PCI 22 PCL 19 2 Adi 54 PCI_AD20 PCI AD17 1 EH gt 8 14 PCI_C BE 2 9 pu ADHI 80 PCI ADi6 PCI_IRDY 61 2 16 62 SM t PRAMEN PCI 8 14 9 4 CLKRUN 85 Gi KAUN S ae PCI TRDY amp 8 14 8 14 POL SERRE m 87 SERRE 8 8 14 T 8 14 crounps 3 3V 6 DEVSELE 8 14 PCI 1 H PERRit DEVSEL PCI_DEVSEL 8 14 Fera 38 apis PCI AD13 PI PCI AD12 E Ad 80 1 1 AD 10 2 GROUND13 4 Per ADS PCI T GROUND ADIS PCI C BERO 7 ADIs Fag PCI C BERO 8 14 ADU 3 3VI7 PCI AD6 PCI ADS 91 3 313 AD S a PCI AD4 MINI LPC ADO ADIS AD A PCI_AD2 AD3 be P 96 Close te 55V 32 svo RESERVED 1 4 RESERVED WiP4 1 100 GROUNDS GROUND14 024 9 1618 AC97 SYNC AC CONN
103. 09 1 2 0603 0603 1210 1 11210 1210 11 2 18V li j 125V 125v 1 sv 1K 4 i 0603 UNA PR38 4 gt 1 0805 10 NA 10 085 AOB420 NA GND PR40 PUB 4 1 ET 6 4 1 PRI 0603 a 0 68UH NA 20 CPU CORE EN P NBALE T 0603 FM SPHASE T 1 5050 01 4 AOB416 NA 20 J 1 1 GND LGATE EN 0 Ll 2626 PC63 61 ISL6207 NA a4 F oUNA PRAT 508 VCC CORE 0603 0805 03 9 50V Ds 16V 1 NA GND E d z PC64 PC60 PC35 PR35 5 22000 1 220U NA_1 2200 1 i GND De 0 T 2 2 PR20 VID4 sot 22 423 3KINA 2 PRe3 0603 03 E 0603 Seanad PR24 P vib2 NA gt 0603 PR26 gt 6g 001 paer 1 PL PL4 PLG change to 27300090127 2 ADD PR44 PR42 PR43 PR45 N A 3 PR30 PR33 PR35 change from 2K to for one low sde mos O C P WM 5 ADD input cap PC76 PC69 PC30 PC55 PC49 PC24 PC51 PO43 lt 6 ADD output cap PC64 PC60 PC35 LA 7 PC24 PC30 PC43 PC49 PC51 PC55 change from 272023106701 to 272023106502 Document 1 69 76 60 Number Doc Date EHN 20 2004 Bheet 25 of 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com
104. 1 22 Jos ina X AC97 SDOUT 916 MDC SDIN BITCIK 22 105 IN SDATA OUT JAC97_SDOUT 9 16 18 uS MNPOLSEKRR x1 AG CODEC AC OAC RESETA Th RSTi 9 16 18 18 MINIPCI_SPKR lt MOD_AUDIO_MON RESERVED 10K 4 3223 AUDIO GROUND15 114 0402 15 sys AUDIO OUT SYS AUDIO IN 28 5 gt sys AUDIO OUT GND SYS AUDIO IN GND 8x Mini Lec 4 AUDIO AUDIO 120 314 MPCIACT 12 RESERVEDS MPCIACT 124 gt weciact 9 7 VCCSVA 3 3VAUXIT 15502 0 GND2 0402 80 20 24 08 92 SHORT SMT4 16 TYCO J GND 1566678 1 PIN24 124 ARE AUX POWER 480 2094 wa WZ 16 Sec soure 291000001206 GAD cidi LPC 48M R255 1 0 n2 0402 5 MINI LPC CLK 1049 LERAMER LERAMEW R472 1 0 2 0402 5 MINI _LPC_FRAME lt p R348 p 0402 5 MINI LPC ERG PCI R267 1 0 A 2 0402 5 MINI PCI SERIRQ LADO LADO R269 1 AQ A 2 0402 5 MINI LPC ADO il 1019 LADI 8476 1 2 0402 5 MINI LPC 1045 LAD2 R268 1 AQ A 2 0402 5 MINI LPC AD2 1049 tana 1403 R478 1 A A 2 0402 5 MINI LPC AD3 lt Title gt PS Document Number Doc Roo Date 20 2004 Bheet 15 o 26 5 3 z T PDF created with FinePrint pdfFactory trial version http www fineprint com
105. 1429 caso E pie 4029 CAD29 E 8255 40 GAD2B AD28 888 CAD28 m 8 i29 CAD MT SSE 027 CAD26 410 HAVE INTEGRATED ALL PULL UP RES ABOVE 5 28 25 AD25 CAD25 H AD24 122 ue AD23 124 AD22 oana 121 Gabe AD21 120 AD20 18 0 AD19 118 GAB18 018 5 GAB 017 CAD17 112 AD16 CAD16 m CADIS 015 GADI5 AD14 22 4NCC 013 Pon CDI a 11 399 1 0402 CADIO 1 0402 AD10 ADS CADO CADE mE 07 38 ADG 32 ABS 1 ADS Gaps 38 GAB 04 1 AD3 Cabs 2 Gaba Hi e ADI 29 AB E ADO e a m PCI C BE 3 1 8 5 PCI C BESE 1 35 50 815 PCI C BER Eae C BE2 22 HS 815 PCLCBERT CIBE1 Hie 343 87 HE CADI 8 5 PCI C BERO C BEOR aroye 10 214 39 CADE cU HA 5 39 07 ADRS Ra 2 085 CDEVSELS jos CETUR 58 90 5 PCI CARD BOL DEVSELE PCI CSTOP SS
106. 16 Meg x 64 H and HD 256MB 32 Meg x 64 HD 512MB 64 Meg x 64 HD VDD VDDQ 2 5V 0 2 36 8399 N B Maintenance VDDSPD 2 2V to 5 5 2 5V I O SSTL 2 compatible Commands entered on each positive CK edge DQS edge aligned with data for READs center aligned with data for WRITEs Internal pipelined double data rate DDR architecture two data accesses per clock cycle Bidirectional data strobe DQS transmitted received with data 1 e source synchronous data capture Differential clock inputs CK and CK can be multiple clocks CK0 CK072 CK 1 CK 17 etc Four internal device banks for concurrent operation Selectable burst lengths 2 4 or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15 6 u s MT4VDDT864H MT8VDDT1664HD 7 8125 MTAVDDT1664H MT8VDDT3264HD MT8VDDT6464HD maximum average periodic refresh interval Serial Presence Detect SPD with EEPROM Fast data transfer rates PC2700 PC2100 or PC1600 Selectable READ CAS latency for maximum compatibility Gold plated edge contacts 37 8399 N B Maintenance 1 3 10 LAN VT6103L 10Base T 100Base TX Ethernet PHY The VT6103L is a Physical Layer device for Ethernet IOBASE T and 100BASE TX using category 5 Unshielded Type 1 Shielded and Fiber Optic cables This VLSI device is designed for easy implementation of 10 100 Mb s Fast Ethernet LANs It interfaces to a MAC through an MII interface ensuring interoperability between products f
107. 19 vss 135 HZ 49679 B VES 185 187 woe VDD 120 1202100 Gu Place these capacitors near socket VDD 21 VDD 122 8 vss 23 VSS 139 VDD 22 VDD 123 8 58 24 vss 140 17 VDD 23 VDD 124 4 2 vss 25 VSS 141 VDD 24 VDD 125 VSS 26 VSS 142 VDD 25 VDD 126 A 3 3 VSS 27 VSS 143 C96 C80 00 27 VDD 128 47u T 1 5529 0805 0402 0603 1 0402 OTR VSS 30 VSS 146 VDD 29 VDD 130 4 S b tev 58 31 VSS 147 VDD 30 VDD 131 VSS 32 VSS 148 Z 31 VDD 132 1 vss 33 VSS 149 x v VDD 32 lt 7 38 34 186 150 VDD 33 VDDAt VSS 35 VSS 151 VoD VDDA2 VSS 36 VSS 152 5 55 37 58 153 36 VDDIO 0 2596 DDR 8 vss 38 VSS 154 nes 37 VDDIO 1 58 39 VSS 155 0402 eta VDD VDDIO 2 2 vss 40 VSS 156 5 14 as VDDIO 3 VSS 41 VSS 157 id vp 40 VDDIO 4 8 vss 42 VSS 158 PG 41 2509 P 28 VDDIO 5 MBVIDTA 8 vss 43 VSS 159 2 EN vout 4 vp 42 VDDIO 6 9 VSS 44 VSS 160 livin 22 VOD 43 VDDIO 7 VSS 45 VSS 161 20 2 5VDDA PG 4j 6 D ERE m E oe cu 16V 80310 7 H2 VSS_47 55 163 75 AMEBBO4AEEY 100P 1 00 46 VDDIO 10 H2 vss 48 VSS 164 Sore VOD 47 VDDIO 11 1 SORT VSS 49 VSS 165 S 0002 80 20 m 16V X7R 58 49 Nee 0603 10 VDD 49 VDDIO 13 IQ Hit vss 5 167 00 49 13 16V 60310379 H 8 167 00 50 C95 1 02
108. 2 OD GPO22 CPU Speed Select Connected to the CPU voltage regulator used to select high speed L or low speed H This pin performs the GHI function if Function 0 RxES 3 0 DPSLP P21 OD GPD3 GPO23 CPU Deep Sleep This pin performs the DPSLP function if Device 17 Function ORxES5 3 0 CPUMISS 1 7 AGPBZ GPI6 ADIO I CPU Missing Used to detect physical presence of the CPU chip in its socket High indicates no CPU present Connect to the CPUMISS pin of the CPU socket The state of this pin may be read in the SMBus 2 registers This pin may be used as CPUMISS and GPI17 at the same time AGP Busy Low indicates that an AGP master cycle is in progress CPU speed transitions will be postponed if this input is asserted low Connected to the AGP Bus AGPBZ pin PCI Bus Interface Signal Name Pin O Signal Description AD 31 0 see IO Address Data Bus Multiplexed address and data The address is driven with FRAM EZassertion and data is driven or received in following cycles CBE 3 0 IA Command Byte Enable The command is driven with assertion Byteenables corresponding to supplied requested data are driven on following clocks DEVSEL Device Select The VT8235 Version CE asserts this signal to claim PCI transactions through positive or subtractive decoding As an input DEVSELZ indicates the response to
109. 20 His 88 52 2 vpp 52 VDDIO 16 Ves VSS 170 M24 00 53 VDDIO 17 vss 55 85 171 OR ES VDD 56 VDDIO 20 in VLDT pour 4 H26 ves 58 VSS 174 VDD 57 VDDIO 21 am vss 59 VSS 175 v X VDD 58 VDDIO 22 8 1 vss 60 VSS 176 ND VDD 59 VDDIO 23 VSS 61 VSS 177 vob 60 VDDIO 24 5 21 vss 62 VSS 178 10 vob VDDIO 25 58 63 VSS 179 P20 00 62 VDDIO 26 vss 64 VSS 180 22 00 63 VDDIO 27 8 1 vss 65 VSS 181 P24 64 VDDIO 28 2 1 vss 66 86 182 8 0 65 VDDIO 29 VSS 67 VSS 183 VDD 66 VDDIO 30 41 68 VSS 184 c97 1 0220 K T 167 peostoso x7 Kz 195 69 ASSES VDD 69 VDDIO 33 5 1 yss vss 187 200 69 18V 7 58 71 55 187 0 VDD 71 VDDIO 35 0224 vss 73 Ves ep AE20 001 16V X7R Kis VSS 73 55 189 AE29 VOD 73 VDDIO 37 516 IQ Kiz VSS 78 4 74 VDDIO 38 16 Kaa yss 7e Z 00 75 VDDIO 39 1 vss 77 vss 193 AET8 PG 1 258 P 40077 400047 8 31 557 Vesias VDD 78 VDDIO 42 vss 80 VSS 196 BICH4TKA 9 VDD 79 VDDIO 43 D vss VSS 197 1000 15 ar NB within VSS VSS 199 euo VOD 82 VDDIO 46 1 inch 4 4 vss VSS 200 024 DAUNA 2 vpp VDDIO 47 2 vss 85 VSS 201 5902 0 Jat 84 VDDIO 48 2 vss 86 vss_202 AG27 SV oos w7 VDD 85 VDDIO 49 55 87 VS
110. 21 MEMADDB 12 MEMDATA 27 E L0 NC AE22 AEZS MEMADDB 13 MEMDATA 28 eR BPSOLKs 1 0102 10 CADIN H 14 NC AE28 MEMDATA 29 10 CADIN NG AE24 221 507 jaba bn 4 DDR BAAO MEMDATA S0 8114 1 AO je 0402 NC 7 4 DDR 1 MEMDATA 31 6 10 CADIN 15 LO CADIN NC AF18 AFAT 4 DDR BABO 15 MEMBANKB O MEMDATA 32 j CPU MD33 WZ LO CADIN NC AF21 AE21 ee 4 DDR MEMDATA 33 CPU MBS4 ara 10 2 AF22 AE22 MEMDATA 34 CEU Mas L0 CADIN NC AF23 2 508 4 DDR CASM lt D4 MEMCASA L MEMDATA 35 LO CADIN NC AF24 4 DDR_CASB MEMCASB L MEMDATA 36 PU MDIT 10 CADIN LIS NC AG17 BP3 TP514 CPU MD38 L0 CADIN NC AG18 EFS MEMDATA 38 FAm ES 10 CADIN NC AG2 gt t MEMDATA 39 CPU MD4O LO CADIN 8 NC AGA MEMCHECK 2 MEMDATA 40 LO CADIN NC AG6 8 MEMDATA 41 53 GBU LO CADIN 0 NC AG7 AGZx 1 MEMCHECK 4 MEMDATA 42 3 CU Mp4 4 10 CADN NC 4695 Tps O11 Ua MEMDATA sa 84 tk 10 1112 NC
111. 272075470401 272075471401 Description CAP 047U 1 6V 10 0603 X7R SMT 068 16V 10 0603 X7R SMT CAP I8P CR25V 10 0603 NPO S CAP 022U CR 25V 10 0603 X7R S 2900 50 10 0603 78 5 4700 50 5 0603 X7R S CAP 1000P CR 50V 1096 0603 X7R IN 1000 50 10 0603 78 5 CAP 1000P CR 50V 20 0603 X7R S CAP 1000P 50V 20 0603 X7R S CAP 01U CR 50V 10 0603 X7R S CAP 01U CR 50V 10 0603 X7R S CAP 01U 50V 1096 0603 X7R SMT CAP 0 10 CR 50V 10 0603 X7R S CAP 01U 50V 80 20 0603 Y5 V S CAP 0 10 CR 50V 80 20 0603 Y 10 50V 80 2094 0603 Y5 V S CAP 180P 50V 5 0603 NPO SMT 22 50V 5 0603 00 5 CAP 2200P 50V 10 0603 78 5 CAP 2200P 50V 20 0603 X7R S 0 22U CR 50V 80 20 0603 CAP 33P CR 50V 10 0603 X7R S CAP 47P 50V 10 0603 COG SMT CAP 470P 50V 10 0603 X7R SMT 8399 N B Ma ocation S E 2 2 gt c d 25 3 al S Y d Q d 2 D CISA 105 109 75 92 PC1 PC123 PC127 PC132 PC139 PC21 PC36 P C84 C11 C13 C3 C8 PC90 C15 C16 C35 C37 C39 ro E an ro e t3 qe ww gt d d e 9 C28 C30 C31 C32 C33 C34 o2 j S eo gt
112. 27T0 15 7068 Le 342503200003 TACT PLATE W4L18T0 15 7521 GR 342503400005 PLATE W5L24T0 13 7170LI Lf 342503400005 co TACT PLATE W5L24T0 13 7170LI 342673100024 TACT PLATE WSL62T0 13 1 3T 8 342682900010 CONTACT PLATE WSL28T0 15MM BATTE sese SY RC E p _ 7 po NENNEN ss Oo MMY U 141 9 Spare Part List 10 Part Number 346503100001 346503100005 346503200202 346503400503 346673420003 346677300001 346678600005 346682900007 346682900009 346682900010 346682900013 346682900014 346684100002 346684100003 346684100004 346684400002 347104030012 347104030030 347104045125 347105020090 347105060030 347105060060 347108010012 347108080090 347108150024 Description INSULATOR BATT ASSY THERMAL FUSE INSULATOR 5 BAT TERY ASSY 7521Li INSULATOR BATT ASSY ONE ROUND BL INSULATOR BATT ASSY W7L13 8175 MYLAR 15 10 0 8 8640P INSULATOR FIBER UL94V 0 D 17 5mm INSULATOR FIBER UL94V 0 64X15 T NYLON BATTERY PULL 8599 AL FOIL T P BRACKET 8599 AL FOIL T P SWITCH MB 8599 SPONGE M B 8599 INSULATOR AL FOIL INVERTER 8599 INSULAT OR CARD BUS 8399 INSULAT OR SOUTH BRIDGE 8399 TUBE M B FOR ANT ENNA 8399 INSULAT OR RIBRE 63 15 0 25MM BAT 5 1 04 030 012 5 1 04 030 030 5 1 04 045 125 5 1 05 020 090 5 1 05 060 030
113. 33 standards to allow reliable data transfer at rates up to 133 MB sec The IDE controller is SFF 80381 v1 0 and Microsoft Windows family compliant Universal Serial Bus controller that is USB v2 0 1 1 and Universal HCI v2 0 1 1 compliant The VT8235CD includes three root hubs with six function ports with integrated physical layer transceivers The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in a non USB aware operating system environment Keyboard controller with PS2 mouse support Real Time Clock with 256 byte extended CMOS In addition to the standard ISA RTC functionality the integrated RTC also includes the date alarm century field and other enhancements for compatibility with the ACPI standard Notebook class power management functionality compliant with ACPI and legacy APM requirements Multiple sleep states power on suspend suspend to DRAM and suspend to Disk are supported with hardware automatic wake up Additional functionality includes event monitoring CPU clock throttling and stop Intel processor protocol PCI bus clock stop control modular power clock and leakage control hardware based and software based event handling general purpose I O chip select and external SMI Full System Management Bus SMBus interface 8399 N B
114. 399 MAX I LCD LTN150XB L03 15 XGA SAMSUN LT PF 15 XGA SAMSUNG 8399 MAX I WIRE ASSY BIOS BATT ERY 8355 WIRE ASSY LTN150XB L03 8599 WIRE ASSY LTN150XB L03 GREATLAND WIRE ASSY MDC MODEM 4 4PIN 8399 WIRE ASSY ANTENNA WHA YU 8399 ANTENNA OPTION 8399 IDI FFC ASSY TOUCH P AD T ENN RICH 859 FFC ASSY TOUCH P AD HONG FU 8599 FFC ASSY TOUCH P AD CEI 8599 CASE KIT Creaxtix 8399 MAX LCD ASSY 15 XGA SAMSUNG 8399 ID ASSY 11 1V 4 0Ah LL BL 424 ocation S 8399 N B Maintenance CONTACT PLATE ASSY W5L45T0 13 FU ASSY 11 1V 4 0Ah LI CASE CL BATT ASSY 11 1V 4 0Ah LI CORE PA CFM Medion ADPT ASSY 19V4 74 TOUCHPAD MODULE SYNAPTICSTM42PU HDD ME KIT 8599 LCD ME KIT 15 XGA SAMSUNG 8599 ROM ME KIT 8599 HDD DRIVE 40GB 2 5 C25N040AT MR Location S 143 8399 N B Maintenance 9 Spare Part List 12 Part Number Description ocation S 624200010140 LABEL 5 20 BLANK COMMON P N 526268411004 SCALE 0 200 340684100 340684100 INSULATOR KIT CPU 8399 COVER 55 R 8399 3237684100 DDR SODIMM MODULE j256MB PC3200 MICRON OPTION 3241807868 IC CPU AMD Athlon 64 3200 0PGA 62W 754 OPTION 377244010 STANDOFF 4 400 5 5 55 34467230 DUMMY 34710506 GASKET 1 05 060 040 34710506 GASKET 1 05 060 060 37010301 SPC SCREW M3L 4 KHD NIV NLK D5 3 10 8 3
115. 4068410 HAETSINK 8399 OPTION 42168410 WIRE ASSY MDC MODEM 4 2PIN 8399 41267230 ASSY FAX MODEM S6K MDCS6S I MANGUST 347110020025 1 10 020 025 370102611001 SPC SCREW M2 6L10 NIB NY 523468411008 DVD COMBO ASSY KME UJDA760 8399 OPTION 340684100003 SHIELDING ASSY BOTTOM 8399 340682900018 COVER 55 8599 371102610406 3406841 371102611 34068290 44168440 34710808 SCREWiM2 6L4 K HEAD NIB COVER ASSY CPU 8399 SCREW jM2 6L6 K HEAD NIB HOUSING ASSY BOTTOM 8599 BATT ASS Y 11 1V 4 0Ah LI BL 4240G0116 GASKET 1 08 080 090 OPTION 52346841 HDD ASSY 40G FUJITSU MHS2040AT 8399 OPTION 3406841 HEATSINK ASSY CPU K8 AVC 8399 OPTION 37710265 S STANDOFF jM2 6DPSH12 5L4 NIW NYLOK 41168410 PVAjPWA 8399 MITHER BD 4226829 FFC ASSY TOUCH PAD TENN RICH 8599 OPTION 3466829 AL FOIL T P BRACKET 8599 3406829 BRACKET ASSY TOUCH PAD 8599 4426809 TOUCHPAD MODULE SYNAPTICS TM42PUMI950 37110201 SCREW MeL 3 K HD D3 8 t 0 75 NIW 3406829 SPEAKER ASSY 28 4 3 2W FENG CHIUN 8999 OPTION 3406841 COVER ASSY TOP 8399 37010301 SPC SCREWjM3L6 NIB K HD 0 8 NYLOK 3446829
116. 4912 24mOHM 288204912001 T SMT TRA 291000000203 MA 2P 1 3 5MM R A SMT 2 291000000708 7 2 5 6 07 291000020222 MA 2P 1 1 25MM H4 2 ST S 120 291000020415 4 1 1 25 5 5 38 S2N S2N N HDR MA 2P 1 ON 291000013016 CONHDRMAISPPLIMMOM2SSTSM N HDR MA 2P 1 N HDR MA 4P 1 ON 291000143011 CON FPC FFC 15P 2 83MM BD BD ST 15 139 8399 N B Maintenance 9 Spare Part List 8 Part Number Description ocation S Part Number Description Location S 291000150606 CON FPC FFC 6P 0 5MM R A SMT 312278206161 EC 820U 2 5V 20 8X12 5 0S CO PC25 PC29 PC53 PC58 291000152614 CON FPC FFC 26P 1 MM H 2 0 R A SM 1501 314100250502 1 25 7 30 20 495 11 5 3 316684500001 PRANDQA 291000611255 MINIPCI SOCKET 124P 0 8MM H 9 2 291000616807 CON PCMCIA CARD 68P 929100000140 1502 291000617542 SOCKET AMD BGA PGA754 SKT 4 291000622010 DIMM SOCKET DDR 200P REVERSE 116 291000622011 DIMM SOCKET DDR 200P H 9 2mm SM n 323768410001 DDR SODIMM MODULE 256MB PC3200 7 E 4 ro m o3 nu X gt r3 c gt 324180786803 ICCPU AMD Athlon 64 3200 0PGA 331000000303 HOLDER PCMCIA 331000000071 A 291000810818 CON PHONE JACK 12P R A R
117. 5 5 18 IDE PIORDY PDRDY PDDMARDY PDSTROBE 18 IDE 51 PDCS1 13 IDE PDCS3 PDCS3 SUSAH GPO1 Era SUSA 5 SMBDATAL Dn DATAO 4 5 13 IDE PDAO SUSBH GPO2 SUSBH 19 20 22 ay 13 IDE PDAT SUSC SUSC 19 21 2N7002 13 IDE PDA2 SMBALRT GPI7 13 18014 AE24 SMBCKi PCOMPP 8315 1 262 0402 w22 SMaori SCOMPP R350 1 260 125 2 0402 PVREF SCOM R350 1 0402 1 GPH PCOMPP was ACSDIN2 302 1 ATK A 2 0402 4 PGOMPP 443 gt GPO0 18 ACSDIN2 R302 7 0402 13 17 IDE SDD O 15 IDE SDDO GPIO Soo Rem 1 AJ 0102 340 000 GPIOA GPI24 GPO24 GPIO25 TESTS R371 59 2 0402 SA1 SDD1 GPIOC GPI25 GPO25 GBo 1 92 0402 42 5002 GPIOD GPI30 GPO30 IN amp 11 dus w w SA3 SDD3 GPIOE GPI31 GPO31 MINIPCI 15 SA4 SDD4 45 5005 PCLKRUN CLKRUN 14 15 X 346 006 CPUSTP IGPOS CPOS SA7 SDD7 PCISTP GPOS TOK TOKINA SAB SDD8 0402 0402 49 5009 E 10 60010 MEMR ISA_MEMR 17 SA11 SDD11 MEMW TSA FOMCSF 1 _ 17 Puer 27731 PCI 14 15 SAT2 SDD12 ROMCSWIKBCS TSA SOEF ISA_ROMCS 17 SA13 SDD13 SOE ISA_SOE 17 DTC144TKAINA gt CARD_PME 14 15 SA14 SDD14 IORHGPIZ2 GPO22 3 15 50015 IOWit GPI23 GPO23 TESTE gt 14 15 13 IDE SDDREQ IORDY GP119 LcD 101 12 13 IDE_SDDACK SDDAC
118. 58 0085 oces 50229 ov 4 19 lt 4 GND R224 GND GND 8353 case 560K 560K 1000P 0402 0402 0402 w506 SWs05 1 1 10 8 HT lt HT 7 DTO16 PT11AB B 1 GND DOWN TC010 PSS11CET 5 7 USB 2 0 297040105010 USBP4 R404 1 gj 603 136 1 0603 USBPS GND SW_TCO10 PS11CET 8 USBP4 404 1 A 2 Qf h 2 0 USBP5 8 Bt 1 A 2 Ee m Sec soure 297030105003 Sec soure 297040100027 902 100M 90Z 100M USBP4 1 USBP5 8 6603 oND 0603 GND4 TYCO 1470748 EA 3 re SHOBLSMTA Sec soure 331000008090 gt GND USB GND Bize pocument lev Number lt Doo gt Roo Date EHM 20 2004 Bheet 17 04 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com
119. 6 1206 MD4z 042 1146 CPU MD7 5 4 MD7 MD7 1 MD43 MD47 MD43 MD47 MDS 16 1 AP30 MDS MD amp 1 amp 1 HP38 N MD2 1 108 MD2 MD2 31 68 8 DDR CLK7E DDR CLKGE COREE CPU DOMO 14 RPX8 DOMO DOMO 14 RPXE DDR CLK7 DDR CLKG 2 Cru 000 13 4 0050 pas 4 MDE MD5Z MD48 52 CPU MDS 11 6 MDS 05 11 6 049 4053 049 053 MD4 10 MDS MD4 10 5 CPU 9 MDO MDO 9 B 0058 DOME 0055 DAME MD50 54 50 54 1 25VTT 1 25VTT 1 28VTT 2596 DDR 2 5VS_DDR 9 MDST 55 MDST MDES DDR CKEA DDR _ R259 47 0402 56 4060 56 60 gt DDR CKEB R260 4 0402 C204 1 1 XIR DDR DDR BABO 0805 0 220 16V 0603 57 067 57 MDE R256 2 gt 2 DDR gt DDR C225 1 0220 cei X7R 0057 0057 DOM 82K PR DDR _CSo 2 DDR WEB 47478 0402 16V 0220 16v 0603 0603 0 5 2 DDR DDR WEAR 4 RPXE C260 1 am XIR 5 5 2 EON DDR CS1 DDR 5 0805 0220 167 0603 059 4063 59 C gt 2 DDR CASAF 6 C278 1 o22u 0248 1 XIR DDR_CS2 0 0402 16V 0220 167 0603 SMBDATA DDR SMEDATA DDR C gt MEMADD 13 9 C277 1 cei XIR SMBCLK DDR SMBCLK DDR DDR DDR 0908 0805 02207 167 0603 C gt DDR CS1
120. 6 and GDBIL for GD 15 0 needs to be inverted on the receiving end 1 on GDBIx indicates that the corresponding data bit group should be inverted Used to limit the number of simultaneously switching outputs to 8 for each 16 pin group Pipelined Request Not used by AGP 8x Asserted by the master external graphics controller to indicate that a full width request is to be enqueued by the target North Bridge The master enqueues one request each rising edge of GCLK while GPIPE is asserted When GPIPE is deasserted no new requests are enqueued across the AD bus Note See RxAE 1 for GPIPE GDBIH pin function selection GADSTBOF GA DSTBO for 4x GADSTBOS GA DSTBO for 4x 15 15 Bus Strobe 0 Source synchronous strobes for GD 15 0 the agent that is providing the data drives these signals GDSO provides timing for 2x data transfer mode GDSO and GDSO provide timing for 4x mode For 8x transfer mode GDSO is interpreted as GDSOF ilFirstl strobe and GDS0 as GDSOS iSSecondl strobe Signal Name Pin Signal Description GADSTBIF GA AE7 IO Bus Strobe 1 Source synchronous strobes for GD 31 16 1 DSTBI for 4x the agent that is providing the data drives these signals GDS1 GADSTBIS GA provides timing for 2x data transfer mode GDS1 and GDS1 DSTB1 for 4x provide timing for 4x transfer mode For 8x transfer mode GDS is interpreted as GDSIF iSFirstle strobe and
121. 7 27 OD SMBCK2 VSUS33f General Purpose Output 27 Rx95 2 1 95 3 1 87 5 3 VIA VT8235CD South Bridge 9 8399 N B Maintenance Power Management and Event Detection Continued Signal Name LID GPI4 INTRUDER 6 Pin 1 T O Signal Description Notebook Computer Display Lid Open Closed Monitor Used by the Power Management subsystem to monitor the opening and closing of the display lid of notebook computers Can be used to detect either low to high high to low transitions to generate 10K PU to VSUS33 if not used Intrusion Indicator The value of this bit may be read at PMIO Rx20 6 THRM GPI18 AOLGPI Y4 Thermal Alarm Monitor Rx8C 3 1 Rising or falling edges selectable by PMIORx2C 6 may be detected to set status at PMIO Rx20 10 Setting of this status bit may then be used to generate an SCI or SMI THRM may also be used to enable duty cycle control of stop clock STPCLK to automatically limit maximum temperature see Device 17 Function 0 Rx8C 7 4 RING GPI3 Y2 Ring Indicator May be connected to external modem circuitry to allow the system to be re activated by a received phone call 10K PU to VSUS33 if not used BATLOW GPI5 v4 Battery Low Indicator 10K PU to VSUS33 if not used 3 3V only CPUSTP GPO5 AC7 CPU Clock Stop RxE4 0 0 Signals the system clock gener
122. 8 6 3V 50V of 16 16V of GND 2 5V_P DVMAIN 253 PL12 ld i m 2012 1 SHORT SMT4 1202100 Ll pces P 00910 4 PJL2 040 4 PCe6 95 JP 189205 PCB7 220 22U NA E 20 0 10 4 4 Jl 50 F 100 NA 060 GND 10 78 PR49 1M VW 7 0603 45V P 9 1 10 0603 PDii 5514 SS DC2010 T 0603 4 50 bez 4 100 GND PR48 16V 22 1206 0603 PRA GND 0603 SUSCH 4 ZL D 0805 2 10 PUIt 4 A04422 1 14 EN PSV BST 4 2 H i sos 42 5 P 3 vour ux 2 HE 444 VDDP S ND7 26006 DL Fe P AGND PGND 1 ttt 1 561470 TSSOP14 82K 44 2 2UH 0603 D PUt0 IHLPSOSOCE 01 4 1 20 1 1 1 010 4 zx Pces 820U NA 0603 Gus 288204410010 EU av 1 50V 1206 5 16 2 doled 21 8200 AN PD10 SSA34 NA 002010 us 1 5 5 1 36407 1 ADD 77 1500 6 3 2 PL8 take off placement PR50 0603 PRS 1 lt Title gt Document Number Doc Roo I I I I Date 20 2004 Bheet 21 of 26 5 3 z T PDF created with FinePrint pdfFactory trial version http www fineprint com
123. 8H Update OUTPUT port 39H Setup Cache Controller 3AH Test If 18 2Hz Periodic Working 3BH test for RTC ticking 3CH initialize the hardware vectors 3DH Search and Init the Mouse 93 8399 N B Maintenance 7 3 Error Codes 2 Following is a list of error codes in sequent display on the debug board POST HEX DESCRIPTION Update NUMLOCK status 3FH special init of COMM and LPT ports 40H Configure the COMM and LPT ports 41H Initialize the floppies 42H Initialize the hard disk 43H Initialize option ROMs 44H OEM s init of power management 45H Update NUMLOCK status 46H Test For Coprocessor Installed 47H OEM functions before boot 48H Dispatch To Op Sys Boot 49H Jump Into Bootstrap Code 94 8399 N B Maintenance 8 Trouble Shooting 8 1 Base Work Condition 8 2 No Power 8 3 Battery Can not Be Charged 8 4 No Display 8 5 External Monitor No Display 8 7 Keyboard Touch Pad Test Error 8 6 Memory Test Error 8 8 USB Port Test Error 8 9 Hard Disk Driver Test Error 8 10 CD ROM Driver Test Error 8 11 Audio Failure 8 12 LAN Test Error 8 13 Modem Test Error 8 14 Mini PCI Test Error 8 15 CardBus amp Reader Test Error 8 16 TV Encoder Test Error 95 8399 N B Maintenance 8 1 Base Work Condition 1 4 System Voltage Check 4 Pa Pos Pao P20 PFI PLI PDS x F5 U19 Q12 z 015 016 PWR VD
124. 9909 mu 55555525505550550 22 9099 m E 88888888989888888 22 SB VEDSL vns SSSSSSSSSSSSSSSSS 2 2 Fag INTRUDER amp 8338 AJK A 2 0402 VD4 DPSLP IGPIO23 P28 x vos SB_A20M EU 3 SB FERRF o 8479 een Dos 107 SE_IGNNEF wsc 8309 1 002 SB 1 4 S8 INTR SB APICD R316 1 n 2 0402 5 gt LorsTop 26 822 vont NMI E VO suponer SB 1 AJK A 2 042 0402 vois Sus SB STPCLK SB APICCLK 8310 1 0 0402 322 pB28 SE STPCLKE AA 222 vpis 18 mE SB R308 1 2 0402 7 VBE VBEO MCOL LAN COL 16 SB AGPBZ R276 1 A 2 0402 R59 0402 5 LAN MTX 35 GND 5 APS 5 2 08 SN SERIRO 1 AJK A 2 0402 7 Kes UpCMD MTXD1 16 7 DNCMD 14 MTXD2 LAN MTXD2 16 7 UPSTB UPSTB MTXD3 LAN MTXD3 16 Lai YY 7 UPSTB Eq UPSTB SCAM an n 080 E 7 DNSTB DNSTB o 7 DNSTBR J caid gt LAN_MRXER 16 se A SB_VLREF C10 VLREF MRXDV LAN MRXDV 16 88 VooMpP LAN 16 SHE BETS 1 A 5 080 mas ___ 2
125. AD CPU FAN Control m gt gt DEAD P 24 says Signal HI Low DTCHATKANA FANO FANON FANOFF 12 8 57 R277 10K CORE 0402 R211 5 PWRETNE 6 KBC WAKE _UP WAKE UR CPUCORE 27i 1 2 0402 5 027 DTC144TKA 4 1 921 IL SB PWRBTNG 2N7002 m 022 0402 i Zh 4 1802096 FANO 0 DTC144TKA lt 7 1 25MM ST MA 2 0402 4 5 GND VDD3 ACES 80 20 85205 0200 5 soure 291000010209 hed a eae SOR et a E 0402 5 CPU FAN Control 9 scu lt m ON 3 5 SVS 26 1 025 C321 5 TOP 1 Signal Hi Low 999 DTC144TKA Sov 0 FAN OFF R123 R295 9 470K 10K 80 20 03403 0402 1 0402 1 16V 23 i T 5 i GND G 4 i E gi 5 SUSB a26 9 DTC144WK Ou ges susBi 9 2022 BAT DATA 274 1 QA A 2 0402 DATA 5 ba Mirac 2 i25MM STMA2 c E ACES DTC144TKA 85205 0200 0402 4 4 019 Tiie 480 20 2 7002 Title soure 291000010209 CIK 275 1 Rr 2 0402 5 Document ND Number lt Doc gt Date 20 2004 Ens 18 of 26 I T PDF created with FinePrint pdfFactory trial version http www fineprint
126. AMD Athlon 64 CLAWHAMMER Processor K8N800 North Bridge 8235 South Bridge H8 W83L950D System Explode View 8399 Hardware Specification AMD INC VIA INC VIA INC WINBOND LTD Technology Corp MiTAC Technology Corp MiTAC SERVICE MANUAL FOR 8399 Sponsoring Editor Jesse Jan Author Grass Ren Assistant Editor Ping Xie Publisher International Corp Address 1 R amp D Road 2 Hsinchu Science Based Industrial Hsinchu Taiwan R O C Tel 886 3 5779250 Fax 886 3 5781245 First Edition Aug 2004 E mail Willy Chen mic com tw Web http www mitac com http www mitacservice com
127. At power up VD7 reflects the state of a strap on Logical combination of the A20GATE input from internal or SDCS3 VD 6 4 reflect external keyboard controller the state of straps on pins SDA 2 0 and VD 3 0 reflect the and Port 92 bit 1 Fast_A20 state of straps on pins FERR U24 I Numerical Coprocessor Error This signal is tied to the Strap_VD3 0 The specific interpretation of these straps is north coprocessor error signal on the bridge chip design CPU Internally generates interrupt 13 if active Output voltage dependent swing is programmable tot VPAR F24 IO Parity If the VPAR function is implemented in a compatible 1 5V or 2 5V by Device 17 Function 0 Rx67 2 manner on the north IGNNE T24 OD Ignore Numeric Error This pin is connected to the CPU bridge this pin should be connected to the north bridge VPAR iPignore errorlr pin pin P4X333 INIT R26 OD Initialization The VT8235 Version CE asserts INIT if it P4X400 P4X800 KT400 If VPAR is not implemented in the detects a shut down special north bridge chip or cycle on the PCI bus or if a soft reset is initiated by the register is incompatible with the 8235CE 4x V Link north bridges INTR T25 CPU Interrupt INTR is driven by the VT8235 Version CE to connect this pin to an signal the CPU that an 8 2K pullup to 2 5V Pro266 Pro266T KT266 KT266A interrupt request is pending and needs service KT333 P4X266 PN266 NMI T26 Non Maskable Interrupt NMI is used to force a KN266
128. B options Machine Check Architecture Includes hardware scrubbing of major ECC protected arrays Power Management Multiple low power states System Management Mode SMM ACPI 2 0 compliant including support for processor performance states Electrical Interfaces HyperTransport Technology LVDS like differential unidirectional DDR SSTL 2 per JEDEC DDR specification Clock reset and test signals also use DDR like electrical specifications Packaging 754 lidded micro P gt 27 mm pin pitch 29x29 row pin array te 40mm x 40mm organic substrate 49 Organic C4 die attach 8399 N B Maintenance 1 3 2 K8N800 North Bridge The K8N800 chipset is a high performance cost effective and energy efficient solution for the implementation of mobile personal computer systems with 8 16 bit 800 600 400 200 MHz HyperTransport CPU host interface based on AMD Claw Hammer processors Defines Highly Integrated Solutions for Performance PC Desktop Designs High performance North Bridge with HyperTransport interface to AMD K8 CPU plus AGP 8x external bus to external Graphics Controller plus high speed V Link interface to South Bridge Combines with VIA VT8235CD V Link South Bridge for integrated LAN Audio ATA133 IDE and 6 USB 2 0 ports 587 Ball Grid Array package with 35 x 35 mm body size 1 27mm ball pitch 1 5V core 0 15 process
129. Bal 1 AA 2 0402 Title Document lev Number lt Doo gt Date Bheet 3 o 26 20 2004 T PDF created with FinePrint pdfFactory trial version http www fineprint com 5 3 I 3 I z I DIMM SLOT amp X7R 1 25VSREF MEM 2 5VS DDR 2 5 3 DDR 41 28VSREF MEM 1 25VTT 9 SO DIMM should coro 1 CPU MD 0 63 2 0402 10 10 63 1 25VTT c275 1 010 css 4 00 MDO 0402 10 0402 10 MDT MD1 CPU MD59 RPI9 MD59 MD59 16 1 BP37 1 0220 4 CPU 063 101078 MD63 1 68 8 0402 10 0402 10 5050 0055 MD62 amp 11 RPX8 MD62 MD62 14 RPXS c291 1 cosa 1 MD2 CPU_MD58 1 MD58 MD58 13 4 0402 10 0402 10 CPU DAST 4 18 0057 0057 71 C292 1 C285 P On DO CPU
130. CLKG 24 lt 7 AVDD48 PCICLK8 HTTCLK2 Hi fonts RO ue cd SB 10 242 66M 7 ase Gu R258 1 0402 a HANGE VALUE R810 18 AN R283 1 24 48MHZISEL24 48if 18 AUDIO 14M ee 0202 1 S aeMHziESa SDATA F8 DATAO 49 ON for ISC950403 10 14M SB APICCLK 0402 48 REFaFS2 49 OFF for RTM360803 REFI FSI 4 2 lt R234 0402 T pm 108 PD 10 14 SB OSC lt GNDO MODEAHTTCLKO RA D GCLK NB GND MODEB PCICLK7 HTTCLK1 AD gt REST 1 2 0402 15 PCICLK_F 23 i PCI SB 8 ET ENDS RESET BTL_PD GNDS Canis Ee x ics R250 2 osos GND7 R415 R252 1 OKNA 2 0402 ete 12027100M 1606 L Hf 24 ON for RTM360803 R811 108950405 ISC950403 360803 SSOP48 co46 71 T coat OFF for ISC950403 7 27 27 8239 1 2 0402 FS2 0402 0402 c 5 5 R231 1 2001 0402 51 WZ 7 WZ T AAA GND mess 1 2 0402 MODE FUNCTIONALITY TABLES ODEA MODEB Pin Pins Pinil AGP Clock Signal 0 O B3MHZ E VALUE 3 3 66 AGP 0255 1 1 8 9 ODE 0402 10 INPUT GCLK NB C249 1 22 5 12 0 1 NLY 2 6MHZ 0402 10 R145 R146 SB VOLK C252 1 22P 5 12 4 OPULT
131. CORE P PG VCC CORE P PGOOD vec 8 4 f 4 E H E SL Pos Pcegl 6 30 pcsa p 109 E MET PVDO 7 3K f PO34 0 18 T 1000P 10U 220 1210 P VIDI 00 0603 0603 0603 1210 T 25v 25V 1 1 P VID2 5 01 PME MP 16V 29V Ax 1 Pca2 88 Vibe 1 1 M NEP 2 1 2 sov 3 010 PR28 i 4 28 809 1 e 2 0603 19 id PC37 PR32 11 25 08 ISEN2 GND gt 42 CORE 1 111007 ISEN3 PR34 PUT 2 Bx 9 t ISEN4 24 Pla M ENBALE 1 4 S P4 2 1 4700P 399K EN 1 i 1 1 1 vec UGATE i 1 0603 0603 4 10 10 1 SEN iuf 0603 a 0 68UH E PWM PHASE t EE 4 4 8 45 Pos 4 IHLPSOSOCE 01 4 n IR AoBa6 Pas 20 E 25 29 46 2 ROND lt 4 4 LGATE 2 2 TTXB20U 78200 10002 anD o Hi 2 PC33 31 1516207 4 062010 25V 25 0603 0603 10 TU 508 4 E 16V 1096 0805 03 1 J GND 2 16V 1 1516559 21 28 PC42 PR36 107K 50128 4 4 GND 0603 0603 C 1 4 4 330P NA D VMAIN 0603 0603 1 1 Te 10 4 NC 4 PR37 v P 0603 2659 PCS7 Po2s _ Posi 0 1U NA T 1000P A 100 100 11
132. CRMA 2 DACA vss 9 1301 22 TV LUMA DACB 1202 100 DACC GND 1 paco GND 1 lt 7 EUH VDDA2 1 22 noo 0805 52 52 0402 0402 ot am 2 Not 80 20 0402 R57 1 AQ 0603 80 20 80 20 80 20 3 1622 x 50V 50V 18 BEAD_600Z 100M NA POFP64_0 5MM 06030 1 A NZ GND GND D10 09 08 7 A GND TV GND TV GND TV AVOSNA BAV99 NA S VIDEO TV VDDA1 P 1271 012 1 1 2 7167 cso 2 19 27H 1608 107 01U He 1 TV LUMA 050 0402 0402 I 27uH 1608 480 20 480 206 480 2095 Ss 1 CRMA 50 50 Li0 27uH 1608 7 1 TV oo 77 ene 4 a 4 cas cas c5 270P 270P d 7 270P 270P 270P 0402 0402 0402 SUYIN 0402 0402 0402 1094 910 10 PR 33007S 07T1 C 10 10 1096 50 50 50 7524 2 5V TV VDDA2 50V 50V 50 u 1206 1291 1 1 Lacey 1 1 1202 1 0 77 JP BEAD DFS NA cse GND TV GND 0805 0 010 050 0402 0402 RP2 80 20 80 20 80 20 1 a lt 7 50 50 Kb X GND 77 754 1206 dt 4 T 8 12 12 12 12 12 mils 2 5 VOD R68 R69 22 22 22 1 E B Q 191 pore 22K 22K 0402 0402 0402 Close to VGA Connector 120211000 0402 0402 DEPT 4 10 410 i 18 5
133. Clock for Panel Muxed on Bus Pins GIRDY SBPLDAT VO 112 Serial Bus Data for Panel Muxed on Bus Pins GC BE1 SBDDCCLK 112 Serial Bus Clock for CRT DDC on AGP Bus GREQ Pins SBDDCDAT AA3 VO 12 Serial Bus Data for CRT DDC AGP Bus GGNT Pins SPCLK 2 1 C2 P2 IO Serial Port SMB I 2 C Clocks Clocks for serial data transfer SPCLK1 is typically used for 12 C communications SPCLK2 is typically used for CRT Display DDC communications SPDAT 2 1 Cl Pl IO Serial Port SMB I 2 C Data Data signals for serial data transfer SPDATI is typically used for I 2 communications SPDAT2 is typically used for CRT Display DDC communications Dedicated Digital Video Port 0 DVP0 TMDS Interface Signal Name Signal Description DVP0D11 TVD11 1 O Digital Video Port 0 Data Default output drive is 8 mA 16 DVP0D10 TVD10 M3 mA may be selected via SR3D 6 1 DVPO0D9 TVD9 M2 DVPODS TVD8 Ll NOTE DVPOD 6 0 are also used for power up reset straps DVP0D7 TVD7 M4 for the embedded graphics controller Check the Strap Pin DVPO0D6 TVD6 L3 table for details DVPODS TVD5 12 DVP0D4 TVD4 K1 DVP0D3 TVD3 DVP0D2 TVD2 K3 DVPO0DI TVD1 K2 DVP0DO0 DVPOHS TVHS N4 Digital Video Port 0 Horizontal Sync Internally pulled down DVPOVS TVVS N3 O Digital Video Port 0 Vertica
134. D C AGND C AGND G7 G2 C232 VDD3 63 10 El 69 0402 Gio 85 80 20 45V C231 C230 Gi428 10 Hi iU C227 High Shutdown R216 0402 0402 SPKR ROUT 1 100K 80 20 of 16V R223 0402 10V 80 20 286101428001 47 5 AGND AGND 1000 R217 0402 16V 1K R222 SHUTDOWN CPWX6 6 0402 AGND AGND 1 HP SENSE 1 arg 1 EAPD OFF EAPD Shutdown DTC144TKA F204 0402 L cota 100K PR 77 Low HI AGND GND lt Title gt PS Document Number Doc Roo Date EHM 20 2004 Bheet 18 o 26 5 I 3 I z I T PDF created with FinePrint pdfFactory trial version http www fineprint com W83L950D ute 5 980500 12 10 du 17 18 PWR ON 101415 SERIRQ Iio H 81 901 GPAT SRDYTI ST KBC PWR GPB2 SD2 B 03 GPAuRXD AL KBRC 8 4SVDD3 3 Omi 1
135. D PDA2 CDROM LED amp paci r1 HDD PDAO HDD DA2 HDD 5 i d RPXB HDD _LED aon Ed HDD LED 1 9 IDE_PDIOR 1 04 5_ HDD 42 avec 41 amp HDD PDAT 44 BAWSG NA 9 IDE GND2 RSV 42 9 R426 1 9 542 0402 CLi90G 0506 0804 FM 22PX2 2MM vel ALLTOP 17834 144 5 8427 9 0402 5 IDE Connector 4 HDD 18014 R325 20K 2 0402 4 1 d 4 18 SCROLL 01 19808 0503 HDD PIORDY R320 1 AJK A 2 0402 C251 cosa 2 010 ho NM CL908 K 0505 040 040 774 80 20 80 26 b of 0504 HDD PDDREQ 8226 206 2 0402 7 L1 WW vv GND CLi90G 0501 19 AC_POWER WW CLi90G 0502 19 BATT_POWER 2 0510 1 19 2 M 4 19 M 19 22SRVGC TRB E 5VS R429 8430 IDERST 0 17 IDE SDD O 15 IDE 8000 RP68 1 0 8 16 8000 0603 0603 Z CDROM_COMM 18 IDE SDD3 4 13 CD 5003 CDROM RIGHT ee EE 1 DESDE 8 12 CD 3004 WIS 10 10 10 10 mils IDE 5006 10 CD 5006 J21 5007 A rour 2 om Sec soure 291000150607 IDE 5008 RP63 1 08 ig 5008 5 AD 6 og 6 CD 5008 16V IDE 5009 CD SDDS CD SDD7 CD SDDS 50010 2 15 CD SDDiG CD_SDDE pay o 50070 Sec soure 297040100027 ang ETE EN ESI IDE SDDS 6 11 CD SDDi3 CD
136. D ROM drive by holding the tray that pops Figure 2 9 Figure 2 9 Remove the CD DVD ROM drive Reassembly 1 Push the CD DVD ROM drive into the compartment and secure with one screw 2 Replace the battery pack Refer to section 2 2 1 reassembly 55 8399 N B Maintenance 2 2 6 DDR SDRAM Disassembly 1 Carefully put the notebook upside down Remove the battery pack Refer to section 2 2 1 Disassembly 2 Pull the retaining clips outwards 0 and remove the DDR SDRAM Figure 2 10 Figure 2 10 Remove the DDR SDRAM Reassembly 1 To install the DDR match the DDR s notched part with the socket s projected part and firmly insert the DDR into the socket at 20 degree angle Then push down until the retaining clips lock the DDR into position 2 Replace the battery pack Refer to section 2 2 1 reassembly 56 8399 N B Maintenance 2 2 7 Modem Card Disassembly 1 Carefully put the notebook upside down Remove the battery pack Refer to section 2 2 1 Disassembly 2 Remove the two screws Figure 2 11 3 Disconnect the cable from the system board Then free the modem card Figure 2 12 Figure 2 11 Remove the two screws Figure 2 12 Disconnect the cable Reassembly 1 Fit the modem card Then reconnect the cable and secure with two screws 2 Replace the battery pack Refer to section 2 2 1 reassembly 57 8399 N B Maintenance 2 2 8 LCD ASSY Disassembly 1 Remove the battery pack an
137. DIN memm PWRINI SVDD3 VDD3 160 VDDA PD6 D17 Pos 155 PUIS Pos Pao DVMAIN 43V P gt 3175 LAN 43 VS LAN PL14 PU14 PL13 PR73 108 109 PL20 PR76 R296 rris 14 43V To Next Page 23 14 15 24 PUI9 25 165 3VS_USB Discharge BATT PLIS PR74 Pao 5 P me 5VS 2 5VS ramen NB VCCSUS U35 Pu 5V 1 AVDDAD R408 Q41 152 Pis _ 2 5 JS3 PL12 PR49 PU11 Ty PR51 PU10 PU12 PL7 1052710528 gt 25VS DDR To Next Page PLI1 PR53 Pay 105 106 1 25 DDR P 1 Avr PUI3 PJLI PL9 PL10 PQ4 P25 VCC_CORE PQ7 PL3 PL4 PU5 PU6 PU7 96 8399 N B Maintenance 8 1 Base Work Condition 2 4 System Voltage Check P Pao e PL2 PU3 PU2 101 202 2 5VS_DDR 1 2 P 1 2VLDTA pz P2 PUA 103 104 11 V Pm 1 51 Pr 127 2 5 m VDDA1 Pu TV_VDDA2 R235 C237 R261 Pe 125VSREF MON TV VDD R184 C150 C159 Pu 1 25VSREF_CLAW LVDSVCC DVDD w Pu DCVCC 3V VCCA P12 Piy P LLVCC Ps 2 5VDDA Pu 3 TV NB_AVDD2 Pe NB_AVDD1 Ps 3 3VDACVDD P6 1 5V_VCCAGP Ps 1 5V_NB Pe 1 5V_VCCVL 1 5VPLL1 Ps 1 5VPLL2 97 8 1 Base Work Condition 3 8399 N B Maintenance
138. DS DB LVDS D10 516 LV I2SEL 50 M 0402 LVDS D9 LVDS DIT Bi AS 2 0402 480 209 480 2094 480 2094 7 NB 9 T LVDS DT LDS HE Fab 58 Riz ANA 048 LVDS 7 50 7 0 VDS DIT 012 DSEL 2CDAT IPC 108 7 7 11 013 LVDS 014 81013 L2 78 7 4 224 0804 LVDS 012 7a 7 NB FPDi2 2 LVDS_D13 LVDS_D15 TST2 Lv EDGE 7 FPDi3 LVDS Di4 LVDS D18 4 015 EDGE PDF 7 14 016 22 V DUA 1 05 015 LVDS D17 3 24 DUAL 7 5 TVOS DIS D17 DUAL IV NTA 2 La LVINTR 018 INTR RPB 4 225 0804 LVDS 016 LVDS 019 1 25 lecvec 7 d AAA LVDS D17 019 TXCLK 9141 2012 3 7 amp LVDS 018 LVDS D20 100 42 TXCLK 1202 100 7 18 IVD DIS LVDS DAT 00 020 CLKt 7 NB_FPD19 lVDS D22 D21 RESERVED 0 28 4 224 AA 0804 LVDS D20 LVDS D23 97 022 RESERVED 1 7 NB FPD20 D23 100 7 21 1 RESERVED 2 22 lt do x 0805 040 7 22 A tee 22 LVDS VREF 8 RESERVED 3 29 Tm 10V one 90 99 7 2 425 190 20 50V 50V GND 0 RESERVED 4 21 5 SZ GND 1 RESERVED 5 LV AO RPi3 0804 GND GND 2 GND 3 RESERVED 6 22 WZ GND 4 RESERVED 7 24 x GND 5 GND 6 RESERVED 38 LV M GND 7 RESERVED 9 2 LAY oue LV INTR
139. G 9 2 lt 1 100 320 0805 0805 oau 050 0402 080 0402 R368 1 IKAS 2 0402 480 20 lt 80 20 43 80 20 E 80 20 0 case 4 1 25MMISTIMA2 BATS4C 5 lt 7 0402 R272 85205 0200 SVDD3 80 20 4 7KINA XZ 0402 5 o 015 EECS i 8 CS 4 25 EESK ew 078 Sec soure 291000010209 EEDI ask caos SB 188 2012 EEDO 59 6323 324 C332 2 5V NM93C46 180207 4 08 040 0905 508 EN 10 0002 10 150 80 20 1202100 380 20 5 D 20 2 R448 SZ 3K RICKI 8348 A 2 0402 RTCX2 GND SB n H A 1202 100 4 4 SB 4 x 1791 R450 C356 32 768 2 C355 402 18 18 1 97 1 caat 0402 E 0805 0805 10 10 10 10V 50 80209 1202 00M 180 2094 SB PLLGND 1 ii 50V 1804 20 2 GND Title Document ev Number Doo Date EHM 20 2004 Bheet 10 of 26 T PDF created with FinePrint pdfFactory trial version http www fineprint com Encoder VIA VT 1622
140. GDS1 as GDSIS iSSecondld strobe GFRAME GFR 9 IO Frame Assertion indicates the address phase of a PCI transfer for 4 Negation indicates that one more data transfer is desired by cycle initiator Interpreted as active high for 8x GIRDY GIRDY 10 IO Initiator Ready Interpreted as active low for PCI AGP2x 4x for 4x and high for AGP 8x For AGP write cycles the assertion of this pin indicates that the master is ready to provide all write data for the current transaction Once this pin is asserted the master is not allowed to insert wait states For AGP read cycles the assertion of this pin indicates that the master is ready to transfer a subsequent block of read data The master is never allowed to insert a wait state during the initial block of a read transaction However it may insert wait states after each block transfers For PCI cycles asserted when the initiator is ready for data transfer GTRDY GTRD 14 IO Target Ready Interpreted as active low for PCI AGP2x 4x Y for 4x and high for AGP 8x For AGP cycles indicates that the target GDEVSEL GDE VSEL for 4x mode is ready to provide read data the entire transaction when the transaction can complete within four clocks or is ready to transfer a initial or subsequent block of data when the transfer requires more than four clocks to complete The target is allowed to insert wait states after each block transfer for bo
141. HERMDA lt 1 10K 1 O B3MHZ B3MHZ B3MHZ 0402 310 AF pice 0402 001 ODE GND 0402 71 INPUT 1 6 24 50 us 1 1 NLY 3MHZ B3MHZ B3MHZ 2 Series resistors less than 1 41 20 i vob SMBCLK 19 3 GCLK NB amp SB VCLK is 4 longer i 2 MPO i pid 19 MODEC than 66M AGP 2 CPU THERMDC 2o A 20 THERN_ALERM TORTA Pin23 Pin24 781 i 508 0 PCICLES AGP Clock Signal T 84500781001 SZ PCI SB CLK 0283 5P 4 15 1 PCI_STOP 0402 10 PCI CARD CLK 257 1 22 1 12 0402 10 MINI PCI CLK C259 1 22 1 12 0402 10 1 6 24 2 Series resistors less than 1 183 152 FSI 150 CPU HIT 3 PCI SB CLK is 3 more than the 7 7 7 longest PCI clock 0 0 0 1 13390 0 0 1 0 16800 6720 0 0 1 1 20200 0 1 0 10020 0 1 0 1 13350 6675 9 1 1 0 1670 67 68 C242 1 22 0 1 20040 6680 DEFAULT 0402 1 10 1 0 0 0 1500 60 00 LPC 48M C270 1 22 1 0 0 1 18000 6000 0402 1 10 1 0 1 0 2100 7000 CLK 1 C281 1 22 1 1 0 1 1 24000 6000 0402 PETS 1 1 0 0 20000 6750 1 1 0 1 33 6667 1 1 1 0 67 6667 5 7 1 1 1 1 30000 7500 Title Document lev Number lt gt Date 20 2004 Eni 5 of 26 I T PDF created with FinePrint pdfFactory trial version http www fineprint com
142. High Performance HyperTransport CPU Interface Chipset support for AMD 8 ClawHammer Processor Processor interface via HyperTransport Bus Separate transmit and receive buses for no lost bus turnaround cycles All transmit and receive signals use 2 pin low voltage swing differential signalling for high reliability and high speed 4 8 or 16 bit control address data transfer both directions 8399 N B Maintenance 800 600 400 200 MHz clock rates with Double Data Rate style operation for 1600 1200 800 400 MT s in both directions simultaneously total 6 4GB sec using 16 bit transfer mode Default 8 bit 200 MHz operation on startup for high reliability with speedup to dual 16 bit 800 MHz operation 6 4 GB sec total bandwidth under software control transmit and receive may be different widths and or speeds Full Featured Accelerated Graphics Port AGP 8x Controller Supports 533 MHz 8x 266 MHz 4x and 133 MHz 2x transfer modes for AD and SBA signaling v3 0 compliant with 8x transfer mode Pseudo synchronous with the host CPU bus with optimal skew control Supports SideBand Addressing SBA mode non multiplexed address data AGP pipelined split transaction long burst transfers up to 1GB sec Eight level read request queue Four level posted write request queue Thirty two level quadwords read data FIFO 256 bytes Sixteen level quadwords write data FIFO 128 b
143. IIVCC D9 E9 Power Interface Power 3 3V 5 E10 Ell 25 D12 Power MII Suspend Power 2 5V 5 E12 RAMVCC E7 Power Power For Internal LAN RAM 2 5V 5 RAMGND E6 Power Ground For Internal LAN RAM 82 8399 N B Maintenance 5 3 VIA 8235 South Bridge 4 Serial EEPROM Interface Universal Serial Bus 2 0 Interface Signal Name Pin I O PU Signal Description Signal Name Pin I O Signal Description EECS D11 0 Serial EEPROM Select USBP0 E20 IO USB 2 0 Port 0 Data EECK C12 Serial EEPROM Clock USBPOC D20 IO USB 2 0 Port 0 Data EEDO B12 I Serial EEPROM Data Output Connect to EEPROM Data USBPI A20 IO USB 2 0 Port 1 Data Out pin USBPIC B20 USB 2 0 Port 1 Data EEDI A12 0 Serial EEPROM Data Input Connect to EEPROM Data In pin USBP2 E18 IO USB 2 0 Port 2 Data USBP2 D18 IO USB 2 0 Port 2 Data USBP3 18 IO USB 2 0 Port 3 Data USBP3 E 18 IO 8 2 0 Port 3 Data Low Pin Count LPC Interface USBP4 D16 0 USB 2 0 Port 4 Data Signal Name Pin I O PU Signal Description USBP4 amp E16 IO USB 2 0 Port 4 Data LERNDE ARE LPC Frame USBP5 Al6 USB 2 0 Port 5 Data LREQ 6 10 LPC Bus Master Request USBPS E Bl6 IO USB 2 0 Port 5 Data LADIS
144. J14 103221109 117 8399 N B Maintenance 8 10 CD ROM Driver Test Error 1 CD ROM driver can t run normally maybe an error message is shown when reading data from CD ROM CD ROM Driver Test Error Check the CD ROM driver for proper installation Re Test Yes Replace OK the faulty parts Board level Troubleshooting Check following parts and signals Parts Signals U20 CD 8 15 CD SDCS 1 3 4 CD SDA 0 2 CD SDDACK Z CD _SDIOW Replace CD SDDREQ Motherboard CD SIORDY CD IRQIS CD SDIORZ PCI RST 118 8399 N B Maintenance 8 10 CD ROM Driver Test Error 2 CD ROM driver can t run normally maybe an error message is shown when reading data from CD ROM 45V m 38 42 if 43V C34 0 10 010 R364 R384 R398 V 27K 10K 47K PR63 PR68 IDE_SDD 0 15 CD 5000 15 EN p13 P13 IDE_SDCS 1 3 50 8 1 3 SDA 0 2 CD SDA 0 2 4 4 P8 79 IDE SDDACK CD SDDACK amp 28 IDE_SDIOW CD_SDIOW 25 J21 IDE_SDDREQ CD_SDDREQ 22 NNR U20 R385 10K co v South Bridge RP69 z IDE SIORDY 0 4 CD SIORDY 27 VT8235 ANNE 18015 i CD_IRQ15 29 mo a E IDE_SDIOR AA CD_SDIOR 24 i 43V 43V 45V 43V R327 R331 10K 10K R297 22 PCI_RST 74 08 V IDE PCIRST4 IDERST 5 Q32 DTCI44TKA 119 8399 N B
145. J45 RJ1 1 294011200016 LED GREEN H0 8 0603 CL 190G SMT 5 294011200200 LED GREEN RED H0 8 W1 9 19 22SRV D510 295000010008 FUSE 1 1A POLY SWITCH 1812 SMT 295000010016 FUSE NORMAL 6 5A 32VDC 3216 SMT Fl 21 295000010102 FUSE FAST 3A 32V 1206 SMT CERAMI 295000010116 FUSE FAST 10 86VDC 6125 5 0 C 4 4 N D EM ISP 2 29 A SUYIN CON STEREO JACK 5P R A 28MF60 07 CON STEREO JACK 5P R A 28MF60 05 CON MINI DIN 7P R A W GROUND 030 331910002006 CON POWER JACK 2P 20VDC 5A DIP 332110020097 WIRE 220 UL1007 74MM BLACK YIYI CN6 332810000212 PWR CORD 125V7A 2P BLACK AMERI 295000010154 FUSE FAST 1 25A 63V 1206 SMT 043 295000100004 FUSE FAST 1A 63V 1206 T HIN FILM 297030100015 SW TOGGLE SPST 5V ImA 4P SMT T AI 297040105010 SW PUSH BUTTOM 5P SPST 12V 50MA 310111103013 THERMIST OR 10K 1 RA DISK 103AT T 310111103025 THERMIST OR 10K 1 RA DISK 103AT 310111103031 THERMIST OR 10K 1 150MM BN35 3H1 312272263511 EC 22U 25V 20 RA 8 10 5 105 C 0 PCL15 PC27 PC52 PC54 312273361501 EC 330U 6 3V 6 3 7 105 32 33 384 312276806151 6801 6 3V 20 D10 105 C 0S C 312278206151 EC 820U 4V 20 100 10 5 SP 0S gt ro az uu ala Q 4 oo E po fo w gt 2 5 2 gt gt D 2 Q N oa N ty 2 gt
146. K AE11 16 13 IDE_SDIOR SDIOR SHDMARDY SHSTROBE 16 3 16 HAEL SA17 ISA SA16 17 45V 42 5V 18 IDE_SDIOW SDIOW SSTOP 7 5 ISA 17 9 9 5 13 IDE SIORDY SDRDY SDDMARDY SDSTROBE SA18 GPO18 SAIS ISA SA8 17 13 IDE 50 51 SDCSt SA19 GPO19 E 1 13 IDE 806838 SDCS3 FEN 19 IDE SDAD ISA SDT ISA_SD0 SA SDi 10 ISA SD4 WARE UE GPa 13 IDE_SDAt SDA1 1 801 17 a 4 4 4 E14 15 502 BADO 17 15 502 1 5 505 5 5 5 C393 C394 C334 1 SDA2 XD2 Faria ISA 803 s 1 ISA 503 1 1 TSA_SD6 SCI SUSCLK 100 13 IDE 19015 18015 XD3 A514 504 88 a 11 1 ISA SD7 0805 0402 0402 AF13 ISA 505 Md 80 2096 80 20 80 20 ae ARIZ 8a Soe ISA 506 17 SCOMPP XD6 1 557 ISA_SD6 17 26 Xp ISA SD7 17 8225 BGA451 36 1MM GND GPIO24 GPIO25 GPIOSO GPIOST 9 caso cas cage 100 010 SA 17 16 gt LDT Frequency ROMCS LPC Interface Select 51 gt EEPEOM Select SDCS3 gt Test Mode Select 0805 0402 0402 00 200MHz Default 10 600MHz 0 ble Porting 0 Disable Default e 80 20 e 80 20964 80 20 01 400MHz 11 800MHz 1 nsable LPC Default EEPROM On board Default 1 PINOUT 3VS RESERVE RESERVE XTSMI VAKE UP R359 8358 R362 R367 R365 EWR 2 7KI
147. MS2951CS 3 3 3 3V 150MA VLOT 1C G692L293T CIRCUIT 2 93V IC 875061EUP VOLT DETECTOR DIODE SS14 40V 1A SMA VISHAY DIODE BAS22L VRRM75V MELF SOD 80 DIODE SSA34 40V 3A SMA DIODE BATS4C SCHOTTKY DIODE SOT 2 DIODE BAW56 70V 215mA SOT 23 DIODE UDZ5 6B ZENER 5 6V UMD2 SM DIODE BAWS6LT 1 70V 215MA SOT 23 DIODE BAV70LT 1 70V 225MW SOT 23 DIODE SBM1040 10A SCHOT TKY POWER DIODE RLS4148 200MA 500MW MELE S DIODE BZV55 C24 ZENER 5 SOD 80 DIODE 1 8355 80V 100mA SOD 23 SM DIODE 158 154 400 400V 1 0A TRANS DTC144TKA N MOSFET SOT 23 TRANS DT A144EKA PNP SMT TRANS FDV301N N CHANNEL SOT 23 TRANSAOBA16 30V 110A 00650HM N 8399 N B Ma ocation S PU20 U a a 5 ci PD14 PD17 PD7 PD8 3 PS 2 g N N D vo ro ro d ro 3 8 JEHA TE Fr a d e Mai gt gt intenance 283200717001 288203400001 TRANSAOS400 N MOSFET SOT 23 288203403001 TRANSAOS403 P MOSFET SOT 23 ALP 288203413001 TRANSAO3413 P MOSFET SOT 23 RAN 288204403008 TRANSAO4403 P MOSFET 46mOHM VG 288204407001 TRANSAO4407 P MOS 01 508 5 TRANS A04409 P MOSFET S0 8P MSL TRANS A04410 N MOSFET ID 18A 0 0 TRANS A04422 24mOHM N MOSFET SOI TRANSSIA832DY N MOSFET 028 NS A0
148. Maintenance Integrated bus mastering dual full duplex direct sound AC97 link compatible sound system Plug and Play controller that allows complete steer ability of all PCI interrupts and internal interrupts DMA channels to any interrupt channel One additional steerable interrupt channel is provided to allow plug and play and reconfigure ability of onboard peripherals for Windows family compliance The VT8235CD also enhances the functionality of the standard ISA peripherals The integrated interrupt controller supports both edge and level triggered interrupts channel by channel The integrated DMA controller supports type F addition to standard ISADMA modes Compliant with the PCI 2 2 specification the VT8235CD supports delayed transactions and remote power management so that slower ISA peripherals do not block the traffic of the PCI bus Special circuitry 15 built in to allow concurrent operation without causing dead lock even in a PCI to PCI bridge environment The chip also includes eight levels double words of line buffers from the PCI bus to the ISA bus to further enhance overall system performance CA MA Command CPU Cache CD North Bridge MD System Memory Sideband Signals Vlink DIMM Module ID Init A20M Interface INIR NMI SMI Stop CLK SMB FERR IGNNE Sleep USB 2 0 Ports
149. Maintenance 8 11 Audio Failure 1 There is trouble with the sound from speaker or completely no sound Audio Failure 1 Check if speaker cables are connected properly 2 Make sure all the drivers are installed Board level Troubleshooting properly Check following parts and signals Parts Signals U10 AVDDAD AOUT Correct it U14 VREF_OUT GPI3 U26 MIC1 TP534 U13 MIC2 5V_AMP J13 CDROM LEFT SHUTDOWN 121 CDROM RIGHT SPKR 145 CDROM sPKR ROUT Try another known good speaker Replace d 2 2 CD ROM Motherboard L43 AC97 SDIN HP SENSE R200 AC97 SDOUT R191 AC97_RST R194 AC97_BITCLK R213 SB SPKR Re test Replace the L62 CARDSPK faulty parts R172 AOUT_L R173 120 8 11 Audio Failure 2 Audio In xvf 8399 N B Maintenance There is trouble with the sound from speaker or completely no sound AVDDAD L47 1207 100 5 25 38 199 189 190 100 010 0 1U 26 42 145 1207 100 3VS 19 Oo e 7 C186 C182 C185 0 1U 0 1U 0 1U 47 R200 IK 191 0 VREF OUT 28 L43 C135 P18 J10 600Z 100M 1U STV R194 MICI T 21 D C141 3 PC 600Z 100M 1U AY NY R213 IK MIC2 e 22 i R214 RI78 C2011 C162 47K 41K 270P 270P FTI 501 Internal Microphone 1207 100 2 1 CDR
150. NA 2 7KINA 27K 2 7KINA 0603D 06080 0603 06030 SA16 SA17 ISA_ROMCS SDCS1 SDCS3 R373 R372 R376 R381 R379 R317 R351 2 7K 27K 10K 1K 1K 0603 0603 ZIONA 0402 0402 0603D 0603D 0603D 5 PVREF SVREF R319 R352 GPO16 SDAO 5 1 gt SA 18 LDT Width 383 383 GPO 2 0603 0603 8 017 Trasmit Timing control Extermal loop test mode oris GPO19 0 Disable Default 1 16 Bit 1 Ensable GPIO MB 100 MB IDi GPIOlU GPIOll 012 GPIOl4 R363 2 7KINA RESERVE RESERVE 0603D SB GHI RESERVE SDAO Mitac 22 27KINA 9503 lt Title gt PD Bize lev GND GND Date Bheet 9 o 26 20 2004 T PDF created with FinePrint pdfFactory trial version http www fineprint com 2 5VS_DDR SB VIA_VT8235CD 3 3 THERA XLLXLLLXLLXXXXXXX 4
151. NTB KBD CS1 PEE gt PCI TRDYS Aag ROV SB 141 d PCI STOPR TRDY PCI_INTD SPRR_MUTER 1445 14 15 PCI SERR 1445 PCI PAR PAR 14 5 PCI_PERR PERR use 922 8287 1 2 0402 1 M PCI REQ 0 7 FONTE INTAR GND PCI PCI_GNT 4 14 INTB 2 PCI_GNT S 1 INTCH SB KA20G PCI_REQHS 4 15 PCI_INTD INTD KBCK KA20G 3238 4886 lt lazoG 19 5 PCI REGHO KBDT KBRC SERGI KBRC 19 14 PCI gt PCL REQO N2 15 PCI REQUE 1 12 M1 58 618 PCI_REQHS REQ2y PCI 4 D amp PCI REGIS REQ4 IPBTDFR GPI4 GPO14 28 RBD 0ST ENBL SB 12 5 IPBRDFR GPHO GPOTO 2 KBD 060 19 PCI GNT amp O 6 IPBTDCK GPISGPOE T 15 PCI_SERR PCI_FRAME 44 POLONTOR GNTO SB GPIO12 PCI PARE PCI DEVSELE 15 PCLGNTI GNTI IPBOUTO GPIT2 GPO12 PRG MUTER LcD 02 12 PCI PERRE PC GNTIS GNT2 IPBOUTI GPI13 GPO13 88 po PCI TRDY PC CNTA GNT3 IPBINO GPI8 GPO8 1 PCI GNTIS IPBIN1 GPI9 Po9 GNTS 22 222222222222222222222222 FOIGUS oo 8885025520220250200020050 222222222222222 Reera
152. NsE Nco Hx i nade D Puts 32 nes VOSENSE2 4 SGND SOS je af 2 5 all 4 poor Sonos 02 8200 iU 107 Sow 83582588 1206 o 1u deo s 10 FT 16V 0603 100 50 44444444 doled 1206 16V 105 PR69 4 1 1 i T 10008 0603 i 7 pcos 107 10 7 5 180P 0603 4 0603 VA 2K Poro 1 5 J 0508 0603 a7p 2868 0603 PRG 20K Am pne 10 e Pred 200 0603 i 0603 OK 2004 060 10 7 i 603 0603 1 A 1 3 JS 4 1 4 44 4 1 Dq 4 SHORT SMT1 NA GND PR63 SGND3 5003 0803 9 4 2 SVDD3 4 1 2 INTVCC2 9 PR57 J 100K 10K 0603 0603 PR72 di 1 100K Pan 0603 J G 2N7002 pars 4 4 1 2 7002 55 Paro 4 PWR ON 3VS 5 6 1 2 7002 0 0603 0 12 DVT 19 PWR ON 3VS 5 6 PRIV 1 0806 1 PR74 change from 0 008 to 0 012 2 PL13 PL15 change to 273000990018 for height 3 PC90 change from 1000P to 4700P for H W sequence 36 03 1 003 change to 5 003 2 PC106 change from 1000P to8200P 272075822401 3 90 change from 4700P to 0 01U 272075108403 Title Document lev Number Doc Date 20 2004 Bheet 26 of 26 5 z 3 z T PDF created with FinePrint pdfFactory trial version http www fineprint com REFERENCE MATERIAL
153. OM LEFT R173 330 C144 IU 18 8 VT amp 2 CDROM RIGHT R172 330 142 1U 20 RI77 C134 R176 C133 E 100K 2200P gt 100K 2200P 5 S 3 CDROM_COMM C143 1U 19 8 P18 U10 Audio Codec 1714 2 AUDIO 14M R240 22 45 CLK Generator ICS950403 SB next page 10 AC97 SYNC R304 22 8 R192 22 AC97_SDIN P10 D 5 AC97 SDOUT R305 22 U20 11 AC97_RST R300 22 lt 6 R333 22 AC97 BITCLK Bridge VT8235 AVDDAD 3 C188 0107 R436 10K cias FH AHC1G86DBV 10 100K 1 SB SPKR P14 12 PCBEEP 4 1 2 CARDSPK 62 U26 R202 10K R393 R206 PCMCIA 10K 10K Controller To next page To next page AC_GPI3 To next page 121 8399 N B Maintenance 8 11 Audio Failure 3 Audio Out There is trouble with the sound from speaker or completely no sound TEM 45V L52 120Z 100M 2 e Y Y e e 7 18 19 Z 419 235 229 212 C213 0 1U 100U 0 1U 0 1U 0 10 V VDD3 216 100K SHUTDOWN 22 SB_GPOO wk From front page 020 DECIAATEA C2344 8 R219 100K 2 R221 100K 3 C231 1U 10 e If C232 1U 11 e FTI P 15 U13 Audio 4 21 5 153 1202 100 16 SPKR ROUT 154
154. PURST generation Keyboard Chip Select 51 0 0 To external keyboard controller chip Strap high to enable LPC BIOS ROM Note KBCK KBDT MSCK and MSDT are powered by the VSUS33 suspend voltage plane Speaker Signal Name Pin I O PU Signal Description SPKR strap AF8 Speaker Strap low to enable high to disable CPU frequency strapping Signal Name Pin Signal Description PWRGD ACS I Power Good Connected to the Power Good signal on the Power Supply Internal logic powered by VBAT PWROK AF1 0 Power OK Internal logic powered by VSUS33 PCIRST R1 0 PCI Reset Active low reset signal for the PCI bus The VT8235 Version CE will assert this pin during power up or from the control register OSC ABS I Oscillator 14 31818 MHz clock signal used by the internal Timer RTCXI AEA I RTC Crystal Input 32 768 KHz crystal or oscillator input This input is used for the internal RTC and power well power management logic and is powered by VBAT RTCX2 AF3 0 RTC Crystal Output 32 768 KHz crystal output Internal logic powered by VBAT TEST 9 1 Test TPO AF9 0 Test Pin Output Output pin for test mode NC see pin No Connect Do not connect list 5 3 VIA 8235 South Bridge 7 General Purpose Inputs 8399 N B Maintenance General Purpose Inputs Continued Signal Name Pin VO Signal Description Signal
155. S 203 wa op e voDiorg HEL 1524 M21 vss as vss 205 Yo 87 AE Testa vss so VSS 205 VDD Ves ot VSS 207 VOD 90 sENsE AEH 8187 1 0402 vss 2 88 208 91 AH vss 98 VSS 209 2 VSS 94 VSS 210 VDD 93 A0 1 2VLDTA N20 vss 95 VSS 211 5 94 VLDTO A1 2 vss 96 VSS 212 95 VLDTO A2 N24 vss 97 VSS 213 VDD 96 VLDTO A3 P2 vss 98 VSS 214 2 00 97 A4 1 2VLDTB 99 55 215 20 24 VDD 5 28 vss 100 vss 216 A22 es AAS pp 99 VLDTO AG Place HT vss 101 vss 217 VDD 100 bypass caps VSS 102 vss 218 128 gt Et B1 55 103 7820 ALL PWROK 2 50 34 25 VIDO E12 0 VLDTO B2 VSS 104 VIT 1 25VTT 25 E15 B3 near i VSS 105 4 B4 ct VSS 106 VIT A2 3 E14 unconnected 25 018 85 i VSS 107 VIT 2 25 VIDA G13 vip s Clawhammer VSS 108 VIT 1 iE BT link VSS 109 VIT gt RESET 2 QUA HANI EO NE VSS 110 vir Bt 4 5 vyssim VIT B2 R369 VSS 112 VIT V 4 VSS 113 10 0402 85515 VIT SENSE BUS 248 5 X 6 NB_LDTRST 383 1 AYA 2 0402 gt CLAWHAMMER Quo om BGA754_SKT 8 CPU_PCIRST
156. SDD3 18 CD SDD13 1 1DE 5014 10 CD 50014 CD SDD2 DES tm 0018 is CD SDD14 T67 1207 100 1608 x 1 IDE 80015 8 CD 50015 CD 5601 002 0014 55 CD 50015 T DATA RPX8 CD_SDDO DD1 CD SDDREQ 19 T DATA t 3 005000 9 IDE SDAO pee GND o CD 1 4 9 IDE SD CD EDCSTE CD SIORDY H pows uy 25 31 SWEEERT tu 1 i 9 IDE 50 51 CD EDCSSI CD RAIS 2 IORDY DMACK o CD mJ TRO Hono sa E TC010 PSS11CET SW504 One A CD SDAD X DAT 297040105010 FPC FFC 0 5MM 6P P Ed CD_SDDACKE CD_SDCST pag dE Lan CD 90 53 SW 010 511 ACES need CD SDDREG CDROM LED o SEN m 20096 0600 D 1 Veco S Yes H 69 CD IRQ15 Close to IDE Connector SW RIGHT 9 IDE 18015 CD SDIORE VCCI m 9 IDE_SDIOR eT anos eee x x 47 0804 49 50 010 SW 010 511 015 4 RSV 0402 0402 1 7 yq GND 1 1 A 43V 470 NA GND amp cp 1 2 0402 1 503 507 ESD0805A NA ESD0805A NA 5 0 8 GND GND CD 18015 R384 1 A 2 0402 i SPEED GU 1 2 x Sec soure 297040100027 Y GN eX 1 CD sDDREQ R385 1 AQK A 2 0402 FPC FFC 0 SMM f2P NA 5 331000050005 Xp Sec soure 1 CD 8007 E R328 5 6K 0402 5 R327 R331 10K 10K
157. SERVICE MANUAL FOR 8399 BY Grass Ren Repair Technology Research Department EDVD Aug 2004 mitac gt 8399 N B Maintenance Contents 1 Hardware Engineering Specification x E EP ETE 3 1 1 Introduction PCT n 3 1 2 Hardware Specification 5 13 Systems Hardware Parts 7 L4 Other Functions QE EFE ER E ER RRF ACRES 40 2 System View amp 1 GOD 45 2 1 6 45 2 2 System Disassembly dero 48 3 Definition amp Location of Connectors Switches Setting 67 4 Definition amp Location of Major Component 70 5 Pin Description of Major Component 2 71 5 1 AMD Mobile Athlon 64 ClawHammer Processor
158. SET L LIOS System Reset PWROK IIOS Indicates that voltages and clocks have reached specified operation LDTSTOP L LIOS Technology Stop Control Input Used for power management and for changing HyperTransport link width and frequency VID 4 0 O IOS Voltage ID to the regulator THERMDA Anode of the thermal diode THERMDC Cathode of the thermal diode THERMTRIP L Thermal Sensor Trip output asserted at nominal temperature of 125 0 COREFB H L Differential feedback for VDD Power Supply VDDIOFB H L Differential feedback for VDDIO Power Supply CORE SENSE VDD voltage monitor pin VDDA Filtered PLL Supply Voltage VTT SENSE VTT voltage monitor pin VDDIO SENSE VDDIO voltage monitor pin VDD Core power supply VDDIO DDR SDRAM ring power supply VLDT A HyperTransport ring power supply for side A and side VLDT B of the package VIT S VTT regulator voltage for side A and side B of the die B VSS S Ground Debug Pin Descriptions Signal Name Type Description DBREQ L I IOS Debug Request DBRDY O IOS Debug Ready JTAG Pin Descriptions Signal Name Type Description TCK 1108 Clock TMS 1105 JTAG Mode Select TRST L LIOS JTAG Reset TDI 1105 JTAG Data Input TDO O IOS Data Output Clock Pin Descriptions Signal Name Type Description CLKIN H L 100 1200
159. TA 11 FASS CEU 28 LO gt 10 L0 MEMADDA 12 MEMDATA 12 AHS L0 CTUN 828 trout EB T MEMADDA 13 MEMDATA 13 6 LO CADIN H 0 15 CTLOUT Heee gt CTLOUT 6 4 0 131 VEMADD MEMDATA 14 2492 10 bo CTLOUT ML p27 CTLOUT Lo 9 MEMADDBIO MEMDATALISI CPU MD16 DDR CLK4 207 3 0402 DDR CLK4f 10 CAD CTLOUT L0 to GTtOUT Li L 64 tpsto MEMADDB I MEMDATALIS CPU MD17 DDR CLKS R210 1 0402 DDR CLKS 10 CADIN 2 7 CPU MOIS BOR cike 0402 PDE GE 10 AE26 10 REFO MEMADDBIS 181 CPU 19 DDR 8186 1 0402 DDR CLK7 L0 CADIN Hj4 Lo 422810 REFT MEMADDBI4 MEMDATA 19 020 10 CADIN HIS LO REF AJ DTSTOP amp 961 2 0402 MEMADDBIS MEMDATAI20 CPU MD21 LO CADIN HIS LDTSTOP L Rag m LOTSTOP 6 10 MEMADDBIS MEMDATA 21 AG3 LO CADIN H 7 LDTSTOP_NB 6 7 MEMDATA 22 Mbs LO CADIN B NC 19 8 MEMDATA 23 GBU MDA 10 H 9 NC 25 x MEMADDB S MEMDATA 24 ARI GBU MDE LO CADIN H 10 NC AA2 2 MEMADDB 10 MEMDATA 25 802 55 Mbot 10 H 11 MEMADDB 11 MEMDATA 26 GPU MOS 6 L0 CADIN H 12 NC AE
160. TB j 2 UpstB GD14 DP2D09 FPD21 12 GD15 DP2D08 FPD20 12 GND GND 10 DNSTB DNSTB GD16 DP2D06 12 10 DNSTB 2 GD17 DP2D05 FPDI7 12 GD18 DP2D04 FPDIG 12 10 UPCMD 28 upcMD GD19 DP2DE FPDE 12 10 DNCMD DNCMD GD20 DP2D02 FPDI4 12 GD21 DP2CLK 12 NB L VLVREF GD22 DP2D01 FPDI3 12 GD23 DP2D03 FPDIS 12 LCOMPP LCOMPP VLPCOMP GD24 DP1D09 AES GD25 ARZ 3820 ALL PWROK 25 C gt E ewROK GD26 DP1D10 AEX GD27 ADS NB_PCIRST gt GD28 DP1D07 5 GD29 DP1D06 TESTIN 26 AEA AGP 8XDE R99 1 0 0402 TESTIN GD30 DP1D08 Gps 2 CLK R31 1 o o sussti 8098718 26 9081 0 10 DEBUG R164 1 A 2 0402 SUSST apis NB FPD09 IPC DATA 190 1 AJK A 2 0402 DEBUG 0 NB FPDOS 12 gig 5 2 0402 BISTIN 402 1 GBEvSBDAT 158 A 5 2 040 12 DATA LVDS 12 PSTN 1 AA A 2 0802 a NB FPUIS SP SSON Ri 1 X A 2 0402 GBEP DP2D07 ARLE TONS c FPDi9 12 LCOMPP GBE3 DP1D11 2 11 CRT RED R GDSOS GDSOf DP3Do2 HAE NE FROM 3 4 NB 02 12 11 CRI GREEN AG GDSOF GDSO DP3D04 NB FPDo4 12 11 GDsis GDStWDP2DET AE NS Fpp RSET cas lt AGP_ADSTBS1 R162 1 A A 2 0402 4 RSET 081508065 DEADET NB FPDI2 Ns seis As AGP ADSTBS Ri62 0402 TESTIN R137
161. a VT8235 Version CE initiated transaction and is also sampled when decoding whether to subtractively decode the cycle IO Frame Assertion indicates the address phase of a PCI transfer Negation indicates that one more data transfer is desired by the cycle initiator IRDY Initiator Ready Asserted when the initiator is ready for data transfer TRDY STOP Target Ready Asserted when the target is ready for data transfer Stop Asserted by the target to request the master to stop the current transaction SERR System Error SERR can be pulsed active by any PCI device that detects a system error condition Upon sampling SERR active the VT8235 Version CE can be programmed to generate an NMI to the CPU PERR PAR Parity Error PERR sustained tri state is only for the reporting of data parity errors during all PCI transactions except for a Special Cycle Parity A single parity bit is provided over AD 31 0 and C BE 3 0 81 5 3 VIA VT8235CD South Bridge 3 8399 N B Maintenance PCI Bus Interface Continued LAN Controller Media Independent Interface MIT Signal Name Pin Description INTA A4 I PCI Interrupt Request The INTA through INTD pins are INTB B4 typically connected to thePCI bus INTA INTD pins per the INTC B5 table below are enabled by setting Devicel7 INTD C4 Function 0 Rx5B 1 1 BIOS s
162. aDMA 133 100 66 transfer protocols Thirty two levels double words of prefetch and write buffers Dual DMA engine for concurrent dual channel operation 24 8399 N B Maintenance Bus master programming interface for SFF 80381 rev 1 0 and Windows 95 compliant Full scatter gather capability Support ATAPI compliant devices including DVD devices Support PCI native and ATA compatibility modes Complete software driver support Direct Sound Ready AC97 Digital Audio Controller AC Link access to 4 CODECs AC97 AMC97 MC97 Multi channel Audio Bus Master Scatter Gather DMA Dedicated read and write channels supporting simultaneous stereo playback and record Dedicated read and write channels supporting simultaneous modem receive and transmit 1 stereo DirectSound channel with source volume control mixer 1 shared FM SPDIF PCM read channel 1 dedicated channel supporting multi channel audio 32 byte line buffers for each SGD channel Programmable 8bit 16bit mono stereo PCM data format support AC97 2 1 compliant 25 8399 N B Maintenance System Management Bus Interface Host interface for processor communications 4 Slave interface for external SMBus masters Universal Serial Bus Controller USB v2 0 and Enhanced Host Controller Interface EHCI v1 0 compatible USB v1 1 and Universal Host Controller Interface UHCI v1 1 compatible Eighteen level double words data FIFO with full scatter an
163. activates reads and writes the two copies are inverted from each other to minimize switching noise The signals are inverted only when the bus is used to carry address information 1 MEMRESET L 0105 DRAM Reset pin for Suspend to RAM power management mode This pin is required for registered DIMMs only MEMVREF VREF DRAM Interface Voltage Reference 1 MEMZP A Compensation Resistor tied to VSS 1 MEMZN A Compensation Resistor tied to 2 5 V 1 Note For connection details and proper resistor values see the AMD Athlon M 64 Processor Motherboard Design Guide order 24665 HyperTransport Technology Pin Descriptions Signal Name Type Description LO CLKIN H I 1 0 LHT Link 0 Clock Input LO CTLIN H I 1 0 Link 0 Control Input 2 10 CADIN H L 15 0 Link 0 Command Address Data Input L0 CLKOUT H I 1 0 O HT Link 0 Clock Outputs L0 CTLOUT H I 1 0 O HT Link 0 Control Output 10 CADOUT H L 15 0 O HT Link 0 Command Address Data Outputs 10 REFI A Compensation Resistor to VLDT 1 10 REFO A Compensation Resistor to VSS 1 MEMADDB 13 0 MEMDATA 63 0 B IOS DRAM Interface Data Bus MEMCHECK 7 0 B IOS DRAM Interface ECC Check Bits MEMCS L 7 0 O IOS DRAM Chip Selects 1 MEMRASA L O IOS DRAM Row Address Select MEMRASA and MEMRASB L MEMRASB L are functionally identical Two copies are provided to accommodate the
164. ation Strap VDO 5 NB Strap VDO signal state is reflected Check the Configuratio on signalpin VD 0 during power NorthBridge DS n up for North Bridgeconfiguration fordetails Signal Name Pin Signal Description VSUS33 AAA Suspend Power 3 3V 5 Always available unless the AB4 6 mechanical switch of the power supply is turned off If the ihsoft offI D state is not implemented then this pin can be connected to VCC33 Signals powered by or referenced to this plane are PVRGD RSMRST PWRBTN SMBCK1 2 SMBDT1 2 GPOO SUSA GPO1 SUSB GPO2 SUSC SUSST1 SUSCLK GPO4 GPD EXTSMI RING LID GPI5 BATLOW 6 PMEZ SMBALRT VSUS25 T4 U4 Suspend Power 2 5V 5 VSUSUSB C24 USB Suspend Power 2 5V 5 VBAT Battery Battery input for internal RTCXI RTCX2 VLVREF H22 V Link Voltage Reference 0 9V 5 for 4x transfers and 0 625V 5 for 8x transfers VLCOMP J22 V Link Compensation V Link Compensation Circuit Voltage 2 5V 5 list MIIVCC D9 LAN Power 3 3V 5 Power for LAN Media E9 11 Independent Interface interface to external PHY Connect to VCC33 through a ferrite bead MIIVCC25 012 LAN Suspend Power 2 5V 5 E12 LANVCC E7 LAN Power 2 5V 5 Power for LAN Connect to through a ferrite bead LANGND E6 LAN Ground Connect to GND through a ferrite bead USBVCC see
165. ation and PCI Bus Power Management Interface Specification for PCI to CardBus Bridges card signals are internally buffered to allow hot insertion and removal without external buffering The ENE CB1410 internal data path logic allows the host to access 8 16 and 32 bit cards using full 32 bit PCI cycles for maximum performance Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting The ENE CB1410 can also be programmed to accept fast posted writes to improve system bus utilization Multiple system interrupt signaling options are provided including parallel PCI parallel ISA serialized ISA and serialized PCI Furthermore general purpose inputs and outputs are provided for the board designer to implement sideband functions Many other features designed into the ENE CB1410 such as socket activity light emitting diode LED outputs are discussed in detail throughout the design specification 30 8399 N B Maintenance An advanced complementary metal oxide semiconductor CMOS process achieves low system power consumption while operating at PCI clock rates up to 33MHz Several low power modes enable the host power management system to further reduce power consumption The CB1410 Supports the Following Features e e operation with 5V tolerant 144 pin LQFP or 144 ball LFBGA package for CB1410 single slot Cardbus controller Compliant with
166. ator to disable the CPU clock outputs Not connected if not used PCISTP GPO6 AD6 PCI Clock Stop RxE4 1 0 Signals the system clock generator to disable the PCI clock outputs Not connected i not used GPOI 2 Suspend Plane Control 94 2 0 Asserted during power management POS STR and STD suspend states Used to control the primary power plane 10K PU to VSUS33 if not used SUSB GPO2 AD3 Suspend Plane B Control Rx94 3 0 Asserted during power management STR and STD suspend states Used to control the secondary power plane 10K PU to VSUS33 if not used SUSC AF2 Suspend Plane C Control Asserted during power management STD suspend state Used to control the tertiary power plane Also connected to ATX power on circuitry 10K PU to VSUS33 if not used Power Management and Event Detection Continued Signal Name Pin IO Signal Description SUSST1 Y3 0 Suspend Status 1 Rx94 4 0 Typically connected to GPO3 the North Bridge to provide information on host clock status Asserted when the system may stop the host clock such as Stop Clock or during POS STR or STD suspend states Connect 10K PU to VSUS33 SUSCLK Suspend Clock 32 768 KHz output clock for use by the North Bridge e g KT400A CLE266 or P4X400 for DRAM refresh purposes Stopped during Suspend to Disk and Soft Off modes Connect 10K PU to VSUS33 CPUMISS
167. bead for isolation of digital switching noise VCCPLLI 05 Power for Graphics Controller PLL1 E Clock 1 5V 5 connected via ferrite bead for isolation of digital switching noise GNDPLL1 C5 Ground for Graphics Controller PLL1 E Clock Connect to main ground plane via ferrite bead for isolation of digital switching noise VCCPLL2 5 Power for Graphics Controller PLL2 D Clock 1 5V 5 connected via ferrite bead for isolation of digital switching noise GNDPLL2 Ground for Graphics Controller PLL2 D Clock Connect to main ground plane via ferrite bead for isolation of digital switching noise VCCPLL3 Power for Graphics Controller PLL3 LCD Clock 1 5V 5 connected via ferrite bead for isolation of digital switching noise GNDPLL3 Ground for Graphics Controller PLL3 LCD Clock Connect to main ground plane via ferrite bead for isolation of digital switching noise 79 8399 N B Maintenance 5 3 VIA 8235 South Bridge 1 V Link Interface CPU Interface Signal Name Signal Description Signal Name Pin v Signal Description VD 7 0 see pin IO Data Bus These pins are also used to send strap information to 20 026 OD A20 Mask Connect to A20 mask input of the CPU to control list the chipset north address bit 20 generation bridge
168. bly 1 Carefully align the arrowhead corner of the CPU with the beveled corner of the socket then insert CPU pins into the holes Place the lever back to the horizontal position and push the lever to the left 2 Reconnect the fan s power cord to the system board fit the heatsink onto the top of the CPU and secure with five screws 3 Replace the battery pack See section 2 2 1 reassembly 53 8399 N B Maintenance 2 2 4 HDD Module Disassembly 1 Carefully put the notebook upside down Remove the battery pack Refer to section 2 2 1 Disassembly 2 Remove two screws fastening the HDD module and slightly lift up HDD module Figure 2 7 3 Remove four screws to separate the hard disk drive from the bracket free the hard disk driver Figure 2 8 Figure 2 7 Remove HDD module Figure 2 8 Free the HDD driver Reassembly 1 Attach the bracket to hard disk drive and secure with four screws 2 Slide the HDD module into the compartment and secure with two screws 3 Replace the battery pack Refer to section 2 2 1 reassembly 54 8399 N B Maintenance 2 2 5 CD DVD ROM Drive Disassembly 1 Carefully put the notebook upside down Remove the battery pack Refer to section 2 2 1 Disassembly 2 Remove one screw fastening the CD DVD ROM drive Figure 2 9 3 Insert a small rod such as a straightened paper clip into CD DVD ROM drive s manual eject hole 0 and push firmly to release the tray Then gently pull out the CD DV
169. ce Text function Bresenham line drawing style line function ROP3 256 operation Color expansion Source and destination color keys Transparency mode Window clipping 8 16 and 32 bpp mode acceleration 3 D Hardware Acceleration Features Microsoft DirectX 7 0 and 8 0 compatible OpenGL driver available Floating point setup engine Triangle rate up to 4 5 million triangles per second and Pixel rate up to 400 million pixels per second for 2 texture depth test and alpha blending 8K Texture Cache Microsoft DirectX Texture Compression S3TC Flat and Gouraud shading Hardware back face culling 8399 N B Maintenance 16 bit 32 bit Z test and 2448 Z Stencil test support Z Bias support Stipple Test Line Pattern test Text re Transparence test Alpha test support Edge anti aliasing support Two textures per pass Tremendous Texture Format 16 32 bpp ARGB 1 2 4 8 bpp Luminance 1 2 4 8 bpp Intensity 1 2 4 8 bpp Paletized ARGB YUV 422 420 format Texture sizes up to 2048x2048 High quality texture filter modes Nearest Linear Bi linear Tri linear Anisotropic LOD Bias support Vertex Fog and Fog Talbe Specular Lighting Alpha Blending Bump mapping High quality dithering ROP2 support Internal full 32 bit ARGB format for high rendering quality 8399 N B Maintenance System balance to achieve high performance Advanced System Power Management Power down of SDRAM CKE Independent clock stop control
170. che PU System BIOS Inside 256 KB Flash EPROM Include System BIOS and VGA BIOS OSD OSD Audio Volume Up Down status Brightness status RF Antenna On Off status Display Status Memory OMB on board Expandable up to 1024 Expandable with combination of optional 128 256 512 MB memory 200 pin DDR 333 400 DRAM Memory Module x2 PC 2700 3200 specification ROM Driver 12 7mm Height HDD 2 5 9 5 mm height 40 60 80 GB ATA 100 133 Support Removable for Distributor Display 15 XGA TFT Display Resolution 1024X768 Video Controller Keyboard 19mm key pitch 3 0mm key stroke 307mm length Windows Logo Key x 1 Application Key x 1 Glide pad with 2x buttons and 2 direction scroll button 8399 N B Maintenance 1 2 Hardware Specification 2 Continue to previous page Built in 10 100 M based T LAN One Mini PCI slot and antenna reserved for wireless LAN 8399 N B Maintenance 1 2 Hardware Specification 3 Continue to previous page AC Adapter Universal AC adapter 90W Input 100 240V 50 60Hz AC support power on charge 6 8 cell 2000 2200mAH 3 7V Li ion smart battery Dimensions 335 280 30 335x280x42 max 3 5kg Architecture Microsoft WHQL Designed for Windows XP Dimensions Accessories Power Cord AC Adapter RJ 11 Phone Cable p System Driver CD Title Architecture 128 256 512MB DDR RAM AC Adapter w o Power Cord Battery Notebook Carry Bag 1 3 System Hardware Parts 1 3 1 Proc
171. com POWER ON PERPHERIAL CIRCUIT VREF 9 R435 5 ass ais PWR VDDIN 0805 5003 003 25 5VS 03413 eins 03413 ams AO3418 Uii v F5 4 1 INPUT OUTPUT tH vor vin FUSE 1206 2 3216 1 x J 2 4 14 1206 10100 AMSSIO7 4 4 4 1 can 10 SOT223 C340 1 345 ae C269 ASU n AMERBDODEFT css 80 20 286303107001 100 su Wo 470 0805 0603 SOT89N 470 209 0805 80 20 0805 lt 7 WZ 10 50V 80 20 480 2094 GND GND x7 GND 4 GND ADENEF 1928 DTC144WK BORDA 288202237002 19 SW SVDD3 SW SVDD3 313 1 0402 2 Bose 5402 PWRON 003 19 0 5 0 5 4 DTCi44TKA 288202240001 GND u28 0805 029 ER N svrae He 2 4 SENSE OUT VIN u35 u21 5 1 45 8 AO4403 45V 35 4403
172. d VOCHT VOCHT vec gu 4 VCCHT VCCHT GND 402 10 Cons C660 VCCHT VCCHT GND vec 4 100 0010 VCCHT 0402 10 0805 0402 VONT GND vec VOCHT CiB 1 010 80 20 GND vec A i tov 0402 10 80 20 GND vec VOCHT Ci7 1 010 GND vec VOCHT VECHT GND vec x GND vec 7 lt GND 2 222922229222229229222222922222229222229299222292222222 GND vec 555555555555555555555555555555555555555555555555555555 GND 15 15 E GND GND 15 451 110 26 ND ND 1503 1 012 1504 1 012 ona ona fF fF GND GND GND GND ma co 1 1 cesa cees ona ono 100 0010 100 0010 EN eu 0805 0402 0805 0402 GND ano 10V 80 20 10V of 80 20 oe 80 20 50V 80 20 50 gt 451 110 26 T 42 5VS DDR a o a o Xp E s3aVbACVDD NB E NB AVDD2 BEY 1 5VPLLI o 14 012 0603 5 4 12VLDTA 17 012 12 012 12021 0 7 12027100 4 202 100M Ri9 494122 0603 1 M 38 geo J R24 j09 1 2 0402 C28 4 4 SM 4 4 100 100 En om eur 100 Cea 0805 0805 RPCOMP R25 1 49 91 2 0603 5505 0402 4 NU 506 0202 To 20 80 20 aoe 80 20 19 80 20 0402 19 80 20 1802096 7 Soy 80 20 Sov 80 20 180 10 80 20 180 x lt gt a o Xp E NB
173. d gather capability Three root hubs and six function ports Integrated physical layer transceivers with optional over current detection status on USB inputs Legacy keyboard and PS 2 mouse support Sophisticated PC2001 Compatible Mobile Power Management Supports both ACPI Advanced Configuration and Power Interface and legacy APM power management ACPI v1 0 Compliant APM v1 2 Compliant CPU clock throttling and clock stop control for complete ACPI to state support PCI bus clock run Power Management Enable PME control and PCI CPU clock generator stop control Supports multiple system suspend types power on suspends with flexible CPU PCI bus reset options 8399 N B Maintenance suspend to DRAM and suspend to disk soft off all with hardware automatic wake up Multiple suspend power plane controls and suspend status indicators One idle timer one peripheral timer and one general purpose timer plus 24 32 bit ACPI compliant timer Normal doze sleep suspend and conserve modes Global and local device power control System event monitoring with two event classes Primary and secondary interrupt differentiation for individual channels Dedicated input pins for power and sleep buttons external modem ring indicator and notebook lid open close for system wake up 32 general purpose input ports and 32 output ports Multiple internal and external SMI sources for flexible power management models E
174. d keyboard See sections 2 2 1 and 2 2 2 Disassembly 2 Remove two hinge covers Figure 2 13 3 Carefully put the notebook upside down Remove the two screws fastening the wireless cover Figure 2 14 Figure 2 13 Remove two hinge covers Figure 2 14 Remove the two screws 58 8399 N B Maintenance 4 Disconnect the LCD cable from the system board and detach the antenna Figure 2 15 5 Remove the four screws and put up the LCD assembly then free the LCD assembly Figure 2 16 Figure 2 15 Disconnect the LCD cable Figure 2 16 Free the LCD assembly Reassembly 1 Attach the LCD assembly to the base unit and secure with four screws then fit the antenna 2 Reconnect the one cable to the system board Then replace the wireless cover and secure two screws 3 Replace the two hinge covers 4 Replace the keyboard and battery pack Refer to sections 2 2 2 and 2 2 1 Reassembly 59 8399 N B Maintenance 2 2 9 Inverter Board Disassembly 1 Remove the battery keyboard and LCD assembly Refer to section 2 2 1 2 2 2 and 2 2 8 Disassembly 2 Remove two screws and rubbers on the corners of the LCD panel Figure 2 17 3 Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out Repeat the process until the cover is completely separated from the housing 4 Remove the one screw fastening the inverter board Figure 2 18 F
175. ed nothing happens power indicator does not light up Check following parts and signals Parts Signals PWR VDDIN PFI DVMAIN PLI Notebook connected No Connect AC PL5 to power Either AC adaptor Adaptor or battery PUI LEARNING PD3 ADINP PD5 BATT PD6 Where From Power Source Problem First use AC to power it Yes Please try another known good battery or AC adapter Please replace the Check following parts and signals faulty AC adaptor Parts Signals or Battery PJ2 PR92 PR94 PWR VDDIN 16 97 DVMAIN PL17 44 ADEN 15 PU20 BAT V PR75 PR108 BAT_T PD6 PR109 BAT_C Board level Trouble shooting PR76 85 D 14 88 3 5 101 8 2 No Power 2 When power button is pressed nothing happens power indicator does not light up 8399 N B Maintenance PDS BAV7OLTI 1 4 br 2 PWR VDDIN PD6 BAV7OLTI 1 gt PUI To chapter 8 2 2 07004 PLI PRI 8 SBM1040 DVMAIN TAAVDC 120Z 100M 0 01 3 H 149 DE e 93 55 e 59 PC2 49 148 PD2 PC38 PC39 40 PR4 150 5 PCI52 PR6 l
176. enings USB port 4 Power connector 8399 N B Maintenance 46 2 1 5 Bottom View Wireless Card cover CPU 2 1 6 Top open View LCD Screen Stereo set Keyboard Caps Lock Wireless Card Indicator CD DVD Rom Indicator HDD Indicator Num Lock Caps Lock Scroll Lock Power Button 8399 N B Maintenance 47 8399 N B Maintenance 2 2 System Disassembly The section discusses at length each major component for disassembly reassembly and show corresponding illustrations Use the chart below to determine the disassembly sequence for removing components from the notebook NOTE Before you start to install replace these modules disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power 2 2 1 Battery Pack 2 2 2 Keyboard Modular Components 22 3 CPU 2 2 4 HDD Module 2 2 5 DVD ROM Drive 2 2 6 DDR SDRAM NOTEBOGK 2 2 7 Modem Card 2 2 8 LCD Assembly LCD Assembly Components 2 2 9 Inverter Board 2 2 10 LCD Panel 2 2 11 System Board Base Unit Components 2 2 12 Touch Pad 48 8399 N B Maintenance 2 2 1 Battery Pack Disassembly 1 Carefully put the notebook upside down 2 Remove the four screws then remove the CPU cover Figure 2 1 3 Put up the battery pack then free the battery pack Figure 2 2 Figure 2 1 Remove the four screws Figure 2 2 Remove the ba
177. eral Purpose Input 17 Status on PMIO Rx20 5 CPUMISS GPI18 THRM Y4 I General Purpose Input 18 Rx8C 3 0 AOLGPI GPI20 GPO20 01 I General Purpose Input 20 RxE4 6 1 E5 1 0 ACSDIN2 PMIO 4C 20 1 PCSO 21 21 General Purpose Input 21 RxE4 6 1 E5 2 0 ACSDIN3 PMIO 4C 21 1 PCS1 SLPBTN GPI22 22 R22 I General Purpose Input 22 RxE5 3 1 PMIO 4C 22 GHI 1 GPI23 23 P21 General Purpose Input 23 5 3 1 PMIO 4 23 DPSLP 1 Note Register references above are Device 17 Function 0 unless indicated otherwise Note Default pin function is underlined in the signal name column above Note Input pin status for the above GPI pins 31 0 is also available on PMIO Rx4B 48 31 0 Note See also Power Management I O register Rx50 for input pin change status for GPI16 19 and 24 27 Note See also Power Management I O register Rx52 for SCI SMI select for GPI16 19 and 24 27 Note See also Power Management 1 register Rx4C General purpose input pins 20 31 are shared with OD open drain general Programmable Chip Selects Signal Name Pin Signal Description 0 GPIO20 U1 Programmable Chip Select 0 RxE4 6 1 E5 1 1 ACSDIN2 1 GPIO21 V3 Programmable Chip Select 1 RxE4 6 1 E5 2 1 ACSDIN3 SLPBTN 86 5 3 VIA VT8235CD South Bridge 8 General Purpose Outputs 8399 N B Maintenance
178. essor The AMD Hammer processor family is designed to support performance desktop and workstation applications It provides a high performance HyperTransport link to I O as well as a single 64 bit high performance DDR memory controller Compatible with Existing 32 bit Code Base Including support for SSE SSE2 MMXTM 3DNow TM technology and all legacy x86 instructions Runs existing operating systems and drivers Local APIC on chip 8399 N B Maintenance AMD x86 64 Technology 64 bit x86 instruction set extensions 64 bit integer registers 48 bit virtual addresses 40 bit physical addresses Eight new 64 bit integer registers 16 total Eight new 128 SSE SSE2 registers 16 total Integrated Memory Controller Low latency high bandwidth 72 bit DDR at 100 133 166 and 200MHz HyperTransport Technology to I O Devices Two 8 bit links each support 1600 mega transfers MT per second or 1 6 Gbytes s in each direction Can be configured as single 16 bit link supporting 1600 MT s or 3 2 Gbytes s in each direction 64 Kbyte 2 way Associative ECC Protected L1 Data Cache Two 64 bit operations per cycle 3 cycle latency 64 Kbyte 2 way Associative Parity Protected L1 Instruction Cache With advanced branch prediction 16 way Associative ECC Protected L2 Cache Exclusive cache architecture storage in addition to L1 caches 8399 N B Maintenance 256 KB 512 KB and 1 M
179. ettings must match the physical INTE GPI12 DA connection method GPO12 INTA INTB INTC INTD INTF E4 PCI 510 1 INTA NTB INTC INTD GPO13 PCI 5102 INTB INTC INTD INTE INTG GPI14 PCI Slot3 INTC INTD INTE INTF GPO14 PCI Slot4 INTD INTE INTF INTG INTH GPI15 3 PCISlot5 INTE INTF INTG INTH 15 PCI 5106 INTFZ INTG INTH INTA 5 7 R3 PCI Request These signals connect to the VT8235 Version CE REQ4 P3 from each PCI slot oreach PCI master to request the PCI bus REQ3 D5 use pin R3 as REQS Function 0 RxE4 mustbe set to 1 REQ2 C5 otherwise this pin will function as General Purpose Input 7 1 B6 REQO AS GNT5 GPO7 R2 PCI Grant These signals are driven the VT8235 Version GNT4 R4 CE to grant PCI access to aspecific PCI master To use pin R2 GNT3 E5 as GNT5 Function 0 RxE4 must be set to Lotherwise this pin GNT2 C6 will function as General Purpose Output 7 D6 GNT0 A6 PCIRST PCI Reset This signal is used to reset devices attached to PCI bus PCICLK R23 I PCI Clock This signal provides timing for all transactions on the PCI Bus 7 IO PCI Bus Clock Run This signal indicates whether the PCI clock is or will be stopped high or running low The VT8235 Version CE drives this signal low when the PCI cl
180. frequency Programmable output divider ratios Programmable output rise fall time Programmable output skew Programmable spread percentage for EMI control Watchdog timer technology and RESET output to reset system if system malfunction Programmable watch dog safe frequency Support I2C index read write and block read write operations Uses external 14 318 crystal Support Hyper Transport Technology HTTCLK 48 300mil SSOP 29 8399 N B Maintenance 1 3 5 PC Card Interface Controller ENE CB1410 The ENE CB1410 is a high performance PCI to PC Card controller that supports a single PC Card socket compliant with the 1997 PC Card Standard The ENE CB1410 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers The 1997 PC Card Standard retains the 16 bit PC Card specification defined in PCI Local Bus Specification and defines the new 32 bit PC Card CardBus capable of full 32 bit data transfers at 33 MHz The ENE CB1410 supports both 16 bit and CardBus PC Cards powered at 5 V or 3 3 V as required The ENE CB1410 is compliant with the PCI Local Bus Specification and its PCI interface can act as either a PCI master device or a PCI slave device The PCI bus mastering is initiated during 16 bit PC Card DMA transfers or CardBus PC Card bridging transactions The ENE CB1410 is also compliant with the latest PCI Bus Power Management Interface Specific
181. ge g PCI INTD PCI IRDY4 20 61 AC97 SDOUT AC97_RST R127 R128 AC97_BITCLK MDC SDIN R305 R300 22 105 107 110 R476 R269 LADI0 3 R268 R478 0 MINI LPC AD 0 3 93 16 22 36 PCI TRDY 56 64 PCI PCI PCI DEVSEL 66 68 72 U8 R297 22 MINI PCIRST 26 14 R248 27 MINI PCI CLK 25 U14 CLK GEN 31 R253 22 LPC_48M R255 0 MINI_LPC_CLK 121 1 5950403 By 122 103290000 TOd ININ 128 8 15 CardBus amp Reader Test Error 1 An error occurs when a PC card device is installed PC Card Slot Failure 1 Check if the PCMCIA CARD device is installed properly 2 Confirm PCMCIA card driver is installed ok Yes lt E Try another known good PCMCIA card device Board level Troubleshooting Replace Motherboard Change the faulty mn then end 8399 N B Maintenance Check following parts and signals Parts U20 U26 U14 J502 U27 Signals VCCA VPPA CCLKRUN CAD 0 31 CCBE 0 3 CCLK CIRDY CTRDY CSTOP CDEVSEL CFRAME CPAR CPERR CSERR CGNT CINT CREQ CBLOCK CRST R2 D2 R2 714 R2 A18 CVS 1 2 CCD 1 2 CARD _PCIRST PCI CARD 129 8399 N B Maintenance 8 15 CardBus amp Reader Test Error 2 An error occurs when a PC card device is installed
182. he default value The rising edge of this signal is used to sample all power up strap options In addition HTRST is driven active to reset the K8 CPU PWROK Power OK Driven by South Bridge PWROK output from the power supply PWRGOOD input to the South Bridge SUSST Suspend Status For implementation of the Suspend to DRAM feature Connect to an external pull up to disable TESTIN Test In This pin is used for testing and must be left unconnected or tied high 4 7K U to 2 5V on all board designs BISTIN Built In Self Test In Reserved for test Connect to GND for normal operation DEBUG Debug Reserved for test Connect to ground for normal operation XIN Reference Frequency In 14 31818 MHz INTA PCI Interrupt Output A Connect to the South Bridge GPOUT General Purpose Output GPOO General Purpose Output 78 8399 N B Maintenance 5 2 VIA K8N800 North Bridge 7 Integrated Graphics Power and Ground Signal Name Pin T O Signal Description VCCDAC B2 P DAC Voltage 3 3V 5 connected via ferrite bead for isolation of digital switching noise GNDDAC C3 D4 DAC Ground Connect to main ground plane VCCRGB 4 Power CRT RGB Outputs 3 3V 5 connected ferrite bead for isolation of digital switching noise GNDRGB B4 Connection point for RGB Load Resistors Connect to main ground plane via ferrite
183. hing Resistance 100 for Switch Over temperature auto shutdown output current for VCCOUT 150mA output current for VPPOUT Only 3 3V is required for chip normal operation 12V is not required for 3 3V or 5V Output Break Before Make Switching 16 Pin SSOP Package 1 3 7 97 Audio System VIA VT1617 1617A The VT1617 1617A is a high performance audio codec which complies with the AC 97 revision 2 3 It integrates Sample Rate Converters on all channels and can be adjusted in 1Hz increments This chip supports 96KHz sampling rates high quality 96K Hz S PDIF output stereo digital playback 33 8399 N B Maintenance The 20bit gt A ADCs VT1617 1617A implements stereo recording and white noise removal to ensure the best quality of recording It features 8 channel hardware expansion for flexible 7 1 channel applications It also contains a hardware down mixing feature that allows the end users enjoy 6 channel audio with 2 channel or 4 channel speakers The analog mixer circuitry integrates a stereo enhancement to provide a pleasing 3D surround sound effect for stereo media The 1617 1617 has a built in quality headphone amplifier and a high accuracy PLL for cost saving This codec is designed with aggressive power management to achieve low power consumption when used with a 3 3V analog supply the owner consumption is further reduced AC 97 V2 3 Audio Codec Fully compliant with AC 97 Revision 2 3 High Audio
184. id commands to minimize snoop overhead In addition advanced features are supported such as snoop ahead snoop filtering L1 write back forward to PCI master and L1 write back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization Delay transaction and read caching mechanisms are also implemented for further improvement of overall system performance The VT8235CD V Link Client Controller is a highly integrated PCI LPC controller Its internal bus structure is based on a 66 MHz PCI bus that provides 2x bandwidth compared to previous generation PCI bridge chips The VT8235CD also provides a 533 MB sec bandwidth Host Client V Link interface with V Link PCI and V Link LPC controllers It supports six PCI slots of arbitration and decoding for all integrated functions and LPC bus To provide for the increasing number of multimedia applications the AC97 CODEC 1617 1617 is integrated onto the motherboard A full set of software drivers and utilities are available to allow advanced operating systems such as Windows XP and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE Plug amp Play and Advance configuration and power interface ACPI Following chapters will have more detail description for each individual sub systems and functions 8399 N B Maintenance 1 2 Hardware Specification 1 AMD 62W Dublin 32 bit Hammer 64 bit with uPGA Package L2 Ca
185. igure 2 17 Remove LCD cover Figure 2 18 Remove the one screw 60 8399 N B Maintenance 5 To remove the inverter board on the lower part of the LCD housing disconnect two cables Figure 2 19 Figure 2 19 Remove the inverter board Reassembly 1 Reconnect the two cables Fit the inverter board back into place and secure with one screw 2 Replace the LCD cover and secure with two screws and rubbers 3 Replace the LCD assembly Refer to section 2 2 8 Reassembly 4 Replace the keyboard and battery pack Refer to sections 2 2 2 and 2 2 1 Reassembly 61 8399 N B Maintenance 2 2 10 LCD Panel Disassembly 1 Remove the battery keyboard and LCD assembly Refer to sections 2 2 1 2 2 2 and 2 2 8 Disassembly 2 Remove the LCD cover Refer for two steps 2 3 of section 2 2 9 Disassembly 3 Remove the eight screws fastening the LCD panel and detach the cable Then lift it up Figure 2 20 4 Remove the five screws fastening the LCD brackets Figure 2 21 Figure 2 20 Remove the eight screws Figure 2 21 Remove the five screws and detach the cable 62 8399 N B Maintenance 5 Disconnect the cable and free the LCD panel Figure 2 22 Figure 2 22 Free the LCD panel Reassembly 1 Reconnect the cable then replace the LCD brackets and secure with five screws 2 Fit the LCD panel back into place and secure with eight screws then reconnect the cable to the inve
186. is signal corresponds to CSIFX on the primary IDE connector PDCS3 V23 Primary Slave Chip Select This signal corresponds to CS3FX on the primary IDE connector SDCS1 strap 25 Secondary Master Chip Select This signal corresponds to CS17X on the secondary IDE connector Strap low resistor to ground to enable serial EEPROM interface via the MII bus this disables the EExx pins This pin has an internal pullup to default to serial EEPROM interface via the EExx pins SDCS3 strap AF26 Secondary Slave Chip Select This signal corresponds to CS37X on the secondary IDE connector Strap information is communicated to the north bridge via VD 7 PDA 2 0 W24 Primary Disk Address PDA 2 0 are used to indicate which byte V25 in either the ATA command block or control block is being W23 accessed SDA 2 0 strap 24 Secondary Disk Address SDA 2 0 are used to indicate which AC22 byte in either the ATA command block or control block is being AF24 accessed Strap information is communicated to the north bridge via VD 6 4 PDD 15 0 see pin Primary Disk Data list SDD 15 0 see pin Secondary Disk Data list Serial IRQ Signal Name Pin I O Signal Description SERIRQ AD9 I Serial IRQ This pin has an internal pull up resistor 84 5 3 VIA VT8235CD South Bridge 6 8399 N B Maintenance AC97 Audio Modem Interface Internal Keyboard Controller Signal Name Pin PU Signal
187. l Sync Internally pulled down DVPODE TVDE 1 Digital Video Port 0 Data Enable Internally pulled down DVPODET TVCLKR 4 I Digital Video Port 0 Display Detect If VGA register 3 5 12 5 0 3C5 1A 5 will read 1 if display is connected Tie to GND if not used DVPOCLK TVCLK P3 O Video Port 0 Clock Internally pulled down The terminology ie3C5 nnlg above refers to the VGA iGSequencerl registers at I O port 3C5 index np CRT Interface Signal Name Pin VO Signal Description AR B3 AO Analog Red Red output to CRT monitor AG A3 AO Analog Green Green output to CRT monitor AB A2 AO Analog Blue Blue output to CRT monitor RSET C4 AI CRT Output Reference Resistor Tie to GNDRGB through an external 90 9 1 resistor to control the RGB RAMDAC full scale current HSYNC 1 Horizontal Sync Digital output to CRT monitor VSYNC Bl Vertical Sync Digital output to CRT monitor 75 8399 N B Maintenance 5 2 VIA K8N800 North Bridge 4 Dedicated Digital Video Port 0 TV Encoder Interface Signal Name Pins Signal Description TVD11 DVPODII MI TV Encoder 0 Data TVD10 DVPOD10 M3 TVD9 DVPOD9 M2 To configure DVPO as a TV Out interface port pins TVD8 DVPOD8 L1 DVPOD 6 5 must be strapped high TVD7 DVPOD7 M4 TVD6 DVPOD6 L3 Note One TV Encoder interface is supported through either TVD5 5 12 or GDVPI
188. lity with simultaneous LCD CRT CRT DVI CRT TV LCD TV DVI TV operation capability CRT LCD or TV refresh rates are independently programmable to allow optimum image quality Enables different images on different displays simultaneously for true multitasking Full Media capabilities on all displays Support for CRT resolutions up to 1920x1440 and panel resolutions up to 1600x1200 Automatic panel power sequencing and VESA DPMS CRT power down 8399 N B Maintenance Built in reference voltage generator and monitor sense circuits Serial Bus and DDC Monitor Communications for CRT Plug and Play configuration Video Support High quality 5 tap horizontal and 5 tap vertical scaler up or down for both horizontal and vertical scaling linear interpolation for horizontal and vertical p scaling filtering for horizontal and vertical down scaling Color space conversion Color enhancement contrast hue saturation brightness and gamma correction Color and chroma key support Hardware sub picture blending Bob weave de interlacing mode and advanced de interlacing to improve video quality Video gamma correction PAL NTSC TV output capability using external TV encoder Support CCIR601 standard MPEG 2 1 Video Decoder MPEG 2 hardware slice layer iDCT and motion compensation for full speed DVD playback 2 D Hardware Acceleration Features BitBLT 9bit block transfer functions including alpha blts 8399 N B Maintenan
189. mp GSBSTB for GST 2 0 ABI Status only Provides information from arbiter to master to indicate what it may do Only valid while GGNT is asserted 000 Indicates that previously requested low priority read or flush data is being returned to the master graphics controller 001 Indicates that previously requested high priority read data is being returned to the master 010 Indicates that the master is to provide low priority write data for a previously enqueued write command 011 Indicates that the master is to provide high priority write data for a previously enqueued write command 100 Reserved arbiter must not issue may be defined in the future 101 Reserved arbiter must not issue may be defined in the future 110 Reserved arbiter must not issue may be defined in the future 111 Indicates that the master graphics controller has been given permission to start a bus transaction The master may enqueue AGP requests by asserting PIPE or start a PCI transaction by asserting GFRM ST 2 0 are always outputs from the target North Bridge logic and inputs to the master graphics controller AGP Bus Interface Continued Signal Name Signal Description GSTOP GSTOP 12 for 4x Stop PCI transactions only Asserted by the target to request the master to stop the current transaction Interpreted as active high for AGP 8x GREQ GREQ Y1 Re
190. n the system BIOS runs a series of internal checks on the hardware This power on self test post allows the computer to detect problems as early as the power on stage Error messages of post can alert you to the problems of your computer If an error is detected during these tests you will see an error message displayed on the screen If the error occurs before the display is initialized then the screen cannot display the error message Error codes or system beeps are used to identify a post error that occurs when the screen is not available The value for the diagnostic port is written at the beginning of the test Therefore if the test failed the user can determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI PCI slot 91 8399 N B Maintenance 7 2 Diagnostic Tool for Mini PCI Slot The Mini PCI DOG killer card is a single step debug tool which utilizes Mini PCI interface Type III A and is able to hold a PCI bus cycle so that address data and control bus states on PCI bus can be inspected Especially the tool can help an engineer trace address data bus for BIOS read cycles as soon as power on and debug open or short circuit problems easily Usually this sort of problem will make a PC motherboard fail to boot P N 411906900001 Description PWA MPDOG MINI PCI DOGKELLER CARD Note Order it from MIC TSSC 92 7 3 Error Codes 1 8399 N B Maintenance Following is a list
191. nhanced integrated real time clock RTC with date alarm month alarm and century field Thermal alarm on external temperature sensing circuit I O pad leakage control Plug and Play Controller PCI interrupts steerable to any interrupt channel Steerable interrupts for integrated peripheral controllers USB floppy serial parallel and audio 27 8399 N B Maintenance Microsoft Windows Windows NTTM Windows 2000TM Windows 98TM and plug and play BIOS compliant Built in NAND tree pin scan test capability 0 22um 2 5V low power CMOS process Single chip 27 x 27 mm 1 0 mm ball pitch 487 pin BGA 1 3 4 System Frequency Synthesizer and DDR SDRAM Buffer ICS950403 The ICS950403 is a system clock synthesizer chip for AMD K8 based notebook systems with AMD VIA or Ali chipset This provides all clocks required for such a system The ICS950403 employs a proprietary closed loop design which tightly controls the percentage of spreading over process and temperature variations Serial programming I 2 C interface allows changing functions stop clock programming and frequency selection Output Features 2 Differential pair push pull CPU clocks 3 3 V 8 PCICLK Including 1 free running 3 3 V 3 Selectable PCICLK HTTCLK 3 3V 1 HTTCLK 3 3V 1 48MHz 3 3V fixed 28 8399 N B Maintenance 1 24 48MHz 3 3V 3 REF 3 3V 14 318MHz Features Benefits Programmable output
192. ock is running default on reset and releases it when it stops the PCI clock External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping Connect this pin to ground using a 100 0 resistor if the function is not used Refer to the inPCI Mobile Design Guidelo and applicable VIA North Bridge Design Guide KT400A CLE266 or PAX400 for more details Signal Name Pin I O PU Signal Description MCOL 1 PD Collision Detect From external PHY MCRS 1 PD MII Carrier Sense Asserted external PHY when the media is active MDCK 7 PD Management Data Clock Sent to the external PHY as a timing reference for MDIO MDIO B7 IO PD MII Management Data I O Read from the MDI bit or written to the MDO bit MRXCLK C9 I MII Receive Clock 2 5 or 25 MHz clock recovered by the PHY MRXD 3 0 C7 A8 I MII Receive Data Parallel receive data lines driven by the B8 C8 external PHY synchronous with MRXCLK MRXDV D8 I MII Receive Data Valid MRXERR D10 I MII Receive Error Asserted by the PHY when it detects a data decoding error MTXCLK C10 I Transmit Clock Always active 2 5 or 25 MHz clock supplied by the PHY MTXD 3 0 A9 B9 O PD Transmit Data Parallel transmit data lines B10 synchronized to A10 MTXCLK MTXENA C11 PD Transmit Enable Signals that transmit is active from the MII port to the PHY M
193. of error codes in sequent display on the debug board POST HEX DESCRIPTION 27H RAM Quick Sizing 28H Protected mode entered safely 29H RAM test completed 2AH Protected mode exit successful 2BH Setup Shadow 2CH Going To Initialize Video 2DH Search For Monochrome Adapter 2EH Search For Color Adapter 2FH Signon messages displayed POST HEX DESCRIPTION 10H Some Type Of Long Reset Turn off FASTA20 for POST 12H Signal Power On Reset 13H Initialize the Chipset 14H Search For ISA Bus VGA Adapter 15H Reset Counter Timer 1 16H user register configure through CMOS 17H Size Memory 18H Dispatch To RAM Test 19H checksum the ROM 1AH Reset PIC s 1BH Initialize Video Adapter s 1CH Initialize Video 6845 Regs 1DH Initialize Color Adapter Initialize Monochrome Adapter Test 8237 Page Registers 20H Test Keyboard 21H Test Keyboard Controller 22H Check If CMOS Ram Valid 23H Test Battery Fail amp CMOS X SUM 24H Test the DMA controllers 29H Initialize 8237A Controller 26H Initialize Int Vectors 30H special init of keyboard ctrl Test Keyboard Present 32H Test Keyboard Interrupt 33H Test Keyboard Command Byte 34H TEST Blank and count all RAM 35H Protected mode entered safely 2 36H RAM test complete 37H Protected mode exit successful 3
194. quest Master graphics controller request for use of the for 4x AGP bus GGNT GGNT AA3 Grant Permission is given to the master graphics controller to for 4x use the AGP bus GSERR GSERR 15 for 4x Note The AGP interface pins can be optionally configured as additional interfaces for connecting to external display devices For simplification of the AGP pin description tables above and on the next page that multiplexing is not shown here see isAdditional 12C Interfacesl o and display pin description tables later in this document for more information Note The AGP interface pins can be optionally configured as additional interfaces for connecting to external display devices For simplification of the AGP pin description tables above and on the next page that multiplexing is not shown here see isAdditional I2C Interfacesll and display pin description tables later in this document for more information Note Separate system interrupts are not provided for AGP The AGP connector provides interrupts via PCI bus INTA B Note separate reset is not required for the AGP bus RESET resets both PCI and AGP buses Note Two mechanisms are provided by the AGP bus to enqueue master requests GPIPE to send addresses multiplexed on the AD lines and the SBA port to send addresses unmultiplexed AGP masters implement one or the other or select one at initialization time they are not allowed to change AGP System Error
195. r 4 seconds will force system off at ACPI mode There is no sleep button on this machine 1 4 3 Lid Switch System automatically provides a Keyboard cover state through PS2 to relative application when user closes the Keyboard cover 1 4 4 LED Indicators System has some status LED indicators to display system activity 41 8399 N B Maintenance 1 4 4 1 Three LED Indicators on Display Housing Cover From left to right that indicates AC Power Battery Power and Battery Charger AC Power This LED lights green when AC powers to the notebook and flash on 1 second off 1 second when Suspend to DRAM is active using AC power The LED is off when the notebook is off or powered by batteries Battery Power This LED lights green when Battery powers to the notebook and flash Isecond off 1 second when Suspend to DRAM is active using Battery power The LED is off when the notebook is off or powered by AC power Battery Charge Status During normal operation this LED stays off as long as the battery 15 charged When the battery charge drops to 10 of capacity the LED lights red flashes per 1 second and beeps per 2 second When AC is connected this indicator glows green if the battery pack is fully charged or orange amber if the battery is being charged When battery charging error it will flash orange light 42 8399 N B Maintenance WLAN RF Status Wireless LAN only This LED indicates WLAN RF
196. rm reset System also provides icon LEDs to display system status such as AC Battery Power Battery WIRELESS LAN status CD ROM HDD NUM LOCK CAP LOCK and SCROLL LOCK status It also equipped 6 USB2 0 ports The memory subsystem supports on board Expandable up to 1024 Expandable with combination of optional 128 256 512 MB memory 200 pin DDR 266 333 400 DRAM Memory Module x2 PC 2100 2700 3200 specification The K8N800 chipset is a high performance cost effective and energy efficient solution for the implementation of desktop personal computer systems with 8 16 bit 800 600 400 200MHz HyperTransport CPU host interface based on AMD ClawHammer Processors The K8N800 north bridge supports a high speed 8 bit 83x66 Mhz Quad Data Transfer interconnect V Link to the VT8235 South Bridge These chips also contain a built in bus to bus bridge to allow simultaneous concurrent operations on each bus Five levels double words of post write buffers are included to allow for concurrent CPU and V Link operation For V Link Host operation forty eight levels double words of post write buffers and sixteen levels double words of prefetch buffers are included for concurrent V Link bus and DRAM cache accesses When combined the V Link host Client controllers realize a 8399 N B Maintenance Complete PCI sub system and support enhanced PCI bus commands such as Master Read Line memory Read Multiple and Memory Write Inval
197. rom different vendors Product Features Single Chip 100Base TX 10Base T Physical Layer solution Dual Speed 100 10 Mbps Half And Full Duplex Interface to Ethernet Controller MII Interface to Configuration amp Status Optional Repeater Interface Auto Negotiation 10 100 Full Half Duplex Meet All Applicable IEEE 802 3 10Base T and 100Base Tx Standards On Chip Wave Shaping No External Filters Required Adaptive Equalizer Baseline Wander Correction LED Outputs e 2 Link Status Duplex status Speed Status Collision 48 Pin SSOP Package 8399 N B Maintenance 39 8399 N B Maintenance 1 4 Other Functions 1 4 1 Hot Key Function Keys Combination Fl F2 Fn Fn F4 Fn F5 Fn F6 Fn Fn F8 Fn F9 Fn F10 Fn F11 Fn F12 Wireless lan on off Wireless Lan on gt off Display switch LCD gt CRT gt LCD amp CRT TV out will be not TV present TV gt CRT gt TV amp CRT TV out is connected RN Toggle to enable mute the Battery Low Warning beep sound 40 8399 N B Maintenance 1 4 2 Power on off Suspend Resume Button 1 4 2 1 APM Mode At APM mode Power button is on off system power 1 4 2 2 ACPI Mode At ACPI mode power button behavior was set by windows power management control panel You could set standby or power off to power button function Continue pushing power button ove
198. rror 1 An error occurs when using the computer as TV 1 Check if the TV device 15 installed properly 2 Confirm TV driver 15 installed ok Board level Troubleshooting Check following parts and signals Parts Signals Correct it TV VDD TV DS TV VDDAI 12 DATA VDDA2 DC CLK TV LUMA TV CRMA TV COMP Check if BIOS setup is ok Replace Motherboard TV_PCIRST TVD 0 15 TVHS TVVS TVCLK TVCLKI Re test Correct it 131 8 16 TV Encoder Test Error 2 An error occurs when using the computer as TV 8399 N B Maintenance 3V TV 26 40 57 VDD 18 32 48 59 VDDAI 64 1 TV VDDA2 5 9 13 52 010 6 TVD 0 11 TVVS TVCLK TVCLKI TV DS C7 270P c5 270P 2 PAA 0 PCI_RST R381 0 NN TV_PCIRST V TV_RSET R55 4 64 NWN TV_TE R79 10K A TVD12 RI BAA wk 1 10K TVD13 3 NN 014 R94 10K 2 Av 15 RS9 _10K 9 64 10 TV C66 10P X6 14 318MHZ I C396 27P 132 9 Spare Part List 1 Part Number 221679920001 221679950001 221679950002 221679950003 221679950004 222600020049 22260002031
199. rter board 3 Replace the LCD cover and secure with two screws and rubbers Refer to section 2 2 9 Reassembly 4 Replace the LCD assembly Refer to section 2 2 8 Reassembly 5 Replace the keyboard and battery pack Refer to sections 2 2 2 and 2 2 1 Reassembly 63 8399 N B Maintenance 2 2 11 System Board Disassembly 1 Remove the battery keyboard CPU hard disk drive CD DVD ROM drive DDR SDRAM modem card and LCD assembly Refer to sections 2 2 1 2 2 2 2 2 3 2 2 4 2 2 5 2 2 6 2 2 7 and 2 2 8 Disassembly 2 Remove the four screws Figure 2 23 3 Remove the eleven screws and free the housing Figure 2 24 E a 2 9 ES i Ny amp Figure 2 23 Remove the four screws Figure 2 24 Remove the eleven screws 64 8399 N B Maintenance 4 Remove the three screws and lift up the housing s shielding Figure 2 25 5 Disconnect the speaker s cable and the touch pad s cable Then remove the one screw and four hex nuts Now you can lift up the system board Figure 2 26 Figure 2 25 Remove the three screws Figure 2 26 Free the system board Reassembly 1 Replace the system board into the top cover and secure with one screw and four hex nuts 2 Reconnect the touch pad s cable the speaker s cable 3 Replace the housing s shielding and secure with three screws 4 Replace the housing and secure with fifteen screws 5 Replace the LCD assembly modem card DDR SDRAM
200. s Host Strobe B Output strobe both edges The host may stop HSTROBE to pause output data transfers EIDE Mode Primary Device I O Write Device write strobe UltraDMA Mode Primary Stop Stop transfer Asserted by the host prior to initiation of an UltraDMA burst negated by the host before data is transferred in an UltraDMA burst Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst SDIOW SSTOP EIDE Mode Secondary Device I O Write Device write strobe UltraDMA Mode Secondary Stop Stop transfer Asserted by the host prior to initiation of an UltraDMA burst negated by the host before data is transferred in an UltraDMA burst Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst PDDRQ Primary Device DMA Request Primary channel DMA request SDDRQ Secondary Device DMA Request Secondary channel DMA request UltraDMA 133 100 66 33 Enhanced IDE Interface Continued Signal Name Pin I O Signal Description Y24 Primary Device DMA Acknowledge Primary channel DMA acknowledge SDDACK AD23 O Secondary Device DMA Acknowledge Secondary channel DMA acknowledge 014 AD24 Primary Channel Interrupt Request 015 26 Secondary Channel Interrupt Request PDCS1 V22 Primary Master Chip Select Th
201. s 31 FS3 R253 22 LPC 48M R255 0 MINI LPC CLK 121 122 Mini PCI l Connector C270 C259 22P Y 22P 37 R245 15 CPUCLK C103 3900P CPUCK R132 U6 169 36 R247 15 CPUCLK C107 3900P CPUCK CPU 1 98 8399 N B Maintenance 8 1 Base Work Condition 4 lt gt 4 lt gt System Reset Check 4r lt gt 2 5V 1 POWERBTN gt lt 5 501 0220 a 7 08 V CPU PWROK 2 5V T P2 L ALL PWROK 2 5V gt U6 SVDD3 CPU 4 md ALL PWROK 2 5V CPU 20 pag e 25 KBC_RESET 2 4 1 2 U12 RESET F CTE i 4 C389 5 NB PCIRST amp North lt A GND Bridge SEB 1 gt Plo IMP811 V din 5 PIS V 1 2VPG 2 5V CPU_PCIRST U10 U16 E d Audio R355 P20 Power o 220 V Codec KBC E Module PWROK SB Controller 16 Jis W83L950D V AC97_RST 25 ww Connector 22 5058 926 SUSB a 4 re 4 U20 Pia 8 RSMRST 020 gt RSMRST South CARD_PCIRST 20 66 U26 ae PCMCIA Bridge 7 KBC_SB_PWRBTN gt SB_PWRBTN 8 Controller 3V USA 15 V ae PCI_RST
202. s for CPU DDR SDRAM VLINK interface graphics engine 20 3 video display and on chip AGP bus Suspend power plane for preservation of memory data Suspend to DRAM and self refresh power down Low leakage I O pads ACPI 1 0B and PCI Bus Power Management 1 1 compliant Full Software Support Drivers for major operating system and APIs windows 9x Windows NT Windows2000 Windows XP Direct3D DirectDraw and DirectShow OpenGL ICD for Windows 9x NT 2000 and XP Chipset and Video BIOS support including all standard VESZA CRT display modes 1 3 3 VIA VT8235CD BGA PCI LPC ISA South Bridge The VT8235CD South Bridge is a high integration high performance power efficient and high compatibility device that supports Intel and non Intel based processor to V Link bus bridge functionality to make a complete Microsoft PC2001 compliant PCI LPC system The VT8235CD includes standard intelligent peripheral controllers 8399 N B Maintenance IEEE 802 3 compliant 10 100 Mbps PCI bus master Ethernet MAC with standard MII interface to external PHY ceiver Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands Dedicated FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices In addition to standard PIO and DMA mode operation the VT8235CD also supports the UltraDMA 133 100 66 and
203. shown after Mini PCI device is installed or the Mini PCI device does t work Mini PCI Test Error 1 Please check if the Mini PCI device is installed properly Board level 2 Confirm Mini PCI device driver is Troubleshooting installed ok Parts Signals PCI AD 0 31 Yes 014 PCI 0 3 122 Please replace Motherboard Q10 PCI INTC U8 PCI 2 R248 SERIRQ R255 LDRQO R297 AC97_SYNC R348 PCI PERRA R267 PCI REQI R127 CLKRUN R128 PCI SERR R300 PCI INTD R305 PCI IRDY Please try another known good Mini PCI device Please change the faulty part then end R268 AC97 SDOUT R476 AC97_RST R478 Check following parts and signals AC97_BITCLK MDC_SDIN LAD O 3 PCI PAR PCI TRDY PCI FRAMEZ PCI STOP PCI DEVSEL MINI PCIRST MINI PCI CLK MINI LPC CLK 127 8399 N B Maintenance 8 14 Mini PCI Test Error 2 An error message is shown after Mini PCI device is installed or the Mini PCI device does t work R339 45V 330 ur Q10 43V asy 2 DTCIA4TKA t 123 97 C89 0 10 54 V PCI AD 0 31 PCI AD21 R120 100 48 PD 13 98 PCI_INTC 17 emm QUY PCI GNT2 amp 30 SERIRQ MINI PCI SERIRQ LDRQO R348 R267 0 MINI_LPC_LDRQ 21 112 020 AC97 SYNC PCI PERR amp 29 65 PCI REQ14 CLKRUN PCI_SERR 67 71 103 1_ 0 3 86 73 59 45 South Brid
204. splay 2 Connect the yo device to the OK M B one at a time to find out which part is causing the problem 106 8399 N B Maintenance 8 4 No Display 2 There is no display on both LCD and monitor after power on although the LCD and monitor is known good RP7 RP12 53 70 79 95 1 8 81 86 LVDS D 0 23 2224 FPD 00 23 30 40 48 87 LVDS R182 22 NB 12 68 88 LVDS CLKIN R179 22 NB_FPCLK PLLVCC 1015 75 LVDS HSYNC R199 22 NB_FPHS 74 LVDS VSYNC R198 22 NB FPVS 76 LVDS DE R193 22 NB FPDE 4 Pl m R197 67 3 0 4 LV A 0 2 63 65 LV 72 Q2 U12 44 TXOUT2 5 1 2 A03400 R141 47K LV_PD 2 U9 1 f 45 TXOUT2 7 I R142 47K LV INTR 21 c42 C2 c2 0 1U North mi E mem 46 TXOUTI 11 1000P 1000P 0 1U Bridge T TXOUTI 5 4 470K LVDS 49 TXOUTO 12 Encoder 1 5V 50 TXOUTO 14 12 gt DTCI44TKA 9 R102 0 R188 10K LVDS_VREF 78 ENAVDD 41 TXCLK 6 J8 1 5 R190 42 TXCLK 8 3V 10K Di R434 R433 BAWS6 10K z 10K ENPBLTNB XX ENPBLT RP3 gt R124 0 3 Q3 SVDD3 43V IK 4 9 DTC144TKA Q 2 RP53 e 20 R432 10K ed R415 4 7K LV DSEL 61 0 U16 5
205. st Error 1 Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk Hard Driver Test Error Check the BIOS setup 2 Replace another good hard driver try again Board level Troubleshooting Check following parts and signals Parts Signals U20 HDD PDD 0 15 14 HDD _PDCS 1 3 PR61 HDD PDA 0 2 Replace 62 HDD_PDDACK RP59 Motherboar HDD 16014 otherboard nage HDD_PDIOW HDD_PDDREQ R327 HDD PIORDY 8331 HDD PDAI Q32 HDD PDIOR Z R325 R320 08 IDERST 116 8399 N B Maintenance 8 9 Hard Disk Driver Test Error 2 Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk 45V 41 42 1 C5 254 43V 0 10 R325 R320 V PR61 PR62 10K 4 7K IDE PDD 0 15 oe HDD_PDD 0 15 3 18 RP59 IDE PDCS 1 3 4 0 8 HDD PDCS 1 3 3738 PDA 02 HDD PDA 0 2 3536 V ps IDE HDD 30 IDE IRQ14 HDD 16014 32 IDE PDIOW amp NN HDD_PDIOW 24 IDE_PDDREQ HDD_PDDREQ 22 R226 10K South Bridge RP58 IDE PIORDY 0 4 HDD PIORDY 28 VT8235 Ne e IDE PDAI AA HDD PDAI 34 IDE PDIOR AN HDD_PDIOR 26 3V 3V 5V 3V R327 R331 10K 10K 22 PCI RST 7 08 V IDE_PCIRST IDERST 2 032 DTCIA44TKA 27 R229 470
206. sted write buffers Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities Enhanced PCI command optimization MRL MRM MWI etc Four lines of post write buffers from PCI masters to DRAM Sixteen levels double words of prefetch buffers from DRAM for access by PCI masters Delay transaction from PCI master accessing DRAM Transaction timer for fair arbitration between PCI masters granularity of two PCI clocks Symmetric arbitration between Host PCI bus for optimized system performance Complete steerable PCI interrupts 23 8399 N B Maintenance 2 2 compliant 32 bit 3 3V PCI interface with 5V tolerant inputs Fast Ethernet Controller High performance PCI master interface with scatter gather and bursting capability Standard MII interface to external PHYceiver 1 10 100 MHz full and half duplex operation Independent 2K byte FIFOs for receive and transmit Flexible dynamically loadable EEPROM algorithm Physical Broadcast and Multicast address filtering using hashing function Magic packet and wake on address filtering Software controllable power down UltraDMA 133 100 66 33 Master Mode EIDE Controller Dual channel master mode hard disk controller supporting four Enhanced devices Transfer rate up to 133MB sec to cover PIO mode 4 multi word DMA mode 2 drives and UltraDMA 133 interface Increased reliability using Ultr
207. t PRS mE DID Bzvsscaav 0 10 0 1U 1000 470K 1000P 1000 0010 4 7K gt PR75 C n V e oeo 100K PJO3 PJO4 SPARKGAP 6 V V V PR3 PR82 100K 226K PQIS n 04407 P23 pug 415 76 I LIMIT OUT F MU P 44 I 16 MAX4073FEUT T 59 SUE d 1U 33K U16 V PQI4 KKH 14 ADEN 2111002 Controller PQI7 V PQI DTCI44WK 23 LEARNING BATT 102 8 2 Power 3 When power button is pressed happens power indicator does not light up 8399 N B Maintenance PD6 m BAV7OLTI D PWR VDDIN 15 PR75 4 0407 100K P 1 TR SFT 10A PLIT 7 2 DVMAIN 120Z 100M birmi 2 op 1 PLI6 L Al PCI29 120Z 100M 0 1U PR76 33K PQ14 L PCI25 2N7002 7 z ian ADEN 14 eet 16 PR88 4 99K V V PJ2 5 PR92 4SVDD3 a i ji PR9 130 z 20K 0 1U A A D BAV7OLTI 2 RP44 U16 2 33 4 VOLT 5 78 _ _ 77 S PRAA A 0 BAT_D BAT_DATA 3 KBC PROT 0 BAT_C BAT_CLK 2 Controller V c301_L 2 T ou SVDD3 BATTI 2 m s V pciza
208. t capability and dynamic stop for minimum power consumption Parity checking to insure correct data transfers 7 8399 N B Maintenance Integrated Peripheral Controllers 4 Integrated Fast Ethernet Controller with 1 10 100 Mbit capability Integrated USB 2 0 Controller with three root hubs and six function ports Dual channel UltraDMA 133 100 66 33 master mode EIDE controller AC link interface for AC 97 audio codec and modem codec HSP modem support Integrated DirectSound compatible digital audio controller LPC interface for Low Pin Count interface to Super I O or ROM Integrated Legacy Functions Integrated Keyboard Controller with PS2 mouse support Integrated DS12885 style Real Time Clock with extended 256 byte CMOS RAM and Day Month Alarm for ACPI Integrated DMA timer and interrupt controller Serial IRQ for docking and non docking applications Fast reset and Gate A20 operation Concurrent PCI Bus Controller 33 MHz operation 22 8399 N B Maintenance Supports up to six PCI masters Peer concurrency Concurrent multiple PCI master transactions i e allow PCI masters from both PCI buses active at the same time Zero wait state PCI master and slave burst transfer rate PCI to system memory data streaming up to 132Mbyte sec data sent to north bridge via high speed V Link Interface PCI master snoop ahead and snoop filtering Eight DW of CPU to PCI po
209. t implementation details 76 8399 N B Maintenance 5 2 VIA K8N800 North Bridge 5 AGP Multiplexed Digital Video Port 1 GDVP1 TV Encoder 24 Bit Dual 12 Bit Flat Panel Display Interface Signal Name AGP Name Pin T O Signal Description Signal Name Pin I O Signal Description GTVD11 GDVP1D11 GC BE3 O GTVD10 GDVP1D10 GD26 GTVD9 GDVP1D9 GD24 AF6 GTVD8 GDVP1D8 GD30 AE4 GTVD7 GDVP1D7 GD28 5 GTVD6 GDVPID6 GD29 GTVDS GDVPIDS GSBA4 AF2 GTVD4 GDVP1D4 GD27 ADS GTVD3 GDVPID3 GSBAS AD3 GTVD2 GDVPID2 GSBSTBS AEI GTVD1 GDVPIDI GSBSTBF GTVD0 GDVP1D0 GSBA2 ADI GDVP1HS GSBA3 AD2 O Horizontal Sync Internally pulled down GTVVS GDVP1VS GSBAO O Vertical Sync Internally pulled down GTVDE GDVPIDE GSBAI O Display Enable Internally pulled down GTVCLKR GD31 AD4 1 Clock In Input from TV encoder Internally GDVPIDET pulled down GTVCLK GSBA6 AE3 O Clock Out Output to TV encoder Internally GDVPICLK pulled down GTVCLK GSBA7 AF3 O Clock Out Complement Output to TV GDVP1CLK encoder Internally pulled down The above pins may be connected to an external TV Encoder chip such as a VIA VT1623 or VT1623M for driving a TV set T O pads for the pins on this page are powered by 15 1 5 I O Flat Panel Power
210. th read and write transactions For PCI cycles asserted when the target 15 ready for data transfer Device Select PCI transactions only This signal is driven by the North Bridge when a PCI initiator is attempting to access main memory It is an input when the chip is acting as PCI initiator Not used for AGP cycles Interpreted as active high for AGP 8x 73 8399 N B Maintenance 5 2 VIA K8N800 North Bridge 2 AGP Bus Interface Continued Signal Name Pin Signal Description AGP8XDT Y2 I AGP 8x Transfer Mode Detect Low indicates that the external graphics card can support 8x transfer mode GRBF GRBF AD6 I Read Buffer Full Indicates if the master graphics controller for 4x is ready to accept previously requested low priority read data When is asserted the North Bridge will not return low priority read data to the graphics controller ACI I Write Buffer Full for 4x GSBA 7 0 see pin I Side Band Address Provides an additional bus to pass address GSBA 7 0 for list and command information from the master graphics controller 4x to the target North Bridge These pins are ignored until enabled GSBSTBF GSB I Side Band Strobe Driven by the master to provide timing for STB for 4x AEI GSBA 7 0 8x mode uses GSBSTBF iBFirstlr strobe and GSBSTBS GSBS GSBSTBS iBSecondl strobe These signals are interpreted as TB for 4x GSBSTB a
211. ttery pack Reassembly 1 Replace the battery pack into the compartment The battery pack should be correctly connected when you hear a clicking sound 2 Replace the CPU cover and secure the four screws 49 8399 N B Maintenance 2 2 2 Keyboard Disassembly 1 Remove the battery pack Refer to section 2 2 1 Disassembly 2 Open the top cover 3 Loosen the five latches locking the keyboard Figure 2 3 Figure 2 3 Loosen the five latches 50 8399 N B Maintenance 4 Slightly lift up the keyboard and disconnect the cable from the mother board then separate the keyboard Figure 2 4 Figure 2 4 Lift up the keyboard and disconnect the cable Reassembly 1 Reconnect the keyboard cable and fit the keyboard back 2 Replace the keyboard into place and fasten the five latches 3 Replace the battery pack Refer to section 2 2 1 reassembly 51 8399 N B Maintenance 2 2 3 CPU Disassembly 1 Remove the battery pack Refer to section 2 2 1 Disassembly 2 Disconnect the fan s power cord from system board and remove five screws that secure the heatsink upon the CPU Then free the heatsink Figure 2 5 3 To remove the existing CPU lift the socket arm up to the vertical position Figure 2 6 Figure 2 5 Free the heatsink Figure 2 6 Disconnect the cable 52 8399 N B Maintenance Reassem
212. ut state for each of the above general purpose outputs is selectable via Power Management registers 4 48 Note Default pin functions are underlined in the table above Power Management and Event Detection 23 23 P21 DPSLP General Purpose Output 23 RxE5 3 1 PMIO 4C 23 1 GPO26 GPD6 ADI OD SMBDT2 VSUS33f General Purpose Output 26 Rx95 2 1 95 3 1 Signal Name Pin Signal Description PWRBTN I Power Button Used by the Power Management subsystem to monitor an external system on off button or switch Internal logic powered by VSUS33 SLPBTN I Sleep Button Used by the Power Management subsystem GPIO21 to monitor an external sleepbutton or switch RxE4 6 1 ACSDIN3 80 6 1 E5 2 0 and PMIO Rx4C 21 1 PCS1 RSMRST I Resume Reset Resets the internal logic connected to the VSUS33 power plane and also resets portions of the internal RTC logic Internal logic powered by VBAT EXTSME 100 External System Management Interrupt When enabled GPD to allow it a falling edge on this input causes SMI to be generated to the CPU to enter SMI mode 10K PU to VSUS33 if not used 3 3V only PME I Power Management Event 10K PU to VSUS33 if not used SMBALRT I SMB Alert When programmed to allow it SMB Rx8 3 1 assertion generates an IRQ SMI or power management event 10K PU to VSUS33 if not used GPO2
213. v 2 1608 25MHZ o 132 012 4 1 1 1202 100 1 1 R98 C51 L3 1 22 ces 01U 1 1 77 5 4 1 0402 0402 0402 0402 0402 GND 45 ca 1 ces 10 4 4 4 10 10 35 6 45VS 22P 0402 22 407 caos I 409 T V 0603 0603 010 23 5 0402 0402 0402 10 10 10 eb C422 C423 WZ 5 010 04U 0402 0402 10 4 10 4 NA E E GND PLL a ig Sec soure 291000010410 cs L CLOSE TO n 43V 45V 1 21808 J15 9 i ay ust 3 MONO OUT 1 9343 0402 51 i 14 a usc P 5 1 Bein c2 SHORT SMT4 PIK 1 Te 5 E 8 Hx 1 _1808 1 1000P Te i C353 1 25 8 4 1808 TP 1 il 33 6 3 1 gt ACES 9 3 8342 47K 0404 0402 85205 0400 10 RING MDC RING 16 1 80 20 RING 1 1 1 5 63 MINISMDC110 NA 1 19 8 0 1 GND CLOSE TO MDC____ GND1 1 1 AC97 SYNC 85 GND1 97_5 91518 71 Raa 1 22 0404 MDC SDIN 1 9 1518 AC97_SDOUT MDC SDIN 915 97 RST 5 G 8336 1 22 040 RJ45 8P RJ11 4P 2 i 9 1470120 2 2 0 T m 8334 1 22 AC97 BITOLK 5 gt TP 1 GND 45 GND MDC 4 4 3 1473293 0 CLOSE Sec soure 291000810819
214. ytes Intelligent request reordering for maximum AGP bus utilization Supports Flush Fence commands Graphics Address Relocation Table GART 8399 N B Maintenance One level TLB structure Sixteen entry fully associative page table LRU replacement scheme Independent GART lookup control for host AGP PCI master accesses Windows 95 OSR 2 VXD and integrated Windows 98 2000 XP mini port driver support High Bandwidth 533 MB Sec 8 bit V Link Host Controller South Bridge Interface Supports 66 MHz V Link Host interface with total bandwidth of 533 MB sec Operates in 2 4 and 8x modes Full duplex commands with separate command strobe for 4x 2x mode half duplex for 8x mode Request Data split transaction Configurable outstanding transaction queue for Host to V Link Client accesses Supports Defer Defer Reply transactions Transaction assurance for V Link Host to Client access eliminates V Link Host Client Retry cycles Intelligent V Link transaction protocol to eliminate data wait state throttle transfer Latency V Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size to avoid data overflow Highly efficient V Link arbitration with minimum overhead 8399 N B Maintenance All V Link transactions have predictable cycle length with known command data duration Integrated Graphics Video Accelerator Optimized Share Memory Architecture SMA 16 32 64

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