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Intel SDS2 User's Manual

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1. 4 65 Table 48 Boot Device Priority 65 Table49 ards Dive Selections oes et attt ted etae oe ome de 66 Table 50 Removable Drive 66 51 2 Menu Selects 66 Table 52 24 Pin Main Power Connector 74 Table 53 8 Pin 12 V Power Connector 74 Table 54 Aux Signal Connector 74 Table 55 DIMM Connector coe ri eee oborta ePi poeticae ode ee 75 Table 56 IGMB Connector PI oUL coe tee tus Seb Cen aot race tmp 76 Table 57 IPMB Connector ea tence cendo 76 Table 58 Connector PIT ol s sciet edo ente ae arra E neto 76 Table 59 HSBP B Connector RR ene eate uit 77 Table 60 Front Panel 34 Pin Header 77 Table 51 932 bit5 V POLSIOEPIBSOLE Rei Ret or RD SEE 78 Table 62 64 bit 3 3V PCI Slot Pil OlE b eth a ea e 78 Table 53 VGA Connector PIB OL Rd mM 80 Table 64 69 pir SCSI Connector sss scare ena eee els oa qp ttt 80 Table 85 Bj d5COnBeelorPIr oui eiii pita t ERO
2. A N e we NIETS 275 aS ats e Te PORT ZCR Present Figure 5 SDS2 PCI Interrupt Mapping Diagram 24 Order Number A85874 002 Intel Server Board SDS2 PCI IRQ 10 PCI IRQ 9 PCI IRQ 8 PCI IRQ 7 PCI IRQ 6 PCI IRQ 5 PCI IRQ 13 PCI IRQ 11 PCI IRQ 12 PCI IRQ 2 PCI IRQ 3 PCI IRQ 4 PCI IRQ 0 PCI IRQ 1 Revision 1 2 Intel Server Board SDS2 Server Management 5 Server Management The SDS2 server management features are implemented using the Sahalee Server Board Management Controller chip The Sahalee BMC is an ASIC packaged in a 156 pin BGA that contains a 32 bit RISC processor core and associated peripherals The following diagram illustrates the SDS2 server management architecture A description of the hardware architecture follows Revision 1 2 25 Order Number A85874 002 Server Management Intel Server Board SDS2 Speaker a 4 I c 5 L 9 o Identify LED Power LED a E Bl 5 c Chassis Intrusion a 4 ES U lt x 2 Drive Activity Fault LED c 5 a gt 2 5 2 gt a 8 5 a 9 U gt 2 c Front Panel Connectors LL Pb 6 PROCESSOR SOCKETS IERR 2
3. 111 9 Extended RAM Step disable option in BIOS Setup has no 112 10 High resolution video modes do not work 2 112 11 Lower performance with CAS Latency 2 113 12 5052 reboots during POST with 4GB or more of total system memory installed 113 13 Novell NetWare v 6 0 does not install on 052 114 14 Adaptec 2100S RAID controller causes system lockup and video blanking 114 15 5052 Build Your Own BYO Platform Confidence Test PCT v 1 00 fails on the first run 115 16 5052 0 71 System Temperature out of the range POST message 115 17 5052 0 75 System Voltage out of the range POST 116 18 Miscellaneous numeric keys entered during POST enable PXE 116 19 5052 board level operating temperature and power supply voltage tolerance MOOI CANON EE 117 20 Recommendation for 5052 rubber bumper installation 117 21 Keyboard and Mouse do not function under Microsoft Windows 2000 when legacy 119 22 Data miscompares when using Seagate ATA III model ST310215A hard drives 120 23 Boot to ser
4. 5965 OEM Connector 5VSB In addition to the public IPMB the Sahalee BMC also has five private busses Four of these are used on the Server Board The Sahalee BMC is the only master on the private busses The following table lists all Server Board connections to the Sahalee BMC private busses Table 18 Private Bus 1 Devices Posee sve NA SES Table 19 Private Bus 2 Devices union Voltage Nos mm E SOS Gomer O od y OS ow Power Supp aS FRU sve o PowrUntcag odo Note The power supply entries in Table 19 apply only to the Intel SC5100 chassis Reference chassis power supplies may utilize different addresses Table 20 Private Bus 3 Devices Voltage Address HE SL 0 0 North Bridge 20 0 4 Bridge Revision 1 2 31 Order Number A85874 002 Server Management Intel Server Board SDS2 Vonage or EX poe E om fev fom S oma sav fos oms fev ome fev Table 21 Private Bus 4 Devices Vouge Address 1 3VSB 5 4 Error Reporting This section documents the types o
5. Core Temp Aux IPMB Connector Hot swap Backplane Header CPU Voltage 1 empl ME Transceiver Header RI Wake on Ring Chip Set ii INTELLIGENT PLAT d Logic 2 5V BBD COM2 Private Management Busses i i FANs 6 Power 5 E Intrusion Distributio e 5 FORM MANA EMENT BUS IPMB Board H R 12V Power Connector Non volatile read write storage 3 3V SYSTEM SENSOR FRU INFO EVENT DATA amp CONFIG LOG RECORDS DEFAULTS 12 BASEBOARD MANAGEMENT CONT ROLLER BMC 1 25V 3 3V Standby CODE RAM Chassis ID LVDS A Term System I F updateable Baseboard ID PORTS Power State LVDS A Term 2 LVDS A T o 3 Platform LVDS B Term BIOS VF System Management LVDS B Term 2 i 1 Bus Interrupt Term Chip set SMI Routing MI Figure 6 SDS2 Sahalee BMC Block Diagram View as Reference Only 26 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 5 1 The Sahalee BMC contains a 32 bit RISC processor core and associated peripherals used to Sahalee Baseboard Management Controller Server Management monitor the system for critical events The Sahalee BMC packaged in a 156 pin BGA monitors all power supplies including those generated by the external power suppl
6. Order Number A85874 002 Connections 79 Connections Intel Server Board SDS2 Pm sea Pn Side 8 6 I O Connectors 8 6 1 VGA Connector The video connector interface is a standard VGA compatible 15 pin connector An ATI RAGE XL video controller with 4 MB of on board video memory supplies video The following table details the pin out of the VGA connector Table 63 VGA Connector Pin out GND 7 GND 10 GND 11 N C 12 DDCDAT 13 HSYNC horizontal sync 14 VSYNC vertical sync 15 DDCCLK 8 6 2 SCSI Connector The SDS2 Server Board provides two SCSI connectors accessible internally The following table details the pin out of the 68 pin SCSI connector Table 64 68 pin SCSI Connector Pin out Connector Contact Number Signal Name Signal Name Connector Contact Number 0802 vers 80 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Connections LONE pp PEME TN e 7 7 Bo C _ oem DB 4 Een 080 PRESERVED 51 PRESERVED 4 GROUNDS ieee ROUND See gt 7 Pe o _ __ _ ee Zo fee ee p M LEN LONE 28 8 6 3 NIC Connectors The SDS2 Server Board supports two RJ 45 connectors The following table details the pin out of these c
7. Mea b oe 80 MER ICE o aues PN T naan 80 9 5 2 i as 80 8 6 3 NIC Connector aces tod d ba 81 8 0 4 gt ad sin nd b nie ters Sia uter setae 82 8 6 5 Universal Serial Bus USB 82 8 6 6 Floppy audaci een rad 83 Db Serial 84 8 6 8 Paralel PO 85 8 6 9 Keyboard and Mouse 0 0 0 0 85 8 72 MISCCIANEOUS re de Sede 86 8 7 1 6 5 86 S2 AS MAS SIS MUN 86 8 7 3 External SCSI Activity LED Input Signal Connector 2 86 98 Rear UO Panel pp ner e SU EE 87 MO Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Table of Contents 8 9 Connector Manufacturers Part Numbers sse 87 MEDI ree S 88 9 System Configuration JUIN DONS uere be itt duod I d 88 9 2 Performing CMOS Clear BIOS Recovery and
8. s Power Faut LED Anods 3 HDD Rciviy LED Gathode Revision 1 2 77 Order Number A85874 002 Connections Intel Server Board SDS2 8 5 PCI Slot Connector The Server Board support two 32 bit 33 MHz 5V PCI Slots and four 64 bit 66 MHz 3 3 V PCI Slots The tables below define their pin outs 78 Table 61 32 bit 5 V PCI Slot Pin out sea Ses sr asy Rev so Penne ADI Grou Comecir Fay Conector Key CBE E 75 OA LEES 5740 Lane 50 scrser Roba Ground 14 15 16 17 18 19 20 21 22 23 4 24 26 2 oj ala Table 62 64 bit 3 3V PCI Slot Pin out Pn sea Side A Order Number A85874 002 Revision 1 2 Intel Server Board SDS2 Revision 1 2 Pm sea Pn Side e pv s mr sv 56 905 e PRSNTIF Rev 57 Ground Af 9000 12 ConnestorKey ConneciorKey 60 REGS ase __ pe ek ev REGE an a 6 oeae 83 22 Gui anes 68 2064 2964 aen Ao Ground 34 Gud FRAME 40_ PERRF SMBUSGLK Abeo Ground pav em Ao
9. 10 2 5 PCIIRQ11 pee Eum gt PCIIRQI6 P PCI Cvele PCIIRQ17 P IRQ PCIIRQ18 lt MAPPING PCIIRQ19 SCAN PCIIRQ20 PCIIRQ16 E MASK for PCIIRQ21 PCIIRQ31 gt PCIIRQ16 31 PCIIRQ22 PCIIRQ23 PCIIRQ24 P PCIIRQ25 PCIIRQ26 pb 4 Figure 3 5052 Interrupt Routing Diagram CSB5 Internal 22 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Subsystem Super I O Timer Cascade Serial 2 15 Serial Portt ISA 0 ISA ad Floppy ISA ISA SCI ISA ISA ISA ad Mouse ISA Coprocessor Error P IDE SA PCI Clock S 33 MHz SERIRQ o 21 D D 5 pje E SCSI Ch A PCIIRQO SCSI Ch B PCIIRQ1 NIC 1 PCIIRQ2 NIC 2 PCIIRQ3 Video PCIIRQ4 Slot INFA PCIIRQ5 Slot2 INTA PCIIRQ6 Slot3 INTA PCIIRQ7 Slot4 INTA PCIIRQ8 1015 INTA PCIIRQ9 Slot6 INTA PCIIRQ10 INTBCD PCIIRQ11 PIRQ LATCH INTBCD PCIIRQ12 INTBCD PCIIRQ13 N C PCIIRQ14 SCI from SIO PCIIRQ15 o 00 5 mp D 75 ents D 5 PIRQ1 Jezi e498 19 Figure 4 5052 Interrupt Routing Diagram Revision 1 2 23 Order Number A85874 002 Subsystem Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 m LA j O
10. ep Horst Bs pin system configuration soting header 9 Jumpers 9 1 System Configuration Jumpers This section describes jumper options on the Server Board Jumper headers provide various configuration options as shown in the figure below All jumper headers except the Chassis Intrusion header CN50 are located near the front of the board between the coin cell battery socket and the IDE connector The Chassis Intrusion header is located near the back corner of the board next to the PCI Slot 6 connector 88 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Jumpers DEFAULT FUNCTION CN48 DEFAULT FUNCTION OPEN CLOSED CMOS Clear OPEN CLOSED FRB3 Timer Disable OPEN CLOSED Password Disable OPEN CLOSED RSV CN49 DEFAULT FUNCTION OPEN CLOSED RSV OPEN CLOSED BMC Force Update OPEN CLOSED BIOS Recovery CLOSED SPARE JUMPER CN50 DEFAULT FUNCTION CABLED CLOSED Chassis Instrusion Disable CN45 DEFAULT FUNCTION OPEN CLOSED RSV CN59 DEFAULT FUNCTION OPEN CPU Frequency Select CN46 DEFAULT FUNCTION OPEN CPU Frequency Select OPEN OPEN Protects BIOS boot block OPEN CPU Frequency Select OPEN CPU Frequency Select CN47 DEFAULT FUNCTION OPEN CLOSED RSV OPEN OPEN Protects BMC boot block OPEN CLOSED RSV Figure 11 SDS2 Configuration Jumpers Note CN59 CPU Frequency Select jumper header pins are not installed on production FAB4
11. 2 4 40 4 00000 000 105 12 2 6 Installation Precautions 105 12 2 7 External ICMB Cable Information Rear eril eae ettet cias 105 13 ZEB 106 13 1 Saura Erata ae im rero o 106 MBA sere usare Cols Gore be eot os OPI etu tube ttis 108 1 Intel RAID controller SRCMR not yet supported with Intel Server Board SDS2 108 2 Intel amp Server Board SDS2 BIOS update utility does not allow updates from a PXE Server or from network drives 2 108 3 Intel Server Board SDS2 FRU SDR update fails with console redirection enabled in BOS E 108 4 First characters and arrow keys not echoed with console redirection 109 Revision 1 200000 Mii Order Number A85874 002 Table of Contents Intel Server Board SDS2 5 Intel amp ICP Vortex RAID Controllers will cause the Intel Server Board SDS2 to halt during POST when the BIOS Logo screen is 109 6 Intel Server Board 5052 CD ROM trenere 110 T NIC driver set 5 12 v 2 3 15 for UnixWare 7 1 1 drops DPC LAN connection 111 8 NIC driver set 5 12 v 5 41 27 for Microsoft Windows 2000 prevents a DPC LAN connection when the operating system is
12. Den oe Teo DD REED E pa robe 94 Table 82 5052 Server Board Power Consumption sssssssseeeee 95 Table 83 SDS2 Power Supply Specification esee esee nennen 95 Table 84 Voltage Timing Parameters 95 Table 5 Tri COD OE TIMING s eds tst Qt eo el temo pnis fe IU doa 97 Table 86 Transient Load 0 99 Table 87 Estimated 5052 Server Board MTBF sse 100 Table 88 Safety Regulations ennt nnne nnne entes 102 Table 89 EMG Regulations usce col obedit 102 Table 90 ICMB External Cable 105 Fable Oi Errata SUI SIE Dare rere fn Med ctl tus pas ae 106 Revision 1 2 xiii Order Number A85874 002 List of Tables Intel Server Board SDS2 lt This page intentionally left blank gt Xiv Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Introduction 1 Introduction This chapter provides an architectural overview of the Intel 5052 Server Board It provides a view of the functional blocks and their electrical relationships The figure below shows the functional blocks of the Server Board and the plug in modules that it supports Front Side Bus 133MHz D y y APIC Bus PCI 32 bit Bus 33MHz 5V DA
13. 4 5 1 0 808 4 5 2 Bus Master IDE 7 5 3 USB Interface 4 5 4 Compatibility Interrupt 455 es aa outs oso ra a 4 5 6 Power 4 242 41 4 5 7 General Purpose Input and Output Pins 46 Chipset Support 46T Super sss ne faeta adis Order Number A85874 002 Intel amp Server Board SDS2 Revision 1 2 Intel Server Board SDS2 Table of Contents 20 47 ROUNO x 20 4 7 1 Legacy Interr pt RoutiNg 20 4 7 2 APIC Interrupt ROUUNG to tease 21 4 7 3 i Senalilzed IHCESUDDBOLL 21 4 7 4 IRQ Scan for pelli escis deesset 21 5 Server Managermehi t e tete 25 5 1 Sahalee Baseboard Management 27 5 1 1 Fault Resilient Booting 29 ME nter 30 LN OSE eM orem TN 30 25 acie FROST MR HP TEE 30 nog 30
14. 4 6 1 1 General Purpose Input and Output GPIO The National Semiconductor PC87417 Super I O provides number of general purpose input output pins that the SDS2 Server Board utilizes The following table identifies the pin the signal name used in the schematic and a brief description of its usage Table 11 Super Usage Table N BMC SYSIRQ 00 System Interrupt Controller interrupt from BMC SIO 40M BMC 40MHz clock output to BMC 18 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Subsystem s 4 6 1 2 Serial Ports Two serial ports are provided on the Server Board a 9 pin DB9 connector is located on the rear I O to supply and a 10 pin header on the Server Board provides COM2 4 6 1 3 Floppy The FDC in the SIO is functionally compatible with floppy disk controllers in the DP8473 and N844077 All the FDC functions are integrated into the SIO including analog data separator and 16 byte FIFO 4 6 1 4 Keyboard and Mouse Two PS 2 ports are provided for keyboard and mouse and are mounted within a single stacked housing The mouse connector is stacked over the keyboard connector 4 6 1 5 Parallel Port The parallel port is supported on the Server Board through the rear I O 4 6 1 6 Real time Clock The SIO contains a real time clock with external battery backup The device also contains 242 bytes of general purpose battery backed CMOS RAM
15. Go to BIOS Initialize processors Set 4 GB segment limits Perform platform initialization E Initialize the hardware Initialize memory type Initialize memory size Shadow boot block Test system memory Initialize interrupt services Initialize real time clock Initialize video Initialize beeper Initialize boot Restore segment limits to 64 KB Boot mini DOS CP Beeps Reason Pee a TL INN Ea a Se ene DEO NEN 7 M E ep 1 1 e SGE SD NN EN 1 0 CNN CI peal ong Revision 1 2 49 Order Number A85874 002 BIOS Intel Server Board SDS2 6 2 5 3 POST Error Codes and Messages The following table defines POST error codes and their associated messages The BIOS prompts the user to press a key in case of serious errors Some error messages are preceded by the string Error to indicate that the system may be malfunctioning All POST errors and warnings are logged in the System Event Log unless it is full Table 29 POST Error Messages and Codes 0251 System CMOS checksum bad
16. Interrupt 4 Selects the IRQ for COM port 1 Serial Port 2 Disabled If set to Auto BIOS or OS configures the port Enabled Auto Base I O Address Selects the base I O address for COM port B interrupt Selects the IRQ for COM port Parallel Port Disabled If set to Auto BIOS or configures the port Enabled Auto Mode Output only Selects Parallel Port Mode Bi Directional EPP ECP Base I O Address 378h Selects the base I O address for LPT port aes a eee Interrupt 5 Selects the IRQ for LPT port EE S o 1 DMA channel Selects the DMA for LPT port Legacy USB support Disabled If disabled legacy USB support is turned off at the Enabled end of the BIOS POST PS 2 Mouse Disabled If disabled PS 2 Mouse Port will not function Enabled Should make IRQ12 available for other devices Revision 1 2 61 Order Number A85874 002 BIOS Intel Server Board SDS2 Table 42 Advanced Chipset Controller Submenu Selections e a ____ _ PCI Device Selects sub menu sub menu Wake LL Ring a EU controls legacy wake up May not be present if Disabled not supported Wake On LAN Enabled Only controls legacy wake up May not be present if Disabled not supported Sleep Button Present Selects the sleep button of the platform Absent Table 43 PCI Device Submenu Selections Feature PCI IRQ line 1 Disable Select the IRQ for PCI IRQ Auto Select PCI IRQ
17. C nats caches omnia POSTvawes SSCS nase C Tosama registers win nia POSTvabes Restore Processor contorwordaurngwarmboot mausgCPusmesemgdmees otona ache bremeno cP 2062 EON rou 46 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS P CP EN Eg EE E Beeps 1 3 3 1 Auto size DRAM system BIOS stops execution here if the BIOS does not detect any usable memory DIMMs Revision 1 2 47 Order Number A85874 002 2C 2F 32 33 34 35 42 44 45 46 BIOS Intel Server Board SDS2 U Beeps 48 Revision 1 2 Order Number A85874 002 LN LN EN EN EN Intel Server Board SDS2 BIOS P Beeps Reason MEN Fix up Multi Processor table 1 2 Search for option ROMs One long two short beeps on checksum failure Check for SMART Drive Shadow option ROMs Set up Power Management Initialize security engine Enable hardware interrupts Set time of day Check key lock E Initialize spermatic rate EE EE Table 28 Recovery BIOS POST Codes P Reason Initialize chip set Initialize bridge Initialize processor aM Initialize timer Initialize system I O Check forced recovery boot al Validate checksum a
18. FOXCONN 390170 6 168 pin DIMM connectors 11 12 15 16 FOXCONN EH09201 GY V 64 bit PCI connectors 3 3V FOXCONN EH06001 GV V 32 bit PCI connectors 5V 13 14 FOXCONN QA11343 P1 68 pin SCSI connectors 30 31 FOXCONN HL07207 KD2 40 pin IDE connector 24 20411 FOXCONN HLO7177 KD4 34 pin floppy connector 34 2 PULSE J0026D01B RJ 45 NIC connectors Revision 1 2 87 Order Number A85874 002 Jumpers Intel Server Board SDS2 __ iy Wanutactuer z FOXCONN moere 25 pinDSUB parallel port coneco Lm i Feon oromere seral pon comes Hostes opin Saheer rr roxconn ostoz Dual PS keyboard mouse connector ee Bin chassis intrusion connector MO 3929426 TATA main power connector n Foxconn sexes paren oer m 208 5005 Spin OEPM corea er Zn BMC ware wit protectheader e Foxconn pin BIOS witeprotectheader ZpBMGFRBtmerdssbleneader m 7 Foxconn epin BMC FRG update header s Y Sot epin BNC SRAM header en Spin PUTT ToO head 22924283838 t FOXCONN Spin fen conres 5054 epn aveai eomer oe 1758904 SpiniUKpowercomedor s SPEEDTECH Wrz 118012 BiG pin processor speed rato header sr Y Seon 2xt7 pinfontpanel
19. Status Fixed with the release of FAB5 SDS2 severboard in October 2002 25 Potential Mylex AcceleRAID 352 Adaptor Card Mechanical Interference at PCI Slot 6 120 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing Problem Implication Workaround Status Mechanical interference between the Myelex installed memory module DIMM and the onboard SCSI connector occurs if a Wide or Singled Ended SCSI cable is installed on embedded SCSI A or B connector LVD SCSI cable connectors do not interfer Mechanical interference may damage the Mylex memory module connector and DIMM when the Mylex AcceleRADI 352 Adaptor Card ins fully seated in PCI slot 6 connector Insure correct SCSI cable connector is used if a cables are installed on the onboard SCSI connectors at SCSI A or B Will not fix 26 Bootable CD will not boot if inserted during OPTION ROM scan Problem Implication Workaround Status During POST while the OPTION ROM scan for the on board OB devices and add in PCI adapters is in process if an bootable CD ROM is inserted in to he CD ROM the system will not attempt to boot to the CD ROM An attempt to boot to the floppy was made and then the OS on the hard drive booted No attempt was made to boot to the bootable CDROM Bootable CD ROM must be inserted before POST begins or the system is reset Reset system after CD ROM is inserted Will not fix 27 Swapping bootable
20. e gt lt lt lt tc is tc a a a 7 7 7 2 LOIS 19 LOTS 19 91016124 91015 ISOS 0911 2 Ov Bl a OIN HIN Sz 9 NvHas S NvHas lt YALSIDOAY Wvaas 93151999 WNvaas ZHIN 99 HIS uadana 7HIN99 2 99 ZHI 99 lOd ZHN 99 ZHIN99 ZHN 99 2 99 ZHN 661 ZHW 551 ZHW 551 2 551 2 661 ZHN 661 ZHN 661 i ZHN 551 ZHN 99 2 55 MT9QH8NO 08310 Tld 11 419 WNvHas golo 15 M1084d5V JH 2 26 uad4ngs 19 ZHINEE 19 6859 ZHN 99 2 EE 2 EE 2 EE 2 8v ZHI 8 2 91 2 91 ZHN9L 2 551 2 581 ZHW 661 ZHIN99 19 M19 ZHINEE 19 ZHW vL ZHIN 87 19 OldV X19 LSOH ZHW 81571 Figure 8 SDS2 Server Board Clock Generation Distribution Diagram 71 Revision 1 2 Order Number A85874 002 Clock Voltage Generation and Distribution Intel Server Board SDS2 7 2 Voltage The system power supply provides 3 3V 5V 12V 12V and 5VSB and voltage regulators on the Server Board are used to create the following voltages e 3 3VSB e VCORE for the CPUs e VIT for the CPUs e 2 5V for the chipsets e 1 8V for the onboard SCSI The following figure illustrates voltage generation and di
21. 2 Locate the chassis standoff labeled 1 in your chassis 3 Place the rubber bumper at a location 6 25 inches 16 cm toward the front of the chassis and 7 75 inches 19 cm toward the center of the chassis from standoff 1 See location B below 4 Press the rubber firmly into place Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing Workaround Status Figure 1 Placing the Rubber Bumper in the Chassis Utilizing the rubber bumper with the SDS2 Server Board is a workaround for issues that may occur due to vibration during shipment of the integrated system product NoFix 21 Keyboard and Mouse do not function under Microsoft Windows 2000 when legacy USB is enabled in BIOS setup Problem Implication Workaround Status Revision 1 2 When the Legacy USB Support option is set to Enabled in BIOS setup a PS 2 keyboard and mouse do not function under Microsoft Windows 2000 This has not been seen to occur with other operating systems Enabling the Legacy USB Support option in BIOS setup will make a PS 2 keyboard and mouse non functional under Microsoft Windows 2000 Leave the Legacy USB Support option in BIOS setup set to Disabled which is a default option if Microsoft Windows 2000 is being used Fix Intel has identified a fix for this issue which will be incorporated in the SDS2 FAB 5 server board 119 Order Number A85874 002 Errata Listing Intel Server
22. Enable loading BIOS code from a floppy disk into the Flash device This is typically used when the BIOS code has been corrupted BIOS Write When CN46 s pins 1 and 2 are OPEN default BIOS boot block is protected from being updated Protect When they are CLOSED BIOS boot block can be updated BMC Write When CN47 s pins 1 and 2 are OPEN default BMC boot block is protected from being updated Protect When they are CLOSED BMC boot block can be updated Chassis When CN50 s pins 1 and 2 are cabled to the chassis default a switch installed on the chassis Intrusion indicates when the cover has been removed When they are CLOSED the chassis intrusion feature Disable is disabled When CN49 s pins 1 and 2 are OPEN default the BMC enters operational mode upon the negation of its reset When they are CLOSED the BMC enters force update mode upon the negation of its reset FRB3 When CN48 s pins 1 and 2 are OPEN default FRB operation is enabled This allows the system Timer to boot from another processor if Processor 1 fails When they are CLOSED FRB2 and FRB3 are Disable disabled Table 79 CPU Frequency Select Jumper Options Revision 1 2 91 Order Number A85874 002 Jumpers Intel Server Board SDS2 Table 80 List of Assembled Jumpers in Production 3 4 Open Wren close clears CMOS password SPARE jumper storage 9 2 Performing CMOS Clear BIOS Recovery and BMC Force Update 9 2 1 Performin
23. Maximum Capacity Sectors entered This field is only available for Type User This field is informational only for Type Auto LBA Format Information Only Total number of sectors on the drive that are Total Sectors addressable in LBA format LBA Format Information Only Capacity of the drive while using LBA addressing Maximum Capacity This value may be higher than the Maximum Capacity above for drives bigger than 8 4 GB Multi Sector Transfer Disabled Specifies the number of sectors that are transferred 2 Sectors per block during multiple sector transfers 4 Sectors This field is informational only for Type Auto 8 Sectors 16 Sectors LBA Mode Control Disabled Enable Disable LBA instead of cylinder head Enabled sector addressing This field is informational only for Type Auto 32 Bit I O Disabled Enabling allows 32 bit IDE data transfers Enabled This field is informational only for Type Auto 56 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS Feature Option Descripion Transfer Mode Standard Select the method for moving data to from the drive FPIO 1 This field is informational only for Type Auto FPIO 2 This field is updated to display only the modes FPIO 3 supported by the attached device FPIO 4 FPIO 3 DMA 1 FPIO 4 DMA 2 Ultra DMA Mode Disabled Selects the Ultra DMA mode used for moving data Mode 0 to from the drive Autotype the drive toselect the Mode 1 optimum transfer
24. Order Number A85874 002 Intel Server Board SDS2 Processor and Chipset Table 2 Memory DIMM Pairs emery DMM Row Figure 2 SDS2 Memory Bank Layout Revision 1 2 7 Order Number A85874 002 Processor and Chipset Intel Server Board SDS2 3 2 2 Bus bus is between the BMC and the six DIMM slots This bus is used by the system BIOS to retrieve DIMM information needed to program the HE SL memory registers which are required to boot the system The following table provides the addresses for each DIMM slot Table 3 Addresses for DIMM Slots DIMM 1A 0 0 DIMM OxA8 3 3 Chipset The Server Works ServerSet Ill HE SL chipset provides an integrated I O bridge and memory controller and a flexible I O subsystem core PCI targeted for multiprocessor systems and standard high volume servers The Server Works ServerSet chipset consists of the three components listed below CNB20HE SL Champion North Bridge The HE SL North Bridge is responsible for accepting access requests from the host processor bus and for directing those accesses to memory or to one of the PCI buses The HE SL monitors the host bus examining addresses for each request Accesses may be directed to a memory request queue for subsequent forwarding to the memory subsystem or to an outbound request queue for subsequent forwarding to one of the PCI buses The HE SL also accepts inbound requests from
25. Timing requirements 93 U Ultra DMA 66 16 Ultra DMA Mode 17 Ultra160 2 3 10 14 Ultral60 SCSI 2 Uncorrectable errors 38 Universal Serial Bus 46 USB 46 USB connector 17 80 85 USB connector interface 17 USB controller 8 16 17 USB interface 16 USB ports 3 80 User binary 35 65 66 67 Vbat 40 VID 6 27 Video BIOS 65 Video connector interface 78 Video Controller 2 11 12 Video memory 14 78 Video SDRAM 14 Voltage distribution 70 Voltage generation 70 Voltage Identification 6 Voltage Regulator Module 6 Voltage regulators 70 102 Voltage specifications 93 VRM 6 VRMI 40 VRM2 40 W Watchdogl 39 X X Bus 3 Z Zero Channel Raid 14 105 Revision 112 Order Number A85874 002 Intel Server Board SDS2 Index Zero channel RAID controller 14 Revision 1 2 Order Number A85874 002
26. Workaround Status Intel Server Board SDS2 The SDS2 server board will not complete POST if more than 4GB or more of total system memory is installed and the Extended RAM step option in BIOS Setup is set to Every Location Choose a different option besides Every Location for the Advanced gt Memory Configuration 2 Extended RAM Step BIOS Setup option The default setting for this option is Disabled Fixed This issue is fixed in SDS2 BIOS Production Release 2 4 Build 47 and later versions 13 Novell NetWare v 6 0 does not install on SDS2 Problem Implication Workaround Status Novell NetWare v 6 0 will not install on the SDS2 server board The install proceeds normally until the NetWare v 6 0 splash screen appears for the first time The install will then start iterating the portion of the install from initializing system resources to the splash screen indefinitely Novell NetWare v 6 0 cannot be installed to the SDS2 server board None Fixed This issue has been root caused as a Novell NetWare v 6 0 operating system issue Novell has released NetWare v 6 0 support pack SP 1 which fixes this issue Intel has verified the Novell NetWare v 6 0 can be successfully installed to the SDS2 server board when SP1 is applied The procedure for applying SP1 is as follows 1 Create a 200MB bootable DOS partition on the installation hard drive 2 Format the partition and create a directory called
27. out of the connector Table 72 DB25 Parallel Port Pin out Pin SignatName Pin Sianal Name i DATA4 GND psu 8 6 9 Keyboard and Mouse Connector Two PS 2 ports are provided for keyboard and mouse and share a common housing The top one is labeled mouse and the bottom is labeled keyboard although the board set supports swapping these connections The following table details the pin out of the PS 2 connectors Table 73 Keyboard and Mouse PS 2 Connector Pin out Revision 1 2 Order Number A85874 002 Connections 85 Connections Intel Server Board SDS2 Pin Signal Name Pin Signal Name KBDATA MSDATA fs we h Ne 8 7 Miscellaneous Headers 8 7 1 Fan Headers There are two fan connectors for processors and four system fan connectors All six fans are monitored by the BMC and they all share the same pin out Table 74 Fan Header Pin out GROUND is the power supply ground ut FAN_TACH signal is connected to the BMC to monitor the FAN speed 8 7 2 Chassis Intrusion The BMC monitors the chassis intrusion switch by polling the ADM1026 device The cable from the chassis cover is connected through the 2 pin header below To disable chassis intrusion detection short the 2 pin header with a jumper Table 75 Chassis Intrusion Header Pin out Pm CHASSIS INTR 8 7 3 External SCSI Activity LED Input Signal Connector A 4 pin header labeled HDD LED
28. 1 0 the power supply tolerance is specified as 5 for the 3 3V rail Intel has induced a failure condition during board level temperature and voltage margin testing at 55 C and 5 voltage on the 3 3V rail in SDS2 Server Boards configured with PCI adapters in the 64bit 66MHz PCI slots under extreme workloads during final validation testing As a result the SDS2 Server Board board level operating temperature specification has been modified to 0 C to 45 C and the power supply tolerance specification for the 3 3V rail has been modified to 3 The SDS2 Server Board passes board level temperature and voltage margin testing performed according to these modified specifications The SDS2 Server Board s operating environment should be maintained within the modified board level operating temperature specification of 0 C to 45 C and the modified power supply tolerance specification of 3 for the 3 3V rail The power supply tolerance specification for the 5V 12V and 5V standby rails is still i596 The system level operating temperature specification of the Intel Server Board SDS2 integrated into the Intel amp SC5100 Server Chassis is still 0 to 35 C The Intel SC5100 Server Chassis cooling system is capable of maintaining a SDS2 board level temperature below 45 C at a 35 C system ambient temperature None Fix Intel has identified a fix for this issue which will be incorporated in the SDS2 FAB 5 server board 20 Recommendation for
29. 39 Certification marks 101 Chained memory structure 15 5 Chassis intrusion 27 38 Chassis intrusion detection 84 SV 39 Chassis Intrusion header 86 Chip select 11 12 8 Chipset failure 38 82550 2 11 12 15 16 CIOB20 2 4 8 9 11 12 31 38 82550PM 9 20 CIOB20 I O Bridge 2 11 12 8259 16 CMOS 45 46 66 82C59 17 20 CMOS clear 65 CMOS Clear 89 90 A CMOS clear jumper 51 65 A D converter 38 CMOS map 65 AC link mode 33 CMOS modification 51 CN49 89 90 91 ACPI control registers 8 CN50 86 89 90 Active terminators 14 ADM1026 27 31 84 CNB2 0HE SL 38 Advanced Menu 51 54 57 CNB20 2 AGTL signaling environment 4 CNB20HE SL 8 9 AGTL terminator module 4 Configuration registers 14 16 20 AIC 7899W 3 10 13 14 Controller 45 Alert on LAN 15 CPU Fan 1 41 Analog measurement channels 27 CPU Fan 2 41 ASF Progress Events 43 CPU fans 3 CSBS 2 3 8 9 10 11 12 16 17 18 20 21 22 30 32 68 CSB5 South Bridge 2 11 12 Current specifications 93 Auto negotiation support 15 Auxiliary signal connector 72 IV Revision 1 2 Order Number A85874 002 Index Intel Server Board SDS2 D Graphics Controller 2 Data channels 21 H Data transfer 8 Device ID 11 12 Hard reset 30 DIMM 42 Hecetas 27 DIMM sockets 2 6 HE SL CNB20 North Bridge 2 DMA Mode 17 HE SL memory registers 8 DP8473 19 Host bus interface 4 Host controller 21 E Errata Summary Table 10
30. 5 3 Intelligent Platform Management 30 5A Eror ReponiNg nee en 32 5 4 1 Error Sources and Types ccccceceeeeeeeeeeeeeeseeceaeeeeeeeeneesaeeceaeseaeeeeeeesaeeenaeseeeeseneesaaees 32 54 2 POLBUS EMOS abet dut Du 32 5 4 3 Intel Pentium Processor Bus 32 544 Memory Bus EtfOIs o rt ed RR bo p on RR Ke erat Fast rs s 33 OUS eb e tremere oett 33 55 dU see s tava d eMe TK E 33 56a 2 PUR Dd RA c 33 Dele 35 System BIOS creme 35 6 2 BIOS Error Haridling ice eu a Hen 36 6 2 1 EMar Sources 36 6 2 2 Handling and Logging System 4444000 36 6 23 a d onde Maii etna Eod au Barone weal add 38 624 Firmware BMG seo n ete e ERU I tege da fet DE UN S tse iare 39 6 2 5 Error Messages and Error Codes sse nennen 45 637 UUM EIN i oe Reuter pda eed e on E ie one 52 6 3 1 Configuration Utilities Overview 4 100000 enne 52 6 3 2 Setup Utility fe tice tr ttti breit a t 52 6 3 3 CMOS Memory c USE E NUR EAE
31. 6 Exit Menu Selections The following menu options are available on the Exit menu Use the up and down arrow keys to select an option and then press the Enter key to execute the option Table 51 Exit Menu Selections Option Description Exit Saving Changes Exit after writing all modified Setup item values to NVRAM Exit Discarding Changes Exit leaving NVRAM unmodified User is prompted if any of the setup fields were modified Load Setup Defaults Load default values for all SETUP items Load Custom Defaults Load values of all Setup items from previously saved Custom Defaults NOTE This is hidden if custom defaults are not valid or present Save Custom Defaults Stores Custom Defaults in NVRAM Discard Changes Read previous values of all Setup items from NVRAM Save Changes Write all Setup item values to NVRAM 66 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS 6 3 3 CMOS Memory Definition The CMOS map is available in the NVRAM LST file generated for every BIOS release The CMOS map is subject to change without notice 6 3 4 Clearing CMOS The BIOS detects the state of the CMOS jumper If the jumper is set to CMOS Clear prior to power on or a hard reset the BIOS changes the CMOS and NVRAM settings to a default state This guarantees the system s ability to boot from floppy Password settings are unaffected through CMOS clear The BIOS clears the ESCD parameter block and loads a null ESCD i
32. 67 12 Order Number A85874 002 Table of Contents Intel Server Board SDS2 6 3 4 Olea MOS rarer ener ere 67 6 4 Flash Update Pe a PR Fed 67 6 4 1 Leading ihe System BIOS eot adnan Qe Guias bu dens 67 p4 2 User Binary ABa ac o tee lect ait toni uem ee ltd edu ee 68 643 Eangu ge dei dnd Enc an ae ee 68 6 4 4 OEM Logo Screen ME UL LE 68 6 4 5 Recovery Mode ie oue t antea o etat tud ated ha a 68 Clock Voltage Generation and Distribution 70 ro Wc oem P UE S 70 34 3 Anllade eec reddite e pire Du tom nd tasti npe au E End e ce dbi tute 72 MEC eil St 74 8 1 Power Distribution Board COnm CtOl vis te x enon 74 8 2 Memory Module Connector esses eene nnne tnnt 75 8 3 System Management Headers pereat Eben RR eer t ee 76 8 3 1 eade eh erie 76 8 3 2 OEMJIPMEB GOHFIBCIOL Ru EEG bud c me EAE MU Rene 76 8 3 3 SCSI HSBP IPMB Connector scien does bee ee ho unc 76 8 4 Front Panel 4 212 6 2 ebur PER EE a RE NE E UOS 77 95 JPOP SIStOCONMECIOR 26 cakes ta porq tr 78 S62 VO CONNEC
33. A is for commercial or industrial environments and FCC Class B is for residential environments 12 2 2 3 Canada A nationally recognized certification mark such as CSA or cUL signifies compliance with safety requirements EMC compliance to Industry Canada ICE3 003 is required Class A is for commercial or industrial environments and FCC Class B are for residential environments 12 2 3 Prevent Power Supply Overload The power supply output must not be overloaded To avoid overloading the power supply the calculated total current load of all the modules within the server should be less than the maximum output current rating of the power supply If this is not adhered to the power supply may overheat catch fire or result in a shock hazard If the load drawn by a module cannot be determined by the markings and instructions supplied with the module contact the module supplier s technical support 12 2 4 Place Battery Marking on Computer There is insufficient space on this server board to provide instructions for replacing and disposing of the battery The following warning must be placed permanently and legibly on the host server as near as possible to the battery WARNING Danger of explosion if battery is incorrectly replaced Replace with only the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions 104 Revision 1 2 Order Number A85874 002 Intel Server Bo
34. Board SDS2 22 Data miscompares when using Seagate ATA model T310215A hard drives Problem Intel has induced data miscompares in SDS2 sytems configured with a Seagate ATA model ST310215A hard drive under extreme workloads during validation testing Intel has verfied that other hard drive models are not affected by this issue Implication The Seagate ATA model ST310215A hard drive installed on the Intel Server Board SDS2 is currently not a supported configuration and should not be implemented in a production environment Workaround None Status Fix Intel has identified a fix for this issue which will be incorporated in the SDS2 FAB 5 server board 23 Bootto service partition via modem fails Problem When utilizing the direct platform control DPC feature of Intel Server Control ISC v 3 5 2 software to boot a SDS2 server board to the service partition via modenm the server board will hang during ROM DOS load Implication The DPC feature of ISC v 3 5 2 software cannot be used to remotely boot the SDS2 server board to the service partion via modem Workaround None Status Fixed SDS2 BIOS Production Release 2 6 Build 49 and later versions include a fix for this issue 24 Secondary IDE References Added To Documentation for FAB 5 Problem New FAB5 AXXXX 502 has second IDE ATA 100 connector enabled Implication Users now have second IDE channel for use in system configurations Workaround None
35. Default CMOS checksum error configuration used 0260 System timer error System timer error 0271 Check date and time setting RTC time setting error 0280 Previous boot incomplete Default configuration used 0252 Password checksum bad Passwords cleared 0281 Memory Size found by POST differed from EISA CMOS 0613 Aconfiguration changed 50 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS Code 0614 0615 0616 0617 0618 0619 061A 0 00 0 01 0B02 0B1B Error Message Failure Description COM A config error device disabled S COM B configuration changed EMEN COM B config error device disabled S Floppy configuration changed RE Floppy config error device disabled S Parallel port configuration changed Parallel port config error device disabled Po Rebooted during BIOS boot at Post Code Pe Rebooted during OS Runtime System Error on Bus Device Function PCI system error in Bus device Function PCI System error in Bus device Function 0 1 0B22 0B28 0B29 0B30 0B31 0B32 0B33 0B34 0B35 Fan 6 Alarm occurred Failed Processor 1 because an error was detected Failed Processor 2 because an error was detected PCI Parity Error Bus Device Function Processors are installed out of order Unsupported Processor detected Processore 1 Unsupported Processor detect on Processor 2 DLL Fan 2 Alarm occurred Fan 3 Alarm occurred F
36. Order Number A85874 002 BIOS 41 BIOS 42 Intel Server Board SDS2 Event Event Reading Offset Sensor Type Triggers Fan Boost Front Panel 3Ch OEM C7h Temp Threshold Fan Boost Threshold PDB Temp Fan Boost Proc 1 Core 3Eh OEM C7h Temp 3Dh OEM C7h Threshold Fan Boost Proc 2 Core 3Fh OEM C7h Temp Threshold Threshold 01h 04h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Threshold 01h Dm Dm DM D Threshold 04h 04h Fan 04h Fan 04h 4 4 4 Fan 04h Fan 04h 1h 04h 04h Power 5 Supply 1 04h 04h 04h 04h Threshold 04h 0th Eee me omom Fanon gp Power Supply Sensor Failure 08h Specific 6Fh Predictive Fail A C Lost 49h 4Ah Bh Ch Dh 50h 52h 53h 54h 55h 58h 59h Ah Order Number A85874 002 Revision 1 2 Intel Server Board SDS2 BIOS Event Event Sensor Sensor Type Reading Offset Name Type Triggers Presence Power 5Bh Power Supply Sensor Failure Supply 2 08h Specific 6Fh Predictive Fail A C Lost Presence Power 5Ch Power Supply Sensor Failure Supply 3 08h Specific 6Fh Predictive Fail A C Lost Missing CPU Module
37. PCI slot current levels supported by the 5V rail 36 OB P100 NICs do not show at POST but attempt PXE boot and appear in Boot Menu125 Ctr d Reference RR ERR Ib eem IV Revision 1 2 ix Order Number A85874 002 List of Figures Intel Server Board SDS2 List of Figures Figure 1 5052 Server Board Block Diagram 1 Figure 2 SDS2 Memory Bank LayOUL edere aeree inae keep apu etin 7 Figure 3 5052 Interrupt Routing Diagram CSB5 22 Figure 4 SDS2 Interrupt Routing 23 Figure 5 5052 PCI Interrupt Mapping Diagram sese 24 Figure 6 5052 Sahalee BMC Block Diagram View as Reference Only 26 Figure 7 5052 Locations of ADM1026 and Sahalee sse 29 Figure 8 5052 Server Board Clock Generation Distribution Diagram 71 Figure 9 5052 Server Board Voltage Generation Distribution Diagram 73 Figure 10 5052 Server Board Rear I O Panel sese 87 Figure 11 SDS2 Configuration J rmpetrs enr rr Perte o ER d
38. Recovery is complete it is safe to power off the system Power off the system unplug the power cord s and remove the chassis panel Remove the BIOS Recovery jumper from CN42 pins 9 10 Replace the chassis panel plug in the power cord s and power on the system Performing BMC Force Update In the event of a release of an updated BMC Firmware the following procedure may be used to update the Firmware 1 Prepare a bootable floppy diskette containing the updated BMC firmware files for the SDS2 Server Board obtained from Intel s web sites 2 Power off the system unplug the power cord and remove the chassis panel 3 Add a jumper CN49 pins 1 2 BMC Force Update 4 Insert the BMC Firmware floppy diskette into the disk drive 5 Reinstall the chassis panel plug in the power cord s and power on the system 6 If any POST errors occur press F1 to continue BMC Firmware update may take several minutes to complete When the BMC Firmware update is complete it is safe to power off the system 7 Power off the system unplug the power cord s and remove the chassis panel 8 Remove the BMC Force Update jumper from CN49 pins 1 2 9 Replace the chassis panel plug in the power cord s and power on the system Note The instructions for BMC Force Update are general guideline Please follow the specific instructions described in the release notes Revision 1 2 93 Order Number A85874 002 Electrical and Thermal Spe
39. SDS2 rubber bumper installation Problem Revision 1 2 A rubber bumper is included with the Intel Server Board SDS2 Intel recommends installing this bumper on the chassis before integrating the board into the chassis in order to improve the board s tolerance to vibration that may occur during shipment of the integrated system product 117 Order Number A85874 002 Errata Listing Implication 118 Intel Server Board SDS2 If you are installing the Intel Server Board SDS2 into the Intel SC5100 Server Chassis Intel recommends installing the rubber bumper included with the server board If you are installing the Intel Server Board SDS2 into a chassis other than the Intel SC5100 Server Chassis compare the rubber bumper height to the chassi standoff height If the bumper is the same height as the standoffs in the chasis install the rubber bumper included with the SDS2 Server Board If the suport is not the same height procure a bumper that matches the height of the standoffs used in your chassis The rubber bumper should be installed on the chassis as follows For the Intel SC5100 chassis 1 Remove the backing from one of the rubber bumpers included with your chassis 2 Press the rubber bumper firmly into place approximately 1 2 inch 2 cm to the right of the chassis baseboard hole marked 9 See location A below For other chassis 1 Remove the backing from one of the rubber bumpers included with your chassis
40. To disable the Intel BIOS logo screen access the Intel Server Board SDS2 BIOS Setup by pressing F2 when the Intel BIOS logo screen appears In BIOS Setup change the Advanced gt Boot Time Diagnostic Screen option to Enabled Fixed For the ICP Vortex RAID Controllers please contact ICP technical support Please refer to Technical Advisory 507 for firmware release schedules and additional details 6 Intel amp Server Board SDS2 CD ROM issues Problem Implication Workaround 110 The Intel Server Board SDS2 system resource CD ROM has the following two issues 1 The BYO Platform Confidence Test Manual on the SDS2 system resource CD ROM is Rev 2 0 dated 9 2001 rather than the latest Rev 2 2 dated 10 2001 The instructions in the Rev 2 0 manual for creating a bootable Platform Confidence Test floppy diskette are not correct and do not contain enough detail for the user to successfully create a bootable floppy diskette 2 Editing a file with the DOS Edit command after booting to the SDS2 system resource CD ROM will cause the system to hang A bootable Platform Confidence Test floppy diskette cannot be successfully created by following the instructions in the SDS2 BYO Platform Confiedence Test Manual Rev 2 0 on the SDS2 system resource CD ROM Attempting to edit a file with the DOS Edit command after booting to the SDS2 system resource CD ROM will cause the system to hang Users should not use the DOS Edit comman
41. Ue Eu ua Ex ucl aea a epa eas 27 Table 15 Temperature 0 4 4 nennen nnne nnne nennen nnn 28 Table 16 Sahalee Input Denton ta de det Su I uS 28 Ttable T IPMB Bus Devies en eot ario de eio Po dee ele esa Pa ee iae e bd 31 Table 18 Private Bus 1 Devices ettet tette ttes 31 Table 19 Private Bus 2 Devise sot t AE te dn at 31 Table 20 Private Bus 8 Devices s cao mb ae eed tae 31 Table 21 Private Bus 4 DOVI BS ac ederet tete td ete vtt ecd Cu NR 32 Table 22 BlOS Generated SEL ie dos nmt eels 37 Table 23 Event Request Message Event Data Field Contents 38 Table 24 Platform SEL Log Sensors for SDS2 esses eene 39 Table 25 Event Request Message Event Data Field Contents 45 Table 25 Port S bCode Deflhitioltus ii s ie ie da tt tae HS 45 Table 27 Standard BIOS POST Codes 46 lable 26 Recovery BIOS POST GOCGS coda ct ata dO eee eee 49 Table 29 POST Error Messages Codes essere 50 Table 30 BMC Beep Codes imer oe Getestet ate mrcrasher tei ideam tend etre
42. at CN44 is provided on the Server Board to track SCSI drive activity on the Hot Swap Back plane The following table details the pin out of the header This allows two RAID controller cards to connect their disk activity cables to the front panel hard disk LED activity light Note that IDE hard disk activity LED is not enabled on the SDS2 board via the front panel connector at CN37 Pins 2 and 3 are tied together routed through an AND gate to Pin 9 of CN37 front panel connector 86 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Connections Table 76 External Drive Activity Header Pin out Pin Signal name DRIVE_ACTIVITY DRIVE_ACTIVITY 8 8 Rear Panel The following diagram shows the locations of keyboard mouse USB serial parallel video and NIC connector interfaces on the system I O panel as viewed from the rear of the system 195 10 148 01 13569 0 00 16 51 28829 276 25 258 70 167 64 Figure 10 SDS2 Server Board Rear I O Panel 8 9 Connector Manufacturers and Part Numbers The following table shows the quantity and manufacturer s part numbers for connectors on the Server Board Refer to manufacturer s documentation for more information on connector mechanical specifications Table 77 Server Board Connector Manufacturer Part Numbers CN Numbers Qty Manufacturer Mfg Part Functional Description U1 U4 67276 3708 Rev 4 P370 processor sockets DIMM 1 6 6
43. characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design The Intel Server Board SDS2 may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license The information in this manual is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means without the express written consent of Intel Corpora
44. controller SRCMR not yet supported with Intel Server Board SDS2 Problem The Intel RAID Controller SRCMR installed on the Intel Server Board SDS2 is currently an unsupported configuration Intel has induced a failure condition in Intel Server Board SDS2 systems configured with the Intel RAID Controller SRCMR under extreme workloads during final validation testing Intel has verfied that other Intel RAID controllers and Intel server boards are not affected by this issue The Intel RAID controller SRCMR installed on the Intel Server Board SCB2 does not exhibit this failure Implication The Intel RAID Controller SRCMR installed on the Intel Server Board SDS2 is currently not a supported configuration and should not be implemented in a production environment Workaround None Status Will not fix 2 Intel amp Server Board SDS2 BIOS update utility does not allow updates from a PXE Server or from network drives Problem The current Intel Server Board SDS2 BIOS update utility PhoenixPhlash does not allow the BIOS updates to be performed from a PXE server or from a network drive Implication The Intel Server Board SDS2 BIOS cannot be updated from a PXE server or a network drive The BIOS update must be performed from a floppy diskette or from a hard drive Workaround None Status Fixed SDS2 BIOS Production Release 2 1 Build 44 adds support for the Intel iFLASH BIOS update utility The iFLASH BIOS update utility has the a
45. detection is implemented in the Sahalee BMC e FRB level is for recovery from a Watchdog timeout on Hard Reset Power up Sahalee BMC provides hardware functionality for this level of FRB Revision 1 2 29 Order Number A85874 002 Server Management Intel Server Board SDS2 5 2 System Reset Control Reset circuitry on the SDS2 Server Board looks at resets from the front panel CSB5 ITP and processor subsystem to determine proper reset sequencing for all types of reset The reset logic is designed to accommodate a variety of ways to reset the system which can be divided into the following categories e Power up reset e Hard reset e Soft programmed reset The following subsections describe each category of reset 5 2 1 Power up Reset When the system is disconnected from AC power all logic on the Server Board is powered off When a valid input AC voltage level is provided to the power supply 3 3 V standby power is applied to the Server Board A power monitor circuit on 3 3 V standby asserts N_RST_BMCRST_L causing the BMC to reset The BMC is powered by 3 3 V standby and monitors and controls key events in the system related to reset and power control After the system is turned on the power supply asserts the PWHRGD 00 signal after all voltage levels in the system have reached valid levels The BMC receives PWRGD 00 after approximately 500 ms it asserts RST P6 PWHRGOOD which indicates to the proc
46. different as shown in Table 80 ICMB External Cable Connectors The electrical specifications for this cable are available in chapter eight of the PMI Intelligent Chassis Management Bus Bridge Specification version 1 0 available at the following URL on the Intel web site http developer intel com design servers ipmi license icmb11 old htm Table 90 ICMB External Cable Connectors Product Code Female Jack for External Cable AXX2ICMBKIT Universal ICMB card for integration with Keyed RJ45 Type B SCB2 SDS2 Revision 1 2 105 Order Number A85874 002 Errata Listing Intel Server Board SDS2 13 Errata Listing 13 1 Summary Errata Table The following tables indicate the errata and the document changes that apply to the Intel Server Board SDS2 Intel intends to fix some of the errata in a future stepping of components and to account for the other outstanding issues through documentation or specification changes as noted The tables use the following notations Fix Intel intends to fix this erratum in a future release of the component Fixed This erratum has been previously fixed NoFix There are no plans to fix this erratum Table 91 Errata Summary Description of Errata Intel RAID controller SRCMR not yet supported with Intel Server Board SDS2 Un Intel amp Server Board SDS2 BIOS update utility does not allow updates from a PXE server or from network drives Intel Server Board SDS2 FRU SDR update
47. fails with console redirection enabled in BIOS Setup First characters and arrow keys not echoed with console redirection 5 Fixed Intel amp ICP Vortex RAID Controllers will cause the Intel Server Board SDS2 to halt during POST when the BIOS Logo screen is enabled EE Intel8 Server Board SDS2 CD ROM issues NIC driver set 5 12 v 2 3 25 for UnixWare 7 1 1 drops DPC LAN connection Un NIC driver set 5 12 v 5 41 27 for Microsoft Windows 2000 prevents a DPC LAN connection when the operating system is loaded 9 Fixed Extended RAM step disable option in BIOS Setup has no effect High resolution video modes do not work correctly Lower performance with CAS Latency 2 memory SDS2 reboots during POST with 4GB or more of total system memory installed Novell NetWare v 6 0 does not install on SDS2 Adaptec 2100S RAID controller causes system lockup and video blanking 15 SDS2 Build Your Own BYO Platform Confidence Test PCT v 1 00 fails on first test run SDS2 0B71 System temperature out of the range POST message SDS2 0B75 System Voltage out of the range POST message 118 Mixcellaneous numeric keys entered during POST will enable PXE boot EN Fixed SDS2 board level operating temperature and power supply voltage tolerance modification Fab 5 Recommendation for SDS2 rubber bumper installation is on the base SC5200 Chassis Fab 5 106 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing 21 Fixed Keyb
48. mode Mode 2 Mode 3 Mode 4 Mode 5 Table 34 Processor Settings Submenu Selections Featre Option Description Processor Retest No If yes BIOS will clear historical processor status and Yes retest all processors on the next boot Processor POST Information Only Displays measured processor speed speed setting Processor 1 CPUID CPUID Reports CPUID for Processor 1 if present If empty Not Installed reports Vacant If disabled by BMC reports Disabled Disabled Processor 1 L2 Information Only Displays L2 Cache Size for Processor 1 Cache Size Processor 2 CPUID CPUID Reports CPUID for Processor 2 if present If empty Not Installed reports Vacant If disabled by BMC reports Disabled Disabled Processor 2 L2 Information Only Displays L2 Cache Size for the next Processor Cache Size Revision 1 2 57 Order Number A85874 002 BIOS Intel Server Board SDS2 6 3 2 3 2 Advanced Menu Selections The following tables describe the menu options and associated submenus available on the Advanced Menu Please note that MPS 1 4 1 1 selection is no longer configurable The BIOS always builds MPS 1 4 tables Table 35 Advanced Menu Selections Memory Select sub menu Configuration PCI Configuration Selects sub menu Device peripheral Selects sub menu Configuration Advanced Chipset Select sub menu Control Boot time Diagnostic Disabled If enabled the BIOS will display the OEM logo during Screen Ena
49. nwupdate 3 Copy server exe from the SP1 directory startup into the nwupdate directory 4 Launch the Novell NetWare v 6 0 install and select to use the existing boot partition 14 Adaptec 2100S RAID controller causes system lockup and video blanking Problem Implication 114 When an Adaptec 2100S RAID controller is installed in the SDS2 server board the video will blank and the system will lock up during POST when the onboard SCSI controller option ROM is set to Enabled in the SDS2 BIOS setup defalt option The Adaptec 2100S RAID controller cannot be used with the SDS2 server board when the onboard SCSI controller option ROM is set to Enabled in the SDS2 BIOS setup Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing Workaround Status This issue does not occur when the SDS2 onboard SCSI controller option ROM is set to Disabled To disable the SDS2 onboard SCSI controller option ROM access the Intel Server Board SDS2 BIOS Setup by pressing F2 during POST In BIOS Setup change the Advanced gt PCI Configuration gt Embedded SCSI gt Option ROM Scan option to Disabled Fixed This issue is fixed in SDS2 BIOS Production Release 2 5 Build 48 and later versions 15 SDS2 Build Your Own BYO Platform Confidence Test PCT v 1 00 fails on the first run Problem Implication Workaround Status The first time the SDS2 BYO PCT v 1 00
50. place hold Revision 1 2 67 Order Number A85874 002 BIOS Intel Server Board SDS2 This file is loaded into the PHLASH program with the b bin file gt The disk created by the BIOS EXE program automatically runs PHLASH s o PLATCXLU BIN command in non interactive mode For a complete list of PHLASH options run PHLASH h Once an update of the system BIOS is complete the user is prompted for a reboot The user binary area is also updated during a system BIOS update User binary can be updated independently of the system BIOS CMOS is cleared when the system BIOS is updated 6 4 2 User Binary Area The BIOS flash ROMincludes a 16 KB area in flash for implementation specific OEM add ons The user binary area can be saved and updated The valid extension for user files is ROM 6 4 3 Language Area The system BIOS language area can be updated only by updating the entire BIOS The BIOS supports English Spanish French German and Italian These languages are selectable using Setup 6 4 4 OEM Logo Screen A 128 KB region of Flash ROMis available to store the OEM logo in compressed format The BIOS contains the standard Intel logo Using the Phoenix PHLASH utility this region can be updated with an OEM supplied logo image The OEM logo must fit within 640 X 384 size If an OEM logo is flashed into the system it overrides the built in Intel logo 6 4 5 Recovery Mode The SDS2 baseboard supports a method for performin
51. three PCI bus segments Table 4 Bus Segment Characteristics P32 A 33 MHz Slots 3 and 4 Full Length P64 B 64 bits 66 MHz Slots 1 and 2 Full Length P64 C 64 bits 66 MHz Slots 5 and 6 Full Length Note When an add in 33 MHz PCI card is plugged into a P64 bus segment such as in the P64 C slot 5 this reduces the bus speed for all devices attached to that bus segment including the on board SCSI controller 4 1 1 32 bit 33 MHz PCI Subsystem All 32 bit 33 MHz PCI for the SDS2 Server Board is directed through the HE SL North Bridge The 32 bit 33 MHz PCI segment created by the HE SL is called the P32 A segment The P32 A segment supports full length full height PCI cards and contains the following embedded devices and connectors e 20 30 Graphics Accelerator ATI RAGE XL Video Controller Two Network Interface Controller Intel 82550 Fast Ethernet Controller e PCI Slots 4 CSB5 South Bridge PCI to LPC bridge Each of the embedded devices above except for the CSB5 South Bridge is allocated a GPIO to disable the device 4 1 1 1 Device IDs IDSEL Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD 31 16 which acts as a chip select on the PCI bus segment in configuration cycles This determines a unique PCI device ID value for use in configuration cycles The following table shows the bit to which each IDSEL signal is attached for P32 A devices and c
52. timing parameters Table 84 Voltage Timing Parameters All main outputs must be within regulation of each other within this time All main outputs must leave regulation within this time 400 msec Revision 1 2 95 Order Number A85874 002 Electrical and Thermal Specifications 96 Order Number A85874 002 Intel Server Board SDS2 Revision 1 2 Intel Server Board SDS2 Electrical and Thermal Specifications Electrical and Thermal Specifications Intel Server Board SDS2 10 4 Estimateded Server Board MTBF The estimated Mean Time Between Failures MTBE is calculated at 103 996 hours at a maximum operating temperatur The table below shows the calculated 13 Output Voltage Timing Table 87 Estimated SDS2 Server Board MTBF 0 _ ce Tar a i 42 Bee zE 2 o Tj D 2 ino 9 pie E b 32 PT 00071 ED CD DLP 5 Delong fe tom PRON acd msec pe S E TS an a e e gd 103 Delay from output voltages within regulation limits to Delay rom reguaiioniimie 1o PWOKasceredal asserted at insect Failure Rate tunon on MTBF h pwok Delay from Delay from PWOK de asserted to output voltages 3 3V 5V 12V 42V de asserted to
53. 3 I Error handling 34 35 I O APIC 17 20 21 Error logging 35 I O bridge 8 10 Error pins 32 I O Bridge 8 10 31 ESCD parameter block 65 I O bus 11 Event Logging 39 I O subsystem core 8 Event Trigger 37 bus 8 Exit Menu 51 54 64 ID button 33 ID LED 33 75 F IDE channels 16 80 IDE controller 8 IDSEL signal 11 12 IMBus interface 9 10 Install 47 Intellogo 66 Interrupt Controller 45 Fan connectors 84 Fan speed measurement 27 Fan tachometers 27 Fast IDE controller 16 Fault Resilient Booting 29 flash ROM 34 Flash ROM 65 66 peat Floppy connector 3 81 85 K Form factor 2 Front panel connector 3 86 keyboard and mouse 18 19 83 Front Panel reset 45 Keyboard Command Bar 51 52 Front Panel Temp 40 Full duplex support 15 L Language 54 66 G LED indicators 75 General purpose I O 16 Legacy support 2 General Purpose Logic I O 27 Load slew rate 95 Generator ID 35 Low speed legacy I O 8 Get SDR Time command 43 LPC bus 2 8 16 Get SEL Time command 43 LVDS SCSI channel terminator 40 GPI pin 17 LVDS SCSI channel2 terminator 1 40 GPIO 8 11 17 18 GPIO pins 8 M GPO pin 17 Main Menu 51 52 54 Graphics accelerator 2 9 14 Memory 39 Graphics Accelerator 11 Memory capacity 2 6 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Memory configuration requirements 6 Memory controller 2 4 6 8 Memory interleaving 6 Memory scrubbing 6 9
54. 4 6 1 7 Wake up Control The SIO contains functionality that allows various events to control the power on and power off of the system Revision 1 2 19 Order Number A85874 002 Subsystem Intel Server Board SDS2 4 6 2 BIOS Flash The SDS2 Server Board incorporates Fairchild 2917 008 8Mbit Flash ROM The flash device is connected through the X bus of the CSB5 47 Interrupt Routing The SDS2 Server Board interrupt architecture implements both PC compatible PIC mode and APIC mode interrupts through the use of the integrated I O APICs in the CSB5 4 7 1 Legacy Interrupt Routing For PC compatible mode the CSB5 provides two 82C59 compatible interrupt controllers The two controllers are cascaded with interrupt levels 8 15 entering on level 2 of the primary interrupt controller standard PC configuration A single interrupt signal is presented to the processors to which only one processor will respond for servicing The CSB5 contains configuration registers that define which interrupt source logically maps to I O APIC INTx pins Interrupts both PCI and IRQ types are handled by the CSB5 The CSB5 then translates these to the APIC bus The numbers in the table below indicate the CSB5 PCI interrupt input pin to which the associated device interrupt INTA INTB INTC INTD is connected The CSB5 s I O APIC exists on the I O APIC bus with the processors Table 12 PCI Interrupt Routing Sharing PCI Slot 1 P64 B PCI Slot 2
55. 74 002 Intel Server Board SDS2 Subsystem e The scatter gather mechanism supports both DMA and PIO IDE drives and ATAPI devices e Support for ATA and ATAPI PIO Mode 0 1 2 3 4 DMA Mode 0 1 2 and Ultra DMA Mode 0 1 2 3 4 5 e The IDE drive transfer rate is capable of up to ATA 100 100 MB sec per channel 4 5 3 USB Interface The CSB5 contains a USB controller and four USB hubs The USB controller moves data between main memory and the four USB connectors The SDS2 Server Board provides a three external USB connector interface on the rear I O One additional USB is supported internally through a 10 pin header 2 X 5 that can be cabled to a front panel board All four ports function identically and with the same bandwidth The USB Specification Revision 1 1 defines the external connector Table 68 10 pin USB Connection Header 2 x 5 Pin out 4 5 4 Compatibility Interrupt Control The CSB5 provides the functionality of two 82C59 PIC devices for ISA compatible interrupt handling 4 5 5 APIC The 5 5 integrates a 32 entry I O APIC that is used to distribute 32 PCI interrupts It also includes an additional 16 entry I O APIC for the distribution of legacy ISA interrupts 4 5 6 Power Management One of the embedded functions of CSB5 is a power management controller The SDS2 Server Board uses this to implement ACPI compliant power management features The 5052 supports sleep states SO 1 S4 and 55 4 5 7 G
56. 89 Figure 12 5052 Configuration Jumper Locations 90 Figure 13 Output Voltage TIImilig rs oco md oe mit lta pec a re 97 Figures pd Turre On Off 98 Figure 15 SDS2 Server Board Mechanical Drawing sese 101 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 List of Tables List of Tables Table 1 SDS2 Intel Pentium Processor Support 4 Table 2 Memory DIMM Pairs 7 Table 3 Addresses for DIMM Sale oc tame nt iad nico a ton 8 Table 4 PCI Bus Segment 4 444444000 11 Tables P32 Config tation IDs 12 Table 6 P32 A Arbitration Connections 12 Table 7 P64 B Arbitration Gonrnectlorts Re ve idem 13 Table 8 P64 B Arbitration hen UH m bete 13 Table 9 ise ET 15 Table 10 CSB5 GPIO Usage Table 17 Table 11 S per l O GPIO Usage e orn eer ee i S ege gas 18 Table 12 PCI Interrupt Routing Sharing assit pet etr T e Retro eb Coo bn Plebe 20 Table 13 Interrupt Definitions i or Re tr e enr Rt ento o Dr weed 20 Table 14 ADMT1026 Input Denpitioh x i ctr ei
57. A58285 402 or 403 and FAB5 PBA A58285 502 The following figure details the locations of these jumpers Revision 1 2 89 Order Number A85874 002 Jumpers Intel Server Board SDS2 90 i E CN50 FUNCTION fi kaj Chassis Intrusion a FUNCTION CPU Frequency Select CPU Frequency Select 1 CPU Frequency Select CPU Frequency Select RSV RSV 4 27 Mud CN FUNCTION FONG TION CMOS Clear N BIOS Write Protect A Password Disable BMC Write Protect RSV RSV BIOS Recovery 2 Spare Jumper d Figure 12 SDS2 Configuration Jumper Locations Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Jumpers The following tables describe each jumper options Table 78 System Configuration Jumper Options Description CMOS When CN42 s pins 1 and 2 are OPEN default CMOS contents are preserved through the system Clear reset When they are CLOSED CMOS contents are set to manufacturing default during system reset Password When CN42 s pins 3 and 4 are OPEN default the current system password is maintained during Disable a system reset When they are CLOSED the password is cleared disabled on reset BIOS When CN42 s pins 9 and 10 are OPEN default the system attempts to boot using the BIOS Recovery programmed in the Flash memory When they are CLOSED the BIOS attempts a recovery boot
58. B 31 1 44 1 25Mb 372 2 88 MB 37 Legacy Floppy B Disabled Hidden if not detected 720 KB 31 1 44 1 25 MB 2 88 MB 37 Hard Disk Pre delay Disabled Allows slower spin up drives to come reagy 3 seconds 6 seconds 9 seconds 12 seconds 15 seconds 21 seconds 30 seconds Sseksseme Sees ProcessorSetings Revision 1 2 55 Order Number A85874 002 BIOS Intel Server Board SDS2 Feature Spanish Italian French German Table 33 Primary Master and Slave IDE Submenu Selections 1 Description Select the byte of device that is attached to the IDE None Channel CDROM If User is selected the user will need to enter the parameters of IDE device cylinders head and User sectors ATAPI Removable IDE Removable Other ATAPI CHS format 1 to 2048 Number of Cylinders on Drive This field is only Oylinders changeable for Type User This field is informational only for Type Auto CHS format Heads Number of read write heads on Drive This field is only available for Type User This field is informational only for Type Auto CHS format Sectors Number of Sectors per Track This field is only available for Type User This field is informational only for Type Auto CHS format See description Computed size of Drive from Cylinders Heads and
59. BMC Force Update 92 9 2 1 Performing CMOS Cleats 92 9 2 2 Performing BIOS Recovery BOOL ati tetro oe hn te o RR 92 9 2 3 Performing BMC Force Update uo D er ean ur ap re b ed eee 93 10 Electrical and Thermal Specifications 94 10 1 Absolute Maximum obse 94 10 2 Power GConsumplionz usce p E DEEP a I ER ed UN RE PE 94 10 9 Power Supply SUSCIISITTOE Docet oi ood 95 10 3 1 Power rre tro t are rompe ders 95 10 3 2 Voltage Recovery Timing 98 10 4 Server Board MTBF 100 11 Mechanical Speclficatlons iieri ioter mr iii elie ieee 101 12 Regulatory and Integration Information eese 102 12 1 Regulatory otiose cate hice titre ett eae 102 12 2 Installation 103 125232 Ense EMO ct TE ee 103 12 2 2 Ensure Host Computer and Accessory Module Certifications 104 12 2 3 Prevent Power Supply 104 12 2 4 Place Battery Marking on 104 12 2 5 Use Only for Intended Applications
60. Board Digital Presence Thermal Trip IERR Processor Sensor Proc 1 Status 5Fh 07h Specific 6Fh FRB1 FRB2 FRB3 Disabled Presence Thermal Trip IERR Processor Sensor Proc 2 Status 60h 07h Specific 6Fh FRB1 FRB2 FRB3 Disabled Fault Status Slot Connector Sensor Asserted 21h Specific 6Fh Device Installed Disabled Fault Status Slot Connector Sensor Asserted DIMM 1 E EDS 21h Specific 6Fh Device Installed Disabled Fault Status Slot Connector Sensor Asserted Smp 21h Specific 6Fh Device Installed Disabled Fault Status Asserted DIMM 4 6Bh Slot Connector Sensor DIMM 5 21h Specific 6Fh Device Installed Revision 1 2 43 Disabled Fault Status Order Number A85874 002 Slot Connector Sensor Asserted 21h Specific 6Fh Device Installed Disabled BIOS Intel Server Board SDS2 Sensor Name DIMM 6 System ACPI Power State Event Event Reading Offset Sensor Type Triggers Fault Status Slot Connector Sensor Asserted 21h Specific 6Fh Device Installed Disabled System ACPI 1 Sensor Power State Specific 6Fh S4 22h S5 G2 G3 Mechanical Off System Event SMI Timeout System Event Sensor OEM System Boot 12h Specific 6Fh Event Hard Reset SMI Timeout Sensor F3h Speciic ern State Asserted device not found Sensor Failure Sensor device error F6h Specific 6Fh detected Bus T
61. Intel Server Board SDS2 Technical Product Specification Order Number A85874 002 Revision 1 2 a ntel December 2 2002 Enterprise Platforms and Services Marketing Revision History Intel Server Board SDS2 Revision History Revision Modifications Number 5 15 2002 1 1 Added Section 13 Errata Corrected miscellaneous document errors Added Table 6 2 5 4 Baseboard Management Controller BMC Beep Code Generation 12 2 02 1 2 Added Errata 19 37 that are corrected with FAB5 Updated Table 6 2 5 4 Added Table 25 ii Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Disclaimers Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or
62. LEE 51 Table Utility Seer icto bu teat a op pa den 52 Revision 1 200000 XP Order Number A85874 002 List of Tables Intel Server Board SDS2 Table Men Selections 55 Table 33 Primary Master and Slave IDE Submenu Selections 56 Table 34 Processor Settings Submenu 57 Table 35 Advanced Menu Selectlofis inus merces toa termo tese pan 58 Table 36 Memory Configuration Menu Selections 58 Table 37 PCI Configuration Menu Selections 59 Table 38 On board SCSI and LAN Submenu 59 Table 39 On board VGA Submenu Selections sse 59 Table 40 PCI slot Submenu Selections ete 59 Table 41 I O Device Peripheral Configuration Submenu 5 61 Table 42 Advanced Chipset Controller Submenu 62 Table 43 PCI Device Submenu Selections eret eene tende 62 Table 44 Security Menu Selections rrt eter trag ox 62 Table 45 Server Menu SelectiorT8 aoncacdest Ei ea d pts peret eden aie 63 Table 46 System Management Submenu Selections 64 Table 47 Console Redirection Submenu
63. MIRQ 32 Missing CPU Module 41 MPS 57 Multiple bit error detection 6 Multiple bit errors 4 N N KBD PINITL 30 N_PWRGD 00 30 RST BMCRST 28 30 N RST P6 PWRGOOD 30 N844077 19 Network Interface Controller 2 11 NIC connector 85 NMI 39 North Bridge 2 4 8 9 11 31 NVRAM 65 NVRAM modification 51 NVRAM LST file 65 OEM logo 57 66 P32 A 2 9 11 12 19 20 P64 B 2 10 11 12 13 19 20 68 P64 C 3 10 11 12 13 19 20 68 Parallel port 18 19 83 85 Password settings 65 PC87417 18 31 PCI bus segments 11 PCI masters 12 13 PDB Temp 40 PERR 32 37 76 77 Phlash 34 PHLASH utility 65 66 Physical Security ViolationlI 39 PIO Mode 17 PLATCBLU BIN 65 PLATCXLU BIN 65 66 PLATCXLX BIN 65 PLATCXXX BIN 65 Platform Security Violation 39 Revision 1 2 Index Plug N Play Auto configuration Manager 51 Port 80h card 44 POST 45 POST codes 44 POST Error 39 POST error codes 43 49 POST routines 51 Postcard 44 Power connector 72 86 Power consumtion 92 Power control buttons 75 Power Status 39 Power supply connection 72 Power Unit Reduncancy 39 Power on Self Test See POST 45 Power up Reset sequence 30 Proc 1 Status 42 Proc 1 Temp 40 Proc 2 Status 42 Proc 2 Temp 40 Processor BIST failure 38 Product ID string 34 Protection diode 14 Q Quiet Boot Logo 65 R RAGE XL 2 9 11 12 14 20 78 RAIDIOS 14 Realt
64. P64 B PCI Slot 3 P32 A 7 PCI Slot 4 P32 A E ET FW acp pn pipe BECOME OI BENE IE n 1 11 12 1 13 11 1 12 13 1 11 12 1 13 11 1 1 4 PCI Slot 6 P64 C 10 7899W SCSI Ch A 3 2 1 3 2 1 1 4 7 1 1 Legacy Interrupt Routing The table below recommends the logical interrupt mapping of interrupt sources on the SDS2 Server Board The actual interrupt map is defined using configuration registers in the CSB5 Table 13 Interrupt Definitions 20 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Subsystem D Ros LEE EE mon SMI System Management Interrupt General purpose indicator sourced by the CSB5 and BMC to the processors SCI System Control Interrupt Used by system to change sleep states and other system level type functions 4 7 2 APIC Interrupt Routing For APIC mode the 5052 interrupt architecture incorporates three Intel I O APIC devices to manage and broadcast interrupts to local APICs in each processor The I O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA compatibility interrupts IRQ 0 15 When an interrupt occurs a message corresponding to the interrupt is sent across a three wire serial interface to the local APICs The APIC bus minimizes interrupt latency time for compatibility interrupt sources The I O APICs
65. R IU qe ttm v EE 81 xii Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 List of Tables Table 66 IDE 40 Connector 82 Table 67 Stacked Three port USB Connector 82 Table 68 10 pin USB Connection Header 2 x 5 83 Table 69 34 pin Floppy Connector nnne 84 Table 70 DBS Setial POH riti tte estate idet bei Ri DH ea ua ERE 84 Table 71 10 pin Header Serial Port Pin out sess enne 84 Table 72 DB25 Parallel Port soeur ot be uo Depto 85 Table 73 Keyboard and Mouse PS 2 Connector 85 Table 74 Header Pi iO uit ouk Ft dev uk RO Cui axi FR ER ge iw Ee 86 Table 75 Chassis Intrusion Header nennt 86 Table 76 External Drive Activity Header Pin out eese 87 Table 77 Server Board Connector Manufacturer Part 87 Table 78 System Configuration Jumper 91 Table 79 CPU Frequency Select Jumper 91 Table 80 List of Assembled Jumpers in Production seenen 92 Table 81 Absolute Maximum Ratings sai
66. Socket370 e Server Works ServerSet IIl HE SL chipset HE SL North Bridge CIOB20 I O Bridge CSB5 South Bridge Support for six PC 133 compliant registered ECC SDRAM memory modules e 32 0 33 MHz 5 V Full length PCI segment A P32 A with three embedded devices 2D 3D Graphics Controller RAGE XL Video Controller with 4MB of SDRAM Two Network Interface Controller Intel 82550 Fast Ethernet Controller Two 32 bit Slots PCI Slots 3 and 4 e 64 bit 66 MHz 3 3 V full length PCI segment B P64 B Two 64 bit Slots PCI slots 1 and 2 2 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Architecture 64 bit 66 2 3 3 V full length PCI segment C P64 C with one embedded device Dual Channel Wide Ultra160 SCSI controller Adaptec AIC 7899W Two 64 bit 3 3 V Slots PCI slots 5 and 6 e LPC Low Pin Count bus segment with two embedded devices Baseboard Management Controller BMC providing monitoring alerting and logging of critical system information obtained from embedded sensors on the Server Board Super controller chip providing all PC compatible I O floppy serial keyboard mouse e X Bus segment from CSB5 with one embedded device Flash ROM device for system BIOS Fairchild 29LV008B 8Mbit Flash ROM e Two IDE connectors supporting up to two ATA 100 compatible devices each Note Fab 4 board PBA A58285 402 and 403 supported only one IDE connector Fab 5 PBA A58285 502 and lat
67. TA Bus 133MHz ADD CTRL Bus 133MHz me DATA Bus 133MHz Channel A Channel B Figure 1 SDS2 Server Board Block Diagram Revision 1 2 1 Order Number A85874 002 Architecture Intel Server Board SDS2 2 Architecture The SDS2 Server Board is a monolithic printed circuit board that can accept two Intel Pentium processors using the Socket 370 FCPGA2 package The SDS2 Server Board complies with the Entry SSI version 1 0 and ATX version 2 03 12 inch x 13 inch form factor It is designed around the Server Works ServerSet HE SL chipset The chipset contains three components e The HE SL CNB20 North Bridge provides an integrated memory controller e The CIOB20 Bridge provides the interface for two peer 64 bit 66 MHz PCI busses The CSB5 South Bridge provides the LPC bus for legacy support The Server Board also contains other embedded devices such as e 20 30 graphics accelerator Two 10 100 Network Interface Controller e Dual channel Ultra160 SCSI e Standard I O e Server management The SDS2 Server Board provides six DIMM sockets for a maximum memory capacity of 6 GB Only registered PC 133 compliant Registered SDRAM memory modules are supported The current tested memory listing is posted on the Intel technical support web site http support intel com support motherboards server SDS2 The SDS2 Server Board provides the following features e Dual Intel Pentium FCPGA2 processors
68. TF The events that the BIOS supports are shown in the following table Table 25 Event Request Message Event Data Field Contents ASFCode Description Commet Memory initialization At beginning of ECC initialization or memory test Hard disk initialization At beginning of IDE device detection Secondary processor s initialization At beginning of MP Init User authentication When waiting for User Supervisor password User initiated system setup When Setup is invoked USB resource configuration When USB devices scan initialization begins Keyboard controller initialization At keyboard discovery scan 0 0 0 0 0 0 0 0 0 0 0 0 Cache initialization At beginning of setting up processor cache SM Bus initialization At beginning of configuring SMBus to communicate with BMC Embedded controller management When first checking for functional BMC controller initialization Calling operating system wake up When waking from Wake On LAN Wake On Ring vector Magic Packet etc Starting operating system boot Immediately prior to calling INT19h process e g calling Int 19h 6 2 5 2 POST Codes The BIOS indicates the current testing phase to I O location 80h and to LCD on the front panel during POST after the video adapter has been successfully initialized If a Port 80h card Postcard is installed it displays this 2 digit code on a pair of hex display LEDs Video initialization At beginning of initialization primary video controlle
69. a Listing Intel Server Board SDS2 In addition to this message the SC5100 front panel system status LED will light solid amber indicating a system temperature fault This condition will continue to appear during POST each time the SDS2 system is rebooted until AC power is removed from the system by disconnecting the AC power cord Implication The described condition will appear if the SC5100 front panel cable is disconnected from the SDS2 server board and then reconnected while 5V standby voltage is applied to the system Workaround the AC power cord from the system will clear this condition Status NoFix Disconnecting and reconnecting the SC5100 front panel cable from the SDS2 server board while 5V standby voltage is applied to the system is not a supported action This action causes the SC5100 front panel temperature sensor to report an invalid temperature reading Customers must disconnect the AC power cord from the SDS2 SC5100 system before disconnecting or reconnecting the SC5100 front panel cable to the server board 17 SDS20B75 System Voltage out of the range POST message Problem The following message may be encountered during POST when SDS2 FRU SDR files v 5 0 B and previous versions are programmed on the SDS2 server board System Monitoring Check 0B75 System Voltage out of the range Press F1 to override boot suppression or F2 to enter Setup This issu Implication The descri
70. ader is detailed in the following table that is representative of the Foxconn HL07051 P9 Housing located at CN18 Pin 6 5Volts i 9 GND 10 USB 4 D cope PORTA D Pin1 N C Pin2 N C Pin 3 Pin 4 N C Pin 5 KEY Table 68 10 pin USB Connection Header 2 x 5 Pin out Pin Signal name Ne Fused 5 V USB_PORT4_D 8 USB_PORT4_D GND ND 8 6 6 Floppy Connector The following table details the pin out of the 34 pin floppy connector Revision 1 2 83 Order Number A85874 002 Connections Intel Server Board SDS2 Table 69 34 pin Floppy Connector Pin out Pin Signal Name Pin Signal Name s romae r sw fe FONE 8 6 7 Serial Port Connector Two serial ports are provided on the Server Board one DB9 connector is located on the rear I O to supply COM1 and a 10 pin header at location CN33 provides COM2 The following tables detail their connector pin outs Table 70 DB9 Serial Port Pin out Data Carrier Detect Data Terminal Ready s 058 Data s ois CieartoSend s Table 71 10 pin Header Serial Port Pin out 84 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 in Sara name Duci 2 Receive Data s 058 DwaSeey s fes Gieartosend s RI 8 6 8 Parallel Port One DB25 parallel port connector is provided on the rear I O The following table details the pin
71. an 5 Alarm occurred 0B50 0B51 0B60 0B61 0B62 0B70 Processor 1 with error taken offline Processor 2 with error taken offline DIMM group 1 has been disabled DIMM group 2 has been disabled DIMM group 3 has been disabled The error occurred during temperature sensor Error while detecting a temperature failure reading System temperature out of the range Temperature error detected The error occurred during voltage sensor reading Error while detecting voltage 0B71 0B74 6 2 5 4 Baseboard Management Controller BMC Beep Code Generation The BMC generates beep codes upon detection of the failure conditions listed in the following table Each digit in the code is represented by a sequence of beeps whose count is equal to the digit Table 30 BMC Beep Codes Revision 1 2 51 Order Number A85874 002 BIOS Intel Server Board SDS2 Reason for Beep 1 5 1 1 FRB failure processor failure Chipset control failure 6 3 Setup Utility This section describes the ROM resident Setup utility that provides the means to configure the platform The Setup utility is part of the system BIOS and allows limited control over on board resources such as parallel port and mouse The following topics are covered here e Setup utility operation e Configuration CMOS RAM definition e Function of CMOS clear jumper 6 3 1 Configuration Utilities Overview On board devices are configured through the Setup utility that is em
72. an integrated I O bridge that provides a high performance data flow path between the IMBus and the 64 bit I O subsystem This subsystem supports peer 64 bit PCI segments Because it has multiple PCI interfaces the CIOB can provide large and efficient I O configurations The CIOB functions as the bridge between the IMBus and the multiple 64 bit PCI I O segments The IMBus interface can support 512 MB s of data bandwidth in both the upstream and downstream direction simultaneously The internal PCI arbiter implements the Least Recently used algorithm to grant access to requesting masters 3 3 2 1 PCI Bus P64 B I O Subsystem P64 B supports two 64 bit 66 MHz 3 3V full length PCI slots 3 3 2 2 PCI Bus P64 C I O Subsystem P64 C supports the following embedded devices and connectors Dual Channel Wide Ultra160 SCSI controller Adaptec AIC 7899W e Two 64 bit 66 MHz 3 3V full length PCI Slots 3 3 3 CSB5 South Bridge Please refer to Section 4 5 for information on CSB5 10 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Subsystem 4 O Subsystem 41 Subsystem The primary bus for SDS2 DP Server Board is PCI with three PCI bus segments The PCI buses comply with the PCI Local Bus Specification Rev 2 2 The P32 A bus segment is directed through the HE SL North Bridge while the two 64bit segments P64 B and P64 C are directed through the CIOB20 I O Bridge The table below lists the characteristics of the
73. ard SDS2 Regulatory and Integration Information 12 2 5 Use Only for Intended Applications This product was evaluated for use in ITE computers that will be installed in offices schools computer rooms and similar locations The suitability of this product for other product categories other than ITE applications such as medical industrial alarm systems and test equipment may require further evaluation 12 2 6 Installation Precautions During the installation and testing of the board the user should observe all warnings and cautions in the installation instructions To avoid injury be aware of the following e Sharp pins on connectors e Sharp pins on printed circuit assemblies e Rough edges and sharp corners on the chassis e Hot components like processors voltage regulators and heat sinks Damage to wires that could cause a short circuit e Observe all warnings and cautions that instruct you to refer computer servicing to qualified technical personnel WARNING Do not open the power supply There is risk of electric shock and burns from high voltage and rapid overheating Refer servicing of the power supply to qualified technical personnel 12 2 7 External ICMB Cable Information When the ICMB accessory is incorporated as part of a server solution the external cable used to connect the ICMB cards will need to be manufactured Note the female connectors on the early version and the universal version of the ICMB cards are
74. atform Confidence Test to extract to 7 Reboot your system using the floppy diskette 8 You will be asked to agree to a licensing agreement prior to the actual file expansion occurring The agreement is the file LEGAL TXT 9 ARAMDRIVE will be created into which the diagnostic tests are copied 10 When the copy process is complete you will be presented with a menu of five options These menu options are discussed in greater detail in the Platform Confidence Test manual Rev 2 2 Fixed The SDS2 system resource CD ROM with part number A58098 003 has corrected these issues 7 driver set 5 12 v 2 3 15 for UnixWare 7 1 1 drops DPC LAN connection Problem Implication Workaround Status When the NIC driver set 5 1 2 v 2 3 15 for UnixWare 7 1 1 is utilized on the Intel Server Board SDS2 the DPC LAN connection to the SDS2 server is dropped when a power control action is initiated NIC driver set 5 1 2 v 2 3 15 for UnixWare 7 1 1 should not be used with the Intel Server Board SDS2 if DPC LAN is being used Intel recommends using the driver version embedded in the UnixWare 7 1 1 operating system CD ROM distribution v 1 3 9 in order to avoid this failure Fixed Intel recommends using the driver version embedded in the UnixWare 7 1 1 operating system CD ROM distribution v 1 3 9 as the fix for this issue 8 NIC driver set 5 12 v 5 41 27 for Microsoft Windows 2000 prevents a DPC LAN connection when the o
75. bed condition may appear if SDS2 FRU SDR files v 5 0 B or previous versions are programmed on the SDS2 server board Workaround Disconnecting the AC power cord from the system will clear this condition Status Fixed SDS2 FRU SDR files v 5 0 B and previous versions contain slightly incorrect SDR values for the Vbat voltage battery backup voltage The Vbat voltage sensor values have been corrected in SDS2 FRU SDR files v 5 0 D and later versions 18 Miscellaneous numeric keys entered during POST enable PXE boot Problem Entering various numeric key sequences during POST will cause the SDS2 system BIOS to enter the PXE boot sequence The BIOS should only enter the PXE boot sequence when the F12 key is pressed during POST 116 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing Implication Workaround Status The SDS2 system BIOS will enter the PXE boot sequence if various numeric keys are pressed during POST Do not enter numeric keys during the POST process Fixed This issue is fixed in SDS2 BIOS Production Release 2 5 Build 48 and later versions 19 5052 board level operating temperature and power supply voltage tolerance modification Problem Implication Workaround Status In Table 73 of the Intel Server Board SDS2 Technical Product Specification TPS Rev 1 0 the board level operating temperature is specified as 0 C to 55 C In Table 75 of the SDS2 TPS Rev
76. bedded in flash ROM Setup provides enough configuration functionality to boot a system diskette or CD ROM Setup is always provided in flash for basic system configuration The configuration utilities modify the CMOS and NVRAM under direction of the user The actual hardware configuration is accomplished by the BIOS POST routines and the BIOS Plug N Play Auto configuration Manager The configuration utilities always update a checksum for both areas so that any potential data corruption is detectable by the BIOS before actual hardware configuration takes place If the data is corrupted the BIOS load the default configuration and requests that the user reconfigure the system and reboot 6 3 2 Setup Utility Operation The ROM resident Setup utility configures only on board devices The Setup utility screen is divided into four functional areas Table 31 describes each area Table 31 Setup Utility Screen Keyboard Command Bar Located at the bottom of the screen This bar displays the keyboard commands supported by the Setup utility Menu Selection Bar Located at the top of the screen Displays the various major menu selections available to the user The server Setup utility major menus are Main Menu Advanced Menu Security Menu System Menu Boot Menu and the Exit Menu 52 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS Options Menu Each Option Menu occupies the left and center sections of the screen Each menu
77. bility to perform BIOS updates from a PXE server or from network drives 3 Intel Server Board SDS2 FRU SDR update fails with console redirection enabled in BIOS Setup Problem When using Intel Server Board SDS2 BIOS Production Release 2 Build 41 BMC v 28 and FRU SDR files v 5 0 A if console redirection is set to Enabled 108 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing in BIOS Setup the following error message will appear when attempting to update the FRU SDR files Updating the FRU and Sensor Data Records Packaged file is corrupt Implication If console redirection is set to enabled in BIOS Setup the Intel Server Board SDS2 FRU SDR files cannot be updated Workaround sure that console redirection is set to disabled in BIOS Setup this is the default BIOS setting before performing a FRU SDR file update Status Fixed This issue is fixed in SDS2 BIOS Production Release 2 1 Build 44 and later versions 4 First characters and arrow keys not echoed with console redirection Problem Two issues occur with console redirection on the Intel amp Server Board SDS2 1 When booting to ROM DOS under console redirection the first character of a command is not echoed to the screen until the Enter key is pressed 2 In BIOS Setup under console redirection the arrow keys are not properly echoed when pressed Implication The first character and arrow keys are not correctly echoe
78. bled POST This option is hidden if the BIOS does not detect a valid logo in the flash area reserved for this purpose Reset Configuration No Select Yes if you want to clear the System Data Ye Configuration Data during next boot Automatically reset to No in next boot 5 Installed 5 Other If PnP O S is selected only the devices required to PnP O S boot the system are configured If Other is selected all devices are configured Off Memory Processor Boot Selects the behavior of the system in response to a Error Halt Memory or Processor reconfiguration If set to Boot the system will attempt to boot If set to Halt the system will require user intervention to complete booting Table 36 Memory Configuration Menu Selections Feature __ Description Memory Bank 1 Normal Displays the current status of the memory bank Memory Bank 2 Not Installed Disabled indicated that a DIMM in the bank has failed and the entire bank has been disabled Memory Bank 3 Disabled Memory Retest No Causes BIOS to retest all memory on next boot Yes 58 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS Extended RAM Step Disabled Selects the size of step to use during Extended 1MB RAM tests 1KB Every Location Table 37 PCI Configuration Menu Selections Feature _ Opin j Descipin Embedded SCSI 22 1 Selects sub menu Embedded NIC 1 Pe Selects sub menu Embed
79. can also supply greater than 16 interrupt levels to the processor s 4 7 3 Serialized IRQ Support The SDS2 Server Board supports a serialized interrupt delivery mechanism Serialized IRQs SERIRQ consists of a start frame a minimum of 17 IRQ data channels and a stop frame Any slave device in the quiet mode may initiate the start frame While in the continuous mode the start frame is initiated by the host controller 4 7 4 IRQ Scan for PCIIRQ The IRQ data frame structure includes the ability to handle up to 32 sampling channels with the standard implementation using the minimum 17 sampling channels The SDS2 Server Board has an external PCI interrupt serializer for PCIIRQ scan mechanism of CSB5 to support 16 PCIIRQs Revision 1 2 21 Order Number A85874 002 Subsystem Intel Server Board SDS2 IOAPIC n PCI Cvcle AAA ARA RASA AAA IRQO iO gt lt HH lt lt lt __ IRQ3 gt SCAN2 gt INT FEE Ee 8259 PIC IRQ4 PI IRQ0 15 P Mapping no 25 4 nnn esas 4 4 4 lt Pl lt 4 gt lt IRQ8 4 lt IRQ9 4 lt 4 lt CLE IRQ10 EP IRQ11 PCIIRQO P PCI Cvcle PCIIRQ1 PCIIRQ2 PCIIRQ3 SCANO lt PCIIRO4 ix us MASK for PCIIROS POIROO Ni PCIIRQO 15 PCIIROG 15 PCIIRQ7 P P PCIIRQ9 LR
80. cific 6Fh Log Area Reset Cleared BB 1 25V BB 2 5V BB 3 3V BB 3 3V Standby 5V 12 pcc 1 i Order Number A85874 002 40 Revision 1 2 Intel Server Board SDS2 Revision 1 2 BB 12V Proc VRM1 Voltage 02n Threshold Proc VRM2 13h Voltage 02h Threshold LVDS SCSI channel 1 terminator 1 LVDS SCSI channel 1 terminator 2 LVDS SCSI channel 1 terminator 3 LVDS SCSI channel 2 terminator 1 LVDS SCSI channel 2 terminator 2 LVDS SCSI channel 2 terminator 3 LVDS SCSI channel 1 Performance LVDS SCSI channel 2 Performance Baseboard Temp Front Panel Temp 01h Temp PDB Temp Proc 1 Temp Proc 2 Temp 01 Threshold Fan Boost Baseboard Temp Event Offset Triggers Event Reading Sensor Type Type 10h Voltage 02h Threshold Threshold Threshold Threshold Threshold Threshold h h h pare mre 5 5 5 5 5 5 5 5 5 5 Voltage 02h Threshold Performance Lags Digital Voltage 02h Discrete 06h Digital Voltage 02h Discrete 06h Temp 01h dip Re Performance Lags Threshold Temp 01h Threshold Temp 01h Threshold 4 5 6 7 8 9 D E 0 2 3 4 1 1 1 1 1 1 1 3 3 3 3 h h h h Threshold gt 5 5 5 5 y 5
81. cifications Intel Server Board SDS2 10 Electrical and Thermal Specifications This section describes the electrical and thermal specifications required to integrate this board in a system 10 1 Absolute Maximum Ratings Operation of the SDS2 Server Board at conditions beyond those shown in the following table may cause permanent damage to the system provided for stress testing only Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 81 Absolute Maximum Ratings Operating Temperature 0 C to 55 C Storage Temperature 55 C to 150 C Voltage on any signal with respect to ground 0 3V to 0 3V 2 3 3V Supply Voltage with respect to ground 0 3V to 3 63V 5V Supply Voltage with respect to ground 0 3V to 5 5V Notes 1 Chassis design must provide proper airflow to avoid exceeding Intel Pentium processor maximum case temperature 2 means supply voltage for the device 10 2 Power Consumption The following table shows the power consumed on each supply line for a SDS2 Server Board configured with the following manner Two processors each with 30 W max e Four DIMMs total two active burst and two standby e Three PCI cards two 3 3 V and 5V e Five fans total two processor fans and three system fans e Five SCSI HD with SCSI backplane Note The following numbers are provided as an example Actual power consumption will vary d
82. contains a set of features Selecting certain features within a major Option Menu drops you into submenus Item Specific Help Screen An item specific help screen is located at the right side of the screen 6 3 2 1 Entering Setup Utility During POST operation the user is prompted to enter Setup using the F2 function key as follows Press lt F2 gt to enter Setup Note that a few seconds might pass before Setup is entered This is the result of POST completing test and initialization functions that must be completed before Setup can be entered When Setup is entered the Main Menu options page is displayed 6 3 2 2 Keyboard Command Bar The bottom portion of the Setup screen provides a list of commands that are used for navigating the Setup utility These commands are displayed at all times for every menu and submenu Each Setup menu page contains a number of features Except those used for informative purposes each feature is associated with a value field This field contains user selectable parameters Depending on the security option chosen and in effect via password a menu feature s value can be changeable or not If a value is not changeable due to insufficient security privileges or other reasons the feature s value field is inaccessible The Keyboard Command Bar supports the following Revision 1 2 53 Order Number A85874 002 BIOS Intel Server Board SDS2 Key Option F1 Help Pressing F1 on any menu invoke
83. d to edit files after booting to the SDS2 System Resource CD ROM Users should also use the following insturctions for the BYO Platform Confidence Test Manual Rev 2 2 to create a bootable Platform Confidence Test floppy diskette Installing the Server Board Platform Confidence Test Package on the Intel Server Board SDS2 1 Insert the resource CD into a Windows based system and let the auto run feature launch the graphical user interface if auto run does not launch the GUI launch it manually by double clicking on your CDROM drive Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing Status 2 On the Utilities page drop down the menu and choose the Platform Confidence Test option 3 Click on the Create Diskette icon that appears and when prompted choose to save the file to a temporary folder on your hard drive 4 Locate the file you just saved and run the SDS2PCT exe program obtained from the CD This will extract the files for the Platform Confidence Test onto the floppy along with a file called MKBOOT BAT 5 Reboot the server to the resource CD and insert the floppy with the Platform Confidence Test files into the floppy drive 6 Exit to DOS by choosing Quit from the menu and then selecting Quit Now At the DOS prompt change to the floppy disk and execute the MKBOOT BAT file This will make your floppy disk bootable and copy over the appropriate DOS components for creating a RAMDRIVE for the Pl
84. d to the screen with console redirection Workaround user can workaround this issue by pressing the Enter key or by pressing the arrow keys several times Status Fixed This issue is fixed in SDS2 BIOS Production Release 2 1 Build 44 and later versions 5 Intel amp ICP Vortex RAID Controllers will cause the Intel Server Board SDS2 to halt during POST when the BIOS Logo screen is enabled Problem When booting the Intel Server Board SDS2 with an Intel RAID Controller or ICP Vortex RAID controller installed the system will halt during POST when the Intel Server Board SDS2 BIOS Logo screen is enabled This issue occurs only with Intel RAID Controllers running with version 6 2 6i firmware and ICP Vortex Controllers running version 28 firmware Intel has found the root cause of this issue to be an INT 10 BIOS video interrupt call during RAID POST The Intel Revision 1 2 109 Order Number A85874 002 Errata Listing Implication Workaround Status Intel Server Board SDS2 Server Board SDS2 does not service this interrupt when the BIOS Logo screen is enabled When booting the Intel Server Board SDS2 with an Intel RAID Controller or ICP Vortex RAID controller installed the system will halt during POST when the Intel Server Board SDS2 BIOS Logo screen is enabled A workaround for this issue is to press the ESC key when the Intel BIOS logo screen appears Alternately the Intel BIOS logo screen may be disabled
85. ded NIC 2 22 1 Selects sub menu Embedded Video Selects sub menu Controller Fo Table 38 On board SCSI and LAN Submenu Selections Option SCSI Controller Enabled If Disabled the BIOS will hold the embedded chip in LAN Controller 1 Disabled reset In this configuration the controller HW is LAN Controller 2 completely disabled and will be invisible to the PnP operating systems Option ROM Scan Enabled If Enabled initialize device expansion ROM Disabled Table 39 On board VGA Submenu Selections Feature Option VGA Controller Enabled If Disabled the BIOS will hold the embedded chip in Disabled reset In this configuration the controller HW is completely disabled and will be invisible to the PnP operating systems Table 40 PCI slot Submenu Selections Feature Description Revision 1 2 59 Order Number A85874 002 BIOS Intel Server Board SDS2 Option ROM Scan Enabled Enable option ROM scan of the selected device Disabled 60 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS Table 41 I O Device Peripheral Configuration Submenu Selections Feature Bescipin Serial Port 1 Disabled If set to Auto BIOS or OS configures the port Enabled Auto Base I O Address Selects the base I O address for COM port 1
86. effect unless at 10 minutes least one password is enabled 20 minutes 1 hour 2 hours Hot Key CTRL ALT A L Z 0 9 Key assigned to invoke the secure mode feature Cannot be enabled unless at least one password is enabled Can be disabled by entering a new key followed by a backspace or by entering delete Secure Mode Boot Disabled System boots in Secure Mode The user must enter Enabled a password to unlock the system Cannot be enabled unless at least one password is enabled Video Blanking Disabled Blank video when Secure mode is activated A Enabled password is required to unlock the system This cannot be enabled unless at least one password is enabled This option is only present if the system includes an embedded video controller Floppy Write Protect Disabled When Secure mode is activated the floppy drive is Enabled write protected A password is required to re enable floppy writes Cannot be enabled unless at least one password is enabled Power Switch Inhibit Disabled Determines whether power switch function from front Enabled panel 6 3 2 3 4 Server Menu Selections Table 45 Server Menu Selections X Feaue Option 7 Description System Management 555 Selects sub menu Console Redirection Redirection Psd sub menu Console Resection Partition Type the partition type of the EE M Partition the default is 12h Clear Event Log Enter If selected t
87. em Reconfigured OEM System Boot Event Hard Reset Processor Critical Interrupt E PCI SERR System Boot m Initiated by power up Initiated User requested PXE boot re Automatic boot to diagnostic Boot Error LN No bootable media Sensor Failure EE Bus Device Address Not Acknowledged mpm Bus Device Error Detected Chipset Specific LAM function 0 errors Critical Interrupt 0 errors The Event Request Message Event Data Field Contents table below describes the various fields in the event request message sent by the BIOS Revision 1 2 37 Order Number A85874 002 BIOS Intel Server Board SDS2 Table 23 Event Request Message Event Data Field Contents Event Event Data Trigger Class Discrete 00 Unspecified byte 2 01 Previous state and or severity in byte 2 10 OEM code in byte 2 11 Sensor specific event extension code in byte 2 00 Unspecified byte 3 01 Reserved 10 OEM code in byte 3 11 Sensor specific event extension code in byte 3 Offset from Event Trigger for discrete event state Event Data 2 7 4 Optional offset from Severity Event Trigger OFh if unspecified 3 0 Optional offset from Event Trigger for previous discrete event state OFh if unspecified 6 2 3 SMI Handler The SMI handler handles and logs system level events that are not visible to the server management firmware The SMI handler even those that are normally considered to generate an NMI preprocesses all system error
88. em from booting if halt on Post Error code is disabled in the BIOS Setup in the Advanced menu Sensor Name Sensor number and Sensor type for the SDS2 platform are listed in the following Table 24 Platform SEL Log Sensors for SDS2 Table 24 Platform SEL Log Sensors for SDS2 Revision 1 2 39 Order Number A85874 002 BIOS Intel Server Board SDS2 Event Event Reading Offset Sensor Triggers Power Off Power Unit Sensor Bower Gvci 09h Specific 6Fh A C Lost R Reaai Power Unit Generic OBh edundancy Regain 09h Redundancy lost Timer Expired Hard Reset Watchdog2 Sensor Bower Down 23h Specific 6Fh 9er Own Power Cycle Timer Interrupt Platform Secure mode Security Sensor violation attempt Violation Specific 6Fh Out of band access Attempt 06h password violation Power Unit Status Power Unit Redundancy Watchdog Platform Security Violation General Chassis Intrusion LAN Leash Lost System Sensor POST Error 06h Firmware ai POST error Specific 6Fh Progress OFh Physical Security Violation Physical Sensor Security 05h Specific 6Fh FP Diag Interrupt NMI for IA 32 INIT for 1 64 Event Logging Disabled Critical Sensor Interrupt 13h Specific 6Fh erent rane Mame Sensor Correctable ECC Specific 6Fh Uncorrectable ECC Correctable Memory Error Loggin Event Logging Sensor Disabled Disabled 10h Spe
89. eneral Purpose Input and Output Pins The CSB5 provides a number of general purpose input and output pins Many of these pins have alternate functions and thus all are not available The following table lists the GPI and GPO pins used on the SDS2 Server Board and gives a brief description of their function Table 10 CSB5 GPIO Usage Table GPIOName Desmptin Reporting for Fata Errors from HE such as multi bit ECC errors Bus protocol errors and FSBus parity errors MIRQL Reporting for Correctable Errors from HE SL such as single bit errors on Front Side Data bus and Memory Data bus N CIOBALERTN Reporting for errors from CIOB CSB5 Generation of NMI from 5 5 N_BMC_IRQ_SMI_00 Input from BMC of SMI event Revision 1 2 17 Order Number A85874 002 Subsystem Intel Server Board SDS2 Demun U18 FRBS3STP 00 Output signal to turn off FRB timer to stop fault conditions this signal is wire or with the 2 pin jumper 4 6 Chipset Support Components 4 6 1 Super I O The National Semiconductor PC87417 Super I O device contains all of the necessary circuitry to control two serial ports one parallel port floppy disk and PS 2 compatible keyboard and mouse The SDS2 Server Board supports the following features e e Two serial ports e Floppy e Keyboard and mouse through PS 2 connectors e Parallel port e Real time clock e Wake up control
90. epending on the exact configuration temperature voltage level etc Refer to the appropriate system chassis document for more information 94 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Electrical and Thermal Specifications Table 82 SDS2 Server Board Power Consumption Wemy 834 Baa eow sm pooo mao 82A faw Fe Feres Total Curent 828A TemPowe 80484 Total 10 3 Power Supply Specification This section provides power supply design guidelines for an SDS2 based system including voltage and current specifications and power supply on off sequencing characteristics Table 83 SDS2 Power Supply Specification Nom Max Unis Tolerance 10 3 1 Power Timing The following are the timing requirements for single power supply operation Output voltages must rise from 10 to within regulation limits rise within 5 to 70 ms The 3 3 V 5 V and 12 V output voltages begin to rise approximately at the same time All outputs must rise monotonically The 5 V output must be greater than the 3 3 V output during any point of the voltage rise however never by more than 2 25 V Each output voltage shall reach regulation within 50 ms Tyout_on Of each other and begin to turn off within 400 ms of each other The following table shows the output voltage
91. er revisions supports two IDE connectors e Four Universal Serial Bus USB ports Three on the rear I O and one on the Server Board as a 10 pin header e Two serial ports One out to rear I O and one through a 10 pin header on the Server Board e One floppy connector e Four multi speed system fan connectors and two single speed CPU fan connectors e 34 SSI compliant front panel connector Revision 1 2 3 Order Number A85874 002 Processor and Chipset Intel Server Board SDS2 3 Processor and Chipset The Server Works ServerSet III HE SL chipset provides the 36 bit address 72 bit data 64 bit data 8 bit ECC processor host bus interface operating at 133 MHz in the AGTL signaling environment The HE SL North Bridge provides an integrated memory controller the interface to 32 bit 33 MHz Rev 2 2 compliant PCI bus and two Inter Module Bus interfaces Inter Module Bus IMB provides the interface to two 64 bit 66 MHz Rev 2 2 compliant PCI buses via the CIOB20 The SDS2 DP Server Board directly supports up to 6 GB of ECC memory using six PC 133 compliant registered SDRAM DIMMs The ECC implementation in the HE SL can detect and correct single bit errors and it can detect multiple bit errors 3 4 Processors The 5052 Server Board supports two Intel Pentium III processors in the Socket 370 FCPGA2 package If two processors are installed both processors must be of identical revisions with the same core voltage and
92. essors and 5 that the power is stable Upon RHST P6 PWRGOOCD assertion the CSB5 will toggle PCI reset 5 2 2 Hard Reset A hard reset can be initiated by resetting the system through the front panel switch During the reset the Sahalee BMC de asserts the HST P6 PWRGOOCD signal After approximately 500 ms it is reasserted and the Power up Reset sequence is done The Sahalee BMC is not reset by a hard reset It may be reset at power up 5 2 3 Soft Reset A soft reset causes the processors to begin execution in a known state without flushing the caches or internal buffers The keyboard controller located in the SIO or by the CSB5 can generate soft resets The output of the SIO is input to the CSB5 5 3 Intelligent Plattorm Management Buses Management controllers and sensors communicate on the PC based Intelligent Platform Management Bus bit protocol defined by the Bus Specification and a byte level protocol defined by the ntelligent Platform Management Bus Communications Protocol Specification provide an independent interconnect for all devices operating on this bus The IPMB extends throughout the Server Board and system chassis An added layer in the protocol supports transactions between multiple servers on inter chassis bus segments 30 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Server Management Table 17 IPMB Bus Devices SOSIHSBP A 5 68
93. f system bus error conditions monitored by the SDS2 Server Board 5 4 1 Error Sources and Types One of the major requirements of server management is to correctly and consistently handles system errors System errors on the SDS2 which can be disabled and enabled individually can be categorized as follows e PCI bus e Processor bus errors e Memory single and multi bit errors e General server management sensors managed by Sahalee BMC 5 4 2 PCI Bus Errors The PCI bus defines two error pins PERR and SERR for reporting PCI parity errors and system errors respectively In the case of PERR the PCI bus master has the option to retry the offending transaction or to report it using SERR All other PCLrelated errors are reported by SERR SERR is routed to NMI if enabled by BIOS 5 4 3 Intel Pentium Ill Processor Bus Errors The HE SL supports all the data integrity features supported by the Pentium Pro bus including Address Request and Response parity The HE SL always generates ECC data while it is driving the processor data bus although data bus ECC can be disabled or enabled by BIOS enabled by default The HE SL generates MIRQ on SBEs Single bit errors and generates SALERT on 32 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Server Management uncorrectable errors In addition the HE SL can generate BERR on unrecoverable ECC errors detected on the processor bus Unrecoverable errors are rou
94. fied zero channel RAID card is installed then SCSI interrupts are routed to the RAID card instead of PCI interrupt controller and the host based device is effectively hidden from the system The 5052 Server Board uses an implementation commonly referred to as RAIDIOS to support this feature Note Zero Channel Raid Cards ZCR cards are only supported on PCI slot 6 Note Intel zero channel raid cards SRCMR and SRCMRU are not supported on SDS2 4 2 Ultra160 SCSI The SDS2 Server Board provides an embedded dual channel SCSI bus through the use of the Adaptec s AIC 7899W SCSI controller The AIC 7899W controller contains two independent SCSI controllers that share a single 64 bit 66 MHz PCI bus master interface as a multifunction device packaged in a 456 pin BGA Internally each controller is identical capable of operations using either 16 bit SE or LVD SCSI providing 40 MBps Ultra wide SE 80 MBps Ultra 2 or 160 MBps Ultra160 Each controller has its own set of PCI configuration registers and SCSI I O registers The SDS2 Server Board supports disabling of the on board SCSI controller through the BIOS setup menu The SDS2 Server Board provides active terminators termination voltage re settable fuse and protection diode for both SCSI channels The SCSI BIOS setup menu CNTRL A provides the ability to enable or disable the on board terminators for both channels A and B 4 3 Video Controller The SDS2 Server Board provides a
95. for non bootable CDROM during POST causes hang at boot Problem Workaround Status Revision 1 2 Powered on the system with a bootable Win2k AS CD in the CDROM drive As soon as the BIOS began to POST add in cards with OPTION ROMS the Bootable CD was ejected and a non bootable CD was inserted When the system completed POST and attempted to boot the floppy drive showed an access attempt The system then hanged with a blinking cursor on a black background The boot order was set with 1 Floppy 2 CDROM 3 Hard Drive Reset the system BIOS does not rescan status of boot devices upon completion of POST Will not fix 121 Order Number A85874 002 Errata Listing Intel Server Board SDS2 28 OB P100 NICs do not show at POST but attempt PXE boot and appear in Boot Menu Problem On board NIC are not displayed during post but do appear in Boot Device menu These controllers will also attempt to do a PXE boot if no other bootable devices are found Implication Not all boot devices displayed during POST when diagnostic display is enabled Workaround None This is by design The system BIOS builds the on board network controller Option ROM with an option that always makes the OPROM quiet It therefore does not display any text messages and does not allowing the CTRL S option Status Will not fix 29 Dodson Adaptec 39160 in slots 5 amp 6 causes Expansion ROM error Problem Add in Adaptec 39160 Ultra 160 control
96. g CMOS Clear Clear CMOS as follows 1 Power off the system unplug the power cord and remove the chassis panel 2 Add a jumper on CN42 pins 1 2 CMOS Clear 3 Replace the chassis panel plug in the power cable s and power on the system 4 After POST completes power down the system unplug the power cable s and remove the chassis panel 5 Remove the jumper from CN42 pins 1 2 6 Replace the chassis panel and connect system cables 7 Power on the system press F2 at the prompt to run the BIOS Setup utility and select Get Default Values at the Exit menu 9 2 2 Performing BIOS Recovery Boot In the event of BIOS corruption the following procedure may be used to perform a BIOS Recovery boot 1 Prepare a bootable floppy diskette containing the BIOS recovery files for the SDS2 Server Board obtained from Intel s web sites 92 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Jumpers 9 2 3 Power off the system unplug the power cord and remove the chassis panel Add a jumper on CN42 pins 9 10 BIOS Recovery Insert the BIOS Recovery floppy diskette into the disk drive Reinstall the chassis panel plug in the power cord s and power on the system The screen will remain blank while the BIOS Recovery is performed At the end of the BIOS Recovery two high pitched beeps will sound and the floppy drive access light will turn off The BIOS Recovery may take several minutes to complete When the BIOS
97. g a BIOS recovery in order to restore the system from a failed flash This utilizes a jumper on the baseboard The system beeps through out the process The recovery BIOS boots only from a 1 44 MB floppy diskette inserted into a 1 44 MB floppy drive or LS 120 240 drive Nothing is displayed to the video screen during the recovery process Note The user must make the Recovery floppy diskette following the instructions included in the release notes Failure to do so will cause the process to fail 6 4 5 1 Performing BIOS Recovery The follow procedure boots the recovery BIOS and flashes the normal BIOS 1 Prepare a BIOS recovery diskette by following the instructions included with the BIOS release 2 Turn off system power 3 Move the BIOS recovery jumper to the recovery position 4 Insert the BIOS recovery diskette 68 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS 5 Turn on system power The system boots from the recovery diskette The BIOS will beep twice when the update process starts The system will continue to beep while updating the BIOS If BIOS update completes successfully the system will stop beeping If the update fails the system will sound an alternating pattern of a buzz and a beep When the flash update completes 1 2 3 4 5 Turn off system power Remove the recovery diskette Restore the recovery jumper to its original position Turn on system power Flash an
98. he System Event log will be cleared immediately Revision 1 2 63 Order Number A85874 002 BIOS Intel Server Board SDS2 Feature Option S Description Assert NMI PERR Disabled If enabled PCI bus parity error PERR is Enabled enabled and is routed to NMI Assert NMI SERR Enabled If enabled PCI bus system error SERR is Disabled enabled and is routed to NMI FRB 2 Policy FRB2 Disable Controls the policy of the FRB 2 timeout This Disable Immediately option determines when the Boot Strap Never Disable Processor BSP should be disabled if FRB 2 error occur And Detemines when FRB2 stop Allow 3 Failures Thermal Sensor Disabled Determines wheter Thermal Sensor monitoring Enabled function BMC IRQ IRQ11 Determines BMC IRQ IRQ5 IRQ10 Disabled Post Error Pause Disabled If enabled the boot is stopped when Post error EN NNNM dM AC Link Power On Selects system power state after AC loss Last State Stay off Table 46 System Management Submenu Selections Option A BoardSeralNumber Sytem Partnumber a SymemSeWume Chassis PartNumber a chassis SerialNumber a ES D BMC Device Revision Information field only Sec
99. his issue is not seen when up to 4GB of system memory is installed in the SDS2 system Blue screens may be encountered under Microsoft Windows 2000 when using a SCOM 3C980C TX NIC in an SDS2 system with greater than 4GB of system memory installed This issue results because the 3COM 3C980C TX NIC does not physically support dual address cycles DAC therefore the NIC is not able to access physical addresses above 4GB Due to negative performance impact Intel does not recommend using a NIC adapter that does not support DAC or 64 bit PCI on a system with greater than 4GB of system memory installed Intel recommends installing a maximum of 4GB of system memory in the SDS2 system when utilizing the 3COM 3C980C TX NIC This issue does not occur when 3COM driver el98xn5 sys v4 0 0 15 which is available on the Microsoft Windows NET CDROM is used instead of 3COM driver el98xn5 sys v3 48 0 0 This is another possible workaround for this issue Fixed Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing 34 Peer to peer PCI transactions are not supported between the CIOB controlled 64 bit PCI bus and the legacy 32 bit PCI bus controlled by the HE SL north bridge Problem Peer to peer PCI transactions are supported between the two peer CIOB controlled 64 bit 66MHz 3 3V PCI busses Peer to peer PCI transactions are not supported between the CIOB controlled 64 bit 66 2 3 3V PCI bus and the legacy 32 b
100. ies and those regulated locally on the Server Board The Sahalee BMC also monitors SCSI termination voltage fan tachometers for detecting a fan failure and system temperature Temperature is measured on each of the processors and at locations on the Server Board away from the fans When any monitored parameter is outside the defined thresholds the Sahalee BMC logs an event in the System Event Log SEL Management controllers and sensors communicate on the PC based Intelligent Platform Management Bus Attached to one of its private bus is Hecetas which is an ADM1026 The ADM1026 is a versatile Systems Monitor ASIC Some of its features include Analog measurement channels Fan speed measurement channels General Purpose Logic pins Remote temperature measurement On chip temperature sensor Chassis intrusion detection The table below details some of the inputs on Hecetas as used in the SDS2 Table 14 ADM1026 Input Definition Cm s ow s euve ouewog CPU1 VID1 CPU1 VID 1 CPU1 VID2 CPU1 VID 2 Revision 1 2 Order Number A85874 002 27 Server Management Intel Server Board SDS2 5 2 Serial Bus Clock N_SM2_DATA Serial Bus Data N_ADM_FAN_PWM Pulse width modulated output for control of fan speed N_RST_BMCRST_L Power on Reset with minimum of 200ms pulse width 3VSB Monitors 3V Standby supp
101. ime clock 19 43 Recovey floppy 66 Regulatory markings 99 Reset Configuration Data 65 Resettable fuse 14 S0 17 33 51 17 33 S4 17 33 S5 17 33 Safety standard requirements 99 Scatter gather mechanism 17 SCSI BIOS 65 SCSI connectors 78 85 SCSI controller 3 10 11 14 18 65 Order Number A85874 002 Index SCSI Controller 13 68 SDRAM DIMM connectors 73 Security 51 54 Processor 45 46 SEL Log Sensors 38 Sensor Event 37 Sensor Failure 43 Sensor Processor 45 46 Serial ports 3 18 19 82 Serialized IRQs 21 SERIRQ 21 SERR 32 37 76 77 ServerSet HE SL chipset 2 Set NMI Source command 37 Set SEL Time command 43 Setup utility 51 Setup Utility 65 Setup utility navigation 52 Setup utility entering 52 Shadow 45 46 47 Single bit error correction 6 Single bit errors 4 17 32 Slave device 21 SMI 35 38 SMI handler 35 37 SMI Timeout 42 Socket 370 FCPGA2 2 Socket370 2 4 Soft reset 30 Software ID 35 South Bridge 8 9 32 Start frame 21 Stop frame 21 Super I O controller 3 Synchronous clocks 68 System errors 32 35 System Event 7Ah 42 System Event Log 38 49 System Event Log full 38 System Event Log timestamp 43 System flash 34 System Setup Utility 34 System temperature 27 Systems Monitor ASIC 27 Tach Fan 41 Intel Server Board SDS2 Temperature measurement 27 Termination voltage 14 27 Terminator module 5
102. imeout Sensor Failure NMI Signal State SMI Signal State Digital Discrete 03h 5 Digital DEM och Discrete 03h S Power Button ensor Button 79h Button 14h Specific 6Fh Sleep Button Reset Button 6 2 4 2 Timestamp Clock The BMC maintains a four byte internal timestamp clock used by the System Event Log and Sensor Data Record subsystems This clock is incremented once per second and is read and set using the Get SEL Time and Set SEL Time commands respectively The Get SDR Time command can also be used to read the timestamp clock The BMC has direct access the system real time clock This allows the BMC to automatically synchronize the SEL SDR timestamp clock to the real time clock time on BMC startup The BMC periodically reads the real time clock to maintain synchronization even when software asynchronously changes the value In addition to this the BIOS send a timestamp to the BMC using Set SEL Time command during POST 44 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS 6 2 5 Error Messages and Error Codes The system BIOS displays error messages on the video screen Before video initialization beep codes inform the user of errors POST error codes are logged in the System Event Log The BIOS displays POST error codes on the video monitor 6 2 5 1 ASF Progress Codes The BIOS utilizes ASF Progress Events as described in the ASF Specification Revision 1 0a from the DM
103. ired for system configuration and flash ROMupdate The BIOS is implemented as firmware that resides in the flash ROM The term BIOS as used in the context of this document refers to the system BIOS the BIOS Setup and option ROMs for on board peripheral devices that are contained in the system flash The system BIOS controls basic system functionality using stored configuration values The terms flash ROM system flash and BIOS flash may be used interchangeably in this document BIOS Setup is a Flash ROMresident setup utility that provides the user with control of configuration values stored in battery backed CMOS configuration RAM BIOS options can also be set utilizing the System Setup Utility SSU Operation of the SSU is discussed in a separate document BIOS Setup is closely tied with the system BIOS and is considered a part of BIOS Phoenix Phlash PHLASH EXE is used to load areas of flash ROM with Setup BIOS and other code data The following is the breakdown of the SDS2 product ID string 4 byte board ID SDS2 e 1 byte board revision starting from 0 e 3 byte OEM ID 86B for standard BIOS e 4 byte build number e 1 3 bytes describing build type D for development A for Alpha B for Beta Pxx for production version xx e 6 byte build date in yymmdd format 4 byte time in hhmm format 6 1 System BIOS The system BIOS is the core of the flash ROM resident portion of the BIOS The system BIOS provides s
104. is run on an SDS2 system following a cold boot the following error message will be encountered ERROR BMC CHECKCHASSISSTATUS V4 11 1 0107 Chassis Status miscompared with known values EXP 210101h RCVD 210001h MASK FFFFFFFFh Standard Error Code OBE1501F BMC CHECKCHASSISSTATUS FAILED This issue is not seen if the SDS2 BYO PCT v 1 00 is re run a second time without restarting the system or after restarting the system with a Ctrl Alt Del warm boot The SDS2 PCT v 1 00 will fail with the BMC Check Chassis Status test when the test is run following a cold boot None Fixed This issue is due to the SDS2 BYO PCT v 1 00 incorrectly identifying an error condition This issue has been fixed in SDS2 BYO PCT v 1 01 SDS2 BYO PCT v 1 01 will be added to the SDS2 system resource CD ROM in future engineering change order ECO 16 SDS20B71 System Temperature out of the range POST message Problem Revision 1 2 When the SDS2 server board is installed the SC5100 chassis if the SC5100 front panel cable is disconnected from the SDS2 server board and then reconnected while 5V standby voltage is applied to the system AC power cord connected to the system the following message will be seen during POST the next time the system is powered on System Monitoring Check 0B71 System Temperature out of the range Press lt F1 gt to override boot suppression or lt F2 gt to enter Setup 115 Order Number A85874 002 Errat
105. it 33MHz 5V PCI bus which is controlled by the HE SL north bridge This information is not officially documented in ServerWorks datasheets or confidential chipset documents Implication PCI adapter card transactions between 64 bit PCI bus and the 32 bit PCI bus will fail Workaround Peer to peer PCI transactions must use the 64 bit buses controlled by the CIOB Status NoFix 35 SDS2 PCI slot current levels supported by the 5V rail Problem The SDS2 server board is capable of supporting a maximum total of 21 amps on the 5V rail to the six PCI slots on the server board Implication The SDS2 server board can support a maximum total of 21 amps on the 5V rail to the six PCI slots on the server board Integrators must consider this when selecting PCI card configurations for use in the SDS2 server board Workaround Select PCI cards that utilize a combination of 3 3V and 5V voltage in order to minimize the current utilized by the PCI cards on the 5V rail Status No Fix 36 OB P100 NICs do not show at POST but attempt PXE boot and appear in Boot Menu Problem On board NIC are not displayed during post but do appear in Boot Device menu These controllers will also attempt to do a PXE boot if no other bootable devices are found Implication Not all boot devices displayed during POST when diagnostic display is enabled Workaround None This is by design The system BIOS builds the on board network controller Option ROM with a
106. ization is x72 which includes 8 ECC check bits ECC from the DIMMs is passed through to the processor front side bus The SDRAM interface runs at the same frequency as the processor bus The memory controller supports 2 way interleaved SDRAM memory scrubbing single bit error correction and multiple bit error detection Memory can be implemented with either single sided one row or double sided two row DIMMs e Only registered PC 133 compliant memory is supported e Support is 2 way interleaved SDRAM and requires two DIMMs to be installed per bank e ECC single bit error correction and multiple bit error detection Maximum memory capacity of 6 GB e Minimum memory capacity of 128 MB Note Memory interleaving is a way to increase memory performance by allowing the system to access multiple memory modules simultaneously rather than sequentially in a similar fashion to Hard Drive striping Interleaving can only take place between identical memory modules 3 2 1 Memory Configuration Memory configuration requirements are as follow PC 133 SDRAM Registered DIMM modules e DIMM organization x72 ECC e Pin count 168 SDRAM Supported 64 Mb 128 Mb 256 Mb DIMM capacity 64 MB 128 MB 256 MB 512 MB 1 GB e Serial PD Rev 2 0 e Voltage Options 3 3 V VDD VDDQ e Interface LVTTL e DIMMs must be populated in pairs for a x144 wide memory data path e Any or all memory banks be populated 6 Revision 1 2
107. ler installed in slots 5 amp 6 causes an Expansion ROM error after last system POST No other adapters are present Implication Error message Expansion ROM not initialized PCI Mass Storage controller in slot 06 Bus 02 Device 09 Function 01 Workaround single image Option ROM requires one master controlling channel that is set using the lt Ctrl A gt SCSI Select utility Each channel loads the Option ROM determines whether it is the master channel and if not it unloads completely If it is the master it proceeds to scan all devices and list all possible drives Only one channel does this scanning but ALL channels load the Option ROM initially if the Option ROM is enabled on the slot The error is coming from the second channel on the Adaptec 39160 even though the first channel has already completed the master scan The reason it is only happening in Slots 5 and 6 and when the NIC Option ROMs are all loaded is because that is when the available Option ROM space is at a minimum The NIC Option ROM s are small but apparently they make enough difference The onboard 7899 Option ROM loads after Slots 1 4 but before Slots 5 amp 6 The solution here is to enable channel B of the ASC39160 as the master channel When this is done channel A loads the Option ROM sees that it is not the master and unloads Then channel B loads the Option ROM does the full scan of all devices and remains in memory At this
108. lia amp New Zealand EMS Regulations based on CISPR 22 The SDS2 Server Board is marked with the following regulatory markings 102 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Regulatory and Integration Information UL Recognition Mark USA Canada CE Mark Europe C Tick Mark Australia GOST Mark Russia BSMI Mark Taiwan SHE iB RE SIHESRISELHSECTIR E68 C073 12 2 Installation Instructions CAUTION Follow these guidelines to meet safety and regulatory requirements when installing this board assembly Read and adhere to these instructions and to the instructions supplied with the host computer and associated modules If the instructions for the host computer are inconsistent with these instructions or the instructions for associated modules contact the supplier s technical support to find out how to ensure that the system meets safety and regulatory requirements If the instructions are not followed the user increases safety risk and the possibility of noncompliance with regional laws and regulations 12 2 1 Ensure EMC Before computer integration the host chassis power supply and other modules should pass EMC certification testing In the installation instructions for the host chassis power supply and other modules pay close attention to the following e Certifications e External I O cable shielding and fi
109. line 16 IRQ3 IRQ4 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 6 3 2 3 3 Security Menu Selections Table 44 Security Menu Selections User Password is Status only user cannot modify Once set can be disabled by setting to a null string or clear password jumper on board Administrator Clear Status only user cannot modify Once set can be Password is Set disabled by setting to a null string or clear password jumper on board Set User Password Press Enter When the Enter key is pressed the user is prompted for a password press ESC key to abort Once set can be disabled by setting to a null string or clear password jumper on board 62 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS Feature Description Set Administrative Press Enter When the Enter key is pressed the user is prompted Password for a password press ESC key to abort Once set can be disabled by setting to a null string or clear password jumper on board Password on boot Disabled If enabled requires password entry before boot Enabled Fixed disk boot Normal Will write protect the boot sector of the hard drive to sector Write protect prevent viruses from corrupting the drive under DOS if set to write protect Secure Mode Timer 2 minutes Period of key PS 2 mouse inactivity specified for 5 minutes Secure Mode to activate A password is required for Secure Mode to function Has no
110. ltering e Mounting grounding and bonding requirements e Keying connectors when incorrect mating of connectors could be hazardous Revision 1 2 103 Order Number A85874 002 Regulatory and Integration Information Intel Server Board SDS2 If the host chassis power supply and other modules have not passed applicable EMC certification testing before integration EMC testing must be conducted on a representative sample of the newly completed computer 12 2 2 Ensure Host Computer and Accessory Module Certifications The host computer and any added subassembly such as a board or drive assembly including internal or external wiring should be certified for the region s where the end product will be used Marks on the product are proof of certification Certification marks are as follows 12 2 2 1 Europe The CE marking signifies compliance with all relevant European requirements If the host computer does not bear the CE marking obtain a supplier s Declaration of Conformity to the appropriate standards required by the European EMC Directive and Low Voltage Directive Other directives such as the Machinery and Telecommunications Directives may also apply depending on the type of product and final configuration 12 2 2 2 United States A certification mark by a Nationally Recognized Testing Laboratory NRTL such as UL CSA or ETL signifies compliance with safety requirements Compliance to FCC requirements is also required FCC Class
111. ly 5VSB Monitors 5V Standby supply lt lt N gt gt o o NI oT A co A An 8 bit analog readings of the following system temperatures are provided Table 15 Temperature Sensors Primary processor socket thermal sensor 5 C or better Secondary Processor Secondary processor socket thermal sensor 5 C or better The table below details some of the inputs on Sahalee as used in the SDS2 Table 16 Sahalee Input Definition Signatname 28 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Server Management C14 N FAN6 SENSE P Rear System Fan 2 Speed L12 N MEM ALERT L Memory ECC Error Detect M12 N BMC SECUREMODE Secure Mode Detect Note For a complete listing of BMC sensors please refer to SDS2 Baseboard Management Controller External Product Specification ADM1026 Sahalee Figure 7 SDS2 Locations of ADM1026 and Sahalee 5 1 1 Fault Resilient Booting The Sahalee BMC implements Fault Resilient Booting FRB levels 1 2 and 3 If the default bootstrap processor BSP fails to complete the boot process FRB attempts to boot using an alternate processor e FRB level 1 is for recovery from a BIST failure detected during POST This FRB recovery is fully handled by BIOS code e FRB level 2 is for recovery from a Watchdog timeout during POST The Watchdog timer for FRB level 2
112. mage The boot order information is also cleared when CMOS is cleared via jumper The configuration data for the on board SCSI controllers is not cleared during clear CMOS event as each device controls its own default settings If the Reset Configuration Data option is enabled in Setup ESCD data and BIOS Boot specification data is cleared and reinitialized in next boot 6 4 Flash Update Utility Note The Phoenix PHLASH utility must be run without the presence of a 386 protected mode control program such as Microsoft Windows NT 2000 or EMM386 Phoenix PHLASH uses the processor s flat addressing mode to update the flash ROM 6 4 1 Loading the System BIOS The BIOS update utility PHLASH loads a new copy of the BIOS into Flash ROM The loaded code and data include the following e On board Video BIOS and SCSI BIOS BIOS Setup Utility e Quiet Boot Logo Area When running PHLASH in interactive mode the user may choose to update a particular Flash area Updating a flash area takes a file or series of files from a hard or floppy disk and loads it in the specified area of Flash ROM To manually load a portion of the BIOS the user must specify which data file s to load The choices include PLATCBLU BIN PLATCXLU BIN PLATCXXX BIN PLATCXLX BIN or PLATCXXU BIN The last three letters specify the functions to perform during the flash process C Rewrite BIOS B Rewrite Boot block L Clear LOGO area U Clear user binary X
113. n ATI RAGE XL PCI graphics accelerator along with video SDRAM and support circuitry for an embedded SVGA video subsystem The ATI RAGE XL chip contains a SVGA video controller clock generator 2D and 3D engine and RAMDAC in a 272 pin PBGA Two 2 MB SDRAM chips provide 4 MB of video memory The SVGA subsystem supports a variety of modes up to 1024 x 768 resolution in 8 16 24 32 bpp modes under 2D and up to 800 x 600 resolution in 8 16 24 32 bpp modes under 3D It also supports both CRT and LCD monitors at up to 100 Hz vertical refresh rate The SDS2 Server Board provides a standard 15 pin VGA connector 4 3 1 Video Modes The RAGE XL chip supports all standard IBM VGA modes The following table shows the 2D 3D modes supported on the CRT The table specifies the various display resolution refresh rates and color depths supported 14 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Subsystem Table 9 Video Modes S5 soon 43 60 Supponed T Supponed _ oaoa 70 78 15004200 59 66 7685 Supponed swr 8002800 _ 60767650160 Supported Supported 69727590100 E S 102676 60 72 75 90 100 _ _ Lusso i _ Supponed 4 4 Network Interface Controller NIC The SDS2 Server Board supports two 10Base T 100Base TX network subs
114. n option that always makes the OPROM quiet It Revision 1 2 125 Order Number A85874 002 Errata Listing Intel Server Board SDS2 therefore does not display any text messages and does not allowing the CTRL S option Status Will not fix 126 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Glossary Glossary This appendix contains important terms used in the preceding chapters For ease of use numeric entries are listed first e g 82460GX with alpha entries following e g AGP 4x Acronyms are then entered in their respective place with non acronyms following Bye CIOB PCI 64 bit hub CMOS In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the baseboard E E G H H Inter integrated circuit bus Intel architecture ICMB Intelligent Chassis Management Bus IPMB Intelligent Platform Management Bus milliseconds IT K LAI LP U Ms P S B U B L C P N C N L T M P R R GT S 2 Revision 1 2 Order Number A85874 002 Glossary Intel Server Board SDS2 ROM RTC Realtime dock Component of OH peripheral chip on the basora 7 ll Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Reference Documents Reference Documents Refer to the following documents for additi
115. notified 6 2 3 4 System Limit Error The BMC monitors system operational limits It manages the A D converter defining voltage and temperature limits as well as fan sensors and chassis intrusion Any sensor values outside of specified limits are handled by the BMC and there is no need to generate an SMI to the host processor 6 2 3 5 Processor Failure The BIOS detects processor BIST failure and logs this event The first OEM data byte field in the log can identify the failed processor For example if processor 0 fails the first OEM data byte is 0 The BIOS depends upon BMC to log the watchdog timer reset event 6 2 3 6 Boot Event The BIOS downloads the system date and time to the BMC during POST and logs a boot event This does not indicate an error and software that parses the event log should treat it as such 6 2 3 7 Chipset Failure The BIOS detects the chipset CNB2 0HE SL and CIOB20 failure and logs this event The chipset error generates an SMI 6 2 4 Firmware BMC The BMC implements the logical System Event Log SEL device as specified in the Intelligent Platform Management Interface Specification Version 1 5 The SEL is accessible via all BMC transports This allows the System Event Log information to be accessed while the system is down via out of band interfaces 6 2 4 1 Sensor Number and Types Codes The BIOS generates a POST error message when the System Event Log is full This warning will not inhibit the syst
116. oard and Mouse do not function under Microsoft Windows 2000 when legacy USB is enabled Fab5 in BIOS setup 22 Data miscompares when using Seagate ATA model ST310215A hard drives Fixed Boot to service partition via modem fails Fab 5 Secondary IDE References Added To Documentation for FAB 5 Fab 5 25 Potential Mylex AcceleRAID 352 Adaptor Card Mechanical Interference at PCI Slot 6 Bootable CD will not boot if inserted during OPTION ROM scan Bootable CD will not boot if inserted during OPTION ROM scan 28 No Fix The On Board NIC BIOS controls the add in PRO100 P100 SA adapter card when PRO100 boot agent is Disabled Unable to boot Netware 6 0 NW6 From CD ROM With Adaptec Adaptor 2100S in Slot 6 EXE 3COM 3C980C TX NIC causes Microsoft Windows 2000 blue screen when greater than 4GB of system memory is installed No Fix Peer to peer PCI transactions are not supported between the CIOB controlled 64 bit PCI bus and the legacy 32 bit PCI bus controlled by the HE SL north bridge 36 SDS2 PCI slot current levels supported by the 5V rail OB P100 NICs do not show at POST but attempt PXE boot and appear in Boot Menu Following are in depth descriptions of each erratum change indicated in the tables above The errata and change numbers below correspond to the numbers in the tables Revision 1 2 107 Order Number A85874 002 Errata Listing Intel Server Board SDS2 13 2 Errata 1 Intel RAID
117. onal information Refer to the following documents for additional information Coppermine T Processor Data Sheet Rev 1 0 FM 2051 Tualatin Processor Electrical Mechanical and Thermal Specification Rev 0 9 FM 2024 Tualatin Dual Processor Platform Design Guide Rev 1 0 OR2660 ServerWorks Champion North Bridge 2 0 HE Version 1 8 ServerWorks Champion North Bridge 2 0 HE SuperLite Version 1 2 ServerWorks Champion Bridge Version 1 6 ServerWorks Champion South Bridge Version 1 5 PCI Local Bus Specification Revision 2 2 USB Specification Revision 1 0 Adaptec 7902 PCI Bus Master Dual Channel Ultra320 SCSI Controller Datasheet preliminary ATI RAGE XL Graphics Controller Specifications Technical Reference Manual Rev 2 01 VRM 8 5 DC DC Converter Specification Intel 82550 Fast Ethernet Controller Datasheet Intelligent Platform Management Interface IPMI Specification SDS2 Baseboard Management Controller External Product Specification Rev 0 81 Ref NO 10282 Revision 1 2 Order Number A85874 002 Index Intel Server Board SDS2 Index 1 B 1 25V 39 Baseboard Temp 40 12V 39 Beep Codes 6 35 45 50 12V 39 Beep Codes 44 BIOS 45 46 47 48 2 BIOS components 34 2 5 V logic levels 68 2 5V 39 BIOS features 34 291 008 3 20 2 way interleaved SDRAM 6 9 BIOS implementation 34 BIOS LCD command 37 3 BIOS Setup 34 90 3 3 V logic levels 68 3 3v Standby 39 24 3 3VI
118. ondary HSBP Revision 64 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS Table 47 Console Redirection Submenu Selections Feature Serial Port Address Disabled When enabled Console Redirection uses the I O port On board COM A specified Choosing Disabled completely disables On board COM B Baud Rate When Console Redirection is enabled use the baud rate specified When EMP is sharing the COM port as console redirection the baud rate must be set to 19 2 k to match EMP baud rate unless auto baud feature is used Console Redirection Flow Control None None No flow control CTS RTS CTS RTS Hardware based flow control XON XOFF XON XOFF Software flow control CTS RTS CD CTS RTS CD Hardware based Carrier Detect flow control When EMP is sharing the COM port as console redirection the flow control must be set to CTS RTS or CTS RTS CD depending on whether a modem is used 6 3 2 3 5 Boot Menu Selections Boot Menu options allow the user to select the boot device The following table is an example of a list of devices ordered in priority of the boot invocation Items can be re prioritized by using the up and down arrow keys to select the device Once the device is selected use the plus key to move the device higher in the boot priority list Use the minus key to move the device lower in the boot priority list Table 48 Boot Device Prio
119. onnectors Table 65 RJ 45 Connector Pin out Pin Sumarame Pn SignalName Revision 1 2 81 Order Number A85874 002 Connections 8 6 4 IDE Connector There is one IDE channel on the Server Board through the use of a 40 pin connector The connector pin out is detailed in the table below Note IDE LED hard disk drive activity Pin 39 signal is not routed to the front panel connector IDE hard disk activity will not cause the front panel LED s to turn on Table 66 IDE 40 pin Connector Pin out Sianal Name Pin Signal Name s fos fe r oos fe 0010 s foa 19 pen 17 on 15 00015 m m 8 6 5 Universal Serial Bus USB Connectors The Server Board provides four USB ports three on the rear I O and one internally through a 10 pin header The following table details the pin out of the stacked three port USB connector Intel amp Server Board SDS2 1 TXDP 7 RXDP rz wow s Table 67 Stacked Three port USB Connector Pin out 82 Order Number A85874 002 Revision 1 2 Intel Server Board SDS2 Connections Pin Signal Name Fused 5 V USB_PORT1_D 3 3 Use PORTI s o 5 5 6 USB PORTED S o FuedsV 10 USB PORTS D 11 USB PORTS D m A 10 pin header 2X5 located at CN18 on the Server Board provides an option to cable out the USB to the front panel The pin out of the he
120. ores the system state from disk and resumes normal operation This assumes that no hardware changes were made to the system while it was off e S5 Soft off Only the RTC section of the chip set and the BMC are running in this state The SDS2 Server Board supports sleep states sO s1 s4 and s5 When the Server Board is operating in ACPI mode the operating system retains control of the system and the operating system policy determines the entry methods and wake up sources for each sleep state Sleep entry and wake up event capabilities are provided by the hardware but are enabled by the OS 5 6 Link Mode The AC link mode allows the system to monitor its AC input power so that if AC input power is lost and then restored the system returns to one of the following pre selected settings e Power On e Last State Factory Default Setting e Stay Off Revision 1 2 33 Order Number A85874 002 Server Management Intel Server Board SDS2 Setup Utility F2 can change the AC link mode settings 34 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS 6 BIOS This section describes the BIOS embedded software for the SDS2 server board The BIOS contains standard PC compatible basic input output 1 0 services system specific hardware configuration routines and register default settings that are embedded in Flash read only memory ROM This document also describes BIOS support utilities not ROM resident that are requ
121. orresponding device description Revision 1 2 11 Order Number A85874 002 Subsystem Intel Server Board SDS2 Table 5 P32 A Configuration IDs IDSEL Value ATI XL Video Controller Intel 82550 Fast Ethernet Controller 1 PCI Slot 4 CSB5 South Bridge 4 1 1 2 P32 A Arbitration P32 A supports seven PCI masters ATA RAGE XL two Intel 82550s PCI masters from slots 3 and 4 CSB5 and HE SL All PCI masters must arbitrate for access using resources supplied by the HE SL The following table defines the arbitration connections Table 6 P32 A Arbitration Connections ATI RAGE XL Video Controller D_PCIREQL3 D_PCIGNTL3 PCI Slot 3 D PCIREQLA4 D 4 PCI Slot 4 D PCIREQL5 D PCIGNTL5 CSB5 South Bridge 4 1 2 64 bit 66 MHz PCI Subsystem There are two 64 bit 66 MHz PCI busses directed through the CIOB20 I O Bridge Both segments support full length full height PCI cards The PCI cards must meet the PCI specification for height inclusive of cable connections and memory The two PCI segments are peer buses 4 1 2 1 Device IDs IDSEL Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD 31 16 which acts as a chip select on the PCI bus segment in configuration cycles This determines a unique PCI device ID value for use in configuration cycles The following tables show the bit to which each IDSEL signal is attached for P64 B and P64 C devices and co
122. orted high resolution and high color video modes will cause the monitor screen to turn gray or to operate incorrectly The following table indicates the SDS2 video modes that are currently not supported 640x480 Supported for all video modes indicated in the SDS2 TPS 800x600 Supported for all video modes indicated in the SDS2 TPS 1024x768 Supported for all color modes at refresh rates of 72Hz and lower Supported for 8 and 16 bpp color modes only at 75Hz refresh rate Not supported for refresh rates of 85Hz and higher 1280x1024 Supported for 8 16 and 24 bpp color modes only at refresh rates of 47Hz and lower Supported for 8 bpp color mode only at 60Hz refresh rate Not supported for refresh rates of 70Hz and higher 112 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing Workaround Status 1600x1200 Not supported Utilize a video mode that is currently supported by the SDS2 Server Board Fixed SDS2 BIOS Production Release 2 4 Build 47 and later versions have added support for additional high resolution video modes The following video modes are supported by SDS2 BIOS Production Release 2 4 Build 47 and later versions 640x480 Supported at refresh rates of 120Hz and lower 800x600 Supported at refresh rates of 100Hz and lower 1024x768 Supported at refresh rates of 80Hz and lower 1152x864 Supported at refresh rates of 75Hz and lower 1280x1024 Supported at refresh rates of 60Hz and lowe
123. output voltages 3 3V 5V 12V 12V msec dropping out of regulation limits Tpwok low Duration of PWOK being in the de asserted state during an off on cycle 100 msec using AC or the PSON signal Delay from 5VSB being in regulation to O Ps being in regulation at AC 1000 turn on Revision 1 2 97 Order Number A85874 002 100 Revision 1 2 AO9RO7A nno Intel Server Board SDS2 Mechanical Specifications 11 Mechanical Specifications The following figure shows the Server Board mechanical drawing PA arr stirs eee oe Lii 122 TU L 291 94 277 92 265 94 16042 13317 304 80 12446 12332 11367 34 23 PIN 330 20 Figure 15 SDS2 Server Board Mechanical Drawing Revision 1 2 101 Order Number A85874 002 Regulatory and Integration Information Intel Server Board SDS2 12 Regulatory and Integration Information 12 1 Regulatory Compliance The SDS2 server board complies with the following safety standard requirements Table 88 Safety Regulations Regulation UL 1950 5 950 Bi National Standard for Safety of Information Technology Equipment including Electrical Business Equipment USA and Canada EN 60950 The Standard for Safety of Information Technology Equipment including Electrical Business Equipment European Community IEC60 950 The Standard for Safety of Information Technology Equipment including Electrical Busine
124. ower to be applied to the system unless both processor sockets contain a properly seated processor or terminator module e Processors should be populated in the sequential order In other words processor socket 1 should be populated before processor socket 2 50 released on FAB 5 supports the tB1 stepping CPUID 06B4 These processors are being evaluated for addition to supported processor list The current Intel support web site has the latest supported processor list for SDS2 http support intel com support motherboards server SDS2 Revision 1 2 5 Order Number A85874 002 Processor and Chipset Intel Server Board SDS2 3 1 1 Processor Voltage Regulator Module VRM SDS2 Server Board has dual on board RM circuitry to support the two processors circuit is compliant with the VRM8 5 specification and provides a maximum of 60A which will support the currently available processors and future releases of the Pentium III processors The board hardware and the BMC read the processor VID Voltage Identification bits for each processor before turning on the power to the processors 5 If the VIDs of the two processors are not identical then the BMC will not turn on the VRMs and a beep code is generated Table 30 BMC Beep Codes lists all of the error codes 3 2 Memory Subsystem The SDS2 Server Board supports up to six DIMM sockets for a maximum memory capacity of 6 GB using 1 GB DIMMs The DIMM organ
125. own set of configuration registers Once configured each appears to the system as a distinct hardware controller sharing the same PCI bus interface In the SDS2 Server Board implementation the primary role of the CSB5 is to provide the gateway to all PC compatible I O devices and features The 5052 uses the following CSB5 features e PCI bus interface e LPC bus interface e IDE interface with Ultra DMA 100 capability e Universal Serial Bus USB interface e PC compatible timer counter and DMA controllers e and 8259 interrupt controller e Power management e General purpose I O Following are descriptions of how each supported feature is implemented in SDS2 4 5 1 PCI Bus Interface The CSB5 fully implements 32 bit PCI master slave interface in accordance with the PCI Local Bus Specification Revision 2 2 On the SDS2 Server Board the PCI interface operates at 33 MHz using the 5 V signaling environment 4 5 2 PCI Bus Master IDE Interface The CSB5 acts as a PCl based Fast IDE controller that supports programmed transfers and bus master IDE transfers The CSB5 supports two IDE channels supporting two drives each drives 0 and 1 The FAB 5 PBA A58285 502 SDS2 Server Board supports two IDE channels through the standard 40 pin 2x20 connector Note FAB 4 boards PBA A58285 402 and 403 supported only one IDE channel The SDS2 IDE interface supports the following features 16 Revision 1 2 Order Number A858
126. perating system is loaded Revision 1 2 111 Order Number A85874 002 Errata Listing Intel Server Board SDS2 Problem Microsoft Windows 2000 NIC driver set 5 1 2 v 5 41 27 prevents the Intel Server Board SDS2 from making a DPC LAN connection when the operating system is loaded Implication NIC driver set 5 1 2 v 5 41 27 for Microsoft Windows 2000 should not be used with the Intel Server Board SDS2 if DPC LAN is being used Workaround Intel recommends using NIC driver set 5 0 1 v 5 40 11 or driver set 5 1 3 v 5 41 32 in order to avoid this failure Status Fixed Intel recommends using NIC driver set 5 0 1 v 5 40 11 or driver set 5 1 3 v 5 41 32 as the fix for this issue 9 Extended RAM Step disable option in BIOS Setup has no effect Problem Setting the Intel amp Server Board SDS2 BIOS Setup Advanced Memory Configuration Extended RAM Step option to Disabled has no effect Implication The Intel Server Board SDS2 will still perform the Extended RAM count even when this option has been set to Disabled in BIOS Setup Workaround None Status Fixed This issue is fixed in SDS2 BIOS Production Release 2 1 Build 44 and later versions 10 High resolution video modes do not work correctly Problem Several of the high resolution video modes listed as supported in Table 6 of the Inte amp Server Board SDS2 Technical Product Specification TPS Rev 1 0 are currently not supported Implication Selecting unsupp
127. point no other channels are found so no other devices error The key here is that the LAST available Adaptec channel should be listed as the Master unfortunately this is opposite from their default they default to the first available channel 122 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Errata Listing Status Will Not Fix 30 Can Not Change BIOS SETUP IDE Options Using lt Enter gt Key Problem In SETUP when attempting to change any option under the Primary Secondary IDE controller sub menu one must use the space bar The enter key does not function The TPS does not mention having to use the SPACE bar to change the options Implication Possible confusion on how to select the options in the BIOS Setup IDE sub menu Workaround None Status Will not fix 31 Minimum Wait Time Between Power Off and Power On via Front Panel Power Button Is One Second Problem Minimum wait time between power off and power on using the front panel power button on the SC5100 chassis is not documented Implication System will not respond to the power button until one second has elapsed Workaround Wait longer than one second when cycling the AC power via the front panel power button Status Will not fix 32 Unable to boot Netware 6 0 NW6 From CD ROM With Adaptec Adaptor 2100S in Slot 6 Problem Unable to install or boot to NW6 from CD Rom with Adaptec SCSI Adaptor 21008 installed in Slot 6 NW6 requi
128. r 1600x1200 Not supported Selecting an unsupported video mode no longer causes the monitor to turn gray or to operate incorrectly 11 Lower performance with CAS Latency 2 memory Problem Implication Workaround Status Performance of the Intel Server Board SDS2 memory subsystem is lower than expected when CAS Latency 2 memory is used The copy bandwidth observed with CAS Latency 2 memory installed is less than the copy bandwidth with CAS Latency 3 memory installed The memory subsystem copy performance of the SDS2 Server Board is lower with CAS Latency 2 memory installed than with CAS Latency 3 memory installed Use of CAS Latency 3 memory is recommended for optimum memory subsystem copy performance Fixed This issue is fixed in SDS2 BIOS Production Release 2 4 Build 47 and later versions When using SDS2 BIOS Production Release 2 4 Build 47 the copy bandwidth observed with CAS Latency 2 memory installed is greater than the copy bandwidth with CAS Latency 3 memory installed 12 SDS2 reboots during POST with 4GB or more of total system memory installed Problem Revision 1 2 When 4GB or more of total system memory is installed in the SDS2 server board and the Extended RAM step option in BIOS Setup is set to Every Location the SDS2 server board will reboot during the memory scan portion of POST This is due to a timeout of the FRB 2 timer 113 Order Number A85874 002 Errata Listing Implication
129. r if present 2h i 3h 4h i 5h 6h 7h PCI resource configuration At beginning of configuring PCI devices in system 8h Option ROM initialization At beginning of Option ROM scan 9h Ah Bh i Ch Dh 12h i 13h Table 26 Port 80h Code Definition Code 2 Phoenix check point POST code Revision 1 2 45 Order Number A85874 002 BIOS Intel Server Board SDS2 The following table contains the POST codes displayed during the boot process A beep code is a series of individual beeps on the PC speaker each of equal length The following table describes the error conditions associated with each beep code and the corresponding POST checks point code as seen by a port 80h card and LCD For example if an error occurs at checkpoint 22h a beep code of 1 3 1 1 is generated The indicates a pause within the sequence Some POST codes occur before the video display is initialized To assist in determining the fault a unique beep code is derived from these checkpoints as follows e 8 bit test point is broken down to four 2 bit groups e Each group is made one based 1 through 4 One to four beeps are generated based on each group s 2 bit pattern Note Not all POST codes generate a Beep Code Example Checkpoint 4Bh is divided into 01001011 beep code is 2 1 3 4 Table 27 Standard BIOS POST Codes CP Beeps
130. res SP1 updated drivers to be installed Implication System hangs and fails to load drivers completely Unable to boot to SSU floppy if NW6 CD is installed in CD ROM drive Workaround Recommended installation methodology is to install from the Netware 6 SP1 Overlay CD This CD installs Netware 6 with all the SP1 fixes already incorporated The SP1 Overlay CD is available from http support novell com filefinder 13659 index html Revision 1 2 123 Order Number A85874 002 Errata Listing Status Intel Server Board SDS2 Alternatively the updated drivers may installed using the following procedure to install NW6 a Boot to DOS and fdisk format the C partition b Boot to C drive and load loddvc com and cdex from there loddvc aoatapi sys D cdrOm001 cdex exe D cdrOm001 L z aotapi sys is whatever driver is appropriate for the cd L z requires lastdrive z in config sys c Copy server exe from SP1 to the nwupdate directory Run Install bat from the 7 drive Fixed 33 3COM 3C980C TX NIC causes Microsoft Windows 2000 blue screen when greater than 4GB of system memory is installed Problem Implication Workaround Status 124 Intel has induced blue screens under Microsoft Windows 2000 in SDS2 sytems configured with a 3COM 3C980C TX NIC with driver el98xn5 sys v3 48 0 0 and greater than 4GB of system memory installed under extreme workloads during network validation testing T
131. res a 12 V Power Connector The board will not power on without 12 V Power supplied to this connector 74 Table 54 Aux Signal Connector Pin out Pin Signal Name 12C Clock Order Number A85874 002 Revision 1 2 Connections Intel Server Board SDS2 Not Used tc Si n 8 2 Memory Module Connector 75 d Os DL Pp ge 2q Q sa C 2 o A ge 5 9 Co c C ou og gt 5 5 23 olo NE o o 5 o o o je lt gt tt dt dh dt tt dd td lt gt c xt io N N Go a 8 ku A oe 5666 eS 9 S x ea gs 8g BIS S 19 B S Ig sgg g Ig 18 g s gt 1S 2 9 B Om TOD qt ee 588 E S Sos 21 9 8182 8 2 2 690 lt t o ars 5 2 Q NEN df tt z 99g 8 A 2 2 95 5 99989 O S e aja 8 8 O S N e HES im gt 86 5 nets ze D ofS 2 rs Order Number A85874 002 Connections Intel Server Board SDS2 8 3 System Managemen
132. rity Selections Boot Priority Removable Devices Attempt to boot from a legacy floppy A or removable media device like LS 120 Attempt to boot from a hard drive device ATAPI CD ROM Drive Attempt to boot from an ATAPI CD ROM drive 1 4 PXE UNDI Attempt to boot from a network This entry will appear if there is a network device in the system that is controlled by a PXE compliant option ROM Revision 1 2 65 Order Number A85874 002 BIOS Intel Server Board SDS2 Table 49 Hard Drive Selections Option 4 Drive 1 or actual drive To select the boot drive use the up and down arrows to highlight a device string then press the plus key to move it to the top of the list or the minus key Other bootable cards to move it down Additional entries for each Other bootable cards cover all the boot devices that are not reported to the drive that has a PnP header system BIOS through BIOS Boot specification mechanism It may or may not be bootable and may not correspond to any device If BIOS boot spec support is set to limited this item covers all drives that are controlled by option ROMs like SCSI drives Press ESC to exit this menu Table 50 Removable Drive Selections Option Descripion Lists Bootable Removable Devices in the Use keys to place the removable devices in the boot order you want Includes Legacy 1 44 MB floppy 120 MB floppy etc 6 3 2 3
133. rom individual sensors and logging system events 6 2 2 Handling and Logging System Errors This section describes actions taken by the SMI handler with respect to the various categories of system errors It covers the events logged by the BIOS and the format of data bytes associated with those events The BIOS is responsible for monitoring and logging certain system events The BIOS sends a platform event message to BMC to log the event Some of the errors such as processor failure are logged during early POST and not through the SMI handler 6 2 2 1 Logging Format Conventions The BIOS complies with the Intelligent Platform Management Interface Specification Revision 1 5 The BIOS always uses system software ID within the range 00h 1Fh to log errors As a result the Generator ID byte is an odd number in the range 01h 3fh OEM user binary should use software IDs of 1 The Software ID allows external software to find the origin of the event message 36 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS The BIOS logs the following SEL entries Table 22 BIOS Generated SEL Errors Sensor Sensor Sensor Sensor Type Number Type Specific Code Offset FRB1 BIST Failure FRB2 Hang in POST Failure Memory Uncorrectable ECC POST Memory OEh POST Memory Resize Resize orem pu pum mere 7 Event Logging 10h 00h Correctable Memory Error Logging Disabled Disabled 01h Event Type Logging Disabled System Event Syst
134. rresponding device description 12 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Subsystem Table 4 P64 B Configuration IDs IDSEL Value Device Table 5 P64 C Configuration IDs Adaptec AIC 7899W SCSI Controller PCI Slot 5 4 1 2 2 P64 B Arbitration P64 B supports three PCI masters PCI masters from slots 1 and 2 and CIOB All PCI masters must arbitrate for access using resources supplied by the CIOB The following table defines the arbitration connections Table 7 P64 B Arbitration Connections Baseboard Signals FREQL1 FGNTL1 PCI Slot 1 FREQL2 FGNTL2 PCI Slot 2 4 1 2 3 P64 C Arbitration P64 C supports four PCI masters PCI masters from slots 5 and 6 onboard SCSI and CIOB All PCI masters must arbitrate for PCI access using resources supplied by the CIOB The following table defines the arbitration connections Table 8 P64 B Arbitration Connections Baseboard Signals SCSIREQLO SCSIGNTLO Adaptec AIC 7899W SCSI Controller Pe4REQL1 P64GNTL1 PCI Slot 5 P64REQL2 Pe4GNTL2 PCI Slot 6 Revision 1 2 13 Order Number A85874 002 Subsystem Intel Server Board SDS2 4 1 2 4 Zero Channel RAID ZCR Capable PCI Slot 6 The SDS2 Server Board supports zero channel RAID controller on PCI Slot 6 This add in card leverages the on board SCSI controller along with its own built in intelligence to provide a complete RAID controller subsystem on board If a speci
135. s The SMI handler sends a command to the BMC to log the event and provides the data to be logged a Set Source command to indicate BIOS as the source of the NMI and a BIOS LCD command to display the LCD and LED message s A correctable memory error does not generate an SMI Correctable and uncorrectable memory errors are handled and logged by the BMC 6 2 3 1 PCI Bus Error The PCI bus defines two error pins PERR and SERR for reporting PCI parity errors and system errors respectively 6 2 3 2 Intel Pentium Processor Bus Error In the case of irrecoverable errors on the host processor bus proper execution of SMI handler cannot be guaranteed and SMI handler cannot be relied upon to log such conditions The BIOS SMI handler records the error to the System Event Log only if the system has not experienced a catastrophic failure that compromises the integrity of the SMI handler The BIOS always enables the error correction and detection capabilities of the processors by setting appropriate bits in processor model specific register MSR 38 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS 6 2 3 3 Memory Bus Error The BMC monitors and logs memory errors The BIOS will configure the hardware to notify the BMC on correctable and uncorrectable memory errors Uncorrectable errors generate an SMI to stop the system and prevent propagation of the error The BMC will query the hardware for error information when
136. s the general Help window This window describes the Setup key legend The up arrow down arrow Page Up Page Down Home and End keys scroll the text in this window Enter Execute Command The Enter key is used to activate sub menus when the selected feature is a sub menu or to display a pick list if a selected option has a value field or to select a sub field for multi valued features like time and date If a pick list is displayed the Enter key will undo the pick list and allow another selection in the parent menu ESC Exit The ESC key provides a mechanism for backing out of any field This key will undo the pressing of the Enter key When the ESC key is pressed while editing any field or selecting features of a menu the parent menu is re entered When the ESC key is pressed in any major menu the exit confirmation window is displayed and the user is asked whether changes can be discarded Select Item The up arrow is used to select the previous value in a pick list or the previous options in a menu item s option list The selected item must then be activated by pressing the Enter key Select The down arrow is used to select the next value a menu item s option list or a value field s pick list The selected item must then be activated by pressing the Enter key gt Select Menu The left and right arrow keys are used to move between the major menu pages The keys have no affect if a sub menu or pick list is displayed Se
137. speed for the bus and core If one processor is installed an AGTL terminator module must be installed in the other socket The support circuitry on the Server Board consists of the following Dual Socket 370 FCPGA2 processor sockets supporting 133 MHz FSB if using one processor an AGTL terminator module goes in the empty socket e Processor host bus AGTL support circuitry including termination power supply Table 1 SDS2 Intel Pentium Processor Support Matrix Processor Package Speed Cache Core CPUID Supported Family Type Core Bus Size Stepping S Spec Intel FCPGA 800MHz 1 0GHz 256KB N A N A Pentium Intel FCPGA2 836606 1 2 133 2 256KB 068Ah Yes Pentium SL5QJ Tray 06B1h Yes Intel FCPGA2 836716 1 13GHZ 133MHz 512KB Pentium III Tray SL5PU 06B1h Yes Intel FCPGA2 836721 1 26GHZ 133MHz 512KB Pentium III Tray SL5QL Intel FCPGA2 836583 1 26GHZ 133MHz 512KB 06B1h Yes Pentium III SL5LW Boxed FCPGA2 838253 1 4GHZ 133MHz 512KB 06B1h 4 Revision 1 2 Order Number A85874 002 1 1 Intel FCPGA2 836384 1 18GHZ 133MHz 512KB tA1 06B1h Yes Pentium III SL5LV Boxed 1 1 1 1 Intel Server Board SDS2 Processor and Chipset Pentium III 47 Intel m 1 33MHz 2KB i h Pentium III SL5XL Notes e All processor sockets must be populated with either a processor or a terminator module The BMC will not allow DC p
138. ss Equipment International EMKO TSE 74 SEC 207 94 Summary of Nordic deviations to EN 60950 Norway Sweden Denmark and Finland EU Low Voltage Directive 73 23 ECC Compliance to EU Low Voltage Directive via EN60 950 IEC 60950 The SDS2 server board has been tested and verified to comply with the following EMC regulations when installed in a compatible Intel host system For information on Intel compatible host system s refer to Intel s Server Builder website or contact your local Intel representative Table 89 EMC Regulations Regulation Class A Title 47 of the Code of Federal Regulations Parts 2 and 15 Subpart B pertaining to unintentional radiators USA ICES 003 Class Interference Causing Equipment Standard Digital Apparatus Class A including CRC c 1374 Canada CISPR 22 Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment International VCCI Class A Implementation Regulations for Voluntary Control of Radio Interference by Data Processing Equipment and Electronic Office Machines Japan EN55022 Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment Europe EN55024 Generic Immunity Standard EU EMC Directive Compliance to EU EMC Directive via EN55022 amp EN55024 89 336 EEC BSMI CNS13438 Class A Taiwan EMC Regulations based on CISPR 22 C tick AS NZS 3548 Austra
139. stribution on the SDS2 Server Board 72 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Clock Voltage Generation and Distribution N ca O LO t N HE SL SCSI NIC 1 NIC 2 Sahalee 2 1 2 o 2 5 z amp A 5 4 i N 2 m TEA gt gt gt O ite LO LO 4 gt amp 2 5 3 EE NN a amp 5 go amp LL gt 5 gt N Figure 9 SDS2 Server Board Voltage Generation Distribution Diagram Revision 1 2 73 Order Number A85874 002 Connections Intel Server Board SDS2 8 Connections 8 1 Power Distribution Board Connector The main power supply connection is obtained using a 24 pin connector A separate 8 pin connector is used for the 12 V power connector dedicated to providing power to the processor A third 5 pin auxiliary signal connector is used to communicate with the power supply The following tables define the pin outs of these connectors Table 52 24 Pin Main Power Connector Pin out Pm Sia cse Pin Sana Carr 5v rea cou feer s ewe Gray 20 5 wwe s 848 Pome er ev fra ro rev ven 2 ev frea wm aevo Yeow s ev me Table 53 8 Pin 12 V Power Connector Pin out Pin Signal Coir Pin Signal s aveo Yeow eion Note The SDS2 server board requi
140. t Headers 8 3 1 ICMB Connector The Intelligent Chassis Management Bus ICMB allows inter chassis communications between intelligent chassis This makes it possible to externally access chassis management functions alert logs port mortem data etc Additional information about ICMB can be found in the Intelligent Chassis Management Bus Version 1 0 Table 56 ICMB Connector Pin out ICMB_TX Transmit signal ICMB_EN Enable signal s oo 8 3 2 OEM IPMB Connector Table 57 IPMB Connector Pin out Signal Name Description IPMB_SDA 5 VSB Data Line IPMB_SCL 5 VSB Clock Line 8 3 3 SCSI HSBP IPMB Connector The Intelligent Platform Management Bus IPMB as used on SDS2 Server Board allows for connections to Hot Swap Back planes HSBP with multiple hard drives Table 58 HSBP A Connector Pin out IPMB_SDA 5 VSB Data Line 2 GND IPMB_SCL 5 VSB Clock Line I2C ADR CNTRL Address Control 76 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Connections Table 59 HSBP B Connector Pin out IPMB_SDA 5 VSB Data Line IPMB_SCL 5 VSB Clock Line I2C ADR CNTRL Address Control 8 4 Front Panel Header A 34 pin header is provided for cabling to the system front panel The header contains reset NMI power control buttons and LED indicators The table below details the pin outs of the header Table 60 Front Panel 34 Pin Header Pin out Pm Sorana 6 Fen Fai LED
141. tandard PC BIOS services and support for industry standards such as the Advanced Configuration and Power Interface Specification Revision 1 0b and Wired for Management Baseline Specification Revision 2 0 In addition the system BIOS supports the following features e Security e MPS support e Server management and error handling CMOS configuration RAM management Revision 1 2 35 Order Number A85874 002 BIOS Intel Server Board SDS2 OEM customization e PCI and Plug and Play PnP BIOS interface e Console redirection e Resource allocation support 6 2 BIOS Error Handling This section defines how errors are handled by the system BIOS on the SDS2 server board Also discussed are the role of BIOS in error handling and the interaction between the BIOS platform hardware and server management firmware with regard to error handling In addition error logging techniques are described and beep codes for errors are defined 6 2 1 Error Sources and Types One of the major requirements of server management is to correctly and consistently handles system errors System errors which can be disabled and enabled individually or as a group can be categorized as follows e PCI bus e Memory correctable uncorrectable errors e Sensors e Processor internal error bus address error thermal trip error temperatures and voltages and GTL voltage levels The BMC manages the sensors It is capable of receiving event messages f
142. ted to NMI by BIOS 5 4 4 Memory Bus Errors The HE SL is programmed to generate an SMI on single bit data errors in the memory array if ECC memory is installed The HE SL performs the scrubbing The SMI handler simply records the error and the DIMM location to the System Event Log Double bit errors in the memory array are mapped to SMI because the Sahalee BMC cannot determine the location of the bad DIMM 5 4 5 ID LED The blue ID LED located at the back edge of the Server Board near NIC2 is used to help locate a given server platform requiring service when installed in a multi system rack The LED is lit when the front panel ID button is pressed and is turned off when the button is pressed again 5 5 ACPI The Advance Configuration and Power Interface ACPI aware operating system can place the system into a state where the hard drive spin down the system fans stop and all processing is halted In this state the power supply is still on and the processors still dissipate some power such that the power supply fan and processor fans continue to run Note ACPI requires an operating system that supports this feature The sleep states discussed below are defined as e 50 Normal running state e S1 Processor sleep state No content is lost in this state and the processor caches maintain coherency e S4 Hibernate or Save to Disk The memory and machine state are saved to disk Pressing the power button or another wakeup event rest
143. the CIOB20 and the legacy PCI bus The HE SL is also responsible for generating the appropriate controls to control data transfer to and from the memory CIOB20 Champion I O Bridge The CIOB20 provides the interface for two 64 bit 66 MHz Rev 2 2 compliant PCI bus The CIOB is both master and target on both PCI buses e CSBb5 South Bridge The CSB5 controller has several components It provides the interface for a 32 bit 33 MHz Rev 2 2 compliant PCI bus The CSB5 can be both a master and a target on that PCI bus The CSB5 also includes a USB controller and an IDE controller The CSB5 is also responsible for much of the power management functions with ACPI control registers built in The CSB5 also provides a number of GPIO pins and has the LPC bus to support low speed legacy 8 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Processor and Chipset 3 3 1 CNB20HE SL Champion North Bridge The Champion North Bridge Rev 2 0 High End Super Lite CNB20HE SL is the third generation product in the Server Works Champion North Bridge Technology The HE SL is a 644 pin ball grid array BGA device and uses the proven components of previous generations like the Pentium Pro Bus interface unit the PCI interface unit and the SDRAM memory interface unit In addition the HE SL incorporates a proprietary Intra Module Bus IMBus Interface The IMBus interface enables the HE SL to directly interface with the CIOB20 through its two
144. tion Intel Pentium Itanium and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright O Intel Corporation 2002 Revision 1 2 iii Order Number A85874 002 Table of Contents Table of Contents 1 2 3 4 eens ArchitecliUre canine Processor and Chipset esee Sd Processos 3 1 1 Processor Voltage Regulator Module 3 2 Memory SUDSySIONTI Com eed Dori 3 2 1 Memory 2 905 an ditiis OH MEG II Hm 3 3 1 CNB20HE SL Champion North Bridge 3 3 2 20 Champion I O Bridge 3 3 0 gt CSB5 South Bridge c RE ERR VO eU eoe eU eH a 4d 4 1 1 32 bit 33 MHz PCI Subsystem 4 1 2 64 bit 66 MHz PCI Subsystem 4 2 Ultrat60 aola PNE 43 Video t naan 4 3 1 ob et 4 4 Network Interface Controller 4 4 1 Connector and Status 5 4 5 CSB5 South Bridge PCkto LPC Bridge IDE USB
145. tup Defaults Pressing F9 causes the following to appear Load default configuration now Yes No If Yes is selected and the Enter key is pressed all Setup fields are set to their default values If No is selected and the Enter key is pressed or if the ESC key is pressed the user is returned to where they were before F9 was pressed without affecting any existing field values Save Configuration changes and exit now Yes No If Yes is selected and the Enter key is pressed all changes are saved and Setup is exited If No is selected and the Enter key is pressed or the ESC key is pressed the user is returned to where they were before F10 was pressed without affecting any existing values Save and Exit Pressing F10 causes the following message to appear 54 Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 BIOS 6 3 2 3 Menu Selection Bar The Menu Selection Bar is located at the top of the screen It displays the various major menu selections available to the user e Main Menu e Advanced Menu e Security Menu e Server Menu Boot Menu e Exit Menu These and associated submenus are described below 6 3 2 3 1 Main Menu Selections The following tables describe the available functions on the Main Menu and associated submenus Default values are highlighted Table 32 Main Menu Selections Feature Option Legacy Floppy A Disabled Hidden if not detected 720 K
146. unidirectional 16 bit wide data busses with parity support The HE SL also increases the main memory interface bandwidth and maximum memory configuration with a 144 bit wide memory interface The HE SL integrates three main functions e integrated high performance main memory subsystem e An IMBus interface that provides a high performance data flow path between the Pentium Pro bus and the I O subsystem e interface which provides an interface to the compatibility PCI bus segment and the CSB5 South Bridge Other features provided by the HE SL include the following e Full support of ECC on the processor bus e Full support of ECC on the memory interface e Eight deep in order queue e Full support of registered 133 ECC SDRAM DIMMs e Support for 6 GB of 2 way interleaved SDRAM e Memory scrubbing 3 3 1 1 Bus P32 A I O Subsystem The HE SL provides a legacy 32 bit PCI subsystem and acts as the central resource on this PCI interface P32 A supports the following embedded devices and connectors e CSB5 South Bridge e Two Intel 82550PM 10 100 Fast Ethernet PCI network interface controllers An ATI RAGE XL Video Controller with 30 20 graphics accelerator e Two 32 bit 33 MHz 5V full length PCI Slots Revision 1 2 9 Order Number A85874 002 Processor and Chipset Intel Server Board SDS2 3 3 2 CIOB20 Champion I O Bridge The Champion Bridge CIOB is 352 pin ball grid array device and provides
147. vice partition via modem 120 24 Secondary IDE References Added To Documentation for FAB 5 120 25 Potential Mylex AcceleRAID 352 Adaptor Card Mechanical Interference at PCI Slot 6 120 26 Bootable CD will not boot if inserted during OPTION ROM 121 27 Swapping bootable for non bootable CDROM during POST causes hang at boot 121 28 P100 NICs do not show at POST but attempt PXE boot and appear in Boot Menu122 29 Dodson Adaptec 39160 in slots 5 amp 6 causes Expansion ROM error 122 30 Not Change BIOS SETUP IDE Options Using Enter 123 31 Minimum Wait Time Between Power Off and Power On via Front Panel Power Button Is P CM lish cho atta 123 32 Unable to boot Netware 6 0 NW6 From CD ROM With Adaptec Adaptor 2100S in Slot 6 123 33 3C980C TX NIC causes Microsoft Windows 2000 blue screen when greater than 4GB of system memory is installed sssssssssseeseeeeeenen nenne 124 viii Revision 1 2 Order Number A85874 002 Intel Server Board SDS2 Table of Contents 34 Peer to peer PCI transactions are not supported between the CIOB controlled 64 bit PCI bus and the legacy 32 bit PCI bus controlled by the HE SL north bridge 125 35 SDS2
148. y custom blocks such as user binary The system should now boot normally using the updated system BIOS Revision 1 2 69 Order Number A85874 002 Clock Voltage Generation and Distribution Intel Server Board SDS2 7 Clock Voltage Generation and Distribution 7 1 Clock All buses on the SDS2 Server Board operate using synchronous clocks Clock synthesizer driver circuitry on the Server Board generates clock frequencies and voltage levels as required including the following e 133 MHz at 2 5 V logic levels For CPU1 CPU2 HE SL DIMM Sockets and the ITP port 66 MHz at 3 3 V logic levels For HE SL 64 and P64 C PCI slots e 48 MHz at 3 3V logic levels For CSB5 s USB e 33 3 MHz at 3 3 V logic levels For CIOB CSB5 and on board PCI devices and slots e 16 67 MHz at 2 5 V logic levels For processor and the CSB5 APIC bus clocks e 14 318 MHz at 3 3V logic levels For CSB5 and Video Other clock sources on the SDS2 Server Board generates 80 MHz at 3 3 V logic levels For Ultra 360 SCSI Controller e 32 768 MHz at 3 3 V logic levels For SIO and BMC e 14 318 MHz at 3 3 V logic levels for main clock generator For information on processor clock generation see the CK133 WS Synthesizer Driver Specification The following figure illustrates clock generation and distribution on SDS2 Server Board 70 Revision 1 2 Order Number A85874 002 Clock Voltage Generation and Distribution Intel Server Board SDS2
149. ystem using the Intel 82550 PM NIC The 82550 components are highly integrated PCI LAN controllers in a thin BGA 15 mm2 package The controller s baseline functionality is equivalent to that of the Intel 82559 with the addition of Alert on functionality The SDS2 Server Board supports independent disabling of either of the two NIC controllers under BIOS setup menu The 82550 supports the following features e 32 bit PCl Card Bus master interface e Integrated IEEE 802 3 10Base T and 100Base TX compatible PHY e 820 3u auto negotiation support e Chained memory structure similar to the 82559 82558 82557 and 82596 e Full duplex support at both 10 and 100 Mbps operation e Low power 3 3 V device Revision 1 2 15 Order Number A85874 002 Subsystem Intel Server Board SDS2 4 4 1 NIC Connector and Status LEDs The 82550 drives LEDs on the network interface connector to indicate link activity on the LAN and 10 Mbps or 100 Mbps operation e The green LED indicates a network connection when lighted solidly and TX RX activity when blinking e The amber LED indicates 100 Mbps a network connection when lighted solidly and TX RX activity when blinking 4 5 CSB5 South Bridge PCI to LPC Bridge IDE USB The CSB5 is a multi function PCI device housed a 256 pin BGA device providing PCl to L PC bridge PCI IDE interface PCI USB controller and power management controller Each function within the CSB5 has its

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