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HP 6131C User's Manual

1. veh xd xd fxd S ceramic 4 25Vdc ceramic 50Vdc mica 390pF 300Vdc mylar O1uF 200Vdc ceramic 1 50Vdc Si 200mA 75V SS NPN comp IKa 5 1 4W ww 1002 45 met film 7 5K 1 1 8W comp lKa 45 1 4W ww 1004 45 comp 3Ka 5 1 4 comp 9105 45 1 2W 7504 259 1 2W comp 750a 45 1 4W comp 824 45 1 4W comp IKa 595 1 4W comp 750a 2595 1 4W comp 824 45 1 4W comp 10 596 1 4W Diode zener 4 22V 400mW Diode zener 4 99V Diode zener 4 22 400mW Photo Isolator Monostable Multivibrator IC Logic Plug In Board fxd fxd fxd ceramic 47uF 25Vdc Mica 150pF 300Vdc ceramic 47 25Vdc tant 4 7uF 6Vdc pank 16 CO Refer to proper Option Appendix 28480 1901 0050 28480 1854 0071 Refer to proper Option Appendix EB 7515 01121 0686 7515 CB 8205 01121 0683 8205 CB 7515 01121 0683 7515 28480 1990 0407 28480 0160 0174 28480 0150 0121 RDMI15F39153C 72136 0140 0200 292 10552 5 55289 0160 0207 28480 0150 0121 28480 1901 0050 Refer to Instrument Modification Sheet 28480 1854 0071 Refer to proper Option Appendix Refer to Instrument Modification Sheet Refer to proper Option Appendix Refer to Instrument Modification Sheet 1025 01121 0683 1025 242 56289 0813 0050 M
2. EE EO IS RINE EE TET IGITAL VOLTAGE SOURCE MODEL 6131C BINARY LOGIC Was E SEEDERS OE NER TOATE SSE St SHAAN OH EEE AEDES RTCA ARE TSR ety ratte a RNY A MEET SR RAPES RR PER ZAI HE VA CMR NIE E SAE INTIS ESET IE HII OE _____ HEWLETT i PACKARD HP 6131C DIGITAL VOLTAGE SOURCE MODEL 6131 BINARY LOGIC OPERATING AND SERVICE MANUAL FOR SERIALS 13124 00101 AND ABOVE Serials Above 1312A 00101 a change page may be included Hewiett Packard HP Part 06131 90004 Printed October 1973 Section I IV TABLE OF CONTENTS Page No GENERAL INFORMATION 1 1 1 1 Description 1 1 1 10 interfacing l 1 1 13 Specifications 1 1 1 15 Options 1 2 1 17 Instrument Identification 1 2 1 20 Ordering Additional Manuals 1 2 INSTALLATION brane Med 2 1 initial Inspection 2 1 2 3 Mechanical Check 2 1 2 5 Electrical Check 2 1 2 7 Repacking for Shipment 2 1 2 9 Installation Data 2 1 2 11 Location 2 1 2 13 Outline Diagram 2 1 2 15 Rack Mounting 2 1 2 17 Input Power Requirments 2 2 2 18 Power Requirements 2 2 2 20 Connections for 230 Volt Operation 2 2 2 22 Power Cable 2 2 OPERATING INSTRUCTIONS 3 1 9 1 Data Input Connector 3 1 3 3 Input 3 1 3 5 Voltmeter Ranges 3 1 3 7 Ammeter Ranges 3 2 3 9 Programming 3 2 3 13 Voltage Magnitude and Voltage Sign Data Inputs 3
3. flag signal and the overload status signal are sent to the computer NPN CURRENT LATCH CODING CURRENT 124 123 LATCH mA RANGE 50mA 30mA more positive voltage LO more negative voltage as shown in Figure 3 7 the overload condition still exists after a variable delay period refer to next paragraph the unit commences current latch operation and the latch status signal changes state The current overload status signal switches to the normal state when the current latch mode commences A second 10 5 wide flag signal is produced when current latch begins NOTE For standard Option J20 the two 10usec Flag outputs corresponding to the leading and trailing edges of the Overload status output are disabled and not transmitted to the computer 3 31 Current Latch Delay Two terminals on the rear barrier strip provided for connection of a capacitor to delay the current latch circuit Capacitor C4 determines the delay between detec tion of an over current condition current overload Status and the time that current latch begins the current latch status signal switches to the over load state Some delay is desirable when driving 8 capacitive load since current surges higher than the current latch setting would activate the current latch circuitry If the terminals are open a natural delay period of from 3 to 10 approximate will result If capacitor CT is uti li
4. TRW Inc Philadelphia Pa Howard B Jones Div of Cinch Mig Corp New York Kurz and Kasch Inc Dayton Ohio Kilka Electric Corp Mt Vernon N Y Littlefuse Inc Des Plaines Minnesota Mining and Mfg Co St Paul Minn Minor Rubber Inc Bloomfield N F James Millen Mfg Inc Maiden Mass Compton Calif 71590 71700 71707 71744 71785 71984 72136 72619 72699 72765 72962 Dialight Corp 72982 73096 73138 73168 73293 73445 73506 73559 73734 74193 74545 74868 74970 75042 75183 75376 75382 75915 76381 76385 76487 76493 7 Mi er Co 76530 76854 77068 77122 77147 77221 77252 77342 776830 77764 78189 78452 78488 78526 78553 78584 79136 79307 79727 79963 80031 80294 81042 81073 81483 81751 82099 82142 82219 82389 82647 82866 82877 82893 83058 83186 83298 83330 83385 83501 Table 6 3 Code List of Manufacturers Continued MANUFACTURER ADDRESS Cinch Oak Mfg Co Div of Oak Electro Netics Corp Crystal Lake Ill Bendix Electrodynamics Div No Hollywood Calif Painut Mountainside N J Patton MacGuyer Co Providence Phaostron Instrument and Electronic Co South Pasadena Calif Philadelphia Steel and Wire Corp Philadelphia Pa American Machine and Foundry Co
5. Program the output voltage to 16 3835 volts Gate the unit Change to 35a 17W Perform Steps c through e h The voltmeter indication should change by less than 1 6mV from indication recorded in Step 4 5 23 Programming Time Definition Maximum time required for the output voltage to settle to within 0 1 of the programmed voltage change after simul taneous receipt of the data and gate com mands as measured with a resistive load 5 24 Equal positive and negative output voltages cannot be obtained by simple switching the posi tion of the polarity switch negative numbers must be programmed in the 2 s complement form For this reason a computer or calculator would be the easiest means to obtain the equal positive and negative numbers necessary to perform this test To perform this test for worst case result use the test setup in Figure 5 2 employing the com puter or calculator recommended Program the com puter or calculator so that it will program the DVS between 16 3835 and 16 384 volts and between 100and 100 volts The observed waveform should be within the tolerance of Figure 5 3 If the com puter or calculator is not available use the Pocket Programmer and Function Generator see Figure 5 2 as the programming device and proceed as foliows CONTROL SETTINGS Set switches on HP 3490A as follows 1 FUNCTION DC 2 RANGE As needed 10V or 100V 3 SAMPLE RATE HOLD MULTIMETER 3490 D
6. 4 74 The other output of multivibrator A124 the 50 microsecond positive pulse TP40 mentioned above is one of two input signals to an OR gate consisting of AICR1 and A6CR20 The other in put will be discussed under current latch and voltage range processing output of this OR gate TP31 feeds the flag isolator which is similar to the input isolators described above In this instance the isolstor is not used to iso late the computer from the DVS output since the input and output are both referenced to common 3 Here it used to make it possible to shift the dc level of the output stage so that it can interface with either an NPN or a PNP circuit 4 75 Following QS of the flag isolator are two optional amplifier inverter stages Q6 and Q7 The standard options either include an NPN Q6 stage as an inverter if that option requires a ready and busy HI output else leave out if the reverse logic sense is required Other instrument modifications may require an NPN or a PNP output of either logic sense To provide an PNP output jumpers W1 W2 and W3 are connected so that the entire output side of the isolator is connected between 12 volts and common 3 and transistors are used for and 07 Gircuit details depend on inter face requirements Refer to the appropriate Option Appendix or the Instrument Modification Sheet for this unit 4 76 Diq ital To Analog Converter
7. MAINTENANCE 5 1 INTRODUCTION 5 2 Upon receipt of the power supply the per formance test Paragraph 5 6 should be made This check is suitable for incoming inspection 1f a fault is detected in the power supply while making the performance check or during normal operation proceed to the troubleshooting pro cedures Paragraph 5 37 After troubleshooting and repair perform any necessary adjustments and calibrations Paragraph 5 69 Before return ing the power supply to normal operation repeat the performance test to ensure that the fault has been properly corrected and that no other faults exist Before performing any maintenance checks turn on the power supply and allow a 30 minute warm up 5 3 TEST EQUIPMENT REQUIRED 5 4 Table 5 1 lists the test equipment required to perform the various procedures described in this section NOTE n certain maintenance procedures including troubleshooting DVS piug in boards are required to be mounted on the Extender Board sup plied with the DVS The extender board includes an epoxy plate that is positioned with screws on either side of the extender board printed circuit board to interface with the particular plug in board being ex tended The following extender board screw positions for the epoxy board are to be used for extending the associated plug in board Extender Board Position Associated Plug In Board Logic A2 Input Al Control A6
8. Voltage bits out of calibration para graph 5 71 Defective board paragraph 5 46 Defective board paragraph 5 46 Sign bit circuit defective paragraph 5 47 Sign bit circuit defective paragraph 5 47 Voltage Processing circuits defective paragraph 5 47 A6 or A7 boards defective paragraph 5 46 Defective A7 board paragraph 5 64 Defective Al board paragraph 5 47 A7K defective Defective 6 board paragraph 5 55 Defective A6 board paragraph 5 55 Defective A6 or A7 boards paragraph 5 46 Table 5 3 Overall Troubleshooting Continued SYMPTOM PROBABLE CAUSE Poor Line Regulation Poor Load Regulation 5 46 Board Isolation Procedure The board iso lation procedure describes how to isolate trouble to the power amplifier board A7 the control board or to the voltage processing boards Al 2 and When the defective board s is located further isolation is necessary before the trouble can be traced down to a particular circuit or com ponent Paragraphs 5 47 through 5 68 describe troubleshooting procedures on individual boards which isolate the trouble down to a component or circuit The board isolation procedure assumes that an output voltage problem zero or incorrect output voltage exists To isolate troubles to the defective board s proceed as follows 1 Remove boards A2 and A3 from the DVS 2 Remove load and connect voltmeter ac ross HI and LO output te
9. shaded area on the front panel meter face indicates the amount of output voltage that is available in excess of the normal rated output Although the instrument will operate in this shaded region with out being damaged it is not guaranteed to meet of its performance specifications Figure 3 2 Operating Controls and Indicators 3 AMMETER RANGES 2 8 CURRENT control 3 selects the cur MS SUNL rent range on the front panel meter 0 06 0 15 or CURRENT 0 6 A 2 amp slo blo fuse is used as shown on 4 096 the rear of the unit 2 048V L22 30mA1 1 024 N C 3 9 PROGRAMMING 512mV VOLTAGE RANGE DATA 256mV 3 10 Input output data is connected from a digital VOLTAGE N C computer to P1 J1 on the rear of the DVS as shown MAGNIT UDE 4 DATA OVERLOAD STATUS in Figure 3 3 substitute for the computer i cse ze dir etapas HP Pocket Programmer This accessory plugs into i and manually programs all the input to the DVS by switch closures extension cable with 8mV connectors on both ends is also available to mate amv with 11 and the Programmer plug Pocket Program 2mV mers can be purchased from your local Hewlett Packard Sales Office im 0 6 LSB VOLTAGE SIGN DATA 3 11 The coding voltage levels and polarity of the input output data are selected by the customer to fit his applicetion Three plug in boards 1 SATE
10. 3025 01121 0686 3025 1 R28 fxd comp 5 1Ka 5 4 W 4 EB 5125 01121 0686 5125 1 29 fxd comp IKa 5 5 W 1025 01121 0686 1025 R30 fxd comp 1 2 5 1 EB 1225 01121 0686 1225 1 R31 fxd comp 2Ka 45 W 3 EB 2025 01121 0686 2025 1 R32 fxd comp 36Ka 45 5 2 EB 3635 01121 0686 3635 1 R33 fxd comp 2Ka 4595 iW EB 2025 01121 0686 2025 R34 fxd comp 36 5 3 W 3635 01121 0686 3635 R35 fxd comp 180 5 1 W 2 EB 1845 01121 0686 1845 1 R36 fxd comp 9102 5 5 W 1 EB 9115 01121 0686 9115 1 R37 fxd comp 180Ka 5 1845 01121 0686 1845 R38 fxd met oxide 36Ka 5 2W 1 Type C428 16299 0698 3651 1 R39 NOT ASSIGNED R40 ixd comp 2 7Ka 5 2 2725 01121 0686 2725 1 R41 fxd comp 104 5 4 W 2 EB 1005 01121 0686 1005 1 R42 fxd comp 5 1Ka 5 W EB 5125 01121 0686 5125 R43 fxd comp 510 5 EB 5115 01121 0686 5115 R44 fxd comp 8 2K 5 iw 2 8225 01121 0686 8225 1 R45 fxd film 221 1 1 8W 2 Type CEA 0 07715 0757 0473 1 R46 fxd film 8254 1 1 8W 2 Type CEA T 0 07718 0757 0421 1 RA7 fxd film 7 5Ka 1 1 8W 2 Type CEA T 0 07716 0757 0440 1 R43 fxd comp l 5Ka 596 3 3 EB 1525 01121 0686 1525 1 R49 fxd 27Ka 45 1 W 3 2735 01121 0686 2735 1 R50 fxd comp 1 3Ka 5 1W 2 GB 1325 01121 0689 1325 1 R51 NOT ASSIGNED R52 fxd comp 2 7 5 W EB 2725 01121 0686 2725 R53 fxd com
11. 30mA current latch input bits transistor 02 is conducting Q14 is cut off and 012 50mA stage does not conduct Under these conditions no ref erence current is supplied to the summing junction 012 Conversely when 02 is cut off 012 is allowed to conduct one of two fixed amounts of cur rent as determined by the current latch range bit Transistor 013 30mA stage is controlled in similar manner by the 30mA bit and the range bit 4 96 To better illustrate the action of this circuit assume that the programmed current latch is 20mA the three current latch data inputs are all In this case transistors 012 and O13 are not conduct ing because of high level inputs to Q2 and 03 Transistors Q1 and 8 are conducting thus limit ing the conduction of O11 to its X1 range value If a 200mA current latch is programmed same as above except current latch range data input is LO transistors 012 013 are cut off as before but range transistor Ql is not conducting This cuts off Q8 and the conduction of Q11 is increased to its X10 value 4 97 Negative and Positive Current Comparators The current comparators compare the voltage drop across current sampling resistor 5 proportional to the output current with the voltage drop across A6R30 or AGR37 proportional to the current latch value If the output current equals or exceeds the current latch reference value one of the Z4 compara tors positive
12. CURRENT OVERLOAD CHECK 27 Turn off power to the DVS Disconnect the 35a 17W load and connect the 200 1 50 watt minimum load resistor between the HI and LO terminals The jumper remains connected be tween the terminals 28 Check Option descriptions Appendix A B or C or where applicable the Modification Sheet in the manual to determine the existence of output transistor pull up resistor AGA6R8 If A6AG6R8 is used proceed to step 29 If AGAGRB8 is not used proceed to step 30 29 Connect a dc voltmeter between 0 LOAD STATUS and DATA COM test points on the Pocket PROGRAMMER Select a voltmeter range capable of reading 12 volts Proceed to step 31 30 Connect an ohmmeter between the 0 LOAD STATUS and DATA COM test points on the pocket programmer The common lead should be connected to the DATA COM test point 31 Program the current latch value for 20mA The I LATCH current latch switch positions on the Programmer are listed below for the six current latch values 32 Setthe voltage magnitude and OUTPUT SIGN on the Programmer for an output voltage of 3 5V 33 Turn on power to the DVS and press the Programmer GATE switch Overload status signal Should be normal voltmeters should indicate the collector voltage at output stage or the ohmmeter should indicate an open circuit 34 Increase the output voltage in 0 1V steps Overload status signal should switch to the overload state between 3 8V and 4 2 out
13. Voltmeter Ammeter Plug Input Power NPN Si Switch AC Line Switch Range Current Switch Range Voltage Power Transformer 5 Regulator IC Pes deb feet Type BWH Type C428 Type C428 Type C428 Type C428 EB 2015 EB 8205 EB 1645 Type C428 EB 1815 Type BWH Type C428 Type C428 428 425 2035 1N2163A 192P10392 NE 2H MDX 2A 110 72 212 18699 1 212 7966 1 5110236 0811 1671 0764 0031 0764 0007 0764 0045 0764 0031 0686 2015 0686 8205 0686 1645 0764 0031 0686 1815 0811 1671 0764 0045 0764 0031 0764 0007 0764 0045 0686 2035 9100 2185 1902 3185 1902 0597 1902 0763 1902 0064 1902 0597 1902 0184 1902 0182 0180 1921 0180 2385 0180 1808 0160 0161 2140 0015 2110 0303 1251 0087 1120 1154 1120 1155 1251 0086 1854 0463 3101 1055 3100 1916 3100 1919 06131 80091 1820 0430 1902 0048 HP PART NO Bes OO HS BO Re Y MER DESIG DESCRIPTION TQ MFR PART CODE PART RS MECHANICAL Al Input Board Card Extractor Handle Pin 5081 4901 1480 0059 52012062 250 2 Logic Board Card Extractor Handle 5081 4903
14. nect positive probe to base of A7Q25 and negative probe to 2 see Figure 7 2 sheet 3 If meter reads approximately 40 7 volts one drop the A7 latch circuit is defect ve see paragraph 5 67 If meter reads less than one voltage drop the A6 latch circuit is defective see par agraph 5 58 provided A7025 is not shorted from base to emitter 12 Apply a GATE pulse via the Pocket Program mer 14533B to get the DVS out of the latch condi tion 13 Measure output voltage Output voltage should be V If output is not Vy the latch circuits are defective see paragraph 5 67 14 Connect V to ANLG IN as shown in Figure 5 7B and measure the output voltage Out put voltage should be If not the latch circuits are defective see paragraph 5 67 15 Turn off the DVS and make the following test setup changes a Remove A7 extender board and return to its slot b Insert the 2 board in its slot C Install A3 with extender board side positive in the slot d Remove the input from the ANLG IN and LO S terminals On the Pocket Programmer set all volt age magnitude bits to the on position 16 board check voltages at TP52 16 384 41 TP53 16 384V 41 and 55 21 5V 45 voltages should be within toler ance if not check the associated regulating cir cuit on the A3 board 17 the Pocket Programmer set all volt age magni
15. 1 lector drivers Refer to proper Ap pendix for details Binary Interface for NPN Open Col lector Circuits Input output cir cuits on P C boards A1 A2 and are modified to interface with a binary source employing open collector drivers Refer to proper Appendix for details Option No 028 120 061 062 063 BCD Interface Microcircuit Logic Levels Input output circuits on boards 1 2 and A6 modi 1 2 fied to interface with BCD source employing microcircuit logic of the TTL or DTL family Refer to proper Appendix for details Binary Interface for Microcircuit Logic Levels Input output circuits P C boards A1 A2 and are modi fied to interface with a binary source employing microcircuit logic of the TTL or DTL family Refer to proper Appendix for details 064 1 17 INSTRUMENT IDENTIFICATION 1 18 Hewlett Packard instruments are identified by a three part ser al number The first part is the power supply model number The second part is the serial number prefix consisting of a number letter combination denoting the date of a significant design change The first digits indicate the yeat 10 1970 11 1971 etc the second two digits indicate the week and the letter A de signates the U S A as the country of manufacturer The third part is the power supply serial number different 5 digit sequential number is assigned to each po
16. and 7 is the specified load current change which is equal to the rated output current 5 34 A mercury wetted relay as connected in the load switching circuit of Figure 5 5 should be used for loading and unloading the supply When this OSCILLOSCOPE A METHOD USING A SINGLE ENDED SCOPE PROPERLY TERMINATED NOTE THAT GROUND CURRENT Ig MAY CAUSE ERRONEOUS RESULTS BOTH DVS AND OSCILLOSCOPE SHOULO PLUGGED INTO SAME AC POWER BUSS GROUND CURRENT iF P P SPECIFICATION EXCEEDED DUE TO Ig USE METHOD B OSCILLOSCOPE B METHOD USING A DIFFERENTIAL SCOPE WITH FLOATING INPUT GROUND CURRENT PATH 18 BROKEN COMMON MODE REJECTION OF DIFFERENTIAL INPUT SCOPE GNORES DIFFERENCE IN GROUND POTENTIAL OF OVS AND SCOPE HPI8O OSCILLOSCOPE WITH 1801 VERTICAL PLUG IN WITH OPTION 001 18214 TIME BASE PLUG IN AND TWO 100078 PROBES Peak to Peak Ripple and Noise Test Setup Figure 5 4 load switch is connected to 60Hz input mercury wetted relay will open and close 60 times per second Adjustment of the 25K control permits adjustment of the duty cycle of the load current Switching and reduction in jitter of the oscilloscope display 5 35 The maximum load ratings listed in Figure 5 5 must be observed in order to preserve the mer cury wetted relay contacts Switching of larger load currents can be accomplished with mercury pool relays with this technique fast rise times can still be obta
17. and Power Amplifier A7 Not Used Not Used Not Used Not Used Side Side mom Note further that when a board is ex tended the front panel cover should be completely removed to avoid any possibility of inadvertently touching the plug in board to the front panel cover 5 5 To conveniently program the DVS the Hewlett Packard Pocket Programmer Model 14533B is recom mended A three foot 50 conductor extension cable Model 145344 is available for convenience in attaching the Pocket Programmer to the rear pan el data input connector if the Pocket Programmer is to be used read the operating instructions in the Programmer manual before proceeding 5 6 PERFORMANCE TEST 5 7 The following tests can be used as an incom ing inspection check and appropriate portions of the test can be repeated either to check the opera tion of the instrument after repairs or for periodic maintenance tests The tests are performed using nominal 115 volt 60 Hz single phase input sup ply to the unit If the correct result is not obtained for a particular check do not adjust any controis proceed to the troubleshooting procedures 5 8 PRE OPERATION CHECKOUT 5 9 This procedure checks the basic operation of the DVS to assure that all programming functions are operating satisfactorily INITIAL CONDITIONS 1 Check that the rear terminal strip is connected as shown in Figure 3 1 HI should be strapped to S high sense
18. collapses rapidly causing to deenergize 4 132 POWER DISTRIBUTION See Figure 7 2 Sheet 4 4 133 12 26 140V and 155V bias and Suppiy voltages are obtained from power supply board A4 The 45V is obtained from chassis mount ed 5 volt regulator 21 Note that the 5 supply is referenced to 4 which is at 26V with respect to 2 the common potential for the 26V supply The 12V supply is referenced to 3 which is connected to the computer ground The 12V 26V 140V and 155V supplies are simple networks con taining rectifier diodes filter capacitors and bleeder resistors 4 134 Amplifier board A7 contains two regulator circuits for deriving 15V outputs from the 426V inputs Each circuit is composed of a series re gulator 026 028 and an input comparator stage 027 029 The input stage compares a portion of the output voltage with a fixed reference voltage across VR5 or VR6 If a difference exists it generates an error voltage which is of the correct amplitude to counteract this difference 4 135 Boards Al A2 A3 and A6 contain filter capacitors for various supply voltages In add ition board 1 contains zener diodes and resis tors to develop 5V referenced to 3 and board A6 contains a series regulator A6Q34 resistors and a zener diode to provide 4 99V referenced to 2 Series regulator A6Q34 also provides 14 5 output referenced to 2
19. ed properly 3 Disconnect the leads of the monitoring de vice at TP65 and 3 and connect to TP76 and 2 respectfully observing the presence of two logic levels as described in Step 2 If only one logic level is present check the 4 photo isola tor circuit paragraph 5 53 Also check network 621 4 Disconnect the lead of the monitoring device from TP76 and connect to TP73 checking for the pre sence of two logic levels as in Step 2 If only one logic level is present it is likely that A6Z1 or 622 is defective 5 Disconnect the lead of the monitoring device from TP73 connect to TP77 observing the sence of two logic levels as in Step 2 If only one logic level is present check A6Q25 for an open or short circuit If 2 logic levels are present the trouble lies within the board A7K1 7 2 5 61 Negative Programmable Output Current Latch Defective If the unit will current latch for posi tive output currents but not for negative output currents or if the unit is in current latch for all values of negative output current and works cor rectly for positive output current latch settings the cause of trouble must be in a circuit which handles the flow of the negative current latch sig nal There are two stages which handle only the negative output current latch signal A6Z4 and A6CRI 5 62 Positive Programmable Output Current Latch Defective If the unit will current latch for nega tiv
20. remains low b Output volt b Remove short and proceed age increases to Step 2 Short A7O4 emitter to collector 8 Output voltage A7O5 opened remains low b Output voltage b Remove short and proceed increases to Step 3 Short A7Q3 base to emitter Output voltage 704 opened 703 shorted remains low b Output voltage b Remove short and proceed increases to Step 4 Short A7Q1B emitter to collector Output voltage a 702 defective remains low b Output voltage b Remove short Check increases 7 for short and QIB for open 5 30 d Table 5 15 ACTION RESPONSE Feedback Differential Amplifier Troubleshooting Unit Locked Up Full Positive CONCLUSION Short A7Q5 emitter to base a Output voltage remains high b Output voltage decreases Short A7Q2B emitter to collector and 7024 emitter to base Output voltage remains high b Output voltage decreases Short A7O1A emitter to a collector A7Q1B emitter to Output voltage remains high b Output voltage decreases 5 69 ADJUSTMENT AND CALIBRATION 5 70 Adjustment and calibration may be required after performance testing troubleshooting or pair and replacement Perform only those adjust ments that affect the operation of the faulty circuit and no others All the controls referred to in these adjustments are shown on the component location diagrams in Section
21. 104 The latching flip flop is also set when the Shorting relay 4 1 is deenergized Figure 7 2 Sheet 3 This ensures that the power amplifier is turned off when the output terminals are shorted by contacts of relay AAK 4 105 Buffer and Current Latch Status Circuits The buffer amplifier A6Q21 inverts the negative going latch signal from Q20 and applies it to the power amplifier Figure 7 2 Sheet 3 and to the latch status isolator output amplifier A6A5 The isolator 6 521 01 Q2 is similar to the input isolators previously described The latch status isolator provides a LO output to indicate latched status and a HI output for normal condition The output amplifier stages A6A5Q3 and A6A5Q4 that follow 6 502 provide sufficient current drive and proper signal inversion to interface with the computer Circuit details depend on interface requirements Refer to the appropriate Option Appendix or tne Instrument Modification Sheet for this unit 4 106 QCurrent Overload Circuits The current overload circuits consist of an overload flag gen erator isolator output inverter and over load status isolator output amplifier circuit If the current latch value is exceeded the negative going overload signal at TP17 is applied to the overload flag generator and to the overload status isolator and output amplifier circuit 4 107 Overload Flag Generator The overload flag generator consists of two emitter coupled am
22. 24 To preserve the protection feature when erating the instrument from a two contact outlet use a three prong to two prong adapter and con nect the ground lead on the adapter to ground SECTION OPERATING INSTRUCTIONS Figure 3 1 Model 6131C Rear View 3 1 INPUT CONNECTOR 3 2 Before output voltage can be obtained data input plug P1 must be in place as shown in Figure 3 1 A connection must be made between the cable continuity interlock pin 25 and the computer com mon relay A4K1 must be energized see Figure 7 2 Sheet 3 this connection is not present or if the input connector is removed the output termin als will be shorted and the output current will be reduced to less than 10mA This protects any loads connected to the DVS in the event that the cable is inadvertently disconnected Note also that the output is shorted when ac power is removed 3 3 AC INPUT 3 4 To turn on the unit set the LINE switch item in Figure 3 2 to The pilot light directly above the LINE switch should light Fuse 1 2A at 115Vac or 1A at 230Vac protects the main power supply NOTE Any deflection of the current meter after turn off does not represent cur rent flowing in the load but rather is current flowing through the internal shorting relay 3 5 VOLTMETER RANGES 3 6 The VOLTAGE control 2 selects either the 120V or 20V range which corresponds to the upper and lower scales on the voltmeter
23. 3 3 17 Storage 3 3 3 20 Voltage Range 3 3 3 24 Current Limit 3 4 3 29 Current Overload and Latch 3 4 3 35 Connecting the Load 3 6 3 41 Current Monitor 3 6 3 43 Analog input 3 6 PRINCIPLES OF OPERATION 4 1 4 1 Introduction 4 1 4 3 Basic Block Diagram Discussion 4 1 4 6 Voltage Processing 4 2 4 10 Current Latch and Voltage Range Processing 4 2 4 15 Power Amplifier 4 2 4 20 Power Distribution 4 3 4 22 Detailed Block Diagram Discussion 4 3 4 25 Voltage Processing 4 3 4 40 Power Amplifier 4 5 V MAINTENANCE oue 5 3 5 6 5 8 5 1 5 3 5 4 0 7 2 5 69 5 71 5 73 S5275 5 77 S79 VI 6 1 6 3 VII o M 03 9 7 7 APPENDIX A 1 5 7 9 REPLACEABLE PARTS Introduction Test Equipment Required Performance Test Pre Operation Checkout Constant Voltage Tests Troubleshooting Overall Trouble Isolation Procedure Voltage Processing Circuit Troubleshooting Photo Isolator Circuit Troubleshooting Control Board Troubleshooting 6 Power Amplifier Board Troubleshooting Adjustment and Calibration Output Voltage Adjustment Meter Zero Voltmeter Adjustment Ammeter Adjustment Current Latch Adjustment 4 Introduction Order Information CUIT DIAGRAMS Introduction Overall Block Diagram Component Location Illustrations Schematic Diagrams OPTION introduction Data Connector
24. 49 fxd comp 5 IKa 5 1 4W CB 5125 01121 0683 5125 R50 52 fxd comp 10 259 1 4W CB 1035 01121 0683 1035 1 R53 54 fxd comp 20Ka 259 1 4W CB 2035 01121 0683 2035 R55 56 fxd comp 10Kn 5 1 4W CB 1035 01121 0683 1035 55 59 fxd comp 2Ka 45 1 4W CB 2025 01121 0683 2025 1 59 fxd comp 5 1 5 1 4W 5125 01121 0683 5125 860 fxd comp 10 259 1 4W CB 1035 01121 0683 1035 R61 63 fxd comp 20Kn 45 1 4W CB 2035 01121 0683 2035 R64 65 fxd comp 5 IKa 5 1 4W CB 5125 01121 0683 5125 R66 fxd comp 1004 595 1 4W CB 1015 01121 0683 1015 1 67 fxd comp 259 1 4W CB 1025 01121 0683 1025 1 R73 fxd comp 4 7 259 1 4W CB 4725 01121 0683 4725 i R74 fxd comp 20Ka 4595 1 4W CB 2035 01121 0683 2035 R75 fxd comp 6 2Ka 5 1 4W CB 6225 01121 0683 6225 1 R76 ip fxd comp 100Ka 2595 1 4W CB 1045 01121 0683 1045 1 R77 fxd comp 5 6 5 1 4W 5625 01121 0683 5625 R78 fxd comp 4 7 45 1 4W CB 4725 01121 0683 4725 R79 fxd comp 2Ka 45 1 4W CB 2025 01121 0683 2025 R80 fxd comp 20Ka 45 1 4W CB 2035 01121 0683 2035 R81 fxd comp 2 7Ka 595 1 4W 2725 01121 0683 2725 1 R82 fxd comp 1 596 1 4W CB 1025 01121 0683 1025 R83 fxd comp 200Ka 596 1 4W CB 2045 01121 0683 2045 1 R84 fxd comp 5 IKa 595 1 4W CB 5125 01121 0683 5125 R85 fxd comp 33Ka 5 1 4W CB 3335 011211 0683 3335 1 R86 fxd comp 82Ka 45 1 4W CB 8235 01121 0683 8235 1 R87 fxd comp 3 6 595
25. 5 7 DVS Analog Input Connections 6 Measure the output voltage Output should be 10 0 2 If output is 10V 40 295 pro ceed to step 7 If output is 0 2 the pro blem is in the range circuits on board A6 paragraph 5 61 or the range relay A7K1 is defective the output is not 10V 40 2 V 40 2 trouble shoot the A7 board paragraph 5 64 7 Connect a positive dc voltage Vx be tween the ANLG IN and LO S terminals as shown in Pigure 5 7B Set the RANGE switch on the Pro grammer to X1 8 Measure the output voltages Output should be 0 2 If output is Vx 0 2 proceed to step 9 If output is 10V 0 2 the problem is in the range circuits on board A6 paragraph 5 61 or the range relay A7K1 is defective output is not Vx 0 2 or 10Vy 0 2 troubleshoot the board paragraph 5 64 9 Turn off DVS and make test setup changes Remove the A7 board and install it with the extender board side position D in the A7 slot b Connect 2004 load in parallel with the voltmeter across the HI and LO output terminals Connect V to ANLG IN as shown in Figure 5 7 10 Turn DVS and measure output Output should be less than 1 volt because the DVS should be in the latch condition If output is less than 1V proceed to step 12 If output is Vy DVS is not in latch condition proceed to step 11 11 Measure the voltage across A7R92
26. 52012062 250 1480 0059 1 Socket 16 21 4 79 12 316 AG5D 3R 1200 0767 1 IC Socket 14 25 26 314 AG5D 3R 1200 0768 A3 D A Board Card Extractor Handle Roll Pin Heat Dissipator 031 5081 4905 1480 0059 1205 0033 52012062 250 207 Control Board Card Extractor Handle Roll Pin Heat Dissipator Q34 5081 4906 1480 0059 1205 0033 52012062 250 207 Amplifier Board Card Extractor Handle Roll Pin Heat Dissipator Q6 7 11 13 15 17 26 28 31 33 06131 80001 1480 0059 52012062 250 207 1205 0033 Front Panel Assembly Front Panel loaded 06131 60009 Front Panel lettering 06131 60008 Meter Bezel 4040 0297 i Meter Spring 1460 0256 2 Base Indicator 251 5040 0305 1 Lens Indicator 081 5040 0234 i Knob Black Pointer 0370 1099 1 Front Door Assembly Door Blank Lettering Only 28480 28480 06130 60009 06130 00012 Spring Door 28480 06130 00011 Lens Door 28480 5040 0234 Latch Door 27 10 301 10 94222 1390 0037 Rear Panel Assembiy 5060 7992 Rear Panel 5000 9490 Barrier Strip 10 Terminal 0360 1156 Jumper Barrier Strip 0360 1143 Heat Sink Rear 5020 8068 Cover Heat Sink Spacer Heat Sink Cover Hex 8 32 x 5 8 long AC Line Cord Strain Relief Bushing Line Cord Shoulder Washer Gray 01 06 Mounting Screws 5000 9442 0380 0
27. Check A6Q16 for open Connect voltmeter common to TP99 and check TP15 Voltage magnitude less than 20mV a Current sampling circuit operating properly go to Step 9 b Check current sampling resistor and interconnect wires b Voltage magnitude is more than 20mV Connect voltmeter common to 2 4 Check TP35 Logic level 1 a Negative current comparator is operating properly go to Step 10 b Voltage magnitude equals approximately 13V b Check current latch decoder see 5 63 1f current latch decoder circuits are operating properiy check the negative cur rent comparator circuit 624 R39 R33 R31 Check TP36 a Positive current comparator is operating properly check OR gate CR2 for shorts a Logic level 1 Table 5 8 Unit Always Current Latch Continued ACTION RESPONSE CONCLUSION Check TP36 b Voltage magnitude b Check current latch decodat Continued equals approximately see para 5 63 If current 13V latch decoder circuits are oper ating properly check the posi tive current comparator A6Z4 R32 R34 R43 and the negative reference inverter 603 23 Table 5 9 Unable to Current Latch at Turn On NOTE Positive voltage equals logic level 1 logic level 0 equals approximately OV unit off pono gt 5Ka a Relay ONU
28. EB 5625 01121 0686 5625 1 R8 Refer to proper Option Appendix VRI Refer to proper ption Appendix 21 1 Photo Tsolator 1 28480 1900 0407 1 A6A 6 Overload Status Tsolator and Output Amplifier 2 Diode 200ma 75V 2 28480 1901 0050 2 Q1 3 SS NPN Si 3 28480 1854 0071 3 Q4 Refer to Instrument Modification Sheet R1 fxd comp 10 5 1 4W 1 CB 1035 01121 0683 1035 1 R2 fxd comp 1 3Ka 45 1 2W l 1325 01121 0686 1325 1 R3 fxd comp 7504 5 1 2W 1 EB 7515 01121 0683 7515 1 R4 fxd comp 82a 595 1 4W 1 CB 8205 01121 0683 8205 1 R5 fxd comp 12Ka 5 1 4W i CB 1235 01121 0683 1235 1 R6 fxd comp 1004 596 1 4W 1 1015 01121 0683 1015 1 R7 Refer to Instrument Modification Sheet R8 Refer to proper Option Appendix VRI Refer to proper Option Appendix Zl 1 28480 1900 0407 1 A6C1 fxd mica 240 300Vdc 4 RDMI15F241 3C 00853 0140 0199 1 6 9 MER HP DESIG DESCRIPTION MFR PART CODE PART NO 6 2 fxd ceramic 47uF 25Vdc 5011B7 56289 0160 0174 fxd mica 30pF 300 RDMISE300 3C 00853 0160 2199 fxd mylar 0014F 200Vdc 3 192 10292 56289 0160 0153 1 5 6 7 fxd mica 240pF 300Vdc RDMI5F241J3C 00853 0140 0199 C8 fxd mylar 2200pF 200Vdc 1 192P22292 56289 0160 0154 1 9 10 fxd mylar 001yF 200Vdc 192P10292 55289 0160 0153 C11 fxd mylar 200Vdc 1 192233392 56289 0160 0163 1 C12 fxd mica 150 300Vdc 1 RDMISFi1S1 3C 00853 0140 0196 1 013 14 fxd mica 390 3
29. LINES MAGNITUDE DATA VOLTAGE SIGN OR BCD 16 LINES VOLTAGE PROCESSING SHEET I POLARITY DATA GATE REAL FROM COMPUTER RESET STORAGE GATE CURRENT LATCH DATA 3 LINES CURRENT LATCH AND VOLTAGE RANGE PROCESSING SHEET 2 VOLTAGE RANGE DATA X1 X10 Q CT Q CURRENT LATCH DELAY Figure 4 4 1 INTRODUCTION 4 2 This section contains the principles of oper ation for the Digital Voltage Source DVS The section is divided into three main paragraphs a basic block diagram discussion a detailed block diagram discussion and a detailed circuit analysis The depth of coverage increases with each level of discussion until in the detailed circuit analysis the function of each major component is described using the schematic diagrams of Figure 7 2 OVERLOAD STATUS INPUT 230VAC POWER FLAG VOLTAGE MAGNITUDE Bi POLAR CURRENT POWER AMPLIFIER SHEET 3 OVLD RANGE FLAG ENABLE VOLTAGE RANGE CURRENT LATCH CURRENT SAMPLING LATCH STATUS jos POWER 12 DELAYED POWER DISTRIBUTION SHEET 4 Basic Block Diagram 4 3 BASIC BLOCK DIAGRAM DISCUSSION 4 4 Figure 4 1 is a basic block diagram of the DVS showing its four major circuits together with the principle input output signals of each circuit Each major circuit has an associated sheet number for correlation
30. Measure Impe go to Step 2 dance between 2 and TP98 Impedance lt 5Ka b Relay 4 1 defective causing false resetting of latching flop Connect voltmeter Logic levei 0 a No latch go to Step 3 common to 2 Tum unit on Do Logic level 1 b Latch circuit on 6 board not GATE Check is operating check latch circuit TP21 on A7 board paragraph 5 67 3 Check TP20 Logic level 1 a Buffer stage A6Q21 probably working go to Step 4 Voltage magnitude Buffer stage 6021 not equals approximately working check A6Q21 for short 5V 4 Check 4 a Logic level 0 6020 probably working Reset amplifier may be defective Check 024 for short and 6022 for open If reset amplifier is working properly go to Step 5 b Logic level 1 b Check A6Q20 for short 5 With an oscilloscope 98 goes low a Delay for A4K1 working observe operation of t2200ms after power check complete A4K1 TP98 and turn on of power TP88 b TP98 goes low b Check 12V delayed circuit es Both referenced to 2 200ms after power on pecially A4C10 CR22 for shorts See Figure 7 2 sheet 4 5 23 Table 5 10 Unable to Current Latch at Latch Settings NOTE Logic level 1 equals a positive voltage logic level 0 equals approximately OV ACTION RESPONSE CONCLUSION a Goto Step 2 Turn unit off Measure impedance from TP18 to 2 connect positive meter lead t
31. Potter and Brumfield Div Princeton Ind Electronic Components Div Camden Resistance Products Harrisburg Pa Illinois Tool Works Inc Shakeproof Div Elgin Everlock Chicago inc Chicago Stackpole Carbon Co St Marys Pa Stanwyck Winding Div San Fernando Electric Mfg Co Inc Newburgh Tinnerman Products Inc Cleveland Ohio Stewart Stamping Corp Yonkers N Y Waldes Kohinoor Inc L i C N Y Whitehead Metals Inc New York N Y Continental Wirt Electronics Corp Philadelphia Pa Zierick Mfg Co Mt Kisco Y Mepco Div of Sessions Clock Co Morristown T Bourns Inc Riverside Calif Howard Industries Div Msl Ind Inc Racine Wisc Grayhill Inc La Grange International Rectifier Corp El Segundo Calif Columbus Electronics Corp Yonkers Goodyear Sundries amp Mechanical Co Inc New York N Y Airco Speer Electronic Components Du Bois Pa Sylvania Electric Products Inc Electronic Tube Div Receiving Tube Operations Emporium Switchcraft Inc Chicago Metals and Controls Inc Control Products Group Attleboro Mass Research Products Corp Madison Wis Rotron Inc Woodstock N Y Vector Electronic Co Glendale Calif Carr Fastener Co Cambridge Mass Victory Engineering Corp Springfield Jj Bendix Corp Electric Power Div Eatontown N J Herman H Smith Inc Brooklyn N Y Central Screw Chicago TIL Gavi
32. RESET AND DISCONNECT LOCK CHECK 6 On the Pocket Programmer switch on the 8192 bit Observe that the digital voltmeter indi cates approximately 0 3 volts 81 92 and the DVS CURRENT meter reads less than 10mA The error is because the over current latch circuit activated when the DVS was turned on NOTE Whenever the DVS is turned on the Gate switch must be toggled to reset the over current latch circuit 7 Press the Pocket Programmer GATE switch The digital voltmeter should indicate 81 92V and the DVS CURRENT meter 410mA 6 scale 8 Disconnect the Pocket Programmer data input cable The meters will indicate OV and less than 10mA The instrument is in the disconnect interlock and overcurrent latch status mode 9 Reconnect the data input cable The meters will indicate 0 and less than 10mA instrument is still in the overcurrent status 10 Press the Pocket Programmer GATE switch The meters will indicate 81 92V and 410mA again The VOLTAGE RANGE CHECK 11 Set the RANGE switch on the Pocket Programmer to X1 The digital voltmeter should read 8 192V VOLTAGE MAGNITUDE CHECK 12 On the Programmer turn on all of the voltage magnitude bits The digital voltmeter reading will be 16 3835V 0 001V 13 Turn off all of the voltage magnitude bits The voltage reading will be 0 volts 0 001 volts 14 Turn on each voltage magnitude bit 0 5 through 8192
33. STEP OUTPUT ov MEASURE OUTPUT HERE STEP CHANNEL i 8 SIGN PROGRAMMING T lt RANGE PROGRAMMING TIME Figure 5 3 Programming Time Waveforms Example as before Wout 16 3845 volts 0 1 of 16 Fora 8 1925 volt to 8 192 voit transition look for a reading of 8 176 volts on the 3490 f Using the DELAY control on the 1821 start at the zero crossing and sweep until the volt age in step e is reached Determine the time T from the transition time of channel B trace to the beginning of the bright spot DVS programming time wili then be Programming Time 5 25 Ripple and Noise Definition The residual ac voltage which is superimposed in the dc out put of a regulated power suppiy Ripple and noise may be specified and measured in terms of its RMS or preferable peak to peak value Ripple and noise measurement can be made at any input ac line voltage combined with any dc output voltage and load current within rating 5 26 The amount of ripple and noise that is pres ent on the power supply output is measured either in terms of the RMS or preferable peak to peak value The peak to peak measurement is parti cularly important for applications where noise spikes could be detrimental to a sensitive load such as logic circuitry The RMS measurement is not an ideal representation of the noise since fairly high output noise spikes of s
34. The digital to analog circuits consist of bit switches and ladder networks a polarity offset switch and two reference voltage circuits The converter provides dis crete output currents as determined by the voltage magnitude input bits from the storage flip flops 4 77 D A Bit Switches and Ladder Networks This circuit is composed of four similar sets of bit switches and resistive ladder networks one per Bit The switching circuits consist of transistors 201 3 through 1601 3 while the analog ladder networks consist of resistors A3R50 through 96 Since all four networks are similar only the network for the four most significant digits is described in the following paragraphs 4 78 The bit switch network consists of a driver Qi and two low saturation switching transistors Q2 and 03 With a voltage program input of 4 volts 001111101000000 the D A Board switching cir cuits receive the complemented input of 12 3835 110000010111111 The high inputs the digits which have a value of binary 1 A16 A15 9 etc at the base of Q1 are inverted and through steer ing diode CR1 cause Q2 to turn on placing a 16 384V on the input line to the ladder network The low inputs the digits which have a value of binary 0 A14 A13 A12 etc at the base of Q1 are inverted and through steering diode CR2 cause Q3 to turn on placing OV ground on the input line to the ladder network 4 79 Inthe simpl
35. a GATE signal is applied 3 10 CONSTANT VOLTAGE TESTS 5 11 For constant voltage measurements the measuring device must be connected across the rear sensing terminals of the supply in order to achieve valid indications measurement made across the load includes the impedance of the leads to the load and such lead lengths can easily have an impedance several orders of magnitude greater than the supply impedance 10 milliohms at dc thus invalidating the measurement 5 12 To avoid mutual coupling effects each mon itoring device must be connected directly to the sensing terminals by separate pairs of leads The load resistor is connected across the output termi nals and must be selected according to the output voltage and current of the supply When measur ing the constant voltage performance specifica tions the CURRENT LATCH should be programmed well above the maximum output current which the supply will draw since the onset of current latch action will cause a drop in output voltage in creased ripple and other performance changes not properly ascribed to the constant voltage oper ation of the supply 5 13 Calibration Error Definition The maximum absolute voltage accuracy deviation at constant room temperature 115 input no load following a minimum warm up time of 30 minutes It is the ability of the instrument to accurately convert a di gital input into an analog output volt age 5 14 To measure the acc
36. and LO to LO 5 low sense 4 Connect a digital voltmeter in parallel with a 2004 1 50 watt resistor across the LO terminals on the rear of the DVS 3 Connect the Pocket Programmer to the data input connector and set its switches as fol lows a Setthe INPUT LEVEL REF switch to DATA COM b Set the MP DCPS switch to DCPS C Set the SOURCE SELECT switch to EXT The above three switches remain in these positions Variable Voltage Loads Resistor Function Supply meter Device Repetitive Load Switch Resistive DC Power Rms Volt Transformer Oscilloscope DC Voltmeter Generator Programming Table 5 1 Test Equipment Required Sensitivity 100 full scale Accuracy 0 004 Current Rating 2A Range 90 130Vac Equipped with voltmeter accurate within 1V Differential input dc to S0MEHz Accuracy 1 Input resist ance 20 000 ohms volt min Rate 60 400Hz 2usec rise and fall time 200a SOW 5 35a 17 5 Value 200a 51 50 watts 0 0005Hz 5MHz 0 25Vdc 0 400mA 10Hz 10M Hz throughout all of the following procedures Set the RANGE switch to X10 Set the data and sign bit switches for an output f 0 00 volts The proper coding for Pocket Programmer data and sign bit switches depends on the instrument being programmed The v
37. be 0 0064 milliamperes 0 0028mA and 0 00035mA Summing all four currents together yields a final result of 1 23835mA total flowing into TP56 from the ladder network output of the ladder network is summed with 1 6384 from the polarity switch yielding a net input to the power amplifier of 0 40005mA con tinuous offset current of 0 05 A at the operational amplifier input yields an effective power amplifier input of 0 40000mA The power amplifier ampli fies this current to produce a 4V DVS output volt age 4 82 Potentiometers A3R52 through A3R59 are justed to compensate for the conducting resistances of 02 03 and resistance tolerances within the net work With these controls properly adjusted the total series resistances in each rung are 20Ka as shown in Figures 4 5 and 4 6 Notice that the out put current of each of the four ladder networks are weighted in powers of 16 Thus resistor A3R92 divides the output current of that rung by 16 resis tors A3R93 R94 divide the next rung output current by 256 and resistors A3R95 R96 divide the output current of the remaining rung by 4096 This circuit 4 83 Polarity Offset Switch Circuit consists of amplifier A3Q13 and switch A3Q14 constant reference of 16 384V is supplied to the emitter of switch 014 With a negative sign input 013 receives a high level input signal and switch A3Q14 does not conduct With positive input sign however Q13 receives a low
38. comp 200a 5 W EB 2015 01121 0686 2015 R109 fxd comp 824 45 1 W EB 8205 01121 0686 8205 R110 NOT ASSIGNED Rill fxd comp 1804 45 4 W EB 1815 01121 0686 1815 R112 fxd comp 200a 5 W 2015 01121 0686 2015 R113 fxd comp 274 5 4 W 2705 01121 0686 2705 pe DESIG DESCRIPTION MFR PART NO A7R114 R115 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 128 R129 R130 R131 T1 VR1 2 VR3 4 VR5 6 VR7 VR8 9 VR10 VR11 VR12 13 Cl 2 C4 5 C6 7 DSI Fl n 1 M2 Pl 01 6 51 82 83 T3 21 fxd ww 2 75 5 2 fxd met oxide 47Ka 5 2W met oxide 27Ka 5 2W fxd met oxide 22K 5 2W fxd met oxide 47Ka 4596 2W fxd comp 2004 5 5 W NOT ASSIGNED fxd comp 82a 5 4W fxd comp 160Ka 5 4 W fxd met oxide 47Kn 596 2W fxd comp 1804 5 4 W fxd ww 2 7 559 2W fxd met oxide 22 595 2W fxd met oxide 47 5 2W fxd met oxide 27Ka 5 2W fxd met oxide 22Ka 596 2W fxd comp 20K 5 1 2w Toroidal Transformer 1 1 1 Diode Zener 12 4V 400mW Diode Zener 56 2V IW Diode Zener 9 4V 500mW Diode Zener 7 5V 400mW Diode Zener 56 2V 1W Diode Zener 16 2V 400mW Diode Zener 20 5 400mW Diode Zener 6 8V 400mW CHASSIS ELECTRICAL PARTS fxd elect 5 600 25Vdc fxd elect 8 600 amp F 25Vdc NOT ASSIGNED fxd elect 430nF 200V fxd mylar 0 01u4F 200Vdc Lamp glow 115V Fuse 2A 250V Jack Input
39. converter due to drift or other disturbances 4 86 The 16 384V reference supply contains series regulating feedback loop composed of com parison amplifier 011 error amplifiers 012 and Q15 and series regulator 010 Incipient changes in the 16 384V output are detected by Q11B am plified by Q12 and Q15 and applied to the series regulator Feedback loop stability is maintained by output capacitor C13 and feedback network C12 R21 4 87 421 5 Volt Regulator regulated 21 5 volts is obtained from series regulator A3Q40 and zener diode VR40 which keeps the base voltage of Q40 at a constant level 4 88 CURRENT LATCH AND VOLTAGE RANGE PROCESSING See Figure 7 2 Sheet 2 4 89 Input Isolator Circuits The four input isola tors A6Al through A6A4 forthe latch bits range 50mA and 30mA and the voltage range bit are identical to those used in voltage processing refer to paragraph 4 68 The current latch range X1 or X10 input bit L24 is at positive level for the X1 range and a more negative level forthe Xl0range The 30mA and 50mA bits L22 and L23 of current latch data must be LO true negative logic form For example when the 30mA input L22 is LO more negative level the 30mA bit is present and when the 30mA input is HI more positive level the 30mA bit is absent The voltage range input bit is at more negative level for the X1 range and positive level for the X10 range The input isolators invert
40. depending on which half of the amplifier is active at the time The conduc tion of the other series transistors Q1 and Q5 or 04 and 13 controlled by the positive or negative bias transistors 014 015 Q30 and 031 or 16 Q17 Q32 and Q33 4 125 The function of the bias networks is to di vide the voltage drop and thus the power dissipa tion among the three series connected power tran sistors in the active branch This is accomplished by sensing the programmed output voltage level and using it to develop two additional voltages one representing the output voltage plus 2 3 of the difference between 140 volts and the output volt age and the other representing approximately 1 3 of the same value For the positive bias network R116 and R115 develop the 2 3 voltage function while R118 and R117 develop the 1 3 voltage func tion R126 through R129 perform the same function for the negative bias network The 2 3 voltage level at the junction of R116 and R115 is power amplified by compound emitter followers Q30 and 031 and appears at approximately the same 2 3 voltage level at the emitter of power transistor Q5 The 1 3 voltage level is similarly amplified by 014 and 015 and appears at the emitter of Q1 From this it can be seen that 1 3 of the voltage drop between 140 volts and the programmed voltage level appears across each of the three series con nected power transistors The negative bias net work operates in a simi
41. for this board has been broken down according to input and output Signals Table 5 6 lists the possible trouble symptoms and directs the reader to the correct paragraph or table for further isolation Before proceeding to Table 5 6 for the paragraph table applicable to the trouble present the following procedure should be used to determine if the trouble lies within the input circuits a Remove the board and install it in the extender board Install the extender board A6 combination in the A6 board slot b Connect a voltmeter or logic probe be tween 2 common and TP75 of the bit to be test Set the STORAGE DISABLE switch to DIS ABLE d Toggle bit to be tested If two logic levels can be obtained proceed to Table 5 6 If only one logic level is present proceed to Para graphs 5 57 5 58 and 5 59 Two logic levels present Two logic ievels present Two logic levels present Q2 collector remains low or zero if failure persists check for bridged or open P C Proceed to Step 2 Q2 collector still remains b Q2 shorted Replace low or zero Q2 and retest entire isolator stage If output now remains high proceed to Table 5 4 Q1 shorted Replace Q1 and proceed to Step 3 21 shorted Replace Zl and proceed to Step 3 Proceed to Table 5 4 Repair completed Q1 shorted Replace Q1 and repeat Step 3 Proceed to Table 5 4 conductors 5 57 Latch Data In
42. individually and check the digital voltmeter readings in the following chart all read ings lmvV NOTE Turn each bit off after making check SWITCH READING SWITCH READING 12 mV 256mV 1 024V 2 048 4 096V 8 192V 128 256 512 1024 2048 4096 8192 0 SmV imV 2mV 8mV iGmV 32mV 64mV 5 3 15 Switch the STORAGE DISABLE switch on board A2 to the STORAGE position 16 Repeat the sequence of Programmer switch operations of step 14 but press the Pro grammer GATE switch after each voltage magnitude bit change Observe that the previously program med voltage remains until the new value is gated into storage 17 Switch the STORAGE DISABLE switch back to the STORAGE DISABLE position set the OUTPUT SIGN switch on the Programmer to the negative position and turn off all voltage magni tude bits to obtain 0 5mV imV 18 Repeat steps 14 15 and 16 set voltage magnitude switches so that the input is received in the negative 2 s complement code To obtain any negative number first complement the corresponding positive number and then add a binary 1 to the least significant digit example to program the unit to a 0 5mV output switches 0 5 through 8192 must be set to their binary 1 position To program the supply to lmV the 0 5 switch is set to binary 0 and the remaining switches are set to 1 stated previously the proper coding for the
43. input causing O14 to Saturate A path for the offset current of 1 6384mA is now completed to the summing point Potentiom eter A3R100 provides a means of adjusting the off Set current 4 84 D A Converter 16 384 Volt Reference Circuit This circuit provides aregulated output voltage of 16 384Vdc maintain the output volt age constant a series regulating feedback loop is employed A reference comparator circuit AR Z1 As described previously the 1 23835mA compares a portion of the output voltage across divider R34 R36 and AR R3 with an internal zener diode reference voltage If a difference exists the comparator sends an error signal to series regulator Q31 via driver Q32 This error signal is of the phase and amplitude necessary to counteract the original difference Transistor Q30 provides a con Stant biasing current to 032 and 21 Potentiom eter R36 can be adjusted to alter the voltage divider resistance and thus the 16 384 output Output capacitor C30 stabilizes the feedback loop 4 85 D A Converter 16 384 Volt Reference Circuit This regulator circuit is similar the 16 384V reference supply except that the 16 384V reference supply utilizes the regulated 16 384V as one of its dc inputs in a kind of Auto Tracking configuration With this technique any change in the 16 384V output causes equal percentage change in the 16 384V output thereby minimizing inaccuracies in the D A
44. is complemented all ones become zeros ali zeros becomes ones and a binary one is added to the least significant Notice that because of the nature of negative 2 s complementing it is impossible to program for negative zero volts Output The lowest negative number that can be programmed is 0 5mV Hence to obtain an out put of zero volts the sign must be positive 3 15 The voltage magnitude and sign data are stored in the DVS upon the receipt of a gate input from the computer As shown in Figure 3 4 the voltage magnitude and sign data bits must remain for at least 10usec after the triggering edge of the Gate Once the 10 period is expired the voltage program and sign can be changed to prepare for the next gate The gate must reset for at least 2yusec before starting new gate and the time be tween the leading edges of two consecutive gates must be at least 55psec Lose 55 SEC MIN eee DATA TRUE PA AD a SEC MIN DAFA TRUE VOLTAGE SIGN AND CURRENT _ LATCH DATA INPUTS RESET TIME 24 SEC MN Sp SEC MIN le 4 INPUT FLAG OUTPUT E GE E BUSY READY H P504 SEC J Figure 3 4 Timing Diagram No Range Change 3 3 3 16 Notice that in addition to initiating the stor age and processing of voltage and sign data the Gate also stores the voltage range and current latch data which are discussed in s
45. is then processed by separate circuits as will be describ ed in subsequent paragraphs 4 12 Current Latch Processing The three lines of current latch data are decoded and are used to establish a reference current limit which is com pared with a sample of the output current current sampling input from the power amplifier If the current sampling input equals or exceeds the reference current limit a current overload status signal is immediately sent to the computer in forming it that an overload condition exists If the overload condition still exists after a variable delay period the current latch and current latch status output signals are simultaneously ed The current latch delay period is approximate ly 5 to 10 with the terminals open and with added capacitance can be extended to 2 The time delay should be extended for applications involving capacitive loads to prevent surge currents from initiating premature current latch action When the Cr terminals are shorted the current latch circuitry is disabled inhibiting the generation of the current latch and latch status output signals If generated the current latch output signal turns off the power amplifier so that the output current is reduced to a safe value less than 10mA The latch status signal informs the computer of the current latch status of the DVS 4 13 Whenever a current overload or latch condi tion occurs an overload f
46. low proceed to Table 5 5 b Q2 collector still remain high Observe voltage between 21 failure Q1 collector and com Toggle input bit Two logic levels present b High logic level only b Proceed to Step 3 Zero or low logic level only Proceed to Step 4 Observe voltage between a Q2 collector goes low Q1 opened Q2 collector and OUT common Short Q1 col lector to emitter Ql opened and b Q2 collector remains high Zi failure 4 Connect short from 71 21 failure pin to pin2 Observe voltage between QI collector and IN common Toggle input bit Two logic levels present Q1 shorted and Zi failure Zero or low logic level only Table 5 5 Photo Isolator Troubleshooting Output Remains Low NOTE Refer to Figure 5 8 for component reference designations used in this table ACTION RESPONSE PROBABLE CAUSE voltage between Q2 collector and OUT common Short Q2 base to emitter momentarily Observe voltage between Q2 collector and OUT common Short 21 pin 4 to pin 6 momentarily Q2 collector still remains low or zero High logic level only voltage between Q2 collector and OUT common Toggle input bit High logic level only NOTE 5 55 A6 CONTROL BOARD TROUBLESHOOTING 5 56 Since the Board handles many different signals the troubleshooting
47. milli 1073 M mega 106 B micro 1076 met metal obd OD P C pot p p ppm rect Si SPDT SPST Reference Designators Continued vacuum tube neon bulb photocell etc Zener diode socket integrated cir cuit or network Description Abbreviations manufacturer modular or modified mounting nano 1079 normally closed normally open nickel plated ohm order by description outside diameter pico 10712 printed circuit potentiometer peak to peak parts per million peak reverse voltage rectifier root mean square silicon single pole double throw single pole single throw small signal slow blow tantulum titanium volt variable Watt wirewound CODE NO 00629 00656 00853 01121 01255 01281 01295 01686 01930 02107 02114 02606 02660 02735 03508 03797 03877 03888 94009 04072 04213 04404 04713 05277 05347 05820 06001 06004 96486 06540 06555 06666 06751 06776 06812 07137 EBY Sales Co Inc Table 6 3 ADDRESS MANUFACTURER Jamaica N Y Corp New Bedford Mass Sangamo Electric Co 5 Carolina Div Allen Bradley Co Litton Industries Inc Beverly Hills Calif TRW Semiconductors Inc Pickens S C Milwaukee Wis Lawndale Calif Texas Instruments inc Semiconductor Components Div Dallas Texas Manchester Rockford Ill D
48. not neglect the possibility of two or more faults being present CAUTION Trouble isolation by exchanging a known good board for a suspected faulty one allowed only f r the A1 A2 and A3 boards Exchanging a good board for a faulty one in any of the other card slots will often result in causing damage to the good board 5 42 OVERALL TROUBLE ISOLATION PROCEDURE 5 43 Trouble isolation Power Distribution Almost any trouble sympton could be caused by an incorrect power supply or reference volt age thus it s good practice to routinely check all of the most important power suppiy voltages before attempting to isolate a problem to a par ticular circuit The tests described in Table 57 2 Provide relatively fast check for trouble in this area In many cases these checks can save hours that might be spent troubleshooting circuits which are not themselves defective sible by removing the top cover the 7 power amplifier test points are accessible by installing the extender beard AZ combination in the 7 slot The test points are located by referring to the component location diagrams 5 44 Notice that there are four separate power supply common return systems in the DVS desig nated common common 2 common 3 and common 4 When making any voltage waveform measurements be sure to use the ap propriate power supply common reference point The appropriate common point can be determined by refe
49. of 400Hz or less is suitable In the STORAGE mode check waveforms at test points in the following order TP2 3 4 6 7 40 31 41 42 16 43 8 9 and 28 the STORAGE DISABLE mode check voltages at TP9 and TP28 should be gt 2 4 TP28 should be S0 8V referenced to 2 NOTE When tracing signals at each test point make certain to connect oscilloscope to proper common reference point either common or common 4 CAUTION 4 common is 26 volts off ground 2 5 52 if the signal is lost at TP40 one of the delay multivibrators 173 or 174 or its power supply is at fault The 5 and 5 2 supply voltages for A1Z3 and 4174 are derived from the 12V source supply and components on board Al see Figure 7 2 sheet 4 If the gate pulse iso lator or flag isolator is at fault see paragraph 5 53 for isolator troubleshooting instructions 5 53 PHOTO ISOLATOR CIRCUIT TROUBLE SHOOTING 5 54 Once a trouble has been localized to a par ticular photo isolator circuit following the steps of Table 5 4 or 5 5 will troubleshoot its three main semiconductor components without requiring the removal of any parts from the board Although some of the photo isolator circuits in the DVS differ in the means of input drive and some are followed by one or more stages of amplification or inversion all are generally similar to the circuit first make sure that all of the two or three dc supplies to the cir cuit are
50. possible analog output cur rents can be obtained one for each of the eight current latch bit combinations The output current of the current latch decoder appears at a current summing junction collectors of A6Q11 Q12 and Q13 and is determined by the conduction of these transistors resultant current at the junction flows through AGR30 and A6R37 to develop negative and positive reference voltages respectively for the comparators 4 93 Current latch range is determined by the range bit which turns on A6Q1 in the X1 range and turns off A6Q1 in the X10 range With Q1 on X1 range a path is completed for the voltage divider network R8 R13 in its collector circuit Bias voltages which are less positive now permit tran sistors Q8 and 010 to conduct effectively shorting out resistors R16 R17 and R18 respec tively in the base circuits of Q11 Q12 and Q13 This action insures that the conduction of Q11 is decreased by a factor of 10 If transistors 012 and or Q13 are conducting their conduction is likewise 10x less than that of the X10 current latch range 4 94 Transistor 011 is biased in its active region and always conducts one of two fixed amounts of reference current to the summing junction As just described the two fixed currents vary by a factor of 10 and depend on the status of the current latch range bit 4 95 Transistors 012 and Q13 may or may not be conducting depending on the status of the 50mA
51. switches to 4 5Vdc at 550 50mA SION CONCLU If the monitored voltage is positive the negative gross current limiter is lock ed in the limiting state Check 7018 20 If the monitored voltage is excessively negative the positive gross current lim iter is locked in the limiting state Check 7021 23 If the voltage does not switch the negative gross current limiter is not limiting Check A7Q18 20 A UNABLE GET DVS OUT OF CURRENT LATCH CONNECT 2000 LOAD ACROSS DVS OUTPUT TERMINALS 1 OUTPUT OUTPUT CURRENT CURRENT APPROX 0 5A APPROX 0 5 YES CHECK CURRENT LATCH OPERATION SECTION 3 PROGRAM DYS FOR 100 OUTPUT PROGRAM DVS FOR 00 OUTPUT 2 POSITIVE CURRENT OK NO NEGATIVE CURRENT WITH AN OHMMETER CHECK THE FOLLOWING FOR OPEN 1 7013 OR Q3 2 7032 A7Q33 04 OR 06 TURN OFF NEGATIVE VOLTAGE CURRENT NO POSITIVE CURRENT TURN OFF 0 LATCH YES NEGATIVE CURRENT DVS WITH AN OHMMETER CHECK THE FOLLOWING FOR OPEN i ATCRIG 2 ATQIO OR Q2 3 7014 OR 7015 OR Qj 4 A7031 OR Q5 PROGRAM DVS FOR 0 OUTPUT 4 NO POSITIVE CURRENT AND NO NEGATIVE CURRENT WITH AN OHMMETER CHECK THE FOLLOWING ATCRIB OR A CR22 2 CO
52. the overall schematics of Figure 7 2 For the sake of simplicity the bias supplies and regulators are not included on Figure 7 but are discussed in the detailed circuit analysis 4 24 The detailed block diagram discussion de scribes in block diagram terms the operation of each major circuit Details concerning the compo nents inside the many circuit blocks are given in the detailed circuit analysis which also includes information on the internal adjustments and con trols Waveforms and timing diagrams are included throughout to supplement the text For ease of un 4 3 derstanding the waveforms are idealized The waveforms are keyed to various points on Figure 7 1 by means of encircled test point numbers 4 25 VOLTAGE PROCESSING 4 26 The voltage processing circuits consist of an input board logic board and a digital to analog converter board The circuits will be explained functionally based on signai flow from board to board timing diagram for the voltage processing circuits is included on Figure 7 1 4 27 Voltage Magnitude Input Data Incoming voltage magnitude data TP10 is in computer binary form where positive numbers are received from the computerin straight binary and negative bers are received in the negative 2 s complement code Negative 2 s coding consists of complement ing the corresponding positive number changing all logical zeros to ones and all ones to zeros and adding binary 1 to th
53. the storage disable switch in the DISABLE position substitutes a fixed positive volt age for this pulse This permits the bits to pass directly through the storage flip flops The out put of the OR gate either gates or disables the current latch and voltage range storage flip flops the same manner 4 33 As the unit is turned on the initial gate pulse generator produces a storage gate input to the OR gate that assures that the storage flip flops are in the desired initial state 4 34 Storage Having storage capability permits the DVS to provide a continuous output after initial data is no longer present Fifteen latching flip flops are provided for the voltage magnitude bits and one for voltage sign storage storage gate TP9 strobes the flip flops allowing the magni tude and sign inputs to either set or reset them If the data source is either NPN positive logic or positive logic the non inverting outputs of the voltage storage flip flops are connected For negative logic inputs the inverting outputs are connected The proper outputs are selected by locating the storage flip flop packages at appro priate locations on the board Since the data has already been inverted complemented once by the input isolators the outputs of the flip flops are low for the bits of the incoming data from the com puter that are ones The polarity of the sign bit is adapted to the logic of the DVS circuits by means of a jumper at t
54. these input levels 4 90 Storage The current latch and voltage range storage flip flops A622 are identical to those used on board 2 in voltage processing When high storage gate level is present at the clock in puts to the storage flip flops the levels present at the data inputs appear at the Q outputs and the complement of that data at the outputs What ever data is present when the storage gate clock input becomes low is stored in the flip flops and continues to appear until the next high clock input occurs the storage disable mode the clock input remains high and the flip flops pass the data bits directly through to the current latch de coder and range pulse generator without storing them 4 91 Storage Gate The storage gate circuit de velops the signals for the storage flip flops The storage date signal is received from the logic board in the voltage processing circuits and is applied to the base of Q4 through speed up work Cl and R62 04 and R63 comprise a level setting circuit to provide the proper interface with the logic board Note that the emitter of 04 is re turned to 4 26 while the emitters of Q5 and 6 are connected to 2 The storage gate signal is inverted by Q5 and again by Q6 to provide the proper clock level to the storage flip flops 4 92 Qurrent Latch Decoder This circuit con verts the three coded current latch bits to an analog output current Eight
55. 00Vdc 2 RDMISFE391 3C 00853 0140 0200 1 C15 ceramic luF 50Vdc 1 5 50 1 55289 0150 0121 1 C16 fxd tant 4 7 35Vdc 1 150D475X903582 DYS 50289 0180 0100 1 Cl fxd ceramic 47 25vdc SCIiBC 56289 0160 0174 1 2 Diode Si 200mA 75V 17 28480 1901 0050 8 CR5 13 Diode Si 200mA 75V 28480 1 1901 0050 CR14 15 Refer to proper Option Appendix CR16 18 Diode 51 200mA 75V 28480 1901 0050 CR19 Stabistor 51 10 400mW H 28480 1901 0460 1 CR20 Diode 51 200mA 75V 28480 1901 0050 A601 2 3 55 NPN 17 28480 1854 0071 8 QA SS NPN 6 2N3417 03508 1854 0087 5 05 6 NPN 28480 1854 0071 08 13 SS PNP Si 9 28480 1853 0099 8 014 15 SS NPN Si 28480 1854 0071 016 18 58 233417 03508 1854 0087 019 20 35 PNP si 28480 1853 0099 021 22 55 NPN Si 2N3417 03508 1854 0087 Q23 SS PNP Si 25480 1853 0093 024 33 SS NPN Si 28480 1854 0071 Q34 Power NPN Si 1 2 1711 17803 1854 0003 1 81 3 fxd comp 3 9Ka 595 1 4W 3 CB 3925 01121 0683 3925 1 R4 6 fxd comp 39 5 1 4W 3 CB 3935 01121 0683 3935 1 R7 fxd ww 2204 45 2W 1 Type BWH 07716 0811 1763 1 R8 10 fxd comp 5 IKa 596 1 4W 9 CB 5125 01121 0683 5125 1 R1i 13 fxd comp 9 IKa 596 1 4W 3 CB 9125 01121 0583 9125 1 R14 15 fxd comp 20Kn 5 1 AW 12 2035 01121 0583 2035 2 Riob 18 fxd film 19 6 51 1 8W 3 Type CEA T O 07716 0698 3157 R19 var cermet IKa 10 1 62 224 1 73138 2100 2633 12 R20 21 2004 10 2 62 222 1 73138 2
56. 07716 0757 0482 1 R96 fxd met film 1394 41 1 8W 1 CEA T O 07716 0698 4099 i EE R97 fxd met film 11Kn 41 1 8W i Type CEA T O 07716 0757 0443 i R98 fxd met film 1Ma 1 1 4W T O 07716 0757 0344 l R99 fxd met film 390 196 1 8W i Type CEA T O 07716 0698 5093 H R100 Var ww l5Ka 5 1 Model 100 11502 2100 0896 1 102 NOT ASSIGNED E R103 fxd 5 6Kn 45 1 2W 1 EB 5625 01121 0686 5625 1 VR30 f E zener 4 22 400mW 1 28480 1902 3070 1 VR31 Diode zener 12 4V 400mW 1 28480 1902 3185 1 VR40 Diode zener 5 62V 400mW 1 284830 1902 3104 4 Power Supply Board 1 28480 06131 60023 C1 3 NOT ASSIGNED 5 fxd elect 1 450 45Vdc 2 28480 0180 1893 1 C6 7 NOT ASSIGNED 9 fxd elect 200uF 175Vdc 2 28430 0180 1885 1 C10 fxd elect 100 25Vdc 1 30D107G025DD2 56289 0180 0094 1 C11 C22 fxd ceramic 05uF 400V 4 33C 17A CDH 56289 0150 0052 1 C23 fxd elect 100 25Vdc 30D107G025DD2 28480 0180 0094 1 4 Rect Si 1A 400 prv 18 28480 1901 0328 8 CR5 6 7 Rect Si 250mW 200 prv 4 1N485B 03877 1901 0033 4 CR8 21 Rect 8i 1A 400 prv 28480 1901 0328 CR22 Rect Si 250mW 200 prv 1 485 03877 1901 0033 Relay 6Vdc 1 643 6V 09023 0490 0513 Qi 55 PNP Si 1 28489 1853 0099 1 R1 R3 fxd comp 560 259 1 2W 3 5615 01121 0686 5615 1 5 fxd comp 3 3 5 1 2W 3 3 125 01131 0686 3325 1 RS 7 fxd met oxide 33Kn 5 2W 2 Type C428 16299 0764 00
57. 09213 09214 09353 09922 11115 11236 11237 11502 11713 12136 12615 12617 12697 13103 14493 14655 14936 15801 16299 Code List of Manufacturers MANUFACTURER ADDRESS Westinghouse Electric Corp Electronic Tube Div Elmira N Y Fairchild Camera and Instrument Corp Semiconductor Div Mountain View Calif Biricher Corp The Los Angeles Calif Sylvania Electric Prod Inc Sylvania Electronic Systems Western Div Mountain View Calif IRC Div of TRW Inc Burlington Plant Burlington Towa Continental Device Corp Hawthorne Calif Raytheon Components Div Semiconductor Operation Mountain View Calif Breeze Corporations Inc Union N J Reliance Mica Corp Brooklyn Y Sloan Company The Sun Valley Calif Vemaline Products Inc Wyckoff General Elect Co Minia ture Lamp Dept Cleveiand Ohio Nylomatic Corp Norrisville Pa RCH Supply Co Vernon Calif Airco Speer Electronic Components Bradford Pa Hewlett Packard New Tersey Div Rockaway N f General Elect Co Semiconductor Prod Dept Buffalo N Y General Elect Semiconductor Prod Dept Auburn N Y C amp K Components Inc Newton Mass Burndv Corp Norwalk Conn Wagner Electric Corp Tung Sol Div Bloomfield N F CTS of Berne Inc Berne Ind Chicago Telephone of Cal ic So Pasadena Calif IRC Div of TRW Boone Plant Boone General Instrument Corp Rectifier Div Phil
58. 0Ka 41 1 8W 1 CEA 7 0 07716 0757 0472 1 R15 fxd met film 160 219 1 8W i Type CEA T 0 07716 0698 5092 1 R16 fxd ww 2974 1 1 4W 20ppm 1 Type R303B 01686 0811 1929 1 R17 fxd ww 2434 219 1 4W 20ppm 1 Type R303B 01686 0811 2075 1 R18 var ww 5004 Type 100 1 Model 100 11502 2100 0898 i RiS fxd ww 10 20 19 2ppm 1 7007 01686 0811 2577 1 R20B 1 7007 01686 0811 2757 1 R20B fxd ww 15 82Ka 0 1 i Type 7007 01686 0811 2757 i R21 fxd comp 1 8 45 1 2W 1 1825 01121 0686 1825 1 R22 fxd met film 7 5 41 1 8W 1 Type CEA T 0 07716 0757 0440 i R23 fxd met film 12Ka 31 1 8W 2 Type CEA T 0 07716 0698 5088 1 R24 fxd comp 2 2Ka 2595 1 2W 2 EB 2225 01121 0686 2225 1 R25 fxd met film 12Ka 41 1 8W Type CEA T 0 07716 0689 5088 R26 fxd comp 2 259 1 2W i EB 2025 01121 0686 2025 1 R27 fxd met film 6004 419 1 8W 1 7 0 07716 0757 1100 1 R30 fxd met film 2Ka 41 1 8W 1 0 07716 0757 0283 1 R31 fxd comp 51a 45 1 2W 1 EB 5105 01121 0686 5105 1 REF DESIG MFR HP CODE PART NO 1 DESCRIPTION A3R93 1 4 ww 100Ka 19 TC 5 1 7010 01686 0811 1997 1 R94 fxd ww 408 22 1 TC 5 i Type 7007 01686 0811 2762 1 95 fxd met film 562Kn 1 1 8W 1 Type CEA
59. 1 14 Diode 15V 400mW 20 09182 1901 0461 8 CR15 Diode Si 75V 200mA 17 09182 1901 0050 8 CR16 17 Stabistor Si lOprv 3 09182 1901 0460 3 CR18 Diode Si 15V 400mW 09182 1901 0461 CR19 20 Diode Si 75V 200mA 09182 1901 0050 CR21 Stabistor Si 10 09182 1901 0460 CR22 Diode 81 15V 400mW 09182 1901 0461 CR23 Diode Si 75V 200mA 09182 1901 0050 CR24 CR27 Diode 8i 15V 400mW 09182 1901 0461 GR28 CR40 Diode Si 75V 200mA 09182 1901 0050 K Reed Relay and Coil Assembly 1 09182 5080 7127 1 Reed Relay Part of K1 1 DRS 2 12617 0490 0727 1 Coil Part of K1 1 SF12P 71707 0490 0728 1 K2 Reed Relay 1 09182 0490 0399 1 Q1 Diff Amp NPN 1 09182 1854 0221 1 Q2 Diff Amp NPN 1 09182 1854 0229 1 Q3 4 SS NPN Si 7 2N3417 03508 1854 0087 7 Q5 58 PNP Si 1 09182 1853 0010 1 Q6 SS PNP Si 1 09182 1853 0038 1 07 SS NPN Si 1 09182 1854 0232 1 55 2 09182 1854 0071 2 09 SS PNP Si 5 09182 1853 0099 5 Q10 11 SS NPN Si 6 09182 1854 0271 6 912 13 SS PNP 31 6 09182 1853 0037 6 014 15 SS NPN Si 09182 1854 0271 O16 17 SS PNP Si 09182 1853 0037 018 19 58 253417 03508 1854 0087 020 022 SS 51 09182 1853 0099 023 24 25 SS NPN Si 2N3417 03508 1854 0087 DESCRIPTION PART NO CODE PART 6 13 7026 SS PNP Si 1 02735 1853 0041 1 027 58
60. 1 4W CB 3625 01121 0683 3625 1 888 fxd comp 9 1 59 1 4W CB 9125 01121 0683 9125 1 889 90 fxd comp 6 2 5 1 4W CB 6225 01121 0683 6225 R31 fxd comp 100Ka 45 1 4W CB 1045 01121 0683 1045 R92 fxd comp 12Ka 45 1 4W 1235 01121 0683 1235 1 R93 94 95 fxd comp 20 45 1 4W CB 2035 01121 0683 2035 R96 fxd comp 1 259 1 2W EB 1325 01121 0686 1325 R97 fxd comp 51Ka 45 1 4W CB 5135 01121 0683 5135 1 R98 fxd comp 7504 259 1 4W CB 7515 01121 0683 7515 R99 fxd comp 824 259 1 4W CB 8205 01121 0683 8205 R100 101 fxd comp 10Kn 45 1 4W CB 1035 01121 0683 1035 R102 fxd ww 3904 5 242E 56289 0811 1799 1 R103 fxd comp 10 259 1 4W 1035 01121 0683 1035 R105 fxd comp 10 5 1 4W CB 1065 01121 0683 1065 1 106 fxd film 10 1 1 8W Type CEA T O 07716 0757 0442 R107 fxd comp 5 6Meg 5 1 4W H CB 5655 01121 0683 5655 1 R108 var cermet 20 10 1 62 228 1 73138 2100 2514 1 109 fxd ww 75a 595 SW 1 243E 56289 0812 0097 1 Diode zener 4 99V 400mW 1 28480 1902 3032 1 VR2 Diode zener 12 4V 400mW 1 28480 1902 3185 1 VR4 6 Diode zener 4 22V 400mW 3 28480 1902 3070 3 Z1 Hybrid Resistive Network IC 1 28480 1810 0041 1 22 Quad 4 Bit Bistable Latch 1 SN7475 01295 1820 0876 1 23 Operational Amplifier IC 1 818641 27014 1820 0223 1 24 Dual Operational Amp 1 28480 1820 0092 1 DESCRIPTION REF MFR HP DESIG PART E PO
61. 100 2413 1 R22 24 fxd film 3 57 19 1 8W 3 Type CEA T O 07716 0698 3496 1 25 26 fxd comp 200a 596 1 4W 2 CB 2015 01121 0683 2015 1 R27 fxd 6Kn 1 1 8W 1 Type CEA T O 07716 0698 3476 1 28 fxd film 2 37 195 1 8W 1 07716 0698 3150 1 R29 fxd film 4K 51 1 8W H Type CEA T O 07716 0698 5808 1 R30 fxd film 1214 41 1 8W 2 Type CEA T O 07716 0757 0069 1 R31 32 fxd fitm 432 196 1 8W 2 07716 0757 0480 1 R33 34 fxd film IKa 1 1 8W 4 Type CEA T O 07716 0757 0280 i R35 36 fxd film 10Ka 41 1 8W 3 Type CEA T O 07716 0757 0442 1 R37 fxd film 121a 175 1 8W CEA T O 07716 0757 0068 R38 fxd film 7504 45 1 4W 2 CB 7515 01121 0683 7515 1 R39 fxd film IKa 219 1 8W Type CEA T O 07716 0757 0280 R40 fxd comp 2 4Kn 5 1 4w 1 CB 2425 01121 0683 2425 i RAI fxd comp 5 IKa 255 1 4W CB 5125 01121 0683 5125 R42 fxd film 8 2 22 1 8W 2 Type CEA 07716 0757 0946 1 MFR DESIG TO MFR PART CODE PART No Rs DESCRIPTION A6R43 fxd film 1 1 1 8W Type CEA 07716 0757 0280 R44 fxd film 1824 215 1 8W Type CEA T O 07716 0757 0406 1 RAS fxd film 8 2 2 1 8W Type CEA T O 07716 0757 0946 R46 fxd film 11 41 1 8W Type CEA T O 07716 0757 0443 1 R47 fxd film 1 3Ka 1 1 4W i Type CEB T O 07716 0757 0735 1 R48 fxd film 1 21 41 1 4W Type CEB T O 07716 0757 0734 1
62. 2 4586 97 56289 0160 2149 Foot Assembly 5 28480 5060 0767 Stand Tilt 1 28480 1490 0030 Fastener 4 C17859632 24D 89032 0590 0053 Fastener 9 C8022632 24B 89032 0590 0710 Mounting Kit Includes Rack Ears Trim and Screws 1 28480 1 5060 8740 Packing Carton 1 28480 3211 1180 Floater Pad Packing Carton 2 28480 9220 1400 Extender Assembly Plug In Board Printed Circuit Board Printed Circuit Board Connector Epoxy Plate 28480 28480 71785 28480 5060 7948 5020 8049 j 1251 0495 5020 5728 251 20 30 390
63. 327 Board Edge Connectors 252 22 30 340 1251 1887 Inductor 1 9100 2198 fxd ww 2 72 5 2W Type BWH 0811 1671 fxd ww 1 252 41 AW 8 2 18 0811 2556 fxd comp 100 5 1 2W fxd comp 4 7 5 1 2W fxd ww 2 74 55 2W fxd film 4Ka 1 1 8W fxd film IKa 41 1 8W fxd ww 10 0 1 1 4W 1015 0686 1015 0001 0698 0001 0811 1671 CEA 0 0698 5808 Type CEA T 0 0757 0280 Type E30 0811 1994 A6 Control Board Refer to proper Option Appendix A6A1l Input Isolator Circuit CR1 2 Diode Si 200mA 75V 2 28480 1901 0050 2 Q1 2 SS NFN Si 2 28480 1854 0071 2 BLISS Refer to proper Option Appendix fxd comp 750 5 1 2W i EB 7515 01121 0686 7515 i R5 fxd comp 82a 45 1 4W 1 8205 01121 0683 8205 1 R6 fxd 7504 596 1 4 H CB 7515 01121 0683 7515 1 21 Photo Isolator 1 28490 1990 0407 through 6 4 Same ASAS Latch Status Isolator and Amplifier CR1 2 Diode Si 75 2 28480 1901 0050 2 01 4 SS NPN Si 4 28480 1854 0071 4 R1 comp 106 259 1 4W 1 CB 1035 01121 0683 1035 i R2 fxd comp 1 3 59 1 2W 1 EB 1325 01121 0686 1325 1 R3 comp 750 5 1 2W 1 7515 01121 0682 7515 fxd comp 8254 4595 1 4W 1 CB 8205 01121 0683 8205 H R5 fxd comp 12Ka 596 1 4W H CB 1235 01121 0683 1235 1 R6 fxd comp 1005 5 1 4W 1 CB 1015 01121 0683 1015 1 R7 ixd comp 5 6 45 1 2W i
64. 4 03182 06131 60022 6 12 7 Amplifier Plug In Board C1 fxd mica 330pF 500Vdc 2 RCM15E331J 84171 0140 0168 1 2 3 fxd mylar 0 224F 80Vdc 2 192P2249R8 56289 0160 2453 1 C4 fxd elect luP 35Vdc 1 1150D105X9035A2 56289 0180 0291 1 C5 6 fxd mylar 0 0022 200V 4 192P22292 56289 0160 0154 1 C7 8 fxd elect 0 47uF 35Vdc 3 150D474X9035A2 56289 0180 0376 1 C9 fxd mylar 0 0022pF 200V 192 22292 56289 0160 0154 C10 fxd mylar 0 00474F 200Vdc 3 192 47292 56289 0160 0157 1 C11 fxd mylar 0 0022 F 200V 192P22292 56289 0180 0154 C12 fxd mylar 0 00474F 200Vdc 192P47292 56289 0160 0157 213 fxd ceramic 0 001 500Vdc 3 40C88A1 56289 0160 3398 1 14 NOT ASSIGNED C15 fxd mylar 0 01 200Vdc 1 192P10392 56289 0160 0161 1 C16 fxd mylar 0 022yuF 200Vdc 2 192P22392 56289 0160 0162 1 17 fxd mica 330pF 500Vdc RCMI15E331 84171 0140 0168 C18 fxd elect 0 474F 35Vdc 150D474X9035A2 56289 0180 0376 C19 fxd ceramic 0 001pF 500Vdc 40C88A1 56289 0160 3398 C20 fxd ceramic 100pF 1 1 DD 101 71590 0160 2061 1 224 fxd ceramic 0 001 500Vdc 40C88A1 56289 0160 3398 C22 fxd mylar 0 0033 4F 200V 1 09182 0160 0155 1 C23 fxd mylar 0 022pF 200Vdc 192P22392 56289 0160 0162 24 25 fxd ceramic 0 47 25Vdc 2 5C11B7 56289 0160 0174 C26 fxd elect 5uF 150Vdc 1 40D505P150DC4 56289 0180 1841 1 27 fxd mylar 0 00474F 200Vdc 192 47292 56289 0160 0157 C28 fxd mylar 0 01uF 400Vdc 1 663UW 84411 0160 0381 1
65. 4 71 Gate Input and Timing In instruments equipped with one of the standard options the gate input from the computer is a negative going transition biased attenuator network R1 R2 and R3 identical to those of the voltage and sign bit inputs adapts the gate input to the interface requirements of the driver circuit In verter 02 provides the positive going transition needed at the input TP3 of one shot multivi brator Z3 which has a Schmitt trigger input sen Sitive to positive levels For special modifications an additional inverting stage that is normally jumpered out may be added ahead of Q2 to accom modate a positive going input gate The 3 micro second duration of the negative pulse at the output of Z3 TP4 is determined by the values of R7 and C5 The trailing edge of the negative 3 micro second pulse triggers another one shot multivi brator identical to the first except that its timing components R8 and C6 cause it to produce an output pulse 50 microseconds long Multivibrator Z4 produces a negative 50 microsecond pulse at its output TP6 and a positive 50 microsecond pulses at its Q output 40 Both of these pulses start 3 microseconds after the start of the incom ing gate The negative output TP6 drives the light emitting diode of the gate pulse isolator circuit This isolator circuit similar to those used for the voltage magnitude inputs lines pro duces a negative output pulse TP7 Thi
66. 4 W EB 4325 01121 0686 4325 R80 fxd comp 7504 59 3 W EB 7515 01121 0686 7515 R81 fxd comp 7 5 5 3 W 7525 01121 0686 7525 R82 fxd comp 5604 259 W 5615 01121 0686 5615 R83 fxd film 6 2K 1 1 8W CEA 0 07716 0698 5087 R84 fxd film 4 53 31 1 8W Type CEA T 0 07716 0698 4443 R85 var ww 2004 10 Type 500 11502 2100 1771 R86 fxd ww 89 9 40 136 2ppm 1367 01686 0811 2900 R87 fxd ww 10 0 19 5ppm E30 01686 0811 1994 R88 fxd comp 8 2Ka 45 3 W EB 8225 01121 0686 8225 R89 fxd comp 1 3 2595 W EB 1325 01121 0686 1325 R90 fxd comp 5 25 5 W EB 5125 01121 0686 5125 R91 fxd comp 2Kn 5 GB 2025 01121 0689 2025 R92 93 NOT ASSIGNED R94 fxd comp 8204 5 2 8215 01121 0686 8215 R95 NOT ASSIGNED R96 fxd comp 2004 5 W EB 2015 01121 0686 2015 R97 fxd comp 394 5 2 W EB 3905 01121 0686 3905 R98 fxd comp IKa 5 amp EB 1025 01121 0686 1025 R99 fxd comp 360a 5 5 W 3615 01121 0686 3615 R100 fxd comp 7504 55 3 W EB 7515 01121 0686 7515 101 fxd comp 82a 5 3 W EB 8205 01121 0686 8205 R102 fxd 470a 5 iw EB 4715 01121 0686 4715 R103 fxd comp 1805 5 W EB 1815 01121 0686 1815 R104 fxd comp 2004 5 W EB 2015 01121 0686 2015 R105 fxd comp 27a 5 5 2705 01121 0686 2705 R106 fxd comp 82Ka 5 W 8235 01121 0686 8235 R107 fxd comp 68 t5 GB 6835 01121 0689 6835 R108 fxd
67. 46 1 8 9 fxd comp 51Ka 5 2 5135 01121 0589 5135 1 10 fxd comp 3Ka 65 1 2W i EB 3025 01121 0685 3025 1 RII fxd 3 6Ka 55 1 2W 1 3625 01121 0686 3625 1 812 fxd comp 9 IKa 45 1 2W i EB 9125 01121 0686 9125 1 R13 fxd comp 33Ka 5 1 2W EB 3325 01121 0686 3325 R14 ww 5 45 1 100 4 11236 2100 0741 1 R15 fxd film 6 2 41 1 8W 1 CEA 0 07716 0698 5087 1 R186 fxd film 6Ka 1 1 8W 1 0 07716 0698 3475 1 R17 ixd film 20 0Ka 51 1 8W 1 0 7716 0757 0449 1 R18 fxd film 118Ka 1 1 8W 1 Type CEA 0 07716 0698 3265 i R19 fxd film 1 31 1 8W i Type CEA T 0 07716 0757 0280 1 R20 fxd film 1974 1 1 4 i Type 303 01586 0811 1925 1 821 fxd film 10 196 1 8W i Type CEA T 0 07718 0757 0346 1 R22 fxd film 42 24 41 1 8W 2 Type CEA 7 0 07716 0757 0316 1 R23 Thermistor 644 10 1 181671 02606 0837 0023 1 R24 var ww lOa 5 i Type CT 100 4 06486 2100 1767 1 4825 fxd film 42 25 1 1 8W Type CEA T 0 07716 0757 0316 R26 fxd comp 2004 5 1 2W 1 2015 01121 0686 2015 827 fxd comp 2 5 1 2W 1 2025 01121 0686 2025 1 TA NOT ASSIGNED T2 Bias Transformer 1 28480 5080 1773 5 Interconnect Board 1 06131 60024 Cl fxd film 0 01 200Vdc 1 192 10392 0160 0161 1 2 fxd tant 4 7 35Vdc 1 1150D475X9035B2 DyYS 0180 0100 1 fxd ceramic 0 1 50Vdc 5050B1 CML 5 0150 0121 Rect Si 200 prv 1901 0
68. 5 71 OUTPUT VOLTAGE ADJUSTMENT 5 72 Before proceeding to the following adjustment procedures make the following preparations 1 Strap the following terminals on the rear terminal strip of the DVS a A7Q6 opened A7Q5 shorted b Remove 05 short and pro ceed to Step 2 a A704 shorted A7Q3 opened or A7Q2A shorted b Remove 02 shorts and proceed to Step 3 a A7Q2B opened or A7Q1B shorted Remove shorts Check for defects to LO 5 to GND Hi to 8 2 Connect the Pocket Programmer to the data input connector and set its switches as fol lows Set the INPUT LEVEL REF switch to DATA COM Set Set the MP DCPS switch to DCPS the SOURCE SELECT switch to EXT oet set for for the RANGE switch to X1 the data and sign bit switches an output of 0 5mV Refer to the appropriate Option Appendix the correct data and sign bit coding f Set the I LIMIT switches for a 500mA limit 9 Setthe switch on the A2 board to the STORAGE DISABLE position 4 Connect a digital voltmeter across the S and LO 5 output terminals 5 Turn on DVS and momentarily depress GATE switch on Pocket Programmer to deactivate the current latch circuit 6 With the DVS programmed for an output of 0 5mV test the voltage processing circuits by individually turning on each bit and observing the relative change in output voltage associated with each bit value If a
69. 719 8120 0050 0400 0013 2190 0491 0340 0166 REF DESIG DESCRIPTION MFR PART NO CODE PARTNO RS Bushing Transistor Screws 01 06 12 0340 0168 Insulator Mica 01 06 6 0340 0174 Hinge Plastic 2 5040 1449 Bracket Hinge 2 5000 6208 Fuse Holder 1 1400 0084 Hex Nut Fuse Holder i 2950 0038 Lockwasher Fuse Holder 1 2190 0037 Neoprene Washer Fuse Holder 1 1400 0090 Rear Chassis 1 5000 6206 Spacer Rear Chassis Hex 8 32 x 7 8 long 4 0380 0392 Cover Bottom 1 5000 9805 Cover Top 1 5000 9806 Side Frame 2 5060 0731 Side Cover Front 2 5000 8703 Side Cover Rear 2 5000 8701 Side Trim Fluted Adhesive Back Handle Assembiy Side Retainer Side Handle Sheet Metal 5000 0051 9060 0222 5060 0766 Chassis Power Supply U Shape Aluminum Sheet Metal 5000 6205 Chassis Plug in Card Aluminum Sheet Metal 5000 6204 Guide Rail Plug In Card Plastic Right Guide Rail Plug In Card Plastic Left Shoulder Washer Plug In Chassis Spacer P C Guide 3 8 O D 10 C L 5040 1419 5040 1420 2190 0492 9319 A 194 0380 0471 Clamp Tube C1 C2 5000 6276 MISCELLANEOUS Clamp 1 4 Dia 3 T4 4 79307 11400 0330 Clamp 2 Dia C3 1 4586 28 56289 0180 0078 Clamp 1 3 8 Dia C6 C7
70. 8480 28480 01121 01121 01121 01121 01121 EB 3325 EB 1035 EB 2225 EB 1035 EB 3335 28480 5060 6192 0160 3398 0160 2639 1901 0050 1854 0087 1853 0078 1854 0317 0686 3325 0686 1235 0686 2225 0686 1035 0160 3398 0160 2639 1901 0050 1854 0087 1853 0078 1854 0317 0686 3325 0686 1035 0686 2225 0686 1035 0686 3335 5080 7139 TO MFR PART NO CODE PART NO RS 2140 0324 b 4 font de eM des des CAD feed gt 4 DESIG MFR HP TQ MFR PART NO CODE PART NO RS DESCRIPTION R34B 1 7007 01686 0811 1167 1 R34B fxd ww 19404 0 1 1 7007 01686 0811 1167 1 R36 var ww 1004 596 9 Model 100 11502 2100 1450 2 R40 fxd comp 1 2 45 1 2W 1 1225 01121 0686 1225 1 u R50 fxd met film 1964 51 1 8W 1 Type CEA T O 07716 0698 3440 1 dt R51 fxd 184 55 1 2W 1 EB 1805 01121 0686 1805 1 R52 59 vat ww 1004 5 Model 100 11502 2100 1450 R60 fxd ww 19 96 2 15 TC 2 i Type 7007 01686 0811 2574 1 R61 67 fxd ww 19 96 1 TC 5 7 Type 7007 01686 0811 2575 2 868 76 fxd ww 10K 1 TC 5ppm 9 0 01686 0811 1994 2 77 78 fxd met film 10 2195 1
71. 8W 2 Type CEA T O 07716 0757 0442 1 R79 JUMPER e R80 86 fxd ww 20Kn 1 TC 7 Type 7007 01686 0811 2609 2 R87 89 91 fxd met film 20Kn 41 1 8W 4 Type CEA T O 07716 0757 0449 1 R92 fxd ww 150 196 TC x 5ppm 1 7007 01686 0811 2763 1 R20 R34A fxd ww 16 0 1 Matched to ww 23504 0 1 Match to 5 fxd mica 330pF 500Vdc 1 RCM15331 00853 0140 0168 1 C11 fxd ceramic 001uF 500Vdc 1 28480 0160 3398 1 12 fxd mylar 01 200V 1 192 10392 56289 0160 0161 1 613 30 fxd elect 221 35V 2 150D226X0035R2 56289 0180 0160 1 C40 41 fxd elect luf 35Vdc 2 1500105 9035 2 56289 0180 0291 i CR10 14 Diode Si 200mA 75V 5 28480 1901 0050 5 Li Ferrite Bead 1 28480 9170 0847 1 010 55 51 3 28480 1853 0099 3 011 Dual NPN Si i 28480 1854 0221 1 012 SS NPN Si 2 28480 1854 0071 2 013 55 NPN Si 1 28480 1854 0087 1 Q14 55 NPN Si i 28480 5080 7132 1 015 30 55 51 28480 1853 0099 931 SS NPN Si 2 28480 1854 0244 2 032 SS NPN Si 28480 1854 0071 040 SS NPN Si 28480 1854 0244 R10 fxd comp 43 45 1 2W 1 EB 4335 01121 0686 4335 1 R11 fxd comp 3Ka 595 1 2W 1 EB 3025 01121 0686 3025 1 R12 fxd met film IKa 219 1 4 i Type CCA T 0 07716 0757 0338 1 R13 fxd comp 2 4Ka 595 1 2W 1 2425 01121 0686 2425 1 RiA fxd met film 20
72. A6R21 ccw until the voltmeter indicates approximately 0 7V Program the voltage to 14 00V the current latch to 70mA k Adjust AGR20 until the voltmeter in dicates approximately 0 7V 1 Program the voltage to 4 00 and the current latch to 20m Adjust A6R108 until voltmeter indicates approximately 0 7V SECTION REPLACEABLE PARTS 6 1 INTRODUCTION 6 2 This section contains information for ordering replacement parts Table 6 4 lists parts in alpha numeric order by reference designators and provides the following information a Reference Designators Refer to Table 6 1 b Description Refer to Table 6 2 for ab breviations Total Quantity Given only the first time the part number is listed except in instruments containing many sub modular assemblies in which case the TQ appears the first time the part number is listed in each assembly d Manufacturer s Part Number or Manufacturer s Federal Supply Code Num ber Refer to Table 6 3 for manufacturer s name and address f Hewlett Packard Part Number 9 Recommended Spare Parts Quantity RS for complete maintenance of one instrument during one year of isolated service h Parts not identified by a reference desig nator are listed at the end of Table 6 4 under Me chanical and or Miscellaneous The former consists of parts belonging to and grouped by individual as semblies the latter consists of parts
73. ABLE If two logic levels are present these circuits are working on static level otherwise check the Interconnect Board A5 and Logic Board A2 and A6Q4 Q5 O6 as follows With A281 in the STORAGE position apply a pulse train to the GATE input terminal J1 pin 32 Check for the pre sence of a pulse by connecting an oscilloscope or logic probe to 2 common end TP s 28 69 70 and 30 in order Note that TP28 is approximate 26 volts with respect to 2 2 is connected to the Low Sense terminal on the rear barrier block Low Sense is typically connected to chassis ground If a point is reached at which the pulse is not present it may be assumed that the transistor or related components just before this point is de fective If the gate pulse is traced through to TP30 it is likely that A6Z2 is defective and must be replaced Before replacing A6Z2 ensure that 4 99V supply voltage is present at A622 pin 5 If not check the 4 99V supply components see Figure 7 2 sheet 4 5 60 Voltage Range Troubleshooting trouble shoot the voltage range circuits the following pro cedure is recommended 1 Connect the common lead of oscilloscope or logic probe to 22 common 2 Connect the other lead of TP65 and check by toggling the appropriate switch for the presence of two logic levels If only one logic level is pre sent check the interconnect board for continuity and ensure that the programming device is connect
74. CIRCUITS KEEP SAME TEST SET UP AND SEE 8 BELOW TROUBLE IN THE 26 SUPPLY SEE TABLE 5 2 B LOCALIZE FAULT IN CURRENT LATCH CIRCUITS CONNECT VOLT METER BEWEEN 8 AND 79 METER YES METER READINGS READS TURN OFF CORRECT BETWEEN 0 9 3 DYS 79 AND 80 METER READS 410 4V YES 3 TROUBLE 15 IN CURRENT veg LATCH SWITCH CIRCUIT P TRANSISTOR SWITCHES 4798 09 AND ASSOCIATED COMPONENTS TOGGLE GATE SWITCH 3 CONNECT VOLT METER BETWEEN 1279 AND TURN ON DVS REPEAT STEPS 2 AND 3 T 5 TROUBLE ISIN CURRENT LATCH ISOLATOR CIRCUIT CHECK 7024 AND 7025 STAGES Figure 5 9 A7 Power Amplifier Current Latch Troubleshooting 5 27 5 9B provides a procedure for localizing the fault to either the current latch isolator or the current latch switch stages If the procedure of Figure 5 9 indicates that the fault is in the power cir cuits the procedure given in Figure 5 10 can used to localize the fault to the defective stage within the power circuits 5 68 Output Voltage Troubleshooting The power amplifier contains four functional circuits current latch gross current limit feedback differential amplifier and power amplifier any one of which Can cause a failure in output voltage the failure being that output voltage is locked up or down full positi
75. Coupling Amplifier Inverter Q6 serves as a level changing transistor coupling the rela tively small negative output level of Q5 to the 155 volt level used in the power amplifier The gain of the coupling amplifier is small only slightly great than If the gross current limit is exceeded the coupling amplifier receives a turn down signal from Q23 if positive output voltage gross current limit is exceeded 020 if negative output volt age gross current limit is exceeded The opera tion of the positive and negative gross current limit circuits is described in subsequent paragraphs 4 121 Power Amplifier The power amplifier con sists of three push pull stages which are of com plementary symmetry design The input stage 010 and Q12 is driven by a single ended stage Q7 For positive output currents the positive section of the amplifier transistors 010 011 Q1 02 O5 Q30 Q31 014 and 015 is conducting while the negative section transistors Q12 Q13 Q3 Q4 Q6 032 033 O16 and 017 is cutoff The re verse true for negative output currents At zero output current both halves of the power amplifier are conducting slightly with diodes CR17 and CR22 providing the voltage drop to forward bias Q10 and Q12 simultaneously This eliminates dead spots when the unit is program med away from zero 4 122 Transistor O7 is a voltage amplifier having a gain of approximately 40 w
76. F4C TD 30983 0757 0949 Type CEA T 0 07716 0757 0440 CB 1025 01121 0683 1025 242E 56289 0813 0050 CB 3025 01121 0683 3025 9115 01121 0686 9115 7515 01121 0586 7515 7515 01121 0683 7515 Refer to proper Option Appendix CB 8205 01121 0683 8205 Hefer to proper Option Appendix 1025 01121 0683 1025 CB 7515 01121 0583 7515 CB 8205 01121 0683 8205 CB 1035 01121 0683 1035 28480 1902 3070 5211213 54 04713 1902 0533 25480 1902 3070 Refer to proper Option Appendix 28480 1990 0407 SN13617 01295 1820 0261 Refer to proper Option Appendix 28480 0160 0174 72136 0140 0196 28480 0160 0174 150D475X5006A2 DYS 56289 0180 1954 RDM15F151 3C A2DS1 Q1 3 R1 R2 R3 R4 R5 R6 R7 R8 R9 10 81 71 4 25 26 27 8 79 12 1 2 1 2 CR1 3 Q1 Q2 Q3 R1 R2 R3 R4 5 through 15 16 1 C 1 3 Q1 Q2 Q3 A3A16R1 R2 R3 R4 5 R6 21 AR Ri AR R2 AR R3 AR R4 Lamp 6Vdc incandescent SS NPN Si fxd comp lKa 5 1 4W fxd comp 4 7Ka 5 1 4 fxd comp IKa 596 1 4W fxd comp 2004 259 1 4W fxd film 30 IKa 41 1 8W fxd comp 5 IKa 596 1 4W fxd comp 5104 5 1 4W fxd comp 2Ka 2590 1 4W fxd comp lKa 595 1 4W Switch slide DPDT DESIG DESCRIPTION 4 2 Input NAND Gate IC Monostable Multivibrator IC Hybrid Res
77. GE DISABLE only if Pocket Programmer is used PROCEDURE a Connect 2004 50W load between HI and LO Programming Time Test Setup output terminals on rear of DVS Connect 14533B Pocket Programmer Turn unit ON and GATE DVS b Connect 3310 A B output after adjusting to proper levels to 14533B Example Program ali but the 8192 Bit to the down shorted to Data posi tion Program the sign bit to the up not shorted to Data com position Con nect the 3310 A B output to the sign bit and DATA com to the 3310 A B ground The output will now program between 8 1925 volts and 8 192 volts fora AVour 16 3845 volts In this example 0 1 of 16 3845mV The output voltage should read within 16mV of final value within 300usec Obtain a stable display on oscilloscope While adjusting DELAY DIV control on 18214 took for the bright spot on the CRT trace The beginning of the bright spot indicates where the 3490A will be triggered d To calibrate system delay adiust bright Spot on CRT display using DELAY control to the position where 3490A indicates approximately zero volts The time between the actual zero crossing of the DVS output channel A and the start of the bright spot indicates system delay Tg e Measure the voltage just prior to the wave form transitions see Figure 5 3 Voltage reading should be within 0 1 of AVOUT CHANNEL MEASURE OUTPUT DVS DVM READS ZERO HERE
78. MBINATION OF OPEN TRANSISTORS IN THE POSITIVE AND NEGATIVE VOLTAGE CIRCUITS FOR INSTANCE CHECK THE FOLLOWING TURN OFF DVS B UNABLE TO PROGRAM DVS CURRENT LATCH i CANNOT PROGRAM POSITIVE VOLTAGE CURRENT LATCH BUT NEGATIVE VOLTAGE CURRENT LATCH PAIRS PROGRAMMING Git AND TROUBLE POSITIVE VOLTAGE 7012 013 CIRCUITS TURN DYS 8 7014 015 0 2 CHECK 70 OR Q2 7016 017 3 CHECK ACRI FOR SHORT C A7Q30 031 AND 7032 033 POSITIVE VOLTAGE CURRENT LATCH PROGRAMMING D 02 AND Q3 BUT CANNOT PROGRAM NEGATIVE VOLTAGE E Ql AND Q4 CURRENT LATCH 1 TROUBLE IN NEGATIVE VOLTAGE CIRCUIT TURN OFF DYS 2 CHECK 7012 OR Q3 3 CHECK ATCRIB 21 70820 Q5 AND Q6 Figure 5 10 Localize Current Latch Trouble 5 29 Table 5 13 Gross Current Limiters Troubleshooting Continued ACTION RESPONSE CONCLUSION Repeat Step 3 expect monitor Monitored voltage If the voltage does not switch the voltage at the cathode of switches to 20V the positive gross current limi CR23 and increase negative approximately at ter is not limiting Check output voltade to draw 550mA 550 50mA A7021 23 Table 5 14 Feedback Differential Amplifier Troubleshooting Unit Locked Down Full Negative SOLEAT RESCUE CONCLUSION Short t A7QS emitter to collector Output voltage a A7Q6 shorted
79. Metallurgical Corp No Chicago Ill Union Carbide Corp Electronics Div Mountain View Calif UID Electronics Corp Hollywood Fla Pamotor Inc Pampa Texas General Electric Schenectady N Y General Electric Lamp Div of Con sumer Prod Group Nela Park Cleveland Ohio General Radio Co West Concord Mass LTV Electrosystems Inc ponents Operations Huntington Ind Dynacool Mfg Inc Saugerties N Y National Semiconductor Corp Santa Clara Calif Palo Alto Calif Kenilworth N J Hewlett Packard Co Heyman Mfg Ca IMC Magnetics Corp New Hampshire Div Rochester SAE Advance Packaging Inc Santa Ana Calif Ramona Calif Owensboro Ky Chicago 11 Budwig Mfg G E Co Tube Dept Lectrohm Inc Mallory Co Inc Indianapolis Ind Muter Co Chicago New Departure Hyatt Bearings Div Sandusky Ohio Skokie General Motors Corp Ohmite Manufacturing Co Penn Engr Corp Doylestown Pa Polaroid Corp Cambridge Mass Raytheon Co Lexington Mass Simpson Electric Div of American Gage and Machine Chicago Sprague Electric Co North Adams Mass Superior Electric Co Bristol Conn Svniron Div of FMC Corp Homer City Pa Philadelphia Pa New York N Y Thomas and Betts Union Carbide Corp Ward Leonard Electric Co Mt Vernon N Y MANUFACTURER ADDRESS 70563 Am
80. NPN 09182 1854 0071 028 SS NPN Si 1 09182 1854 0244 029 SS Si 09182 1853 0099 Q30 31 SS NPN Si 09182 1854 0271 Q32 33 SS PNP Si 09182 1853 0037 R1 fxd film 1Ma 1 iw 1 Type CEB T 0 07716 0757 0344 1 R2 fxd film 45 1 1 8W 1 Type CEA T 0 07716 0698 5091 1 R3 fxd film 6194 1 W 1 Type CEB T 0 07716 0757 0728 1 4 5 fxd film 200 1 1 8W 2 CEA 7 0 07716 0757 0472 1 R6 fxd comp lKa 5 Ww 4 EB 1025 01121 0686 1025 1 R7 fxd film 4 75Ka 1 1 8W 1 Type CEA T 0 07716 0757 0437 1 R8 fxd film 118Ka 1 1 8W 1 Type CEA T 0 07716 0698 3265 1 R9 var ww 100 596 1 100 11502 2100 1450 1 R10 11 fxd film 21 5n 1 1 8W 2 CEA 0 07716 0698 3430 1 R12 13 fxd film 43Ka 1 1 8W 2 Type CEA 1 0 07716 0698 5090 1 R14 15 fxd film 12Ka 51 1 8W 3 Type CEA T 0 07716 0698 5088 1 R16 fxd comp lKa 596 4 W EB 1025 01121 0686 1025 R17 18 fxd film 5102 1 2 Type CEB T 0 07716 0698 5145 1 R19 fxd comp 1004 45 5 W 2 EB 1015 01121 0686 1015 1 R20 fxd film 12Ka 51 1 8W Type CEA T 0 07716 0698 5088 R21 fxd comp 1 3Ka 5 2 EB 1325 01121 0686 1325 1 R22 23 fxd comp 51a 5 W 2 EB 5105 01121 0686 5105 1 R24 fxd comp 5 6Ka 5 1 EB 5625 01121 0686 5625 1 R25 fxd comp 5604 55 3 EB 5615 01121 0686 5615 1 R26 fxd comp 510a 1596 2 EB 5115 01121 0686 5115 1 R27 fxd comp 3Ka 5 4 W 1
81. O output terminals b On the Programmer set the data bit OUTPUT SIGN and RANGE switches for an output voltage of 100V Turn on DVS and press GATE switch on Programmer d Set the DVS front panel CURRENT switch 5 33 to 0 6 and adjust A4R24 until ammeter reads 0 5A e Setthe data bit OUTPUT SIGN and RANGE switches for an output voltage of 100V The meter should read 0 5 f Ifit does not halve the error and adjust A4R24 accordingly 5 79 CURRENT LATCH ADJUSTM ENT 5 80 To calibrate the accuracy of the current latch circuit proceed as follows Remove the 6 control board and using the extender board place A6 in the extended posi tion Short the terminals rear barrier strip b a voltmeter across A646Q3 Fi gure 7 2 Sheet 2 Connect meter positive to collector and common to emitter of A6A6Q3 When current latch occurs the voltmeter will read approximately 0 7 volts Attach 200 ohm 50 watt 1 load resistor across the HI and LO output terminals d Setthe switches on the Pocket Program mer for an output voltage of 4 00V and a current latch of 20mA e Adjust potentiometers A6R19 R20 R21 and R108 fully clockwise Turn on DVS and press GATE switch on Pocket Programmer Allow a 30 minute DVS warm up period 0 Adjust A6R19 ccw until the voltmeter indicates approximately 0 7V h Program the voltage to 10 00V and the current latch to 50mA i Adjust
82. Pocket Pro grammer depends upon the instrument being pro grammed The voltage magnitude switches may be up open circuit or down grounded to program ones orzeros Refer to the appropriate Option Appendix or Modification Sheet supplied with the instrument being programmed aROSS CURRENT LIMIT 19 Tum off power to the DVS Disconnect the 2004 load and connect the 355 17W load ackoss the HI and LO terminals 20 On the DVS rear barrier strip jumper the terminals This disables the programmable current latch circuit 21 Set the voltage magnitude switches and OUTPUT SIGN switch on the Programmer for an out put voltage of 10 volts 22 Set the CURRENT METER RANGE switch on the DVS front panel to 0 6A and the STORAGE DISABLE switch on board A2 to DISABLE 23 Tum on power to the DVS and press the Programmer GATE switch Observe that the DVS voltmeter reads 10V 24 While observing the DVS ammeter crease the voltage magnitude input in 1 steps to a maximum of 22V until the current no longer increases limiting The current at limiting should be between 0 55A and 0 6A 25 Set the voltage magnitude switches and OUTPUT SIGN switch on the Programmer for an out put voltage of 10V 25 While observing the DVS ammeter in crease the voltage magnitude input in 1V steps to a maximum of 22V until the current no longer increases limiting The current at limiting should between 0 55A and 0 6A
83. TP33 will merge if the cur rent latch delay is less than approximately 10 For example if the current latch is 10usec the wavetorm at TP33 consists of a single pulse having a width of approximately 20usec 4 109 Overload Range Flag Isolator and Inverter The positive high output from the OR gate TP33 BEGIN CURRENT OVERLOAD OVLD SIGNAL BEGIN CURRENT Fr LATCH 2011SEC LATCH DELAY e SEC SEC 9 OUTPUT OVLD FLAG GEN Overload Flag Generator Output With 20usec Latch Delay Figure 4 7 is applied to the overload range flag isolator and inverter circuit The photo isolator circuit A6Q31 75 Q32 is identical to those previously described The low output at the collector of 032 is applied to the base of inverter 033 to produce a high the collector of 033 which is conducted through A6CR20 Diode A6CR20 along with diode 1 1 comprise on OR gate input to the flag iso lator and output amplifier inverter circuit Pigure 7 2 sheet 1 4 110 Overload Status Isolator and Output Am plifier The overload status isolator and output amplifier A6A6 is similar to the latch status iso lator and output amplifier A6A5 described in par agraph 4 105 latch condition the input to 5 is positive causing A6A5Q2 to conduct an overload condition the input to A6A6 is negative causing A6A6Q2 to cutoff Inverter prov
84. VS UNDER TEST STRAP CT POCKET PROGRAMMER AN HP145338 25 Lut NOTES OSCILLOSCOPE HP i80 C D X HPI821A DELAY TRIGGER O COMMON CHANA CHAN B O PROGRAMMING SIGN DEVICE TOI BIT SEE NOTE 7 syne OUTPUT 0 i OUTPUT DATA i COM i HIE PEE FUNCTION GENERATOR HP 3310478 PROGRAMMING DEVICES SUCH AS HP9820 CALCULATOR OR HP 2100 COMPUTER ARE PREFERRED IN THIS TEST SET UP THE POCKET PROGRAMMER AND FUNCTION GENERATOR ARE ALTERNATES IF THE CALCULATOR OR COMPUTER ARE NOT AVAILABLE X WITH 1801 VERTICAL PLUG IN WITH OPTION 001 821 TIME BASE PLUG IN AND 100048 100058 OR 100068 PROBE Figure 5 2 4 SAMPLE HOLD TRACK HOLD b Set switches on HP 1821A Delay Section of HP 180 C D as follows 1 AC or ACF SLOPE or AUTO 2 TRIGGER LEVEL Adjust for stable display 3 TIME DIV Delayed to 0 1 to 0 Set HP 1821A Main Section of HP 180 as follows 1 SWEEP MODE AUTO 2 INT SLOPE or AC 3 TIME DIV 1msec with X10 magnifier 4 Set sweep to MAIN d Set switches on HP 3310 A B as follows 1 FREQUENCY 100Hz 2 FUNCTION Squarewave 3 OUTPUT LEVEL Value specified in DVS Appendix for data and sign bits e Set switches on HP 14533B as follows 1 SOURCE SELECT EXT 2 MP DCPS DCPS 3 I LATCH 500mA 122 down 123 up L24 down 4 INPUT LEVEL REF DATA COM 5 RANGE f On DVS A2 board set switch to STORA
85. VS can be operated from a 115Vac 10 48 440Hz power source In addition the DVS can be operated from a 230Vac 10 single phase input when the unit is equipped with Option 28 see Paragraph 1 15 This versatility makes the instrument compatible with the European power system 1 13 SPECIFICATIONS 1 14 specifications for the Digital 1 1 1415 OPTIONS 1 16 As mentioned previously DVS s interfaced at the factory There is standard instrument each unit has an option number for identification There are five standard options which satisfy the majority of interfacing require ments Two of these options 061 and 063 are for BCD instruments while the other three 120 062 and 064 are for binary units Detailed coverage of these options is included in Appendixes at the rear of the manual Description Rewire for 230Vac Input Consists of reconnecting the input transform ers for 230 volt operation and chang ing the fuse Refer to Section II for details Binary Interface for 12661 DVS Program Card Input output circuits on boards 1 2 and are modi fied to interface with computer Refer to proper Appendix for details BCD Interface for NPN Open Col lector Circuits Input output cir cuits C boards 1 2 and are modified to interface with a BCD digital source employing open
86. a Connect test setup shown in Figure 5 1 Set the METER switch to the highest voltage and current ranges b Program the current latch to 0 5 ampere supply d Program the output voltage to 4 100 0 volts and gate the unit Read and record voltage indicated on 5 5 voltmeter f Disconnect load open and gate the unit g Reading on voltmeter should not vary from reading recorded in Step e by more than 500uV h Reconnect load i Program the output to 100 0V and gate the unit j Repeat Steps e and 8 Reading on voltmeter should not change from reading recorded in Step by more than 500uV Program the output to 16 3835 volts X1 range and gate the unit m Change load to 355 17 watts n Repeat Steps e and o Reading on voltmeter should not change from the reading recorded in Step e by more than 150 p Reconnect load 35 17W Program the output to 16 384 volts X1 range and gate the unit Repeat Steps e and f 5 Reading on voltmeter should not change from reading recorded in Step by more than 150uV POWER SUPPLY UNDER TEST HLS HL LO LOS GND DIGITAL OR DIFFERENTIAL VOLTMETER Figure 5 1 Constant Voltage Load Regulation Test Setup 5 18 Line Regulation Definition The change A Egg in the static value of dc output voltage re sulting from a change in ac input volt age over the specified range from l
87. adelphia Handle Co Inc Camden N J 0 5 Terminals Inc Cincinnati Ohio Hamlin Inc Lake Mills Wisconsin Clarostat Mfg Co Inc Dover Thermalloy Dallas Texas Hewlett Packard Co Loveland Div Loveland Colo Cornell Dubilier Electronics Div Federal Pacific Electric Co Newark General Instrument Corp Semicon ductor Prod Group Hicksville N Y Fenwal Elect Framingham Mass Corning Glass Works Electronic Components Div Raleigh N C Newark N J Use Code 28480 assigned to Hewlett Packard Co Paio Aito California 6 2 CODE NO 16758 3 17803 17870 18324 19315 19701 21520 22229 22753 23936 24446 24455 26982 27014 28489 28520 28875 31514 31827 33173 35434 37942 42190 43334 44655 46384 47904 49956 55026 56289 58474 58849 59730 61637 63743 Use Code 71785 assigned to Cinch Mfg Co Chicago Ill Table 6 3 Code List of Manufacturers Continued MANUFACTURER ADDRESS Delco Radio Div of General Motors Corp Kokomo Ind Atlantic Semiconductors Inc Asbury Park Fairchild Camera and Instrument Corp Semiconductor Div Transducer Plant Mountain View Calif Daven Div Thomas A Edison Industries McGraw E dison Co Orange Signetics Corp Sunnyvale Calif Bendix Corp The Navigation and Control Div Teterboro Electra Midland Corp Mineral Wells Texas Fansteel
88. and 16 384 voit supplies at test points TP55 TP52 and TP53 If any of these voltages is not within tolerance check the regu lating circuit for that particular voltage Note that a shorted switching transistor Q2 or Q3 can affect the 16 384 volt reference If one of these two switching transistors is shorted either a high or low input respectively to Q1 will load down the positive reference through Q2 and Q3 in series Q2 or Q3 short can be detected by monitoring the 16 384 volt regulator output while toggling each input bit b Program all voltage magnitude input bits to produce low inputs at the base of Q1 and measure the voltage at TP54 of each bit The voltage at TP54 should be between zero and 8mV 1f any bit is higher than 8mV check Q1 and Q3 c Now program for high inputs at the base of Al and again measure the voltage at TP54 of each bit Allbits should be within 8mV of TP52 voltage If any are lower than this voltage check and 32 d ladder network switching circuits are now operating properly the voltage at TP54 of each bit can be alternated between the values specified above by toggling the input bit e the sign bit tested good at A2TP51 but does not affect the output of the A3 board check transistors A3Q13 and 14 in the polarity offset switch A failure either here or in the 16 384 volt reference supply is likely NOTE If any repair or adjustment of the power amplifier is requ
89. ata The current latch data input from the computer consists of a three bit binary code which is shown in Section of this man ual This code establishes the point at which the DVS will current latch The voltage range data input is a single binary bit which determines the voltage range X1 or X10 4 55 Input Isolators Four input isolator circuits identical to the voltage magnitude input isolators described above are utilized They provide the logic interface and dc isolation for the current latch and voltage range data signals from the com puter 4 56 Storage and Storage Disable In store mode the three bits of current latch data TP74 are stor ed in flip flops along with the one bit of voltage range data TP76 These storage flip flops are enabled by the storage gate and are identical to the ones used in the voltage processing storage circuit If the storage disable switch in the voltage processing circuits is in the DISABLE position these flip flops as well as those in voltage processing are disabled and pass data directly through without storing it The three current latch data output lines from storage TP75 are applied to the current latch decoder and the voltage storage output TP73 to the range pulse generator 4 57 Qurrent Latch Decoder The current latch decoder generates a reference voltage for each the six current latch bit combinations just mentioned the current latch bits are re
90. ation paragraph 5 79 4 Connect voltmeter positive lead to the POS REF TP101 on board and the common lead reading is incorrect check the negative reference to TP99 inverter 6023 73 and the positive reference re 5 Set the current latch to a value of 1000mA sistor A6R37 Also check the current latch cal and check that voltmeter reads 1 250 510 If ibration paragraph 5 79 Table 5 6 6 Troubleshooting Guide SYMPTOM Unit always in current latch AG TROUBLESHOOTING SECTION Proceed to Table 5 8 Proceed to Table 5 Unable to current latch at turn on Unable to current latch at latch setting Current latch operating properly but latch status is always in the same state on or off Proceed to Table 5 10 Proceed to Table 5 11 Proceed to Table Current latch operating properly but overload status is always in the same state on or off Flag is not generated for both range switching and overload conditions Proceed to paragraph 5 61 Check the overload range flag isolator 6031 032 033 and 25 Check 2 millisecond delay circuit A6CR12 CR13 CR16 Q26 Q27 Q28 Flag is not generated when range is switched but is generated for an overload condition Check overload flag generator A6CR14 CRI5 Q29 Q30 Flag is not generated for an overload condition but is generated when range is s
91. ation as described in Step 1 If there is pull up resistor A6A6R8 5 64 A7 POWER AMPLIPIER BOARD TROUBLE SHOOTING 5 65 Before attempting to troubleshoot the power amplifier it is important to classify the kind of trouble present according to the trouble symptoms Generally troubles in the 7 board generate two broad categories of symptoms current latch prob lems and output voltage problems For example if output voltages can be programmed with no load but no current can be drawn when a load is added the problem is most likely a current latch type However if output voltages cannot be programmed without a load the problem is probably an output voltage type b Two logic levels RESPONSE Only one logic level Two logic levels pres i b One logic level pres b Two logic levels pres b operation of the overload status photo isolator circuit see para graph 5 53 5 26 Latch Status Troubleshooting Continued RESPONSE a One logic level CONCLUSION A6A5Q3 defective or A6A5Q2 shorted b Remove short and check the operation of the latch status photo isolator circuit see paragraph 5 53 Overload Status Troubleshooting CONCLUSION a 4 defective or A6A6Q3 shorted Remove short and proceed to Step 2 A6A6Q3 defective or A6A6Q2 shorted Remove short and check the use an ohmmeter 5 66 troubleshooting pr
92. biased attenuator network R1 R2 and R3 makes it possible by seiecting appropriate values to adapt to any of the three standard binary interface options or through resistor choice and or resistor bias polarity to adapt to other driver circuits as required whether NPN or PNP The logic convention of the source may either be positive true or negative true See Figure 4 4 The voltage levels and circuit de tails for the inputs and outputs of instruments having any of the stahdard options are given in the appropriate Option Appendix in the back of this manual interface information for other instruments is given on the Instrument Modification Sheet in cluded with the instrument NPN LOGIC LEVELS ISOLATOR INPUT 0 1 NEGATIVE TRUE INPUT BIN 1 ISOLATOR INPUT TE 0 POSITIVE TRUE INPUT BIN 1 Figure 4 4 Input Voltage Divider Networks 4 69 When the input TP10 is at its more positive level Ol is turned on and energizes the LED in photo isolator assembly Z1 The photons emitted by the diode cause the phototransistor to conduct turning on Q2 to apply a low to the data input TP13 of the storage flip flop for that data bit and R5 form a low impedance load for the photo transistor to minimize its switching time more negative level from the computer produces a high input to the flip flop Note that a signal level inversion occurs between the isolator inp
93. bit and observe the volt age reading r Set the Programmer RANGE switch to X10 and adjust A7R85 for 10 times and the reading in Step imV y Repeat Steps p through r until no further adjustments are necessary t Turn off DVS and replace bottom cover or remove extender boards and replace boards as applicable 5 73 METER ZERO 5 74 To zero set either the voltmeter or ammeter proceed as follows a Turn the instrument off Wait one min ute for power supply capacitors to discharge com pletely b Insert sharp object pen point or awl into the small indentation near the top of the rqund black plastic disc located directly below the meter face c Rotate the disc until meter reads exactly Zero 5 75 VOLTMETER ADJUSTMENT 5 76 To adjust the calibration of the DVS volt meter proceed as follows a On the Pocket Programmer set the data bits OUTPUT SIGN and RANGE switches for a voltage output of 20V b Turn on DVS and press GATE switch on Programmer Set the DVS front panel VOLTAGE control to the 20V position and adjust A4R14 until meter reads 20V d Setthe data bit OUTPUT SIGN and RANGE switches for an output voltage of 20V The voltmeter should read 20V If it does not halve the error and adjust A4R14 accordingly 5 77 AMMETER ADJUSTMENT 5 78 To adjust the calibration of the DVS Ammeter proceed as follows Connect 200 ohm 50 watt 1 resistor across the and L
94. burn Mass Essex Wire Corp Stemco Controls Div Mansfield Ohio Raytheon Components Div Ind Components Oper Quincy Mass Wagner Electric Corp Tung Sol Div Southco Inc Leecraft Mfg Inc L 1 C Methode Mfg Co Rolling Meadows Bendix Corp Microwave Devices Div Weckesser Inc Amphenol Corp Amphenol Controls Div Janesville Wis Industrial Retaining Ring Co Irvington N J IMC Magnetics Corp Eastern Div Westbury N Y Sealectro Corp Mamaroneck Y inc Cleveland Ohio international Electronic Research Corp Burbank Calif Boston Mass Radio Materials Co Augat Inc Livingston N F Lester Pa Franklin Ind Chicago Renbrandt Inc Al Al 1 1 DESIG REF Al 1 2 01 2 R1 2 3 R5 R6 Z1 A2 through 1 17 1 3 C5 C6 CR1 4 Q1 Q2 Q5 Q6 Q7 1 2 3 R4 R5 R6 R7 RB R9 R10 R11 R12 R13 R14 R15 R16 R17 18 19 R20 R21 R22 R23 VRI VR2 3 VR5 271 9 23 4 Table 6 4 Replaceable Parts HP DESCRIPTION Input Board Isolator circuit Diode Si 200mA 75V 55 NPN fxd comp 750a 55 1 2W comp 824 5 1 4W comp 75024 595 1 4 Photo isolator as A1A1 fxd Diode fxd fxd fxd
95. ceived from storage The incoming bits are first converted to an analog reference current which is then used to develop the negative reference voltage This voltage is fed directly to the negative current comparator and to the negative reference inverter which provides an equal amplitude opposite po larity reference voltage to the positive current com 4 58 Current Comparators positive negative current comparators compare a sample of the output current voltage drop across the current sampling resistance with the negative or positive reference If the IR drop across the sampling sistance equals or exceeds the reference voltage an overload signal TP17 Figure 4 3 is generated The polarity of the output current determines which of the comparators is activated The overload sig nalis fed both to the current overload circuits isolator and overload flag generator and the current latch circuit variable delay Once the unit switch es to the current latch mode the output current is reduced to under 10mA and the current overload sig nal at TP17 reverts to its normal state 4 59 Qurrent Overload Circuits The current overload c rcuits comprise an isolator output amplifier and overload generator The iso lator a photo isolator of the type used through out the DVS provides dc isolation between the computer and the DVS output amplifier in terfaces the DVS overload circuits wit
96. collector is fed to the emit ter of A7Q24 via swamping resistor A7R70 This allows 7024 to conduct through the 10M Hz tank circuit 1 primary winding and capacitor C20 in its collector circuit Voltage divider resistors R68 and R69 establish the base bias Regeneration for sustained oscillation is coupled from the col lector winding of to the base winding Each end of the output winding contains a rectifier fiiter network in order to drive the push pull cur rent latch switch A7Q8 and A7Q9 Rectifiers CR7 and CR8 conduct on the positive half cycles rectifier diodes CR11 and CR12 conduct on the negative half cycles Under latch conditions both Q8 and Q9 conduct to zero bias the power amplifier push pull input stage A7Q10 and 7012 4 131 Disconnect Interlock Relay A4K1 and driver transistor A4Q1 protect the load by shorting the output terminals of the DVS under certain con ditions The output terminals are shorted when is deenergized This occurs if the 3 common input from the computer is removed or the 12V DELAYED is not present When the unit is first turned on is also deenergized because the 12V bias input is delayed for approximately 0 2 seconds after tum on Notice that the current latch circuits are activated at this time and thus must be reset with a gate input before the unit can be restored to normal operation The output is also shorted at turn off of the unit because the 12V bias input
97. computer The range pulse generator provides two outputs one for the range relays in the power amplifier and the other for the generation of a voltage range signal to the computer if the input voltage range bit calls for the X1 range the range pulse generator con nects a common to the power amplifier range relays to energize them the X10 range the range relay lead is open and the relays are deener gized The range pulse generator also provides a negative output pulse for each positive or negative transition of the voltage range input The positive going output triggers a 2msec delay circuit which provides the voltage range flag signal This signal is OR ed with the overload flag signal and applied to the voltage processing circuits through a photo isolator and an output amplifier The overload range flag enable output signal drives the flag OR circuit in the voltage processing circuits exampie of a voltage range flag is shown on Figure 3 5 The Zmsec delay period allows time for operation of the range relays and for process ing of the voltage range input bit 4 66 DETAILED CIRCUIT ANALYSIS 4 67 VOLTAGE PROCESSING See Figure 7 2 Sheet 1 4 68 Input Isoletor Circuits The input isolator circuits A1 A15 for the fifteen voltage data bits and for the sign bit A17 are all identical They employ light emitting diode phototransistor iso lators to eliminate dc paths between the computer and the DVS output
98. dance of both the equalizing and main feedback networks In the Xl range the relays are energized reducing the impedance of the feedback networks and thus increasing the amount of negative feed back through both networks the X1 range the overall amplification is multiplied by a factor of 1 jn the X10 range the relays are deenergized mul tiplying the amplification by 10 4 44 Coupling Amplifier This inverting stage couples the input stage of the overall amplifier to the power amplifier stages which are much higher power level The voltage and current gain of the coupling amplifier is minimal 4 45 Power Amplifier The power amplifier stage furnishes most of the current gain of the overall amplifier The output stage is a class AB push puil complementary connected amplifier which produces the positive or negative output voltage The output at the high sense terminal is fed back to the input of the overall amplifier resulting in a constant put voltage which is independent of load variations 4 46 Current Latch Input The current latch signal is received from the latch processing circuits if the preselected current latch value is exceeded An isolating oscillator first isolates the power ampli fier from the current latch circuit The isolator out put then activates the current Latch switch which turns off the power amplifier 4 47 Under current latch conditions the non conducting power amplifier presents an i
99. e least significant bit Ex amples of positive and negative input numbers will be given later 4 28 Input Isolators Voltage magnitude and voltage sign data input isolators provide the logic interface and dc isolation required between the user s computer and the DVS Incoming voltage magnitude data is applied first to a resistive volt age divider which establishes voltage levels that can be readily utilized by the DVS DC isolation is provided by a photo isolator The input iso lator circuit inverts the polarity of the input data and in the case of PNP driver circuit converts it to signal levels appropriate to the NPN logic circuits of the DVS 4 29 Gate Input and Timing The gate input initiates storage and other timing functions within the DVS As described in Section III Fi gure 3 4 the leading edge of the gate must be received at least 10usec before the voltage mag nitude data and sign bits are terminated 4 30 The input gate signal is first level set by a resistive voltage divider and then inverted if necessary to ensure that the 3 microsecond delay circuit receives a positive going input transition The 3 microsecond delay circuit produces 3 microsecond negative pulse TP4 whose trailing edge activates the 50 microsecond delay circuit The two complementary outputs of the 50 micro second delay are 5 microsecond pulses delayed from the input gate by 3 microseconds The 3 microsecond delay ensures tha
100. e output currents but not for positive output currents or if the unit is in current latch for all values of positive output current and works cor rectly for negative output current latch settings the cause of trouble must be in a circuit which handles the flow of the positive current latch sig nal only There are three stages which handle only the positive output current latch signals A6Z4 A6CR2 and the Negative Reference Inverter 623 A6023 and associated components Check 624 and A6CR2 first these two components are operative the trouble probably lies in the negative reference inverter Check A6Z4 and A6CR2 for open or shorted junctions 5 63 Current Latch Decoder Troubleshootir To troubleshoot the current latch decoder circuit the following procedure is recommended 1 Connect voltmeter positive lead to the NEG REF TP100 on board A6 and the common lead to TP99 Turn unit on and GATE unit Set the STORAGE DISABLE switch on A2 to DISABLE 2 Set the current latch to each value and check that the associated voltage reading is as indicated below Current Latch Voltage Reading Value mA mV 10 17mV 20 425 50 162 5 70 4 87 5 100 125 200 4250 500 625 3 Ifall voltages are incorrect check current latch decoder stage A6Q1 and the negative refer ence resistor A6R30 If any voltage reading or combination of voltage readings are incorrect re fer to Table 5 7 Also check the current latch calibr
101. ears at the output terminals as the programmed output voltage 4 37 Polarity Offset Switch and 16 384V Reference input data bearing a negative sign the polarity offset switch is held off by the sign input from storage and has no effect on the operation of the D A converter Under these con ditions the D A converter supplies a positive output current which is proportional to the applied binary data For positive input data the sign input turns on the polarity offset switch and a negative reference current of 1 6384m is applied to the D A converter from the 16 384V reference source The negative reference current is then summed within the D A converter with a positive current which is numerically equivalent to the complemented value of the original input data The resultant output then is a negative analog current which has been restored to the original numerical value of the positive input data prior to complementing by the additional of the 1 6384mA reference current 4 38 To better understand the processes which take place within the voltage processing circuits refer to Figure 4 2 With 4 volts programmed SOLATORS 001HHOIOO0000 AND 100000101 D STORAGE FROM amp 2 COMPUTER B ISOLATORS 110000011000000 AND ay STORAGE A2 FROM COMPUTER X THE POWER AMPLIFIER HAS 0 05 OFFSET Figure 4 2 into the DVS the isolators s
102. easurement 5 30 The simple direct test equipment connection of the rms measurement is normally not adequate to measure the high frequency components of the peak to peak ripple and noise Figure 5 4A shows technique using a 50a coaxial cable between the DVS and oscilloscope that is terminated in its char acteristic impedance Note that the terminating network is placed across the DVS output to avoid attenuating the low frequency 60Hz component of the ripple and noise Further the impedance matching network eliminates standing waves and cable ringing which might introduce erroneous values in the measurement 5 31 In most cases the single ended scope meth od of Figure 5 4A will be adequate to eliminate non real components of ripple so that a satisfactory measurement may be obtained However if the DVS and oscilloscope cannot be plugged into the same ac power buss or the peak to peak reading obtained with a single ended scope exceeds the specifications due to Ig it will be necessary to use a differential scope with properly terminated floating inputs as shown in Figure 5 4B Note that the coax connectors are not connected to ground on the DVS end Because of its common mode rejection a differential oscilloscope dis plays oniy the difference in signal between its two vertical input terninals thus ignoring the effects of any common mode signal produced by the dif ference in the ac potential between the power sup ply case a
103. eck POS REP TP101 with meter common con nected to TP99 a Negative reference inverter operating properly Check posi tive current comparator 624 R32 R34 and R43 a Voltage equals 0 625V 410 b Voltage does not equal 0 625V 41096 b Check negative reference inverter A623 023 Table 5 11 Latch Status Troubleshooting STEP ACTION RESPONSE CONCLUSION Check the operation of a Only one logic level a A6A5Q4 defective or A6A5Q3 A6A5QA by first shorting present shorted A6A5Q3 emitter to base and then emitter to collector b Two logic levels b Remove short and proceed Monitor the output with present to Step 2 a voltmeter connected between TP22 and 3 common If there is no pull up resistor A6A5R8 use an ohmmeter 5 25 Table 5 11 STEP ACTION Check the operation of A6A5Q3 by shorting A6ASQ2 first emitter to collector and then emitter to Mon itor the output after each Operation as described in Step 1 present present Table 5 12 ACTION If A6A6Q4 is in the circuit modifica present tions sheet test its operation by first short D ing A6A6Q3 emitter to ent base Monitor the out put with a voltmeter connected between TP25 and common after each operation Check the operation of A6A6Q3 by shorting ent A6A602 first emitter to collector and then emitter to base Monitor the out ent put after each oper
104. ee major Stages a feedback dif ferential amplifier coupling amplifier and power amplifier Negative feedback is employed from output to input creating a near zero impedance summing junction at the input of the feedback differential amplifier The amplifier provides an output of 1 volt for every of input current E 10 000 x in the range or 10 volts for very 100 of input current Egy 100 000 X in the X10 range Hence in the range the D A converter supplies its maximum input current of approximately 1638 4 microamperes to obtain 416 384 volt output For the X10 range however the D A converter need pro vide only 100044A to attain the maximum rated output of 100 volts If a number larger than 50 is programmed in the X10 range the additional D A input current has little effect on the output because the output of the amplifier is internally limited to approximately 110 55 volts 4 42 Feedback Differential Amplifier This circuit amplifies and inverts the D A output and or analog input signal before applying to the coupling amplifier 1 provides most of the voltage gain of the overall amplifier Negative feedback is em ployed with an equalizing network which shapes the high frequency responses for stability purposes 4 43 Voltage Range A range input from the voltage range processing circuits controls the operation of the range relays which in turn determine the im pe
105. eee wee Input Output Signal Polarity Receiver Circuits and Logic Levels Voltage Magnitude Input Data Voltage Sign Section Page No IV PRINCIPLES OF OPERATION Continued 4 52 Current Latch and Voltage Range Processing 4 6 4 66 Detailed Circuit Analysis 4 8 4 67 Voltage Processing 4 8 4 88 Current Latch Voltage Range Processing 4 12 4 114 Power Amplifier 4 15 4 131 Power Distribution 4 17 SECTION 1 GENERAL INFORMATION 1 1 DESCRIPTION 1 2 Digital Voltage Source DVS is a com plete digital to analog link between a computer or other digital source and any application re quiring a fast accurately settable source of dc or low frequency ac power 1 3 constant voltage current limiting source the DVS will furnish full rated output voltage at the maximum rated output current or can be contin uously programmed throughout two output voltage ranges The output is bipolar and is program mable on either side of or through zero without output polarity switches or notch effects In ad dition the DVS has low output impedance the load does not degrade the accuracy specification The DVS analog output is floating and fully isolat ed from the digital inputs thus avoiding ground loops between the output ground and the computer ground 1 4 The output voltage is controlled by digital data inputs applied to the DVS via a ribbon con nector on the rear panel 1 5 Overcurrent protection is
106. h output signal is not generated until after variable delay period has elapsed delay ranges from approximately 3usec to 2msec Variable delay stage Q16 receives the overload signal and if the terminals are open passes the inverted signal on to Q17 with a minimal delay less than 1 Under these conditions the latch delay period is dependent solely on the natu ral circuit delays of the level detector latching flip flop current latch switch and the power am plifier see Sheet 3 The time required to initiate turn off at the power amplifier with the termin als open is approximately 3 to lOysec 4 99 For greater latch delays a capacitor can be connected across the terminals When 016 is cut off by the negative going overload signal the positive going slope on its collector is now deter mined by the time taken by capacitor Cy to charge through R42 Hence increasing the value of increases the latch delay period 4 100 Shorting the CT terminals places the collec tor of Q16 at 2 potential preventing 017 from conducting This prevents the unit from operating the current latch mode Note that if the unit is already in the current latch mode shorting the terminals will not transfer it out of current latch 4 101 Level Detector Transistors Q17 and Q18 form a Schmitt trigger circuit which switches state when the positive going input signal reaches the threshold level Transistor Q17 co
107. h the com puter receiver circuits by providing an overload Status signal TP25 of the proper magnitude and Igyr EXCEEDS CURRENT LIMIT NORMAL CURRENT OVLD OVLD VARIABLE LATCH DELAY VARIABLE DLY l 2 msEC 5 NORMAL NORMAL OVLD STATUS lovin RESET Dx CURRENT LATCH 3 e ASEC 1 mundus DLY INPUT LATCHING F F RESE 2 LATCH TO PWR AMPL NORMAL i NORMAL LATCH STATUS LATCH X POLARITY DEPENDENT ON COMPUTER DRIVER OR RECEIVER CIRCUITS Figure 4 3 Current Overload and Latch Circuits Timing Diagram polarity 4 60 The overload flag generator provides a 10psec wide flag enable output signal TP33 at both the leading and trailing edges of the current overload signal at TP17 The first trip signal indicates the stert of an overload while the se cond denotes that current latch has occurred If the variable delay period is less than 10usec note that the trip signals at TP33 will overlap and appear as one signal Since the minimum latch delay is approximately 3usec the minimum trip signal width is 13usec The overload flag trip sig nals are OR ed with the voltage range flag signal and then applied through a photo isolator and an output amplifier to the voltage processing circuits This signal overload range flag enable is applied to OR circuit in the vol
108. hat output ter paragraph 5 67 minals are not shorted Turn unit on and Gate unit Check 21 Logic level 1 b Ensure that input plug Pl is connected Proceed to Step 2 a Buffer stage A6Q21 probabiy working go to Step 3 2 Check TP20 a Voltage magnitude equals approximately 5V b Logic level 1 b Check 6021 for open Check TP14 a Logic level 1 a Reset amplifier working 6020 for open If A6Q20 not open to Step 4 b Logic level 0 b Check Reset Amplifier A6Q24 for short 5 21 Table 5 8 Unit Always in Current Latch Continued ACTION Boon CONCLUSION TP98 Logic level 0 Relay A4K1 probably working go to Step 5 Logic level 1 b Relay A4K1 defective causing false setting of latching flip flop 6019 020 Latching flip flop probably working go to Step 6 Connect voltmeter common to Check 9 Log c level 1 Logic level 0 Check A6Q19 for short Check TP18 mye Level detector A6Q17 and A6Q18 probably good go to Step 7 Logic level wot b Check 46017 for short and A6Q18 for open Logic level Check TP17 a Variable delay A6Q16 probably operating go to Step 8 Voltage magnitude 0 5V Logic level 1 b
109. he output of the sign flip flop Storage can be disabled by the storage disable switch on the logic board in which case the out puts of the storage flip flops follow the data inputs continuously Voltage and sign data from storage is applied to the digital to analog converter 4 35 Digital To Analog Converter digital to analog converter converts the digital data to either a positive polarity analog current for nega tive voltage magnitude inputs ora negative polarity analog current for positive voltage magnitude inputs The latter is accomplished by a negative reference current applied to the converter by the polarity off set switch whenever the input is positive The magnitude of the D A converter output current varies between plus and minus 1 6384mA accord ing to the value of the incoming voltage and sign data 4 36 The D A converter contains a series of switches transistors which are activated by the input data bits from storage These switches then act on a resistive ladder network which produces an output current in milliamperes which is pro portional to the numerical value of the input data The combined output of the ladder network and the polarity offset switch make up the voltage mag nitude signal This signal is applied to the power amplifier where it is summed with the current pro duced by the external analog input if The algebraic sum of these currents is inverted by the power amplifier and app
110. hile the three emitter coupled push pull stages provide most of the total current gain of the power amplifier Hence the voltage at the bases of the push pull input stage Q10 and Q12 is essentially equal to the output voltage of the unit Q7 together with VR10 R36 CR16 CR18 CR21 CR22 R38 R91 and VR11 form a voltage divider network in the base circuit of the input stage The conduction of Q7 controls the current flowing through the voltage divider and thus the bias at the bases of the input transistors Zener diodes VR3 VR4 VR8 and VR9 connected to the bases of 010 and 012 prevent the output voltage from exceeding approximately 110 volts Diode CR19 protects Q10 and Q12 from the effects of possible reverse voltages 4 123 Under current latch conditions transistors 010 and 012 are biased below cutoff due to the conduction of Q8 and Q9 part of the current latch Switch circuit The conduction of these transistors effectively shorts the bases of Q10 and Q12 to the high output terminal reducing the bias current to zero The current latch switch and isolator circuits are described in succeeding paragraphs 4 124 The second push pull stage 011 and 013 on the A amplifier board drives the power output transistors 01 through Q6 which are mounted on the rear heat sink These transistors are connected in series between the 140V and 140V supplies The conduction of Q2 or Q3 is controlled directly by the output of 011 or 213
111. hori duration could be present in the ripple and not appreciably increase the RMS value 5 27 RMS Measurement To check the rms value of ripple and noise proceed as follows a Connect 2002 50W load across HI and LO terminals b Using coax cable connect rms voltme ter HP 3400A is recommended to the DVS HI and LO terminals On the DVS end connect the coax inner conductor to the terminal and the coax shield lead to the LO terminal which is also con nected to DVS ground Strap terminals together d Program the output voltage for 100 volts and the voltage range to X10 The voltmeter should read less then l 5mV rms f Program the voltage range to X1 and out put voltage to 16 3835 volts Change load to 35a 17W g The voltmeter should read less than 0 5mV rms 5 28 Note that continuous ground loop exists from the third wire of the input power cord of the rms meter via the grounded power supply case the wire between the negative output terminal of the power supply and the input of the meter the grounded meter case Any ground current circulat ing in this loop as a result of the difference in po tential between the two ground points causes an IR drop which is in series with the meter input This IR drop normally having a 60Hz line frequen cy fundamental pius any pickup on the leads in terconnecting the power supply and meter appears in the meter reading The magnitude of th
112. ides a LO output to indicate an overload status Stage 6 4 is omitted for the standard options 4 111 Voltage Range Circuits The voltage range circuits energize or deenergize the voltage range relays in the power amplifier and also provide 2msec wide flag output to the computer whenever the voltage range is changed For the X10 range the range input bit is a positive level causing the range storage flip flop to provide a negative in put to the base of Q25 range pulse generator This holds Q25 off opening the collector lead which is connected to the range relay coils Sheet 3 via A5 6 pin D Hence in the X10 range relays are deenergized 4 112 For the range the range input bit is negative level causing the range storage flip flop to provide a positive input causing Q25 to conduct coupling 2 common to the range relay coils to energize them Differentiating networks and limit ing diodes C8 R74 CR12 and C9 R75 CR13 in the base and collector circuits of Q25 couple positive going transitions to the base of Q26 in the 2msec delay circuit whenever a change in range occurs 4 113 The 2msec delay circuit is composed of transistors Q26 and Q28 connected in a type of one shot multivibrator configuration and transis tor Q27 which provides current gain between the one shot stages In the stable state transistors 028 and 027 are conducting and 026 is held off due to the voltage drop across common e
113. ified schematic of Figure 4 5 the Switching transistors are represented by mechanical switches connecting each of the four rungs in the analog ladder network to either 16 384V or ground 2 Again the switch positions represent the bi nary input of 1100 the four most significant bits of the inverted input of 4 volts SUMMING POINT OF AMPLIFIER ZERO IMPEDANCE 16 384 Figure 4 5 Ladder Network Simplified Schematic Ladder Network Thevenin Equivalents Figure 4 6 4 80 Figure 4 6A shows the voltages at the input of each rung To determine the current flowing into the summing point 9 from the ladder network Thevenin Equivalent can be constructed for each rung If the circuit is broken above TP59 the open circuit voltage at TP59 is OV and the impedance looking into TP59 is 20K in parallel with 20K or 10K Thus the Thevenin Equivalent is ground in series with 10K as shown in Figure 4 6B Breaking the circuit at TP58 and replacing this portion by its Thevenin Equivalent we have the circuit shown in Figure 4 6 Now breaking the circuit at TP57 and solving for the voltage at this point 16 384 x 20K 8 192V we are left with the circuit shown in 40K Figure 4 6D This figure shows that the current flowing into the summing point TP56 is 1 2288mA 4 81 The currents flowing into the summing point from the other three ladder networks may be solved in the same manner and the results will
114. inals for High Output High Sensing Low Output Low Sensing Chassis Ground Cur rent Latch Delay Analog input and Current Mon itor are included on a rear barrier strip The Low Output terminal may be connected to the ground terminal or the output may be floated up to 300 volts above ground The output terminals are automatically shorted if the digital input cable is disconnected or if the input power is removed The Sensing terminals may be used when the load is remotely located from the DVS in order to avoid degradation in regulation at the load due to volt age drop in the load leads 1 10 INTERFACING 1 11 Each DVS is pre interfaced with its control ling computer or other digital device by modifying three of the plug in boards Five standard sets of these boards Option 120 and Options 061 through 064 satisfy the majority of interfacing require ments Each instrument must have either an Option number or a Special modification number e g 101 702 etc for identification The numbers are used for instruments which do not fit into the standard option category Detailed descriptions of the different options are included in Appendixes at the rear of each manual while descriptions of spe cial options are included on blue modification sheets in the front of applicable manuals The tion number for each instrument appears on an identification tag at the rear of the unit 1 12 As supplied from the factory the D
115. ined but the large inertia of mer cury pool relays l mits the maximum repetition rate of load switching and makes the clear display of the transient recovery characteristic on an cilloscope more difficult 5 36 The transient recovery time is checked in both the X10 and X1 ranges as follows a test setup shown in Figure 5 5 b Strap terminals together POWER SUPPLY OSCILLOSCOPE X UNDER TEST CONTACT PROTECTION NETWORK 0 5 0 5W 244 NOTE 3 200V i THIS DRAWING SHOWS SUGGESTED METHOD OF BUILOING A LOAD SWITCH HOWEVER OTHER METHODS COULD BE USED SUCH AS A TRANSISTOR SWITCHING NETWORK MAXIMUM LOAD RATINGS OF LOAD SWITCH ARE SAMPS 500V 250W NOT 2500W USE MERCURY RELAY USE WIRE WOUND RESISTOR OSCILLOSCOPE WITH 1806 VERTICAL PLUG IN 182 TIME BASE PLUG IN AND TWO 100078 PROBES LINE SWITCH i REPETITIVE LOAD SWITCH NOTE 1 i H Figure 5 5 Transient Recovery Time Test Setup Turn supply and program the output voltage to 100 volts d Close the line switch on the repetitive 10 load switch setup e Set the oscilloscope for internal sync and lock on either the positive or negative load transient spike Set the vertical input of the oscilloscope for ac coupling so that small dc level changes the output voltage of the power supply will not cause the display to shift g Adjust the sync con
116. input A2 Logic and A6 Control are modified at the factory to fit these requirements Most cus tomer requirements can be satisfied by one of the standard options for this instrument For require ments beyond the scope of the standard options 9 special modifications are made to the A1 A2 and boards Either an option number or a special J number is assigned to each instrument and is printed on an identification tag on the rear heat sink of the unit Options are described in pendixes located at the rear of the manual while specials changes are described in an Instrument Figure 3 3 Input Output Data Connector FLAG INPUT Modifcation sheet which is inserted in the front of any applicable manual 3 12 The following paragraphs describe the input output data that is transferred between the comput er and the DVS Sufficient detail to operate the instrument is included more detailed information is included in Section IV 3 13 VOLTAGE MAGNITUDE AND VOLTAGE SIGN DATA INPUTS 3 14 Fifteen lines designated according to their positive analog equivalent value in millivolts 0 5 1 2 4 8 4096 and 8192 comprise the voitage magnitude input This input is re ceived from the computer or other programming Source in a computer binary code Positive numbers are received in straight binary form while negative numbers are received in negative 2 s compiement form that is the equivalent positive number
117. int Approx 25kHz DO Gain X1 1 0 2 X10 Range 10 40 2 Stability 8 hours X1 Range Same as stability of input signal 500uV X10 Range Same as stability of input sig nal 5mV CURRENT SENSING impedance 8004 Coefficient 1 Volt Amp Accuracy 3 2 TEMPERATURE RATINGS Operating 09C to 559C Storage 409C to 759 COOLING Convection cooling is employed ACCESSORIES FURNISHED 20 Rear Plug HP Part No 1251 0086 Rack Mounting Kit HP Part No 5060 8740 Plug in Extender Board HP Part No 5060 7948 ACCESSORIES AVAILABLE Pocket Programmer Model 14533B This ac cessory permits manual programming of all in put functions by switch closures 3 Foot Extension Cable for Pocket Programming Model 14534 This accessory may be used with the Pocket Programmer for maximum con venience SECTION ii INSTALLATION 2 1 INITIAL INSPECTION 2 2 Before shipment this instrument was inspect edand found to be free of mechanical and electrical defects As soon as the instrument is received proceed as instructed in the following paragraphs 2 3 MECHANICAL CHECK 2 4 external damage to the shipping carton is evident ask the carrier s agent to be present when the instrument is unpacked Check the instrument for external damage such as broken controls or connectors and dents or scratches on the panel surfaces If the instrument is damaged file a claim with the carrie
118. ircuit preventing the generation of the current latch signals to the power amplifier and computer The user could employ this method dur ing testing or troubleshooting when the unit is off line or in any case where programmable latching is not desired 4 63 When the input at TP18 Figure 4 3 becomes sufficiently positive the level detector a Schmitt trigger is activated The positive going output TP19 sets the latching flip flop which in turn provides a current latch signal TP21 to the power amplifier and a latch status signal TP22 to the computer via an isolator and output amplifier Sim ilar to the other output circuits in the DVS this amplifier issues a latch status output signal which is of the polarity and amplitude necessary to inter face with the computer receiver circuits 4 64 The atching flip flop remains set until ap proximately 10 after the next gate input TP1 is received from the computer The leading edge of the 50usec delayed signal 7 is amplified and used to reset the flip flop Notice that if the cur rent overload still exists after the latch is reset the entire current overload and current latch pro cess is repeated and the unit will again revert to the current latch state 4 65 Voltage Range The voltage range circuits consist of a range pulse generator and a 2msec delay circuit The voltage range similar to the current latch is established by the voltage range data bit from the
119. ired that will have to be completed before the D A converter can be perfor mance tested or calibrated f steps a through e above confirm the proper operation of the A3 board voltage regulators bit switches and polarity offset switch the only possible trouble area remaining on the D A board is the resistive ladder network out of toler ance resistor in the ladder network will be detected only by attempting to calibrate the unit Perform the calibration procedure of paragraph 5 71 If one or more bits cannot be calibrated their iden tity should pinpoint the faulty resistor s If the 16 384 volt reference supply and polarity offset switch are operating but the polarity offset current adjustment A3R18 will not bring the DVS output voltage to zero in step of paragraph 5 72 19 or A3Q14 is likely to be at fault 5 51 Gate Flag and Storage Strobe Trouble shooting simplest method of troubleshoot ing these circuits is to trace signals with an oscilloscope while providing a gate input from a pulse generator The pulse generator may be con nected between common and either the GATE input jack on the Pocket Programmer The required pulse amplitude and polarity will depend on the instrument being tested See the appropriate Option Appendix or the Instrument Modification sheet supplied with the instrument for this informa tion The minimum pulse width is 5 microseconds a repetition rate
120. is re sulting noise signal can easily be much greater than the true ripple developed between the output terminals of the power supply and can completely invalidate the measurement To minimize the ef fects of ground current flow the DVS and test in struments in all ripple and noise measurements should be plugged into the same ac power buss whenever possible 5 29 Peak to Peak Measurements The same ground current and pickup problems exist if 05 cilloscope is substituted in place of the rms volt meter in the peak to peak measurements How ever the oscilloscope display unlike the true rms meter reading tells the observer immedietely whether the fundamental period of the signal dis played is 8 3 milliseconds 1 120Hz or 16 7 mii liseconds 1 60Hz Since the fundamental ripple frequency present on the output of an HP supply is 120Hz due to full wave rectification an oscillo scope display showing a 120Hz fundamental com ponent is indicative of a clean measurement setup while the presence of a 60Hz fundamental usually means that an improved setup will result in a more accurate and lower value of measured ripple To verify that the oscilloscope is not dis playing ripple that is induced in the leads or picked up from the grounds the scope lead should be shorted to the scope lead at the power sup ply terminals The ripple value obtained when the leads are shorted should be subtracted from the actual ripple m
121. istive Network D to A Converter Plug In Board NOT USED fxd ceramic 001uP 500Vdc fxd ceramic 005 4F 100V Diode Si 200mA 75V S5 NPN Si SS 51 SS NPN Si fxd 3 3 5 1 2W fxd comp 12Kn 259 1 2W comp 2 2 5 1 2W fxd comp 10Ka 45 1 2W Same as A3A2 fxd ceramic 001 500Vdc ceramic 005 100V Diode 51 200mA 75V SS NPN Si SS PNP Si SS NPN 91 xd comp 3 3Ka 5 1 2W fxd comp 10 259 1 2W fxd comp 2 2 596 1 2W fxd comp 10 4595 1 2W fxd comp 33Ka 596 1 2W Ref Amp 6 8V 5 TC 2 000598 fxd ww Part of 5080 7139 fxd film Part of 5080 7139 fxd film Part of 5080 7139 fxd film Part of 5080 7139 92 ft BO CO NN e GO e CS RS p pe 1854 0071 0683 1025 0683 4725 0683 1025 0683 2015 0757 0453 0683 5125 0683 5115 0683 2025 0683 1025 3101 0932 1820 0054 1820 0261 2305RA 11115 28480 CB 1025 01121 4725 01121 CB 1025 01121 CB 2015 0132 28480 CB 5125 01121 5115 01121 CB 2025 01121 1025 01121 28480 Refer to proper Option Appendix 28480 SN13617 01295 28480 1810 0041 Refer to proper Option Appendix 28480 28480 28480 28480 28480 28480 28480 01121 01121 01121 01121 EB 3325 EB 1235 EB 2225 EB 1035 28480 28480 28480 26480 2
122. l b Level detector not working Check A6Q17 for open 6018 for short Logic level 1 Variable delay A6Q16 probably working go to Step 8 Check TP17 a Logic level 1 b Voltage magnitude 40 5V b Check A6Q16 for short 5 24 Table 5 10 Unable to Current Latch at Latch Settings Continued NOTE Logic level 1 equals a positive voltage logic level 0 equals approximately OV CONCLUSION a to Step 9 ACTION RESPONSE Check TP35 and TP36 Both logic level H 1 b Either equals ap proxim at ely 1 3 V en CR2 or VR2 open and CR2 open go to Step 9 Both equal mately 13V Connect voltmeter common to TP99 and check 5 a Current sampling circuit oper ating properly goto Step 10 Voltage magnitude equals 0 625 10 b Check current sampling resis tor and interconnections b Voltage magnitude not equal 0 625V 10 a Voltage equals a Current latch decoder operating 0 625V 410 properly Check the negative cur rent comparator 624 R31 R33 R39 Proceed to Step 11 500mA With volt meter common connect ed 99 NEG REP 5 Voltage does not b Check current latch decoder equal 0 625V 410 see paragraph 5 63 Ch
123. lag enable signal is sent to the voltage processing circuits which in turn issues a flag output to the computer 4 14 Voltage Range Processing The voltage range data input is stored and then sent as a voltage range select signal to control the power amplifier range relays With the relays energized the voltage program input signal is multiplied by 1 1 range With the relays deenergized the voltage magnitude is multiplied by 10 X10 range Similar to current overload condition a range flag enable and then a flag signal is issued when ever a voltage range change occurs 4 15 POWER AMPLIFIER 4 16 The power amplifier amplifies the bi polar voltage magnitude input current to provide a bi polar output voltage across the load connected between the HI and LO output terminals An ex ternal analog input signal can also be applied to the power amplifier A signal applied to the analog input terminal is summed with the voltage magni tude signal from voltage processing For this condition the power amplifier amplifies the sum these signals Shunt feedback is employed to prevent changes in the output voltage without change in the input signal Additional feedback networks are used within the amplifier stages for Stability purposes 4 17 mentioned previously the amplifier cir cuits multiply the current input signal by X1 or X10 depending on the status of the voltage range input from the voltage range pr
124. lar manner 4 126 The remaining components of the bias net works improve general circuit operation Diodes through CR40 protect the base emitter junc tions of the input bias transistors from becoming excessively reverse biased resistors R104 R105 R206 R108 RIOS R111 R112 R113 R119 R122 and R130 offset undesirable leakage currents and capacitors C13 14 C15 and C17 permit the circuit to respond to rapid changes in programmed output voltage 4 127 Gross Current Limit Comparators The posi tive and negative current limit comparators protect the output transistors of the power amplifier by limiting the maximum output current to a safe level for both source and sink conditions The output current for normal source conditions is limited to a fixed maximum of 0 55A for sink conditions the maximum current is a linear variable ranging from 0 25A at 100V at HI output terminal to 0 55A at Because the two current limiters are so similar only one the positive limiter is described in detail 4 128 When the output current is within specified limits transistor O21 is biased on 022 and 023 are cutoff and diode CR23 is reverse biased Un der these conditions the limiter has no effect on the output current Zener diode VR12 together with resistors R46 and R47 form a bias network that holds the base voltage of Q22 slightly more posi tive than the base voltage of Q21 and thus lishes a positive c
125. lifier from the output power stages by strapping 706 base to emitter 11 Simulate the output of the feedback dif ferential amplifier by connecting a 100Ka potenti ometer set to mid position between the collector of A7Q6 and UD 12 Slowly rotate the potentiometer shaft cw and ccw while observing the output voltage 13 Ifthe output voltage tracks the potenti ometer settings indicating that the output power stages are normal and the original trouble was locked down condition proceed to 5 14 14 Ifthe voltage tracks the potentiometer settings and the original trouble was a locked up condition proceed to Table 5 15 15 Ifthe output voltage does not respond to the potentiometer settings check the power ampli fier A7Q7 and Q10 through Q13 the bias networks 47014 through Q17 and Q30 through Q33 and the output drivers Q1 through Q6 16 Remove the strap and potentiometer from A7Q6 Table 5 13 Gross Current Limiters Troubleshooting 1 With the load removed from the DVS the output programmed for OV and the gross current lim iters disconnected from the base of A7Q6 monitor the voltage at the anode of A7CR36 Monitor the voltage at the cathode of A7CR23 Again monitor the voltage at the anode A7CR36 but this time connect 1002 50 watt load and increase output to a positive level sufficient to draw 550mA STEP ACTION RESPONSE 6 1 4 Monitored voltage
126. ll reset the current latch circuit and re turn the unit to normal operation 3 27 In addition to the current limits described above the current limit circuits also protect the DVS from active loads that force energy back into the DVS sink condition This can appeer as cur rent flow into the HI output terminal when the terminal is positive or current flow out of the terminal when it is negative Figure 3 6 shows the normal operating locus of the DVS shown the DVS will limit the sink current to value rang ing linearly from 0 25 at 100V to 0 55 at OV Figure 3 6 6131C Output Ranges CAUTION Externally applied terminal to ter voltage in excess of 110 will damage the DVS 3 28 Current Latch Programming current latch data bits L22 30mA L23 50mA and L24 range from the computer form a 3 bit binary code to program the DVS current latch value The states of the 30mA and 50mA bits determine the basic value the state of the range bit multiplies that value by 1 or 10 The three current latch bits provide a maximum of eight possible com binations As shown in the following chart only six of the bit combinations are utilized 20 50 70 100 200 and 500mA for Model 6131 If the pocket programmer is used to program current latch refer to the associated manual 3 29 CURRENT OVERLOAD AND LATCH 3 30 If the output current exceeds the value of the programmed current latch a 10
127. mitter resistor R81 Coupling capacitor C11 charges up to nearly 15V through conducting transistor 027 When a range change occurs a positive going transition is received from the range pulse gener ator The multivibrator now is driven into its un stable state with Q26 on and Q27 Q28 off It remains in the unstable state for approximately 2msec until C11 discharges through R82 and R83 sufficiently to allow the conduction of 028 The range flag enable output is coupled to the flag out put circuit Sheet 1 via OR gate diode AGCR16 4 114 POWER AMPLIFIER See Figure 7 2 Sheet 3 4 115 Feedback Differential Amplifier This cir cuit consists of three differential amplifier stages followed by a single ended stage The first two stages A7Q1 and A7Q2 each consist of two sili con transistors housed in a single package The transistors have matched characteristics to mini mize differential voltages due to mismatching or thermal drift 4 116 Diodes A7CR3 and A7CR4 protect the input stage from being overdriven by excessive inputs from the D A Converter and or the external analog input Voltage divider A7R1 R2 and R3 connected to the base of the input stage provides a zero reference bias with no applied input signal The voltage magnitude input from the D A conver teris summed with the external analog input and the resultant analog current applied to the base of the differential amplifier input stage col lec
128. mon 3 and 1 10 of the bit to be tested Toggle the input bit There should be two logic levels at TP10 If there are not look for a problem in the programming source or its connector in the A1 board connector or in the input bias circuit b Toggle the input bit while observing the voltage between common 4 and 1 13 There should be two logic levels If the voltage is zero check for an open 1 or 2 board connector or an open resistor in 277 or A228 If the voltage re mains near zero or about 5 volts the problem is on the Al board either in the input bias circuit or the isolator circuit For isolator circuit trouble shooting instructions see paragraph 5 53 C To check for problems on the A2 board switch to STORAGE DISABLE and check the voltage between 2 97 or A2TP51 for the sign bit and common 4 while toggling the input bit If there are not two logic levels the storage is probably defective But first check for a high logic level at 2 9 i this level is low a storage disable circuit fault is indicated see paragraph 5 51 If TP97 does exhibit two logic levels the fault has been isolated to the A3 board See paragraph 5 50 for A3 board troubleshooting instructions been isolated to the A3 boatd first check the three voltages that are regulated on that board All voltage measurements on A3 are referenced to com mon 2 a Measure the outputs of the 421 5 volt 16 384
129. mpedance of approximately 20 in series with the high out put terminal The output current is limited to be tween 0 and approximately 10mA depending on the programmed output voltage and the type of load 4 48 Qross Current Limit The positive and nega tive gross current limit comparators provide addi tional current limit protection They are fixed to operate at the maximum current limit of approxi mately 0 55 providing protection for the DVS and the load during the variable current latch delay period or in the event of failures in the current latch circuit 4 49 The comparators each monitor the voltage drop across the current sampling resistor Since the IR drop across the sampling resistance varies in proportion to the output current both compara tors effectively monitor the output current of the DVS The use of two comparators allows sampling of output current flowing in either direction with the negative gross current limit comparator ing negative output currents and the positive com parator monitoring positive output currents For normal source currents below the 0 55A threshold the comparators are biased below cutoff and do not influence amplifier operation However if the gross current limit threshold is exceeded the ap propriate comparator conducts sending gross cur rent limit signal to the coupling amplifier This signal turns down the coupling amplifier and hence the power amplifier pre
130. mum gross limit and a programmable current limit referred to as current latch on this unit Each current limit is controlled independently by a separate circuit The gross current limit circuit is fixed to activate at approximately 110 of the rated output current approximately 0 55A adjustable current latch circuit can be programmed to 20 50 70 100 200 and 500mA Current latch input data consist of three lines L22 30mA L23 50mA 1 24 range or X10 three inputs are stored in the DVS when the gate Signal is received As shown in Figure 3 4 the current latch data must remain for at least 10usec after the triggering edge of the gate The flag signal is sent to the computer 55ysec after the gate to indicate that current latch processing is complete 3 26 If the overload condition persists for a tain variable delay period the current latch cir cuit is activated and the output current is reduced to from 0 to 10mA depending on the type of load connected to the unit The output voltage under current latch conditions depends on the programmed output voltage and the type of load With a full resistive load connected to the unit the output voltage and current are reduced to nearly zero At no load the output voltage will correspond to the programmed voltage up to a maximum of 40 volts After the load current is reduced or the current latch increased the next gate that is ceived wi
131. n the output leads Since this noise signal will have an amplitude of approximately 100mV it is recommended that the above capacitor be utilized 3 41 CURRENT MONITOR 3 42 The CURRENT MONITOR terminals Figure 3 8 can be used to monitor the output current of the DVS without affecting the output voltage To mon itor the output current a DVM is connected across the CURRENT MONITOR and LO terminals output voltage reading is proportional to the cur rent output in the ratio of 1 volt 1 ampere output current With a positive output programmed through a resistive load the LO terminal is positive with respect to the HI terminal The accuracy of the CURRENT MONITOR reading is 3 For example a reading of 250mV indicates that the DVS output current is 250 47 5mA 2 3 43 ANALOG INPUT 3 44 The ANLGIN terminal 3 8 can be used to program the output of the DVS with an ana log input The analog input signal can be a dc level or a variable signal a sinewave for instance The analog input signal is connected between the ANLG IN and LO 5 terminals 3 45 The analog input is summed with the digital voltage magnitude data after it is converted to its equivalent analog current at the input to the DVS power amplifier The result of the summation is used to drive the power amplifier which produces the specified output voltage Since the power amplifier inverts its input the analog input voltage must be of oppo
132. nd scope case Before using a differen tial input scope in this manner however it is imperative that the common mode rejection capa bility of the scope be verified by shorting to gether its two input leads at the power supply and observing the trace on the CRT If this trace is a straight line then the scope is properly ig noring any common mode signal present If this trace is not a straight line then the scope is not rejecting the ground signal and must be realigned in accordance with the manufacturer s instructions until proper common mode rejection is attained 5 32 To check the peak to peak ripple and noise output proceed as follows Connect 2005 50W load impedance matching network s and oscilloscope as shown in Figures 5 4A or 5 4 b Strap together terminals Program the output voltage for 100 0 volts d The observed ripple should be less than 7mV p p e Program the voltage range to X1 the out put voltage to 16 3835 volts and change load to 35a 17W The observed ripple should be less than 2mV p p 5 33 Transient Recovery Time Definition The time X for output voltage recovery to within Y milli volts of the nominal output voltage following a Z amp step change in load current where Y is speci fied as 0 12 of full range voltage The nominal output voltage is de fined as the level half way be tween the static output voltage before and after the imposed load change
133. nducts when the threshold is reached biasing Q18 below cutoff The positive going rise on the collector of Q18 is then coupled through limiting diode 9 to set the latching flip flop When current latch commences the Schmitt trigger input goes negative cutting off Q17 and returning the circuit to its original stage The latching flip flop remains in the set state however because diode CR9 blocks the negative going excursion of the collector of Q18 4 102 Latching Flip Flop Transistors Q19 and Q20 are connected in a bi stable multivibrator configuration When the DVS is not in a current latch condition the flip flop is in the reset state with Q19 off and Q20 on Reset is initiated by a short duration negative pulse applied to the base of Q20 by reset amplifier Q24 The reset pulse is generated 3usec after the application of a gate in put from the computer The leading edge of the 50usec wide input from input board Al cuts off Q22 The output of 022 is differentiated by A6C4 and 2 and the positive going spike that occurs at the leading edge of the input is inverted by Q24 and then used to turn on Q20 4 103 A current latch condition is initiated by a positive going transition applied to the base of Q20 from the collector of Q18 This sets the flip flop by turning Q20 off causing Q19 to tum on The flip flop remains in the set state until a gate pulse is rec ived from the computer and a reset pulse is generated 024 4
134. nnection for 230Vac Operation ly from either nominal 115 volt or 230 volt 48 440Hz power source unit as shipped from the factory is wired for 115 volt operation The input power required when operated from a 115 voit power source at full load is 1 2 amperes 100 watts 2 20 CONNECTIONS FOR 230 VOLT OPERATION Figure 2 2 2 21 Normally the primary windings of input transformers T2 and T3 are connected in parallel for operation from a 115 volt source convert the unit to operate from a 230 volt source the primary windings of each transformer must be con nected in series as follows Unplug line cord and remove top cover b Looking from the rear of unit locate the 115 jumpers between terminals 1 3 and 2 4 of transformer T3 see Figure 2 2 Remove both 115 jumpers and solder the 230Vac jumper between terminals 2 and 3 of transformer T3 as shown in Figure 2 2 d Replace existing fuse on rear panel with 1 ampere 230V fuse 2 22 POWER CABLE 2 23 To protect operating personnel the National Electrical Manufacturers Association NEMA rec ommends that the instrument panel and cabinet be grounded This instrument is equipped with a three conductor power cable third conductor is the ground conductor and when the cable is plugged into an appropriate receptacle the instru ment is grounded The offset pin on the power cable s three prong connector is the ground con nection 2
135. not im mediately associated with an assembly 6 3 ORDERING INFORMATION 6 4 order a replacement part address order inquiry to your local Hewlett Packard sales office see lists at rear of this manual for addresses Specify the following information for each part Model complete serialnumber and any Option or Special modification 0 numbers of the instrument Hewlett Packard part number circuit reference des ignator and description order a part not listed in Table 6 4 give a complete description of the part its function and its location s Table 6 1 Reference Designators miscellaneous electronic part fuse jack jumper relay inductor meter assembly blower fan capacitor circuit breaker diode device signal ing lamp 6 1 Table 6 1 MI HP D vw m plug transistor resistor switch transformer terminal block thermal switch Table 6 2 A ampere ac alternating current assy assembly bd board bkt bracket degree Centigrade cd Card coef coefficient comp composition CRT cathode ray tube CT center tapped dc direct current DPDT double pole double throw DPST double pole single throw elect electrolytic encap encapsulated F z farad degree Farenheit fxd fixed Ge germanium H Henry Hz Hertz IC lt integrated circuit ID inside diameter incnd incandescent k kilo 103 m
136. not vary from the reading recorded in Step 4 by more than 500 n Program the output voltage sign to neg ative Perform f through h The reading on the voltmeter should not vary fromthe reading recorded in Step a by more than 500 5 20 Temperature Coefficient Definition The change in output volt age per degree Centigrade change in the ambient temperature under condi tions of constant input ac line voltage output voltage setting and load re sistance 5 21 The temperature coefficient of a power sup ply is measured by placing the power supply in an oven and varing the temperature over any span within its rating Most HP power supplies are 5 6 rated for operation from 0 C to 55 C The power supply must be allowed to thermally stabilize for a sufficient period of time at each temperature of measurement usually 1 2 hour 5 22 To check the temperature coefficient pro ceed as follows a Connect test setup shown in Figure 5 1 b Strap CT terminals and program the out put voltage to 100 00 volts Gate the unit c insert the power supply into the temper ature controlled oven voltmeter and load resis tance remain outside oven Get the temperature to 30 C and allow 30 minutes warm up Record the voltmeter indication e Raise the temperature to 40 C and allow 30 minutes warm up f The voltmeter indication should change by less than 16mV from indication recorded in Step d
137. ny voltage bits are not functioning calibration can not be accomplished refer to troubleshooting procedures paragraph 5 37 If all voltage bits are functioning proceed as follows 0 5 MILLIVOLT CALIBRATION a Turn DVS off Remove bottom cover in order to gain access to potentiometer A7R9 Note that if the DVS is installed in a system both the A3 and A7 boards must be placed in extender boards to perform this calibration b Set all of the potentiometers on the board A3R18 A3R36 A3R52 through A3R59 and A3R100 to midrange Set the data and sign bit switches on the Programmer for an output of 0 5mV d Turn on DVS and momentarily depress GATE switch the programmer Allow a 30 minute DVS warm up period CAUTION High voltages are present on the amplifier board A7 Set the RANGE switch on the Programmer to the X10 position and measure the output voltage Set the RANGE switch to the X1 position and adjust A7R9 until a reading 1 10 the reading in step e is obtained g Repeat steps and f until no further adjustments are needed Setthe RANGE switch to 10 posi tion and adjust A3R100 for a reading of 5mV lmV i Repeat steps e through h until no further adjustments are needed POSITIVE 16 384 VOLT REFERENCE ADJUST j On the Programmer set the RANGE switch to and the OUTPUT SIGN switch for negative 5 32 polarity k Connect a digital voltmeter acro
138. o TP18 Impedance 1Ka terminals on barrier strip are shorted or electrolytic capacitor used is connected with reverse polarity b Impedance lt IKa a Check completed Problem caus d by improper setting of current latch value or current Latch not calibrated see paragraph 5 79 a Output current lt 20 Short the output ter minals and turn unit on Program the current latch and voltage mag nitude values in question then Gate unit b Latch circuits not working go to Step 3 Output current 21009 of rated out put a Current latch circuits on A6 board operating properly check current latch circuit on A7 board see paragraph 5 67 Connect meter common Logic level 1 to 2 and check TP21 b latch circuits not working go to Step 4 b Logic level 0 a Buffer stage A6Q21 probably working go to Step 5 Check TP20 a Logic level 1 b Check Buffer Stage 6021 for short b Voltage magnitude equals approximately 5V Latching flip flop probably working 90 to Step 6 Check TP19 Logic line b Check latching transistor A6Q20 for short any A6C5 for opens Logic ievel 1 a Level detector 6017 O18 probably working go to Step y n Check TP18 Logic leve
139. ocedures thus are divided into two categories according to fault symptoms The symptoms listed in Table 5 3 can be related to these two categories 5 67 Current Latch Troubleshooting Current latch problems on the A7 board can be caused by the current latch circuits themselves the current latch isolators and switch circuits or subsequent circuits including the power amplifier power out put or positive and negative bias circuits Figure 5 presents a procedure for dividing the fault path between either the A7 current latch circuits or the power circuits If this procedure indicates the fault is in the current latch circuits Figure A DETERMINE IF FAULT IS IN A LATCH CIRCUITS OR IN POWER AMPLIFIER POWER QUTPUT POSITIVE NEGATIVE BIAS CIRCUITS CONNECT 508 LOAD ACROSS OVS OUTPUT 1 METER METER READINGS TROUBLE 15 IN METER BETWEEN TEST SET UP READS READS YES TURN CORECT BETWEEN POWER AMPLIFIER AND COMPLETE 0 08V Yrs OFF DVS LEAR YES POSITI To NS ZEN 4 gt OUTPUT 08 POSITIVE 7 is OR NEGATIVE BIAS TOGGLE NO CONNECT VOLT 4 PROGRAM DYS TURN ON GATE METER BETWEEN CIRCUITS FOR OVOLTS DVS SWITCH 79 AND 85 aj mL EET 4 te REPEAT STEPS 14 AND 5 7 CHECK 26V SUPPLY AT TROUBLE IS iN CURRENT LATCH
140. ocessing circuit 4 18 The power amplifier includes a self con tained gross current limit circuit which is fixed to activate at 11096 maximum of the rated output current When activated the gross current limit circuit limits the conduction of the power amplifier preventing the output current from exceeding the maximum current limit value 4 19 Additional protection for the load is pro vided by a circuit which shorts the output of the amplifier whenever input power is interrupted or the input cable from the computer is disconnected 4 20 POWER DISTRIBUTION 4 21 Power distribution circuits accept 115 volts or 230 volts single phase 60 input power and provide unregulated dc bias voltage outputs to the three major circuits Additional regulated bias voltages are generated by reference supplies and voltage regulators in voltage processing and the power amplifier Overload protection is provided by a fuse in the input circuit The delayed 12 volt output to the power amplifier provides protection of the output load by keeping the amplifier output shorted until the internal bias supplies within the DVS have stabilized 4 22 DETAILED BLOCK DIAGRAM DISCUSSION 4 23 Figure 7 1 is a detailed block diagram of the Digital Voltage Source showing each stage or group of stages within each of the three major cir cuits The major circuits are bracketed by heavy weight lines and sheet numbers are provided to cor relate this drawing with
141. of this diagram with the schematic Sheets at the rear of the manual 4 5 The Digital Voltage Source is a digital to analog link capable of providing an accurately settable source of dc or low frequency power It provides 16 384 to 16 3835 volts in 0 5mV steps or 100 to 100 volts in 5mV steps at 0 to 0 from dc to 25k Hz Current limit protection is provided by a current latch circuit which can be programmed to activate at one of six values rang ing from 20mA to 500mA Back up protection is provided by a gross current limit circuit which pre vents the output current from exceeding 110 max imum of the rated output current 4 6 VOLTAGE PROCESSING 4 7 The voltage processing circuits interface isolete store and convert to analog form the digital input data representing the magnitude and sign of the required output voltage The input cir cuits adapt the DVS to the requirements of the dri ver circuits to be used and provide dc isolation between the computer ground and the DVS output Integrated circuits store the received data and a digital to analog converter translates the stored data to a bi polar analog current This bi polar analog current signal controls the output of the power amplifier 4 8 The input gate signal initiates timing and Storage functions for both the voltage processing and current latch and voltage range processing cir cuits The storage function allows the voltage processing circ
142. oltage magnitude switches might either be up open circuit or down grounded to program zeros Similarly the OUTPUT SIGN switch might be up or down to program a positive output Refer to the appropriate Option Appendix or the Instrument Modification Sheet supplied with the instrument being programmed for digital input coding infor mation Set the I LIMIT switches for a 500mA REQUIRED TYPE CHARACTERISTICS USE Diff or Dig Voltmeter Measure dc voltages cali bration procedures MENDED MODEL HP 3462 3490 or 3420 Vary ac input Measure programming time Display transient response waveforms and p p noise Measure dc voltages Measure transient response Power supply load resistors Check current latch perfor mance E Provide input to ANLG IN terminals on DVS Measure rms ripple and noise Supply digital program inputs HP 180A plus 1801A 1805A and 1821A Plug ins HP 412A See Figure 5 5 HP 33104 B HP 6215A HP 3400A HP Pocket Program mer 1433B current limit 4 Open the front access door and put the STORAGE DISABLE switch on the A2 board in the STORAGE DISABLE position 9 Connect the line and switch the LINE switch to ON The STORAGE DISABLE light will come on and the front panel meters will both indicate zero Select the 20V and 06A meter ranges CURRENT LATCH
143. or negative generates a negative go ing current overload signal to turn on the appropri ate OR gate diode CRI or CR2 The polarity of the output current determines which of the comparators is activated The positive current comparator Z4 R32 R34 43 is activated for positive output cur rents to monitor the difference between the out put and latch reference current The current samp ling signal J6 N is one input to the positive cur rent comparator and the positive reference signal is the other input The positive reference signal is developed by the negative reference inverter Z3 and Q23 For excessive positive output currents the positive current comparator generates a nega tive going output signal causing CR2 to conduct The negative current comparator 74 R31 R33 R39 is activated for negative output currents to monitor the difference between the output and latch reference currents The current sampling s gnal is one input to the negative current comparator and the negative reference signal is the other input Por excessive negative output currents the nega tive current comparator generates a negative going signal causing to conduct With or CR2 conducting an overload signal is passed to the current latch and current overioad circuits 4 98 Current Latch Circuits If a current over load signal is generated these circuits generate current latch signal which turns off the power am plifier The latc
144. over Ohio Saugerties N Y RCL Electronics Inc Amerock Corp Sparta Mig Co Ferroxcube Corp Fenwal Laboratories Morton Grove Amphenol Corp Broadview Radio Corp of America Solid State and Receiving Tube Div Somerville N J Semiconductor Products Syracuse N Y Eldema Corp Compton Calif Transitron Electronic Corp Wakefield Mass Pyrofilm Resistor Co Inc Cedar Knolls N J Arrow Hart and Hegeman Electric Co Hartford Conn ADC Electronics Inc Harbor City Calif Caddell amp Burns Inc Mineola N Y Hewlett Packard Co Paio Alto Div Palo Alto Calif Motorola Semiconductor Prod Inc Phoenix Arizona Westinghouse Electric Corp Semiconductor Dept Youngwood Pa Ultronix Inc Grand Junction Colo Wakefield Engr Inc Wakeiield Mass General Elect Co Electronic Capacitor amp Battery Dept Irmo S C Bassik Div Stewart Warner Corp Bridgeport Conn IRC Div of TRW Inc Semiconductor Plant Lynn Mass Amatom Electronic Hardware Co Inc New Rochelle N Y Beede Electrical Instrument Co Penacook N H General Devices Inc Indianapolis Ind semcor Div Components Inc Phoenix Arizona Robinson Nugent Inc New Albany Ind Torrington Mfg Co West Div Van Nuys Calif Transistor Electronics Corp Minneapolis Minn CODE NO 07138 07263 07387 07397 07716 07910 07933 08484 08530 08717 08730 08806 08863 08919 09021 09182
145. ow line 1096 less than nominal to high line 109 more than nominal or high line to low line 5 19 Line regulation should be checked in both the higher X10 range with both negative and pos itive output voltages and the lower X1 range with both positive and negative output voltages since any one of these four conditions can yield an un satisfactory result which is not reflected under the other three conditions To test the line regu lation for all four conditions proceed as follows test setup shown in Figure 5 1 Set the METER switch to the highest voltage and current ranges b Connect variable auto transformer be tween input power source and power supply 115Vac input C Strap terminals together d Program the output voltage to 100 0 volts e Program the output voltage sign to pos itive f Adjust variable auto transformer for low line 104Vac Gate the unit g Read and record voltage indicated on voltmeter Adjust variable auto transformer for high line 126Vac Gate the unit i Reading on differential voltmeter should not vary from reading recorded in Step g by more than 5mV Program the output voltage sign to neg ative Perform Steps f through i k Program the output voltage to 16 3835Vdc Xl range Change to 35a 17W 1 Program the output voltage sign to posi tive Perform Steps f through The reading on the voltmeter should
146. ower transistors A4C5 C20 C22 CR11 CR13 or RS 4 7 16 17 CR17 CR18 or R7 Defective meter loosely connected 4 1 open or defective A4CR7 shorted Short circuit load Interconnect board 5 open Table 5 3 Overall Troubleshooting Continued SYMPTOM Zero or Low Output Voltage Continued Unable to program output voltage or actual output does not coincide with programmed input Able to program only a few voltages of each polarity Able to program at least some negative output voltages within the rating of the supply but no positive output voltages Able to program at least some positive output voltages within the rating of the supply but no negative output voltages Able to program all but a few voltages of each polarity Programmable current latch defective or unable to get unit out of current latch Unit locked up high positive output or locked down high negative output Flag or gate pulse not being generated Unable to program voitage range Programmable current latch defective unable to program Some values Unable to get unit out of current latch or unable to get unit into current latch PROBABLE CAUSE Input connector P1 loosely connected Defective board or unit in latch par agraph 5 46 Meter circuit defective Flag or gate pulse not generated par agraph 5 57
147. p 104 5 5 W EB 1005 01121 0686 1005 R54 fxd comp 5 1Ka 5 5 W EB 5125 01121 0686 5125 855 fxd comp 1004 259 1015 01121 0686 1015 R56 fxd comp 2 4596 EB 2025 01121 0686 2025 REF MFR HP d DESIG DESCRIPTION MFR PART NO CODE PART NO 7857 fxd film 221Ka 196 1 8W Type CEA T 0 07716 0757 0473 R58 fxd film 8254 1 1 8W Type CEA T 0 07716 0757 0421 R59 fxd film 7 5Ka 1 1 8W Type CEA T 0 07716 0757 0440 R60 fxd comp 27 595 iw EB 2735 01121 0686 2735 R61 NOT ASSIGNED R62 fxd comp 1 3Ka 45 IW GB 1325 01121 0689 1325 R63 fxd comp 1 5 5 EB 1525 01121 0686 1525 R64 fxd comp 4 3Ka 5 1 W EB 4325 01121 0686 4325 R65 fxd comp 1 5Ka 5 iW EB 1525 01121 0686 1525 R66 NOT ASSIGNED R67 fxd comp l0Ka 5 W EB 1035 01121 0686 1035 R68 fxd 27Ka 5 W EB 2735 01121 0686 2735 R69 fxd comp 39Ka 5 1 W EB 3935 01121 0686 3935 R70 fxd comp 1504 5 W EB 1515 01121 0686 1515 R71 fxd comp 4 3Kn 45 4 W 4325 01121 0686 4325 R72 fxd comp l0Ka 5 1 W EB 1035 01121 0686 1035 R73 fxd comp 4 3Ka 259 4 W EB 4325 01121 0686 4325 R74 fxd comp 7502 5 3 W EB 7515 01121 0686 7515 R75 fxd comp 7 5 595 2 W EB 7525 01121 0686 7525 R76 fxd comp 560a 5 5 EB 5615 01121 0686 5615 R77 fxd film 6 2Ka 1 1 8W Type CEA T 0 07716 0698 5087 R78 fxd film 4 53 1 1 8W Type CEA T 0 07716 0698 4443 R79 fxd comp 4 3Ka 55
148. plifier stages 6029 and 6030 The collector stage of each amplifier contains a differentiating network C13 R95 and C14 R94 and a limiting diode CR14 and CR15 The limiting diodes con duct only the positive excursion of the differen tiated waveform from the respective collector These diodes also serve as part of the flag enable OR gate along with 6 16 which receives the voltage range flag The first output pulse from the overload flag generator is obtained from the collector of 029 It is initiated by the negative going overload signal begin current overload which turns off Q29 tums Q30 on This causes a negative voltage change at the collector of Q30 and a positive change at the collector of Q29 The positive portion of the differentiated Q29 output is conducted by CR14 while the nagative portion of this waveform and the output of Q30 are blocked The component values of the differentiating net work determine the 10usec width of the conducted pulse The trailing edge begin current latch of the overload signal turns 029 on and Q30 off resulting a second 10 pulse at TP33 through 5 This pulse is obtained from the collector of Q30 and is a replica of the first overload pulse 4 108 Figure 4 7 illustrates the output pulses ob tained from the flag generator TP33 for a current latch delay of 20usec Because the output pulses from the flag generator have fixed width of 10usec the output waveforms at
149. porite Inc Union City 70901 Beemer Engrg Co Fort Washington 70903 Beiden Corp Chicago Ill 71218 Bud Radio Inc Willoughby Ohio 71279 Cambridge Thermionic Corp Cambridge Mass Bussmann Div of McGraw amp Edison Co St Louis Mo CTS Corp Eikhart Ind I T T Cannon Electric Inc Los ngeles Calif 71400 71450 71468 Globe Union Inc Centralab Div Milwaukee Wis General Cable Corp Cornish Wire Div Williamstown Mass Coto Coil Co Inc Providence RL Chicago Miniature Lamp Works Chicago Cinch Mfg Co and Howard B Jones Div Chicago Dow Corning Corp Midland Mich Electro Motive Co Inc Willimantic Conn Brooklyn General Instrument Corp Newark N Drake Mfg Co Harwood Heights Ill Elastic Stop Nut Div of Amerace Esna Corp Union N Erie Technological Products Inc Erie Pa Hart Mfg Co Hartford Conn Beckman Instruments Inc Helipot Div Fullerton Calif Fenwal Inc Ashland Mass Hughes Aircraft Co Electron Dynamics Div Torrance Calif Amperex Electronic Corp Hicksville Y Bradley Semiconductor Corp New Haven Conn Carling Electric Inc Hartford Conn Federal Screw Products Inc Chicago lll Heinemann Electric Co Trenton N J Hubbell Harvey Inc Bridgeport Conn Amphenol Corp Amphenol RF Div Danbury Conn E F Johnson Waseca Minn IRC Div
150. pping pattern shown in Figure 3 8 The power supply should be turned off before changing strapping patterns The leads from the sensing terminals to the load will carry much less current than the load leads and it is not required that these leads be as heavy as the load leads However they should be twisted or shielded to minimize noise pickup Remote sensing leads longer than 15 feet may have high frequency resonances which can cause the power supply to oscillate Tf long leads are anticipated consult your local Hewlett Packard Sales Engineer for techniques to eliminate oscillation 3 38 Note that it is desirable to minimize the voltage drop the load leads and it is recommend ed that the drop not exceed 1 volt per lead if the power supply is to meet its dc specifications If a larger drop must be tolerated please consult an HP Sales Engineer CURRENT MONITOR ANLG IN HLS Hi Figure 3 8 Remote S nsing Strapping Pattern 3 39 Grounding Proper grounding will greatly re duce output ripple and noise It is recommended that the LO output terminal be connected to the GND terminal HI output terminal should not be connected to GND during normal operation 3 40 the output terminals must be floated at some dc potential a capacitor between 0 05 and 0 luf should be connected between the LO and GND terminals If the above capacitor is not con nected a common mode noise signal will be induc ed i
151. present When this has been established toggle the input bit and observe the collector volt age of the transistor that immediately follows the photo isolator package Q2 of Figure 5 8 The choice of which table should be used depends the results of that test If the collector of that transistor remains at a logical high when the input bit is toggled begin at step 1 of Table 5 4 that collector remains at a logical low begin at step 1 of Table 5 5 NOTE Marginal photo isolators in the input cir cuits on the Al and boards can cause erroneous output voltage readings and cur rent latch values when operating in the low or high limits of ac input voltage see paragraph 5 16 This can be detected by programming ali photo isolators to turn on then turn on power to the DVS at low line and check the output of each storage flip flop Thus the marginal photo isolation can be detected and replaced Figure 5 8 Representative Isolator Circuit Table 5 4 Photo Isolator Troubleshooting Output Remains High NOTE Refer to Figure 5 8 for component reference designations used in this table PROBABLE STEF ACTION RESPONSE CAUSE Proceed to Step 2 1 Observe voltage between Q2 collector and common Shunt 7 pin 4 to pin 5 momentarily with lKa resistor a Two logic levels present 0 Q2 opened Repiace Q2 and retest entire isolator stage If output now remains
152. provided by cur rent latch circuit which can be externally or in ternally programmed to one of six values between 4 and 100 of the units rated output current When activated the current latch circuit turns off the output power amplifier reducing the output cur rent to less than 10 reaction time of the current latch circuit time between the start of a current overload and turn off of the power ampli fier can be adjusted by adding an external capac itor at the rear terminals upper current limit is safeguarded by a separate fixed current limit circuit that prevents the output current from ex ceeding 11096 of the current rating The computer is continuously informed of possible current load or current latch conditions by status outputs which are fed back to the user s source 1 6 For maximum reliability and minimum size and weight the DVS utilizes solid state cir cuitry Most of the DVS circuitry is contained on five removable plug in circuit boards accessible from the front of the unit through an access door 1 7 displayed on two front panel meters Output voltage current are continuously The front panel METER RANGE switches select the desired voltage and current ranges 1 8 The DVS also limits sink current resulting from an active load forcing energy back into the DVS to value between 0 25 and 0 55 as function of sink voltage magnitude 1 9 Term
153. put voltmeter reads or ohmmeter reads 0 ohms See following chart CURRENT OVER LOAD OCCURS BETWEEN Volts CURRENT I LATCH SWITCH LATCH POSITIONS mA L24 122 up 3 8 and 4 2 9 5 and 10 5 13 3 and 14 7 19 and 21 38 and 42 95 and 105 down up up down down down up up down down up 35 Change the programmable current latch I LATCH value and output voltage at which cur 5 4 rent overload occurs to the values listed the chart and repeat step 34 36 Set the OUTPUT SIGN switch to negative and repeat steps 34 and 35 CURRENT LATCH CHECK 37 Turn off power to the DVS and remove the jumper between the terminals The 504 load resistor remains connected between the and LO output terminals 38 As in the current overload check step 28 determine the existence of the current latch output transistor pull up resistor 5 If A6A5R8 is used connect a dc voltmeter between the I LATCH STATUS and DATA COM test points on the Programmer If A6A5R8 is not used connect an ohmmeter between these two test points 39 On the Programmer set the current latch I LATCH to 200mA and the voltage magnitude to 81 92V 40 Tum on power to the DVS and press GATE on Programmer instrument should remain in current latch condition voltmeter reads 0 or ohmmeter reads 0 ohms 4l Remove the 200 load resistor from the HI and LO output terminals Unit should remain in latched condition until
154. put Circuits Trouble shooting The following procedure describes the process by which troubles in the current latch data input circuits may be isolated The process con sists of a series of fast checks of the input cir cuits up to and including the storage flip flops 622 5 58 To isolate troubles in the input circuits ceed as follows 1 Connect the common lead of an oscillo scope or logic probe to 3 common 2 the other lead to TP64 of each of the current latch input bits and look for the pre sence of two logic levels as the switch for that bit is toggled If only one logic level is found at TP64 for any of the bits check the programming source for defect 3 Disconnect the leads at TP64 and E and connect them to TP74 of each bit and Check for the two logic levels as described in Step 2 If only one logic level is present for any of the bits check the associated pull up resistor A621 and photo isolator circuit paragraph 5 53 4 Disconnect the lead of the monitoring device of TP74 and connect it to TP75 of each bit Check for the presence of two logic levels as described in Step 2 If two logic levels are not present for any of the bits 621 may be defective See Paragraph 5 59 and 5 60 5 59 Storage Gate Pulse Troubleshooting First determine if the A2 STORAGE DISABLE switch and associated circuits are working by monitoring TP30 Ref 2 while switching from STORAGE to STOR AGE DIS
155. put voltage for any change in line voltage from 104 to 126Vac or 208 to 254V ac Range X10 Range 5mV 500uV Load Effect Load Regulation Change in output voltage for any change in load current within rating X Range 150 X10 Range 500pV Temperature Coefficient Change in output voltage per degree Centigrade change in ambient temperature Range 160pV C X10 Range 1 6mV C PERIODIC AND RANDOM VOLTAGE DEVIATIONS Drift Stability DC output voltage drift under constant line load and ambient temperature for 8 hours after 30 minutes warm up Xl Range X10 Range 5 PARD Ripple and Noise p p rms dc to 50MHz at any line voltage 1 3 Specifications and under any load condition within rating X1 Range 2mV p p 0 5mV rms X10 Range 7mV p p 1 5mV rms Load Transient Recovery Time Time required for the output voltage to recover within 0 19 of full range voltage following a full load current change Xl or X10 Range 150 SPEED Programming Time Maximum time required for the output volt age to settle within 0 19 of the programmed voltage change after simultaneous receipt of data and gate signals with a resistive load connected across the output terminals Xl or X10 Range 300 5 Voltage range change requires 2msec ANALOG INPUT A Impedance lOka 2 19 Maximum Input Voltage Full Range Range 20 X10 Range 10V Bandwidth to 3dB Po
156. r of the unit Under these conditions the current limit is governed solely by the gross current limit circuit which fixes the current limit at about 0 55 amperes Al though the current latch status signal is not gener ated the overload status signal is switched to the overload state if the output current exceeds the programmed current latch value Shorting the C terminals is useful during calibration or trouble shooting when it is desirable to keep the unit out of the current latch mode Ensure that the short ing wire s across the terminals is short less than six inches long The inductance of long wires could cause the current latch circuit to come activated 3 34 Current Latch At Turn On At turn on the output terminals are shorted for approximately 0 2 second This will activate the current latch cir cuitry reducing the output current accordingly After the short is removed from the output terminals a gate input must be received from the computer to reset the latch circuit and return the unit to normal operation 3 35 CONNECTING THE LOAD 3 36 Low sense LO S and high senses Hi S should be connected to LO and respectively as shown in Figure 3 1 3 37 Remote Sensing is used to maintain good regulation at the load and reduce the degradation of regulation which would occur due to the voltage drop in the leads between the power supply and the load Remote sensing is accomplished by utilizing the stra
157. r s agent and notify Hewlett Packard Sales and Service Office as soon as pos Sible If the instrument appears undamaged per form the electrical check given in the following paragraph 2 5 ELECTRICAL CHECK 2 6 Check the electrical performance of the in strument as soon as possible after receipt Section V of this manual contains performance check pro cedures which will verify instrument operation within the specifications stated in Table 1 1 This check is also suitable for incoming quality control inspection Refer to the inside front cover of the manual for the Certification and Warranty state ments 2 7 REPACKING FOR SHIPMENT 2 8 When shipping the entire instrument it is recommended that the package designed for the in strument be used The original packaging material is reusable If it is not available contact your local Hewlett Packard field office to obtain the materials This office will also furnish the ad dress of the nearest service office to which the instrument can be shipped Be sure to attach a tag to the instrument specifying the owner model number full serial number and service required or a brief description of the trouble 2 9 INSTALLATION DATA 2 10 The instrument is shipped ready for bench operation Power connections are made through the power cable supplied with the unit The digi 2 1 tal inputs to control the output voltage current limit etc must be supplied through the data in put pl
158. rminals 3 Connect Pocket Programmer to the data input connector and set its switches as follows Set the INPUT LEVEL REF switch to DATA COM b Set the SOURCE SELECT switch to EXT C Set the MP DCPS switch to DCPS d Set the RANGE switch to X10 e The voltage magnitude bit switches 0 5 through 8192 OUTPUT SIGN switch and I LATCH switches L24 L22 and L23 may be left on either position up or down at this point in the procedure 4 Turn on power apply a GATE pulse to the DVS and measure output voltage Output should be 0 volts 10mV If output is not correct trouble shoot the power amplifier board A7 paragraph 5 64 5 Connect a negative dc voltage V be tween the ANLG IN and LO S terminals on the rear of the DVS Connect polarity to the ANLG IN terminal and polarity to the LO 8 terminal as shown in Figure 5 7A Note that the power am plifier in the DVS inverts this voltage and amplifies it by 1 in the X1 range and by 10 in the X10 range The magnitude of the input maximum of 10V in Power supplies faulty Marginal photo isolators on Al paragraph 5 53 Power Supplies faulty Excessive voltage drop in sensing leads the X10 range depends upon the trouble encount For example if a high range output voltage cannot be programmed apply a high range voltage to the analog input DC POWER SUPPLY DVS UNDER TEST DVS UNDER TEST DC POWER SUPPLY Figure
159. rring to the circuit schematics of Figure 7 2 If the supply voltages are correct or if the supply voltages are incorrect but the components in that supply are not defective proceed to graph 5 45 5 45 Overall Troubleshooting Table After check ing the power supplies disconnect the load and examine Table 5 3 This table contains a list of symptoms and probable causes that may cut down on troubleshooting time For each trouble symptom Table 5 3 isolates the fault to a component or group of components or directs the reader to additional procedures if further isolation of the trouble is necessary Table 5 2 Power Supply Troubleshooting PROBABLY DEFECTIVE METER METER MAXIMUM COMMON POPE NORMAL ROARING RIPPLE P P STONES o d TP84 12 1 5VdC e 4 1 CR2 or R1 86 10 2 0Vdc A4C10 CR22 CR5 CR6 or R27 87 5 0 25 4 CR9 R8 ASC1 C2 21 88 26 4 4 4 19 C21 CR10 CR12 or R4 TPS9 26 4Vdc 90 155 z31Vdc 0 12 A4C8 C12 C13 CR15 CR20 R8 TP93 155 31 0 25V 4 9 11 14 CR14 CR21 R9 140 14Vdo A4C6 C15 C18 CR16 CR19 or R6 NOTE Test points 94 and 95 are 27 TP94 15 0 2V 0 0015V 7 25 026 027 VR5 or CR24 TP95 15 20 9 0 0015 7 24 028 029 CR6 CR25 Table 5 3 Overall Troubleshooting PROBABLE CAUSE Zero or Low Output Voltage Fuseblown Check output p
160. s pulse is inverted by part of A2Z5 in order to obtain the positive going transition TP43 needed to drive another one shot multivibrator A226 4226 is iden tical A123 and 174 except that its timing components are chosen for 2 microsecond output pulse 8 4 72 lf the storage disable switch is in the STORAGE position this 2 microsecond positive pulse is applied to one of the inputs of the OR gate composed of Q1 Q2 and Q3 The output of the OR gate TP9 is a positive 2 microsecond Storage gate to the clock inputs of the voltage magnitude and sign flip flops This output is also inverted by another section of 4275 and sent to the current latch and voltage range processing circuits to control the storage flip flops there The other input of the OR gate is connected to an r c EA differentiating network that produces 20 milli second pulse when the instrument is energized This pulse assures that the A2 and A6 storage flip flops are in the desired initial state 4 73 the storage disable switch is in the STORAGE DISABLE position an input gate does not produce a storage gate The pulse input to the OR gate is disconnected by the switch and Q1 is saturated the current through The continuously high output from Q2 keeps all of the storage flip flops enabled so that data in puts are reflected at the flip flop outputs con tinuously Placing the switch in STORAGE DIS ABLE also lights the STORAGE DISABLE lamp
161. site polarity with respect to the polarity of the desired output voltage The power amplifier amplifies the input signal by 1 in the X1 range and by 10 in the X10 range CAUTION To protect the DVS from damage the combination of digital voltage magni tude data and analog input should not cause the DVS to exceed its rated limits x100Vdc Further regardless of the digital voltage input the analog input in the range should not be greater than 20V nor greater than 210 0 in the X10 range 3 46 The DVS output voltage can be determined by the following formula Vopr Range x Analog Input Digital Program Voltage For ample if a 5 000Vdo output is desired with no digital voltage program input a 5 000Vdc input can be applied to the ANLG IN terminal with the DVS set to the Xi range The equation is VOUT 1 5 000 0 5 000 This same output of course could also be obtained by applying 0 500Vdc input with the DVS in the X10 range Negative DVS output is obtained a similar manner that is by applying a positive analog in put at the ANLG IN terminal The bandwidth of the analog input measured at the 3dB point is approximatley 25kHz other words the gain of the power amplifier falis off if the analog input frequency exceeds 25kHz with the amplifier ap proaching unity gain at 100k Hz SECTION iV PRINCIPLES OF OPERATION ANALOG INPUT ANALOG ANALOG BINARY 15
162. ss ca pacitor 30 Adjust A3R36 for a reading of 16 396 i 003V INDIVIDUAL BIT CALIBRATION m The individual bits are adjusted in two groups 8192 4096 2048 1024 and 512 256 128 64 according to the table below The adjust ment of all bits in the first group should be com pleted before proceeding to the second group If any potentiometer in a group is adjusted to its end stop continue adjusting the remaining potentiom eters in the group and then back off 10 on the tentiometer that reached its end stop Reprogram the bit associated with the potentiometer that was adjusted to its end stop and then adjust A3R36 for the correct output voltage level If A3R36 must be adjusted the entire bit calibration procedure must be repeated Voltage Bit Meter Reading Potentiometer 8192 5mV 100uV A3R52 4096 5mV 100 A3R53 2038 5mV 100uV A3R54 1024 5mV 100uV A3R55 512 5mV 30 256 5mV 30uV 128 5mV 430pV 64 5mV 430uV A3R56 57 58 59 Check each of the remaining bits 32mV l6mV 8mV 4mV 2mV lmV and 0 5 to in sure that they are within 200uV If not check the associated switching transistors and ladder network on the board see Figure 7 2 sheet 1 POSITIVE ZERO VOLTAGE AND X10 FEEDBACK RE SISTOR ADJUSTMENT CALIBRATION o Set the data and sign bits on the Program mer for an output of 0 volts p Adjust A3R18 for OV 1001 q Turn on the 4096
163. t the resulting stor age gate occurs after the start of the incoming data pulses The negative 50 microsecond gate pulse TP6 serves as the input to the gate pulse isolator while the positive output is the input the flag isolator 4 31 The flag output to the computer TP16 is pro duced by an OR gate whose nputs are the 50 micro second pulse TP40 a pair of pulses occurring at the beginning and end of a current overload and a 2 millisecond pulse which occurs during a change in voltage range Waveforms for the flag output signals may be found in Figures 3 4 3 5 and 3 7 The isolator for the flag signal output mits the output amplifier inverter to be biased and configured to interface with the computer s receiver circuit The trailing edge of the 50 microsecond flag produced by a gate input informs the computer that voltage processing is complete and the unit should be producing the requested output The gate pulse isolator provides dc isolation The isolator output TP7 triggers the gate pulse gen erator and also resets the current latching flip flop The gate pulse generator produces 2 micro second positive pulse TP8 with its leading edge delayed by 3 microseconds from that of the input gate 4 32 With the storage disable switch in the STORE position the gate pulse generator output pulse is the input to an OR gate whose output TP9 is the storage gate for voltage magnitude and voltage sign bits Putting
164. tage processing circuits which in turn generates the flag signal which is applied to the computer through another photo isolator and an output amplifier inverter circuit 4 61 Current Latch Circuits These circuits are composed of a variable delay level detector latch ing flip flop reset amplifier isolator and output amplifier if a current overload condition persists for a certain preset delay period these circuits generate a current latch signal The current latch Signal ultimately biases the power amplifier to cut off or near cutoff limiting the output current to less than 10mA A current latch indicator signal is also generated if a current latch condition occurs 4 62 The variable delay circuit delays the fall time of the current overload input TP17 The de gree by which the leading edge of this signal is retarded determines the current latch delay period The variable delay circuit operates in conjunction with the CT terminals on the rear of the unit mentioned previously the condition of these terminals determines the current latch delay With the CT terminals open a natural delay period of from 3usec to 10 results If the user connects a capacitor across the CT terminals the current latch delay period can be extended from 5 to 2msec at the rate of approximately ipF per msec The user can also disable the current latch circuits by shorting the terminals This disables the variable delay c
165. tage range data bit must remain for at least 10 5 after the triggering edge of the gate Once the 10 period is expired the volt age range input can be removed The gate must reset for at least 2usec before starting a new gate and the time between the leading edges of two consecutive gates must be at least Zmsec 3 22 range change is programmed then the trailing edge of the Flag sent to the computer is delayed 2msec after the leading edge of the Gate If a range change is not programmed the DVS Flag is returned 55 5 after the Gate as indicated Figure 3 4 and discussed in paragraph 3 15 3 23 Voltage Range Programming The voltage range bit from the computer has two states and X10 In the range the voltage magnitude data input is multiplied by 1 so that the output voltage can be varied in 0 5mV or greater steps between 0 000 and 16 3835 volts positive sign or 0 005 and 16 384 volts negative sign bit In the X10 range the voltage magnitude data input is multiplied 10 so that the output voltage can be varied in 5mV steps or greater between 100 00 and 100 00 volts ZmSEC MIN Md DATA TRUE DN _ peer Seren TRUE d m r5 SEC MiN TIME 2uSEC MIN e Li SATE iNPUT FLAG OUTPUT iU READY Figure 3 5 Timing Diagram Range Change 3 24 CURRENT LIMIT 3 25 The DVS provides a maxi
166. tor circuits of each of the first three differential amplifiers contain RC networks C1 R6 C2 16 R25 which help prevent amplifier oscillations Potentiometer A7R9 in the base circuit of can be adjusted to compensate for slight differences between the two base voltages of the input stage thus zeroing the output voltage 4 117 The output of the feedback differential am plifier is taken from the collector of A7Q5 and ap plied to the coupling amplifier A7Q6 Negative feedback is employed from the collector of Q5 to the base of for equalization purposes Zener diode VR7 improves the response time of the feed back amplifier by its clamping action at the collec tor of Q5 4 118 Range relay A7K2 switches in the proper value equalizing network for each range C22 and R88 in the X10 range or these components in par allel with C23 and R89 in the X1 range Relay 1 1 changes the range by changing the overall feedback resistance by a factor of 10 overall feedback line from the high sensing terminal to the base of contains resistors R85 R86 and R87 in the X10 range In the X1 range the relay is energized thus shorting out R85 and R86 4 119 The normal output voltage swing at the col lector of Q5 is between 1 volt and 6 volts These two extremes represent output voltages 100V and 100V respectively Q5 provides an output proximately 3V when the output voltage is zero 4 120
167. torage circuits invert the signal which is then changed into a programming current the result of which is 1 23835mA flowing into TP56 on the D A Board A3 The polarity offset is turned on by the posi tive sign program bit This draws a current of 1 6384mA from TP56 leaving 0 40005mA to be amplified and inverted by the amplifier section the result of this will be 4 volts at the output terminals the amplifier section has a 4 0 05uA offset 4 39 4 volts negative 215 complement were programmed into the instrument Figure 4 2B again the isolators storage circuits would invert the signal and the ladder network converts the resultant signal into a programming current the value of which is 39995 The polarity off switch is turned off by the negative sign pro gram input thus no current is drawn from TP56 The 39995mA is amplified and inverted by the power amplifier and the result of this will be 4 volts at the output terminal again the power amplifier has 0 054A offset NETWORK POWER AMPLIFIER 25855 0 40005 D A OUTPUT LADDER A3 Your 710 000 Iw 1 6384 POLARITY OFFSET SWITCH ON POWER AMPLIFIER 0 39995 OUTPUT POLARITY OFFSET SWITCH OFF Voltage Processing Circuits Simplified Schematic 4 40 POWER AMPLIFIER 4 41 The precision power amplifier consists basically of thr
168. trols separately for the positive and negative going transients so that not only the recovery waveshape but also as much as possible of the rise time of the transient is displayed h Starting from the major graticule division representative of time zero count to the right 150 psec and vertically 100mV Recovery should be within these tolerances as illustrated in Figure 5 6 i Program the output voltage to 16 3835 volts change to 35a 17W and the voltage range to X1 j The transient recovery should be within 16mV at 150 8 as illustrated in Figure 5 6 5 37 TROUBLESHOOTING 5 38 Before attempting to troubleshoot this instru ment make certain that the trouble lies within the instrument and not in any associated equipment In order to isolate the DVS from the system in which it is being used the HP Pocket Programmer 14533B is recommended This device permits the operator manually program all functions of the DVS and thus isolate it from other possible sources of trouble within the system such as computer interfacing or a programming error 39 A good understanding of the principles of Operation of the instrument is essential to an ef ficient approach to troubleshooting For this TRANSIENT RECOVERY TIME TRANSIENT RECOVERY TIME UNLOADING TRANSIENT X RANGE X i5Op SEC RANGE Ys100mV X 150 SEC LOADING TRANSIENT 5 6 Transient Recovery Time Wa
169. tt Wire and Cable Div Amerace Esna Corp Brookfield Mass City of Industry Calif 83835 83877 84171 84411 86684 86838 87034 87216 87585 87929 88140 88245 90634 90763 91345 91418 91506 91537 91662 91929 92825 93332 93410 94144 94154 94222 95263 95354 95712 95987 96791 97464 97702 98291 98410 98978 99934 MANUFACTURER ADDRESS Grant Pulley and Hardware Co West Nyack N Y Burroughs Corp Electronic Components Div Plainfield 0 5 Radium Corp Morristown N J Yardeny Laboratories Inc New York N Y Arco Electronics Inc Great Neck TRW Capacitor Div Ogallala RCA Corp Electronic Components Harrison N J Rummel Fibre Co Newark Marco amp Oak Industries a Div of Oak Electro netics Corp Anaheim Calif Philco Corp Lansdale Div Lansdale Pa Stockwell Rubber Co Inc Philadelphia Pa Tower Olschan Corp Bridgeport Conn Cutler Hammer Inc Power Distribution and Control Div Lincoln Plant Lincoln ill Litton Precision Products Inc USECO Div Litton Industries Van Nuys Calif Gulton Industries Inc Metuchen N J United Car Inc Chicago Miller Dial and Nameplate Co Monte Calif Chicago Attleboro Mass Dale Electronics Inc Columbus Neb Elco Corp Willow Grove Pa Honeywell Inc Div Micro Switch Freeport HL Whitso Inc Schiller Pk Sylvania Electric Prod Inc Semi conductor Prod Div Wo
170. tude bits to the off position 18 Check voltages at TP52 53 and 55 on the A3 board Voltage changes should be as indicated below If not check associated regula ting circuit the board If voltages check out perform the troubleshooting procedures for the voltage processing circuits paragraph 5 47 TP AV 52 0 TP53 0 5mV 55 100 5 47 VOLTAGE PROCESSING CIRCUIT TROUBLE SHOOTING 5 48 The following paragraphs should be help ful in locating any circuit failures on the 1 A2 or A3 boards Paragraph 5 49 traces the voltage magnitude and sign bits through the three boards to locate data bit problems on the 1 and 2 boards or to isolate them to the A3 board Paragraph 5 50 troubleshoots the A3 board in detail Paragraph 5 5 troubleshoots the gate flag and storage strobe circuits on the A1 and A2 boards Refer to Figure 7 2 sheet 1 when troubleshooting circuit failures on the 1 A2 or circuit boards Use the extender board paragraph 5 4 to gain access to circuit board test points NOTE For convenience it is best to leave the and boards out of the unit while troubleshooting the voltage processing circuits 5 49 Al and A2 Board Troubleshooting Assuming that the sign bit or one or more voltage magnitude bits do not affect the output of the D A converter the following steps will isolate the problem to a particular board a Observe the voltage between com
171. ubsequent paragraphs It should be noted though that the trailing edge of the Flag indicates to the computer that the volt age processing is complete and will occur 55 8 after the leading edge of the Gate provided the voltage range of the DVS has not been changed 1f voltage range change is programmed the trail ing edge of the Flag is delayed to 2msec from the leading edge of the Gate refer to Paragraph 3 21 3 17 STORAGE 3 18 With the STORAGE switch 4 Figure 3 2 in the STORE position the voltage sign range and current latch program data are stored when the gate is received from the computer In the DISABLE position indicator 051 lights and the data are processed as soon as they are received 3 19 Storage can be disabled in cases where a manual programmer is used or where the computer has internal storage for the voltage magnitude and sign data 3 20 VOLTAGE RANGE 3 21 The voltage range data input from the com puter multiplies the voltage m gnitude data X1 for the lower range or X10 for the higher range In the Xlrange the maximum output voltage swing is from 16 384 to 16 3835 volts in the X10 range the output voltage swing is from 100 00 to 100 00 volts The range of the DVS is controlled by the voltage range data bit from the computer which is stored along with the voltage magnitude sign and current latch data in the DVS when the Gate input is received As shown in Figure 3 5 the vol
172. ug at the rear of the unit Section of this manual provides a complete description of the interfacing requirements 2 11 LOCATION 2 12 This instrument is convection cooled Suffi cient space should be allotted so that a free flow of air can reach the rear of the instrument when it is in operation It should be used in an area where the ambient temperature remains between 09C and 55 C 2 13 OUTLINE DIAGRAM 2 14 Figure 2 1 shows the outline and dimension information for the instrument which can be used to plan a specific installation TERMINAL STRIP DETAIL CURRENT IN pis HS I 1039 UT e 45825 9693 77 zl SOOO s tage emmi Figure 2 1 Outline Diagram 2 15 RACK MOUNTING 2 16 To mount the unit in a standard rack panel proceed as foliows a Remove gray plastic trim strips glued on at each side of unit by inserting a thin screwdriver at edge or top of strip and prying gently away from unit b Attach rack ears furnished with each unit to side of unit using screws supplied with ears c Mount unit in rack using standard mounting screws 2 17 INPUT POWER REQUIREMENTS 2 18 POWER REQUIREMENTS 2 19 This instrument may be operated continuous A4 POWER SUPPLY BD TRANSFORMER T TRANSFORMER T8 i i INSTALL 230VAC aa REMOVE JUMPER 115 VAC JUMPERS 745 INTERCONNECT BD Figure 2 2 Primary Co
173. uits to continuously provide a volt age magnitude output without the need for repeated voltage magnitude and signinputs from the computer Each time the input gate is received a storage gate reset signal and a flag are generated The Storage gate signal initiates the storage function within the current latch and voltage range process ing circuits reset output signal resets the current latch circuit if 1 the circuit is in the latch condition and 2 if the condition that originally caused the latch has been corrected The reset signal is ignored if these two conditions have not been satisfied 4 9 The flag output provides timing information to the computer concerning the status of the volt age processing and current latch and voltage range processing circuits itis generated in response to the gate input or the overload range enable inputs from the current latch and voltage range circuits 4 10 CURRENT LATCH AND VOLTAGE RANGE PROCESSING 4 11 Current latch and voltage range processing circuits interface isolate store and process input digital information to provide the current latch and voltage range output signals to the pow er amplifier Input circuits similar to those used in voltage processing adapt the DVS to the com 4 2 puter circuits and provide dc isolation Integrat ed circuits store the information when the storage gate is received from voltage processing The Stored current latch and voltage range data
174. uracy proceed as fol lows a Connect a digital or differential voltmeter to the HI and LO sensing terminals on the rear of the unit b Program the output to 100 0V and gate the unit The voltmeter should read 100 0 xi0mVdc d Set the range switch to X1 e Program the output to 16 384 volts Gate the input f The differential voltmeter should read 16 384V lmVdc 9 15 Voltmeter Accuracy To check the accuracy of the front panel voltmeter proceed as follows a Connect a Digital or differential volt meter to the and LO sensing terminals on the rear of the unit b Turn on supply and program the output voltage for 100 0V Gate the unit Record the reading on the voltmeter 9 The reading on the front panel meter should be the same as the reading in Step c 5 volts 5 16 Load Regulation Definition The change in the static value of dc output voltage resuit ing from a change in load resistance from open circuit to a value which yields maximum rated output current or vice versa 5 17 Load regulation should be checked in both the higher X10 range with both negative and pos itive output voltages and the lower X1 range with both positive and negative output voltages since any one of these four conditions can yield an un satisfactory result which is not reflected under the other three conditions To test the load reg ulation for all four conditions proceed as fol lows
175. urrent limit switching level If the output current starts to exceed the source cur rent limit of 0 55A the voltage drop across sam pling resistor 5 5 increases and produces age level at the base of Q21 equal to the base volt age of Q22 With zero differential voltage between 021 and 022 022 comes out of cutoff switching Q23 and forward biasing CR23 The negative volt age coupled through CR23 clamps the power ampli fier output current to a maximum 0 55 Back to back diodes CR28 and CR29 protect the base emitter junction of Q22 from voltage transients caused by surge currents through 4 129 During sinking conditions the normally posi tive output voltage becomes negative This nega tive voltage is fed back through diodes CR30 and CR31 and influences the positive current limit switching level at the base 022 the output voltage becomes increasingly negative the positive current limit switching level decreases so that Q22 will switch on and initiate current limiting at output current level less than 0 55 4 130 Current Latch Isolator Switch These two circuits operate in conjunction with the current latch circuits on the A6 Control Board The current latch isolator circuit consists of switching transis tor A7Q25 and tuned collector oscillator 7024 positive going transition at the current latch input at the base of A7Q25 causes it to conduct The resultant output at its
176. ut and output 4 70 Storage When a high level is present at the clock inputs of the storage circuits the level present at the data inputs appears at the Q outputs and the complement of that data at the outputs Whatever data is present when the clock input becomes low is stored in the flip flops and con tinues to appear at the outputs until the next high clock input occurs In STORAGE DISABLE mode the clock input remains high The logic board has two sets of four sockets for these IC packages set is designated Z1 through 24 and connects the inverting Q outputs The other Z9 through Z12 connects the non inverting Q outputs The proper choice of sockets for these IC s depends on the interface requirements of the DVS and whether an inversion of the voltage mag nitude bits is needed The fifteen voltage magni tude outputs from storage to the D A converter must be low for those bits that are true The voltage sign output from storage must be low for positive output voltage and high for a negative one Since one inversion occurs at the input isolators negative true voltage magnitude inputs from the computer require the use of the inverting Z1 through Z4 sockets and positive true inputs require the non inverting Z9 through Z12 sockets to be used The proper polarity of the sign bit is obtained by positioning jumper W1 in the B position for pos itive inputs and the A position if the input is positive LO
177. ve or full negative or zero first step in troubleshooting then is to isolate the trouble to one of the four circuit groups Once this is accomplished the defective part of the faulty circuit can be located by more detailed troubleshooting The following procedures will isolate trouble to one of the four circuit groups by systematically eliminating each circuit from the loop one at a time and noting if the output voltage returns to normal after each circuit isola tion 1 Disconnect the load and insure that the output terminals are not short circuited 2 Program for OV output 3 Isolate the gross current limiters from the loop by opening the connection from A7CR23 and CR36 to the base of 4706 4 Program the output voltage 100 volts above and below 0 volts in 5 volt steps 5 Ifthe original trouble still exists reconnect the gross current limiters and proceed to Step 6 If the original trouble is eliminated turn the DVS off and troubleshoot the gross current limiters Table 5 13 6 Isolate the current latch circuits by opening the connection from diodes A7CR15 and CR20 to the power amplifier 7 Repeat Step 4 8 Ifthe original trouble still exists re connect the current latch circuits and proceed to Step 9 If the original trouble is eliminated turn the DVS off and troubleshoot the current latch circuits Paragraph 5 67 9 Program the DVS for OV output 10 Isolate the feedback differential amp
178. veforms reason it is recommended that Section IV Principles of Operation be reviewed before attempting to troubleshoot the unit Once the principles of operation are understood follow the steps of the Overall Trouble Isolation Procedure in paragraphs 5 43 through 5 46 in the given order to establish which circuit areas are functional and which are not References to more detailed troubleshooting guides are given inthat procedure 5 40 The four sheets of schematic diagrams of Figure 7 2 are based on the functional organiza tion of the unit Figure 7 1 provides an overall block diagram of the unit except for its power distribution and is especially convenient for tracing signal flow through the entire instrument The circled test point numbers on Figures 7 1 and 7 2 are also marked on the component location diagrams which accompany the schematics Re ferences are made to these test points in the Prin ciples of Operation section of the manual as well 5 41 Before proceeding with the trouble isolation procedure check for obvious troubles such as an open fuse a defective power cord an input power failure a defective meter or a loosely con nected board Next visually inspect the boards for mechanical damage discolored or charred com ponents etc If the source of trouble cannot be detected by visual inspection perform the Overall Trouble Isolation Procedure given below Through out the course of troubleshooting the instrument do
179. venting the output current from exceeding the maximum current limit For sink currents the trip point is reduced 4 50 Disconnect Interlock disconnect interlock relay provides load protection by shorting the out put of the DVS whenever the computer cable is dis connected or source power is interrupted Under these conditions the relay is deenergized as shown on Figure 7 1 and contacts of the relay short the output terminals The output is also shorted at turn on for approximately 0 2 seconds and turn off of the unit which protects the load from possible transients during these times For normal operating conditions the relay is energized removing the short between the output terminals and connecting the interlock signal 2 to the cur rent latch and voltage processing circuits 4 51 Metering Circuits The metering circuits provide continuous indications of output voltage and current on the front panel meters The meters operate in conjunction with front panel range switches and appropriate resistive voltage dividers to permit voltage display in one of two ranges and current indications in one of three ranges 4 52 CURRENT LATCH AND VOLTAGE RANGE PROCESSING 4 53 These circuits are located on the control board They consist of input isolating circuits storage decoding current sampling and current overload circuits The circuits will be described functionally based on signal fiow from input to out put 4 54 Input D
180. wer supply starting with 00101 1 19 If the serial number on your instrument does not agree with those on the title page of the man ual Change Sheets supplied with the manual or Manual Backdating Changes define the differences between your instrument and the instrument de scribed by this manual 1 20 ORDERING ADDITIONAL MANUALS 1 21 One manual is shipped with each power supply Additional manuals may be purchased from your local Hewlett Packard field office see list at rear of this manual for addresses Specify the model number serial number prefix and HP Part number shown on the title page Tabie 1 1 AND OUTPUT POWER Input 115 2105 48 440Hz 1 2 100W Standard 230Vac 10 48 440Hz 0 6A 100W Option 28 only Output X1 Range 16 384 to 16 3835Vde 9 0 5A Source X10 Range 100 to 100 9 0 5A Source Sink Current Compliance sink condition results from an active load attempting to force energy back into the DVS This can appear as current flow into the HI output terminal when the terminal is positive or current flow out of tbe terminal when it is negative In either case the cur rent is limited to a value ranging linearly from 0 25A at 100V to 0 55 at OV ACCURACY Basic DC voltage accuracy at 23 C 39C 115Vac input no load following 30 minutes warm up X1 Range X10 Range lmV 10 Source Effect Line Regulation Shange in out
181. witched Overload Flag is disabled for 120 Option Table 5 7 Current Latch Decoder Troubleshooting Guide SYMPTOM PROBABLE Current latch defective for all values 601 Q8 015 72 deceive Current latch defective only for the following A6Q3 opened Q13 or O15 shorted values 20 70 and 200mA Current latch defective only for the following values 50 100 and 500mA A6Q3 shorted Q13 or O15 opened 5 20 Table 5 7 Current Latch Decoder Troubleshooting Guide Continued SYMPTOM PROBABLE CAUSE Current latch defective only for the following A602 opened 012 014 shorted values 20 50 200 500mA Current latch defective only for the following values 70 and 100mA A6Q2 shorted Q12 or Q14 opened Current latch works for 20 or 200mA but does not work for both A608 defective Current latch works for 50 500mA but does 6010 defective not work for both Current latch does not work for 70mA 609 defective Current latch does not work for 100mA 608 Q9 O10 defective Table 5 8 Unit Always in Current Latch NOTE Logic level 1 equals a positive voltage logic level 0 equals approximately OV ACTION RESPONSE CONCLUSION 1 Connect voltmeter a Logic level 0 Current latch circuit on A6 common to board operating properly check Remove load and en current latch circuit on A7 board sure t
182. zed the delay is adjustable between 5usec and 2msec at the rate of approximately lF per msec 3 32 The current latch status signal will switch from overload to normal state approximately 104 Sec after the next gate providing that the overload condition no longer exists Therefore to program the DVS out of the current latch condition and back to normal operation the overload must be removed or the current latch increased and then new gate must be issued The flag will switch to busy Spsec after the gate is received and re main in that state for 50usec 54SEC MIN OUTPUT CURRENT EXCEEDS CURRENT LIMIT STATUS OUTPUT NORMAL NORMAL Serer oe VARIABLE OVLD DELAY SEC OVERLOAD l TO 2msEC RESET CURRENT LATCH LATCH STATUS OUTPUT BEGIN CURRENT LATCH NORMALI NORMAL y OVLD LATCH d P SEC 771 Lour BUSY OVERLOAD 3usec 50u SEC _ FLAG OUTPUT READY NOTE 2 gy sec 4 NOTES 1 AMPLITUDE AND POLARITY OF TIMING SIGNALS VARY IN ACCORDANCE WITH INSTRUMENT MODIFICATIONS REFER TO APPROPRIATE OPTION OR MODIFICATION SHEET 2 OVERLOAD FLAG OUTPUT DISABLED FOR J20 OPTION Figure 3 7 Current Latch Overload Timing Diagram 3 33 Current Latch Disable The current latch circuit within the DVS can be disabled by shorting the CT terminals at the rea

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