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Fujitsu MPE3XXXAE User's Manual

1. 1 2 3 573 574 575 576 Physical cylinder 0 LBA LBA LBA LBA LBA SP SP Physical head 0 SM T 219r 819 1 2 3 573 574 575 576 Physical cylinder O LBA LBA LBA LBA LBA SP SP Physical head 1 574 575 576 1146 1147 ex Zone 0 6 3 6 3 1 Physical parameter Physical sector 1 to 574 For the rest 2 spare sectors Figure 6 6 Address translation example in LBA mode Power Save The host can change the power consumption state of the device by issuing a power command to the device Power save mode There are four types of power consumption state of the device including active mode where all circuits are active In the power save mode power supplying to the part of the circuit is turned off There are three types of power save modes e Idle mode e Standby mode e Sleep mode C141 E093 02EN 1 2 3 Active mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions e A command with Seek or Write or Read is issued Idle mode In this mode circuits on the device is set to power save mode The device enters the Idle mode under the following conditions e A IDLE or IDLE IMMEDIATE command is issued in the active or standby mode e When one of following command is issued the command is executed narmall
2. E 6 14 6 5 3 Usage of read segment ote onte uli ertet nito deb rM LER a 6 15 6 6 Write Cache uie ei A RESORT 6 20 X C141 E093 01 EN 1 1 2 1 2 2 2 3 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 13 3 14 3 15 3 16 3 17 3 18 4 1 4 2 4 3 4 4 4 5 4 6 5 1 2 2 5 3 FIGURES page Current fluctuation Typ when power is turned 1 7 Diskdrive o terview cient inei t t 2 1 1 drive system configuration 2 3 2 drives contisuration z ou o mp RI teen ED 2 3 av atelier maie Er d Loves 3 2 5 2 agn ce enne ideoque eed eat 3 3 Limitation of 81 enne 3 4 Mounting frame eh red RE eo e E PE e Ree EE ee ee Rea ee 3 4 Surface temperature measurement points essere nennen nennen 3 5 SELVICE ALC 3 6 Connector locations 3 m ouis dide dau diede bte dep bi tede 3 7 Cable c nnectiofis o xa oed Be 3 8 Power supply connector pins CN enne nennen nennen 3 9 Cabl configuration tna Pit 3 10 Cable type detection using CBLID signal Host sensing the condition of the CBLID signal eee 3 11 Cable type detection using IDENTIFY DEVICE data Device sensing the condition of the CBLID 1 eee 3 11 VUMPET LOCATON sips iy E EC 3 12 Factory default setting aeter 3 13 Jumper setti
3. Figure 6 9 K 512 KB 524 288 bytes for MPU work for READ command for WRITE command lt 63 305 gt 132 64 512 bytes 312 832 bytes 135 168 bytes Figure 6 9 Data buffer configuration The read ahead operation is performed at execution of the READ SECTOR S READ MULTIPLE or READ DMA command and read ahead data are stored in the buffer for read cache C141 E093 01 EN 1 2 3 Caching operation The caching operation is performed only at receipt of the following commands The device transfers data from the data buffer to the host system if the following data exist in the data buffer e All sector data to be processed by the command e part of data including the starting sector to be processed by the command When a part of data to be processed exist in the data buffer the remaining data are read from the disk medium and are transferred to the host system Commandis that are object of caching operation The following commands are object of caching operation READ SECTOR S READ MULTIPLE READ DMA READ VERIFY When the caching operation is disabled by the SET FEATURES command no caching operation is performed Data that are object of caching operation The following data are object of caching operation 1 Read ahead data read from the disk medium in the data buffer after completion of the command that are object of caching operation 2 Data transferre
4. eee 5 79 PIO data transfer timing iios an ed ee OR ate emcees 5 80 Multiword DMA data transfer timing mode 2 sse 5 81 Initiating an Ultra DMA data in nere 5 82 Sustained Ultra DMA data in burst esee eene nnne nnne nennen nene 5 85 Host pausing an Ultra DMA data in 5 86 Device terminating an Ultra DMA data in burst sese 5 87 Host terminating an Ultra DMA data in 5 88 Initiating an Ultra DMA data out nene 5 89 Sustained Ultra DMA data out eene eene nee enne nennen 5 90 Device pausing an Ultra DMA data out 5 91 Host terminating an Ultra DMA data out burst sees 5 92 Device terminating an Ultra DMA data out burst sese ene 5 93 Powet on Reset Timing bet re Y rte e vete redigo eed 5 94 Response t pOWet On eiie efi e eH eia eti re e E eee GE s 6 2 Response to hardware reset 6 3 Response to Software reset beoe ebore dtt dtes eid eR 6 4 Response to diagnostic command 6 5 Address translation example in CHS mode ssssssssssseee 6 7 Address translation example in LBA mode ssssseseeeeeeennn 6 8 Sector slip processifig Junto Dt erar dee dea aen
5. DASP tP Reset means including Power on Reset Hardware Reset RESET and Software Reset 2 Master and slave devices are present 2 drives configuration V Clear Reset Master device zc tN Slave device i S NE tM Pulse width of RESET us tN Time from RESET negation to BSY set ms 400 ns tQ Self diagnostics execution time ER 3 tR Time from RESET negation to DASP assertion slave device 400 ms tS Duration of DASP assertion ta Figure 5 20 Power on Reset Timing Time from RESET negation to DASP or DIAG negation oa ms E s 5 94 C141 E093 01 EN CHAPTER 6 OPERATIONS 6 1 Device Response to the Reset 6 2 Address Translation 6 3 Power Save 6 4 Defect Management 6 5 Read Ahead Cache 6 6 Write Cache 6 1 Device Response to the Reset This section describes how the PDIAG and DASP signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command C141 E093 01 EN 6 1 6 1 1 Response to power on After the master device device 0 releases its own power on reset state the master device shall check a DASP signal for up to 450 ms to confirm presence of a slave device device 1 The master device recognizes presence of the slave device when it confirms assertion of the DASP signal Then the master device check
6. DMACK 4 MET tI tK DIOR DIOW ae tD Write data N DD0 DD15 NE me cmn c t Read data NO DDO DD15 E y peny ame mom DACE aeron o pan 5 De La Lu Cc Figure 5 9 Multiword data transfer timing mode 2 C141 E093 01 EN 5 81 5 6 3 Ultra DMA data transfer Figures 5 10 through 5 19 define the timings associated with all phases of Ultra DMA bursts Table 5 15 contains the values for the timings for each of the Ultra DMA Modes 5 6 3 1 Initiating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device tui DMACK host t tack mi tenv t STOP P sis host trs HDMARDY SE host 1 tzan tziorDY DSTROBE device taz tvos Xu WATER T PEPE gt COOOX XXXX DD 15 0 xx DE tack DAO DA1 DA2 Fr CS0 CS1 ZN XXX Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 10 Initiating an Ultra DMA data in burst 5 82 C141 E093 01 EN 5 6 3 2 Ultra DMA data burst timing requirements Table 5 15 Ultra DMA data burst timing requirements 1 of 2 NAME MODE 0 MODE 1 MODE 2 MODE
7. FUJITSU DISK DRIVES PRODUCT MANUAL C141 E093 02EN REVISION RECORD Eaton Date published Revised contents 02 Dec 1999 The device specification at start time is modified in the Table 1 1 A dimension is added to the Figure 3 1 R the explanatory notes of the Table 5 4 is modified Section 6 3 1 Power save mode is modified Specification No C141 E093 EN The contents of this manual is subject to change without prior notice All Rights Reserved Copyright 1999 FUJITSU LIMITED C141 E093 02EN 1 This page is intentionally left blank PREFACE This manual describes the MPE3xxxAE series a 3 5 inch hard disk drive with a BUILT IN controller that is compatible with the ATA interface This manual explains in detail how to incorporate the hard disk drives into user systems This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems This manual consists of the following six chapters Chapter 1 DEVICE OVERVIEW Chapter 2 DEVICE CONFIGURATION Chapter 3 INSTALLATION CONDITIONS Chapter 4 THEORY OF DEVICE OPERATION Chapter 5 INTERFACE Chapter 6 OPERATIONS In this manual disk drives may be referred to as drives or devices C141 E093 01 EN iii Conventions for Alert Messages This manual uses the following conventions to show the alert messages An alert message consists of an alert signal and alert statem
8. 5 6 3 10 Host terminating an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes tu DMARQ device host ka tack STOP host EL LE tu tlorpyz pt device tack pou aa host tpvs 0 7 g 7 y TUA OR T NI NP ON 00050 XK KKK KKK KKK tack DAO DA1 DA2 CSO CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 18 Host terminating an Ultra DMA data out burst 5 92 C141 E093 01 EN 5 6 3 11 Device terminating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host lack STOP host DIE B DDMARDY device ters tu lack HSTROBE 7 host HM tovs XXX 2525 2 KE tack DAO DA1 DA2 CSO CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Device terminating an Ultra DMA data out burst C141 E093 01 EN 5 93 5 6 4 Power on and reset Figure 5 20 shows power on and reset hardware and software reset timing 1 Only master device is present V Clear Reset 1 Power on TEENS RESET M Software reset 4
9. 8 5 10 Cylinder Low register X 1F4 The contents of this register indicates low order 8 bits of the starting cylinder address for any disk access At the end of a command the contents of this register are updated to the current cylinder number Under the LBA mode this register indicates LBA bits 15 to 8 Cylinder High register X 1F5 The contents of this register indicates high order 8 bits of the disk access start cylinder address At the end of a command the contents of this register are updated to the current cylinder number The high order 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 x ms Bit 7 Unused Bit 6 L 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 4 DEV bit 0 for the master device and 1 for the slave device Bit 3 HS3 CHS mode head address 3 2 LBA bit 27 Bit 2 HS2 CHS mode head address 3 2 LBA bit 26 Bit 1 HS1 CHS mode head address 3 2 LBA bit 25 Bit 0 HSO CHS mode head address 3 2 LBA bit 24 C141 E093 01 EN 9 Status register X 1F7 The contents of this register indicate the status of the
10. 3 Typical cable characteristics are shown as follows e Cable AWG 30 pitch 0 635 mm e Single Ended impedance typical 80 e Cable capacitance typical 57 pF m 4 The dimensions are shown in Figure 3 10 C141 E093 01 EN 3 9 254 0 to 457 2 mm 10 to 18 inch 127 0 to 304 8 mm 101 6 to 152 4 mm 5 to 12 inch 4 to 6 inch Pin 40 Ground o open Pin 34 0 Pin 30 Ground Pin 34 contact Symbolizes Pin 34 PDIAG CBLID signal Pin 26 Ground Conductor being cut Pin 24 Ground 94 Pin 22 Ground 94 Pin 19 Ground 94 Position 1 Pin 2 Ground System Board Connector 1 Connector 2 Connector Figure 3 10 Cable configuration b Host system that do not support Ultra DMA modes greater than mode 2 shall not connect to the PDIAG CBLID signal c Host system that do support Ultra DMA modes greater than mode 2 shall either connect directly to the device without using a cable assembly or determine the cable assembly type Determining the cable assembly type may be done either by the host sensing the condition of the PDIAG CBLID signal see Figure 3 11 or by relying on information from the device see Figure 3 12 Hosts that rely on information from the device shall have a 0 047 uF capacitor connected from PDIAG CBLID signal to ground The tolerance on this capacitor shall be 2046
11. nennen nennen nene 5 71 Terminating an Ultra DMA data in nennen 5 72 Ultra DMA data out 5 nnne nnne enne nenne 5 74 Initiating an Ultra data out nennen nere 5 74 The data out transfer iiu eo Pt e hona ertt e e eru 5 75 Pausing an Ultra DMA data out 4 5 75 Terminating an Ultra DMA data out eren nennen 5 76 Ultra DMA CRG etre remet Hb teer e 5 78 Series termination required for Ultra DMA 5 79 Timing 35g EBENE UBI IURIS PERENNE 5 80 PIO d ta transfer e RI UA em tnb 5 80 Multiword data transfer 5 81 Ultra 3 3 ace Shandon ais teen 5 82 Initiating an Ultra DMA data in burst ener nnne nenne 5 82 Ultra DMA data burst timing requirements 5 83 Sustained Ultra DMA data in burst 5 85 Host pausing an Ultra DMA data in burst eese nennen eene 5 86 C141 E093 01 EN 1 5 6 3 5 Device terminating an Ultra DMA data in burst sese 5 87 5 6 3 6 Host terminating an Ultra DMA data in 5 88 5 6 3 7 Initiating an Ultra DMA data out burst nee enne 5 89 5 6 3 8 Sustained Ultra DMA data out 4 5 90 5 6 3 9 Device pausing an Ultra DMA data out burst nee eene 5 91 5 6 3 10 Host termi
12. sermaxappress READ ADDRESS v J v vv Invatidcommand v v j V Valid on this command See the command descriptions EE p NN E EN pl um NI E NN sl EN HN E m EE HN Eres E m E s ERR NE ja NES BEER NE el E V V V V V V V V V V V V lt lt lt lt lt lt lt C141 E093 01 EN 5 61 5 4 5 62 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command If BSY bit is 1 the host should wait for issuing a command until BSY bit is cleared to 0 Commands can be executed only when the DRDY bit of the Status register is 1 However the following commands can be executed even if DRDY bit is 0 e EXECUTE DEVICE DIAGNOSTIC e INITIALIZE DEVICE PARAMETERS Data transferring commands from device to host The execution of the following commands involves data transfer from the device to the host IDENTIFY DEVICE IDENTIFY DEVICE DMA READ SECTOR S READ LONG READ BUFFER SMART SMART Read Attribute Values SMART Read Attribute Thresholds The execution of these commands includes the transfer one or more sectors of data from the device to the host In the READ LONG command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cy
13. the device has asserted DDMARDY The host shall negate HSTROBE no sooner than tpvs after the driving the first word of data onto DD 15 0 The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 8 and 5 6 3 2 for specific timing requirements 1 The host shall drive a data word onto DD 15 0 2 The host shall generate an HSTROBE edge to latch the new word no sooner than tpys after changing the state of DD 15 0 The host shall generate an HSTROBE edge no more frequently than tcyc for the selected Ultra DMA Mode The host shall not generate two rising or falling HSTROBE edges more frequently than 2 tcyc for the selected Ultra DMA mode 3 The host shall not change the state of DD 15 0 until at least tpyg after generating an HSTROBE edge to latch the data 4 The host shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first Pausing an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 9 and 5 6 3 2 for specific timing requirements a Host pausing an Ultra DMA data out burst 1 The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 The host shall pause an Ultra DMA burst by not generating an HSTROBE edge Note The device shall not
14. Bit 15 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Word 88 Bit 15 13 Bit 12 8 Bit 7 5 Bit 4 0 Information to be read by IDENTIFY DEVICE command 4 of 4 Enable disable Command set feature enabled Reserved NOP command supported 0 READ BUFFER command supported 0 WRITE BUFFER command supported 0 Reserved Host Protected Area feature set supported 0 DEVICE RESET command supported 0 SERVICE interrupt enabled 0 Release interrupt enabled 0 Look ahead enabled 1 Write cache enabled 1 PACKET Command feature set supported 0 Power Management feature set supported 0 Removable Media feature set supported 0 Security Mode feature set enabled 0 SMART feature set enabled 1 Enable disable Command set feature enabled Reserved Removable Media Status Notification feature set enabled 0 Advanced Power Management feature set enabled 1 CFA feature set supported 0 READ WRITE DMA QUEUED command supported 0 DOWNLOAD MICROCODE command supported 0 Ultra DMA modes Reserved Currently used Ultra DMA transfer modes Reserved Supportable Ultra DMA transfer mode Bit 4 1 Mode 4 Bit 3 1 Mode 3 Bit 2 1 Mode 2 Bit 121 Mode 1 Bit 0 1 Mode 0 Word 89 Time required for SECURITY ERASE UNIT command to complete MPE3102AH X 0009 18 minutes MPE3136AH X 000C 24 minutes MPE3204AH X 0012 36 minutes MPE3273AH X 0018 48 minutes Word 93 CBLID detection results Bit 15 14 Bi
15. Figure 6 7 shows an example where physical sector 5 is defective on head 0 in cylinder 0 Index fp Sector physical NEC ee M 255 6 ee ee ee 574 5715 576 Cylinder 0 efective sector SP Head Qo cq Me i emet EON 0 0 573 574 unused If an access request to sector 5 is specified the device accesses physical sector 6 instead of sector 5 Figure 6 7 Sector slip processing C141 E093 01 EN 6 11 2 Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder This processing is performed when a physical track contains three or more defective sectors and when the automatic alternate processing is performed Figure 6 8 shows an example where physical sector 5 is detective on head 0 in cylinder 0 Index O Teri ty Sector physical 1 2 3 4 5 6 7 OO 575 576 Cylinder 0 efective sector Heador E a EE 1 2 3 4 unused 6 7 575 576 Alternate O0 cylinder Already assigned Head 0 O 3 Defective sector is assigned to unassigned sector 1 alternate cylinder is provided in outer side When an access request to sector 5 is specified the device accesses the alternated sector in the alternate cylinder ins
16. If an error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder the head and the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred The Sector Count register indicates the number of sectors that have not been verified At command issuance I O registers setting contents 1F74 CM 0 1 0 0 0 0 0 R 1F6y DH Start head No LBA MSB 1 5 Start cylinder No MSB LBA 1F44 CL Start cylinder No LSB LBA 1 3 Start sector No LBA LSB 1F24 SC Transfer sector count IFI amp FR XX R Oorl C141 E093 01 EN 5 21 5 At command completion I O registers contents to be read IF DH End cal No ALBA MS 1 5 End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register WRITE SECTOR S X 30 or X31 This command writes data of sectors from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified to 256 sectors in maximum Data transfer begins at the sector specified in the Sector Number register F
17. X B0 This command performs operations for device failure predictions according to a subcommand specified in the FR register If the value specified in the FR register is supported the Aborted Command error is posted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is enabled The device collects or updates several items to forecast failures In the following sections the values of items collected or updated by the device to forecast failures are referred to as attribute values C141 E093 01 EN Table 5 8 Features Register values subcommands and functions 1 2 Features Resister Function X DO SMART Read Attribute Values A device that received this subcommand asserts the BSY bit and saves all the updated attribute values The device then clears the BSY bit and transfers 512 byte attribute value information to the host For infomation about the format of the attribute value information see Table 5 9 X D SMART Read Attribute Thresholds This subcommand is used to transfer 512 byte insurance failure threshold value data to the host For information about the format of the insurance failure threshold value data see Table 5 10 X D2Z SMART Enable Disable Attribute AutoSave This subcommand is used to enable SC
18. XX At command completion I O registers contents to be read IF DH End heal No ALBA MS 1 5 1 4 1F34 SN 1 2 IF 1 4 ER If the command is terminated due to an error the remaining number of sectors for which data was not transferred is set in this register End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00g 1 Error information C141 E093 01 EN 5 19 3 READ DMA X C8 or 9 This command operates similarly to the READ SECTOR S command except for following events e data transfer starts at the timing of DMARQ signal assertion e device controls the assertion or negation timing of the DMARQ signal e device posts a status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not trans
19. 3 MODE 4 COMMENT in ns in ns in ns in ns in ns 240 Typical sustained average two cycle time ES 112 Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge Two cycle time allowing for clock variations from rising edge to next rising edge or from falling edge to next falling edge of STROBE Data setup time at recipient see Note 4 Data hold time at recipient see Note 4 Data valid setup time at sender from data valid until STROBE edge see Note 5 tpvH Data valid hold time at sender from STROBE edge until data may become invalid see Note 5 First STROBE time for device to first negate DSTROBE from STOP ETHERNET a data in burst 100 Limited interlock time see Note Limited interlock time see Note 3 m Interlock time with minimum Note 3 Unlimited interlock time Unlimited interlock time see Note 3 Note 3 Maximum time allowed for output drivers to release from asserted or negated E mE delay time required for ES Drivers to assert or negate from released Envelope time from DMACK to STOP and HDMARDY during data in burst initiation and from DMAC to STOP during data out burst initiation STROBE to DMARDY time if DMARDY is negated before this long after STROBE edge the recipient shall receive no more than one additional data word Ready to final STROBE time no STROBE edges shall be sent this long after negation of
20. 46 GB formatted on one disk using the 48 51 EPRAML recording method and 15 recording zone technology The MPE3xxxAE series have a formatted capacity of 4 33 GB to 17 34 GB respectively High speed Transfer rate The disk drive has an internal data rate up to 40 7 MB s The disk drive supports an external data rate up to 16 7 MB s or 66 6 MB s ultra DMA mode 4 C141 E093 01 EN 1 1 4 1 2 3 1 2 3 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 9 5 ms at read Adaptability Power save mode The power save mode feature for idle operation stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor Wide temperature range The disk drive can be used over a wide temperature range 5 C to 55 C Low noise and vibration In Ready status the noise of the disk drive is only about 3 5 bels MPE3173AE Typical Sound Power ISO7779 1509296 Interface Connection to interface With the builtin ATA interface controller the disk drive can be connected to an ATA interface of a personal computer 512KB data buffer The disk drive uses a 512KB data buffer to transfer data between the host and the disk media In combination with the read ahead cache system described in item 3 and the write cache described in item 6 the buffer
21. 92 us 0 84 us 0 84 0 84 us 0 48 us er K K gt 0 S 1 64 us 1 16 us lt gt male ASM SSM W R Recovery Field 7 98 us 115 7 us CO Figure 4 6 96 servo frames in each track 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark SMK1 SMK2 This area generates a timing for demodulating the gray code and position demodulating Pos A to D by detecting the servo mark C141 E093 01 EN 4 17 3 4 5 6 1 Preamble This area is used to synchronize with the PLL which is used to search the SSM by detecting the ASM Gray code including index bit This area is used as cylinder address The data in this area is converted into the binary data by the gray code demodulation circuit Pos A Pos B Pos C Pos D This area is used as position signals between tracks and the device control at on track so that Pos A level equals to Pos B level PAD This area is used as a gap between servo and data Actuator motor control The voice coil motor VCM is controlled by feeding back the servo data recorded on the data surface The MPU fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cyli
22. BUFFER command Within 5 us following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command Bit 6 Device Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed Bit 5 The Device Write Fault DF bit This bit indicates that a device fault write fault condition has been detected If a write fault is detected during command execution this bit is latched and retained until the device accepts the next command or reset Bit 4 Device Seek Complete DSC bit This bit indicates that the device heads are positioned over a track In the IDD this bit is always set to 1 after the spin up control is completed C141 E093 01 EN 5 11 10 5 12 Bit 3 Data Request DRQ bit This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device Bit 2 Always 0 Bit 1 Always 0 Bit 0 Error ERR bit This bit indicates that an error was detected while the previous command was being executed The Error register indicates the additional information of the cause for the error Command register X 1F7 The Comman
23. DMA transfer mode Currently used multiword DMA transfer mode Supportable multiword DMA transfer mode Bit 2 1 Mode 2 Bit 1 1 Mode 1 Bit 0 1 Mode 0 Advance PIO transfer mode support status Reserved Advance PIO transfer mode Bit 121 Mode 4 Bit 021 Mode 3 Major version number Reserved ATA 4 1 ATA 3 1 ATA 2 1 ATA 1 Supported 1 Undefined Support of command sets Reserved NOP command supported 0 Read Buffer command supported 1 Write Buffer command supported 1 Write Verify command supported Old Spec 0 Host Protected Area feature command supported 1 Device Reset command supported 0 SERVICE Interrupt supported 0 Release Interrupt supported 0 Lock Ahead supported 1 Write cache supported 1 Packet command feature set supported 0 Power Management feature set supported 1 Removable feature set supported 0 Security feature set supported 0 SMART feature set supported 1 Support of command sets 0 1 Reserved Removable Media Status Notification feature set supported 0 Advanced Power Management feature set supported 1 CFA feature set supported 0 READ WRITE DMA QUEUED supported 0 DOWNLOAD MICROCODE command supported 0 C141 E093 01 EN Table 5 5 17 18 19 20 21 Word 85 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Word 86
24. DMARDY Ready to pause time that recipient shall wait to pause after negating DMARDY C141 E093 01EN 5 83 Table 5 15 Ultra DMA data burst timing requirements 2 of 2 NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 COMMENT in ns in ns in ns in ns in ns tziorpy Minimum time before driving IORDY tack Setup and hold times for DMACK before assertion or negation Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst Unless otherwise specified timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies see Note 5 for exceptions For example the sender shall stop generating STROBE edgesfs after the negation of DMARDY Both STROBE and DMARDY timing measurements are taken at the connector of the sender All timing measurement switching points low to high and high to low shall be taken at 1 5 V tur and tj indicate sender to recipient recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding is an unlimited interlock that has no maximum time value huis a limited time out that has a defined minimum f is a limited time out that has a defined maximum Special cabling shall be required in order to meet data setup s and data hold tn times in modes 3 and 4 Timing for shall be met for all capacitive
25. Data ar a a Cyl 1 Cyln Cyl n 1 n odd number W R Recovery W R Recovery W R Recovery Servo Mark Servo Mark Servo Mark lt gt Gray Code Gray Code Gray Code Diameter direction Erase Servo A Erase Servo A Erase JL ServoB Erase Servo B Erase Servo Circumference direction Servo C Erase Servo Erase Erase DC erase area Erase Servo D Erase Servo D PAD Figure 4 5 Physical sector servo configuration on disk surface 4 14 C141 E093 01 EN 2 3 4 5 6 7 8 Servo burst capture circuit The four servo signals can be synchronously detected by the STROB signal full wave rectified integrated A D converter ADC The A D converter ADC receives the servo signals are integrated converts them to digital and transfers the digital signal to the DSP unit D A converter DAC The D A converter DAC converts the VCM drive current value digital value calculated by the DSP unit into analog values and transfers them to the power amplifier Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor This circuit detects number of revolution of the motor by the interrupt generated periodically compares with the target revolution speed then flows the current into the motor coil a
26. INA INC DAO DA1 DA2 CSO 51 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 15 Initiating an Ultra DMA data out burst C141 E093 01 EN 5 89 5 6 3 8 Sustained Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes HSTROBE at host DD 15 0 at host AX KKK HSTROBE at device 01150 KXXXXXX XXXXXXX_XXXXXXX at device Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 16 Sustained Ultra DMA data out burst 5 90 C141 E093 01 EN 5 6 3 9 Device pausing an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host STOP host tsr DDMARDY device HSTROBE host DD 15 0 host XXXXKK___XKXXKKX_XXKXKKKXKK Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than trp after DDMARDY is negated 2 If the timing is not satisfied the device may receive zero one or two more data words from the host Figure 5 17 Device pausing an Ultra DMA data out burst C141 E093 01 EN 5 9
27. MPU takes a difference between the current time and a time for one revolution at 5 400 rpm that the MPU already recognized Then the MPU keeps the rotational speed to 5 400 rpm by charging or discharging the charge pump for the different time For example when the actual rotational speed is 5 600 rpm the time for one revolution is 10 714 ms And the time for one revolution at 5 400 rpm is 11 111 ms Therefore the MPU discharges the charge pump for 0 397 ms x k k constant value This makes the flowed current into the motor lower and the rotational speed down When the actual rotational speed is later than 5 400 rpm the MPU charges the pump the other way This control charging discharging is performed every 1 6 revolution C141 E093 01 EN CHAPTER 5 INTERFACE 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA feature set 5 6 Timing C141 E093 01 EN 5 1 Physical Interface 5 1 1 Interface signals Table 5 1 shows the interface signals Table 5 1 Interface signals Cable select see note CSEL Chip select 0 Chip select 1 Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus bit 0 DDI DD D3 DD4 DD5 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 Data bus bit 10 Data bus bit 11 Data bus bit 12 Data bus bit 13 Data bus bit 14 Data bus bit 15 Device active or slave present s
28. Register Drive operation mode X 02 Enables the write cache function 03 Specifies the transfer mode Supports PIO mode 4 single word DMA mode 2 and multiword DMA mode regardless of Sector Count register contents XOF No operation X 05 Enable the advanced power management function X3 No operation X 54 No operation XSP Disables read cache function X 66 Disables the reverting to power on default settings after software reset XIT No operation X 8r No operation X 84 No operation X 85 Disable the advanced power management function X 88 No operation X99 No operation Enables the read cache function X AB No operation X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands Enables the reverting to power on default settings after software reset X 82 Disables the write cache function At power on or after hardware reset the default mode is the same as that is set with a value greater than X AA except for write cache If X 66 is specified it allows the setting value greater than X AA which may have been modified to a new value since power on to remain the same even after software reset C141 E093 01 EN 5 35 At command issuance I O registers setting contents IT EPIS 1F5y CH 1F4 CL XX 1F34 SN XX 1F24 SC xx or transfer mode 1F1y FR See Table 5 6 At command completion I O registers contents to be read mes To To T
29. addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an error occurs in a sector the read operation is terminated at the sector where the error occurred Command block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical block address in the LBA mode where the error occurred and remaining number of sectors of which data was not transferred At command issuance I O registers setting contents 1F74 CM 0 0 1 0 0 0 0 R 1F64 DH Start head No LBA MSB 1F54 CH Start cylinder No MSB LBA 1 4 Start cylinder No LSB LBA 1 3 Start sector No LBA LSB 1F24 SC Transfer sector count IFI amp FR XX R Oorl C141 E093 01 EN 5 17 2 5 18 At command completion I O registers contents to be read IS DI End cal No ALBA MS 1 5 End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register READ MULTIPLE X C4 This command operates similarly to the READ SECTOR S command The device does not generate an interrupt assertion of the INTRQ signal on each every sector An interrupt is generated after the transfer of a block of sectors for which the number is
30. bit and generates an interrupt soon When the command execution completes the device clears the BSY bit and generates an interrupt The drive supports this command for keep the compatibility with previous drive only READ LONG X22 or 23 This command operates similarly to the READ SECTOR S command except that the device transfers the data in the requested sector and the ECC bytes to the host system The ECC error correction is not performed for this command This command is used for checking ECC function by combining with the WRITE LONG command C141 E093 01 EN 5 39 19 The READ LONG command supports only single sector operation At command issuance I O registers setting contents 1 5 Cylinder No MSB LBA 1F44 CL Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1F24 SC Number of sectors to be transferred 1Fl4 FR XX R Oorl At command completion I O registers contents to be read IF DH Head No BA 1 5 Cylinder No MSB LBA 1F44 CL Cylinder No LSB 1 3 Sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error this register indicates 01 WRITE LONG 32 or X33 This command operates similarly to the READ SECTOR S command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium The device does not generate ECC bytes by
31. cable round trip delay and tgrs timing for the host The device shall negate DMARQ no sooner than tgp after negating DDMARDY The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The host shall assert STOP with t after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated If HSTROBE is negated the host shall assert HSTROBE with t after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition of HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than tmu after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than tpys after placing the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK C141 E093 01 EN 5 77 11 The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 12 The device shall release DDMARD Y within tiogpyz after the host has negated DMACK 13 The host sha
32. command 2 Ultra DMA transfer mode 2 Sets the FR register 2 X 03 and SC register 2 X 42 by the SET FEATURES command At command issuance I O registers setting contents AE TEES 1 5 Start cylinder No MSB LBA 1F44 CL Start cylinder No LSB LBA 1 3 Start sector No LBA LSB 1F24 SC Transfer sector count IFI amp FR XX R Oorl At command completion I O registers contents to be read IF DH End cal No ALBA MS 1 5 End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command except that the device verifies each sector immediately after being written The verify operation is a read and check for data errors without data transfer Any error that is detected during the verify operation is posted At command issuance I O registers setting contents 1F7y CM 0 0 1 1 1 1 0 0 1F6y DH Start head No LBA MSB 1 5 Start cylinder No MSB LBA 1F44 CL Start cylinder No LSB LBA 1 3 Start sector No LBA LSB 1F24 SC Transfer sector count 1F1y FR XX C141 E093 01 EN 5 25 At command completion I O registers contents to be read IS DH Fd heal N
33. contributes to efficient I O processing Read ahead cache system After the execution of a disk read command the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system enables fast data access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead Master slave The disk drive can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device C141 E093 01 EN 5 6 Error correction and retry by ECC If a recoverable error occurs the disk drive itself attempts error recovery The 40 bytes ECC has improved buffer error correction for correctable data errors Write cache When the disk drive receives a write command the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media This feature reduces the access time at writing C141 E093 01 EN 1 3 1 2 Device Specifications 1 2 1 Specifications summary Table 1 1 shows the specifications of the disk drive Table 1 1 Specifications MPENTAE Formatted Capacity 1 17 34 GB Number of Cylinders 17 301 140 User Alternate amp SA Bytes per Sector 512 Positioning time Minimum 1 5 ms typ
34. device The contents of this register are updated at the completion of each command When the BSY bit is cleared other bits in this register should be validated within 400 ns When the BSY bit is 1 other bits of this register are invalid When the host system reads this register while an interrupt is pending it is considered to be the Interrupt Acknowledge the host system acknowledges the interrupt Any pending interrupt is cleared negating INTRQ signal whenever this register is read Bit 7 Busy BSY bit This bit is set whenever the Command register is accessed Then this bit is cleared when the command is completed However even if a command is being executed this bit is 0 while data transfer is being requested DRQ bit 2 1 When BSY bit is 1 the host system should not write the command block registers If the host system reads any command block register when BSY bit is 1 the contents of the Status register are posted This bit is set by the device under following conditions a Within 400 ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is set for no longer than 15 seconds after the IDD accepts reset b Within 400 ns from the host system starts writing to the Command register c Within 5 us following transfer of 512 bytes data during execution of the READ SECTOR S WRITE SECTOR S FORMAT TRACK or WRITE
35. gt Min 30 ps 1 DRQ it 2 INTRO J Data Reg CA Selection 7 Data X X X x IOR Word 0 1 2 255 IOCS16 When the IDD receives a command that hits the cache data during read ahead and transfers data from the buffer without reading from the disk medium Figure 5 2 Read Sector s command protocol Even if the error status exists the drive makes a preparation setting the DRQ bit of data transfer It is up to the host whether data is transferred In other words the host should receive the data of the sector 512 bytes of uninsured dummy data or release the DRQ by resetting C141 E093 01 EN 5 63 5 64 Note BSY DRDY DRQ INTRQ For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to 5 us after the completion of the sector data transfer Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple sector reading If the timing to read the Status register does not meet above condition normal data transfer operation is not guaranteed When the host new command even if the device requests the data transfer setting in DRQ bit the correct device o
36. iei o ded ee a 4 4 4 4 P wer on Sequence coe ee erede ee nete eo D ede ete ente Re ee 4 6 4 5 Selt calibr tionz eon dct ded ge em 4 8 4 5 1 Self calibration 5 4 8 4 5 2 Execution timing of self calibration eese nemen nene 4 9 4 5 3 Command processing during self calibration eene 4 9 4 6 Read write 4 10 4 6 1 Read write preamplifier 4 10 AOD Write CIRCUIT s ut oti eR t RE e RT ORE EN RENT ERES 4 10 4 06 3 J Re ad circuite sn eec etae edet eb en e d Ae D Ado D e etes 4 11 4 6 4 Synthesizer epi eoe Papier ba tex 4 12 4 7 Servo Control iue iret c pee ESO NR UR PES E VER VERRE PUR E e E EP PESE RR evs 4 12 ACA Servo Control CIECUIGS s ie Det dece Have ae erre t eee Fes e e P e ee 4 13 4 7 2 Data surface servo format eene enne enne nennen enne nenne rennen 4 16 4 7 3 Servo formatas tuin 4 16 4 7 4 Actuator motor control 4 18 4 15 Spi dleanotor control sc cise Im RIP eA ec e regir a Ie AL DR Ud 4 19 CHAPTER 5 INTERFACE nope re ERR 5 1 5 1 Physical Interf ce s deu edi bd ah breton eee veter Here ede 5 2 9 1 1 Z terface signals none nere ae RE o rere UE Pate e db o see Pe YER a 5 2 5 1 2 Signal assignment on the connector 5 3 5 2 Logical Interf ce 5
37. immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait tgp before negating DMARQ 3 The host shall resume an Ultra DMA burst by generating an HSTROBE edge C141 E093 01 EN 5 75 b Device pausing an Ultra DMA data out burst 1 2 3 4 5 The device shall not pause an Ultra DMA burst until at least one data word of an Ultra burst has been transferred The device shall pause an Ultra DMA burst by negating DDMARDY The host shall stop generating HSTROBE edges within tgrrs of the device negating DDMARDY If the device negates DDMARDY within tsp after the host has generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than tsp after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and timing for the host The device shall resume an Ultra DMA burst by asserting DDMARDY 5 5 4 4 Terminating an Ultra DMA data out burst a Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 10 and 5 6 3 2 for spe
38. in last Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes The following table describes recommended values for series termination at the host and the device Table 5 14 Recommended series termination for Ultra DMA Signal Host Termination Device Termination Note Only those signals requiring termination are listed in this table Ifa signal is not listed series termination is not required for operation in an Ultra DMA Mode For signals also requiring a pull up or pull down resistor at the host see Figure 5 7 Note y means an Active Inductance Figure 5 7 Ultra DMA termination with pull up or pull down C141 E093 01 EN 5 79 5 6 Timing 5 6 1 data transfer Figure 5 8 shows of the data transfer timing between the device and the host system to Addresses X X 4 d 9 DIOR DIOW t2 gt ig ye Qi 4 Write data N DD0 DD15 7 3 xd t4 Read data ye N DDO DD15 N vA 5 gt e tll m s Figure 5 8 data transfer timing 5 80 C141 E093 01 EN 5 6 2 Multiword data transfer Figure 5 9 shows the multiword DMA data transfer timing between the device and the host system tO gt DMARQ
39. in which the sector is specified with the logical block address At command issuance I O registers setting contents ial aie ae 1 5 Cylinder MSB 1 4 Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1 2 IFI amp FR xx At command completion I O registers contents to be read IPS DH Head No LBA 1 5 Cylinder MSB LBA 1F44 CL Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1F24 SC XX 1 15 Error information C141 E093 01 EN 5 27 11 12 INITIALIZE DEVICE PARAMETERS X 91 The host system can set the number of sectors per track and the maximum head number maximum head number is number of heads minus 1 per cylinder with this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is posted Other than X 00 is specified this command terminates normally The parameters set by this command are retained even after reset or power save operation regardless of the setting of disabling the reverting to default setting In LBA mode The device ignores the L bit specification and operates with the CHS mode specification An accessible area of this command within head moving in the LBA mode is always within a default area It is recommended tha
40. loads from 15 to 40 pf where all signals have the same capacitive load value 5 84 C141 E093 01 EN 5 6 3 3 Sustained Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host BON POOOOOOXK XOXOXOXOKXUXUA Note DD 15 0 and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 11 Sustained Ultra DMA data in burst C141 E093 01 EN 5 85 5 6 3 4 Host pausing an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host STORE gute P EE RES host HDMARDY host DSTROBE device DD 15 0 lt device XXX Notes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tgp after HDMARDY is negated 2 If the tsp timing is not satisfied the host may receive zero one or two more data words from the device Figure 5 12 Host pausing an Ultra DMA data in burst 5 86 C141 E093 01 EN 5 6 3 5 Device terminating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for eac
41. mV peak to peak DC to 1 MHz DC to 1 MHz C141 E093 01 EN 1 5 3 Current Requirements and Power Dissipation Table 1 3 lists the current and power dissipation Table 1 3 Current and power dissipation Typical RMS current 1 mA Typical Power 2 watts MPE3043AE MPE3084AE MPE3173AE Models MPE3043AE MPE3084AE MPE3173AE 1800 peak 1800 peak 1800 peak 540 640 peak Mode of Operation R W On Track 4 1 Current is typical rms except for spin 2 Power requirements reflect nominal values for 12V and 5V power 3 Idle mode is in effect when the drive is not reading writing seeking or executing any commands A portion of the R W circuitry is powered down the spindle motor is up to speed and the Drive ready condition exists 4 R W mode is defined as 50 read operations and 50 write operations on a single physical track 5 mode is defined as continuous random seek operations with minimum controller delay 1 6 C141 E093 01 EN 4 Current fluctuation Typ when power is turned on 5VDC 0 0 0 5A div li 12VDC 2 0 5A div seconds Figure 1 1 Current fluctuation Typ when power is turned on 5 Power on off sequence The voltage detector circuit monitors 5 V and 12 V The circuit does not allow a write signal if either voltage is abnormal This prevents data from being destroyed and eliminates the need to be concerned with the power on off sequen
42. register 00h or disable SC register 00h the setting of the automatic saving feature for the device attribute data The setting is maintained every time the device is turned off and then on When the automatic saving feature is enabled the attribute values are saved before the device enters the power saving mode However if the failure prediction feature is disabled the attribute values are not automatically saved When the device receives this subcommand it asserts the BSY bit enables or disables the automatic saving feature then clears the BSY bit X D SMART Save Attribute Values When the device receives this subcommand it asserts the BSY bit saves device attribute value data then clears the BSY bit X D4 SMART Executive Off line Immediate A device which receives this command asserts the BSY bit then starts collecting the off line data specified in the SN register or stops In the off line mode after BSY is cleared off line data are collected In the captive mode it collects off line data with the BSY assertion as is then clears the BSY when collection of data is completed SN Off line data collection mode 00h Off line diagnosis off line mode Olh Simple self test off line mode 02h Comprehensive self test off line mode 7Fh Self test stop 81h Simple self test captive mode 82h Comprehensive self test captive mode X DP SMART Read Log Sector A device which receives this sub command asser
43. registers C141 E093 01 EN Table 5 3 I O registers I O registers eee ee Command block registers UTD Em hop pe p hd de p m em b de de T mm ncm hd de T pr mme nme hd T omn orm pore T oma b de dde ee er B d dx emm b p p T eem Te B dd ier Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATAO to DATAI5 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATAO to DATA7 3 When reading the Drive Address register bit 7 is high impedance state 4 The LBA mode is specified the Device Head Cylinder High Cylinder Low and Sector Number registers indicate LBA bits 27 to 24 23 to 16 15 to 8 and 7 to 0 C141 E093 01 EN 5 7 5 2 2 1 2 Command block registers Data register X 1F0 The Data register is a 16 bit register for data block transfer between the device and the host system Data transfer mode is PIO or LBA mode Error register X 1F1 The Error register indicates the status of the command executed by the device The contents of this register are valid when the ERR bit of the Status register is 1 This register contains a diagnostic code after power is turned on a reset or the EXECUTIVE DEVICE DIAGNOSTIC command is executed Status at
44. self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds then negated within 6 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Write Master device Status Reg BSY bit Max 6 sec lt gt If the slave device is preset DASP signal is checked for up to 6 seconds Slave device BSY bit gt Max 1 ms i Max 5 sec gt PDIAG DASP Figure 6 4 Response to diagnostic command C141 E093 01 EN 6 5 6 2 6 2 1 Address Translation When the IDD receives any command which involves access to the disk medium the IDD always implements the address translation from the logical address a host specified address to the physical address logical to physical address translation Following subsections explains the CHS translation mode Default parameters In the logical to physical address translation the logical cylinder head and sector addresses are translated to the physical cylinder head and sector addresses based on the number of heads and the number of sectors per track which are specified with an INITIALIZE DEVICE PARAMETERS command This is called as the current translation mode If the number of heads and the number of sectors a
45. specified by the SET MULTIPLE MODE command The implementation of the READ MULTIPLE command is identical to that of the READ SECTOR S command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts In the READ MULTIPLE command operation the DRQ bit of the Status register is set only at the start of the data block and is not set on each sector The number of sectors block count to be transferred without interruption is specified by the SET MULTIPLE MODE command The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command When the READ MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0 If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled the d
46. the completion of command execution other than diagnostic command ICRC UNC IDNF ABRT TKONF AMNF X Unused Bit 7 Interface CRC error ICRC This bit indicates that an interface CRC error has occurred during an Ultra DMA data transfer The content of this bit is not applicable for Multiword DMA transfers Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error except for uncorrectable error and SB not found and Aborted Command Bit 3 Unused Bit 2 Aborted Command ABRT This bit indicates that the requested command was aborted due to a device status error e g Not Ready Write Fault or the command code was invalid Bit 1 Track 0 Not Found TKONF This bit indicates that track 0 was not found during RECALIBRATE command execution Bit 0 Address Mark Not Found This bit indicates that an SB not found error has been encountered C141 E093 01 EN 3 4 5 Diagnostic code X 01 No Error Detected X 02 HDC Register Compare Error X 03 Data Buffer Compare Error X 05 ROM Sum Check Error X 80 Device 1 slave device Failed Error register of the master device is valid under two devices master and slave configuration If the slave device fails the master device posts X 80 OR the diagnostic code with its own status 01 to X 05 However
47. the device from the host computer the device saves the SMART error log on the disk medium The host computer can issue the SMART Read Log Sector sub command FR register D5h SN register 011 and read the SMART error log Table 5 11 SMART error log data format 1 2 C o eean The most recent Error Log point Elapsed time ms from the point when the power is turned on until command reception Error Data PI Error register Sector Count register Sector Number register Cylinder Low register Cylinder High register Device Head register 5 56 C141 E093 01 EN Table 5 11 SMART error log data format 2 2 5 to 1C3 Error Log Data This format of each error log data structure is the same as Byte 02 Structure 2 to to 5B Error Log Data Structure 5 1C4 1C5 Drive Error Total Number e Error log index Indicates the latest error log number If an error has not occurred 00 is displayed e Error log 1 to 5 When an error occurs the error log index value is incremented and information at the time the error occurred is recorded in the error log area specified by this value When the error log index exceeds 05 it returns to 01 e Command data 1 to 5 Indicates five commands data in order received by the device until the error occurs Commands for which an error occurred are included in Command Data 5 e Error data Indicates the I O register values when the error is reported e State Bits 0 to 3 Indicates t
48. the previous write operation Thus the latency time for detecting a target sector of the next command is eliminated This shortens the access time The drive generates an interrupt of command complete after completion of data transfer requested by the host system as same as at previous command When the write operation of the previous command had been completed the latency time occurs to search the target sector If the received command is not a sequential write the drive receives data of sectors requested by the host system as same as sequential write The drive generates the interrupt of command complete after completion of data transfer requested by the host system Received data is processed after completion of the write operation to the disk medium of the previous command Even if a hard reset or soft reset is received or the write cache function is disabled by the SET FEATURES command during unwritten data is kept the instruction is not executed until remaining unwritten data is written onto the disk medium The drive uses a write data as a read cache data When a read command is issued to the same address after the write command the read operation to the disk medium is not performed When an error occurs during the write operation the drive makes retry as much as possible If the error cannot be recovered by retry the drive stops the write operation to the erred sector and continues the write operation from the next sector if the w
49. to prevent unnecessary pressure around the spindle when the disk starts or stops rotating When disk drives are transported under conditions where the air pressure changes a lot filtered air is circulated in the DE The circulation filter cleans out dust and dirt from inside the DE The disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating disk C141 E093 01 EN 4 3 4 3 1 2 3 4 Circuit Configuration Figure 4 2 shows the disk drive circuit configuration Read write circuit The read write circuit consists of two LSIs read write preamplifier PreAMP and read channel RDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Extended Partial Response Class 4 EPR4 and contains the Viterbi detector programmable low pass filter 10 tap adaptive digital FIR filter synthesizer and data separator circuits The RDC also contains the 48 51 group coded recording GCR encoder and decoder and servo demodulation circuit Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for proces
50. 0 see 5 5 5 The host shall negate DMACK no sooner than ty after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY and no sooner than tpys after the host places the result of its CRC calculation on DD 15 0 C141 E093 01 EN b 10 11 12 13 14 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DSTROBE within tjogpyz after the host negates DMACK The host shall not negate STOP no assert HDMARDY until at least tack after negating DMACK The host shall not assert DIOR CSO CS1 DA2 DAI or DAO until at least tack after negating DMACK Host terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 6 and 5 6 3 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred The host shall initiate Ultra DMA burst termination by negating HDMARDY The host shall conti
51. 01 EN 5 73 5 5 4 1 10 11 12 13 14 15 16 If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than ty after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY and no sooner than tpys after the host places the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA burst for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DSTROBE within tjogpyz after the host negates DMACK The host shall neither negate STOP nor assert HDMARDY until at least tacx after the host has negated DMACK The host shall not assert DIOR CSO CS1 DA2 DAI or DAO until at least tack after negating DMACK Ultra DMA data out commands Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 7 and 5 6 3 2 for specific timing requirements D 2 3 4 5 6 7
52. 2 Orientation Frame The disk enclosure DE body is connected to signal ground SG and the mounting frame is also connected to signal ground These are electrically shorted Note Use No 6 32UNC screw for the mounting screw and the screw length should satisfy the specification in Figure 3 4 Limitation of side mounting When the disk drive is mounted using the screw holes on both side of the disk drive use two screw holes shown in Figure 3 3 Do not use the center hole For screw length see Figure 3 4 C141 E093 01 EN 3 3 Use these screw holes Do not use this screw holes Figure 3 3 Limitation of side mounting 2 5 Side surface 2 5 Bottom surface mounting mounting Frame of system Frame of system cabinet cabinet B LL 4 5 or less Screw 5 0 or less Screw Details of A Details of B Figure 3 4 Mounting frame structure 3 4 C141 E093 01 EN 4 Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive Pay attention to the air flow to prevent the DE surface temperature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Fi
53. 2 drives configuration C141 E093 01 EN 2 3 IMPORTANT HA host adapter consists of address decoder driver and receiver ATA is an abbreviation of AT attachment The disk drive is conformed to the ATA 4 interface At high speed data transfer PIO mode 3 mode 4 DMA mode 2 or ultra DMA mode 4 occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 3 and ATA 4 standard and the cable length between the HA and the disk drive should be as short as possible C141 E093 01 EN CHAPTER 3 INSTALLATION CONDITIONS 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections 3 4 Jumper Settings 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm C141 E093 01 EN 3 1 60 27 44 45 0 15 41 28 0 5 95 25 0 15 Figure 3 1 Dimensions C141 E093 02EN 6 16 32UNC Both Stdes 101 6 0 15 146 0 0 3 Nu one 41 1 41 640 15 9NTN 3 2 1 2 3 Mounting Orientation Figure 3 2 illustrates normal orientation for the disk drive The disk drives can be mounted in any orientation Horizontal mounting with the PCB facing down Figure 3
54. 4 and DMA Mode 2 Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is capable of supporting The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system operates The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable Only the Ultra DMA Mode shall be selected at any given time All timing requirements for a selected Ultra DMA Mode shall be satisfied Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and 1 Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA Mode 0 An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after executing a Software reset sequence An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non Ultra DMA Modes after executing a Power on or hardware reset Both the host and device perform a CRC function during an Ultra DMA burst At the end of an Ultra DMA burst the host sends the its CRC data to the device The device compares its CRC data to the data sent from the host If the two values do not match the device reports an error in the error register at the end of the command If an error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that
55. 5 and 5 6 3 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 The device shall initiate termination of an Ultra DMA burst by not generating DSTROBE edges The device shall negate DMARQ no sooner than tss after generating the last DSTROBE edge The device shall not assert DMARQ again until after the Ultra burst is terminated The device shall release DD 15 0 no later than taz after negating DMARQ The host shall assert STOP within t after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated The host shall negate HDMARDY within t after the device has negated DMARQ The host shall continue to negate HDMARDY until the Ultra DMA burst is terminated Steps 4 and 5 may occur at the same time The host shall drive DD 15 0 no sooner than tzay after the device has negated DMARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 If DSTROBE is negated the device shall assert DSTROBE within t after the host has asserted STOP No data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra burst is terminated If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 6 the host shall place the result of its CRC calculation on DD 15
56. 6 viii C141 E093 01EN 9 221 5 2 2 5 2 3 5 3 5 3 1 5 3 2 5 3 3 5 4 5 4 1 5 4 2 5 4 3 5 4 4 5 4 5 3 9 5 5 1 5 5 2 5 5 3 5 5 3 1 5 5 3 2 5 5 3 3 5 5 3 4 5 5 4 5 5 4 1 5 5 4 2 5 5 4 3 5 5 4 4 5 5 5 5 5 6 5 6 5 6 1 5 6 2 5 6 3 5 6 3 1 5 6 3 2 5 6 3 3 5 6 3 4 W O eme Rie Ninn i ine eine Bde e deg ce da 5 6 Command block Yegisters 5 tie cies Aus er eie tees ties ns oti a ee pe o De Ae asa 5 8 Control BIGCK cueste et er ette ate et 5 13 Host Commands 5 enne n PRU 5 13 Command code and parameters eese 5 14 Command descriptions t e PHI ERATIS EUER 5 16 aote equ t teet o tee ed 5 61 Command Protocol eor mete merit 5 62 Data transferring commands from device to 03 5 62 Data transferring commands from host to 4 1 5 64 Commands without data transfer 5 66 OthercommandS 5 67 DMA data transfer 4 5 67 Ulti DMA feat re set ii o RI Ret Lee 5 69 cad M PD P 5 69 Phases of operation io cogn denas oun eene deme 5 70 Ultra DMA data in 0 5 70 Initiating an Ultra DMA data in burst nene nre 5 70 transfer ee eene et eri ect e t Peg Pete dg eeu eget ea eg sy 5 71 Pausing an Ultra DMA data in burst
57. 8 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated The device shall assert DMARQ to initiate an Ultra DMA burst Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP The host shall assert HSTROBE The host shall negate CSO CS1 DA2 DAI and DAO The host shall keep CSO CS1 DA2 DAI and DAO negated until after negating DMACK at the end of the burst Steps 3 4 and 5 shall have occurred at least tack before the host asserts DMACK The host shall keep DMACK asserted until the end of an Ultra DMA burst The device may negate DDMARDY tzjorpy after the host has asserted DMACK Once the device has negated DDMARDY the device shall not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst The host shall negate STOP within after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE C141 E093 01 EN 5 5 42 5 5 4 3 9 The device shall assert DDMARDY within tj after the host has negated STOP After asserting DMARQ and DDMARDY the device shall not negate either signal until after the first negation of HSTROBE by the host 10 The host shall drive the first word of the data transfer onto DD 15 0 This step may occur any time during Ultra DMA burst initiation 11 To transfer the first word of data the host shall negate HSTROBE no sooner than t after
58. 8 Features Register values subcommands and functions sss 5 49 5 9 Format of device attribute value data eese nnne 5 52 5 10 Format of insurance failure threshold value data eee 5 53 5 11 SMART error log data format 5 56 5 12 SMART self test log d ta form t impendere 5 58 5 13 Command code and parameters esee eene eee nennen nnne enne 5 61 5 14 Recommended series termination for Ultra DMA eese 5 79 5 15 Ultra DMA data burst timing requirements nennen nennen 5 83 6 1 Default p rameters benannt een a etta velie io 6 6 C141 E093 01 EN xiii This page is intentionally left blank CHAPTER 1 DEVICE OVERVIEW 1 1 Features 1 2 Device Specifications 1 3 Power Requirements 1 4 Environmental Specifications 1 5 Acoustic Noise 1 6 Shock and Vibration 17 Reliability 1 8 Error Rate 1 9 Media Defects Overview and features are described in this chapter and specifications and power requirement are described The MPE3xxxAE series are a 3 5 inch hard disk drive with a built in ATA controller The disk drive is compact and reliable 1 1 1 1 1 1 2 3 Features Functions and performance Compact The disk has 1 or 2 disks of 95 mm 3 5 inches diameter and its height is 26 1 mm 1 inch Large capacity The disk drive can record up to 8
59. ARDOR IIR De ELI I MEE eee AS ELITS 2 3 2 2 2 Tdrv connection edet etie ee ee defects 2 3 2 2 3 2 drives Connection uoo eun A Oni OB Amo ee eA gnis 2 3 CHAPTER3 INSTALLATION CONDITIONS 1 eterne 3 1 3 1 Beate oa ess 3 1 3 2 Mounting npe T 3 3 3 3 Cable Connections is oe HERE IHE de eee rb petet 3 7 3 3 T tDeyiceCollie ctor os dedu UR D UR UR NB 3 7 3 3 2 Cable connector specifications ere tee eh ea ee 3 8 3 3 37 Deyic Cone Chon inesse p eei ea acea i eR re ERROR 3 8 3 3 4 Power supply connector 3 9 3 3 5 System configuration for Ultra DMA 3 9 C141 E093 01 EN vii 3 4 Jumper Settings unos e ER e ER e tigre eerte ee eae e tpe o Pope deba 3 12 3 4 1 Location of setting jumpers 3 12 3 4 2 Factory default setting ente ei tenet ertet 3 13 34 3 Jumper configuration sette intu enin deb PEDE Aires 3 13 CHAPTER4 THEORY OF DEVICE OPERATION mee 4 1 4 1 Qutlitie to ste ettet ee e e v e m e 4 1 4 2 SubASseMbDHES uc er t v eet t 4 1 42 1 4 1 4 2 2 iine m cup tues te a t LO DX eee e e opes 4 2 ADS Spun serere eerte tees 4 2 LUE MED UE EIE ETE 4 2 4 2 5 Airfilter isse ee dede rete et i hee e e E Ee Rr ete e 4 3 4 3 Contisurationic
60. B Max LBA 1F44 CL Max cylinder LSB Max LBA 1 3 sector Max LBA LSB C141 E093 01 EN 5 59 30 5 60 READ NATIVE MAX ADDRESS F8 This command posts the maximum address intrinsic to the device which can be set by the SET MAX ADDRESS command Upon receipt of this command the device sets the BSY bit and indicates the maximum address in the DH CH CL and SN registers Then it clears BSY and generates an interrupt At command issuance I O registers setting contents 7 TT T8T 8 1 5 1 4 1F34 SN 1 2 1 1 At command completion I O registers contents to be read I Max head MS 1F54 CH Max cylinder MSB Max LBA 1F44 CL Max cylinder LSB Max LBA 1F34 SN Max sector Max LBA LSB 1F24 SC XX 1FIg ER Error information C141 E093 01 EN 5 3 3 Error posting Table 5 13 lists the defined errors that are valid for each command Table 5 13 Command code and parameters IRADSECTORS wurESECTORS Reap MULTIPLE warmEMUTLE v WuTEDMA v j v v ES v RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS lt lt lt lt lt EE lt V FORMATTRACK ire IDLE STANDBY STANDBYIMMEDIATE sp CHECK POWER MODE v BLUSH CACHE
61. BA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register WRITE MULTIPLE 5 This command is similar to the WRITE SECTOR S command The device does not generate interrupts assertion of the INTRQ signal on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command The implementation of the WRITE MULTIPLE command is identical to that of the WRITE SECTOR S command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts In the WRITE MULTIPLE command operation the DRQ bit of the Status register is required to set only at the start of the data block not on each sector The number of sectors block count to be transferred without interruption is specified by the SET MULTIPLE MODE command The SET MULTIPLE MODE command should be executed prior to the WRITE MULTIPLE command When the WRITE MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the value of the
62. Grounded I indicates input signal from the host to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device C141 E093 01 EN 5 5 5 2 Logical Interface The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports the LBA mode When the host system specifies the LBA mode by setting bit 6 in the Device Head register to 1 HS3 to HSO bits of the Device Head register indicates the head No under the LBA mode and all bits of the Cylinder High Cylinder Low and Sector Number registers are LBA bits The sector No under the LBA mode proceeds in the ascending order with the start point of LBAO defined as follows LBAO Cylinder 0 Head 0 Sector 1 Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command the sector LBA address is not changed LBA Cylinder No x Number of head Head No x Number of sector track Sector No 1 I O registers Communication between the host system and the device is done through input output I O registers of the device These I O registers be selected by the coded signals CSO CS1 and DAO to DA2 from the host system Table 5 3 shows the coding address and the function of I O
63. MA Host system that support Ultra DMA transfer modes greater than mode 2 shall not share I O ports They shall provide separate drivers and separate receivers for each cable a The 80 conductor cable assemblies shall be used for systems operating at Ultra DMA modes greater than 2 The 80 coductor cable assemblies may be used in place of 40 conductor cable assemblies to improve signal quality for data transfer modes that do not require an 80 conductor cable assembly And the 80 conductor cable assembly shall meet the following specifications 1 The assembly utilizes a fine pitch cable to double the number of conductors available to the 40 pin connector The grounds assigned by the interface are commoned with the additional 40 conductors to provide a ground between each signal line and provide the effect of a common ground plane 2 The cable assembly may contain up to 3 connectors which shall be uniquely colored as follows All connectors shall have position 20 blocked e The System Board Connector shall have a Blue base and Black retainer Pin 34 PDIAG CBLID shall be connected to ground and shall not be wired to the cable assembly e Connector Device 0 shall have a Black base and Black retainer e Connector Device 1 shall have a Gray base and Black retainer Pin 28 CSEL shall not be connected to the cable contact 28 may be removed to meet this requirement e The cable assembly may be printed with connector identifiers
64. MART s m Es 011 FLUSH CACHE SET MAX ADDRESS EXESE READ NATIVE MAX ADDRESS PXENE Notes FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sector Number Register R Oor 1 Y Necessary to set parameters Y Necessary to set parameters under the LBA mode N Necessary to set parameters The parameter is ignored if it is set N May set parameters D The device parameter is valid and the head parameter is ignored D The command is addressed to the master device but both the master device and the slave device execute it X Do not care C141 E093 02EN 5 15 5 3 2 5 16 Command descriptions The contents of the I O registers to be necessary for issuing a command and the example indication of the I O registers at command completion are shown as following in this subsection Example READ SECTOR S At command issuance I O registers setting contents 1F74 CM EAE 1F54 CH Start cylinder address MSB LBA 1F3y SN Start sector No LBA LSB At command completion I O registers contents to be read seien sopa sc 1F74 ST Error information 1F54 CH End cylinder address MSB LBA 1 4 End cylinder address LSB LBA 1F3y SN End sector No LBA LSB CM Command register FR Features register DH Device Head register ST Status register CH Cylinder High register ER Error register CL Cylinder Lo
65. ROBE 3 Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP 4 The host shall negate HDMARDY 5 The host shall negate CSO CS1 DA2 DAI and DAO The host shall keep CSO CS1 DA2 DAI and DAO negated until after negating DMACK at the end of the burst 6 Steps 3 4 and 5 shall have occurred at least tack before the host asserts DMACK The host shall keep DMACK asserted until the end of an Ultra DMA burst 7 The host shall release DD 15 0 within taz after asserting DMACK 8 The device may assert DSTROBE tzjorpy after the host has asserted DMACK Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK at the end of an Ultra DMA burst 9 The host shall negate STOP and assert HDMARDY within tgny after asserting DMACK After negating STOP and asserting HDMARDY the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device 1 after the first data word has been received 10 The device shall drive DD 15 0 no sooner than tz4p after the host has asserted DMACK negated STOP and asserted HDMARDY C141 E093 01 EN 5 5 3 2 5 5 3 3 11 The device shall drive the first word of the data transfer onto DD 15 0 This step may occur when the device first drives DD 15 0 in step 10 12 To transfer the first word of data the device shall negate DS
66. RQ Signal shall be in a high impedance state Chip select signal decoded from the host address bus This signal is used by the host to select the command block registers Chip select signal decoded from the host address bus This signal is used by the host to select the control block registers Binary decoded address signals asserted by the host to access task file registers Key pin for prevention of erroneous connector insertion This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration This signal indicates that the slave device has been completed self diagnostics This signal is pulled up to 5 V through 10 kQ resistor at each device This signal is used to detect the cable type 80 or 40 conductor cable installed in the system This signal is pulled up to 5 V through 10 kQ resistor at each device This is a time multiplexed signal that indicates that the device is active and a slave device is present This signal is pulled up to 5 V through 10 kQ resistor at each device C141 E093 01 EN signal IORDY DDMARDY DSTROBE CSEL DMACK DMARQ GND Note Description This signal is negated to extend the host transfer cycle of any host register access Read or Write when the device is not ready to respond to a data transfer request DDMARDY is a flow control signal for Ultra DMA data out bursts This signal is asserted by the devi
67. SS F9 This command allows the maximum address accessible by the user to be set in LBA or CHS mode Upon receipt of the command the device sets the BSY bit and saves the maximum address specified in the DH CH CL and SN registers Then it clears BSY and generates an interrupt The new address information set by this command is reflected in Words 1 54 57 58 60 and 61 of IDENTIFY DEVICE information If an attempt is made to perform a read or write operation for an address beyond the new address space an ID Not Found error will result When SC register bit 0 VV Value Volatile is 1 the value set by this command is held even after power on and the occurrence of a hard reset When the VV bit is 0 the value set by this command becomes invalid when the power is turned on or a hard reset occurs and the maximum address returns to the value default value if not set most lately set when VV bit 1 After power on and the occurrence of a hard reset the host can issue this command only once when VV bit 1 If this command with VV bit 1 is issued twice or more any command following the first time will result in an Aborted Command error At command issuance I O registers setting contents ori 1 5 Max cylinder MSB Max LBA 1F44 CL Max cylinder LSB Max LBA 1 3 sector Max LBA LSB At command completion I O registers contents to be read I Max heal MSP 1F5y CH Max cylinder MS
68. Sector Count should not be 0 If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block If an error occurs the subsequent block shall not be transferred Interrupts are generated when the DRQ bit of the Status register is set at the beginning of each block or partial block C141 E093 01 EN 5 23 7 The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined To obtain a valid error information the host should retry data transfer as an individual requests At command issuance I O registers setting contents 1F7y CM 1 1 0 0 0 1 0 1 1F6y DH Start head No LBA MSB 1 5 Start cylinder No MSB LBA 1F44 CL
69. Start cylinder No LSB LBA 1 3 Start sector No LBA LSB 1F24 SC Transfer sector count IFI amp FR XX At command completion I O registers contents to be read IS DH End cal No ALBA MS 1 5 End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 004 1FIg ER Error information Note When the command terminates due to error only the DV bit and the error information field are valid WRITE DMA X CA or X CB This command operates similarly to the WRITE SECTOR S command except for following events e data transfer starts at the timing of DMARQ signal assertion e device controls the assertion or negation timing of the DMARQ signal e device posts a status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the WRITE SECTOR S command A host system can be select the following transfer mode using the SET FEATURES command C141 E093 01 EN 8 1 Multiword DMA transfer mode 2 Sets the FR register X 03 and SC register X 22 by the SET FEATURES
70. TROBE within tps after the host has negated STOP and asserted HDMARDY The device shall negate DSTROBE no sooner than tpys after driving the first word of data onto DD 15 0 The data in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 3 and 5 6 3 2 for specific timing requirements 1 The device shall drive a data word onto DD 15 0 2 The device shall generate a DSTROBE edge to latch the new word no sooner than tpys after changing the state of DD 15 0 The device shall generate a DSTROBE edge no more frequently than tcyc for the selected Ultra DMA Mode The device shall not generate two rising or two falling DSTROBE edges more frequently than 2tcyc for the selected Ultra DMA mode 3 The device shall not change the state of DD 15 0 until at least tpyg after generating a DSTROBE edge to latch the data 4 The device shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first Pausing an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 4 and 5 6 3 2 for specific timing requirements a Device pausing an Ultra DMA data in burst 1 The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 The device shall pause an Ultra DMA burst by not generatin
71. a DAP 3 After reading the requested data and transferring the requested data to the host system had been completed the disk drive continues to read till a certain amount of data is stored HAP stopped Rag eoo last Read Ahead Data stopped DAP 4 Following shows the cache enabled data for next read command Cache enabled data Start LBA Last LBA C141 E093 01 EN 6 15 3 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command the disk drive tries to fill the buffer space with the read ahead data a Sequential command just after non sequential command 1 Atreceiving the sequential read command the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data HAP Mis hit data Empty data DAP 2 disk drive transfers the requested data that is already read to the host system with reading the requested data HAP V Mis hit data Empty data DAP 3 After completion of the reading and transferring the requested data to the host system the disk drive performs the read ahead operation continuously till a certain amount of data is stored HAP gt 7 Read E Mis hit data equ sted dar ahead data data DAP 6 16 C141 E093 01EN b Sequen
72. at the end of the command A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMa burst in the same command If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred For READ DMA or WRITE DMA commands When a CRC error is detected it shall be reported by setting both ICRC and ABRT bit 7 and bit 2 in the Error register to one ICRC is defined as the Interface CRC Error bit The host shall respond to this error by re issuing the command A host may send extra data words on the last Ultra DMA burst of a data out command If a device determines that all data has been transferred for a command the device shall terminate the burst A device may have already received more data words than were required for the command These extra words are used by both the host and the device to calculate the CRC but on an Ultra DMA data out burst the extra words shall be discarded by the device C141 E093 01EN D The CRC generator polynomial is G X 16 X12 X5 1 Note Since no bit clock is available the recommended approach for calculating CRC is to use a word clock derived from the bus strobe The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DDO is shifted in first and DD15 is shifted
73. ation 250G typical no damage 11 ms duration 75G no damage 1 7 1 2 3 Reliability Mean time between failures MTBF The mean time between failures MTBF is 500 000 POH power on hours or more operation 24 hours day 7 days week This does not include failures occurring during the first three months after installation MTBF is defined as follows Total operation time in all fields MTBF number of device failure in all fields Disk drive defects refers to defects that involve repair readjustment or replacement Disk drive defects do not include failures caused by external factors such as damage caused by handling inappropriate operating environments defects in the power supply host system or interface cable Mean time to repair MTTR The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member CSS cycle The number of CSS must be less than 40 000 C141 E093 01 EN 1 9 4 5 1 8 1 2 1 9 1 10 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occurs first Refer to item 3 in Subsection 3 2 for the measurement point of the DE surface temperature Data assuranc
74. bration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks 4 1 4 2 Outline This chapter consists of two parts First part Section 4 2 explains mechanical assemblies of the disk drive Second part Sections 4 3 through 4 7 explains a servo information recorded in the disk drive and drive control method Subassemblies The disk drive consists of a disk enclosure DE and printed circuit assembly PCA The DE contains all movable parts in the disk drive including the disk spindle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 5 The PCA contains the control circuits for the disk drive The disk drive has one PCA For details see Sections 4 3 Disk The DE contains the disks with an outer diameter of 95 mm The MPE3043AE and MPE3084AE have 1 disk The MPE3173AE has 2 disks The head contacts the disk each time the disk rotation stops the life of the disk is 40 000 contacts or more Servo data is recorded on each cylinder total 96 Servo data written at factory is read out by the read write head For servo data see Section 4 7 C141 E093 01 EN 4 1 Head Figure 4 1 shows the read write head structures The Numerals 0 to 7 indicate read write heads These heads are raised from the disk
75. by writing necessary parameters in related registers in the command block and writing a command code in the Command register The device can accept the command when the BSY bit is 0 the device is not in the busy status The host system can halt the uncompleted command execution only at execution of hardware or software reset When the BSY bit is 1 or the DRQ bit is 1 the device is requesting the data transfer and the host system writes to the command register the correct device operation is not guaranteed C141 E093 01 EN 5 13 5 3 1 Command code and parameters Table 5 4 lists the supported commands command code and the registers that needed parameters are written Table 5 4 Command code and parameters 1 of 2 Command code Bit Parameters used Command name 5 1 0 FR sc sN cv pn READ SECTOR S o o READ MULTIPLE 1 rjojojo r o o READ DMA READ VERIFY SECTOR S o o R 1 2 N N NIN NIN NIN NIN DE gt SRG EIEIZEREIES DD E row xx po N N 2 2 2 110 0 1 141 IDLE IMMEDIATE 1101011 1 1 1111110 0 1 STANDBY 1101011 1 1 1111110 0 1 5 14 C141 E093 01 EN 2 2 2 2 2 2 Table 5 4 Command code and parameters 2 of 2 Command name 7 5 STANDBY IMMEDIATE 1 NINININ 1 i SLEEP 1 1 1 1 1 i CHECK POWER MODE S
76. ccording to the differentiation aberration Driver circuit The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor VCM current sense resistor CSR This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back C141 E093 01 EN 4 15 1 2 3 Data surface servo format Figure 4 5 describes the physical layout of the servo frame The three areas indicated by 1 to 3 in Figure 4 6 are described below Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops and the rotational speed of the spindle can be controlled on this cylinder area for head moving Data area This area is used as the user data area and SA area Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving Servo frame format As the servo information the drive uses the two phase servo generated from the gray code and Pos A to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo frame consists of 5 blocks write read recovery servo mark gray code Pos A to D and PAD Figure 4 6 shows the servo frame format C141 E093 01 EN 0 18 24 S 0 84 us 0
77. ce C141 E093 01 EN 1 7 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Temperature Operating 5 C to 55 C ambient 5 C to 60 C disk enclosure surface Non operating 40 to 60 C Thermal Gradient 20 C hour or less Operating 8 to 80 RH Non condensing Non operating 5 to 85 RH Non condensing Maximum Wet Bulb 29 C Altitude relative to sea level Operating 60 to 3 000 m 200 to 10 000 ft Non operating 60 to 12 000 m 200 to 40 000 ft 1 5 Acoustic Noise Table 1 5 lists the acoustic noise specification Table 1 5 Acoustic noise specification Sound Power MPE3043AE per ISO 7779 and MPE3084AE MPESIJSAB ISO9296 Typical at 1m Idle mode DRIVE 3 4 bels 3 5 bels READY Sound Pressure Idle mode DRIVE 29 dBA 30 dBA Typical at 1m READY Seek mode Random 35 dBA 36 dBA Seek mode Random 4 0 bels 4 bels 1 8 C141 E093 01 EN 1 6 Shock and Vibration Table 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Vibration swept sine one octave per minute Operating 5 to 300 Hz 0 5G 0 peak without non recovered errors Non operating 5 to 400 Hz 4G 0 peak no damage Shock half sine pulse operating 2 ms duration 30G without non recovered error 11 ms duration 10G without non recovered error Shock half sine pulse non operating e 2 ms dur
78. ce to indicate to the host that the device is ready to receive Ultra DMA data out bursts The device may negate DDMARDY to pause an Ultra DMA data out burst DSTROBE is the data in strobe signal from the device for an Ultra DMA data in burst Both the rising and falling edge of DSTROBE latch the data from DATA 0 15 into the host The device may stop generating DSTROBE edges to pause an Ultra DMA data in burst This signal to configure the device as a master or a slave device When CSEL signal is grounded the IDD is a master device When CSEL signal is open the IDD is a slave device This signal is pulled up with 10 kQ resistor The host system asserts this signal as a response that the host system receive data or to indicate that data is valid This signal is used for DMA transfer between the host system and the device The device asserts this signal when the device completes the preparation of DMA data transfer to the host system at reading or from the host system at writing The direction of data transfer is controlled by the IOR and IOW signals In other word the device negates the DMARQ signal after the host system asserts the DMACK signal When there is another data to be transferred the device asserts the DMARQ signal again When the DMA data transfer is performed IOCW16 CS0 and CS1 signals are not asserted The DMA data transfer is a 16 bit data transfer The device has a 10 kO pull down resistor on this signal
79. cific timing requirements 1 2 3 4 5 6 7 8 The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges The host shall assert STOP no sooner than tss after it last generated an HSTROBE edge The host shall not negate STOP again until after the Ultra DMA burst is terminated The device shall negate DMARQ within t after the host asserts STOP The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The device shall negate DDMARDY with tj after the host has negated STOP The device shall not assert DDMARDY again until after the Ultra DMA burst termination is complete If HSTROBE is negated the host shall assert HSTROBE with t after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than tmu after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than tpys after placing the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK C141 E093 01 EN b 9 10 11 12 The device shall compare the CRC data received from the host with the r
80. d register contains a command code being sent to the device After this register is written the command execution starts immediately Table 5 3 lists the executable commands and their command codes This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written C141 E093 01EN 52 3 1 2 5 3 Control block registers Alternate Status register X 3F6 The Alternate Status register contains the same information as the Status register of the command block register The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset Device Control register X 3F6 The Device Control register contains device interrupt and software reset Bit 2 SRST is the host software reset bit When this bit is set the device is held reset state When two device are daisy chained on the interface setting this bit resets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state Host Commands The host system issues a command to the device
81. d to the host system once by requesting with the command that are object of caching operation When the sector data requested by the host does not finish storing in the buffer for read cache it is not object of caching operation And also when the sequential hit occurs continuously the caching data required by the host becomes invalid Invalidating caching data Caching data in the data buffer is invalidated in the following case 1 Commands other than the following commands are issued all caching data are invalidated READ SECTOR S READ DMA READ MULTIPLE READ VERIFY 2 Caching operation is disabled by the SET FEATURES command 3 Command issued by the host is terminated with an error 4 Soft reset or hard reset is executed or power is turned off C141 E093 01 EN 6 5 3 1 Usage of read segment This subsection explains the usage of the read segment buffer at following cases Miss hit no hit A lead block of the read requested data is not stored in the data buffer The requested data is read from the disk media 1 Sets the host address pointer HAP and the disk address pointer DAP to the sequential address to the last read segment HAP v Segment only for read DAP 2 Transfers the requested data that already read to the host system with reading the requested data from the disk media Stores the read requested HAP data upto this point Dv FA Empty are
82. d write test and work RAM read write test When the self diagnosis terminates successfully the disk drive starts the spindle motor The disk drive executes self diagnosis data buffer read write test after enabling response to the ATA bus After confirming that the spindle motor has reached rated speed the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM This unlocks the heads which are parked at the inner circumference of the disks The disk drive positions the heads onto the SA area and reads out the system information The disk drive executes self seek calibration This collects data for VCM torque and mechanical external forces applied to the actuator and updates the calibrating value The drive becomes ready The host can issue commands C141 E093 01 EN a Self diagnosis 1 MPU bus test nner register write read test Work RAM write read test Vv The spindle motor starts 4 b Self diagnosis 2 Data buffer write read test i c Confirming spindle motor speed Vv Release heads from actuator lock 4 d Initial on track and read out of system information Execute self calibration f Drive ready state command waiting state End Figure 4 3 Power on operation sequence C141 E093 01 EN 4 5 4 5 1 1 2 Self calibration The disk drive occa
83. e 4 1 Self calibration execution timechart Time etapsed Time lapsed cacoumutated 8 7 About 30 minutes About 90 minutes About 30 minutes About 120 minutes About 30 minutes About 150 minutes EM Command processing during self calibration If the disk drive receives a command execution request from the host while executing self calibration according to the timechart the disk drive terminates self calibration and starts executing the command precedingly In other words if a disk read or write service is necessary the disk drive positions the head to the track requested by the host reads or writes data and restarts calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 100 ms C141 E093 01 EN 4 9 4 6 1 2 Read write Circuit The read write circuit consists of the read write preamplifier PreAMP the write circuit the read circuit and the synthesizer in the read channel RDC Read write preamplifier PreAMP One PreAMP is mounted on the FPC The PreAMP consists of an 4 or 8 channel read preamplifier and a write current switch and senses a write error Each channel is connected to each data head The head IC switches the heads by the serial port SDEN SCLK SDATA The IC generates a write error sense signal WUS when a write error occurs due to head short circ
84. e 6 11 Alternate cylinder assignment eren ener 6 12 Data buffer configuration Joe eerte HERE 6 13 C141 E093 01 EN TABLES page 1 1 Specifications us eec Ee S e edet etes 1 4 1 2 Model names and product 1 5 1 3 Current and power 41551 nnne ener 1 6 1 4 Environmental specifications 1 8 1 5 Acoustic noise specification 1 8 1 6 Shock and vibration specification scrisese 1 9 3 1 Surface temperature measurement points and standard 3 5 3 2 Cable connector specifications esses eene nne 3 8 4 1 Self calibration execution 4 9 4 2 Write clock frequency and transfer rate of each zone 4 12 5 1 Interface signals a n hag ee dy ad eda epe dep tester eee 5 2 3 2 Signal assignment on the interface connector eese eren 5 3 5 3 ice tete o toe D ete te t tetur cem ieu mre etim ect eel eeu Ln 5 7 5 4 Command code and parameters nisi pee ere 5 14 5 5 Information to be read by IDENTIFY DEVICE command eee 5 30 5 6 Features register values and settable modes 4 5 35 5 7 DIASTOS HC COG io eene 5 39 5
85. e disk drive does not perform the read ahead operation If the disk drive receives a full hit command while performing the read ahead operation the disk drive starts transfering the requested data without stopping the read ahead operation 1 In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command the disk drive sets the HAP to the address of which the hit data is stored Last position at previous read command HAP HAP set to hit position for data transfer Cache data BZ pal pit du YA Cache data DAP A Last position at previous read command 2 The disk drive transfers the requested data but does not perform the read ahead operation HAP stopped Cache data pa pic du Cache data Partially hit A part of requested data including a lead sector are stored in the data buffer The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data and reads remaining requested data from the disk media directly Following is an example of partially hit to the cache data Cache data Start LBA Last LBA C141 E093 01 EN 1 The disk drive sets the HAP to the address where the partially hit data is stored and sets the DAP to the address just after the partially hit data T DAP 2 The disk drive starts trans
86. e in the event of power failure Except for the data block being written to the data on the disk media is assured in the event of any power supply abnormalities This does not include power supply abnormalities during disk media initialization formatting or processing of defects alternative block assignment Error Rate Known defects for which alternative blocks can be assigned are not included in the error rate count below It is assumed that the data blocks to be accessed are evenly distributed on the disk media Unrecoverable read error Read errors that cannot be recovered by read retries without user s retry and ECC corrections shall occur no more than 10 times when reading data of 10 bits Read retries are executed according to the disk drive s error recovery procedure and include read retries accompanying head offset operations Positioning error Positioning seek errors that can be recovered by one retry shall occur no more than 10 times in 10 seek operations Media Defects Defective sectors are replaced with alternates when the disk is formatted prior to shipment from the factory low level format Thus the host sees a defect free device Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors Chapter 6 describes the low level format at shipping C141 E093 01 EN CHAPTER 2 DEVICE CONFIGURATION 2 1 Device Configuration 2 2 Syste
87. e spindle of the device is already rotating the spin up sequence shall not be implemented If the contents of the Sector Count register is other than 0 the automatic power down function is enabled and the timer starts countdown immediately When the timer reaches the specified time the device enters the standby mode If the contents of the Sector Count register is 0 the automatic power down function is disabled Enabling the automatic power down function means that the device automatically enters the standby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts countdown after completion of the command execution The period of timer count is set depending on the value of the Sector Count register as shown below 254 to 255 X FE to X FF At command issuance I O registers setting contents 1F74 CM X 97 or X E3 1F54 CH Xx 1F44 CL XX 1F3y SN XX 1F24 SC Period of timer IFI amp FR XX C141 E093 01 EN 5 43 At command completion I O registers contents to be read mem i To Ts oe 1F5y CH 1F4 CL XX 1F34 SN XX 1F24 SC XX 1 15 Error information 23 IDLE IMMEDIATE 95 or X E1 Upon receipt of this comma
88. e write operation the command execution is stopped Then when the drive receives the next command it generates an interrupt of abnormal end However an interrupt of abnormal end is not generated when a write automatic assignment succeeds However since the host may issue several write commands before the drive generates an interrupt of abnormal end the host cannot recognize that the occurred error is for which command generally Therefore it is very hard to retry the unrecoverable write error for the host in the write cache operation generally So take care to use the write cache function C141 E093 01 EN Comments concerning this manual can be directed to one of the following addresses FUJITSU LIMITED Business Planning Solid S quare East Tower 580 Horikawa cho S aiwai ku Kawasaki 210 0913 J apan TEL 81 44 540 4056 FAX 81 44 540 4123 FUJITSU COMPUTER PRODUCTS OF AMERICA INC 2904 Orchard P arkway San J ose California 95134 2009 U S A TEL 1 408 432 6333 FAX 1 408 432 3908 FUJITSU CANADA INC 2800 Matheson Blvd East Mississauga Toronto Ontario LAW 4X5 CANADA TEL 1 905 602 5454 FAX 1 905 602 5457 FUJITSU EUROPE LIMITED 2 Longwalk Road Stockley Park Uxbridge Middlesex UB11 1AB ENGLAND TEL 44 81 573 4444 FAX 44 81 573 2643 FUJITSU DEUTSCHLAND GmbH Frankfurter Ring 211 80807 M nchen GERMANY TEL 49 89 323780 FAX 49 89 32378100 FUJITSU NORDIC AB Kung Hans Vag 12 S 192 68 So
89. ed commands are invalid ignored in this mode Power commands The following commands are available as power commands e IDLE e IDLE IMMEDIATE e STANDBY e STANDBY IMMEDIATE e SLEEP e CHECK POWER MODE Defect Management Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatting at the factory shipment All the user space area are formatted at shipment from the factory based on the default parameters listed in Table 6 1 C141 E093 01 EN 6 4 Spare area Following two types of spare area are provided in the user space 1 Spare sector for sector slip used for alternating defective sectors at formatting in shipment in case that a physical track contains one or two defective sectors 2 sectors track 2 Spare cylinder for alternative assignment used for alternative assignment for the third and subsequent defective sectors in case that a physical track contains three or more defective sectors and also used by automatic alternative assignment 1 cylinder drive 6 4 2 Alternating defective sectors The two alternating methods described below are available 1 Sector slip processing A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in the formatting
90. ee note Device address bit 0 Device address bit 1 Device address bit 2 DMA acknowledge DMA request Interrupt request T O read DMA ready during Ultra DMA data in bursts Data strobe during Ultra DMA data out bursts T O ready DMA ready during Ultra DMA data out bursts Data strobe during Ultra DMA data in bursts DIOR HDMARDY HSTROBE IORDY DDMARDY DSTROBE gt STOP PDIAG CBLID RESET I O write Stop during Ultra DMA data bursts Passed diagnostics see note Cable type detection T f 11111 121 1111111112111 ye ye it it je 1 bee ab Reset gt Note See signal descriptions C141 E093 01EN 5 1 2 Signal assignment on the connector Table 5 2 shows the signal assignment on the interface connector Table 5 2 Signal assignment on the interface connector DIOW STOP DIOR HDMARDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DAI DAO CS0 DASP DATA9 DATAIO DATAII DATAI2 DATAI13 DATAI4 DATAIS KEY GND GND GND CSEL GND reserved PDIAG CBLID DA2 CS1 GND signal Description RESET I Reset signal from the host This signal is low active and is asserted for a minimum of 25 us during power on The device has a 10 kQ pull up resistor on this signal DATA 0 15 IO Sixteen bit bi directional data bus between the host and the device These signals are used for data transfer DIOW STOP I DIOW is the strobe signal asserted by the host to write device r
91. egisters or the data port DIOW shall be negated by the host prior to initiation of an Ultra DMA burst STOP shall be negated by the host before data is transferred in an Ultra DMA burst Assertion of STOP by the host during an Ultra DMA burst signals the termination of the Ultra DMA burst C141 E093 01 EN 5 3 signal DIOR HDMARDY HSTROBE INTRQ CS0 CS1 DA 0 2 KEY PIDAG CBLID DASP I O I O I O I O Description DIOR is the strobe signal asserted by the host to read device registers or the data port HDMARDY is a flow control signal for Ultra DMA data in bursts This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts The host may negate HDMARDY to pause an Ultra DMA data in burst HSTROBE is the data out strobe signal from the host for an Ultra DMA data out burst Both the rising and falling edge of HSTROBE latch the data from DATA 0 15 into the device The host may stop generating HSTROBE edges to pause an Ultra DMA data out burst Interrupt signal to the host This signal is negated in the following cases assertion of RESET signal Reset by SRST of the Device Control register Write to the command register by the host Read of the status register by the host Completion of sector data transfer without reading the Status register When the device is not selected or interrupt is disabled the INT
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93. el numbers MPE3043AE MPE3084AE MPE3173AE 7 Word 49 Capabilities Bit 15 14 Reserved Bit 13 Standby timer value 0 Standby timer values shall be by the device Bit 12 Reserved Bit 11 IORDY support 1 Supported Bit 10 IORDY inhibition 0 inhibition Bit 9 LBA support 1 Supported Bit 8 DMA support 1 Supported Bit 7 0 Vendor specific 8 Word 51 PIO data transfer mode Bit 15 8 PIO data transfer mode X 02 PIO mode 2 Bit 7 0 Vendor specific 9 Word 53 Enable disable setting of word 54 58 64 70 and 88 Bit 15 3 Reserved Bit 2 Enable disable setting of word 88 1 Enable Bit 1 Enable disable setting of word 64 70 1 Enable Bit 0 Enable disable setting of word 54 58 1 Enable 10 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bit 15 9 Reserved Bit 8 Multiple sector transfer 1 Enable Bit 7 0 Transfer sector count currently set by READ WRITE MULTIPLE without interrupt supports 2 4 8 and 16 sectors C141 E093 01 EN 5 31 Table 5 5 12 Word 63 Bit 15 8 Bit 7 0 13 Word 64 Bit 15 8 Bit 7 0 14 Word 80 Bit 15 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 15 Word 82 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16 Word 83 Bit 15 Bit 14 Bit 13 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Information to be read by IDENTIFY DEVICE command 3 of 4 Multiword
94. eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off frequency of the low pass filter and boost up gain are controlled from each DAC circuit in read channel by an instruction of the parallel data signal from MPU M1 The MPU optimizes the cut off frequency and boost up gain according to the transfer frequency of each zone Adaptive equalizer circuit This circuit is 10 tap adaptive digital FIR filter circuit that cosine equalizes the head read signal to the Extended Partial Response Class 4 EPR4 waveform Viterbi detection circuit The digital data output from the adaptive equalizer circuit is sent to the Viterbi detection circuit The Viterbi detection circuit demodulates data according to the survivor path sequence Data separator circuit The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit To write data the VFO circuit generates clocks in synchronization with the clock signals from a synthesizer 48 51 GCR decoder This circuit converts the 48 bits read data into the 51 bits NRZ data C141 E093 01 EN 4 11 Synthesizer circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zone
95. en if the drive fault prediction function is disabled Current attribute value Bit If this bit 1 it indicates the attribute that represents an error rate The current attribute value is the normalized raw attribute data The value varies between Olh and 64h The closer the value gets to Olh the higher the possibility of a failure The device compares the attribute values with thresholds When the attribute values are larger than the thresholds the device is operating normally Attribute value for the worst case so far This is the worst attribute value among the attribute values collected to date This value indicates the state nearest to a failure so far Raw attribute value Raw attributes data is retained Off line data collection status Bits 0 to 6 Indicates the situation of off line data collection according to the table below Bit 7 If this bit is 1 it indicates that the automatic off line data collection function is enabled 0 fine daa colecionionorsaed OOO Off line data collection has been suspended by a command interrupt Off line data collection has been aborted by a command interrupt 6 Off line data collection has been aborted by a fatal error C141 E093 01 EN e Self test execution status Bits 0 to 3 Indicates the rest of self test in 0 to 9 corresponding 0 to 90 Bit4to 7 Indicates the self test execution status at the following table Self test Meaning execution status Self tes
96. en the host executes resetting the device correct operation is not guaranteed Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECALIBRATE SEEK READY VERIFY SECTOR S EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE FLUSH CACHE SECURITY ERASE PREPARE SECURITY FREEZE LOCK SMART except for SMART Read Attribute values and SMART Read Attribute Thresholds SET MAX ADDRESS e READ NATIVE MAX ADDRESS Figure 5 5 shows the protocol for the command execution without data transfer Command Parameter write V Status read BSY Ti DRDY INTRQ Figure 5 5 Protocol for the command execution without data transfer C141 E093 01 EN Other commands e READ MULTIPLE e SLEEP e WRITE MULTIPLE See the description of each command data transfer commands e READ DMA e WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR S or WRITE SECTOR S command except the point that the host initializes the DMA channel preceding the command issuance The interrupt processing for the DMA transfer differs the following point e interrupt processing for the DMA transfer differs the following point a b d 5 h The host writes any parameters to the Features Sect
97. ents The alert signal consists of an alert symbol and a signal word or just a signal word The following are the alert signals and their meanings AWARNING This indicates a hazarous situation likely to result in serious personal injury if the user does not perform the procedure correctly This indicates a hazarous situation could result in personal injury if the user does not perform the porocedure correctly This indicates a hazarous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly This alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly This indicates information that could help the user use the product more efficiently In the text the alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example IMPORTANT HA host adapter consists of address decoder driver and receiver ATA is an abbreviation of AT attachment The disk drive is conformed to the ATA 4 interface The main alert messages in the text are also listed in the Important Alert Items iv C141 E093 01EN LIABILITY EXCEPTION Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other d
98. esults of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DDMARDY within tiorpyz after the host has negated DMACK The host shall neither negate STOP nor negate HSTROBE until at least after negating DMACK The host shall not assert DIOW CSO CS1 DA2 DAI or DAO until at least tack after negating DMACK Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 11 and 5 6 3 2 for specific timing requirements D 2 3 4 5 6 7 8 9 10 The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred The device shall initiate Ultra DMA burst termination by negating DDMARDY The host shall stop generating an HSTROBE edges within of the device negating DDMARDY If the device negates DDMARDY within tsp after the host has generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than tsp after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of
99. evice rejects the READ MULTIPLE command with an ABORTED COMMAND error If an error occurs reading sector is stopped at the sector where the error occurred Command block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred and remaining number of sectors that had not transferred after the sector where the error occurred An interrupt is generated when the DRQ bit is set at the beginning of each block or a partial block C141 E093 01 EN Figure 5 1 shows an example of the execution of the READ MULTIPLE command e Block count specified by SET MULTIPLE MODE command 4 number of sectors in a block e READ MULTIPLE command specifies Number of requested sectors 9 Sector Count register 9 Number of sectors in incomplete block remainder of 9 4 1 v Command Issue Parameter Write Status read V Status read Status read BSY DRDY INTRQ PRG Sector 1302 0 355 5161718 9 transferred Partial gt gt Block Block block Figure 5 1 Execution example of READ MULTIPLE command At command issuance I O registers setting contents 1 5 1 4 1F34 SN 1 2 1 1 Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count
100. f a slave device is present the master device checks the PDIAG signal for up to 31 seconds to see if the slave device has completed the self diagnosis successfully After the slave device receives the software reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds then negated within 31 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal X 3F6 Reg X 0C ata X 00 Master device X 04 Status Reg BSY bit Max 31 sec 4 gt If the slave device is preset DASP is checked for up to 31 seconds Slave device BSY bit EM 1 ms PDIAG zu Max 30 sec A gt DASP Figure 6 3 Response to software reset 6 4 C141 E093 01 EN X 1F7 Reg Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present the master device checks the PDIAG signal for up to 6 seconds to see if the slave device has completed the self diagnosis successfully The master device does not check the DASP signal After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the
101. ferred like in the CHS mode are set The host system can select the DMA transfer mode by using the SET FEATURES command 1 Multiword DMA transfer mode 2 Sets the FR register X 03 and SC register X 22 by the SET FEATURES command 2 Ultra DMA transfer mode 2 Sets the FR register X 03 and SC register X 42 by the SET FEATURES command At command issuance I O registers setting contents Soc pa pls 1 5 Start cylinder No MSB LBA 1 4 Start cylinder No LSB LBA 1 3 Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR XX R Oorl C141 E093 01 EN 4 At command completion I O registers contents to be read IF DH End cal No ALBA MS 1 5 End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register READ VERIFY SECTOR S X 40 or X 41 This command operates similarly to the READ SECTOR S command except that the data is not transferred to the host system After all requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified
102. ferring partially hit data and reads lack data from the disk media at the same time HAP Requested data to be transferred stopped Fidi Lack data ctl tna E d taut pl DAP C141 E093 01EN 6 19 6 6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed When the drive receives a write command the drive starts transferring data of sectors requested by the host system and writing on the disk medium After transferring data of sectors requested by the host system the drive generates the interrupt of command complete Also the drive sets the normal end status in the Status register The drive continues writing data on the disk medium When all data requested by the host are written on the disk medium actual write operation is completed The drive receives the next command continuously If the received command is a sequential write data to be written by a command is logically sequent to data of previous command the drive starts data transfer and receives data of sectors requested by the host system At this time if the write operation of the previous command is still been executed the drive continuously executes the write operation of the next command from the sector next to the last sector of
103. g DSTROBE edges NOTE The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges If the device does not negate DMARQ in order to initiate ULTRA DMA burst termination the host shall negate HDMARDY and wait tgp before asserting STOP 3 The device shall resume an Ultra DMA burst by generating a DSTROBE edge b Host pausing an Ultra DMA data in burst 1 The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 The host shall pause an Ultra DMA burst by negating HDMARDY C141 E093 01 EN 5 71 3 4 5 The device shall stop generating DSTROBE edges within of the host negating HDMARDY If the host negates HDMARDY within tsp after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARDY greater than tsp after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and timing for the device The host shall resume an Ultra DMA burst by asserting HDMARDY 5 5 3 4 Terminating an Ultra DMA data in burst a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3
104. gure 3 5 shows the temperature measurement point Figure 3 5 Surface temperature measurement points Table 3 1 Surface temperature measurement points and standard values Measurement point Temperature C141 E093 01 EN 3 5 5 Service area Figure 3 6 shows how the drive must be accessed service areas during and after installation Mounting screw hole Mounting screw hole P side Cable connection Mode setting switches Mounting screw hole Figure 3 6 Service area 6 External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields C141 E093 01 EN 3 3 Cable Connections 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals e Power supply connector e interface connector CN1 Power supply connector CN1 Mode Setting Pins ATA interface connector Figure 3 7 Connector locations C141 E093 01 EN 3 3 2 Cable connector specifications Table 3 2 lists the recommended specifications for the cable connectors for Host system that do not support Ultra DMA modes greater than mode 2 For Host system that support Ultra DMA modes greater than mode 2 it is recommended to use the 80 conductor cable assembly The 80 conducto
105. h of the Ultra DMA Modes DMARQ device lui DMACK host B tack STOP host LLL tack y host Mmm tss ilt tioRDvz a 1 TWIT DD 15 0 XKXOO KKKK KKK CRO tack DAO DA1 DA2 CSO CS1 Note The definitions for the STOP HDMARD Y and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 13 Device terminating an Ultra DMA data in burst C141 E093 01 EN 5 87 5 6 3 6 Host terminating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device tu 1 host trp tack STOP host RSS 5 tack HDMARDY host tres tuu tu E tiorpyz DSTROBE 7 device SEDENT NINININI NI NINI NZ NI BOS SOO SOON _ 15 0 _ KKK EK tack DAO DA1 DA2 CSO CS1 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Host terminating an Ultra DMA data in burst 5 88 C141 E093 01 EN 5 6 3 7 Initiating an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device tu DMACK host tziorpy DDMARDY device HSTROBE host DD 15 0 host 7 NTN ONO IN ass a
106. he ATA interface section is inactive All I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents 1F7y CM X 99 or X E6 eT 1 5 1 4 1F34 SN 1 2 1 1 C141 E093 01 EN At command completion I O registers contents to be read 1F5y CH XX 1F4 CL XX 1F34 SN XX 1F24 SC XX 1 15 Error information 27 CHECK POWER MODE X 98 or X E5 The host checks the power mode of the device with this command The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector Number registers The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt Sector Count register Sector Number register During moving to standby mode Standby mode X 00 N A During returning from the standby mode Idle mode C141 E093 01 EN 5 47 28 At command issuance I O registers setting contents 1F74 CM X 98 or X ES Ts xv 9 1 5 1 4 1F34 SN 1 2 1 1 At command completion I O registers contents to be read mes Ts To Ts x 0 7 1F5y CH 1F4 CL XX 1F34 SN XX 1 2 X 00 80 X FF 1 15 Error information SMART
107. he drive status when received error commands according to the following table Bits 4 to 7 Vendor unique C141 E093 01 EN 5 57 umessms Active status or idle status BSY bit 0 Off line data collection being executed The host computer can issue the SMART Execute Off line Immediate sub command FR Register D4h and cause the device to execute a self test When the self test is completed the device saves the SMART self test log to the disk medium The host computer can issue the SMART Read Log Sector sub command FR Register 2 D5h SN Register 06h and can read the SMART self test log Table 5 12 SMART self test log data format 00 01 Self test log data format version number 02 Self test log 1 Self test mode SN Register Value 03 Self test execution status 04 05 Total power on time until the self test is completed hours Self test error No KIT to 0A Do SN LBA 0 019 to 19 Vendor unique unique 1A to 1F9 Self test log 2 to Each log data format is the same as that in 21 byte 02 to 19 Self test log 1 to 21 When executes self test the self test index value is incremented and the self test execution result is recorded in the self log test area specified by this value When the self test index exceeds 21 it returns to 01 C141 E093 01EN 29 e Self test index Indicates the latest self test log number If the self test has not been executed 00h is displayed SET MAX ADDRE
108. ical Average Read 9 5 ms typical Write 10 5 ms typical Maximum Read 18 ms typical Write 19 ms typical Start Stop time Start 0 rpm to Drive Read Typical 8 sec Maximum 16 sec Stop at Power Down Typical 20 sec Maximum 30 sec Interface ATA 4 Maximum Cable length 0 46 m Data Transfer Rate To From Media 20 3 to 34 4 MB s To From Host 16 7 MB s Max burst PIO mode 4 burst DMA mode 2 66 6 MB s Max burst ultra DMA mode 4 Data buffer 512 KB Physical Dimensions 26 1 mm max x 101 6 mm x 146 0 mm Height x Width x Depth 1 03 max x 4 0 x 5 75 Weight 620 g Capacity under the LBA mode Under the CHS mode normal BIOS specification formatted capacity number of cylinders number of heads and number of sectors are as follows Formatted Capacity No of Cylinder No of Heads 895 45520 16583 1 4 C141 E093 02EN 1 2 2 Model and product number Table 1 2 lists the model names and product numbers Table 1 2 Model names and product numbers Model Name Capacity Mounting Order No Remarks user area Screw MPE3043AE 4 33 GB No 6 32UNC CA05743 B311 MPE3084AE 8 45GB 6 32UNC CA05743 B321 EP ERE MPE3173AE 17 34 GB No 6 32UNC CA05743 B341 1 3 Power Requirements 1 Input Voltage e 5V 5 e 12V 8 2 Ripple O 200 mV peak to peak 100
109. isk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive C141 E093 01 EN This page is intentionally left blank CONTENTS page CHAPTER1 DEVICE OVERVIEW 1 1 1 1 Fe at res cetus tbe reap a te ei de n ode saad ere obere ce 1 1 1 1 1 Functions and performance 1 1 11 2 cAd ptability eset a MERE 1 2 1 1 3 JIierface uaa te eb De t eat tod eene uti dentem ak 1 2 1 2 D vic SpecifiCatio ns ede dae 1 4 L2 Specifications sumrn ry ue ti eU Re sere eto ERE HS 1 4 1 2 2 ModeLand product number oni ee aee EH ER eed ee ER eg 1 5 1 3 Power Requirements 2 ec pite te eet rte ec pet teste it pee EN od 1 5 1 4 Environmental Specifications eese 1 8 1 5 Acoustic n dinde det demde di dint des deme d tee deter 1 8 1 6 Shock and Vabrationc uh ep SUR eee t eo E 1 9 1 7 Reliability ciet tee tete tem eem e ede 1 9 1 8 Error 1 10 1 9 Defects eR UU eR e IHE 1 10 CHAPTER2 DEVICE CONFIGURATION 2 1 2 1 Device Configuration pen Dare IEEE OU EPA ERREUR 2 1 2 2 System Configuration ib acted REOR ED gd REGE De REG s 2 3 2 2 T ATA interface o iux
110. itself The WRITE LONG command supports only single sector operation This command is operated under the following conditions e The command is issued in a sequence of the READ LONG or WRITE LONG to the same address command issuance WRITE LONG command can be continuously issued after the READ LONG command If above condition is not satisfied the command operation is not guaranteed C141 E093 01 EN At command issuance I O registers setting contents 1 5 Cylinder MSB LBA 1F44 CL Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1F24 SC Number of sectors to be transferred 1F1ly FR XX R 0Oorl At command completion I O registers contents to be read IF DH Head No 1 5 Cylinder MSB LBA 1F44 CL Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error this register indicates 01 20 READ BUFFER X E4 The host system can read the current contents of the sector buffer of the device by issuing this command Upon receipt of this command the device sets the BSY bit of Status register and sets up the sector buffer for a read operation Then the device sets the DRQ bit of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data from the buffer At command iss
111. linder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector or block of data is available for transfer to the host the device sets DRQ bit and clears BSY bit The drive then asserts INTRQ signal e After detecting the INTRQ signal assertion the host reads the Status register The host reads one sector of data via the Data register In response to the Status register being read the device negates the INTRQ signal f The drive clears DRQ bit to 0 If transfer of another sector is requested the device sets the BSY bit and steps d and after are repeated Even if an error is encountered the device prepares for data transfer by setting the DRQ bit Whether or not to transfer the data is determined for each host In other words the host should receive the relevant sector of data 512 bytes of uninsured dummy data or release the DRQ status by resetting Figure 5 2 shows an example of READ SECTOR S command protocol and Figure 5 3 shows an example protocol for command abort C141 E093 01 EN Command Parameter write v Status read Status read b c 1 e e e e a BSY DRDY DRQ eooo Ez INTRQ Data transfer Expanded quat Command Quent
112. ll neither negate STOP nor HSTROBE until at least tacx after negating DMACK 14 The host shall not assert DIOW CSO CS1 DA2 DAI or DAO until at least tack after negating DMACK Ultra DMA CRC rules The following is a list of rules for calculating CRC determining if a CRC error has occurred during an Ultra DMA burst and reporting any error that occurs at the end of a command a b 9 e 5 h Both the host and the device shall have a 16 bit CRC calculation function Both the host and the device shall calculate a CRC value for each Ultra DMA burst The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred For each STROBE transition used for data transfer both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it
113. llentura SWEDEN TEL 46 8 626 4500 FAX 46 8 626 4588 FUJITSU ITALIA S p A Via Nazario Sauro 38 20099 Sesto S Giovanni MI ITALY TEL 39 2 26294 1 FAX 39 2 26294 201 FUJITSU FRANCE S A 1 Place des Etas Unis SILIC 310 94588 Rungis Cedex FRANCE TEL 33 1 41 80 38 80 FAX 33 1 41 80 38 66 FUJITSU ICL ESPANA S A Almagro 40 28010 Madrid SPAIN TEL 34 91 681 8100 FAX 34 91 681 8125 FUJITSU AUSTRALIA LIMITED 2 J ulius Avenue Cnr Delhi Road North Ryde N S W 2113 AUSTRALIA TEL 61 2 9776 4555 FAX 61 2 9776 4556 FUJITSU HONG KONG LTD 10 F Lincoln House 979 King s Road Taikoo Place Island East Hong Kong TEL 852 2827 5780 FAX 852 2827 4724 FUJITSU KOREA LTD Coryo Finance Center Bldg 23 6 Y oulDo Dong Young DungP o Gu Seoul Republic of KOREA TEL 82 2 3787 6000 FAX 82 2 3787 6070 FUJITSU COMPUTERS SINGAPORE PTE LTD 20 Science Park Road 03 01 TELETECH PARK SINGAPORE SCIENCE PARK II Singapore 117674 TEL 65 777 6577 FAX 65 771 5499 FUJITSU TAIWAN LTD 8F Hun Tai Center 168 170 Tun Hwa North Road Ist Sec Taipei TAIWAN TEL 886 2 545 7700 FAX 886 2 717 4644 FUJITSU SYSTEMS BUSINESS MALAYSIA SDN BHD Fujitsu Plaza 1A J alan Tandang 204 Box 636 Pejabat Pos Jalan Sultan 46770 Petaling J aya Selangor Darul Ehsan Malaysia TEL 60 3 793 3888 FAX 60 3 793 0888 FUJITSU SYSTEMS BUSINESS THAILAND LTD 12th F1 Olympia Thai Tower 444 Rachadapis
114. losed loop air circulation system that relies on the blower effect of the rotating disk This system continuously circulates the air through the recirculation filter to maintain the cleanliness of the air in the disk enclosure Read write circuit The read write circuit uses a LSI chip for the read write preamplifier It improves data reliability by preventing errors caused by external noise Controller circuit The controller circuit consists of an LSI chip to improve reliability The high speed microprocessor unit MPU achieves a high performance AT controller C141 E093 01 EN 2 2 System Configuration 2 2 1 ATA interface Figures 2 2 and 2 3 show the ATA interface system configuration The drive has a 40 pin PC AT interface connector and supports the PIO transfer till 16 7 MB s PIO mode 4 the DMA transfer till 16 7 MB s Multiword DMA mode 2 and the ultra DMA transfer till 66 6 MB s Ultra DMA mode 4 2 2 2 1 drive connection HA EE Host P Host adaptor Disk drive AT bus ATA interface Host interface Figure 2 2 1 drive system configuration 2 2 3 2 drives connection HA po Host i i Os Host adaptor Disk drive 0 AT bus Host interface Disk drive 1 ATA interface Note When the drive that is not conformed to ATA is connected to the disk drive is above configuration the operation is not guaranteed Figure 2 3
115. m Configuration 2 1 Device Configuration Figure 2 1 shows the disk drive The disk drive consists of a disk enclosure DE read write preamplifier and controller PCA The disk enclosure contains the disk media heads spindle motors actuators and a circulating air filter Figure 2 1 Disk drive outerview C141 E093 01 EN 2 1 1 2 3 4 5 6 7 Disk The outer diameter of the disk is 95 mm The inner diameter is 25 mm The number of disks used varies with the model as described below The disks are rated at over 40 000 start stop operations MPE3043AE 1 disk MPE3084AE 1 disk MPE3173AE 2 disks Head The heads are of the contact start stop CSS type The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts Spindle motor The disks are rotated by a direct drive Hall less DC motor Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the tip of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays in the specific CSS zone on the disk and is fixed by a mechanical lock Air circulation system The disk enclosure DE is sealed to prevent dust and dirt from entering The disk enclosure features a c
116. mand The number of sectors per block is written into the Sector Count register The IDD supports 2 4 8 and 16 sectors as the block counts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the device clears the BSY bit and generates an interrupt At command issuance I O registers setting contents IT aes 1 5 1FAg CL XX 1F34 SN XX 1F24 SC Sector count block IFI amp FR XX At command completion I O registers contents to be read mes 1 5 1F4 CL XX 1F3y SN XX 1F24 SC Sector count block 1 15 Error information After power on or after hardware reset the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode C141 E093 01 EN 5 37 16 Regarding software reset the mode set
117. mmand The head address is advanced at the subsequent sector from the last sector of the current physical head address The first physical sector of the subsequent physical sector is the consecutive logical sector from the last sector of the current physical sector Figure 6 5 shows an example assuming there is no track skew Physical sector 1 2 3 62 63 64 126 127 189 190 574 575 576 TITRES IT 2 63 1 63 1 63 1 7 LHO LH2 Physical cylinder 0 LS Physical head 0 1 Physical sector 265957 11955120 1825 7183 575 576 Physical cylinder 0 3 Al LSYLS 818 Physical head 1 8 63 1 63 1 63 1 LHIO LHII LHI2 LHI3 ex Zone 0 Physical parameter Physical sector 1 to 574 For the rest 2 spare sectors Specification of INITIALIZE DEVICE PARAMETERS command Logical head LH 0 to 14 Logical sector LS 1 to 63 Figure 6 5 Address translation example in CHS mode C141 E093 01 EN 6 7 2 LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0 physical head 0 and physical sector 1 The logical address is advanced at the subsequent sector from the last sector of the current track The first physical sector of the subsequent physical track is the consecutive logical sector from the last sector of the current physical track Figure 6 6 shows an example of assuming there is no track skew Physical sector
118. n the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored For sensing the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder whole cylinders from most inner to most outer cylinder are divided into 14 partitions at calibration in the factory and the compensation data is measured for representative cylinder of each partition This measured value is stored in the SA area The compensation value at self calibration is calculated using the value in the SA area C141 E093 01 EN Execution timing of self calibration Self calibration is executed when e The power is turned on e self calibration execution timechart of the disk drive specifies self calibration The disk drive performs self calibration according to the timechart based on the time elapsed from power on The timechart is shown in Table 4 1 After power on self calibration is performed about every 30 minutes Tabl
119. nating an Ultra DMA data out nee 5 92 5 6 3 11 Device terminating an Ultra DMA data in burst esee 5 93 56 4 Poweron andteset ius Ete anite e eee Parents 5 94 CHAPTER 6 OPERATIONS neon eR DEED Etre E IQ ae ERE REED Ee eei Eau o 6 1 6 1 Device Response to the 6 1 6 1 R sponseto bii ese title a 6 2 6 1 2 Response to hardware reset 6 3 6 L5 Response t software TeSet ee ovem ele fe tees cene Ee beet eee nae EE 6 4 6 1 4 Response to diagnostic command eene nenne neret 6 5 6 2 Address Translation iis 5 Sogno dte exeun oh ode 6 6 6 2 1 Default parameters tii pete p eee ertet tic 6 6 6 2 2 Logical addres Sr oni en Re en e eh Pu e ed ee er Rd 6 7 6 3 iet i nete eer ge estu e svete tr prete re S ERE Poste etre egens 6 8 6 3 1 Power saye mode i sse ote sb pdt RN t oM Nt ca 6 8 6 3 2 gt Pow rcommiands unii edad bee e Ope o e gH epe ele 6 10 6 4 Detect M nagemelit xo ORE e BHL 6 10 GA Spat sarea ce cette n tet en tet pM Ust ad pto de on s edt d shed 6 11 6 44 2 Alternating defective sectors icc soe abe Ped ra e eed di 6 11 6 5 Read Abhead Cache nem ce e Hd N rede ee ero UE NIE Yee ee 6 13 6 5 1 Data b ffer configuration eire E xe re LP a E RE RE REDE DERE RE TERIS 6 13 6 5 2
120. nd the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance I O registers setting contents 1F7y CM 95 or Drm Ts 1 5 1 4 1F34 SN 1 2 1 1 At command completion I O registers contents to be read mes Ps To Ts ef 1 5 1F4 CL XX 1F3g SN XX 1F24 SC XX 1 15 Error information 5 44 C141 E093 01 EN 24 25 STANDBY X 96 or X E2 Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the standby mode If the device has already spun down the spin down sequence is not implemented If the contents of the Sector Count register is other than 0 the automatic power down function is enabled and the timer starts countdown when the device returns to idle mode When the timer value reaches 0 passed a specified time the device enters the standby mode If the contents of the Sector Count register is 0 the automatic power down function is disabled Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as the READ SECTOR s command is received
121. nder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the target track Operation to move the head to the reference cylinder The MPU moves the head to the reference cylinder when the power is turned The reference cylinder is in the data area When power is applied the heads are moved from the inner circumference shunt zone to the normal servo data zone in the following sequence a Micro current is fed to the VCM to press the head against the inner circumference b current is fed to the to move the head toward the outer circumference c When the servo mark is detected the head is moved slowly toward the outer circumference at a constant speed d Ifthe head is stopped at the reference cylinder from there Track following control starts C141 E093 01 EN 2 3 1 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read or instruction is issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the difference speed error between the specified target position and the current position for each sampling timing during head moving The MPU then feeds the VCM drive current by setting the calculated result into the D A converter The calculation is digitally executed by
122. ng of master or slave device eese 3 13 Jumper setting Of Cable 3 14 Example 1 of Cable Select enne nennen nere nnne 3 14 Example 2 of Cable Select ete ro 3 14 H ad str cture ied HERE HERE Ges ea ee aloes 4 2 Block diagram sof iens a a eed ee IT 4 5 Power on operation sequence ceeeccceessecceeesnececeseseeeeeeneeeeceeeeeeeseaeeeeceaeeeeseneeeeeeeateeess 4 7 Block diagram of servo control circuit esses nnne enne 4 13 Physical sector servo configuration on disk surface sssssssssssee 4 14 O6 servo frames in each iium Favs cbse Se ea e e Hec edere Hes e ord 4 17 Execution example of READ MULTIPLE command 5 19 Read Sector s command protocol cccsccccesesccceeseeeeceeeseeeceseneeeceseececeenneeeeeenneeeeseneeeess 5 63 Protocol for command 5 64 C141 E093 01 EN xi 5 4 3 9 5 6 5 7 5 8 5 9 5 10 5 11 5 12 5 13 5 14 5 15 5 16 5 17 5 18 5 19 5 20 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 xii WRITE SECTOR S command 5 65 Protocol for the command execution without data transfer eese 5 66 Normal DM X dat transfer ze etn nene e tie eat eed tiet i ate ag 5 68 Ultra DMA termination with pull up or pull down
123. ngs 3 4 Location of setting jumpers Figure 3 13 shows the location of the jumpers to select drive configuration and functions reed eos a ae a pubes ON INSVA 90255 MI DC Power Connector Figure 3 13 Jumper location 3 12 C141 E093 01 EN 3 4 2 Factory default setting Figure 3 14 shows the default setting position at the factory Master device setting DC Power Connector Interface Connector Figure 3 14 Factory default setting 3 4 5 Jumper configuration 1 Device type Master device device 0 or slave device device 1 is selected 2 4 6 8 2 4 6 8 OOO OfJoo ner rire 13579 13579 a Master device b Slave device Figure 3 15 Jumper setting of master or slave device Note When the device type is set by the jumper on the device the device should not be configured for cable selection 2 Cable Select CSEL In Cable Select mode the device can be configured either master device or slave device For use of Cable Select function Unique interface cable is needed C141 E093 01 EN 3 13 3 14 2 4 6 8 OLIO O OBJO O 13579 CSEL connected to the interface cable selection can be done by the special interface cable Figure 3 16 Jumper setting of Cable Select Figures 3 17 and 3 18 show examples of cable selection using unique interface cables By connecting the CSEL of the master device to the CSEL Line conduc
124. no changes to other elements of the ATA protocol e g Command Block Register access Several signal lines are redefined to provide new functions during an Ultra DMA burst These lines assume these definitions when 1 an Ultra DMA Mode is selected and 2 a host issues a READ DMA or a WRITE DMA command requiring data transfer and 3 the host asserts DMACK These signal lines revert back to the definitions used for non Ultra DMA transfers upon the negation of DMACK by the host at the termination of an Ultra DMA burst All of the control signals are unidirectional DMARQ and DMACK retain their standard definitions With the Ultra DMA protocol the control signal STROBE that latches data from DD 15 0 is generated by the same agent either host or device that drives the data onto the bus Ownership of DD 15 0 and this data strobe signal are given either to the device during an Ultra DMA data in burst or to the host for an Ultra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data The highest fundamental frequency on the cable shall be 16 67 million transitions per second or 8 33 MHz the same as the maximum frequency for PIO Mode
125. nue to negate HDMARDY until the Ultra DMA burst is terminated The device shall stop generating DSTROBE edges within of the host negating HDMARDY If the host negates HDMARDY within tsp after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARDY greater than tsp after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and timing for the device The host shall assert STOP no sooner than tgp after negating HDMARDY The host shall not negate STOP again until after the Ultra DMA burst is terminated The device shall negate DMARQ within tj after the host has asserted STOP The device shall not assert DMARQ again until after the Ultra DMA burst is terminated If DSTROBE is negated the device shall assert DSTROBE within tj after the host has asserted STOP No data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra DMA burst is terminated The device shall release DD 15 0 no later than taz after negating DMARQ The host shall drive DD 15 0 no sooner than tzay after the device has negated DMARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 C141 E093
126. o ALBA MS 1 5 End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1FIg ER Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 1x x X 0 to This command performs the calibration Upon receipt of this command the device sets BSY bit of the Status register and performs a calibration When the device completes the calibration the device updates the Status register clears the BSY bit and generates an interrupt This command can be issued in the LBA mode At command issuance I O registers setting contents IT PTs ete 1 5 1 4 1F34 SN 1 2 IFI amp FR At command completion I O registers contents to be read mes o 1 5 1 4 1F3y SN XX 1F24 SC XX 1 15 Error information 5 26 C141 E093 01 EN 10 SEEK X 7x X 0 to This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt The IDD always sets the DSC bit Drive Seek Complete status of the Status register to 1 In the LBA mode this command performs the seek operation to the cylinder and head position
127. o OD C141 E093 01 EN Table 5 10 Format of insurance failure threshold value data Threshold 1 Attribute ID The format of each threshold value is the same as threshold 30 that of bytes 02 to OD 17C to IFE Vendor unique Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds The data format version numbers of the device attribute values and insurance failure thresholds are the same When a data format is changed the data format version numbers are updated Attribute ID The attribute ID is defined as follows _ ___ O 2 mewwerefomase 5 4 ES Ed aus n _ Seek time performance Power on time 09 omata 1 2 3 4 5 7 10 12 199 200 Number of retries made to activate the spindle motor C141 E093 01 EN 5 53 Status flag If this bit 1 it indicates that if the attribute exceeds the threshold it is the attribute covered by the drive warranty 1 If this bit is 1 0 it indicates the attribute only updated by an on line test off line test If this bit 1 it indicates the attribute that represents performance If this bit 1 it indicates the attribute that represents the number of occurrences If this bit 1 it indicates the attribute that can be collected saved ev
128. occurred C141 E093 01 EN 5 69 5 5 3 1 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts Each Ultra DMA burst has three mandatory phases of operation the initiation phase the data transfer phase and the Ultra DMA burst termination phase In addition an Ultra DMA burst may be paused during the data transfer phase see 5 5 3 and 5 5 4 for the detailed protocol descriptions for each of these phases 5 6 defines the specific timing requirements In the following rules DMARDY is used in cases that could apply to either DDMARDY or HDMARDY and STROBE is used in cases that could apply to either DSTROBE HSTROBE The following are general Ultra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst Ultra DMA data in commands Initiating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 1 and 5 6 3 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DST
129. or Count Sector Number Cylinder and Device Head register The host initializes the DMA channel The host writes a command code in the Command register The device sets the BSY bit of the Status register The device asserts the DMARQ signal after completing the preparation of data transfer The device asserts either the BSY bit during DMA data transfer When the command execution is completed the device clears both BSY and DRQ bits and asserts the INTRQ signal The host reads the Status register The host resets the DMA channel C141 E093 01 EN 5 67 Parameter write W Command Status read VA c d i BSY DRDY g INTRQ er ree DRQ Data transfer i Expanded Multiword DMA transfer DRQ DMARQ DMACK 4 IOR or IOW Word 0 1 n 1 5 68 Figure 5 6 Normal DMA data transfer C141 E093 01EN 5 5 Ultra DMA feature set Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host This protocol applies to the Ultra DMA data burst only When this protocol is used there are
130. or less 3 10 C141 E093 01 EN Host detected CBLID above Vm PDIAG CBLID conductor Host Device 1 V A V Device 0 Host detected CBLID below Vi open PDIAG CBLID conductor A V Host Device 1 Device 0 with 40 conductor cable with 80 conductor cable Figure 3 11 Cable type detection using CBLID signal Host sensing the condition of the CBLID signal IDENTIFY DEVICE information word 93 bit13 0 Device detected CBLID below PDIAG CBLID conductor Host lt 0 047 uF 10 or 20 V Device 1 4 V Device 0 IDENTIFY DEVICE information word 93 bit13 1 Device detected CBLID above open PDIAG CBLID conductor lt S Host 0 047 uF 0 10 20 A V Device 1 Device 0 with 40 conductor cable with 80 conductor cable Figure 3 12 Cable type detection using IDENTIFY DEVICE data Device sensing the condition of the CBLID signal C141 E093 01EN 3 11 3 4 Jumper Setti
131. or the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 2 If the head is not on the track specified by the host the device performs a implied seek After the head reaches to the specified track the device writes the target sector The data stored in the buffer and CRC code and ECC bytes are written to the data field of the corresponding sector s Upon the completion of the command execution the command block registers contain the cylinder head and sector addresses of the last sector written If an error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Command block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred At command issuance I O registers setting contents 1F74 CM 0 0 1 1 0 0 0 R 1F6y DH Start head No LBA MSB 1 5 Start cylinder No MSB LBA 1F44 CL Start cylinder No LSB LBA 1 3 Start sector No LBA LSB 1F24 SC Transfer sector count IFI amp FR XX R Oorl C141 E093 01 EN 6 At command completion I O registers contents to be read IF DH End cal No ALBA MS 1 5 End cylinder No MSB LBA 1F44 CL End cylinder No LSB L
132. ord 0 Serial number ASCII codo 4 o y X 0400 rirmware revision ASCII o yO number ASCII code 6 o Xo 7 9 10 19 0 1 2 2 23 26 27 46 X 0000 X 0B00 Capabilities 7 N N 4 4 4 Reserved 54 55 56 59 7 8 9 50 52 57 58 60 61 Total number of user addressable sectors LBA mode only 62 63 65 4 60 61 92 6s 66 68 80 001 X 4008 84 85 87 88 94 127 X 00 Security Status 128 Security Status 129 255 80 81 82 90 91 92 93 oo 5 30 C141 E093 01 EN Table 5 5 Information to be read by IDENTIFY DEVICE command 2 of 4 1 Word 0 General configuration Bit 15 0 ATA device 0 Bit 14 8 Vendor specific Bit 7 1 Removable media device Bit 6 1 not removable controller and or device 1 Bit 5 1 Vendor specific Bit 0 Reserved 0 2 Number of Cylinders 3 Number of Heads 11 Total number of user addressable sectors LBA mode only MPE3043AE MPE3084AE MPE3173AE X 22FF X 3FFF 812 4 X FBFCIO X 204C5B4 4 Word 10 19 Serial number ASCII code 20 characters right justified 5 Word 23 26 Firmware revision ASCII code 8 characters Left justified 6 Word 27 46 Model number ASCII code 40 characters Left justified remainder filled with blank code X 20 One of the following mod
133. peration is not guaranteed Command Status read Parameter write VV Transfers dummy data The host should receive 512 byte dummy data or release the DRQ set state by resetting Figure 5 3 Protocol for command abort Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive FORMAT TRACK WRITE SECTOR S WRITE LONG WRITE BUFFER WRITE VERIFY The execution of these commands includes the transfer one or more sectors of data from the host to the device In the WRITE LONG command 516 bytes are transferred Following shows the protocol outline a b The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers The host writes a command code in the Command register The drive sets the BSY bit of the Status register C141 E093 01 EN d g h D When the device is ready to receive the data of the first sector the device sets DRQ bit and clears BSY bit The host writes one sector of data through the Data register The device clears the DRQ bit and sets the BSY bit When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the DRQ bit After detecting the INTRQ signal assertion
134. prior to software reset is retained after software reset The parameters for the multiple commands which are posted to the host system when the IDENTIFY DEVICE command is issued are listed below See Subsection 5 3 2 for the IDENTIFY DEVICE command Word 47 8010 Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands are 16 fixed Word 5920000 The READ MULTIPLE and WRITE MULTIPLE commands are disabled 01 The READ MULTIPLE and WRITE MULTIPLE commands are enabled xx indicates the current setting for number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands e g 0110 Block count of 16 has been set by the SET MULTIPLE MODE command EXECUTE DEVICE DIAGNOSTIC X 90 This command performs an internal diagnostic test self diagnosis of the device This command usually sets the DRV bit of the Drive Head register is to 0 however the DV bit is not checked If two devices are present both devices execute self diagnosis If device is present e Both devices shall execute self diagnosis e The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG signal e Ifthe device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status e The device 0 clears the BSY bit of the Status register and generates an interrupt The device 1 does not gene
135. r cable assembly is manufactured by AMP or 3M Table 3 2 Cable connector specifications Maman Cable socket FCN 707B040 AU B ATA interface cable closed end type 40 pin CN1 Cable socket FCN 707B040 AU O Fujitsu through end type Power supply cable Cable socket housing 1 480424 0 60617 4 LC Note The cable of twisted pairs and neighboring line separated individually is not allowed to use for the host interface cable It is because that the location of signal lines in these cables is not fixed and so the problem on the crosstalk among signal lines may occur It is recommended to use the ribbon cable for ATA interface that cable length is less than 18 inch 46 cm and cable capacitance is less than 35 pico farad Also it is recommended to use AWGIS power supply cable 3 3 3 Device connection Figure 3 8 shows how to connect the devices ATA interface cable Power supply cable Disk Drive 0 DC Host system power supply Disk Drive 1 Figure 3 8 Cable connections 3 8 C141 E093 01 EN 3 3 4 Power supply connector Figure 3 9 shows the pin assignment of the power supply connector CN1 1 12VDC 2 12V RETURN CO CO CO CO J s Tre 4 5VDC Viewed from cable side Figure 3 9 Power supply connector pins CN1 3 3 5 System configuration for Ultra D
136. rate an interrupt e diagnostic status of the device 0 is read by the host system When a diagnostic failure of the device 1 is detected the host system can read a status of the device 1 by setting the DV bit selecting the device 1 When device 1 is not present e device 0 posts only the results of its own self diagnosis e The device 0 clears the BSY bit of the Status register and generates an interrupt Table 5 7 lists the diagnostic code written in the Error register which is 8 bit code If the device 1 fails the self diagnosis the device 0 ORs X 80 with its own status and sets that code to the Error register C141 E093 01 EN 17 18 Table 5 7 Diagnostic code Result of diagnostic No error detected Data buffer compare error ROM sum check error Failure of device 1 At command issuance I O registers setting contents 1F74 CM Ub e wem xD Iw 1F54 CH XX 1F44 CL XX 1F3y SN XX IF24 SC XX IF1y FR XX At command completion I O registers contents to be read 1 5 1F4 CL d 1F3y SN Oly 1F24 SC Oly 1 1 Diagnostic code FORMAT TRACK 50 Upon receipt of this command the device sets the DRQ bit and waits the completion of 512 byte format parameter transfer from the host system After completion of transfer the device clears the DRQ bits sets the BSY bit However the device does not perform format operation but the drive clears the BYS
137. re not specified with an INITIALIZE DEVICE PARAMETERS command the default values listed in Table 6 1 are used This is called as the default translation mode The parameters in Table 6 1 are called BIOS specification Table 6 1 Default parameters mesons areosa MPESITSAE Number of cylinders 8 959 16 383 Number of sectors track As long as the formatted capacity of the IDD does not exceed the value shown on Table 6 1 the host can freely specify the number of cylinders heads and sectors per track Generally the device recognizes the number of heads and sectors per track with the INITIALIZE DEVICE PARAMETER command However it cannot recognizes the number of cylinders In other words there is no way for the device to recognize a host access area on logical cylinders Thus the host should manage cylinder access to the device The host can specify a logical address freely within an area where an address can be specified within the specified number of cylinders heads and sectors per track in the current translation mode The host can read an addressable parameter information from the device by the IDENTIFY DEVICE command Words 54 to 56 C141 E093 01 EN 6 2 2 Logical address 1 CHS mode Logical address assignment starts from physical cylinder PC 0 physical head PH 0 and physical sector PS 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS co
138. rite data is remained If the drive stacks a write command for that the drive posts the command completion next to the command that write operation is stopped by error occurrence After an error occurs at above write operation the drive posts the error status to the host system at next command The drive does not execute this command sets the error status that occurred at the write operation and generates the interrupt for abnormal end However when the drive receives a write command after the completion of error processing the drive posts the error after writing the write data of the write command C141 E093 01 EN At the time that the drive has stopped the command execution after the error recovery has failed the write cache function is disabled automatically The releasing the disable state can be done by the SET FEATURES command When the power of the drive is turned on after the power is turned off once the status of the write cache function returns to the default state The default state is write cache enable and can be disable by the SET FEATURES command The write cache function is operated with the following command WRITE SECTOR S WRITE MULTIPLE WRITE DMA IMPORTANT When the write cache function is enabled the transferred data from the host by the WRITE SECTOR S is not completely written on the disk medium at the time that the interrupt of command complete is generated When the unrecoverable error occurs during th
139. s ow 1F5y CH 1F4 CL XX 1F34 SN XX 1F24 SC XX 1 15 Error information The host sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value However the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is posted PIO default transfer mode 00000 000 X 00 PIO flow control transfer mode X 00001 000 X 08 Mode 0 00001 001 X 09 Mode 1 00001 010 X 0A Mode 2 00001 011 X 0B Mode 3 00001 100 X 0C Mode 4 Multiword DMA transfer mode X 00100 000 X 20 Mode 0 00100 001 X 21 Mode 1 00100 010 X 22 Mode 2 Ultra DMA transfer mode X 01000 000 40 Mode 0 01000 001 41 Mode 1 01000 010 X 42 Mode 2 01000 011 X 43 Mode 3 01000 100 X 44 Mode 4 C141 E093 01 EN 15 SET MULTIPLE MODE X C6 This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands The block count number of sectors in a block for these commands are also specified by the SET MULTIPLE MODE com
140. s a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own power on reset state the slave device shall report its presence and the result of power on diagnostics to the master device as described below DASP signal Asserted within 400 ms and negated after the first command is received from the host or within 31 seconds or after executing software reset which ever comes first PDIAG signal Negated within 1 ms and asserted within 30 seconds then negated within 31 seconds V Power on Master device Power On Reset Status Reg BSY bit Max 31 sec Checks DASP for up to If presence of a slave device is 450 ms confirmed PDIAG is checked for up to 31 seconds Slave device Power On Reset BSY bit 1 ms PDIAG m 30 gt DASP Max 400 ms Max 31 sec E Figure 6 1 Response to power on 6 2 C141 E093 01 EN 6 1 2 Response to hardware reset Response to RESET hardware reset through the interface is similar to the power on reset Upon receipt of hardware reset the master device checks a DASP signal for up to 450 ms to confirm pre
141. s by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant The drive divides data area into 15 zones to set the data transfer rate Table 4 2 describes the data transfer rate and recording density BPI of each zone Table 4 2 Write clock frequency and transfer rate of each zone ae EI Cylinder 0 965 2151 3581 4791 6121 8031 9441 to to to to to to to to 964 2150 3580 4790 6120 8030 9440 11210 Transferrate 3444 34 44 34 44 3444 33 41 31 83 30 59 28 71 MB s m ICD Cylinder 11211 12171 12591 13431 14431 15861 16661 MB s 4 7 to to to to to to to 12170 12590 13430 14430 15860 16660 17300 Transferrate 576g 27 14 26 10 24 80 22 96 21 93 20 36 The MPU transfers the data transfer rate setup data to the RDC that includes synthesizer circuit to change the data transfer rate Servo Control The actuator motor and the spindle motor are submitted to servo control The actuator motor is controlled for moving and positioning the head to the track containing the desired data To turn the disk at a constant velocity the actuator motor is controlled according to the servo data that is written on the data side beforehand C141 E093 01 EN 4 7 1 Servo control circuit Figure 4 4 is the block diagram of the servo control circuit The following describes the f
142. sence of a slave device The master device recognizes the presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the self diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device receives the hardware reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below DASP signal Asserted within 400 ms and negated after the first command is received from the host or within 31 seconds or after executing software reset which ever comes first PDIAG signal Negated within 1 ms and asserted within 30 seconds then negated within 31 seconds Reset _ Master device Status Reg __ BSY bit 31 gt f presence of a slave device is Checks DASP for up to confirmed PDIAG is checked for 450 He up to 31 seconds Slave device BSY bit 4 gt Max 1 ms PDIAG Max 30 sec DASP gt 400 ms Max 31 sec 4 gt Figure 6 2 Response to hardware reset C141 E093 01 EN 6 3 6 1 3 Response to software reset The master device does not check the DASP signal for a software reset I
143. sing by a MPU and then reconverted to an analog signal for control of the voice coil motor Spindle motor driver circuit The circuit measures the interval of a PHASE signal generated by counter electromotive voltage of a motor or servo mark at the MPU and controls the motor speed comparing target speed Controller circuit Major functions are listed below Data buffer management ATA interface control and data transfer control Sector format control Defect management ECC control Error recovery and self diagnosis C141 E093 01 EN ATA Interface Printed Circuit Board Assemb y ess bee SS ee H Data Buffer i DRAM HDC Hard Disk Controller lt MB90255A gt HDC amp MPU Flash ROM FROM MCU Micro Contol ler Unit Resonator 20MHz Read Channel RDC Servo VCM amp SPINDLE Controller CIRRUS SH3512 Pumor i E Svc HA13626FH Temp Read Wr ite Pre amplifier Voice Coil Motor DISK Sensor HEAD Read amp Write TLS26A454 458 Head Assembly Spindle Motor FPC PB14E 5400 rpm Figure 4 MPE3xxxAE Block diagram C141 E093 01 EN 4 4 Power on Sequence Figure 4 3 describes the operation sequence of the disk drive at power on The outline is described below a b d After the power is turned on the disk drive executes MPU bus test internal register rea
144. sionally performs self calibration in order to sense and calibrate mechanical external forces on the actuator and VCM torque This enables precise seek and read write operations Self calibration contents Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution The torque vary with the disk drive and the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current that balances the torque for stopping head stably This includes the current offset in the power amplifier circuit and DAC system The forces are compensated by adding the measured value to the specified current value to the power amplifier This makes the stable servo control To compensate torque varying by the cylinder the disk is divided into 14 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operatio
145. start mode Then a current approx 2 1 A flows into the spindle motor c The SVC generates a phase switching signal by itself and changes the phase of the current flowed in the motor in the order of V phase to U phase W phase to U phase W phase to V phase U phase to V phase U phase to W phase and V phase to W phase after that repeating this order d During phase switching the spindle motor starts rotating in low speed and generates a counter electromotive force The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection C141 E093 01 EN 4 19 2 3 e The MPU is waiting for a PHASE signal When no phase signal is sent for a specific period the MPU resets the SVC and starts from the beginning When a PHASE signal is sent the SVC enters the acceleration mode Acceleration mode In this mode the MPU stops to send the phase switching signal to the SVC The SVC starts a phase switching by itself based on the counter electromotive force Then rotation of the spindle motor accelerates The MPU calculates a rotational speed of the spindle motor based on the PHASE signal from the SVC and accelerates till the rotational speed reaches 5 400 rpm When the rotational speed reaches 5 400 rpm the SVC enters the stable rotation mode Stable rotation mode The MPU calculates a time for one revolution of the spindle motor based on the PHASE signal from the SVC The
146. surface as the spindle motor approaches the rated rotation speed MPE3043AE MPE3084AE Spindle Actuator Spindle Actuator i i i i i i i J 5 0 LI 5 T 0 I MPE3173AE Spindle Actuator i i c 3 2 c 1 j T 0 1 Figure 4 4 Head structure 4 2 3 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 5 400 rpm The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting After that the rotational speed is kept with detecting a servo information Actuator The actuator consists of a voice coil motor VCM and a head carriage The VCM moves the head carriage along the inner or outer edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head C141 E093 01 EN Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE
147. t 13 Bit 12 0 Reserved Device detected CBLID above 80 conductor cable 1 Device detected CBLID below 40 conductor cable 0 Reserved C141 E093 01 EN 5 33 13 14 IDENTIFY DEVICE DMA X EE When this command is not used to transfer data to the host in DMA mode this command functions in the same way as the Identify Device command At command issuance I O registers setting contents 1F74 CM Hd Wc Eo TT eT 1 5 1 4 1F34 SN 1F24 SC 1F14 FR At command completion I O registers contents to be read mes 1F5y CH 1F4 CL XX 1F3y SN XX 1F24 SC XX 1 15 Error information SET FEATURES X EF The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed For the transfer mode Feature register 03 detail setting can be done using the Sector Count register Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Features register Then the device clears the BSY bit and generates an interrupt If the value in the Features register is not supported or it is invalid the device posts an ABORTED COMMAND error Table 5 6 lists the available values and operational modes that may be set in the Features register C141 E093 01 EN Table 5 6 Features register values and settable modes Features
148. t has been completed normally or has not been executed Self test has been stopped by the host computer Self test has been suspended by hard or soft reset 6 sates been competed abnonaly by sebo text e Off line data collection capability Indicates the method of off line data collection carried out by the drive If the off line data collection capability is 0 it indicates that off line data collection is not supported Indicates that Execute Off Line Immediate is supported 2 Indicates that off line data collection being executed is aborted when a new command is received Indicates that supports off line read scan function Indicates that supports self test function e Failure prediction capability flag Bit 0 The attribute value data is saved to a media before the device enters power saving mode Bit 1 The device automatically saves the attribute value data to a media after the previously set operation Bits 2 to 15 Reserved bits C141 E093 01 EN 5 55 e Error logging capability Bit 0 Indicates that error logging function Bits 1 to 7 Reserved bits e Check sum Two s complement of the lower byte obtained by adding 511 byte data one byte at a time from the beginning e Insurance failure threshold The limit of a varying attribute value The host compares the attribute values with the thresholds to identify a failure If an unrecoverable error is detected during execution of a command received by
149. t the host system refers the addressable user sectors total number of sectors in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command At command issuance I O registers setting contents IT i 1 5 1 4 1F34 SN XX 1F24 SC Number of sectors track IFI amp FR XX At command completion I O registers contents to be read T 1F5y CH 1F4 CL XX 1F34 SN XX 1F24 SC XX 1 15 Error Information IDENTIFY DEVICE X EC The host system issues the IDENTIFY DEVICE command to read parameter information 512 bytes from the device Upon receipt of this command the drive sets the BSY bit of Status register and sets required parameter information in the sector buffer The device then sets the DRQ bit of the Status register and generates an interrupt After that the host system reads the information out of the sector buffer Table 5 5 shows the arrangements and values of the parameter words and the meaning in the buffer C141 E093 01 EN At command issuance I O registers setting contents 1F74 CM E EA Dre TTT 1 5 1 4 1F34 SN 1 2 IFI amp FR At command completion I O registers contents to be read mes Ps To Ts ow 1F5y CH 1F4 CL XX 1F34 SN XX 1F24 SC XX 1 15 Error information C141 E093 01 EN Table 5 5 Information to be read by IDENTIFY DEVICE command 1 of 4 W
150. tead of sector 5 When an access request to sectors next to sector 5 is specified the device seeks to cylinder 0 head 0 and continues the processing Figure 6 8 Alternate cylinder assignment Automatic alternate assignment The device performs the automatic assignment at following case 1 Automatic alternate assignment is done when a read error is recovered by retry beyond the regulation number of times during read error retry Before automatic alternate assignment the device performs rewriting the corrected data to the erred sector and rereading If no error occurs at rereading the automatic alternate assignment is not performed And this automatic alternate assignment is done only once toward the read command receipt from the host 2 When a write error occurs and the error does not recovered C141 E093 01 EN 6 5 6 5 1 Read Ahead Cache After a read command which reads the data from the disk medium is completed the read ahead cache function reads the subsequent data blocks automatically and stores the data in the data buffer When the next command requests to read the read ahead data the data can be transferred from the data buffer without accessing the disk medium The host can access the data at higher speed Data buffer configuration The device has a 512 KB data buffer The buffer is used by divided into two and other commands parts for MPU work for read cache of read commands and other commands see
151. the device processes the command after driving the spindle motor At command issuance I O registers setting contents 1F74 CM X 96 or X E2 mem To Poe 1 5 1 4 1F34 SN XX 1F24 SC Period of timer IFI amp FR XX At command completion I O registers contents to be read mes e 0 7 1 5 1F4 CL XX 1F3y SN XX 1F24 SC XX 1 15 Error information STANDBY IMMEDIATE X 94 or X EO Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt This command does not support the automatic power down sequence C141 E093 01 EN 5 45 26 At command issuance I O registers setting contents 1F74 CM 94 or X EO TT IRI 9 1 5 1 4 1F34 SN 1 2 1 1 At command completion I O registers contents to be read mes Ts To Ts x 0 7 1F5y CH 1F4 CL XX 1F34 SN XX 1F24 SC XX 1 15 Error information SLEEP X 99 or X E6 This command is the only way to make the device enter the sleep mode Upon receipt of this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and t
152. the device receives this subcommand it asserts the BSY bit disables the failure prediction feature then clears the BSY bit SMART Return Status When the device receives this subcommand it asserts the BSY bit and saves the current device attribute values Then the device compares the device attribute values with insurance failure threshold values If there is an attribute value exceeding the threshold F4h and 2Ch are loaded into the CL and CH registers If there are no attribute values exceeding the thresholds 4Fh and C2h are loaded into the CL and CH registers After the settings for the CL and CH registers have been determined the device clears the BSY bit X DB SMART Enable Disable Auto Off line This sets automatic off line data collection in the enabled when the SC register specification 00h or disabled when the SC register specification 00 state This setting is preserved whether the drive s power is switched on or off If four hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART Read Attribute Values subcommand FR register SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register DAh to save the device attribute value data on a medium Alternative the device m
153. the firmware When the head arrives at the target cylinder the track is followed Track following operation Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed the MPU does track following control To position the head at the center of a track the DSP drives the VCM by feeding micro current For each sampling time the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware Spindle motor control Hall less three phase eight pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC hereafter The firmware operates on the MPU manufactured by Fujitsu The spindle motor is controlled by sending several signals from the MPU to the SVC There are three modes for the spindle control start mode acceleration mode and stable rotation mode Start mode When power is supplied the spindle motor is started in the following sequence a After the power is turned on the MPU sends a signal to the SVC to charge the change pump capacitor of the SVC The charged amount defines the current that flows in the spindle motor b When the charge pump capacitor is charged enough the MPU sets the SVC to the motor
154. the host reads the Status register The device resets INTRQ the interrupt signal If transfer of another sector is requested steps d and after are repeated Figure 5 4 shows an example of WRITE SECTOR S command protocol and Figure 5 3 shows an example protocol for command abort Parameter write W Command Status read Status read VV b V eeee 7 V E ES E _ DRDY 3 c e INTRQ owe a TTT a mm Expanded ue Command EMEN LLL DRQ Max 1 us Data Reg Selection Data 3 X X 3 X 3 X 3 IOR i mecs ed aie Word 0 1 2 255 IOCS16 Figure 5 4 WRITE SECTOR S command protocol C141 E093 01 EN 5 65 Note For transfer of a sector of data the host needs to read Status register 1 7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to 5 us after the completion of the sector data transfer Note that the host does not need to read the Status register for the first and the last sector to be transferred If the timing to read the Status register does not meet above condition normal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or wh
155. tial hit When the last sector address of the previous read command is sequential to the lead sector address of the received read command the disk drive transfers the hit data in the buffer to the host system The disk drive performs the read ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system 1 In the case that the contents of buffer is as follows at receiving a read command HAP Completion of transferring requested data Read ahead data 28 Ai DAP lt gt Last Start LBA 2 disk drive starts the read ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring hit data HAP Read ahead data New read ahead data DAP 3 After completion of data transfer of hit data the disk drive performs the read ahead operation for the data area of which the disk drive transferred hit data HAP Read ahead data DAP C141 E093 01 EN 6 17 3 4 Full hit hit all All requested data are stored in the data buffer The disk drive starts transferring the requested data from the address of which the requested data is stored After completion of command a previously existed cache data before the full hit reading are still kept in the buffer and th
156. tor of the cable and connecting it to ground further the CSEL is set to low level The device is identified as a master device At this time the CSEL of the slave device does not have a conductor Thus since the slave device is not connected to the CSEL conductor the CSEL is set to high level The device is identified as a slave device os cet mesi a Mam a r o Ene mud us Is ues GND Figure 3 17 Example 1 of Cable Select FECE OE c PEE GND Figure 3 18 Example 2 of Cable Select C141 E093 01 EN 3 Special jumper settings a 2 1 GB clip Limit capacity to 2 1 GB If the drive cannot be recognized by system with legacy BIOS s which do not allow single volume sizes greater than approximately 2 1 GB the following jumper settings should be applied 2 468 2 4 6 8 OO Sere 13579 13579 Master Device Slave Device Cable Select MPE3043AE 4 092 b Slave present If the slave device does not use the Device Active Slave Present DASP signal to indicate its presence the device is configured as a Master with slave present when the following jumper settings is applied 2 4 6 8 OO OO O 13579 Slave present C141 E093 01EN 3 15 This page is intentionally left blank CHAPTER 4 THEORY OF DEVICE OPERATION 4 1 Outline 4 2 Subassemblies 4 3 Circuit Configuration 4 4 Power on sequence 4 5 Self cali
157. ts the BSY bit then reads the log sector specified in the SN register Next it clears the BSY bit and transmits the log sector to the host computer 01 should be specified in the SC register SN Log sector Olh SMART error log 06h SMART self test log 80h 9Fh Host vendor log See Table 5 11 concerning the SMART error log data format See Table 5 12 concerning the SMART self test log data format C141 E093 01 EN 5 49 Table 5 8 Features Register values subcommands and functions 2 2 Features Resister Function X D6 SMART Write Log Sector A device which receives this sub command asserts the BSY bit and when it has prepared to receive data from the host computer it sets DRQ and clears the BSY bit Next it receives 512 bytes of data from the host computer and writes the specified log sector in the SN register Olh should be specified in the SC register SN Log sector 80h 9Fh Host vendor log host can write any desired data in the host vendor log X DE SMART Enable Operations This subcommand enables the failure prediction feature The setting is maintained even when the device is turned off and then on When the device receives this subcommand it asserts the BSY bit enables the failure prediction feature then clears the BSY bit X D9 SMART Disable Operations This subcommand disables the failure prediction feature The setting is maintained even when the device is turned off and then on When
158. uance I O registers setting contents 1F74 CM ONE KON Dre TT eT 1 5 1 4 1F34 SN 1 2 1F14 FR C141 E093 01EN 5 41 21 At command completion I O registers contents to be read mes 1F5y CH 1F4 CL XX 1F34 SN XX 1F24 SC XX 1 15 Error information WRITE BUFFER X E8 The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command Upon receipt of this command the device sets the BSY bit of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the sector buffer then generates an interrupt At command issuance I O registers setting contents 1F74 CM A TTT 1 5 1 4 1F34 SN 1 2 IFI amp FR At command completion I O registers contents to be read mes 1 5 1 4 1F34 SN XX 1F24 SC XX 1FIg ER Error information C141 E093 01 EN 22 IDLE X 97 or X E3 Upon receipt of this command the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the idle mode If th
159. uit or head disconnection Write circuit The write data is output from the hard disk controller HDC with the NRZ data format and sent to the encoder circuit in the RDC with synchronizing with the write clock The NRZ write data is converted from 48 bits data to 51 bits data by the encoder circuit then sent to the PreAMP and the data is written onto the media 48 51 GCR The disk drive converts data using the 48 51 group coded recording GCR algorithm Write precompensation Write precompensation compensates during a write process for write non linearity generated at reading C141 E093 01 EN 1 2 3 4 5 6 Read circuit The head read signal from the PreAMP is regulated by the variable gain amplifier VGA circuit Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit This clock signal is converted into the NRZ data by the 48 51 GCR decoder circuit based on the read data maximum likelihood detected by the Viterbi detection circuit then is sent to the HDC VGA circuit The VGA circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates The VGA output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions Programmable filter The programmable filter circuit has a low pass filter function that
160. unctions of the blocks 1 MPU SVC 2 3 4 5 a e VCM current gt gt DSP o gt gt P Head burst ADC Whit DAC gt Y CSR Position Sense 7 Y VCM 6 7 Spindle ES M dine gt Driver gt n CSR Current Sense Resistor control Ae VCM Voice Coil Motor Figure 4 4 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU includes DSP unit etc and the MPU starts the spindle motor moves the heads to the reference cylinders seeks the specified cylinder and executes calibration according to the internal operations of the MPU The major internal operations are listed below a Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied b Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 C141 E093 01 EN 4 13 c Seek to specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration value Servo frame 96 servo frames per revolution dn
161. ust issue the SMART Enable Disable Attribute AutoSave subcommand FR register D2h to use a feature which regularly save the device attribute value data to a medium The host can predict failures in the device by periodically issuing the SMART Return Status subcommand FR register DAh to reference the CL and CH registers 5 50 C141 E093 01 EN If an attribute value is below the insurance failure threshold value the device is about to fail or the device is nearing the end of its life In this case the host recommends that the user quickly backs up the data At command issuance I O registers setting contents 1F74 CM 1 0 1 1 0 0 0 0 1 5 Key C2h 1F44 CL Key 4Fh 1F3y SN XX 1F24 SC XX IFI amp FR Subcommand At command completion 1 O registers setting contents 1F54 CH Key failure prediction status C2h 2Ch 1FA44 CL Key failure prediction status 4Fh F4h 1F34 SN XX 1F24 SC XX 1 15 Error information The attribute value information is 512 byte data the format of this data is shown below The host can access this data using the SMART Read Attribute Values subcommand FR register DOh The insurance failure threshold value data is 512 byte data the format of this data is shown below The host can access this data using the SMART Read Attribute Thresholds subcommand FR register D1h C141 E093 01 EN 5 51 Table 5 9 Format of device attribute value data attribute 30 that of bytes 02 t
162. w register L LBA logical block address setting bit SN Sector Number register DV Device address bit SC Sector Count register x xx Do not care no necessary to set C141 E093 01 EN 1 Note 1 When the L bit is specified to 1 the lower 4 bits of the DH register and all bits of the CH CL and SN registers indicate the LBA bits bits of the DH register are the MSB most significant bit and bits of the SN register are the LSB least significant bit 2 Aterror occurrence the SC register indicates the remaining sector count of data transfer 3 the table indicating I O registers contents in this subsection bit indication is omitted READ SECTOR S 20 or X21 This command reads data of sectors specified in the Sector Count register from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers Number of sectors can be specified to 256 sectors in maximum To specify 256 sectors reading 00 is specified For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the device performs a implied seek After the head reaches to the specified track the device reads the target sector The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition Upon the completion of the command execution command block registers contain the cylinder head and sector
163. when the host system selects the slave device the diagnostic code of the slave device is posted Features register X 1F1 The Features register provides specific feature to a command For instance it is used with SET FEATURES command to enable or disable caching Sector Count register X 1F2 The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request from the host system That is this register indicates the number of remaining sectors that the data has not been transferred due to the error The contents of this register has other definition for the following commands INITIALIZE DEVICE PARAMETERS FORMAT TRACK SET FEATURES IDLE STANDBY and SET MULTIPLE MODE Sector Number register X 1F3 The contents of this register indicates the starting sector number for the subsequent command The sector number should be between X 01 and the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command Under the LBA mode this register indicates LBA bits 7 to 0 C141 E093 01 EN 5 9 6 7
164. y and the device is still in the idle mode Reset hardware or software IDLE command IDLE IMMEDIATE command A command with out Seek or Write or Read is issued Standby mode In this mode the VCM circuit is turned off and the spindle motor is stopped The device can receive commands through the interface However if a command with disk access is issued response time to the command under the standby mode takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately The drive enters the standby mode under the following conditions e A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode e When automatic power down sequence is enabled the timer has elapsed e reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software e STANDBY command e STANDBY IMMEDIATE command e INITIALIZE DEVICE PARAMETERS command C141 E093 02EN 6 9 4 6 4 e INITIALIZE DEVICE PARAMETERS command e CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode The drive enters only the standby mode from the sleep mode The only method to return from the standby mode is to execute a software or hardware reset The drive enters the sleep mode under the following condition e A SLEEP command is issued Issu

Fujitsu MPE3XXXAE User's Manual

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