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Fujitsu MPA3026AT User's Manual

1. A An Threshold E yc EqDT e e oH 0 1 1 1 1 0 10 1 1 0 0 1 1 1 0 0 11 00 1 1 1 0 01 11 10 111 010 VDT 011 1 1 1 0 01 41 1 010111 1 11 01 01 1 110 0411 1 1101 01 1 1 01 11 11 010 MRZDT 1 1 1 0 01 1 0 041 1 1 010 110 011 1 1 0 0111 014111 0 1Byte RCK NRZDT7 1 T 1 1 NRZDT6 1 0 0 0 0 NRZDTS 1 0 0 0 1 NRZDTA 1 d 1 hu 0 NRZDT3 1 0 0 0 Ely NRZDT2 1 0 i 1 0 NRZDTI l 1 T Bn NRZDTO 1 1 d 0 il NRZDTP 0 0 0 0 1 Figure 4 6 signal transfer C141 E034 02EN 4 5 6 4 6 4 Viterbi detection circuit The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi detection circuit The Viterbi detection circuit demodulates data according to the survivor path sequence Data separator circuit The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit To write data the VFO circuit generates clocks in synchronization with the clock signals from a synthesizer 8 9 GCR decoder This circuit converts the 9 bit read data into the 8 bit NRZ data Time base generator circuit The drive uses c
2. Last LBA Start LBA lt 9 Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command the disk drive transfers the hit data in the buffer to the host system The disk drive performs the read ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system 1 Inthecase that the contents of buffer is as follows at receiving a read command HAP Completion of transferring requested data Read ahead data 22 Ait ity DAP gt Last LBA Start LBA KC 2 The disk drive starts the read ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring hit data HAP Read ahead data New read ahead data Bi aged DAP C141 E034 02EN 3 3 After completion of data transfer of hit data the disk drive performs the read ahead operation for the data area of which the disk drive transferred hit data 1 wv Read ahead data f DAP 4 Finally the cache data in the buffer is as follows Read ahead data gt Start LBA Last LBA c Non sequential read command just after sequential read c
3. 5 TI Sustained Ultra DMA data in ener nennen nenne 5 80 Host pausing Ultra DMA data in 5 81 Device terminating an Ultra DMA data in burst sse 5 82 Host terminating an Ultra DMA data in 5 83 Initiating an Ultra DMA data out burst essere nennen nennen 5 84 Sustained Ultra DMA data out burst nennen nennen enne 5 85 Device pausing an Ultra DMA data out 5 86 Host terminating an Ultra DMA data out 5 87 Device terminating an Ultra DMA data out 5 88 Power on Reset Timing ee DRE IRR RET DRE EIS rE SEEE R Eiker 5 89 Response 10 6 2 Response to hardware 6 3 Response t SoftWare TESEL oet diede iced eed teet ees 6 4 Response to diagnostic command sessssessssseseeeeerenrenne ener trennen nennen 6 5 Address translation example in CHS mode esee rennen 6 7 Address translation example in LBA 6 8 Sector sp prEOCeSSIDB d en eco Ue RR RE Re Ue EE RENI EUER Up 6 11 Alternate cylinder assignment opone pter rte RR Re 6 12 Data buffer Configuration seni nene trennen eren 6 13
4. Read Channel RDC SSI32P4910 SH7600 or SH7650 SYSCLK Preamplifier TLS24306 i i Bus 0 RST CSEL DEN MEM T MEM EE Voice Coil Motor Reset B Data ADDR 0 15 0 8 Servo Controller SVC HAI3525A Data 0 15 Addr 0 16 Data 0 9 Addr 1 2 Servo Demodulate Data 0 15 Addr 0 8 Data Buffer Flash ROM Spindle Motor m Mn 64Kx16 Controller DRAM T 64Kbitx16 Disk Enclosure Printed Circuit Assembly Board blo umg Sed ee ea ey ee eas ee ee 4 4 Power on Sequence Figure 4 3 describes the operation sequence of the disk drive at power on The outline is described below a b 4 After the power is turned on the disk drive executes the MPU bus test internal register read write test and work RAM read write test When the self diagnosis terminates successfully the disk drive starts the spindle motor The disk drive executes self diagnosis data buffer read write test after enabling response to the ATA bus After confirming that the spindle motor has reached rated speed the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM This unlocks the heads which are parked at the inner circumference of the disks The disk drive positions the heads o
5. IOCS16 When the IDD receives a command that hits the cache data during read ahead and transfers data from the buffer without reading from the disk medium Figure 5 3 Read Sector s command protocol Even if the error status exists the drive makes a preparation setting the DRQ bit of data transfer Itis up to the host whether data is transferred In other words the host should receive the data of the sector 512 bytes of uninsured dummy data or release the DRQ by resetting 5 56 C141 E034 02EN 5 4 2 Note For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to 50 us after the completion of the sector data transfer Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple sector reading If the timing to read the Status register does not meet above condition normal data transfer operation is not guaranteed When the host new command even if the device requests the data transfer setting in DRQ bit the correct device operation is not guaranteed Command Status read Parameter write VV BSY DRDY DRQ INTRQ DIRAS Transfers dummy data The host should receive 512 byte dummy data or re
6. IDLE X 97 or X E3 Upon receipt of this command the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the idle mode If the spindle of the device is already rotating the spin up sequence shall not be implemented If the contents of the Sector Count register is other than 0 the automatic power down function is enabled and the timer starts countdown immediately When the timer reaches the specified time the device enters the standby mode If the contents of the Sector Count register is 0 the automatic power down function is disabled Enabling the automatic power down function means that the device automatically enters the standby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts countdown after completion of the command execution The period of timer count is set depending on the value of the Sector Count register as shown below Sector Count register value Point of timer 241t0 251 X FI to X FB 254 to 255 to X FF At command issuance I O registers setting conten
7. 1F5 CH 1FAg CL 1F3 amp SN 1F24 SC 1F14 FR C141 E034 02EN At command completion 1 registers contents to be read oe 07 _ 1 5 1F44 CL XX 1F3y SN XX 1F2y SC XX 1 15 Error information 10 SEEK X 7x to This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt The IDD always sets the DSC bit Drive Seek Complete status of the Status register to 1 In the LBA mode this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address At command issuance I O registers setting contents Head No LBA MS 1F5 CH Cylinder No MSB LBA 1F4 CL Cylinder No LSB LBA 1F3 SN Sector No LBA LSB 1F2 4 SC 1F14 FR At command completion I O registers contents to be read 1F64 DH Head No LBA MSB 1F5g CH Cylinder No MSB LBA 1 Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1F24 SC 1 15 Error information C141 E034 02EN 5 27 11 12 INITIALIZE DEVICE PARAMETERS 91 The host system can set the number of sectors per track and the maximum head number maximum head number is number of heads minus 1 per cylin
8. rente e ed tete ve ule e eU Eee dee eter denen 2 4 22222 drnyeconnection rro sr etre ERR RIPE NE ERE REPRESENTS 2 4 22222 Zdrvesconnection cst epe repetere epu Mie ede 2 5 CHAPTER3 INSTALLATION CONDITIONS eerte 3 1 3 1 Dimensions iren Rer E es 3 1 3 2 Mounting dede eei eaedem uie 3 3 3 3 Cable Connections an Irae ect dete 3 7 3 3 1 connectobs ener edet ide A ee odes 3 7 3 3 2 Cable connector specifications iere ete tei pel 3 8 9 25 D vice connection oret bn pee die petet p een E 3 8 3 3 4 Power supply connector 3 9 3 4 Jumper Settmgs au iecit eno atn Ul m eise diet ues 3 9 C141 E034 02EN Vil 3 4 1 Location of setting jumpers nennen entren rennen trennen entren nennen 3 9 3 4 2 Factory default setting eme e en tete leet ete eee e oe alters 3 10 343 Jumper configuration eene cet tei eet ln ee eR HE terr 3 10 CHAPTER4 THEORY OF DEVICE OPERATION eere 4 1 41 eae a 4 1 4 2 Nibethnrm EE 4 1 4242 Sere bete bec Ere pec 4 1 ADD amp xui uber eue teu ust ue tee tei pu 4 2 42 3 tutt U OUR Rn no dita ip tn letus 4 3 424b ACIUA
9. Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error except for bad sector uncorrectable error and SB not found and Aborted Command Bit 3 Unused Bit 2 Aborted Command ABRT This bit indicates that the requested command was aborted due to a device status error e g Not Ready Write Fault or the command code was invalid Bit 1 Track 0 Not Found TKONF This bit indicates that track 0 was not found during RECALIBRATE command execution Bit 0 Address Mark Not Found This bit indicates that an SB not found error has been encountered C141 E034 02EN 3 4 5 Diagnostic code 01 Error Detected X 02 HDC Register Compare Error X 03 Data Buffer Compare Error 05 Sum Check Error X 80 Device 1 slave device Failed Error register of the master device is valid under two devices master and slave configuration If the slave device fails the master device posts X 80 OR the diagnostic code with its own status X 01 to X 05 However when the host system selects the slave device the diagnostic code of the slave device is posted Features register X 1F1 The Features register provides specific feature to a command For instance it is used with SET FEATURES command to enable or disable caching Sector Count register X 1F2 The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between
10. FUJITSU MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVES PRODUCT MANUAL C141 E034 02EN REVISION RECORD pee August 1997 Specification No C141 E034 EN C141 E034 02EN The contents of this manual is subject to change without prior notice Rights Reserved Copyright 1997 FUJITSU LIMITED This manual describes the MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT 3 5 inch hard disk drive with a BUILT IN controller that is compatible with the ATA interface This manual explains in detail how to incorporate the hard disk drives into user systems This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems This manual consists of the following six chapters Chapter 1 DEVICE OVERVIEW Chapter 2 DEVICE CONFIGURATION Chapter 3 INSTALLATION CONDITIONS Chapter 4 THEORY OF DEVICE OPERATION Chapter 5 INTERFACE Chapter 6 OPERATIONS Chapter 7 MISCELLANEOUS In this manual disk drives may be referred to as drives or devices C141 E034 02EN iii Conventions for Alert Messages This manual uses the following conventions to show the alert messages An alert message consists of an alert signal and alert statements The alert signal consists of an alert symbol and a signal word or just a signal word The following are the alert signals and their meanings This indicates a hazarous situation likely to result in
11. 5 The host shall negate 50 CS1 DA2 DAI and DAO The host shall keep CSO CS1 DA2 DAI and DAO negated until after negating DMACK at the end of the burst 6 Steps 3 4 and 5 shall have occurred at least tack before the host asserts DMACK The host shall keep DMACK asserted until the end of an Ultra DMA burst 7 The host shall release DD 15 0 within t4z after asserting DMACK 8 The device may assert DSTROBE tzjiogpy after the host has asserted DMACK Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK at the end of an Ultra DMA burst 9 The host shall negate STOP and assert HOMARDY within tgnv after asserting DMACK After negating STOP and asserting HDMARDY the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device 1 after the first data word has been received 10 The device shall drive DD 15 0 no sooner than after the host has asserted DMACK negated STOP and asserted HDMARDY C141 E034 02EN 5 63 5 5 3 2 5 5 3 3 11 The device shall drive the first word of the data transfer onto DD 15 0 This step may occur when the device first drives DD 15 0 in step 10 12 To transfer the first word of data the device shall negate DSTROBE within tps after the host has negated STOP and asserted HDMARDY The device shall negate DSTROBE no sooner than tpys after d
12. GND GROUND Figure 5 1 Interface signals 5 2 C141 E034 02EN 5 1 2 Signal assignment on the connector Table 5 1 shows the signal assignment on the interface connector Table 5 1 signal RESET DATA 0 15 IOW STOP RESET DATA7 DATA6 DATAS DATA4 DATA3 DATA2 DATAI DATAO GND DMARQ IOW STOP Signal assignment on the interface connector Signal Pin No GND DATAS DATA9 10 DATAII 12 DATAI13 DATAI4 DATAIS KEY GND GND IOR HDMARDY HSTROBE GND IORDY DDMARDY DSTROBE CSEL DMACK INTRQ DAI DAO CS0 DASP GND IOCS16 PDIAG DA2 CS1 GND Description Reset signal from the host This signal is low active and is asserted for a minimum of 25 us during power on Sixteen bit bi directional data bus between the host and the device These signals are used for data transfer IOW is the strobe signal asserted by the host to write device registers or the data port IOW shall be negated by the host prior to initiation of an Ultra DMA burst STOP shall be negated by the host before data is transferred in an Ultra DMA burst Assertion of STOP by the host during an Ultra DMA burst signals the termination of the Ultra DMA burst C141 E034 02EN 5 3 signal IOR HDMARDY HSTROBE INTRQ IOCS16 CS0 CS1 DA 0 2 KEY PIDAG DASP Description IOR is the strob
13. When the timer value reaches 0 passed a specified time the device enters the standby mode If the contents of the Sector Count register is 0 the automatic power down function is disabled Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as the READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting contents 1F74 CM X 96 or X E2 man 1F5g CH 1F44 CL XX 1F3y SN XX 1F2y SC Period of timer 1F1y FR XX At command completion I O registers contents to be read mam eT x oe 1F5 CH 1F4 CL XX 1F34 SN XX 1 2 5 1F1y ER Error information STANDBY IMMEDIATE 94 or X E0 Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt This command does not support the automatic power down sequence C141 E034 02EN 26 At command issuance I O registers setting contents 1F74 CM X 94 or X EO Xx Xx Xx Xx Xx 1F5 CH 1F4 CL 1F34 SN 1F24 SC 1F14 FR At command completion I O registers contents to be read 1F54 CH 1F4 CL XX 1F3 SN XX 1 2 5 1F1y ER Error information SLEEP 99 or X E6 This command is the only way to make the device enter the sleep mode Upon receipt of
14. al TE 1 2 3 4 5 6 7 247 248 249 Sector logical If an access request to sector 5 is specified the device accesses physical sector 6 instead of sector 5 Figure 6 7 Sector slip processing C141 E034 02EN 6 11 2 Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder This processing is performed when the automatic alternate processing is performed Figure 6 8 shows an example where physical sector 5 is detective on head 0 in cylinder 0 Index J olestie he tet Sector physical 1 2 3 4 5 6 7 249 250 CyindrO L 11 qd v efective sector 0 DLL 2 3 4 unused 6 7 248 249 Sector logical Alternate Le ERAI cylinder Already assigned HeadO Defective sector is assigned to unassigned sector 4 alternate cylinders are provided for each head in zone 14 inner side When an access request to sector 5 is specified the device accesses the alternated sector in the alternate cylinder instead of sector 5 When an access request to sectors next to sector 5 is specified the device seeks to cylinder 0 head 0 and continues the processing Figure 6 8 Alternate cylinder assignment 6 12 C141 E034 02EN 3 6 5 6 5 1 Automatic alternate assignment The device performs the automatic assignment at following case 1 When E
15. Write Precompensation lt Precoder lt Encoder Read Channel RDS PPOL NRZDT 0 7 P RCLK WCLK 4 6 3 1 2 3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control AGC circuit Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit This clock signal is converted into the NRZ data by the 8 9 GCR decoder circuit based on the read data maximum likelihood detected by the Viterbi detection circuit then 1s sent to the HDC AGC circuit The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions Programmable filter The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off frequency of the low pass filter and boost up gain are controlled from each DAC circuit in read channel by an instruction of the serial data signal from MPU M1 The MPU optimizes the cut off frequency and boost up gain according to the transfer frequency of each zone Figure 4 5 shows the frequency
16. C141 E034 02EN TABLES page 1 1 Specifications he erem e nU DDR DU epu 1 4 1 2 Model names and product numbers 1 5 1 3 Current and power dissipation 1 6 1 4 Environmental specifications eig etie dee netter pde ine 1 8 1 5 Acoustic noise specification tto reb ES eie tre bec pes 1 8 1 6 Shock and vibration 1 9 3 1 Surface temperature measurement points and standard values esses 3 5 3 2 Cable connector specifications 2 3 8 4 1 Self calibration execution timechart esses 4 9 4 2 Write precompensation algorithm esses nennen 4 10 4 3 Write clock frequency and transfer rate of each 2 4 15 5 1 Signal assignment the interface connector eene 5 3 5 2 Rd ec TU qiie ges 5 7 5 3 Command code and parameters esses nete trennen 5 14 5 4 Information to be read by IDENTIFY DEVICE 5 30 5 5 Features register values and settable modes sse 5 34 5 6 Diagnostic code eee Gee Dente pte one DOR Dite ER DD 5 37 5 7 Features register values subcommands
17. The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 8 and 5 6 4 2 for specific timing requirements 1 The host shall drive a data word onto DD 15 0 2 The host shall generate an HSTROBE edge to latch the new word no sooner than tpys after changing the state of DD 15 0 The host shall generate an HSTROBE edge no more frequently than tcyc for the selected Ultra DMA Mode The host shall not generate two rising or falling HSTROBE edges more frequently than 2 for the selected Ultra DMA mode 3 The host shall not change the state of DD 15 0 until at least tpyy after generating HSTROBE edge to latch the data 4 The host shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first Pausing an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 9 and 5 6 4 2 for specific timing requirements a Host pausing an Ultra DMA data out burst 1 The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 The host shall pause an Ultra DMA burst by not generating an HSTROBE edge Note The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate
18. 25 3 3 Limitation of sid mo nting Pe epe toes 3 4 Mounting frame DERE 3 4 Surface temperature measurement points 3 5 sc oen D oce A Go edo ie RE eere tote 3 6 Connector LOCA ONS wired fy eid n een ice nti eite dti ed e es 3 7 Cable connections 3 eene need ete peine ap a e e e ep cts 3 8 Power supply connector pins 222 0 4 221 0 000000 ener eene 3 9 T imper location ooo HUN ERR MIRO SUO t Ee php 3 9 Factory default setting e e nU iat etes tdt 3 10 Jumper setting of master or slave device 3 10 Jumper setting of Cable 3 11 Example 1 GF Cable Select ita te etr d tete ee etit er Ee eig 3 11 Example 2 0f Cable tette ne eee ete ie n pee Eine eee Pieds 3 11 Head structure 2 ere neri e tee 4 2 Block 4 5 Pow tonop r tio seg entes 4 7 Read write circuit block 4 11 Frequency characteristic of program
19. Figure 5 22 shows power on and reset hardware and software reset timing 1 Only master device is present V Clear Reset 1 Power on 5 Software reset tN Pu NAUES tP gt Reset means including Power on Reset Hardware Reset RESET and Software Reset 2 Master and slave devices are present 2 drives configuration Clear Reset Master device E tN Slave device IE BSY 7 UI tM Pulse width of RESET 25 us tN Time from RESET negation to BSY set EE 400 ns tQ Self diagnostics execution time SEF R Time from RESET negation to DASP assertion slave device E 400 ms tS Duration of DASP assertion ESEEC S Figure 5 22 Power on Reset Timing Time from RESET negation to DASP or DIAG negation ES C141 E034 02EN 5 89 6 OPERATIONS 6 1 6 2 6 3 6 4 6 5 6 6 Device Response to the Reset Address Translation Power Save Defect Management Read Ahead Cache Write Cache 6 1 Device Response to the Reset This section describes how the PDIAG and DASP signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command 141 034 02 6 1 1 Response to power on After the master device device 0 releases its own power on reset state the master device shall ch
20. If the host negates HDMARDY within tsr after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARDY greater than tsr after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay tgrs timing for the device The host shall assert STOP no sooner than tgp after negating HDMARDY The host shall not negate STOP again until after the Ultra DMA burst is terminated The device shall negate DMARQ within ty after the host has asserted STOP The device shall not assert DMARQ again until after the Ultra DMA burst is terminated If DSTROBE is negated the device shall assert DSTROBE within tj after the host has asserted STOP No data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra DMA burst is terminated The device shall release DD 15 0 no later than taz after negating DMARQ The host shall drive DD 15 0 no sooner than tzay after the device has negated DMARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 C141 E034 02EN 5 5 4 5 5 4 1 10 If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall
21. This subcommand disables the failure prediction feature The setting is maintained even when the device is turned off and then on When the device receives this subcommand it asserts the BSY bit disables the failure prediction feature then clears the BSY bit SMART Return Status When the device receives this subcommand it asserts the BSY bit and saves the current device attribute values Then the device compares the device attribute values with insurance failure threshold values If there is an attribute value exceeding the threshold F4h and 2Ch are loaded into the CL and CH registers If there are no attribute values exceeding the thresholds 4Fh and C2h are loaded into the CL and CH registers After the settings for the CL and CH registers have been determined the device clears the BSY bit The host must regularly issue the SMART Read Attribute Values subcommand FR register DOh SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register DAh to save the device attribute value data on a medium Alternative the device must issue the SMART Enable Disable Attribute AutoSave subcommand FR register D2h to use a feature which regularly save the device attribute value data to a medium 5 48 C141 E034 02EN The host can predict failures in the device by periodically issuing the SMART Return Status subcommand FR register DAh to reference the CL and CH registers If an
22. X 00684EF0 MPA3035AT X 00684EF0 X 008262AC MPA3043AT X 008262AC X 009C7668 MPA3052AT X 009C7668 07 Multiword DMA transfermode 9 64 900 AdvancePlOWansfermodesupportsttus 10 078 Minimum muttiword DMA transfer cycle time per word 120 ns O 66 Manufacturer s recommended transfer cycle time 120 ns 67 Minimum PIO transfer cycle time without flow control 240 ns 80 Majrvesnmumbertll o X000 Mimorvesinnumber mtrpored o 32 sSupprofcommadses I2 o 84 87 68 X 0078 Minimum PIO transfer cycle time with IORDY flow control 120 ns X 4000 Support of command sets fixed 84 87 8 0000 or Ultra modes 13 X 0X07 62 63 64 65 67 80 81 82 83 8 5 30 C141 E034 02EN Table 5 4 Information to be read by IDENTIFY DEVICE command 2 of 3 89 127 Security status not supported 129 159 Undefined 160 255 Reserved 1 Word 0 General configuration Bit 15 0 ATA device Bit 14 8 Vendor specific Bit 7 1 Removable media device Bit 6 1 2 not removable controller and or device Bit 5 1 Vendor specific Bit 0 Reserved 2 Word 10 19 Serial number ASCII code 20 characters right justified 3 Word 23 26 Firmware revision ASCII code 8 characters Left justified 4 Word 27 46 Model number ASCII code
23. and 5 may occur in any order or at the same time The host shall assert STOP The host shall assert HSTROBE The host shall negate 50 51 DA2 DAI and DAO The host shall keep CSO CSI DA2 DAI and DAO negated until after negating DMACK at the end of the burst Steps 3 4 and 5 shall have occurred at least before the host asserts DMACK The host shall keep DMACK asserted until the end of an Ultra DMA burst The device may negate DDMARDY tzjorpy after the host has asserted DMACK Once the device has negated DDMARDY the device shall not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst The host shall negate STOP within after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE C141 E034 02EN 5 67 5 5 4 2 5 5 4 3 9 The device shall assert DDMARDY within tj after the host has negated STOP After asserting DMARQ and DDMARDY the device shall not negate either signal until after the first negation of HSTROBE by the host 10 The host shall drive the first word of the data transfer onto DD 15 0 This step may occur any time during Ultra DMA burst initiation 11 To transfer the first word of data the host shall negate HSTROBE no sooner than t after the device has asserted DDMARDY The host shall negate HSTROBE no sooner than tpys after the driving the first word of data onto DD 15 0 The data out transfer
24. mode Then a current approx 1 3 A flows into the spindle motor c The SVC generates a phase switching signal by itself and changes the phase of the current flowed in the motor in the order of V phase to U phase W phase to U phase W phase to V phase U phase to V phase U phase to W phase and V phase to W phase after that repeating this order d During phase switching the spindle motor starts rotating in low speed and generates a counter electromotive force The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection C141 E034 02EN 4 21 2 3 e The MPU is waiting for a PHASE signal When no phase signal is sent for specific period the MPU resets the SVC and starts from the beginning When a PHASE signal is sent the SVC enters the acceleration mode Acceleration mode In this mode the MPU stops to send the phase switching signal to the SVC The SVC starts a phase switching by itself based on the counter electromotive force Then rotation of the spindle motor accelerates The MPU calculates a rotational speed of the spindle motor based on the PHASE signal from the SVC and accelerates till the rotational speed reaches 5 400 rpm When the rotational speed reaches 5 400 rpm the SVC enters the stable rotation mode Stable rotation mode The MPU calculates a time for one revolution of the spindle motor based on the PHASE signal from the SVC The MPU
25. see Sections 4 3 Disk The DE contains the disks with an outer diameter of 95 mm The MPA3017AT has 1 disk the MPA3026AT MPA3035AT have 2 disks MPA3043AT MPA3052AT have 3 disks The head contacts the disk each time the disk rotation stops the life of the disk is 40 000 contacts or more Servo data is recorded on each cylinder total 60 Servo data written at factory is read out by the read write head For servo data see Section 4 7 C141 E034 02EN 4 1 42 2 Head Figure 4 1 shows the read write head structures The MPA3017AT has 2 read write heads the MPA3026AT has 3 MPA3035AT has 4 MPA3043AT has 5 and MPA3052AT has 6 These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed MPA3017 Model Spindle Actuator 1 rS MPA3026AT Model MPA3035AT Model Spindle Actuator Spindle Actuator 3 un 2 1 1 o UE MPA3043AT Model MPA3052AT Model Spindle Actuator Spindle Actuator 5 1 4 3 3 2 20 0 0 Figure 4 1 Head structure 4 2 C141 E034 02EN 4 2 3 4 2 4 4 2 5 Spindle The spindle consists of a
26. 3 249 250 Physical cylinder 1 LBA LBA LBA LBA LBA Physical head 0 250 251 252 498 499 6 3 6 3 1 ex Zone 0 Physical parameter Physical sector 1 to 250 Figure 6 6 Address translation example in LBA mode Power Save The host can change the power consumption state of the device by issuing a power command to the device Power save mode There are four types of power consumption state of the device including active mode where all circuits are active In the power save mode power supplying to the part of the circuit is turned off There are three types of power save modes e Idle mode e Standby mode e Sleep mode The drive moves from the Active mode to the idle mode by itself C141 E034 02EN 1 2 3 Regardless of whether the power down is enabled the device enters the idle mode device also enters the idle mode in the same way after power on sequence is completed Active mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions e Power on sequence is completed e Acommand other than power commands is issued Reset hardware or software Idle mode In this mode circuits on the device is set to power save mode The device enters the Idle mode under the following conditions e After completion of power on sequence e After completi
27. For information about the format of the attribute value information see Table 5 8 X D SMART Read Attribute Thresholds This subcommand is used to transfer 512 byte insurance failure threshold value data to the host For information about the format of the insurance failure threshold value data see Table 5 9 X D2 SMART Enable Disable Attribute AutoSave This subcommand is used to enable SC register 00h or disable SC register 00h the setting of the automatic saving feature for the device attribute data The setting is maintained every time the device is turned off and then on When the automatic saving feature is enabled the attribute values are saved before the device enters the power saving mode However if the failure prediction feature is disabled the attribute values are not automatically saved When the device receives this subcommand it asserts the BSY bit enables or disables the automatic saving feature then clears the BSY bit X D3 SMART Save Attribute Values When the device receives this subcommand it asserts the BSY bit saves device attribute value data then clears the BSY bit X D8 SMART Enable Operations This subcommand enables the failure prediction feature The setting is maintained even when the device is turned off and then on When the device receives this subcommand it asserts the BSY bit enables the failure prediction feature then clears the BSY bit X Do SMART Disable Operations
28. Rte 5 1 5 1 Physical Interface Reset Ss RA a el eS 5 2 25 1 Jnterf ce ognals s cem ORE ete eee base ab Sess RAE ee ORE siters 5 2 5 1 2 Signal assignment on the connector essere nennen eene enne 5 3 5 2 Logical Interface eet ome Db eere detiene 5 6 J Oiregisters Deine i eet Ee de du ee 5 6 Vili C141 E034 02EN 5 2 22 Command block registers 4 0422 4 2 20100000000000 5 8 5 2 2 Control block registers oce beet etes eee iet le tetur be tec eet eee ponen 5 13 5 3 Host Commands ene Ce TEC Dre D URP RE 5 13 5 3 1 Command code and parameters sss nennen nennen nennen 5 14 5 32 Command descriptions 5 16 3 3 3 POSUDE ree eee eee e eee od ee etse ere ete aet 5 54 5 4 Command Protocol 2 5 prit e tete pereo rerit eere a 5 55 5 4 1 Data transferring commands from device to 5 55 5 4 2 Data transferring commands from host to device 5 57 5 4 5 Commands without data eene 5 59 5 444 Othercommiands nnnc te Din ne Od RO DRE iadasesdbesseessgetapeasectoet ss 5 60 5 4 5 data transfer commands sese nee 5 60 9 5 Ultra 2 io 5 62 5 9 T CCOVEEVIEW s eoe Her rd e
29. The host shall assert STOP no sooner than tss after it last generated an HSTROBE edge The host shall not negate STOP again until after the Ultra DMA burst is terminated The device shall negate DMARQ within t after the host asserts STOP The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The device shall negate DDMARDY with ty after the host has negated STOP The device shall not assert DDMARDY again until after the Ultra DMA burst termination is complete If HSTROBE is negated the host shall assert HSTROBE with tj after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than ty after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than tpys after placing the result of its CRC calculation on DD 15 0 The device shall latch the host s data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5
30. V Valid on this command See the command descriptions lt lt lt lt Ur lt i lt lt lt lt lt lt lt lt lt 1 lt lt lt lt lt 1 1 lt lt lt 1 lt lt 5 54 C141 E034 02EN 5 4 5 4 1 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command If BSY bit is 1 the host should wait for issuing a command until BSY bit is cleared to 0 Commands can be executed only when the DRDY bit of the Status register is 1 However the following commands can be executed even if DRDY bit is 0 EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS Data transferring commands from device to host The execution of the following commands involves data transfer from the device to the host IDENTIFY DEVICE IDENTIFY DEVICE DMA READ SECTOR S READ LONG READ BUFFER SMART SMART Read Attribute Values SMART Read Attribute Thresholds The execution of these commands includes the transfer one or more sectors of data from the device to the host In the READ LONG command 516 bytes are transferred Following shows the protocol outline a b 4 The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers The host writes a command code to the Command register The device sets the BSY bit of the Status register and prepares for data transfer
31. When one sector or block of data is available for transfer to the host the device sets DRQ bit and clears BSY bit The drive then asserts INTRQ signal After detecting the INTRQ signal assertion the host reads the Status register The host reads one sector of data via the Data register In response to the Status register being read the device negates the INTRQ signal The drive clears DRQ bit to 0 If transfer of another sector is requested the device sets the BSY bit and steps d and after are repeated Even if an error is encountered the device prepares for data transfer by setting the DRQ bit Whether or not to transfer the data is determined for each host In other words the host should receive the relevant sector of data 512 bytes of uninsured dummy data or release the DRQ status by resetting Figure 5 3 shows an example of READ SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort C141 E034 02EN 5 55 Command Parameter write v Status read Status read m b c re e e e 4 a e BSY i DRDY d d DRQ o o o o Data transfer Expanded am ox Command zoe Min 30 pis 1 DRQ p INTRQ Data Reg Selection E gt Data X X FEE X eos P Word 0 2 255
32. Xx Xx 1F5 CH 1F4 CL 1F34 SN 1F24 SC 1F14 FR At command completion I O registers contents to be read 1F54 CH 1F4 CL XX 1F3 SN XX 1F24 SC 00 or X FF 1F1y ER Error information SMART X B0 This command performs operations for device failure predictions according to a subcommand specified in the FR register If the value specified in the FR register is supported the Aborted Command error is posted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is disabled In this case the Aborted Command error is posted in response to subcommands other than SMART Enable Operations FR register D8h When the failure prediction feature is enabled the device collects or updates several items to forecast failures In the following sections note that the values of items collected or updated by the device to forecast failures are referred to as attribute values C141 E034 02EN 5 47 Table 5 7 Features Register values subcommands and functions Features Resister Function X DO SMART Read Attribute Values A device that received this subcommand asserts the BSY bit and saves all the updated attribute values The device then clears the BSY bit and transfers 512 byte attribute value information to the host
33. and 5 48 5 8 Format of device attribute value data sese eee 5 50 5 9 Format of insurance failure threshold value data see 5 51 5 10 Command code and parameters essent eren nennen nennen nennen nennen 5 54 5 11 Recommended series termination for Ultra DMA sse 5 72 5 12 Ultra DMA data burst timing requirements 24 nene 5 78 6 1 Default parameters ss o Lucem eerte Uere rU pde in Oleo etate git 6 6 C141 E034 02EN xiii 1 DEVICE OVERVIEW 11 Features 12 Device Specifications 13 Power Requirements 14 Environmental Specifications 15 Acoustic Noise 16 Shock Vibration 17 Reliability 18 Error Rate 19 Media Defects Overview and features are described in this chapter and specifications and power requirement are described MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT is 3 5 inch hard disk drive with a built in ATA controller The disk drive is compact and reliable 1 1 1 1 1 1 2 3 Features Functions and performance Compact The disk has 1 2 or 3 disks of 95 mm 3 5 inches diameter and its height is 25 4 mm 1 inch Large capacity The disk drive can record up to 1 750 MB formatted on one disk using the 8 9 PRML recording method and 15 recording zone technology The MPA3017AT MPA3026AT MPA3035AT MPA3043AT and MPA3052AT have a
34. attribute value is below the insurance failure threshold value the device is about to fail or the device is nearing the end of it life In this case the host recommends that the user quickly backs up the data At command issuance I O registers setting contents 1F74 CM 1 0 1 1 0 0 0 0 5 Key C2h IFA44 CL Key 4Fh 1F3y SN XX 1F24 SC XX 1F1yCFR Subcommand At command completion I O registers setting contents 1 5 Key failure prediction status C2h 2Ch 1F4 CL Key failure prediction status 4Fh F4h 1F34 SN 1 2 5 1F1y ER Error information C141 E034 02EN 5 49 The attribute value information is 512 byte data the format of this data is shown below host can access this data using the SMART Read Attribute Values subcommand FR register DOh The insurance failure threshold value data is 512 byte data the format of this data is shown below The host can access this data using the SMART Read Attribute Thresholds subcommand FR register D1h Table 5 8 Format of device attribute value data Attribute 1 Attribute ID Status flag 04 Attribute value for worst case so far Raw attribute value Reserved Attribute 2 to The format of each attribute value is the same as that attribute 30 of bytes 02 to OD Reserved Failure prediction capability flag Reserved Vendor specific 5 50 141 034 02 Table 5 9 Format of insurance failure threshold value
35. completion I O registers contents to be read 1F6 DH End head No LBA MSB 1F5g CH End cylinder No MSB LBA 1 End cylinder No LSB LBA 1F3y SN End sector No LBA LSB 1F2 4 SC 00g 1F1y ER Error information C141 E034 02EN 5 19 3 Note If the command is terminated due to an error the remaining number of sectors for which data was not transferred is set in this register READ DMA X C8 or X C9 This command operates similarly to the READ SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion device controls the assertion or negation timing of the DMARQ signal e The device posts a status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode are set T
36. formatted capacity of 1 750 MB 2 625 MB 3 500 MB 4 375MB and 5 250MB respectively High speed Transfer rate The disk drive has an internal data rate up to 14 96 MB s The disk drive supports an external data rate up to 16 7 MB s or 33 3 MB s ultra DMA mode C141 E034 02EN 1 1 4 1 2 3 1 2 3 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 10 ms at read Adaptability Power save mode The power save mode feature for idle operation stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor Wide temperature range The disk drive can be used over a wide temperature range 5 C to 55 C Low noise and vibration In Ready status the noise of the disk drive is only about 35 dBA measured at 1 m apart from the drive under the idle mode Interface Connection to interface With the built in ATA interface controller the disk drive can be connected to an ATA interface of a personal computer 128 KB data buffer The disk drive uses 128 KB data buffer to transfer data between the host and the disk media In combination with the read ahead cache system described in item 3 and the write cache described in item 6 the buffer contributes to efficient I O processing Read ahead cache system After the execution of a disk read comman
37. of the write operation to the disk medium of the previous command Even if a hard reset or soft reset is received or the write cache function is disabled by the SET FEATURES command during unwritten data is kept the instruction is not executed until remaining unwritten data is written onto the disk medium The drive uses a write data as a read cache data When a read command is issued to the same address after the write command the read operation to the disk medium is not performed When an error occurs during the write operation the drive makes retry as much as possible If the error cannot be recovered by retry the drive stops the write operation to the erred sector and continues the write operation from the next sector if the write data is remained If the drive stacks a write command for that the drive posts the command completion next to the command that write operation is stopped by error occurrence After an error occurs at above write operation the drive posts the error status to the host system at next command drive does not execute this command sets the error status that occurred at the write operation and generates the interrupt for abnormal end However when the drive receives a write command after the completion of error processing the drive posts the error after writing the write data of the write command C141 E034 02EN At the time that the drive has stopped the command execution after the error recovery has fa
38. seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the target track Operation to move the head to the reference cylinder The MPU moves the head to the reference cylinder when the power is turned The reference cylinder is in the data area When power is applied the heads are moved from the inner circumference shunt zone to the normal servo data zone in the following sequence a Micro current is fed to the VCM to press the head against the inner circumference b Acurrent is fed to the VCM to move the head toward the outer circumference c When the servo mark is detected the head is moved slowly toward the outer circumference at a constant speed C141 E034 02EN 2 3 4 7 5 1 d Ifthe head is stopped at the reference cylinder from there Track following control starts Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read or instruction is issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the difference speed error between the specified target position and the current position for each sampling timing during head moving The MPU then feeds the VCM drive current by setting the calculated result into the D A converter The calculation is digitally executed by the f
39. set parameters under the LBA mode N Necessary to set parameters The parameter is ignored if it is set N May set parameters D The device parameter is valid and the head parameter is ignored D The command is addressed to the master device but both the master device and the slave device execute it X Do not care C141 E034 02EN 5 15 5 3 2 Command descriptions The contents of the I O registers to be necessary for issuing a command and the example indication of the I O registers at command completion are shown as following in this subsection Example READ SECTOR S WITH RETRY At command issuance I O registers setting contents 1 7 1F6 DH See Head No LBA MSB 1F5g CH Start cylinder address MSB LBA 1F44 CL Start cylinder address LSB LBA 1F34 SN Start sector No LBA LSB At command completion I O registers contents to be read ee eE 1F74 ST Error information 1F54 CH Start cylinder address MSB LBA 1F44 CL Start cylinder address LSB LBA 1 3 5 Start sector No LBA LSB CM Command register FR Features register DH Device Head register ST Status register CH Cylinder High register ER Error register CL Cylinder Low register L LBA logical block address setting bit SN Sector Number register DV Device address bit SC Sector Count register x Do not care no necessary to set C141 E034 02EN 1 Note 1 When the L bit
40. slave device receives the software reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal X 3F6 Reg LJ X 0C lt M X 00 Master device or X 04 Status Reg BSY bit Max 31 sec lt If the slave device is preset DASP is checked for up to 31 seconds Slave device BSY bit 4 ms PDIAG Hm Max 30 sec c gt DASP Figure 6 3 Response to software reset 6 4 C141 E034 02EN 6 1 4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present the master device checks the PDIAG signal for up to 6 seconds to see if the slave device has completed the self diagnosis successfully The master device does not check the DASP signal After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating
41. status of the device 1 is read by the host system When a diagnostic failure of the device 1 is detected the host system can read a status of the device 1 by setting the DV bit selecting the device 1 When device 1 is not present e device 0 posts only the results of its own self diagnosis e device 0 clears the BSY bit of the Status register and generates an interrupt Table 5 6 lists the diagnostic code written in the Error register which is 8 bit code If the device 1 fails the self diagnosis the device 0 ORs X 80 with its own status and sets that code to the Error register Table 5 6 Diagnostic code Result of diagnostic No error detected Data buffer compare error ROM sum check error Failure of device 1 C141 E034 02EN 5 37 17 18 At command issuance I O registers setting contents 1F74 CM 1 0 0 1 0 0 0 0 XX XX XX XX XX 1F5 CH 1F4 CL 1F34 SN 1F24 SC 1F14 FR At command completion I O registers contents to be read 1F5g CH XX 1F44 CL 1IF3g SN Olg 1 1F24 SC Oly 1F1 ER Diagnostic code 1 This register indicates X 00 in the LBA mode FORMAT TRACK 507 Upon receipt of this command the device sets the DRQ bit and waits the completion of 512 byte format parameter transfer from the host system After completion of transfer the device clears the DRQ bits sets the BSY bit However the device does not perform format operation but the drive c
42. takes a difference between the current time and a time for one revolution at 5 400 rpm that the MPU already recognized Then the MPU keeps the rotational speed to 5 400 rpm by charging or discharging the charge pump for the different time For example when the actual rotational speed is 5 600 rpm the time for one revolution is 10 714 ms And the time for one revolution at 5 400 rpm is 11 111 ms Therefore the MPU discharges the charge pump for 0 397 ms x k k constant value This makes the flowed current into the motor lower and the rotational speed down When the actual rotational speed is later than 5 400 rpm the MPU charges the pump the other way This control charging discharging is performed every 1 6 revolution C141 E034 02EN 5 INTERFACE 51 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA Feature Set 5 6 Timing C141 E034 02EN 5 1 Physical Interface 511 Interface signals Figure 5 1 shows the interface signals Host DATA 0 15 DATA BUS IDD DMACK DMA ACKNOWLEDGE DMARQ DMA REQUEST IOW I O WRITE IOR I O READ INTRQ INTERRUPT REQUEST IOCS16 IOCS 16 PDIAG PASSED DIAGNOSTIC IORDY I O CHANNEL READY DASP DEVICE ACTIVE DEVICE 1 PRESENT DA 0 2 DEVICE ADDRESS CS0 CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT
43. the PDIAG signal and negates the DASP signal when asserting the PDIAG signal X 1F7 Reg Write Master device Status Reg BSY bit 6 2 If the slave device is preset DASP signal is checked for up to 6 seconds Slave device BSY bit E ox Max 1 ms Max 5 sec gt DASP Figure 6 4 Response to diagnostic command C141 E034 02EN 6 5 6 2 6 2 1 Address Translation When the IDD receives any command which involves access to the disk medium the IDD always implements the address translation from the logical address a host specified address to the physical address logical to physical address translation Following subsections explains the CHS translation mode Default parameters In the logical to physical address translation the logical cylinder head and sector addresses are translated to the physical cylinder head and sector addresses based on the number of heads and the number of sectors per track which are specified with an INITIALIZE DEVICE PARAMETERS command This is called as the current translation mode If the number of heads and the number of sectors are not specified with an INITIALIZE DEVICE PARAMETERS command the default values listed in Table 6 1 are used This is called as the default translation mode The parameters in Table 6 1 are called BIOS specification Table 6 1 De
44. the READ SECTOR S command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium The device does not generate ECC bytes by itself The WRITE LONG command supports only single sector operation The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command This command is operated under the following conditions e The command is issued in a sequence of the READ LONG or WRITE LONG to the same address command issuance WRITE LONG command can be continuously issued after the READ LONG command If above condition is not satisfied the command operation is not guaranteed C141 E034 02EN 5 39 20 At command issuance I O registers setting contents IFG DH Head No LBA MSR 1F5g CH Cylinder No MSB LBA 1 Cylinder LSB LBA 1F3y SN Sector No LBA LSB 1F24 SC Number of sectors to be transferred 1Fl4 FR R 0 gt with Retry R without Retry At command completion I O registers contents to be read 1F6 DH Head No LBA MSB 1F5g CH Cylinder No MSB LBA 1F44 CL Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1F24 SC 00 1 1 15 Error information If the command is terminated due to an error this register indicates 01 READ BUFFER X E4 The host system can read the current contents of the sector buffer of the device by issuin
45. the beginning of each block or partial block C141 E034 02EN 5 23 7 The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined To obtain a valid error information the host should retry data transfer as an individual requests At command issuance I O registers setting contents 1F64 DH FXNEXEREE Start head No LBA MSB 1F5g CH Start cylinder No MSB LBA 1 Start cylinder No LSB LBA 1F3y SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR At command completion 1 registers contents to be read 1F64 DH End head No LBA MSB 1F54 CH End cylinder No MSB LBA 1 End cylinder No LSB LBA 1F3y SN End sector No LBA LSB 1F24 SC 00g 1 15 Error information Note When the command terminates due to error only the DV bit and the error information field are valid WRITE X CA or X CB This command operates similarly to the WRITE SECTOR S command except for following events e The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data tr
46. the host system and the device When the value in this register is 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request from the host system That is this register indicates the number of remaining sectors that the data has not been transferred due to the error The contents of this register has other definition for the following commands INITIALIZE DEVICE PARAMETERS FORMAT TRACK SET FEATURES IDLE STANDBY and SET MULTIPLE MODE Sector Number register X 1F3 The contents of this register indicates the starting sector number for the subsequent command The sector number should be between 01 and the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command Under the LBA mode this register indicates LBA bits 7 to 0 C141 E034 02EN 5 9 6 7 8 Cylinder Low register X 1F4 The contents of this register indicates low order 8 bits of the starting cylinder address for any disk access At the end of a command the contents of this register are updated to the current cylinder number Under the LBA mode this register indicates LBA bits 15 to 8 Cylinder High register X 1F5 The contents of this register indicates high order 8 bits of the disk acc
47. the timings for each of the Ultra DMA Modes 5 6 4 1 Initiating an Ultra DMA data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device tui DMACK host t lack i t STOP ed dis host t trs HDMARDY A host gt a tap tzioRDY DSTROBE device taz tvos BOATS PL ALAA IR TIT 775757 DD 15 0 25 DE PEK DEDEDE tack DAO DA1 DA2 y 262026262 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and are asserted Figure 5 12 Initiating an Ultra DMA data in burst C141 E034 02EN 5 77 5 6 4 2 Ultra DMA data burst timing requirements Table 5 12 Ultra DMA data burst timing requirements MODE 0 MODE 1 MODE 2 COMMENT in ns ETH uu ES Ex MIN MIN MAX time from STROBE edge to STROBE edge Two cycle time from rising edge to next rising edge or from falling edge to next falling edge of STROBE H Data setup time at recipient z Data hold time at recipient Data valid setup time at sender from data bus being valid until STROBE edge Data valid hold time at sender from STROBE edge until data may become invalid First STROBE time for device to first negate DSTROBE from STOP during a data in burst Limited interlock time see Note 1 Interlock time with minimum see Note 1 Unlimited inter
48. to 1 MHz C141 E034 02EN 1 5 3 Current Requirements and Power Dissipation Table 1 3 lists the current and power dissipation Table 1 3 Current and power dissipation Mode of Typical RMS current 1 Typical Power 2 Operation Model MPA MPA Models MPA MPA a 3026AT 3043AT 3026 3043 3035 3052 3035 3052 pe up 13A Kew 520A 18 2 watts 1 5 A peak 0 6A Kew Idle Ready 3 onza 120 0 oua A osa 185A oma 443 A 3 66 watts 66 3 66 watts 408 wans 08 408 wans 44 R W On Track 0 130A 0 160 A 0 190 A 0 620 A 4 66 watts 5 02 watts 5 38 watts Seek Random 0 370 A 0 380 A 0 425 A 0 520 A 7 04 watts 7 16 watts 7 70 watts standby 0 01 A 040 400 A 2 12 watts 1 Current is typical rms except for spin up 2 Power requirements reflect nominal values for 12V and 5V power 3 Idle mode is in effect when the drive is not reading writing seeking or executing any commands 4 R W mode is defined as 5096 read operations and 5046 write operations on a single physical track 5 Seek mode is defined as continuous random seek operations with minimum controller delay 1 6 C141 E034 02EN 4 Current fluctuation Typ at 5V when power is turned on Note Maximum current is 1 5 A and is continuance is 1 5 seconds Figure 1 1 Current fluctuation Typ at 5V when p
49. to request termination of the Ultra DMA burst no sooner than tgp after HDMARDY is negated 2 If the tsp timing is not satisfied the host may receive zero or two more data words from the device Figure 5 14 Host pausing an Ultra DMA data in burst C141 E034 02EN 5 81 5 6 4 5 Device terminating Ultra DMA data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host host tack HOMARDY eur ew host DSTROBE device DD 15 0 tack DAO DA1 DA2 50 CS1 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Device terminating an Ultra DMA data in burst 5 82 C141 E034 02EN 5 6 4 6 Host terminating an Ultra DMA data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device tu 7 DMACK host 5 host REOS tack HDMARDY S host n je SE Vi Eg E device BEER SERRE DD 15 0 XX CRC 2 lt gt tack DAO DA1 DA2 CSO CS1 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated tuu tioRDvz Figure 5 16 Host terminating an Ultra DMA data in burst C141 E034 02EN 5 83 5 6 4 7 Initiating an Ultra DMA data out burst
50. to the timechart the disk drive terminates self calibration and starts executing the command precedingly In other words if a disk read or write service is necessary the disk drive positions the head to the track requested by the host reads or writes data and restarts calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 100 ms C141 E034 02EN 4 9 4 6 4 6 1 4 6 2 1 2 Read write Circuit The read write circuit consists of the read write preamplifier PreAMP the write circuit the read circuit and the time base generator in the read channel RDC Figure 4 4 is a block diagram of the read write circuit Read write preamplifier PreAMP One PreAMP is mounted on the FPC The PreAMP consists of an 6 channel read preamplifier and a write current switch and senses a write error Each channel is connected to each data head The head IC switches the heads by the chip select signals CS and the head select signals HSO HS1 HS2 The IC generates a write error sense signal WUS when a write error occurs due to head short circuit or head disconnection Write circuit The write data is output from the hard disk controller HDC with the NRZ data format and sent to the encoder circuit in the RDC with synchronizing with the write clock The NRZ write data is converted from 8 bit da
51. 0 MPA3026AT 5 086 MPA3035AT 6 780 MPA3043AT 9 042 MPA3052AT 10 850 b Special mode 2 4 6 2 4 6 2 4 6 O OJO O QIO O OIO 1 3 5 1 3 5 1 3 5 Master Device Slave Device Cable Select No of cylinders MPA3017AT 3 390 MPA3026AT 4 092 MPA3035AT 4 092 MPA3043AT 4 092 MPA3052AT 4 092 3 12 C141 E034 02EN 4 THEORY DEVICE OPERATION 4 4 Outline 4 2 Subassemblies 4 3 Circuit Configuration 44 Power on sequence 4 5 Self calibration 4 6 Read Write circuit 47 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks 4 1 42 4 2 1 Outline This chapter consists of two parts First part Section 4 2 explains mechanical assemblies of the disk drive Second part Sections 4 3 through 4 7 explains a servo information recorded in the disk drive and drive control method Subassemblies The disk drive consists of a disk enclosure DE and printed circuit assembly PCA The DE contains all movable parts in the disk drive including the disk spindle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 5 The PCA contains the control circuits for the disk drive The disk drive has one PCA For details
52. 40 characters Left justified remainder filled with blank code X 20 One of three model numbers MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT 5 Word 49 Capabilities Bit 15 14 Reserved Bit 13 Standby timer value 0 vendor specific Bit 12 Reserved Bit 11 IORDY support 1 Supported Bit 10 IORDY inhibition O Disable inhibition Bit 9 LBA support 1 Supported Bit 8 DMA support 1 Supported Bit 7 0 Vendor specific 6 Word 51 PIO data transfer mode Bit 15 8 PIO data transfer mode X 02 PIO mode 2 Bit 7 0 Vendor specific 7 Word 53 Enable disable setting of word 54 58 and 64 70 Bit 15 3 Reserved Bit2 Enable disable setting of word 88 1 Enable Bit 1 Enable disable setting of word 64 70 1 Enable 0 Enable disable setting of word 54 58 1 Enable C141 E034 02EN 5 31 Table 5 4 Information to be read by IDENTIFY DEVICE command 3 of 3 8 0 10 11 12 13 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bit 15 9 Reserved Bit 8 Multiple sector transfer 1 Enable Bit 7 0 Transfer sector count currently set by READ WRITE MULTIPLE without interrupt supports 2 4 8 16 and 32 sectors Word 63 Multiword DMA transfer mode Bit 15 8 Currently used multiword DMA transfer mode Bit 7 0 Supportable multiword DMA transfer mode Bit 2 1 Mode 2 Bit 1 1 Mode 1 Bit 0 1 Mode 0 Word 64 Advance PIO transfer mode support status Bit 15 8 Reserved Bit 7 0 Advan
53. 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device tui DMACK host DDMARDY device HSTROBE host DD 15 0 host DAO DA1 DA2 80 CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 17 Initiating an Ultra DMA data out burst 5 84 C141 E034 02EN 5 6 4 8 Sustained Ultra DMA data out burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes HSTROBE at host DD 15 0 at host HSTROBE at device DD 15 0 at device Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 18 Sustained Ultra DMA data out burst 141 034 02 5 85 5 6 4 9 Device pausing an Ultra DMA data out burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes tre DMARQ device _ DMACK host STOP host tsr DDMARDY device tres HSTROBE host DD 15 0 host XXXIX Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than trp after DDMARDY is negated 2 If the tsp timing is
54. C This command operates similarly to the WRITE SECTOR S command except that the device verifies each sector immediately after being written The verify operation is a read and check for data errors without data transfer Any error that is detected during the verify operation is posted C141 E034 02EN 5 25 9 At command issuance I O registers setting contents 1F64 DH IE SER ERE E Start head No LBA MSB 1F5g CH Start cylinder No MSB LBA 1 Start cylinder No LSB LBA 1F3y SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR XX R 0 gt with Retry R without Retry At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1F5g CH End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1F1y ER Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register RECALIBRATE X 1x x X 0 to X F This command performs the calibration Upon receipt of this command the device sets BSY bit of the Status register and performs a calibration When the device completes the calibration the device updates the Status register clears the BSY bit and generates an interrupt This command can be issued in the LBA mode At command issuance I O registers setting contents 1F74 CM iron
55. C141 E034 02EN 5 69 b 10 11 12 The device shall release DDMARDY within tjogpyz after the host has negated DMACK The host shall neither negate STOP nor negate HSTROBE until at least tack after negating DMACK The host shall not assert DIOW 50 51 DA2 DAI or DAO until at least tacx after negating DMACK Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 11 and 5 6 4 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 10 11 12 The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred The device shall initiate Ultra DMA burst termination by negating DDMARDY The host shall stop generating an HSTROBE edges within of the device negating DDMARDY If the device negates DDMARDY within tsr after the host has generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than tsp after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and timing for the host The device shall negate DMARQ no sooner than tgp after negating DDMARDY The device shall not ass
56. CC correction performance is increased during read error retry a read error is recovered Before automatic alternate assignment the device performs rewriting the corrected data to the erred sector and rereading If no error occurs at rereading the automatic alternate assignment is not performed 2 When a write error occurs and the error does not recovered Read Ahead Cache After read command which involves read data from the disk medium is completed the read ahead cache function reads the subsequent data blocks automatically and stores the data to the data buffer When the next command requests to read the read ahead data the data can be transferred from the data buffer without accessing the disk medium The host can thus access data at higher speed Data buffer configuration The drive has a 128 KB data buffer The buffer is used by divided into three parts for read commands for write commands and for MPU work see Figure 6 9 128 KB 131 072 bytes for read commands for write commands for MPU work 65 536 bytes 128 sectors 48 640 bytes 95 sectors 16 896 bytes M Figure 6 9 Data buffer configuration The read ahead operation is performed at execution of the READ SECTOR S READ MULTIPLE or READ DMA command and read ahead data is stored in the buffer for read commands C141 E034 02EN 6 13 6 5 2 1 2 Caching operation Caching operation is performed only at issuance of the follo
57. ED COMMAND error If an error occurs reading sector is stopped at the sector where the error occurred Command block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred and remaining number of sectors that had not transferred after the sector where the error occurred An interrupt is generated when the DRQ bit is set at the beginning of each block or a partial block C141 E034 02EN Figure 5 2 shows example of the execution of the READ MULTIPLE command e Block count specified by SET MULTIPLE MODE command 4 number of sectors in a block READ MULTIPLE command specifies Number of requested sectors 9 Sector Count register 9 2 Number of sectors in incomplete block remainder of 9 4 1 v Command Issue Parameter Write Status read V Status read V Status read BSY E DRDY INTRQ PRO Sector 112134 728 9 transferred TR Partial gt 55 Block Block block Figure 5 2 Execution example of READ MULTIPLE command At command issuance I O registers setting contents 1F74 CM 1 1 0 0 0 1 0 0 1F64 DH Start head No LBA MSB 1F5g CH Start cylinder No MSB LBA 1 Start cylinder No LSB LBA 1F3y SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR At command
58. EVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART except for SMART Read Attribute values and SMART Read Attribute Thresholds Figure 5 6 shows the protocol for the command execution without data transfer Command Parameter write V Status read 5 f Th DRDY INTRQ Figure 5 6 Protocol for the command execution without data transfer C141 E034 02EN 5 59 5 4 4 5 4 5 Other commands READ MULTIPLE e SLEEP e WRITE MULTIPLE See the description of each command DMA data transfer commands e READ DMA e WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR S or WRITE SECTOR S command except the point that the host initializes the DMA channel preceding the command issuance The interrupt processing for the DMA transfer differs the following point e The interrupt processing for the DMA transfer differs the following point a b 4 5 The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register The host initializes the DMA channel The host writes a command code in the Command register The device sets the BSY bit of the Status register The device asserts the DMARQ signal after completing the preparation of data transfer The device asserts either the BSY bit during DMA data tra
59. Figure 5 10 show the single word DMA data transfer timing between the device and the host system t0 4 DMARQ Sa DMACK _ tI tJ DIOR DIOW 2 e tD p Write data N DD0 DD15 tG EC H DDO DD15 Read data N e Dei ane ron NACK aroo e pawone OOOO G meme wewnoy memuewnov 1 wwccewwennonmow a mwecnsewennonos Figure 5 10 Single word DMA data transfer timing C141 E034 02EN 5 75 5 6 3 Multiword data transfer Figure 5 11 shows the multiword DMA data transfer timing between the device and the host system tO x DMARQ D NECS DMACK 5 A Gu lt d tK DIOR DIOW iD 2 lt Write data N DD0 DD15 tG SA tH DDO DD15 Read data 2 3 N DN E y Deme Lc bene on DMAE enon o _ a memuewnow Lu prace roaren Figure 5 11 Multiword DMA data transfer timing mode 2 5 76 C141 E034 02EN 5 64 Ultra DMA data transfer Figures 5 12 through 5 21 define the timings associated with all phases of Ultra DMA bursts Table 5 12 contains the values for
60. MA data in or data out bursts Each Ultra DMA burst has three mandatory phases of operation the initiation phase the data transfer phase and the Ultra DMA burst termination phase In addition an Ultra DMA burst may be paused during the data transfer phase see 5 5 3 and 5 5 4 for the detailed protocol descriptions for each of these phases 5 6 4 defines the specific timing requirements In the following rules DMARDY is used in cases that could apply to either DDMARDY or HDMARDY and STROBE is used in cases that could apply to either DSTROBE or HSTROBE The following are general Ultra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst Ultra DMA data in commands Initiating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 1 and 5 6 4 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE 3 Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP 4 The host shall negate HDMARDY
61. OE ce ene He ERR ERE TOR ERE PORRO 4 3 42 e alee Sank aa eS ste Nd sg EUN UE dO 4 3 4 3 Circuit Configuration eite eda dettes iru bre ete eget ies ier ite cite irren 4 4 4 4 Poweron Sequence rere t t dede ede e ide ied ede e en eerte 4 6 4 5 Self calibration 5 tete Petre ERO E EE HE p i ee p be PURI ee ient 4 8 4 5 1 Self calibration contents iea nennen 4 8 4 5 2 Execution timing of self calibration ele cece nennen 4 9 4 5 3 Command processing during 4 9 4 6 Read Write pe soe De DROP PE eden ested 4 10 4 61 Read write preamplifier 2 4 10 4 6 2 Write DEEP 4 10 4 63 Read mc inae eee pee nee eb es 4 12 464 Time base generator circuit iet ette de De E Rp tps 4 14 4 7 Servo Control sais ste deti pen b pese bob d 4 15 4 Servo control CITCUIE sere RUE DESEE EIE 4 16 44 2 Datassurtace servo format ee aoi UR m Eo e UE een 4 19 4 L3 frame PESEE pe Dane Ore 4 19 4 7 4 Actuator motor control enne tenter nest tenere 4 20 4 75 5 Spindle motor control eee eae teet reete tee ere 4 21 CHAPTER 5 INTERFACE ois sess sc hele ae neh die a eee ry
62. RDY and no sooner than tpys after the host places the result of its CRC calculation on DD 15 0 C141 E034 02EN 5 65 b 10 The device shall latch the host s data from DD 15 0 on the negating edge of DMACK 11 The device shall compare the CRC data received from the host with the results of its own 12 13 14 CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DSTROBE within tiorpyz after the host negates DMACK The host shall not negate STOP no assert HDMARDY until at least tacx after negating DMACK The host shall not assert DIOR CSO CS1 DA2 DAI or DAO until at least after negating DMACK Host terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 6 and 5 6 4 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 The host shall not initiate Ultra DMA burst termination until at least one data word of Ultra DMA burst has been transferred The host shall initiate Ultra DMA burst termination by negating HDMARDY The host shall continue to negate HDMARDY until the Ultra DMA burst is terminated The device shall stop generating DSTROBE edges within tgrs of the host negating HDMARDY
63. Read 19 ms typical Write 20 ms typical Start Stop time Start 0 rpm to Drive Read Typical 10 sec Maximum 16 sec Stop at Power Down Typical 20 sec Maximum 26 sec Interface ATA 3 Maximum Cable length 0 46 m Data Transfer Rate To From Media 8 019 to 14 964 MB s To From Host 16 7 MB s Max burst PIO mode 4 burst DMA mode 2 33 3 MB s Max burst ultra DMA mode 2 Data buffer 128 MB Physical Dimensions 25 4 mm x 101 6 mm x 146 0 mm Height x Width x Depth 1 0 x 4 0 x 5 75 Weight 600 g 1 Capacity under the LBA mode Under the CHS mode normal BIOS specification formatted capacity number of cylinders number of heads and number of sectors are as follows Model Formatted Capacity No of Cylinder No of Heads MPA3017AT 1749 56 3 390 MPA3026AT 2624 86 5 086 MPA3043AT 4374 88 9 042 MPA3052AT 5249 66 10 850 1 4 C141 E034 02EN 1 2 2 Model and product number Table 1 2 lists the model names and product numbers Table 1 2 Model names and product numbers user area MPAXSIAT No 6 32unc UDMAGS version MPA3O26AT UDMA3S version UDMASS version UDMASS version 1 3 1 2 052 5249 72 No 6 32UNC CA01602 B461 UDMA33 version Power Requirements Input Voltage e 5V 45 e 12V 45 Ripple oom TU 200 mV peak to peak 100 mV peak to peak DC to 1 MHz DC
64. TOR S 30 or X31 This command writes data of sectors from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified to 256 sectors in maximum Data transfer begins at the sector specified in the Sector Number register For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 4 4 2 If the head is not on the track specified by the host the device performs a implied seek After the head reaches to the specified track the device writes the target sector When the command is specified with retry or without retry the device attempts to retry up to 16 times The data stored in the buffer and CRC code and ECC bytes are written to the data field of the corresponding sector s Upon the completion of the command execution the command block registers contain the cylinder head and sector addresses of the last sector written If an error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Command block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred At command issuance I O register
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66. Ultra DMA burst termination the device shall negate DDMARDY and wait tgp before negating DMARQ 3 host shall resume an Ultra DMA burst by generating an HSTROBE edge b Device pausing an Ultra DMA data out burst 1 The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred C141 E034 02EN 2 3 a 5 The device shall pause an Ultra burst by negating DDMARDY The host shall stop generating HSTROBE edges within of the device negating DDMARDY If the device negates DDMARDY within tsr after the host has generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and timing for the host The device shall resume an Ultra DMA burst by asserting DDMARDY 5 5 4 4 Terminating an Ultra DMA data out burst a Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 10 and 5 6 4 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges
67. ad When the disk drive receives the read command that targets the sequential address to the previous read command the disk drive starts the read ahead operation a Sequential command just after non sequential command When the previously executed read command is an non sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command the disk drive assumes the received command is a sequential command and performs the read ahead operation after reading the requested data 1 Atreceiving the sequential read command the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data HAP Mis hit data Empty data DAP 2 The disk drive transfers the requested data that is already read to the host system with reading the requested data HAP V Mis hit data n Empty data DAP 3 After completion of the reading and transferring the requested data to the host system the disk drive performs the read ahead operation continuously HAP gt 4 Read Mis hit data K ahead Empty data data DAP C141 E034 02EN 6 17 4 disk drive performs the read ahead operation for all area of segment with overwriting the requested data Finally the cache data in the buffer is as follows HAP Read ah ad data 4
68. address inei en ee HR et e reet 6 7 6 3 Power Savers xo Re HERI ed obe 6 8 C141 E034 02EN 6 3 1 6 3 2 6 4 6 4 1 6 4 2 6 5 6 5 1 6 5 2 6 5 3 6 6 Powersavemode eee aeui ute dn ae ee Ee ee pe rote teen 6 8 Power commands 22i cie Me eA cue eec de te eee 6 10 Defect Management te Pe e RIETI PD 6 10 Sp re area INIRE Une ERO ane e eei edo ene 6 11 Alternating defective sectors nennen nennen enne 6 11 Read A lead Cache pet eei e edet eee ei tg tee 6 13 Data buffer configuration e Precor terre erri idera 6 13 Caching operation utei tb eee Tone Ee iode 6 14 Usage of read segment eto eret pere pe Ub aer eoe Ee Heo ey 6 15 6 22 C141 E034 02EN 1 1 2 1 2 2 2 3 2 4 3 1 32 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 1 5 2 5 3 FIGURES page Current fluctuation Typ at 5V when power is turned 1 7 2 1 Configuration of disk media heads 2 3 drive system CON SUPATION se edere teen dere eo elite eee ere 2 4 2 drives configuration enar ree pee ar ES EEk e re 2 5 en et Re bee 3 2
69. ansfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the WRITE SECTOR S command A host system can be select the following transfer mode using the SET FEATURES command C141 E034 02EN 8 1 Single word DMA transfer mode 2 Sets the FR register 03 and SC register X 12 by the SET FEATURES command 2 Multiword DMA transfer mode 2 Sets the FR register 03 and SC register X 22 by the SET FEATURES command 3 Ultra DMA transfer mode 2 Sets the FR register 03 and SC register 42 by the SET FEATURES command At command issuance I O registers setting contents 1F64 DH Start head No LBA MSB 1F5g CH Start cylinder No MSB LBA 1 Start cylinder No LSB LBA 1F3y SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR XX R 0 gt with Retry R without Retry At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1F5g CH End cylinder No MSB LBA 1 End cylinder No LSB LBA 1F3y SN End sector No LBA LSB 1F2 4 SC 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register WRITE VERIFY X 3
70. aranteed C141 E034 02EN 5 13 5 3 1 code and parameters Table 5 3 lists the supported commands command code and the registers that needed parameters are written Table5 3 Command code and parameters 1 of 2 Command code Bit Parameters used Command name TS TS TT pP pe esee ferr ReaDsecToRS olo rojo jojo n N v v vv READMULTILE 1i rjo ojorjo o fw v v v v READDMA rirjo ojriojo R N v v v v hows wemEMULTPLE weoma tft fool i wee vereY fo fo fi ti i pwarresecrons foo h e e e h e ecas foo E e e ae SEEK __ ehh ffln i o o o e v memwwws f h i e i h e e h aae pemeve pp pep heee sermucmmemore eeepc fofofo fo feter eif READ LONG WRITE LONG READ BUFFER ne EGE N N NISI WRITE BUFFER WRITE BUFFER sd eR IDLE IDLE IMMEDIATE STANDBY 5 14 C141 E034 02EN Table5 3 Command code and parameters 2 of 2 Command code Bit Parameters used Command name 2 615 1 3 2 1 o SMART fo EEE Notes FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sector Number Register R Retry at error 1 Without retry 0 with retry Y Necessary to set parameters Y Necessary to
71. ast sector read If an error occurs in a sector the read operation is terminated at the sector where the error occurred Command block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical block address in the LBA mode where the error occurred and remaining number of sectors of which data was not transferred At command issuance I O registers setting contents 1F74 CM 0 0 1 0 0 0 0 R 1F6 DH Start head No LBA MSB 1F5g CH Start cylinder No MSB LBA 1 Start cylinder No LSB LBA 1F34 SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR R 0 gt with Retry R without Retry C141 E034 02EN 5 17 2 At command completion I O registers contents to be read 1F64 DH End head No LBA MSB 1F5g CH End cylinder No MSB LBA 1 End cylinder No LSB LBA 1F3y SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register READ MULTIPLE X C4 This command operates similarly to the READ SECTOR S command The device does not generate an interrupt assertion of the INTRQ signal on each every sector An interrupt is generated after the transfer of a block of sectors for which the number is specified by the SET MULTIPLE MODE command The i
72. at has no maximum time value ty is a limited time out that has a defined minimum 115 a limited time out that has a defined maximum 2 All timing parameters are measured at the connector of the device to which the parameter applies For example the sender shall stop generating STROBE edges tgrs after the negation of DMARDY Both STROBE and DMARDY timing measurements are taken at the connector of the sender 3 All timing measurement switching points low to high and high to low are to be taken at 1 5 V 141 034 02 5 79 5 6 4 3 Sustained Ultra DMA data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host Note DD 15 0 and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 13 Sustained Ultra DMA data in burst 5 80 C141 E034 02EN 5 6 4 4 Host pausing an Ultra DMA data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host 1 1 1 111 ac ES host HDMARDY host DSTROBE device doves XXX Notes 1 The host may assert STOP
73. available as power commands e IDLE e IDLE IMMEDIATE e STANDBY e STANDBY IMMEDIATE e SLEEP e CHECK POWER MODE Defect Management Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatting at the factory shipment All the user space area are formatted at shipment from the factory based on the default parameters listed in Table 6 1 C141 E034 02EN 6 41 Spare area Following two types of spare area are provided for every physical head 1 Spare cylinder for sector slip used for alternating defective sectors at formatting in shipment 11 cylinders head 2 Spare cylinder for alternative assignment used for alternative assignment by automatic alternative assignment 4 cylinders head 6 4 2 Alternating defective sectors The two alternating methods described below are available 1 Sector slip processing A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in the formatting Figure 6 7 shows an example where physical sector 5 is defective on head 0 in cylinder 0 Index 7 Sector physical NP Gur qo NIME ONE NN 248 249 250 Cylinder 0 Defective sector Heo npo up Jo
74. ce PIO transfer mode Bit 1 1 Mode 4 Bit 0 1 Mode 3 Word 80 Major version number Bit 15 4 Reserved Bit3 3 Supported 1 Bit2 2 Supported 1 Bit 1 ATA 1 Supported 1 Bit0 Undefined Word 82 Support of command sets Bit 15 4 Reserved Bit3 Power Management feature set supported 1 Bit 2 Removable feature set supported 0 Bit 1 Security feature set supported 0 Bit0 SMART feature set supported 1 Word 88 Ultra DMA modes Bit 15 11 Reserved Bit 10 8 Currently used Ultra DMA transfer modes Bit 7 3 Reserved Bit 2 0 Supportable Ultra DMA transfer mode Bit 2 1 Mode 2 Bit 1 1 Mode 1 Bit 0 1 Mode 0 C141 E034 02EN 13 14 IDENTIFY DEVICE DMA X EE When this command is not used to transfer data to the host in DMA mode this command functions in the same way as the Identify Device command At command issuance I O registers setting contents 1F74 CM 1 1 1 0 1 1 1 0 XX XX XX XX XX 1F5 CH 1F4 CL 1F34 SN 1F24 SC 1F14 FR At command completion 1 registers contents to be read 1F54 CH 1F44 CL 1F34 SN XX 1 2 5 Error information SET FEATURES X EF The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed For the transfer mode Feature register 03 detail setting can be done using the Sector Count register Upon receipt of this comma
75. characteristic sample of the programmable filter Gain D dB 20 r Fb control Boost volume Fc control 1 2 4 5 10 20 30 40 50 100 Fc Log Frequency MHz Figure 4 5 Frequency characteristic of programmable filter Adaptive equalizer circuit This circuit is 3 tap sampled analog transversal filter circuit that cosine equalizes the head read signal to the partial response class 4 PR4 waveform C141 E034 02EN wak NRZDT7 1 gt Et T NRZDT6 1 fo 0 0 0 NRZDIS 1 0 0 1 NRZDT4 1 1 1 0 NRZDI3 1 0 i 0 1 NRZDI2 1 10 0 1 0 NRZDTI l 1 1 1 1 1 NRZDTO 1 f p 1 0 1 NRZDTP 0 Q 1 le le Y Y 2 Y X X Cx NRZDT 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 1 1 o 1 0 ExoeDr p rirjr ojo ririojotr ir rto ojr 1 ojo tr i1 1 0 o ioio i PecdeDT 1 0 1 0 0 0 1 000 0 1 0 1 11 2 0 1 1 1 0 1 0 0 0 1 0 0 WDX WDY Media gt gt lt lt lt 4 gt gt 1 lt lt lt lt lt lt lt lt lt lt lt gt lt gt gt 1 lt lt lt lt lt lt lt gt gt gt 1 lt lt lt lt lt lt lt ee A E Ann LESER
76. d the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system enables fast data access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead Master slave The disk drive can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device C141 E034 02EN 5 6 Error correction and retry by ECC If a recoverable error occurs the disk drive itself attempts error recovery The 18 byte ECC has improved buffer error correction for correctable data errors Write cache When the disk drive receives a write command the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media This feature reduces the access time at writing 141 034 02 1 3 1 2 Device Specifications 1 2 4 Specifications summary Table 1 1 shows the specifications of the disk drive Table 1 1 Specifications MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT Formatted Capacity 1 1750 00 MB 2625 00 MB 3500 00 MB 4375 00 MB 5250 01 MB Number of Cylinders User Alternate amp SA 8 713 84 Positioning time Minimum 3 ms typical Average Read 10 ms typical Write 12 ms typical Maximum
77. data 5 Threshold 1 Threshold of Reserved attribute 1 Threshold 2 to The format of each threshold value is the same as threshold 30 that of bytes 02 to OD Reserved Unique to vendor e fow O e format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds The data format version numbers of the device attribute values and insurance failure thresholds are the same When a data format is changed the data format version numbers are updated C141 E034 02EN 5 51 Attribute ID The attribute ID is defined as follows I Status flag Bit 0 If this bit is 1 the attribute is within the insurance range of the device when the attribute exceeds the threshold If this bit is O the attribute is outside the insurance range of the device when the attribute exceeds the threshold Bits 1 to 15 Reserved bits Current attribute value The current attribute value is the normalized raw attribute data The value varies between Olh and 64h The closer the value gets to Olh the higher the possibility of a failure The device compares the attribute values with thresholds When the attribute values are larger than the thresholds the device is operating normally Attribute value for the worst case so far This is the worst attribute value among the attribute values collected to date This value indicates the state
78. data is limited to the case that the hit check is missed at the data buffer for read command When all data requested by the read command are stored in the data buffer for write command hit all the device transfers data from the data buffer for write command At this time the read ahead operation to the data subsequent to the requested data is not performed Even if a part of data requested by the read command are stored in the data buffer for write command hit partially all data are read from the disk medium without transferring from the data buffer for write command C141 E034 02EN 3 6 5 3 1 Invalidating caching data Caching data in the data buffer is invalidated in the following case 1 Following command is issued to the same data block as caching data e WRITE SECTOR S e WRITE DMA e WRITE MULTIPLE 2 Command other than following commands is issued all caching data are invalidated READ SECTOR S READ DMA READ MULTIPLE WRITE SECTOR S WRITE MULTIPLE WRITE DMA 3 Caching operation is inhibited by the SET FEATURES command 4 Issued command is terminated with an error 5 Soft reset or hard reset occurs or power is turned off 6 The device enters the sleep mode 7 Under the state that the write data is kept in the data buffer for write command as a caching data new write command is issued write data kept until now are invalidated Usage of read segment This subsection explains the usage of
79. der with this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is posted Other than 00 is specified this command terminates normally The parameters set by this command are retained even after reset or power save operation regardless of the setting of disabling the reverting to default setting In LBA mode The device ignores the L bit specification and operates with the CHS mode specification An accessible area of this command within head moving in the LBA mode is always within a default area It is recommended that the host system refers the addressable user sectors total number of sectors in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command At command issuance I O registers setting contents iD PTT Na 1F5g CH 1F44 CL XX 1F3y SN XX 1F2y SC Number of sectors track 1F1y FR XX At command completion I O registers contents to be read Ts x Yor mena 1 5 1F44 CL 1F34 SN XX 1 2 5 Error Information IDENTIFY DEVICE The host system issues the IDENTIFY DEVICE command to read parameter information 512 bytes from the device Upon receipt of this command the drive sets the BSY bit of Status register and sets required parameter information in t
80. disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 5 400 rpm 0 5 The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting After that the rotational speed is kept with detecting a servo information Actuator The actuator consists of a voice coil motor VCM and a head carriage The VCM moves the head carriage along the inner or outer edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating When disk drives are transported under conditions where the air pressure changes a lot filtered air is circulated in the DE The circulation filter cleans out dust and dirt from inside the DE disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating disk 141 034 02 4 3 4 3 1 2 3 4 Circuit Configuration Figure 4 2 shows the disk drive circuit configuration Read write circuit The r
81. e measures and stores the force value of the actuator motor drive current that balances the torque for stopping head stably This includes the current offset in the power amplifier circuit and DAC system The forces are compensated by adding the measured value to the specified current value to the power amplifier This makes the stable servo control To compensate torque varying by the cylinder the disk is divided into 12 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored For sensing the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value B
82. e signal asserted by the host to read device registers or the data port HDMARDY is a flow control signal for Ultra DMA data in bursts This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts The host may negate HDMARDY to pause an Ultra DMA data in burst HSTROBE is the data out strobe signal from the host for an Ultra DMA data out burst Both the rising and falling edge of HSTROBE latch the data from DATA 0 15 into the device The host may stop generating HSTROBE edges to pause an Ultra DMA data out burst Interrupt signal to the host This signal is negated in the following cases assertion of RESET signal Reset by SRST of the Device Control register Write to the command register by the host Read of the status register by the host Completion of sector data transfer without reading the Status register When the device is not selected or interrupt is disabled This signal indicates 16 bit data bus is addressed in PIO data transfer This signal is an open collector output When 516 is not asserted 8 bit data is transferred through DATAO to DATA7 signals When 516 is asserted 16 bit data is transferred through DATAO to DATAI5 signals Chip select signal decoded from the host address bus This signal is used by the host to select the command block registers Chip select signal decoded from the host address bus This signal is u
83. ead write circuit consists of two LSIs read write preamplifier PreAMP and read channel RDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the partial response class 4 PR4 and contains the Viterbi detector programmable filter adaptable transversal filter times base generator and data separator circuits The RDC also contains the 8 9 group coded recording GCR encoder and decoder and servo demodulation circuit Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coil motor Spindle motor driver circuit The circuit measures the interval of a PHASE signal generated by counter electromotive voltage of a motor or servo mark at the MPU and controls the motor speed comparing target speed Controller circuit Major functions are listed below Data buffer 128 KB management ATA interface control and data transfer control Sector format control Defect management ECC control Error recovery and self diagnosis C141 E034 02EN 0 lt 0 1710 8 xoopgLVXXOEVdIN om3
84. eck a DASP signal for up to 450 ms to confirm presence of a slave device device 1 The master device recognizes presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own power on reset state the slave device shall report its presence and the result of power on diagnostics to the master device as described below DASP signal Asserted within 400 ms PDIAG signal Negated within 1 ms and asserted within 30 seconds V Power on Master device Power On Reset Status Reg i r BSY bit 31 ES gt 4 Checks DASP for upto If presence of a slave device is 450 ms confirmed PDIAG is checked for up to 31 seconds Slave device Power On Reset BSY bit P Max 1 ms PDIAG E Max 30 sec DASP x Max 400 ms Figure 6 1 Response to power on 6 2 C141 E034 02EN 6 1 2 Response to hardware reset Response to RESET hardware reset through the interface is similar to the power on reset Upon receipt of hardware reset the master device checks a DASP sig
85. een the HA and the disk drive should be as short as possible C141 E034 02EN 3 3 1 INSTALLATION CONDITIONS 3 1 3 2 3 3 3 4 Dimensions Mounting Cable Connections Jumper Settings Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm C141 E034 02EN Figure 3 1 Dimensions C141 E034 02EN r N l o T 6 6 32UNC Both Sidas 3 2 1 2 3 Mounting Orientation Figure 3 2 illustrates the allowable orientations for the disk drive The mounting angle can vary x5 from the horizontal gravity a Horizontal mounting b Vertical mounting 1 c Vertical mounting 2 Figure 3 2 Orientation Frame The disk enclosure DE body is connected to signal ground SG and the mounting frame is also connected to signal ground These are electrically shorted Note Use No 6 32UNC screw for the mounting screw and the screw length should satisfy the specification in Figure 3 4 Limitation of side mounting When the disk drive is mounted using the screw holes on both side of the disk drive use two screw holes shown in Figure 3 3 Do not use the center hole For screw length see Figure 3 4 C141 E034 02EN 3 3 Use these screw holes Do not use this screw holes Figure 3 3 Limitation of side mounting 2 5 Side surface 2 5 Bottom s
86. er or a slave device When CSEL signal is grounded the IDD is a master device When CSEL signal is open the IDD is a slave device This signal is pulled up with 240 resistor DMACK I The host system asserts this signal as a response that the host system receive data or to indicate that data is valid DMARQ This signal is used for transfer between the host system and the device The device asserts this signal when the device completes the preparation of DMA data transfer to the host system at reading or from the host system at writing The direction of data transfer is controlled by the IOR and IOW signals In other word the device negates the DMARQ signal after the host system asserts the DMACK signal When there is another data to be transferred the device asserts the DMARQ signal again When the DMA data transfer is performed IOCWI16 50 and CS1 signals not asserted The DMA data transfer is 16 bit data transfer GND Grounded Note I indicates input signal from the host to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device C141 E034 02EN 5 5 5 2 52 1 Logical Interface The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device suppor
87. ert DMARQ again until after the Ultra DMA burst is terminated The host shall assert STOP with tj after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated If HSTROBE is negated the host shall assert HSTROBE with tj after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition of HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than tyr after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than tpvs after placing the result of its CRC calculation on DD 15 0 The device shall latch the host s data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DDMARDY within tjogpyz after the host has negated DMACK C141 E034 02EN 5 5 5 13 The host shall neither negate STOP nor HSTROBE until at least after negating DMACK 14 The host shall not assert DIOW CSO CS1 DA2 DAI or DAO until a
88. es an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified If an error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder the head and the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred The Sector Count register indicates the number of sectors that have not been verified If a correctable error is found the device sets the CORR bit of the Status register to 1 after the command is completed before the device generates an interrupt At command issuance I O registers setting contents 1F74 CM 0 1 0 0 0 0 0 R 1F64 DH Start head No LBA MSB 1F54 CH Start cylinder No MSB LBA 1F44 CL Start cylinder No LSB LBA 1F34 SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR R 0 gt with Retry R 1 without Retry C141 E034 02EN 5 21 5 At command completion I O registers contents to be read 1F64 DH End head No LBA MSB 1F54 CH End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register WRITE SEC
89. ess start cylinder address At the end of a command the contents of this register are updated to the current cylinder number The high order 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 Device Head register X 1 F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 Bit 7 Unused Bit 6 L 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 4 DEV bit 0 for the master device and 1 for the slave device Bit 3 HS3 CHS mode head address 3 25 LBA bit 27 Bit 2 HS2 CHS mode head address 3 22 LBA bit 26 Bit 1 HS1 CHS mode head address 3 25 LBA bit 25 Bit 0 50 CHS mode head address 3 27 LBA bit 24 C141 E034 02EN 9 Status register X 1F7 The contents of this register indicate the status of the device The contents of this register are updated at the completion of each command When the BSY bit is cleared other bits in this register should be validated within 400 ns When the BSY bit is 1 other bits of this register are invalid When the host system reads this register while an interrupt is pending it is considered to be the Interrupt Acknowledge the host system acknowledges the interrupt Any pending interrupt is cleared negating INTRQ signal whenever this regis
90. evice does not negate DMARQ in order to initiate ULTRA DMA burst termination the host shall negate HDMARDY and wait tgp before asserting STOP 3 device shall resume an Ultra DMA burst by generating a DSTROBE edge b Host pausing an Ultra DMA data in burst 1 host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 host shall pause an Ultra DMA burst by negating HDMARDY C141 E034 02EN 3 4 5 The device shall stop generating DSTROBE edges within tgrs of the host negating HDMARDY If the host negates HDMARDY within tsr after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARDY greater than tsr after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and tgrs timing for the device The host shall resume an Ultra DMA burst by asserting HDMARDY 5 5 3 4 Terminating an Ultra DMA data in burst a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 5 and 5 6 4 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 The device shall initiate termination of an Ultra DMA burst by n
91. external magnetic fields 3 6 C141 E034 02EN 3 3 Cable Connections 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals e Power supply connector CN1 e interface connector CN1 Power supply connector CN1 Mode Setting Pins ATA interface connector Figure 3 7 Connector locations C141 E034 02EN 3 7 3 3 2 connector specifications Table 3 2 lists the recommended specifications for the cable connectors Table3 2 Cable connector specifications Name Model Manufacturer Cable socket closed end type ATA interface cable E 40 pin CN1 uH FCN 707B040 AU O Fujitsu through end type FCN 707B040 AU B Fujitsu Signal cable 445 248 40 SPECTERS STRIP Cable socket housing 1 480424 0 AMP Power supply cable Contact 60617 4 AMP CN1 Signal cable AWG 18 to 24 77 24 Note The cable of twisted pairs and neighboring line separated individually is not allowed to use for the host interface cable It is because that the location of signal lines in these cables is not fixed and so the problem on the crosstalk among signal lines may occur 3 3 3 Device connection Figure 3 8 shows how to connect the devices ATA interface cable Power supply cable Disk Drive 0 DC Host system po
92. fault parameters MPA MPA MPA MPA MPA 3052AT 3043AT 3035AT 3026AT 3017AT Number Number of cylinders Number of cylinders 10850 850 9 042 6 780 5 5086 590 390 Number of head 15 Number of sectors track 63 Formatted capacity MB 5 249 6 4 374 8 3 499 1 2 624 8 1 748 5 As long as the formatted capacity of the IDD does not exceed the value shown on Table 6 1 the host can freely specify the number of cylinders heads and sectors per track Generally the device recognizes the number of heads and sectors per track with the INITIALIZE DEVICE PARAMETER command However it cannot recognizes the number of cylinders In other words there is no way for the device to recognize a host access area on logical cylinders Thus the host should manage cylinder access to the device The host can specify a logical address freely within an area where an address can be specified within the specified number of cylinders heads and sectors per track in the current translation mode The host can read an addressable parameter information from the device by the IDENTIFY DEVICE command Words 54 to 56 C141 E034 02EN 6 2 2 Logical address 1 CHS mode Logical address assignment starts from physical cylinder PC 0 physical head PH 0 and physical sector PS 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS command The head address is advanced at
93. g an Ultra DMA burst These lines assume these definitions when 1 an Ultra DMA Mode is selected and 2 a host issues a READ DMA or WRITE DMA command requiring data transfer and 3 the host asserts DMACK These signal lines revert back to the definitions used for non Ultra DMA transfers upon the negation of DMACK by the host at the termination of an Ultra DMA burst All of the control signals are unidirectional DMARQ and DMACK retain their standard definitions With the Ultra DMA protocol the control signal STROBE that latches data from DD 15 0 is generated by the same agent either host or device that drives the data onto the bus Ownership of DD 15 0 and this data strobe signal are given either to the device during an Ultra DMA data in burst or to the host for an Ultra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data The highest fundamental frequency on the cable shall be 16 67 million transitions per second or 8 33 MHz the same as the maximum frequency for Mode 4 and DMA Mode 2 Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is capable of suppo
94. g this command Upon receipt of this command the device sets the BSY bit of Status register and sets up the sector buffer for a read operation Then the device sets the DRQ bit of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data from the buffer At command issuance I O registers setting contents 1F5 CH 1F4 CL 1F34 SN 1F24 SC 1 C141 E034 02EN 21 At command completion 1 registers contents to be read oe 07 _ 1 5 1F44 CL XX 1F3y SN XX 1F2y SC XX 1 15 Error information WRITE BUFFER X E8 The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command Upon receipt of this command the device sets the BSY bit of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the sector buffer then generates an interrupt At command issuance I O registers setting contents 1 7 ET 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F14 FR At command completion I O registers contents to be read mam T x oe 1 5 1F44 CL XX 1F3y SN XX 1F2y SC XX 1 15 Error information C141 E034 02EN 5 41 22
95. he drive generates the interrupt of command complete Also the drive sets the normal end status in the Status register The drive continues writing data on the disk medium When all data requested by the host are written on the disk medium actual write operation is completed The drive receives the next command continuously If the received command is a sequential write data to be written by a command is logically sequent to data of previous command the drive starts data transfer and receives data of sectors requested by the host system At this time if the write operation of the previous command is still been executed the drive continuously executes the write operation of the next command from the sector next to the last sector of the previous write operation Thus the latency time for detecting a target sector of the next command is eliminated This shortens the access time The drive generates an interrupt of command complete after completion of data transfer requested by the host system as same as at previous command When the write operation of the previous command had been completed the latency time occurs to search the target sector If the received command is not a sequential write the drive receives data of sectors requested by the host system as same as sequential write The drive generates the interrupt of command complete after completion of data transfer requested by the host system Received data is processed after completion
96. he host system can select the DMA transfer mode by using the SET FEATURES command 1 Single word DMA transfer mode 2 Sets the FR register 03 and SC register X 12 by the SET FEATURES command 2 Multiword DMA transfer mode 2 Sets the FR register 03 and SC register X 22 by the SET FEATURES command 3 Ultra DMA transfer mode 2 Sets the FR register 03 and SC register X 42 by the SET FEATURES command At command issuance I O registers setting contents 1F74 CM 1 1 0 0 1 0 0 R 1F64 DH Start head No LBA MSB 1F54 CH Start cylinder No MSB LBA 1 Start cylinder No LSB LBA 1F3y SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR 0 gt with Retry R 1 gt without Retry C141 E034 02EN 4 At command completion I O registers contents to be read 1F64 DH End head No LBA MSB 1F54 CH End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register READ VERIFY SECTOR S X 40 or This command operates similarly to the READ SECTOR S command except that the data is not transferred to the host system After all requested sectors are verified the device clears the BSY bit of the Status register and generat
97. he sector buffer The device then sets the DRQ bit of the Status register and generates an interrupt After that the host system reads the information out of the sector buffer Table 5 5 shows the arrangements and values of the parameter words and the meaning in the buffer C141 E034 02EN At command issuance I O registers setting contents 1 73 irm 1F5 CH 1F4 CL 1F3 SN 1F24 SC 1 At command completion I O registers contents to be read mem eT x oe 1F5 CH 1F44 CL 1 3 5 1 2 5 1F1y ER Error information C141 E034 02EN Table 5 4 Information to be read by IDENTIFY DEVICE command 1 of 3 X 0C5A General Configuration 1 1 X 0D3E Number of cylinders MPA3017AT X 0D3E X 13DE MPA3026AT X 13DE X 1A7C MPA3035AT X 1A7C X 2352 MPA3043AT X 2352 X 2A62 MPA3052AT X 2A62 0000 3 0010 or Number of Heads MPA3017AT X 0010 X 000F MPA3026AT X 0010 MPA3035AT X 0010 MPA3043AT X 000F MPA3052AT X 000F 6 Numbrofsctrspertack o 1019 Seralmumber ASClicod 2 2526 Fimwaemviio ASClcod 3 o 2746 Modemumber ASCicod 4 0 X 0003 or Enable disable setting of words 54 58 64 70 and 88 7 0007 Variable 60 61 X 00342778 Total number of user addressable sectors LBA mode only MPA3017AT X 00342778 X 004E3B34 MPA3026AT X 004E3B34
98. he spindle motor reaches the steady speed Bit 5 The Device Write Fault DF bit This bit indicates that a device fault write fault condition has been detected If a write fault is detected during command execution this bit is latched and retained until the device accepts the next command or reset Bit 4 Device Seek Complete DSC bit This bit indicates that the device heads are positioned over a track In the IDD this bit is always set to 1 after the spin up control is completed C141 E034 02EN 5 11 10 Bit 3 Data Request DRQ bit This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device Bit 1 Always 0 Bit 0 Error ERR bit This bit indicates that an error was detected while the previous command was being executed The Error register indicates the additional information of the cause for the error Command register X 1F7 The Command register contains a command code being sent to the device After this register is written the command execution starts immediately Table 5 3 lists the executable commands and their command codes This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written C141 E034 02EN 5 2 3 1 2 5 3 Control block registers Alternate Status register X 3F6 The Alternate Status register contains the same informa
99. i e epe m ri e te ttr enn 5 62 3 5 2 Phases Of Operations ee Rp RE HIER e ore eere ee christi 5 63 5 5 3 Ultra DMA data in 5 63 5 5 4 DMA data out 5 2 2 4 24 4 4 000 5 67 3 5 5 Ultra DMA CRC 9 noo Dee CRUDO tun dite ee 5 71 5 5 6 Series termination required for Ultra DMA sss eene 5 72 5 6 Timing cu EEUU eom o NEMUS 5 73 5 6 1 PIO data transfer cosas eot o I eed itu be IEEE RE 5 73 5 6 2 Single word DMA data 1 5 75 5 6 3 Multiword data transfer iste te teet p EE e ee De E pri hen 5 76 564 Ultra DMA data transfer eere tee peret reete geben rere e Rope 5 77 9 65 and reset ete URS E p 5 89 CHAPTER 6 OPERATIONS noe Donde PURPURAE 6 1 6 1 Device Response to the Reset eee eecescesecsecssecseecseecseeeeeeeeeeeeceseesecsaecsaecsaecsaeeaaseneeegs 6 1 61 1 Response to poWer On 3i deci beet reet de lave reb ee aeoe Te eok EEE 6 2 6 1 2 Response to hardware reset sro ede reet tei re E Hiper 6 3 6 1 3 Response to software reset cessere ent te rg retten leot beider Rte 6 4 6 1 4 Response to diagnostic command sess ener 6 5 6 2 Address Translation eiim e pede teet ue en bg ger sy 6 6 6 271 Default parameters goo ren DI Ree dgediicep e itti pent 6 6 6 2 2 Logical
100. igh performance AT controller 22 System Configuration 2 2 1 interface Figures 2 3 and 2 4 show the ATA interface system configuration The drive has a 40 pin PC AT interface connector and supports the PIO transfer till 16 7 MB s ATA 3 Mode 4 the DMA transfer till 16 7 MB s ATA 3 Multiword mode 2 and the ultra DMA transfer till ATA 4 Mode 4 2 2 2 1 drive connection HA Host i i Host adaptor DONE bus ATA interface Host interface Figure 2 3 1 drive system configuration 2 4 C141 E034 02EN 2 2 3 2 drives connection Host HA Host adaptor _ Disk drive 0 AT bus Host interface Disk drive 1 ATA interface Note When the drive that is not conformed to ATA is connected to the disk drive is above configuration the operation is not guaranteed Figure 24 2 drives configuration IMPORTANT HA host adapter consists of address decoder driver and receiver ATA is an abbreviation of AT attachment The disk drive is conformed to the ATA 3 interface At high speed data transfer PIO mode 3 mode 4 DMA mode 2 or ultra DMA mode occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 3 and ATA 4 standard and the cable length betw
101. iled the write cache function is disabled automatically The releasing the disable state can be done by the SET FEATURES command When the power of the drive is turned on after the power is turned off once the status of the write cache function returns to the default state The default state is write cache enable and can be disable by the SET FEATURES command The write cache function is operated with the following command e WRITE SECTOR S e WRITE MULTIPLE e WRITE DMA IMPORTANT When the write cache function is enabled the transferred data from the host by the WRITE SECTOR S is not completely written on the disk medium at the time that the interrupt of command complete is generated When the unrecoverable error occurs during the write operation the command execution is stopped Then when the drive receives the next command it generates an interrupt of abnormal end However an interrupt of abnormal end is not generated when a write automatic assignment succeeds However since the host may issue several write commands before the drive generates an interrupt of abnormal end the host cannot recognize that the occurred error is for which command generally Therefore it is very hard to retry the unrecoverable write error for the host in the write cache operation generally So take care to use the write cache function C141 E034 02EN 6 23 Comments concerning this manual be directed to one of the following addresses FUJI
102. ing to the servo data that is written on the data side beforehand C141 E034 02EN 4 15 4 7 1 Servo control circuit Figure 4 7 is the block diagram of the servo control circuit The following describes the functions of the blocks 1 MPU SVC 2 3 4 5 a 9 m 0 current l DSP P Head burst ADC vit DAC ADD capture 0 Vv CSR Position Sense 1 v VCM 6 7 EA ror L gt Driver gt E CSR Current Sense Resistor control MINE VCM Voice Coil Motor Figure 4 7 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU includes DSP unit etc and the MPU starts the spindle motor moves the heads to the reference cylinders seeks the specified cylinder and executes calibration according to the internal operations of the MPU The major internal operations are listed below a Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied b Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 4 16 C141 E034 02EN Seek to specified cylinder Drives the VCM to position the head to the specified cylinder Calibration Senses and store
103. irmware When the head arrives at the target cylinder the track is followed Track following operation Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed the MPU does track following control To position the head at the center of a track the DSP drives the VCM by feeding micro current For each sampling time the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware Spindle motor control Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC hereafter The firmware operates on the MPU manufactured by Fujitsu The spindle motor is controlled by sending several signals from the MPU to the SVC There are three modes for the spindle control start mode acceleration mode and stable rotation mode Start mode When power is supplied the spindle motor is started in the following sequence a After the power is turned on the MPU sends a signal to the SVC to charge the change pump capacitor of the SVC The charged amount defines the current that flows in the spindle motor b When the charge pump capacitor is charged enough the MPU sets the SVC to the motor start
104. is specified to 1 the lower 4 bits of the DH register and all bits of the CH CL and SN registers indicate the LBA bits bits of the DH register are the MSB most significant bit and bits of the SN register are the LSB least significant bit 2 Aterror occurrence the SC register indicates the remaining sector count of data transfer 3 In the table indicating I O registers contents in this subsection bit indication is omitted READ SECTOR S X20 or X21 This command reads data of sectors specified in the Sector Count register from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers Number of sectors can be specified to 256 sectors in maximum specify 256 sectors reading 00 is specified For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 4 4 1 If the head is not on the track specified by the host the device performs a implied seek After the head reaches to the specified track the device reads the target sector When the command is specified without retry bit 1 or with retry bit 0 the device attempts to read the target sector up to 126 times The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition Upon the completion of the command execution command block registers contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the l
105. isk media is assured in the event of any power supply abnormalities This does not include power supply abnormalities during disk media initialization formatting or processing of defects alternative block assignment Error Rate Known defects for which alternative blocks can be assigned are not included in the error rate count below It is assumed that the data blocks to be accessed are evenly distributed on the disk media Unrecoverable read error Read errors that cannot be recovered by maximum 126 times read retries without user s retry and ECC corrections shall occur no more than 10 times when reading data of 10 bits Read retries are executed according to the disk drive s error recovery procedure and include read retries accompanying head offset operations Positioning error Positioning seek errors that can be recovered by one retry shall occur no more than 10 times in 10 seek operations Media Defects Defective sectors are replaced with alternates when the disk is formatted prior to shipment from the factory low level format Thus the host sees a defect free device Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors Chapter 6 describes the low level format at shipping C141 E034 02EN 2 DEVICE CONFIGURATION 2 1 22 Device Configuration System Configuration 2 1 Device Configuration Figure 2 1 sh
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107. lears the BYS bit and generates an interrupt soon When the command execution completes the device clears the BSY bit and generates an interrupt The drive supports this command for keep the compatibility with previous drive only READ LONG X22 or X23 This command operates similarly to the READ SECTOR S command except that the device transfers the data in the requested sector and the ECC bytes to the host system The ECC error correction is not performed for this command This command is used for checking ECC function by combining with the WRITE LONG command Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command The READ LONG command supports only single sector operation C141 E034 02EN 19 At command issuance I O registers setting contents IFG DH E Head No LBA MSR 1F5g CH Cylinder No MSB LBA 1 Cylinder LSB LBA 1F3y SN Sector No LBA LSB 1F24 SC Number of sectors to be transferred 1Fl4 FR R 0 gt with Retry R without Retry At command completion I O registers contents to be read 1F6 DH Head No LBA MSB 1F5g CH Cylinder No MSB LBA 1F44 CL Cylinder No LSB LBA 1F34 SN Sector No LBA LSB 1F24 SC 00 1 1 15 Error information If the command is terminated due to an error this register indicates 01 WRITE LONG X32 or X33 This command operates similarly to
108. lease the DRQ set state by resetting Figure 5 4 Protocol for command abort Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive FORMAT TRACK WRITE SECTOR S WRITE LONG WRITE BUFFER WRITE VERIFY The execution of these commands includes the transfer one or more sectors of data from the host to the device In the WRITE LONG command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code in the Command register The drive sets the BSY bit of the Status register C141 E034 02EN 5 57 When the device is ready to receive the data of the first sector the device sets DRQ bit and clears BSY bit d The host writes one sector of data through the Data register e The device clears the DRQ bit and sets the BSY bit f When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the DRQ bit 6 After detecting the INTRQ signal assertion the host reads the Status register h The device resets INTRQ the interrupt signal I Iftransfer of another sector is requested steps d and after are repeated Figure 5 5 shows an example of WRITE SECTOR S command protocol and Figu
109. lock time see Note 1 Maximum time allowed for output drivers to release from being asserted or negated Minimum delay time required for output ER to assert or negate from released Envelope time from DMACK to STOP HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation STROBE to DMARDY time if DMARDY is negated before this long after STROBE edge the recipient shall receive no more than one additional data word Ready to final STROBE time no STROBE edges shall be sent this long after negation of DMARDY Ready to pause time that recipient shall wait to initiate pause after negating DMARDY MIN MAX ic m M o 150 o EM uuu 5 78 C141 E034 02EN MODE 0 MODE 1 MODE 2 COMMENT in ns in ns in ns pes wax wm ww wax tIoRDYZ 20 20 20 Pull up time before allowing IORDY to be released tziorpy Minimum time device shall wait before driving IORDY tack 20 20 20 Setup and hold times for DMACK before assertion or negation tss 50 Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst Notes 1 tur tmu and tj indicate sender to recipient or recipient to sender interlocks that is one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding tu is unlimited interlock th
110. m a previous Ultra DMa burst in the same command If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred For READ DMA or WRITE DMA commands When a CRC error is detected it shall be reported by setting both ICRC and ABRT bit 7 and bit 2 in the Error register to one ICRC is defined as the Interface CRC Error bit The host shall respond to this error by re issuing the command A host may send extra data words on the last Ultra DMA burst of a data out command If a device determines that all data has been transferred for a command the device shall terminate the burst A device may have already received more data words than were required for the command These extra words are used by both the host and the device to calculate the CRC but on an Ultra DMA data out burst the extra words shall be discarded by the device The CRC generator polynomial is G X X16 X12 X5 1 Note Since no bit clock is available the recommended approach for calculating CRC is to use a word clock derived from the bus strobe The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DDO is shifted in first and DD15 is shifted in last C141 E034 02EN 5 71 5 5 6 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for
111. mable filter sese 4 12 PRA signal transfert oon HRORTER eO ten 4 13 Block diagram of servo control circuit esseeseseeeeeeee eee enne 4 16 Physical sector servo configuration on disk 5 4 17 Servo frame LOrmMat sss o aD tO dene Ee Hle eee ripe EERS 4 19 5 528 Geil Bie hin MESA A Ree ES 5 2 Execution example of READ MULTIPLE 2 5 19 Read Sector s command 5 56 C141 E034 02EN xi 5 4 5 5 5 6 5 7 5 8 5 9 5 10 5 11 5 12 5 13 5 14 5 15 5 16 5 17 5 18 5 19 5 20 5 21 5 22 61 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 xii Protocol for command abort sese 5 57 WRITE SECTOR S command 4 40 1 5 58 Protocol for the command execution without data transfer 5 59 Normal DMA data transfer 2 2 220 01 0 000000000000 5 61 Ultra DMA termination with pull up or pull down eee 5 72 PIO data transfer tuning het e eei e iced eret 5 74 Single word DMA data transfer 5 75 Multiword DMA data transfer timing 2 5 76 Initiating an Ultra DMA data in
112. mplementation of the READ MULTIPLE command is identical to that of the READ SECTOR S command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts In the READ MULTIPLE command operation the DRQ bit of the Status register is set only at the start of the data block and is not set on each sector The number of sectors block count to be transferred without interruption is specified by the SET MULTIPLE MODE command The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command When the READ MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0 If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled the device rejects the READ MULTIPLE command with an ABORT
113. nal for up to 450 ms to confirm presence of a slave device The master device recognizes the presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the self diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device receives the hardware reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below DASP signal Asserted within 400 ms PDIAG signal Negated within 1 ms and asserted within 30 seconds Reset Master device Status Reg BSY bit s Max 31 sec gt 4 gt If presence of a slave device is Checks DASP for up to confirmed PDIAG is checked for 450 me up to 31 seconds Slave device BSY bit 1 ms PDIAG Max 30 sec lt DASP Max 400 ms Figure 6 2 Response to hardware reset C141 E034 02EN 6 3 6 1 3 Response to software reset The master device does not check the DASP signal for a software reset If a slave device is present the master device checks the PDIAG signal for up to 31 seconds to see if the slave device has completed the self diagnosis successfully After the
114. nd the device sets the BSY bit of the Status register and saves the parameters in the Features register Then the device clears the BSY bit and generates an interrupt If the value in the Features register is not supported or it is invalid the device posts an ABORTED COMMAND error Table 5 5 lists the available values and operational modes that may be set in the Features register C141 E034 02EN 5 33 Table 5 5 Features register values and settable modes and multiword DMA mode regardless of Sector Count register contents Disables the write cache function Enables the read cache function X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands Enables the reverting to power on default settings after software reset At power on or after hardware reset the default mode is the same as that is set with a value greater than X AA except for write cache If X 66 is specified it allows the setting value greater than X AA which may have been modified to a new value since power on to remain the same even after software reset At command issuance I O registers setting contents 1F74 CM 1 1 1 0 1 1 1 1 1F54 CH 1F44 CL 1F34 SN 1 2 5 or transfer mode 1FIg FR See Table 5 6 At command completion I O registers contents to be read 1F5 CH XX 1F4 CL XX 1F34 SN 1 2 5 1F1y ER Error information 5 34 C141 E034 02EN 15 The h
115. nearest to a failure so far C141 E034 02EN Raw attribute value Raw attributes data is retained Failure prediction capability flag Bit 0 The attribute value data is saved to a medium before the device enters power saving mode Bit 1 The device automatically saves the attribute value data to a medium after the previously set operation Bits 2 to 15 Reserved bits Check sum Two s complement of the lower byte obtained by adding 511 byte data one byte at a time from the beginning Insurance failure threshold The limit of a varying attribute value host compares the attribute values with the thresholds to identify a failure 141 034 02 5 53 5 3 3 Error posting Table 5 10 lists the defined errors that are valid for each command Table 5 10 Command code and parameters Command name Error register X 1F1 Status register X 1F7 2m V keap mocne v v KARS E kecara SEEK INITIALIZE DEVICE PARAMETERS IDENTIFY DEVICE IDENTIFY DEVICE DMA SET FEATURES uri HI lt lt SET MULTIPLE MODE EXECUTE DEVICE DIAGNOSTIC Fomara Deis v LL wma Jv freapeurrer ms wemmer wv SLEEP Pd cuzce rower mone 1 1
116. not satisfied the device may receive zero one or two more data words from the host Figure 5 19 Device pausing an Ultra DMA data out burst 5 86 C141 E034 02EN 5 6 4 10 Host terminating an Ultra DMA data out burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes tu DMARQ device tu DMACK host tu tack tss STOP host Ries 202 lioRDvz pio tack _ gt gt host NN CN EE tovs DD 15 0 SS IS IIL OX Dee DOR 12 lt gt lt lt lt 2 lt 2 lt tack DAO DA1 DA2 50 CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Host terminating an Ultra DMA data out burst C141 E034 02EN 5 87 5 6 4 11 Device terminating an Ultra DMA data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host lack STOP host mE trp tiorpyz DDMARDY device tres tu tuu tack HSTROBE 7 a host tovs tack DAO DA1 DA2 50 51 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are longer in effect after DMARQ and DMACK are negated Figure 5 21 Device terminating an Ultra DMA data out burst 5 88 C141 E034 02EN 5 6 5 and reset
117. nsfer When the command execution is completed the device clears both BSY and DRQ bits and asserts the INTRQ signal Then the host reads the Status register The host resets the DMA channel C141 E034 02EN Parameter write v Command Status read BSY aoo DRDY INTRQ DRQ Data transfer Expanded Single Word DMA transfer DRQ DMARQ DMACK IOR or eters IOW Word 0 1 2 255 Multiword DMA transfer DRQ DMARQ DMACK IOR or IOW Word 0 1 n 1 n Figure 5 7 Normal DMA data transfer C141 E034 02EN 5 61 5 5 5 5 1 Ultra DMA feature set Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host This protocol applies to the Ultra DMA data burst only When this protocol is used there are no changes to other elements of the ATA protocol e g Command Block Register access Several signal lines are redefined to provide new functions durin
118. nto the SA area and reads out the system information The disk drive executes self seek calibration This collects data for VCM torque and mechanical external forces applied to the actuator and updates the calibrating value The drive becomes ready The host can issue commands C141 E034 02EN Self diagnosis 1 MPU bus test nner register write read test Work RAM write read test The spindle motor starts Vv b Self diagnosis 2 Data buffer write read test i c Confirming spindle motor speed Vv Release heads from actuator lock ww d Initial on track and read out of system information Execute self calibration f Drive ready state command waiting state End Figure 4 3 Power on operation sequence C141 E034 02EN 4 5 4 5 1 1 2 Self calibration The disk drive occasionally performs self calibration in order to sense and calibrate mechanical external forces on the actuator and VCM torque This enables precise seek and read write operations Self calibration contents Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution The torque vary with the disk drive and the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the driv
119. ommand When non sequential read command is received after executing the sequential read command read ahead operation and more than ten non sequential read commands are received after that continuously the read ahead operation is stopped refer to item 1 Processing is the same as item a above Full hit hit all All requested data are stored in the data buffer The disk drive starts transferring the requested data from the address of which the requested data is stored After completion of command a previously existed cache data before the full hit reading are still kept in the buffer and the disk drive does not perform the read ahead operation C141 E034 02EN 6 19 1 In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command the disk drive sets the HAP to the address of which the hit data is stored Last position at previous read command HAP HAP set to hit position for data transfer Last position at previous read command 2 The disk drive transfers the requested data but does not perform the read ahead operation HAP stopped Cache data pal pit qas 22 Cache data 3 The cache data for next read command is as follows Cache data gt Start LBA Last LBA 4 Partially hit A part of requested data including a lead sector are stored in the data buffer The disk drive starts the data tran
120. on of the command execution other than SLEEP and STANDBY commands Reset hardware or software Standby mode In this mode the VCM circuit is turned off and the spindle motor is stopped The device can receive commands through the interface However if a command with disk access is issued response time to the command under the standby mode takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately The drive enters the standby mode under the following conditions e A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode e When automatic power down sequence is enabled the timer has elapsed e reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software e STANDBY command C141 E034 02EN 6 9 4 6 3 2 6 4 STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode The drive enters only the standby mode from the sleep mode The only method to return from the standby mode is to execute a software or hardware reset The drive enters the sleep mode under the following condition ASLEEP command is issued Issued commands are invalid ignored in this mode Power commands The following commands are
121. onstant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant The drive divides data area into 15 zones to set the data transfer rate Table 4 3 describes the data transfer rate and recording density BPI of each zone C141 E034 02EN Table4 3 Write clock frequency and transfer rate of each zone SER Cylinder 0 623 1789 2218 2619 3031 3828 4142 to to to to to to to to 622 1788 2217 2618 3030 3827 4141 4808 14 964 14 111 13 787 13 473 13 155 12 512 12258 11 702 Cylinder 4809 5120 6108 6614 7195 7892 8461 to to to to to to to 5119 6107 6613 7194 7891 8460 8712 Transferrate 11 443 10 590 10 142 9 623 8 986 8451 8019 MB s The MPU transfers the data transfer rate setup data SDATA SCLK to the RDC that includes the time base generator circuit to change the data transfer rate 4 7 Servo Control The actuator motor and the spindle motor are submitted to servo control The actuator motor is controlled for moving and positioning the head to the track containing the desired data To turn the disk at a constant velocity the actuator motor is controlled accord
122. operation in any of the Ultra DMA Modes The following table describes recommended values for series termination at the host and the device Table 5 11 Recommended series termination for Ultra DMA Signal Host Termination DIOR HDMARDY HSTROBE Note Only those signals requiring termination are listed in this table If a signal is not listed series termination is not required for operation in an Ultra DMA Mode For signals also requiring a pull up or pull down resistor at the host see Figure 5 8 Figure 5 8 Ultra DMA termination with pull up or pull down 5 72 C141 E034 02EN 5 6 5 6 1 Timing PIO data transfer Figure 5 9 shows of the data transfer timing between the device and the host system 141 034 02 Addresses P 2d 9 DIOR DIOW gt 2 2 ee Qi 4 2 gt Write data NC DDO DD15 t3 ye t4 gt Read data 2 ON DDO DD15 t5 v 4 t6 IOCS16 t7 Ax IORDY 10 4 4 t11 rs ns ORION s prenna sisin mat ine oeno p Time from DIOR DIOW assertion to IORDY low level ME il eed 2 a 2 n 2 e ue Ts 1 Time from validity of read data to IORDY high level Pulse width of IORDY 1 250 Figure 5 9 PIO data transfer timing 5 74 C141 E034 02EN 5 6 2 Single word DMA data transfer
123. ost sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value However the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is posted PIO default transfer mode 00000 000 00 PIO flow control transfer mode X 00001 000 X 08 Mode 0 00001 001 X 09 Mode 1 00001 010 X 0A Mode 2 00001 011 X 0B Mode 3 00001 100 X 0C Mode 4 Single word DMA transfer mode X 00010 000 X 10 Mode 0 00010 001 X 11 Mode 1 00010 010 X 12 Mode 2 Multiword DMA transfer mode X 00100 000 X 20 Mode 0 00100 001 X 21 Mode 1 00100 010 X 22 Mode 2 Ultra DMA transfer mode X 01000 000 X 40 Mode 0 01000 001 X 41 Mode 1 01000 010 X 42 Mode 2 SET MULTIPLE MODE X C6 This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands The block count number of sectors in a block for these commands are also specified by the SET MULTIPLE MODE command The number of sectors per block is written into the Sector Count regis
124. ot generating DSTROBE edges The device shall negate DMARQ no sooner than tss after generating the last DSTROBE edge The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The device shall release DD 15 0 no later than t4z after negating DMARQ The host shall assert STOP within t after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated The host shall negate HDMARDY within t after the device has negated DMARQ The host shall continue to negate HDMARDY until the Ultra DMA burst is terminated Steps 4 and 5 may occur at the same time The host shall drive DD 15 0 no sooner than tzay after the device has negated DMARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 If DSTROBE is negated the device shall assert DSTROBE within t after the host has asserted STOP data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra DMA burst is terminated If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 6 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than ty after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMA
125. overy servo mark gray code servo A to D and PAD Figure 4 9 shows the servo frame format Write read Servo Servo Servo Servo Servo recovery mark pap gt 4 gt gt gt gt gt 8 0 us 0 56 us 3 20 us 2 09 us 2 0 us 2 0us 2 0 us 1 53 us Figure 4 9 Servo frame format C141 E034 02EN 4 19 1 2 3 4 5 4 7 4 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC Servo mark This area generates a timing for demodulating the gray code and position demodulating the servo A to D by detecting the servo mark Gray code including index bit This area is used as cylinder address The data in this area is converted into the binary data by the gray code demodulation circuit Servo A servo B servo C servo D This area is used as position signals between tracks and the IDD control at on track so that servo A level equals to servo B level PAD This area is used as a gap between servo and data Actuator motor control The voice coil motor VCM is controlled by feeding back the servo data recorded on the data surface The MPU fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the
126. ower is turned on 5 Power on off sequence The voltage detector circuit monitors 5 V and 12 V The circuit does not allow a write signal if either voltage is abnormal This prevents data from being destroyed and eliminates the need to be concerned with the power on off sequence 141 034 02 1 7 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Temperature Operating 5 C to 55 C ambient 5 C to 60 C disk enclosure surface Non operating 409 to 609 Thermal Gradient 20 or less Operating 8 to 80 RH Non condensing Non operating 5 to 85 RH Non condensing Maximum Wet Bulb 299 Altitude relative to sea level Operating 60 to 3 000 m 200 to 10 000 ft Non operating 60 to 12 000 m 200 to 40 000 ft 1 5 Acoustic Noise Table 1 5 lists the acoustic noise specification Table 1 5 Acoustic noise specification Sound Pressure Idle mode DRIVE READY 35 dBA typical at 1 m Seek mode Random 40 dBA typical at 1 m 1 8 141 034 02 1 6 Shock and Vibration Table 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Vibration swept sine one octave per minute Operating 5 to 300 Hz 0 5G 0 peak without non recovered errors Non operating 5 to 400 Hz 4G 0 peak no damage Shock half sine pulse 11 ms duration 1 7 1 2 3 Ope
127. ows the disk drive motors actuators and a circulating air filter Figure 2 1 C141 E034 02EN The disk drive consists of a disk enclosure DE preamplifier and controller PCA The disk enclosure contains the disk media heads spindle Disk drive outerview 1 2 Disk The outer diameter of the disk is 95 mm The inner diameter is 25 mm The number of disks used varies with the model as described below The disks are rated at over 40 000 start stop operations MPA3017AT 1 disk MPA3026AT 2 disks MPA3035AT 2 disks MPA3043AT 3 disks MPA3052AT 3 disks Head The heads are of the contact start stop CSS type The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts Figure 2 2 illustrates the configuration of the disks and heads of each model In the disk surface servo information necessary for controlling positioning and read write and user data are written Numerals 0 to 5 indicate read write heads C141 E034 02EN MPA3017 Model Spindle Actuator 0 026 Model MPA3035AT Model Spindle Actuator Spindle Actua
128. place the result of its CRC calculation on DD 15 0 see 5 5 5 11 The host shall negate DMACK no sooner than tyr after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY no sooner than tpys after the host places the result of its CRC calculation on DD 15 0 12 The device shall latch the host s data from DD 15 0 on the negating edge of DMACK 13 The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA burst for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 14 The device shall release DSTROBE within tiorpyz after the host negates DMACK 15 The host shall neither negate STOP nor assert HDMARDY until at least after the host has negated DMACK 16 The host shall not assert DIOR CSO 51 DA2 DAI or DAO until at least after negating DMACK Ultra DMA data out commands Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 7 and 5 6 4 2 for specific timing requirements 1 2 3 4 5 6 7 8 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated The device shall assert DMARQ to initiate an Ultra DMA burst Steps 3 4
129. r slave device For use of Cable Select function Unique interface cable is needed 3 10 C141 E034 02EN 02 06 O OJO B01 05 CSEL connected to the interface Cable selection can be done by the special interface cable Figure 3 13 Jumper setting of Cable Select Figures 3 14 and 3 15 show examples of cable selection using unique interface cables By connecting the CSEL of the master device to the CSEL Line conductor of the cable and connecting it to ground further the CSEL is set to low level The device is identified as a master device At this time the CSEL of the slave device does not have a conductor Thus since the slave device is not connected to the CSEL conductor the CSEL is set to high level The device is identified as a slave device Rom woe demie Rm ncm mm mm m etm Figure 3 14 Example 1 of Cable Select CER ato DI P GND Figure 3 15 Example 2 of Cable Select C141 E034 02EN 3 11 3 Special setting 1 SP1 The number of cylinders reported by the IDENTIFY DEVICE command is selected a Default mode 2 4 6 2 4 6 2 4 6 OIO O OIO O O O OIO O 1 3 5 I 383 1 3 5 Master Device Slave Device Cable Select Model No of cylinders MPA3017AT 3 39
130. rating 10G without non recovered errors Non operating 75G no damage Reliability Mean time between failures MTBF The mean time between failures MTBF is 500 000 H or more operation 24 hours day 7 days week This does not include failures occurring during the first three months after installation MTBF is defined as follows Total operation time in all fields MTBF number of device failure in all fields Disk drive defects refers to defects that involve repair readjustment or replacement Disk drive defects do not include failures caused by external factors such as damage caused by handling inappropriate operating environments defects in the power supply host system or interface cable Mean time to repair MTTR The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 489 When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occurs first Refer to item 3 in Subsection 3 2 for the measurement point of the DE surface temperature C141 E034 02EN 1 9 4 1 8 1 2 1 9 1 10 Data assurance in the event of power failure Except for the data block being written to the data on the d
131. re 5 4 shows an example protocol for command abort Parameter write v Command Status read Status read is 7 a psy 2 f__is Dp ci s DRDY INTRQ Data transfer d Expanded Command E DRQ 4 5 Max 1 us Data Reg Selection Data 28 puc IOR RE Word 0 1 2 255 10 516 Figure 5 5 WRITE SECTOR S command protocol C141 E034 02EN 5 4 3 Note For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to 50 us after the completion of the sector data transfer Note that the host does not need to read the Status register for the first and the last sector to be transferred If the timing to read the Status register does not meet above condition normal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECALIBRATE SEEK READY VERIFY SECTOR S EXECUTE D
132. riving the first word of data onto DD 15 0 The data in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 3 and 5 6 4 2 1 The device shall drive a data word onto DD 15 0 2 The device shall generate a DSTROBE edge to latch the new word no sooner than tpys after changing the state of DD 15 0 The device shall generate a DSTROBE edge no more frequently than tcyc for the selected Ultra DMA Mode The device shall not generate two rising or two falling DSTROBE edges more frequently than 2tcyc for the selected Ultra DMA mode 3 The device shall not change the state of DD 15 0 until at least tpyq after generating a DSTROBE edge to latch the data 4 The device shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first Pausing an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 4 and 5 6 4 2 for specific timing requirements a Device pausing an Ultra DMA data in burst 1 The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 The device shall pause an Ultra DMA burst by not generating DSTROBE edges NOTE The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges If the d
133. rting The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system operates The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable Only the Ultra DMA Mode shall be selected at any given time All timing requirements for a selected Ultra DMA Mode shall be satisfied Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and 1 Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA Mode 0 An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after executing a Software reset sequence An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non Ultra DMA Modes after executing a Power on or hardware reset Both the host and device perform a CRC function during an Ultra DMA burst At the end of an Ultra DMA burst the host sends the its CRC data to the device The device compares its CRC data to the data sent from the host If the two values do not match the device reports an error in the error register at the end of the command If an error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred C141 E034 02EN 5 5 2 5 5 3 5 5 3 1 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra D
134. s setting contents 1F74 CM 0 0 1 1 0 0 0 R 1F64 DH Start head No LBA MSB 1F54 CH Start cylinder No MSB LBA 1F44 CL Start cylinder No LSB LBA 1F34 SN Start sector No LBA LSB 1F24 SC Transfer sector count 1Fl4 FR R 0 gt with Retry R without Retry C141 E034 02EN 6 At command completion I O registers contents to be read 1F64 DH End head No LBA MSB 1F54 CH End cylinder No MSB LBA 1F44 CL End cylinder No LSB LBA 1F34 SN End sector No LBA LSB 1F24 SC 00 1 1 15 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register WRITE MULTIPLE 5 This command is similar to the WRITE SECTOR S command The device does not generate interrupts assertion of the INTRQ signal on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command The implementation of the WRITE MULTIPLE command is identical to that of the WRITE SECTOR S command except that the number of sectors is specified by the SET MULTIPLE MODE command are transferred without intervening interrupts In the WRITE MULTIPLE command operation the DRQ bit of the Status register is required to set only at the start of the data block not on each sector The number of sectors block count to be transferred without in
135. s the thermal offset between heads and the mechanical forces on the actuator and stores the calibration value Servo frame 60 servo frames revolution Cyl n 1 Cyl n Cyl n 1 W R Recovery W R Recovery W R Recovery Servo Mark 5 Mark Servo Mark Gray Code Gray Code Gray Code Erase Servo A Erase Servo A Erase Servo B Erase Servo B Erase Servo B Servo C Erase Servo C Erase PAD n odd number lt gt Diameter direction V Circumference direction Erase DC erase area Figure 4 8 Physical sector servo configuration on disk surface C141 E034 02EN 2 3 4 5 6 7 8 Servo burst capture circuit The four servo signals can be synchronously detected by the STROB signal full wave rectified integrated A D converter ADC The A D converter ADC receives the servo signals are integrated converts them to digital and transfers the digital signal to the DSP unit D A converter DAC The D A converter DAC converts the VCM drive current value digital value calculated by the DSP unit into analog values and transfers them to the power amplifier Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor This circuit detects number of revolution of the motor b
136. sed by the host to select the control block registers Binary decoded address signals asserted by the host to access task file registers Key pin for prevention of erroneous connector insertion This signal is an input mode for the master device and an output mode for the slave device in a daisy chain configuration This signal indicates that the slave device has been completed self diagnostics This signal is pulled up to 5 V through 10 KQ resistor at each device This is a time multiplexed signal that indicates that the device is active and a slave device is present This signal is pulled up to 5 V through 10 resistor at each device C141 E034 02EN signal Description IORDY This signal is negated to extend the host transfer cycle of any host DDMARDY register access Read or Write when the device is not ready to DSTROBE respond to a data transfer request DDMARDY is a flow control signal for Ultra DMA data out bursts This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts The device may negate DDMARDY to pause an Ultra DMA data out burst DSTROBE is the data in strobe signal from the device for an Ultra DMA data in burst Both the rising and falling edge of DETROBE latch the data from DATA 0 15 into the host The device may stop generating DSTROBE edges to pause an Ultra DMA data in burst CSEL I This signal to configure the device as a mast
137. serious personal ANG R injury if the user does not perform the procedure correctly This indicates a hazarous situation could result in personal injury if the AW ARN l NG user does not perform the porocedure correctly This indicates a hazarous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly This AC AUTI 0 N alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly This indicates information that could help the user use the product more IMPORTANT efficiently In the text the alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example IMPORTANT HA host adapter consists of address decoder driver and receiver ATA is an abbreviation of AT attachment The disk drive is conformed to the ATA 3 interface The main alert messages in the text are also listed in the Important Alert Items iv C141 E034 02EN LIABILITY EXCEPTION Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host sy
138. sfer from the address of the hit data corresponding to the lead sector of the requested data and reads remaining requested data from the disk media directly The disk drive does not perform the read ahead operation after data transfer Following is an example of partially hit to the cache data Cache data A Start LBA Last LBA 6 20 C141 E034 02EN 1 The disk drive sets to the address where the partially hit data is stored and sets the DAP to the address just after the partially hit data n VELIT TA 4 Lack data DAP 2 The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time However the disk drive does not perform the read ahead operation newly HAP Requested data to be transferred stopped e ET Lack data gt DAP stopped 3 The cache data for next read command is as follows Cache data gt Start LBA Last LBA C141 E034 02EN 6 21 6 6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed When the drive receives a write command the drive starts transferring data of sectors requested by the host system and writing on the disk medium After transferring data of sectors requested by the host system t
139. stem or other causes outside the disk drive C141 E034 02EN CONTENTS page CHAPTER1 DEVICE 1 1 1 1 Features IEEE PRAE IP unten PIRE UE 1 1 1 1 1 Functions and 1 1 12112 Ad ptability rennen pe t i e ie eie tein ote ites 1 2 l L3 Interface us eet rtt GR et rrt NE GUT PEE 1 2 1 2 D vice Specifications oe Sei eum 1 4 1 2 1 Specifications Ine e eder ane iden 1 4 1 2 2 C Model and product number ooo o RS OB pt OCA EU S 1 5 1 3 Power Requirements cene pee n OB DOREM DER eria 1 5 1 4 Environmental Specifications eese enne tenete nennen nennen 1 8 1 5 Acoustic NOISE UE H EE 1 8 1 6 SHOCK and Vibration eri e eed eli he deed ped e 1 9 1 7 Rehability ore ea ree 1 9 1 8 Error Rate semet rope te pente oa pep eO Ee i Prater gere ee eu 1 10 1 9 Media Defects EE 1 10 2 DEVICE 22 2 02202 0 1 000000008 2 1 2 1 ote 2 1 2 2 System Configuration ceo e rH e RED E tens 2 4 222 5
140. t least tacx after negating DMACK Ultra DMA CRC rules The following is a list of rules for calculating CRC determining if a CRC error has occurred during an Ultra DMA burst and reporting any error that occurs at the end of a command a b 4 g h D Both the host and the device shall have a 16 bit CRC calculation function Both the host and the device shall calculate a CRC value for each Ultra DMA burst The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred For each STROBE transition used for data transfer both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual functions and the word being transferred is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved fro
141. ta to 9 bit data by the encoder circuit then sent to the PreAMP and the data is written onto the media 8 9 GCR The disk drive converts data using the 8 9 0 4 4 group coded recording GCR algorithm This code format is 0 to 4 code bit 0 s are placed between 1 Write precompensation Write precompensation compensates during a write process for write non linearity generated at reading Table 4 2 shows the write precompensation algorithm Table 4 2 Write precompensation algorithm Compensation None Late Late Late Bit is time shifted delayed from its nominal time position towards the bit 1 time position C141 E034 02EN 0 lt 0 1710 IMAN VANS RDX RDY WDX WDY Read Write Preamplifier Serial Bus gt ES del RDC Control Logic wG SG DP DN AGC Programmable Servo Pulse AMP Filter Detector AGC 3 Tap EAS Charge k Full Wave Adaptive Viterbi J 8 9GCR Pump Rectifier Equalizer Detector Decoder AGC Control DSCLK Logic Data Separator e Parallel Time Base P Interface Generator WicompDT Write PrecodeDT EncodeDT 8 9GCR lt
142. ter The IDD supports 2 4 8 16 and 32 sectors as the block counts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the device clears the BSY bit and generates an interrupt C141 E034 02EN 5 35 At command issuance I O registers setting contents iron 1F5g CH 1F44 CL XX 1F3y SN XX 1F2y SC Sector count block 1F1y FR XX At command completion I O registers contents to be read eT Tx oe 1F5g CH 1F44 CL 1IF3g SN XX 1 2 5 Sector count block 1F1y ER Error information After power on or after hardware reset the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode Regarding software reset the mode set prior to software reset is retained after software reset The parame
143. ter for read or write operation can be accessed by 16 bit data bus DATAO to DATA15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATAO to DATA7 3 When reading the Drive Address register bit 7 is high impedance state 4 LBA mode is specified the Device Head Cylinder High Cylinder Low and Sector Number registers indicate LBA bits 27 to 24 23 to 16 15 to 8 and 7 to 0 C141 E034 02EN 5 7 5 2 2 1 2 Command block registers Data register X 1F0 The Data register is a 16 bit register for data block transfer between the device and the host system Data transfer mode is PIO or LBA mode Error register X 1F1 The Error register indicates the status of the command executed by the device The contents of this register are valid when the ERR bit of the Status register is 1 This register contains a diagnostic code after power is turned on a reset or the EXECUTIVE DEVICE DIAGNOSTIC command is executed Status at the completion of command execution other than diagnostic command ICRC UNC IDNF ABRT TKONF AMNF X Unused Bit 7 Interface CRC error ICRC This bit indicates that an interface CRC error has occurred during an Ultra DMA data transfer The content of this bit is not applicable for Multiword DMA transfers Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered
144. ter is read Bit 7 Busy BSY bit This bit is set whenever the Command register is accessed Then this bit is cleared when the command is completed However even if a command is being executed this bit is O while data transfer is being requested DRQ bit 1 When BSY bit is 1 the host system should not write the command block registers If the host system reads any command block register when BSY bit is 1 the contents of the Status register are posted This bit is set by the device under following conditions a Within 400 ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is set for no longer than 15 seconds after the IDD accepts reset b Within 400 ns from the host system starts writing to the Command register c Within 5 us following transfer of 512 bytes data during execution of the READ SECTOR S WRITE SECTOR S FORMAT TRACK or WRITE BUFFER command Within 5 us following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command Bit 6 Device Ready DRDY bit This bit indicates that the device is capable to respond to command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of t
145. terruption is specified by the SET MULTIPLE MODE command The SET MULTIPLE MODE command should be executed prior to the WRITE MULTIPLE command When the WRITE MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0 If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block If an error occurs the subsequent block shall not be transferred Interrupts are generated when the DRQ bit of the Status register is set at
146. ters for the multiple commands which are posted to the host system when the IDENTIFY DEVICE command is issued are listed below See Subsection 5 3 2 for the IDENTIFY DEVICE command Word 47 0020 Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands are 32 fixed Word 59 0000 READ MULTIPLE and WRITE MULTIPLE commands are disabled 01 READ MULTIPLE and WRITE MULTIPLE commands are enabled XX indicates the current setting for number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands e g 0110 Block count of 16 has been set by the SET MULTIPLE MODE command C141 E034 02EN 16 EXECUTE DEVICE DIAGNOSTIC 907 This command performs an internal diagnostic test self diagnosis of the device This command usually sets the DRV bit of the Drive Head register is to 0 however the DV bit is not checked If two devices are present both devices execute self diagnosis If device 1 is present e devices shall execute self diagnosis e device 0 waits for up to 5 seconds until device 1 asserts the PDIAG signal e If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status e The device 0 clears the BSY bit of the Status register and generates an interrupt The device does not generate an interrupt A diagnostic
147. the read segment buffer at following cases Miss hit no hit A lead block of the read requested data is not stored in the data buffer The requested data is read from the disk media The read ahead operation is performed till the buffer becomes full when the received lead sector address is sequential to the last sector address of previous read command When it is not sequential the drive checks that the sequential read command is executed for last received ten read commands When no sequential read command is issued the read ahead operation is stopped refer to item 2 C141 E034 02EN 6 15 1 Sets the host address pointer and the disk address pointer DAP to the lead of segment HAP Segment only for read DAP 2 Transfers the requested data that already read to the host system with reading the requested data from the disk media HAP Stores the read requested data upto this point Empty area 221 DAP 3 After reading the requested data and transferring the requested data to the host system had been completed the disk drive stops command execution without performing the read ahead operation HAP stopped pap 77 Empty area stopped DAP 4 Following shows the cache enabled data for next read command Cache enabled data Empty area Start LBA Last LBA C141 E034 02EN 3 Sequential re
148. the subsequent sector from the last sector of the current physical head address The first physical sector of the subsequent physical sector is the consecutive logical sector from the last sector of the current physical sector Figure 6 5 shows an example assuming there is no track skew Physical sector 52 752 62 63 1764 12617127 249 250 Physical cylinder 0 LSI E LS1 p ILS 1 e E Physical head 0 mue LHO LHI LH2 LH3 RR 64 N65 esse cylinder 1 Ls e Ls PhysicalheadO 7 i 5 LH3 LH4 LH5 ex Zone 0 Physical parameter Physical sector 1 to 250 Specification of INITIALIZE DEVICE PARAMETERS command Logical head 0 to 15 Logical sector LS 1 to 63 Figure 6 5 Address translation example in CHS mode C141 E034 02EN 6 7 2 LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0 physical head 0 and physical sector 1 The logical address is advanced at the subsequent sector from the last sector of the current track The first physical sector of the subsequent physical track is the consecutive logical sector from the last sector of the current physical track Figure 6 6 shows an example of assuming there is no track skew Physical sector 1 2 3 249 250 Physical cylinder 0 LBAO LBAI LBA2 LBA LBA Physical head 0 248 249 1 2
149. this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents 1 73 99 or X E6 1F5 CH 1F4 CL 1F34 SN 1F24 SC 1 C141 E034 02EN 5 45 At command completion 1 registers contents to be read oe 07 _ 1F5 CH 1FAg CL 1 8 1F24 SC 27 Error information CHECK POWER MODE X 98 or X E5 The host checks the power mode of the device with this command The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt During moving to standby mode e Standby mode During returning from the standby mode Idle mode Active mode X FF xm 141 034 02 28 At command issuance I O registers setting contents 1F74 CM 98 or 5 Xx Xx Xx
150. tion as the Status register of the command block register The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset Device Control register X 3F6 The Device Control register contains device interrupt and software reset Bit 2 SRST is the host software reset bit When this bit is set the device is held reset state When two device are daisy chained on the interface setting this bit resets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state Host Commands The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the Command register The device can accept the command when the BSY bit is 0 the device is not in the busy status The host system can halt the uncompleted command execution only at execution of hardware or software reset When the BSY bit is 1 or the DRQ bit is 1 the device is requesting the data transfer and the host system writes to the command register the correct device operation is not gu
151. tor 3 2 2 1 1 om om MPA3043AT Model MPA3052AT Model Spindle Actuator Spindle Actuator 4 gt DNE 01 o EN Sh 3 Spindle motor The disks are rotated by a direct drive Hall less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays in the specific CSS zone on the disk and Figure 2 2 Configuration of disk media heads is fixed by a mechanical lock C141 E034 02EN 5 Air circulation system The disk enclosure DE is sealed to prevent dust and dirt from entering The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure 6 Read write circuit The read write circuit uses a LSI chip for the read write preamplifier It improves data reliability by preventing errors caused by external noise 7 Controller circuit The controller circuit consists of an LSI chip to improve reliability high speed microprocessor unit MPU achieves a h
152. ts 1F74 CM 97 or X E3 1F5g CH XX 1F44 CL XX 1F3y SN XX 1F2y SC Period of timer 1F1y FR XX C141 E034 02EN At command completion 1 registers contents to be read oe 07 _ 1 5 1F44 CL XX 1F3y SN XX 1F2y SC XX 1 15 Error information 23 IDLE IMMEDIATE 95 or X E1 Upon receipt of this command the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance I O registers setting contents 1F74 CM X 95 or X EI man 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F14 FR At command completion I O registers contents to be read mam T x oe 7 1 5 1F44 CL XX 1F3y SN XX 1F2y SC XX 1 15 Error information C141 E034 02EN 5 43 24 25 STANDBY 96 or X E2 Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the standby mode If the device has already spun down the spin down sequence is not implemented If the contents of the Sector Count register is other than 0 the automatic power down function is enabled and the timer starts countdown when the device returns to idle mode
153. ts the LBA mode When the host system specifies the LBA mode by setting bit 6 in the Device Head register to 1 HS3 to HSO bits of the Device Head register indicates the head No under the LBA mode and all bits of the Cylinder High Cylinder Low and Sector Number registers are LBA bits The sector No under the LBA mode proceeds in the ascending order with the start point of LBAO defined as follows LBAO z Cylinder 0 Head 0 Sector 1 Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command the sector LBA address is not changed LBA Cylinder No x Number of head Head No x Number of sector track Sector No 1 I O registers Communication between the host system and the device is done through input output I O registers of the device These I O registers can be selected by the coded signals 50 CS1 and DAO to DA2 from the host system Table 5 2 shows the coding address and the function of I O registers C141 E034 02EN Table5 2 I O registers cso csi DA2 DAI DAO perdue Command block registers b de d de o e nem mtm nnm Dh de fof emm nme b de p de omero eme onmes b de p f pos ee RT dx p T pm Ts b Tb Notes 1 Data regis
154. urface mounting mountme PCA B Frame of system cabinet cabinet Bo Frame of system LS 4 5 or less Screw 5 Senes 5 Screw Details of A Details of B Figure3 4 Mounting frame structure 3 4 C141 E034 02EN 4 Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive Pay attention to the air flow to prevent the DE surface temperature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure3 5 Surface temperature measurement points Table 3 1 Surface temperature measurement points and standard values C141 E034 02EN 3 5 5 Service area Figure 3 6 shows how the drive must be accessed service areas during and after installation Mounting screw hole E Q side Mounting screw hole P side Cable connection Mode setting switches R side Mounting screw hole Figure 3 6 Service area 6 External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by
155. wer supply Disk Drive 1 Figure 3 8 Cable connections 3 8 C141 E034 02EN 3 3 4 Power supply connector CN1 Figure 3 9 shows the pin assignment of the power supply connector CN1 1 12VDC 2 12V RETURN 9099 Hem 4 5VDC Viewed from cable side Figure 3 9 Power supply connector pins CN1 3 4 Jumper Settings 3 41 Location of setting jumpers Figure 3 10 shows the location of the jumpers to select drive configuration and functions CNI C01 Power supply connector C04 B01 B01 02 Mode setting Connector pins B05 A01 Interface Connector A39 O O A40 Figure 3 10 Jumper location 141 034 02 3 4 Factory default setting Figure 3 11 shows the default setting position at the factory B02 06 A02 A40 C01 O c euo e OO 01 A39 B01 05 Figure 3 11 Factory default setting 3 4 3 Jumper configuration 1 Device type Master device device 0 or slave device device 1 is selected B02 06 B02 06 OJO O OIO O OJO O OIO O B01 05 B01 05 a Master device b Slave device Figure 3 12 Jumper setting of master or slave device 2 Cable Select CSEL In Cable Select mode the device can be configured either master device o
156. wing commands The device transfers data from the data buffer to the host system at issuance of following command if following data exist in the data buffer sectors to be processed by the command A part of data including load sector to be processed by the command When a part of data to be processed exist in the data buffer remaining data are read from the medium and are transferred to the host system Commands that are object of caching operation Follow commands are object of caching operation READ SECTOR S READ MULTIPLE READ DMA When caching operation is disabled by the SET FEATURES command no caching operation is performed Data that are object of caching operation Follow data are object of caching operation 1 2 3 Read ahead data read from the medium to the data buffer after completion of the command that are object of caching operation Data transferred to the host system once by requesting with the command that are object of caching operation except for the cache invalid data by some reasons Remaining data in the data buffer for write command transferred from the host system by the command that writes data onto the disk medium such as the WRITE SECTOR S WRITE DMA WRITE MULTIPLE Followings are definition of in case that the write data is treated as a cache data However since the hit check at issuance of read command is performed to the data buffer for read command priority caching write
157. y the interrupt generated periodically compares with the target revolution speed then flows the current into the motor coil according to the differentiation aberration Driver circuit The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor VCM current sense resistor CSR This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back C141 E034 02EN 4 7 2 1 2 3 4 7 3 Data surface servo format Figure 4 8 describes the physical layout of the servo frame The three areas indicated by 1 to 3 in Figure 4 8 are described below Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops and the rotational speed of the spindle can be controlled on this cylinder area for head moving Data area This area is used as the user data area SA area Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving Servo frame format As the servo information the drive uses the two phase servo generated from the gray code and servo A to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo frame consists of 5 blocks write read rec
158. y this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder whole cylinders from most inner to most outer cylinder are divided into 12 partitions at calibration in the factory and the compensation data is measured for representative cylinder of each partition This measured value is stored in the SA area The compensation value at self calibration is calculated using the value in the SA area C141 E034 02EN 4 5 20 Execution timing of self calibration Self calibration is executed when The power is turned on The disk drive receives the RECALIBRATE command from the host The self calibration execution timechart of the disk drive specifies self calibration The disk drive performs self calibration according to the timechart based on the time elapsed from power on The timechart is shown in Table 4 1 After power on self calibration is performed about every five or ten minutes for the first 60 minutes or six RECALIBRATE command executions and about every 30 minutes after that Table 4 1 Self calibration execution timechart eset TT TN EE 7 About 10 minutes About 20 minutes About 10 minutes About 30 minutes About 30 minutes About 60 minutes um 4 5 3 processing during self calibration If the disk drive receives a command execution request from the host while executing self calibration according

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