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Fujitsu MHN2200AT User's Manual

1. 3 1 3 1 Dimensions 3 2 3 2 Mounting 3 3 3 3 Cable Connections 3 9 3 3 1 Device connector 3 9 3 3 2 Cable connector specifications 3 10 3 3 3 Device connection 3 10 3 34 Power supply connector 3 11 3 4 Jumper Settings 3 11 3 4 1 Location of setting jumpers 3 11 3 4 2 Factory default setting 3 12 3 4 3 Master drive slave drive setting 3 12 3 4 4 CSELsetting 3 13 Theory of Device Operation 4 1 4 Outline 4 2 4 2 Subassemblies 4 2 421 Disk 4 2 4 2 2 Head 4 2 4 2 3 Spindle 4 3 4 2 4 Actuator 4 3 4 2 5 Air filter 4 3 4 3 Circuit Configuration 4 4 4 4 Power on Sequence 4 7 4 5 Self calibration 4 8 4 5 1 Self calibration contents 4 8 4 5 2 Execution timing of self calibration 4 9 4 5 3 Command processing during self calibration 4 10 4 6 Read write Circuit 4 10 4 6 1 Read write preamplifier 4 10 C141 E120 02EN CHAPTER 5 C141 E120 02EN Contents 4 6 2 Write circuit 4 10 4 6 3 Readcircuit 4 13 4 6 4 Digital PLL circuit 4 14 4 7 Servo Control 4 15 4 7 1 Servo control circuit 4 15 4 7 2 Data surface servo format 4 18 4 7 3 Servo frame format 4 20 4 7 4 Actuator motor control 4 21 4 7 5 Spindle motor control 4 22 METI AC E E 5 1 5 1 Physical Interface 5 2 5 1 1 Interface signals 5 2 5 1 2 Signal assignment the connector 5 3 5 2 Logical Interf
2. lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt l4 i lt V Valid on this command t See the command descriptions 5 88 C141 E120 02EN 5 3 Host Commands Table 5 17 Command code and parameters 2 of 2 m l1 ILL v 1 v Lv v SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE jsecuriryeraseunir j v j v voy ev securrry ereeze Lock v p v jv v PsecummvsETPASSWORD J v j v voy ev Psgumvumock J vj j voy ev FLUSH CACHE V beviceconricuraTion v j v voy ev Invalid command rb lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt E lt V Valid on this command See the command descriptions C141 E120 02EN 5 89 Interface 5 4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command If BSY bit is 1 the host should wait for issuing a command until BSY bit is cleared to 0 Commands can be executed only when the DRDY bit of the Status register is 1 However the following commands can be executed even if DRDY bit is 0 e EXECUTE DEVICE DIAGNOSTIC e INITIA
3. Data TTTTTTTTTTTTI transfe Trasnfers dummy data The host should receive 512 byte dummy data or release the DRQ set state by resetting Figure 5 4 Protocol for command abort 5 4 2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive e WRITE SECTOR S e WRITE LONG e WRITE BUFFER e WRITE VERIFY e SMART WRITE LOG SECTOR e SECURITY DISABLE PASSWORD e SECURITY ERASE UNIT e SECURITY SET PASSWORD e SECURITY UNCLOK 5 92 C141 E120 02EN 5 4 Command Protocol The execution of these commands includes the transfer one or more sectors of data from the host to the device In the WRITE LONG command 516 bytes are transferred Following shows the protocol outline a b c d e f g h i The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers The host writes a command code in the Command register The drive sets the BSY bit of the Status register When the device is ready to receive the data of the first sector the device sets DRQ bit and clears BSY bit The host writes one sector of data through the Data register The device clears the DRQ bit and sets the BSY bit When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive
4. Enables the READ BUFFER command Enables the WRITE BUFFER command Undefined Enables the Host Protected Area function Enables the DEVICE RESET command Enables the SERVICE interrupt Enables the release interrupt Enables the read cache function 5 37 Interface 5 38 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 14 WORD 86 Bits 15 14 Bit 13 10 Bit 9 Bit 8 Bits 7 6 Bit 5 Bit 4 Bit 3 Bits 2 0 15 WORD 87 Bits 15 3 Bit 2 Bit 1 0 16 WORD 88 Bit 15 8 Bit 7 0 Enables the write cache function Enables the P PACKET command set Enables the Power Management function Enables the Removable Media function Enables the Security Mode function Enables the SMART function Reserved Same definition as WORD 83 Enables the Automatic Acoustic Management function Enables the SET MAX Security extending function Same definition as WORD 83 Enables the Power Up In Standby function 2 Enables the Removable Media Status Notification function 2 Enables the Advanced Power Management function Same definition as WORD 83 Reserved Enables the Media Serial Number Same definition as WORD 84 Currently used Ultra DMA transfer mode Supportable Ultra DMA transfer mode Bit 5 1 Supports the Mode 5 Bit 4 1 Supports the Mode 4 Bit 3 1 Supports the Mode 3 Bit 2
5. 1 5 Acoustic Noise Table 1 5 lists the acoustic noise specification Table 1 5 Acoustic noise specification Sound Pressure e Idle mode DRIVE READY 24 dBA typical at 1 m Measure the noise from the cover top surface Note 1 6 Shock and Vibration Table 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Vibration Swept sine 1 4 octave per minute Operating 5 to 400 Hz 9 8m s 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s 0 peak 5G 0 peak Non operating no damage Shock half sine pulse Operating 1715 m s 0 peak 175G 0 peak 2ms duration without non recovered errors 7840 m s 0 peak 800G 0 peak 2ms duration Non operating 1176 m s 0 peak 120G 0 peak 11ms duration no damage 1 8 C141 E120 02EN 1 7 Reliability 1 7 Reliability 1 Mean time between failures MTBF Conditions of 300 000 h jH Power on time 250H month or less 3000H years or less Operating time 20 or less of power on time Power on off 1 day or more needed Environment 5 to 55 C 8 to 9096 But humidity bulb temperature 29 C or less MTBF is defined as follows Total operation time in all fields MTBF H number of device failure in all fields 1 Disk drive defects refers to defects that involve repair readjustment or replacement Disk drive defects do not include failures caused by external factors s
6. 1F2 SC xx IFL FR COh C1h C2h C3h At command completion I O register contents men a Ps Ps ov 1F5 T C141 E120 02EN 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information DEVICE CONFIGURATION RESTORE FR C0h The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command After execution of this command the settings are kept for the device power down or reset If a Host Protected Area has been set by a SET MAX ADDRESS command or if DEVICE CONFIGURATION FREEZE LOCK is set an aborted error is posted DEVICE CONFIGURATION FREEZE LOCK FR Cth The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition is cleared by a power down not cleared by a hardware or software reset Interface If the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power up an aborted error is posted DEVICE
7. At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 5 End cylinder No MSB LBA 1F4 CL End cylinder No LSB LBA IF3 SN End sector No LBA LSB 1F2 SC 00 1 1F1 Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 4 READ VERIFY SECTOR S X40 or X 41 This command operates similarly to the READ SECTOR S command except that the data is not transferred to the host system After all requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified If an unrecoverable error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder the head and the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred The Sector Count register indicates the number of sectors that have not been verified C141 E120 02EN 5 21 Interface At command issuance I O registers setting contents 1F7 CM 0 1 0 0 0 0 0 R 1F6 DH Start head No LBA MSB 1F5 CH Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1
8. C141 E120 02EN 5 121 Interface 5 6 3 8 Sustained Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes HSTROBE at host tovuic tovs tovsic DD 15 0 at host HSTROBE at device DD 15 0 S darc XXXXXXXO XXXXXXX Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 17 Sustained Ultra DMA data out burst 5 122 C141 E120 02EN 5 6 Timing 5 6 3 9 Device pausing an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes tre DMARQ device DMACK host STOP host DDMARDY device tRrs HSTROBE x X i host 0150 KX XX XX XK XXXXXXX host Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t after DDMARDY is negated 2 After negating DDMARDY the device may receive zero one two or three more data words from the host Figure 5 18 Device pausing an Ultra DMA data out burst C141 E120 02EN 5 123 Interface 5 6 3 10 Host terminating an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMAC
9. At command issuance I O registers setting contents 1F6 OH Start head No LBA MSB 1 5 CH 1 4 CL 1F3 SN 1F2 SC 1F1 FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count XX At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1 5 184 CL 1F3 SN 1F2 SC 1 1 End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 1x x X 0 to This command performs the calibration Upon receipt of this command the device sets BSY bit of the Status register and performs a calibration When the device completes the calibration the device updates the Status register clears the BSY bit and generates an interrupt This command can be issued in the LBA mode C141 E120 02EN 5 27 Interface At command issuance I O registers setting contents iro bi Cee 1F5 FS 1F4 CL 1F3 SN 1F2 SC IF1 FR At command completion I O registers contents to be read IIS 1F5 ap 1F4 CL XX 1F3 SN XX IF2 SC XX 1F1 ER Error information Note Also executable in LBA mode 10 SEEK X 7x X 0 to This command performs a s
10. GND reserved IOCS16 PDIAG CBLID DA2 CS1 GND 5 VDC unused 5 3 Interface signal ENCSEL MSTR RESET DATA 0 15 DIOW STOP DIOR HDMARDY HSTROBE INTRQ Description This signal is used to set master slave using the CSEL signal pin 28 Pins BandD Open Sets master slave using the CSEL signal is disabled Short Sets master slave using the CSEL signal is enabled MSTR I Master slave setting Pin A B C D open Master setting Pin A B Short Slave setting Reset signal from the host This signal is low active and is asserted for a minimum of 25 us during power on Sixteen bit bi directional data bus between the host and the device These signals are used for data transfer Signal asserted by the host to write to the device register or data port DIOW must be negated by the host before starting the Ultra DMA transfer The STOP signal must be negated by the host before data is transferred during the Ultra DMA transfer During data transfer in Ultra DMA mode the assertion of the STOP signal asserted by the host later indicates that the transfer has been suspended Read strobe signal from the host to read the device register or data port Flow control signal for Ultra DMA data In transfer READ DMA command This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer The host can negate the HDM
11. Start 0 rpm to Drive Read e Stop at Power Down ATA 5 Max Cable length 0 46 m Data Transfer Rate To From Media 17 4 to 30 7 MB s To From Host 100 MB s Max U DMA mode 5 Physical Dimensions 9 5 mm x 100 0 mm x70 0 mm Height x Width x Depth Capacity under the LBA mode 1 4 C141 E120 02EN 1 3 Power Requirements Under the CHS mode normal BIOS specification formatted capacity number of cylinders number of heads and number of sectors are as follows Table 1 1 Specifications 2 2 No of Cylinder No of Heads No of Sectors MHN2300AT 845 GB 16 383 63 MHN2200AT 8 45 GB 16 383 63 MHN2150AT 845 GB 16 383 63 MHN2100AT 845 GB 16 383 63 1 2 2 Model and product number Table 1 2 lists the model names and product numbers of the MHN Series Table 1 2 Model names and product numbers Model Name Capacity Mounting screw Order No user area MHN2200AT CA05456 B131 MHN2150AT CA05456 B021 MHN2100AT CA05456 B121 1 3 Power Requirements 1 Input Voltage 5V 45 2 Ripple 1 100 mV peak to peak C141 E120 02EN 1 5 Device Overview 3 Current Requirements and Power Dissipation Table 1 3 lists the current and power dissipation typical Table 1 3 Current and power dissipation LE ME Energy 0 025 W GB Efficiency 4 rank E MHN2300AT 0 025 W GB rank E MHN2200AT 0 050 W GB rank D MHN2150AT 0 050 W GB rank D MHN2100AT Current at
12. X 2 2 2 xm 5 3 Host Commands Table 5 3 Command code and parameters 2 of 2 Command code Bit Parameters used DERE E Command name STANDBY IMMEDIATE we EHE ISMART 1 0 1 1 0 0 mu IEEE SECURITY ERASE UNIT EXESEZEJESESESET SECURITY FREEZE LOCK Eira 1 1 SECURITY SET PASSWORD 1 1 1 1 1 securnyuntock peviceconicurarion 1 Notes Z T 21212 2 2 2 2 2 2 FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sector Number Register Retry at error 2 Without retry 0 With retry Y Necessary to set parameters C141 E120 02EN 5 15 Interface Y Necessary to set parameters under the LBA mode Not necessary to set parameters The parameter is ignored if it is set N May set parameters D device parameter is valid and the head parameter is ignored D The command is addressed to the master device but both the master device and the slave device execute it X Do not care 5 3 2 Command descriptions The contents of the I O registers to be necessary for issuing a command and the example indication of the I O registers at command completion are shown as following in this subsection Example READ SECTOR S At command issuance I O registers s
13. XX After power on the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode At command completion I O registers contents to be read Px Tx Px pepe 1F5 en 1F4 CL 1F3 SN 1F2 SC 1F1 ER 16 SET MAX F9 XX XX Sector count block Error information SET MAX Features Register Values Value Command 00h Obsolete Olh SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET MAX UNLOCK 04h SET MAX FREEZE LOCK 056 FFh Reserved C141 E120 02EN 5 45 Interface e SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command This command allows the maximum address accessible by the user to be set in LBA or CHS mode Upon receipt of the command the device sets the BSY bit and saves the maximum address specified in the DH CH CL and SN registers Then it clears BSY and generates an interrupt The new address information set by this command is reflected in Words 1 54 57 58 60 and 61 of IDENTIFY DEVICE information If an attempt is made to perform a read or write operation for an address beyond the new address space an ID Not Found error will result When SC register bit 0 VV Value Volatile is 1 the value set by this command is held even after power on and the occurrence of a hard reset When the VV bit is 0 the value set by this command becomes invalid when the power is turned on o
14. 4 7 Servo Control Servo frame 120 servo frames per revolution Diameter direction Circumference Direction Erase DC erase area Figure 4 8 Physical sector servo configuration on disk surface C141 E120 02EN 4 19 Theory of Device Operation 4 7 3 Servo frame format As the servo information the IDD uses the two phase servo generated from the gray code and servo A to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo frame consists of 6 blocks write read recovery servo mark gray code servo A to D and PAD Figure 4 9 shows the servo frame format Write read recovery Servo B Servo A Gray code Figure 4 9 Servo frame format 4 20 C141 E120 02EN 4 7 Servo Control 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark This area generates a timing for demodulating the gray code and position demodulating the servo A to D by detecting the servo mark 3 Gray code including index bit This area is used as cylinder address The data in this area is converted into the binary data by the gray code demodulation circuit 4 Servo A servo B servo C servo D This area is used as position signals between tracks and the IDD control at on track so that servo A level equals to servo B level 5 PAD This area is used as
15. CL 1F3 SN 1F2 SC 1F1 ER C141 E120 02EN XX XX X 00 or X FF Error information 5 63 Interface 29 SMART X B0 5 64 This command performs operations for device failure predictions according to a subcommand specified in the FR register If the value specified in the FR register is supported the Aborted Command error is posted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is enabled The device collects or updates several items to forecast failures In the following sections the values of items collected or updated by the device to forecast failures are referred to as attribute values C141 E120 02EN 5 3 Host Commands Table 5 7 Features Register values subcommands and functions 1 of 3 Features Resister Function X DO SMART Read Attribute Values A device that received this subcommand asserts the BSY bit and saves all the updated attribute values The device then clears the BSY bit and transfers 512 byte attribute value information to the host For information about the format of the attribute value information see Table 5 8 SMART Read Attribute Thresholds This subcommand is used to transfer 512 byte insurance failure threshold value data to the host Forinformation about
16. DOh SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register 2 DAh to save the device attribute value data on a medium Alternative the device must issue the SMART Enable Disable Attribute AutoSave subcommand FR register 2 D2h to use a feature which regularly save the device attribute value data to a medium The host can predict failures in the device by periodically issuing the SMART Return Status subcommand FR register DAh to reference the CL and CH registers If an attribute value is below the insurance failure threshold value the device is about to fail or the device is nearing the end of its life In this case the host recommends that the user quickly backs up the data At command issuance I O registers setting contents 1 5 Key C2h 1FA CL Key 4Fh 1F3 SN XX 1F2 SC XX 1F1 FR Subcommand C141 E120 02EN 5 67 Interface At command completion I O registers setting contents 1F5 CH Key failure prediction status C2h 2Ch 1F4 CL Key failure prediction status 4Fh F4h 1F3 SN XX IF2 SC XX 1F1 ER Error information The attribute value information is 512 byte data the format of this data is shown the following table 5 8 The host can access this data using the SMART Read Attribute Values subcommand FR register DOh The insurance failure threshold value data is 512 byte data the format of this data is shown the followin
17. Figure 5 16 Figure 5 17 Figure 5 18 Figure 5 19 Figure 5 20 Figure 5 21 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 1 5 Table 1 6 Table 3 1 Table 3 2 Table 4 1 C141 E120 02EN Contents Execution example of READ MULTIPLE command 5 19 Read Sector s command protocol 5 91 Protocol for command abort 5 92 WRITE SECTOR S command protocol 5 94 Protocol for the command execution without data transfer 5 95 Normal DMA data transfer 5 98 Ultra DMA termination with pull up or pull down PIO data transfer timing 5 111 Multiword DMA data transfer timing mode 2 Initiating an Ultra DMA data in burst 5 113 Sustained Ultra DMA data in burst 5 117 Host pausing an Ultra DMA data in burst 5 118 Device terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst Initiating an Ultra DMA data out burst 5 121 Sustained Ultra DMA data out burst 5 122 Device pausing an Ultra DMA data out burst Host terminating an Ultra DMA data out burst Device terminating an Ultra DMA data out burst 5 110 5 112 5 119 5 120 5 123 5 124 5 125 Power on Reset Timing 5 126 Response to power on 6 3 Response to hardware reset 6 4 Response to software reset 6 5 Response to diagnostic command 6 6 Sector slip processing 6 10 Alternate cylinder assignment 6 11 Data buffer configuration 6 12 Specifications 1 4 Model names and produc
18. Hostterminating an Ultra DMA data out burst C141 E120 02EN The following stops shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 10 and 5 6 3 2 for specific timing requirements 1 2 3 4 5 7 8 9 10 11 12 The host shall initiate termination of an Ultra burst by not generating HSTROBE edges The host shall assert STOP no sooner than t after it last generated an HSTROBE edge The host shall not negate STOP again until after the Ultra DMA burst is terminated The device shall negate DMARQ within t after the host asserts STOP The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The device shall negate DDMARDY with t after the host has negated STOP The device shall not assert DDMARDY again until after the Ultra DMA burst termination is complete If HSTROBE is negated the host shall assert HSTROBE with t after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than t after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than t after placing the result of its CRC calculati
19. Security enabled 2 Security supported The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Features register Then the device clears the BSY bit and generates an interrupt If the value in the Features register is not supported or it is invalid the device posts an ABORTED COMMAND error Table 5 5 lists the available values and operational modes that may be set in the Features register C141 E120 02EN 5 3 Host Commands Table 5 5 Features register values and settable modes Features Drive operation mode Register X 85 Disables the advanced power management function X AA Enables the read cache function X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands 2 Enables the reverting to power on default settings after software reset At power on or after hardware reset the default mode is set as follows Disables the Acoustic management function Disables the write cache function Write cashe function Enabled Transfer mode PIO Mode 4 Multiworld DMA Mode 2 Advanced power management function Enabled Mode 1 Acoustic management function Disabled Standard Seek Read cashe function Enabled Default setting after software reset Disabl
20. T T L H L OL H H L H CylinderHigh CylinderHigh L H X L Invalid Invalid Ix d Control block registers Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATAO to DATAI5 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATAO to DATA7 3 When reading the Drive Address register bit 7 is high impedance state 4 H indicates signal level High and L indicates signal level Low And the LBA mode is specified the Device Head Cylinder High Cylinder Low and Sector Number registers indicate LBA bits 27 to 24 23 to 16 15 to 8 and 7 to 0 C141 E120 02EN 5 7 Interface 5 2 2 Command block registers 1 Data register X 1F0 The Data register is a 16 bit register for data block transfer between the device and the host system Data transfer mode is PIO or DMA mode 2 Error register X 1F1 The Error register indicates the status of the command executed by the device The contents of this register are valid when the ERR bit of the Status register is 1 This register contains a diagnostic code after power is turned on a reset or the EXECUTIVE DEVICE DIAGNOSTIC command is executed Status at the completion of command execution other than diagnostic command X Unused Bit 7 Interface CRC Error ICRC This bit indicates that a CRC erro
21. The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed C141 E120 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F7 CM 1 1 1 1 0 0 1 1F5 CH xx 1F4 CL xx 1F2 SC IF1 FR At command completion I O registers contents to be read 1F6 DH 185 xx 1F4 CL xx IFA SN xx 1F2 SC xx 17 READ NATIVE MAX ADDRESS F8 This command posts the maximum address intrinsic to the device which can be set by the SET MAX ADDRESS command Upon receipt of this command the device sets the BSY bit and indicates the maximum address in the DH CH CL and SN registers Then it clears BSY and generates an interrupt At command issuance I O registers setting contents 1F7 CM 1 1 1 1 1 0 0 0 1F5 CH XX 1F4 CL XX 1F3 SN XX IF2 SC XX 1F1 FR XX C141 E120 02EN 5 51 Interface At command completion I O registers contents to be read 1F6 DH Max head LBA MSB 1F5 CH Max cylinder MSB Max LBA 1F4 CL Max cylinder LSB Max LBA 1F3 SN Max sector Max LBA LSB IF2 SC XX 1F1 ER Error information 18 EXECUTE DEVICE DIAGNOSTIC X 90 5 52 This command performs an internal diagnostic test self diagnosis of the device This command usually sets the DRV bit of the Drive Head register is to 0 however the DV bit is not checked If two devices are present bo
22. V Clear Reset Master device tN 4 BOX 2 Slave device poi TRE Time from RESET negation to BSY set 400 ns Time from RESET negation to DASP or DIAG negation sat diagnostics execution time Time from RESET negation to DASP assertion slave le 15 Duration of DASP assertion Figure 5 21 Power on Reset Timing 5 126 C141 E120 02EN CHAPTER 6 Operations 6 1 Device Response to the Reset 6 2 Power Save 6 3 Defect Management 6 4 Read Ahead Cache 6 5 Write Cache C141 E120 02EN Operations 6 1 Device Response to the Reset This section describes how the PDIAG and DASP signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command 6 1 1 Response to power on 6 2 After the master device device 0 releases its own power on reset state the master device shall check a DASP signal for up to 450 ms to confirm presence of a slave device device 1 The master device recognizes presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 r
23. sectors To specify 256 sectors reading 00 is specified For INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the device performs an implied seek After the head reaches to the specified track the device reads the target sector If an error occurs retry reads are attempted to read the target sector before reporting an error irrespective of the R bit setting The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition Upon the completion of the command execution command block registers contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an unrecoverable error occurs in a sector the read operation is terminated at the sector where the error occurred Command block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical block address in the LBA mode where the error occurred and remaining number of sectors of which data was not transferred C141 E120 02EN 5 17 Interface At command issuance I O registers setting contents 1F6 JOH PIE Start head No LBA MSB 5 Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA IF3 SN Start sector No LBA LSB 1F2 SC Transfer sector count FR XX R
24. 02EN 5 3 Host Commands 20 WRITE LONG X 32 or X33 This command operates similarly to the READ SECTOR S command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium The device does not generate ECC bytes by itself The WRITE LONG command supports only single sector operation The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command This command is operated under the following conditions e READ LONG issued WRITE LONG Same address issues sequence After READ LONG is issued WRITE LONG can be issued consecutively If above condition is not satisfied the WRITE LONG Data becomes the Uncorrectable error for subsequence READ command At command issuance I O registers setting contents 1F7 CM 0 0 1 1 0 0 1 R 1F6 DH Head No LBA MSB 1F5 CH Cylinder No MSB LBA 1F4 CL Cylinder No LSB LBA 1F3 SN Sector No LBA LSB 1F2 SC 01 IFL FR At command completion I O registers contents to be read 1F6 DH Head No LBA MSB IF5 CH Cylinder No MSB LBA 1F4 CL Cylinder No LSB LBA 1F3 SN Sector No LBA LSB 1F2 SC 00 1 1F1 ER Error information Ifthe command is terminated due to an error this register indicates 01 C141 E120 02EN 5 55 Interface 21 READ BUFFER X E4 The host system can read the current contents of t
25. 1 2 3 4 5 The device shall initiate termination of an Ultra DMA burst by not generating DSTROBE edges The device shall negate DMARQ no sooner than t after generating the last DSTROBE edge The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The device shall release DD 15 0 no later than t after negating DMARQ T he host shall assert STOP within t after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated T he host shall negate HDMARDY within t after the device has negated The host shall continue to negate HDMARDY until the Ultra MA burst is terminated Steps 4 and 5 may occur at the same time D D C141 E120 02EN b C141 E120 02EN 6 7 8 9 10 11 12 13 14 5 5 Ultra DMA Feature Set The host shall drive DD 15 0 no sooner than t after the device has negated DMARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 If DSTROBE is negated the device shall assert DSTROBE within tj after the host has asserted STOP No data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra DMA burst is terminated If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 6
26. 5 Write Cache The drive uses a cache data of the last write command as a read cache data When a read command is issued to the same address after the write command cache hit the read operation to the disk medium is not performed If an error occurs during the write operation the device retries the processing If the error cannot be recovered by retry automatic alternate assignment is performed For details about automate alternate assignment see item 3 of Section 6 4 2 The write cache function is operated with the following command C141 E120 02EN WRITE SECTOR S WRITE MULTIPLE WRITE DMA IMPORTANT When Write Cache is permitted the writing of the data transferred from the host by the above mentioned Write Cache permit command into the disk medium may not be completed at the moment a normal ending interrupt has occurred In case a non recoverable error has occurred during receiving more than one write command it is difficult for the host to identify a command that caused the error However the error is not reported to the hose if an error at writing has been processed normally Therefore note that it is difficult for the host to retry an operation that caused a non recoverable error 6 21 This page is intentionally left blank Glossary Actuator Head positioning assembly The actuator consists of a voice coil motor and head arm If positions the read write R W head AT bus A bus between the host CPU
27. 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 5 1 Illustrations Current fluctuation Typ at 5V when power is turned on 1 7 Disk drive outerview 2 2 Configuration of disk media heads 2 3 1 drive system configuration 2 4 2 drives configuration 2 4 Dimensions 3 2 Orientation 3 3 Mounting frame structure 3 4 Location of breather 3 5 Surface temperature measurement points 3 6 Service area 3 7 Handling cautions 3 8 Connector locations 3 9 Cable connections 3 10 Power supply connector pins CN1 3 11 Jumperlocation 3 11 Factory default setting 3 12 Jumper setting of master or slave drive 3 12 CSEL setting 3 13 Example 1 of Cable Select 3 13 Example 2 of Cable Select 3 14 Head structure 4 3 Power Supply Configuration 4 5 Circuit Configuration 4 6 Power on operation sequence 4 8 Read write circuit block diagram 4 12 Frequency characteristic of programmable filter 4 13 Block diagram of servo control circuit 4 15 Physical sector servo configuration on disk surface 4 19 Servo frame format 4 20 Interface signals 5 2 C141 E120 02EN Tables Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15
28. 94 C141 E120 02EN 5 4 Command Protocol SEEK READY VERIFY SECTOR S EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE SET MAX ADDRESS READ NATIVE MAX ADDRESS IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE MART DISABLE OPERATION MART ENABLE DISABLE AUTOSAVE S S SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE S MART RETURN STATUS SECURITY ERASE PREPARE SECURITY FREEZE LOCK FLUSH CACHE Figure 5 6 shows the protocol for the command execution without data transfer Parameter write W Command V V V Status read E EN SEEN DRDY INTRQ T LL Figure 5 6 Protocol for the command execution without data transfer C141 E120 02EN 5 95 Interface 5 4 4 Other commands e READ MULTIPLE e SLEEP e WRITE MULTIPLE See the description of each command 5 4 5 DMA data transfer commands e READ DMA e WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR S or WRITE SECTOR S command except the point that the host initializes the DMA channel preceding the command issuance Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed The following outlines the protocol 5 96 C141 E120 02EN 5 4 Command Protocol The interrupt processing for the DMA transfer differs the following point a b d e g The interrupt p
29. CONFIGURATION IDENTIFY FR C2h The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure is shown in Table 5 16 The content of this data structure indicates the selectable commands modes and feature sets that the device 1s capable of supporting If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities the response to an IDENTIFY DEVICE command will reflect the reduced set of capabilities while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of selectable capabilities If the device has executed a previous DEVICE CONFIGURATION FREEZE LOCK command since power up an aborted error is posted DEVICE CONFIGURATION SET FR C3h The DEVICE CONFIGURATION SET command allows to reduce the set of optional commands modes or feature sets supported by a device as indicated by a DEVICE CONFIGURATION IDENTIFY command The format of the overlay transmitted by the device is described in Table 5 16 The DEVICE CONFIGURATION SET command transfers an overlay that modifies some of the bits set in words 63 82 83 84 and 88 of the IDENTIFY DEVICE command response When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit After execution of this command the settings
30. Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kQ or greater Do not touch the printed circuit board but hold it by the edges C141 E120 02EN This page is intentionally left blank Manual Organization MHN2300AT MHN2200AT Maintenance and Diagnosis MHN2150AT MHN2100AT Removal and Replacement Procedure DISK DRIVES MAINTENANCE MANUAL C141 E120 C141 E120 02EN vii This page is intentionally left blank CHAPTER 1 CHAPTER 2 C141 E120 02EN Contents Device 1 1 1 1 Features 1 2 1 1 1 Functions and performance 1 2 1 1 2 Adaptability 1 2 1 1 3 Interface 1 3 1 2 Device Specifications 1 4 1 2 1 Specifications summary 1 4 1 2 2 Model and product number 1 5 1 3 Power Requirements 1 5 1 4 Environmental Specifications 1 7 1 5 Acoustic Noise 1 8 1 6 Shock and Vibration 1 8 1 7 Reliability 1 9 1 8 Error Rate 1 10 1 9 Media Defects 1 10 1 10 Load Unload Function 1 10 Device GonfigurallODs iso diviso ta coco ge Raw curia DER Edge 2 1 2 Device Configuration 2 2 2 2 System Configuration 2 4 2 2 1 ATA interface 2 4 2 2 2 1 drive connection 2 4 2 2 3 2drivesconnection 2 4 Contents CHAPTER 3 CHAPTER 4 Installation Conditions
31. E120 02EN 5 4 Command Protocol words the host should receive the relevant sector of data 512 bytes of uninsured dummy data or release the DRQ status by resetting Figure 5 3 shows an example of READ SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort Command Parameter write v Status read Status read E bic i i DRDY T d f d Data Reg 1 Selection Word 0 1 2 255 IOCS16 4 When the IDD receives command that hits the cache data during read ahead transfers data from the buffer without reading from the disk medium Figure 5 3 Read Sector s command protocol IMPORTANT For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the C141 E120 02EN 5 91 Interface device to starting of the sector data transfer Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple sector reading If the timing to read the Status register does not meet above condition normal data transfer operation is not guaranteed When the host new command even if the device requests the data transfer setting in DRQ bit the correct device operation is not guaranteed W Command Parameter write V Status read V V 1 BSY M DRDY Jt DRO INTRQ
32. Line Immediate is supported Vendor unique Indicates that off line data collection being executed is aborted when a new command is received Indicates that supports off line read scan function Indicates that supports self test function e Failure prediction capability flag Bit 0 The attribute value data is saved to a media before the device enters power saving mode Bit 1 The device automatically saves the attribute value data to a media after the previously set operation Bits 2 to 15 Reserved bits Error logging capability Bit 0 Indicates that error logging function Bits 1 to 7 Reserved bits C141 E120 02EN 5 3 Host Commands e Check sum Two s complement of the lower byte obtained by adding 511 byte data one byte at a time from the beginning e Insurance failure threshold The limit of a varying attribute value The host compares the attribute values with the thresholds to identify a failure Table 5 10 Log Directory Data Format n SMART Logging Version Number of sectors of Address 01h Reserved Number of sectors of Address 06h Reserved Reserved 102 and 13F are both the same format as 100 101 Address 81h Address 9Fh Reserved 03 OB 0 Address 80h 102 13F 140 1FF SMART error logging If an unrecoverable error is detected during execution of a command received by the device from the host computer the device saves the SMART error log on the
33. Power on Sequence Self calibration Read write Circuit Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks C141 E120 02EN 4 1 Theory of Device Operation 4 1 Outline This chapter consists of two parts First part Section 4 2 explains mechanical assemblies of the disk drive Second part Sections 4 3 through 4 7 explains a servo information recorded in the disk drive and drive control method 4 2 Subassemblies 4 2 1 Disk 4 2 2 Head 4 2 The disk drive consists of a disk enclosure DE and printed circuit assembly PCA The DE contains all movable parts in the disk drive including the disk spindle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 5 The PCA contains the control circuits for the disk drive The disk drive has one PCA For details see Sections 4 3 The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm The MHN2300AT and MHN2200AT have two disks and MHN2150AT and MHM2100AT have one disk Servo data is recorded on each cylinder total 120 Servo data written at factory is read out by the read head For servo data see Section 4 7 Figure 4 1 shows the head structures MHN2300AT has 4 heads and MHN2200AT has 3 heads and MHN2150AT and MHN2100AT have 2 heads C141 E120 0
34. Table 3 2 Cable connector specifications To em ATA interface and power Cable socket 89361 144 BERG supply cable 44 pin type 44 pin type IMPORTANT For the host interface cable use a ribbon cable A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines This is because the interface is designed for ribbon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 9 shows how to connect the devices Disk Drive 0 Host system f Disk Drive 1 DC Power supply Figure 3 9 Cable connections 3 10 C141 E120 02EN 3 4 Jumper Settings 3 3 4 Power supply connector CN1 Figure 3 10 shows the pin assignment of the power supply connector CN1 5V RETURN Pin 43 Pin 1 5V DC Pin 41 42 viewed from connector side Figure 3 10 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 11 shows the location of the jumpers to select drive configuration and functions Pin 1 Pin 20 KEY viewed from connector side Figure 3 11 Jumper location C141 E120 02EN 3 11 Installation Conditions 3 4 2 Factory default setting Figure 3 12 shows the default setting position at the factory D Figure 3 12 Factory default setting 3 4 3 Master drive slave
35. a gap between servo and data 4 7 4 Actuator motor control The voice coil motor VCM is controlled by feeding back the servo data recorded on the data surface The MPU fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the target track 1 Operation to move the head to the reference cylinder The MPU moves the head to the reference cylinder when the power is turned The reference cylinder is in the data area When power is applied the heads are moved from the inner circumference shunt zone to the normal servo data zone in the following sequence a Micro current is fed to the VCM to press the head against the outer circumference b The head is loaded on the disk c When the servo mark is detected the head is moved slowly toward the inner circumference at a constant speed C141 E120 02EN 4 21 Theory of Device Operation d Ifthe head is stopped at the reference cylinder from there Track following control starts 2 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read write instruction is issued the MPU seeks the
36. alternate assignment the device performs rewriting the corrected data to the erred sector and rereading If no error occurs at rereading the automatic alternate assignment is not performed An unrecoverable write error occurs during write error retry automatic alternate assignment is performed 6 4 Read Ahead Cache After read command which involves read data from the disk medium is completed the read ahead cache function reads the subsequent data blocks automatically and stores the data to the data buffer C141 E120 02EN 6 11 Operations When the next command requests to read the read ahead data the data can be transferred from the data buffer without accessing the disk medium The host can thus access data at higher speed 6 4 1 Data buffer configuration The drive has a 2 MB data buffer The buffer is used by divided into three parts for read write commands and for MPU work see Figure 6 9 2048 KB for MPU works for read write commands 4 80KB v 1968 KB Figure 6 7 Data buffer configuration The read ahead operation is performed at execution of the READ SECTOR S READ MULTIPLE or READ DMA command and read ahead data is stored in the buffer for read write commands 6 4 2 Caching operation Caching operation is performed only at issuance of the following commands The device transfers data from the data buffer to the host system at issuance of following command if following data exist
37. are compensated by adding the measured value to the specified current value to the power amplifier This makes the stable servo control To compensate torque varying by the cylinder the disk is divided into 23 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored For sensing the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder whole cylinders from most inner to most outer cyl
38. are kept for the device power down or reset If the restriction of Multiword DMA modes or Ultra DMA modes is executed a SET FEATURES command should be issued for the modes restriction prior the DEVICE CONFIGURATION SET command is issued If a DEVICE CONFIGURATION SET command has already modified the original settings as reported by a DEVICE CONFIGURATION IDENTIFY command if DEVICE CONFIGURATION FREEZE LOCK is set if any of the bit modification restrictions described are violated or if a Host Protected Area has been established by the execution of a SET MAX ADDRESS command an aborted error is posted C141 E120 02EN 5 3 Host Commands Table 5 16 DEVICE CONFIGURATION IDENTIFY data structure Word Value Content 0 X 0001 Data structure revision 1 X 0007 Multiword DMA modes supported Bit 15 3 Reserved Bit 2 1 Multiword DMA mode 2 and below are supported Bit 1 1 Multiword DMA mode 1 and below are supported Bit 0 1 Multiword DMA mode 0 is supported 2 X 003F Ultra DMA modes supported Bit 15 6 Reserved Bit 5 1 Ultra DMA mode 5 and below are supported Bit 4 1 Ultra DMA mode 4 and below are supported Bit 3 1 Ultra DMA mode 3 and below are supported Bit 2 1 Ultra DMA mode 2 and below are supported Bit 1 1 Ultra DMA mode 1 and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 X 00CF Command set feature set supported Bit 15 9 Reserved Bit
39. by the edges 6 Handling cautions Please keep the following cautions and handle the HDD under the safety environment C141 E120 02EN 3 7 Installation Conditions General notes ESD mat Wrist strap Shock absorbing mat Use the Wrist strap i Place the shock absorbing mat on the operation table and place ESD mat on it Do not stack when carrying Do not place HDD vertically to avoid falling down Do not drop Figure 3 7 Handling cautions Installation 1 2 Please use the driver of a low impact when you use an electric driver HDD is occasionally damaged by the impact of the driver Please observe the tightening torque of the screw strictly 0 49 N m 5 Kg cm Recommended equipments Contents Model Maker ESD Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD mat SKY 8A Color Seiden Mat Achilles Shock Low shock driver SS 6500 HIOS 3 8 C141 E120 02EN 3 3 Cable Connections 3 3 Cable Connections 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 8 shows the locations of these connectors and terminals Connector setting pins Figure 3 8 Connector locations C141 E120 02EN 3 9 Installation Conditions 3 3 2 Cable connector specifications Table 3 2 lists the recommended specifications for the cable connectors
40. command codes This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written C141 E120 02EN 5 3 Host Commands 5 2 3 Control block registers 1 Alternate Status register X 3F6 The Alternate Status register contains the same information as the Status register of the command block register The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset or vs ore 2 Device Control register X 3F6 The Device Control register contains device interrupt and software reset x x px x x ser Bit 2 SRST is the host software reset bit When this bit is set the device is held reset state When two device are daisy chained on the interface setting this bit resets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state 5 3 Host Commands The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in t
41. cylinder number Under the LBA mode this register indicates LBA bits 15 to 8 7 Cylinder High register X 1F5 The contents of this register indicates high order 8 bits of the disk access start cylinder address At the end of a command the contents of this register are updated to the current cylinder number The high order 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 a maximum head No X Hs Hs1 0 Bit 7 Unused Bit 6 for CHS mode and 1 for LBA mode Bit5 Unused Bit 4 DEV bit 0 for the master device and 1 for the slave device Bit 3 HS3 CHS mode head address 3 2 LBA bit 27 Bit 2 HS2 CHS mode head address 2 2 LBA bit 26 Bit 1 HS1 CHS mode head address 1 2 LBA bit 25 Bit 0 HS0 CHS mode head address 0 2 LBA bit 24 5 10 C141 E120 02EN 5 2 Logical Interface 9 Status register X 1F7 The contents of this register indicate the status of the device The contents of this register are updated at the completion of each command When the BSY bit is cleared other bits in this register should be validated within 400 ns
42. disk medium The host computer can issue the SMART Read Log Sector sub command FR register D5h SN register 01h and read the SMART error log C141 E120 02EN 5 73 Interface Table 5 11 SMART error log data format 0 Error log 1 Command Data 1 Features register eic AJN Sector Count register Sector Number register Cylinder Low register Cylinder High register Device Head register Command register OA to OD Elapsed time ms from the point when the power is turned on until command reception OE to 3D Command Data 2 The format of each type of command to 5 data is the same as that of byte 02 to OD Error register alojo Sector Count register A Sector Number register A r3 Cylinder Low register A O2 Cylinder High register Error log 1 Error data Device Head register Status register 46 to 58 Vendor unique Status 5A 5B Total power on time hour 5C to 1C3 Error log 2 to The format of each error log is the same as Byte 02 to 5B Error log 5 1C4 1C5 Number of unrecoverable errors that have occurred 5 74 C141 E120 02EN 5 3 Host Commands e Error log index Indicates the latest error log number If an error has not occurred 00 is displayed e Error log 1 to 5 When an error occurs the error log index value is incremented and information at the time the error occurred is recorded in the error log area
43. external forces applied to the actuator and updates the calibrating value The drive becomes ready The host can issue commands C141 E120 02EN 4 7 Theory of Device Operation Self diagnosis 1 MPU bus test Internal register write read test Work RAM write read test The spindle motor starts b Self diagnosis 2 Data buffer write read test c Confirming spindle motor speed Load the head assembly Drive ready state command waiting state Figure 4 4 Power on operation sequence Initial on track and read out of system information Execute self calibration 4 5 Self calibration The disk drive occasionally performs self calibration in order to sense and calibrate mechanical external forces on the actuator and VCM torque This enables precise seek and read write operations 4 5 1 Self calibration contents 1 Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution The torque vary with the disk drive and the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current that balances the torque for stopping head stably This includes the current offset in the power amplifier circuit and DAC system 4 8 C141 E120 02EN 4 5 Self calibration The forces
44. immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges If the device does not negate DMARQ in order to initiate ULTRA DMA burst termination the host shall negate HOMARDY and wait t before asserting STOP The device shall resume an Ultra DMA burst by generating a DSTROBE edge b Host pausing an Ultra DMA data in burst 1 2 3 4 5 The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred The host shall pause an Ultra DMA burst by negating HDMARDY The device shall stop generating DSTROBE edges within t of the host negating HDMARDY If the host negates HOMARDY within t after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates greater than t after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and t timing for the device The host shall resume an Ultra DMA burst by asserting HDMARDY 5 5 3 4 Terminating an Ultra DMA data in burst 5 102 a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 5 and 5 6 3 2 for specific timing requirements
45. or disable caching 4 Sector Count register X 1F2 The Sector Count register indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request from the host system That is this register indicates the number of remaining sectors that the data has not been transferred due to the error The contents of this register has other definition for the following commands INITIALIZE DEVICE PARAMETERS SET FEATURES IDLE STANDBY and SET MULTIPLE MODE 5 Sector Number register X 1F3 The contents of this register indicates the starting sector number for the subsequent command The sector number should be between X 01 and the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command Under the LBA mode this register indicates LBA bits 7 to 0 C141 E120 02EN 5 9 Interface 6 Cylinder Low register X 1F4 The contents of this register indicates low order 8 bits of the starting cylinder address for any disk access At the end of a command the contents of this register are updated to the current
46. pio lash Digitizer MEEPR ServoPulse Viterbi Detector Detect Position A B C D to reg ao e RDGATE DATA RWCLK SRV SRV OUTT I 0 7 0 Figure 4 5 Read write circuit block diagram 4 12 C141 E120 02EN 4 6 Read write Circuit 4 6 3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control AGC circuit Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit This clock signal is converted into the NRZ data by the 16 17 GCR decoder circuit based on the read data maximum likelihood detected by the Viterbi detection circuit then is sent to the HDC 1 AGC circuit The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off frequency of the low pass filter and boost up gain are controlled from the register in read channel by an instruction of the serial data signal from MPU M5 The MPU optimizes the c
47. read retries of drive without user s retry and ECC corrections shall occur no more than 10 times when reading data of 10 bits Read retries are executed according to the disk drive s error recovery procedure and include read retries accompanying head offset operations 2 Positioning error Positioning seek errors that can be recovered by one retry shall occur no more than 10 times in 10 seek operations 1 9 Media Defects Defective sectors are replaced with alternates when the disk the MHN Series are formatted prior to shipment from the factory low level format Thus the hosts see a defect free devices Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors 1 10Load Unload Function The Load Unload function is a mechanism that loads the head on the disk and unloads the head from the disk The product supports a minimum of 300 000 normal Load Unload cycles Normal Unload is a normal head unloading operation and the commands listed below are executed Reset e Standby e Standby immediate e Sleep Idle e immediate 1 10 C141 E120 02EN 1 7 Reliability Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk The product supports the Emergency Unload a minimum of 20 000 times When the power is shut down the controlled Normal Unload cannot be
48. sets the DRQ bit After detecting the INTRQ signal assertion the host reads the Status register The device resets INTRQ the interrupt signal If transfer of another sector is requested steps d and after are repeated Figure 5 5 shows an example of WRITE SECTOR S command protocol C141 E120 02EN 5 93 Interface Parameter write WV Command Status read Status read VeV E V V f i i BSY TE a DRDY Bu Vu t Command v i DRQ je gt Max 1 us Data Reg Selection zi Data Word 0 1 2 255 IOCS16 Figure 5 5 WRITE SECTOR S command protocol IMPORTANT For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer Note that the host does not need to read the Status register for the first and the last sector to be transferred If the timing to read the Status register does not meet above condition normal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed 5 4 3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device e RECABLIBRATE 5
49. starting spindle motor 2 At30 disk accessing 3 Power requirements reflect nominal values for 5V power 4 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the value obtained by dividing power consumption by the storage capacity Japan only 5 seek average current is specified based on three operations per 100 msec 4 Current fluctuation Typ at 5V when power is turned on 1 6 C141 E120 02EN 1 4 Environmental Specifications 0 1 2 3 4 5 6 7 5 Figure 1 1 Current fluctuation Typ at 5 when power is turned on 5 Power on off sequence The voltage detector circuits the MHN Series monitor 5 V The circuits do not allow a write signal if either voltage is abnormal These prevent data from being destroyed and eliminates the need to be concerned with the power on off sequence 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Temperature Operating 5 C to 55 C ambient 5 C to 60 C disk enclosure surface Non operating 40 to 65 C Thermal Gradient 20 C h or less Humidity Operating 8 to 90 RH Non condensing Non operating 5 to 95 RH Non condensing Maximum Wet Bulb 29 C Operating 40 C Non operating Altitude relative to sea level Operating 300 to 3 000 m Non operating 300 to 12 000 m C141 E120 02EN 1 7 Device Overview
50. the PDIAG signal Master device Status Reg BSY bit Max 6 sec If the slave device is preset PDIAG signal is checked for up to6 seconds Slave device BSY bit se sd 4 1 ms 1 PDIAG CU pc s DASP 6 6 Max 5 sec gt 1 y Figure 6 4 Response to diagnostic command C141 E120 02EN 6 2 Power Save 6 2 Power Save The host can change the power consumption state of the device by issuing a power command to the device 6 2 1 Power save mode There are four types of power consumption state of the device including active mode where all circuits are active In the power save mode power supplying to the part of the circuit is turned off There are three types of power save modes Idle mode e Standby mode e Sleep mode Regardless of whether the power down is enabled the device enters the idle mode by itself The device also enters the idle mode in the same way after power on sequence is completed 1 Active mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions command other than power commands is issued e A reset command is received 2 Idle mode In this mode circuits on the device is set to power save mode The device enters the Idle mode under the following conditions
51. the Aborted Command error The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA READ LONG READ MULTIPLE READ SECTORS READ VERIFY SECTORS e WRITE DMA e SECURITY DISABLE PASSWORD e WRITE LONG e SECURITY FREEZE LOCK e WRITE MULTIPLE e SECURITY SET PASSWORD e WRITE SECTORS e SET MAX WRITE VERIFY e FLUSH CACHE At command issuance I O register contents 1F7 CM EGEONCUNCNE Dmes Ps Ts 1 5 m 1F4 CL 1F3 SN 1F2 SC 1F1 FR At command completion I O register contents mon a Ps Ps ove 1F5 E 1F4 CL 1F3 SN 1F2 SC 1F1 ER XX XX XX Error information C141 E120 02EN 5 3 Host Commands 34 SECURITY SET PASSWORD F1h This command enables a user password or master password to be set The host transfers the 512 byte data shown in Table 5 13 to the device The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data Table 5 14 Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted Command error Table 5 14 Contents of SECURITY SET PASSWORD data Control word Bit 0 Identifier 0 Sets a user password 1 Sets a master password Bits 1 to 7 Reserved Bit 8 Security level 0 High 1 Maximum Bits 9 to 15 Reserved Password 32 bytes Master password version nu
52. the format of the insurance failure threshold value data see Table 5 9 X DX SMART Enable Disable Attribute AutoSave This subcommand is used to enable SC register 00h or disable SC register 00h the setting of the automatic saving feature for the device attribute data The setting is maintained every time the device is turned off and then on When the automatic saving feature is enabled the attribute values are saved before the device enters the power saving mode However if the failure prediction feature is disabled the attribute values are not automatically saved When the device receives this subcommand it asserts the BSY bit enables or disables the automatic saving feature then clears the BSY bit XD3 SMART Save Attribute Values When the device receives this subcommand it asserts the BSY bit saves device attribute value data then clears the BSY bit X DE SMART Executive Off line Immediate A device which receives this command asserts the BSY bit then starts collecting the off line data specified in the SN register or stops In the off line mode after BSY is cleared off line data are collected In the captive mode it collects off line data with the BSY assertion as is then clears the BSY when collection of data is completed SN Off line data collection mode Off line diagnosis off line mode Simple self test off line mode Comprehensive self test off line mode Self test stop Simple self test captive mo
53. the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than t after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated and no sooner than t after the host places the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DSTROBE within t DMACK after the host negates The host shall not negate STOP no assert HOMARDY until at least t ox after negating DMACK The host shall not assert DIOR CSO CS1 DA2 DAI or DAO until at least after negating DMACK Host terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 6 and 5 6 3 2 for specific timing requirements 1 The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred 2 The host shall initiate Ultra DMA burst termination by negating HDMARDY The host shall continue to negate HDMARDY
54. tys after driving the first word of data onto DD 15 0 5 5 3 2 The data in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 3 and 5 6 3 2 for specific timing requirements 1 2 3 4 The device shall drive a data word onto DD 15 0 The device shall generate a DSTROBE edge to latch the new word no sooner than tys after changing the state of DD 15 0 The device shall generate a DSTROBE edge no more frequently than t for the selected Ultra DMA Mode The device shall not generate two rising or two falling DSTROBE edges more frequently than 21 for the selected Ultra DMA mode The device shall not change the state of DD 15 0 until at least 1 after generating a DSTROBE edge to latch the data The device shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first 5 5 3 3 Pausing an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 4 and 5 6 3 2 for specific timing requirements a C141 E120 02EN Device pausing an Ultra DMA data in burst 1 The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred 2 The device shall pause an Ultra DMA burst by not generating DSTROBE edges 5 101 Interface 3 NOTE The host shall not
55. until the Ultra DMA burst is terminated 3 The device shall stop generating DSTROBE edges within t of the host negating 4 Ifthe host negates within after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates greater than t 5 103 Interface 5 6 7 8 9 10 11 12 13 14 15 16 5 104 after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and t timing for the device The host shall assert STOP no sooner than t after negating HDMARDY The host shall not negate STOP again until after the Ultra DMA burst is terminated The device shall negate DMARQ within t after the host has asserted STOP The device shall not assert DMARQ again until after the Ultra DMA burst is terminated If DSTROBE is negated the device shall assert DSTROBE within t after the host has asserted STOP No data shall be transferred during this assertion The host shall ignore this transition on DSTROBE DSTROBE shall remain asserted until the Ultra DMA burst is terminated The device shall release DD 15 0 no later than t after negating DMARQ The host shall drive DD 15 0 no sooner than t after the device has negated DM
56. 01h 7Fh FFh Standard Seek Maximum performance Slow Seek Minimum acoustic emanation 15 SET MULTIPLE MODE X C6 5 44 This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands The block count number of sectors in a block for these commands are also specified by the SET MULTIPLE MODE command The number of sectors per block is written into the Sector Count register The IDD supports 2 4 8 16 and 32 sectors as the block counts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count register is 0 1 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the device clears the BSY bit and generates an interrupt C141 E120 02EN 5 3 Host Commands At command issuance I O registers setting contents iro bi RII IR 1F5 NS 1F4 CL 1F3 SN 1F2 SC IF1 FR XX XX Sector count block
57. 1 Note Since no bit clock is available the recommended approach for calculating CRC is to use a word clock derived from the bus strobe The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DDO is shifted in first and DD15 is shifted in last 5 5 6 Series termination required for Ultra DMA Series termination resistors are required at both the host and the device for operation in any of the Ultra DMA Modes The following table describes recommended values for series termination at the host and the device Table 5 17 Recommended series termination for Ultra DMA IORDY DDMARDY DSTROBE Note Only those signals requiring termination are listed in this table If a signal is not listed series termination is not required for operation in an Ultra DMA Mode For signals also requiring a pull up or pull down resistor at the host see Figure 5 8 Figure 5 8 Ultra termination with pull up or pull down 5 110 C141 E120 02EN 5 6 Timing 5 6 Timing 5 6 1 PIO data transfer Figure 5 9 shows of the data transfer timing between the device and the host system t0 gt Addresses tl t9 DIOR DIOW b e 2 ti Write data DD0 DD15 i t3 n r Read data DDO DD15 ES t6 IORDY t10 Ka tll 412 Gd o at Da
58. 1 Supports the Mode 2 Bit 1 1 Supports the Mode 1 Bit 0 1 Supports Mode 0 C141 E120 02EN 17 WORD 93 18 WORD 128 C141 E120 02EN Bits 15 14 Reserved Bit 13 Bits 12 8 Bits 7 0 Bit 15 9 Bit 8 Bit 7 6 Bit 5 5 3 Host Commands 1 CBLID is a level higher than Vin 0 CBLID is a level lower than Vi In the case of Device 1 slave drive a valid value is set Bit 12 Bit 11 Bit 10 9 Bit 8 Reserved Device asserts PDIAG Method for deciding the device No of Device 1 00 Reserved 01 Using a jumper 10 Using the CSEL signal 11 Other method Reserved In the case of Device master drive a valid value is set Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 1 Bit 0 Reserved Reserved Device 1 is selected Device 0 responds Device 0 assertion of DASP was detected Device 0 assertion of PDIAG was detected Device 0 an error was not detected in the self diagnosis Method for deciding the device No of Device 0 00 Reserved 01 Using a jumper 10 Using the CSEL signal 11 Other method Reserved Security level 0 High 1 Maximum Reserved Enhanced security erase supported 5 39 Interface 14 SET FEATURES X EF 5 40 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Security counter expired Security frozen Security locked
59. 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects Load Unload Function Overview and features are described in this chapter and specifications and power requirement are described The MHN Series are 2 5 inch hard disk drives with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable C141 E120 02EN 1 1 Device Overview 1 1 Features 1 1 1 Functions and performance The following features of the MHN Series are described 1 Compact The MHN2300AT MHN2200AT MHN2150AT and MHN2100AT have 1 disk or 2 disks of 65 mm 2 5 inches diameter and its height is 9 5 mm 0 374 inch 2 Large capacity The disk drive can record up to 15 GB formatted on one disk using the 16 17 MTR recording method and 15 recording zone technology The MHN Series has a formatted capacity of 30 GB MHN2300AT 20 GB MHN2200AT 15 GB MHN2150AT and 10 GB MHN2100AT respectively 3 High speed Transfer rate The disk drives the MHN Series have an internal data rate up to 30 7 MB s The disk drive supports an external data rate up to 100 MB s U DMA mode 5 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positi
60. 2EN 4 2 Subassemblies Head Head 3 2 _ 2 m Head 1 1 1 0 DE OE 0 ATTE Oris cr 0 m E MHN2300AT MHN2200AT MHN2150AT Either of head or MHN2100AT head 3 is mounted Figure 4 1 Head structure 4 2 3 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 4 200 rpm 1 The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting 4 2 4 Actuator The actuator consists of a voice coil motor VCM and a head carriage The VCM moves the head carriage along the inner or outer edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head 4 2 5 Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating When disk drives are transported under conditions where the air pressure changes a lot filtered air is circulated in the DE The circulation filter cleans out dust and dirt from inside the DE The disk drive cycles air continuously through the circulation filter through an enclosed l
61. 5 CH 1FA CL 1F3 SN 1 2 5 1 1 FR At command completion I O registers contents to be read 1F6 XD ESIDIESE Head No LBA MSB IF5 CH 1F4 CL XX 1F3 SN 01 1 1F2 SC 01 IF1 ER Diagnostic code This register indicates X 00 in the LBA mode C141 E120 02EN 5 53 Interface 19 READ LONG X 22 or X 23 5 54 This command operates similarly to the READ SECTOR S command except that the device transfers the data in the requested sector and the ECC bytes to the host system The ECC error correction is not performed for this command This command is used for checking ECC function by combining with the WRITE LONG command The READ LONG command supports only single sector operation Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command At command issuance I O registers setting contents 1F7 CM 0 0 1 0 0 0 1 R 1F6 DH Head No LBA MSB 5 Cylinder No MSB LBA 1 4 Cylinder No LSB LBA 1F3 SN Sector No LBA LSB 1F2 SC 01 IFL FR xx R Retry At command completion I O registers contents to be read 1F6 DH Head No LBA MS 5 Cylinder No MSB LBA 1F4 CL Cylinder No LSB LBA IF3 SN Sector No LBA LSB 1F2 SC 00 1 1F1 ER Error information Ifthe command is terminated due to an error this register indicates 01 C141 E120
62. 8 1 48 bit Addressing feature set supported Bit 7 1 Host Protected Area feature set supported Bit 6 1 Automatic acoustic management supported Bit 5 1 READ WRITE DMA QUEUED commands supported Bit 4 1 Power up in Standby feature set supported Bit 3 1 Security feature set supported Bit 2 1 SMART error log supported Bit 1 1 SMART self test supported Bit 0 Z SMART feature set supported 8 254 X 0000 Reserved 255 X XxAS Integrity word Bits 15 8 contains the data structure checksum that is the two s complement of the sum of all byte in words 0 through 254 and the byte consisting of bits 7 0 of word 255 C141 E120 02EN 5 87 Interface 5 3 3 Error posting Table 5 15 lists the defined errors that are valid for each command Table 5 17 Command code and parameters 1 of 2 meescons v v vL Fwerresecrors Y Y meswunug v v v Dwmewunu v Y usa dP wm vv v Dwoweuvscrms v v mug _ s v v v v __ PREADNATIVEMaxabpRESS freapuons Dwmuog O EXTR p pu
63. ARDY signal to suspend the Ultra DMA data In transfer Data Out Strobe signal from the host during Ultra DMA data Out transfer WRITE DMA command Both the rising and falling edges of the HSTROBE signal latch data from Data 15 0 into the device The host can suspend the inversion of the HSTROBE signal to suspend the Ultra DMA data Out transfer Interrupt signal to the host This signal is negated in the following cases assertion of RESET signal Reset by SRST of the Device Control register Write to the command register by the host Read ofthe status register by the host Completion of sector data transfer without reading the Status register The signal output line has a high impedance when no devices are selected or interruption is disabled C141 E120 02EN signal CS0 CS1 DA 0 2 PDIAG CBLID DASP IORDY DDMARDY DSTROBE CSEL DMACK C141 E120 02EN 5 1 Physical Interface Description Chip select signal decoded from the host address bus This signal is used by the host to select the command block registers Chip select signal decoded from the host address bus This signal is used by the host to select the control block registers Binary decoded address signals asserted by the host to access task file registers Key pin for prevention of erroneous connector insertion This signal is an input mode for the master device and an output mode for the slav
64. ARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than t after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY and no sooner than t after the host places the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA burst for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DSTROBE within t DMACK after the host negates The host shall neither negate STOP nor assert HDMARDY until at least t 4 after the host has negated DMACK The host shall not assert DIOR CSO CS1 DA2 DAI or DAO until at least after negating DMACK C141 E120 02EN 5 5 Ultra DMA Feature Set 5 5 4 Ultra DMA data out commands 5 5 4 1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowe
65. C141 E120 02EN MHN2300AT MHN2200AT MHN2150AT MHN2100AT DISK DRIVES PRODUCT MANUAL FUJITSU FOR SAFE OPERATION Handling of This Manual This manual contains important information for using this product Read thoroughly before using the product Use this product only after thoroughly reading and understanding especially the section Important Alert Items in this manual Keep this manual handy and keep it carefully FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property Use the product according to this manual IMPORTANT NOTE TO USERS READ THE ENTIRE MANUAL CAREFULLY BEFORE USING THIS PRODUCT INCORRECT USE OF THE PRODUCT MAY RESULT IN INJURY OR DAMAGE TO USERS BYSTANDERS OR PROPERTY While FUJITSU has sought to ensure the accuracy of all information in this manual FUJITSU assumes no liability to any party for any damage caused by any error or omission contained in this manual its updates or supplements whether such errors or omissions result from negligence accident or any other cause In addition FUJITSU assumes no liability with respect to the application or use of any product or system in accordance with the descriptions or instructions contained herein including any liability for incidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTOR
66. DAO DA1 DA2 CS0 C51 XXX Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Device terminating an Ultra DMA data in burst C141 E120 02EN 5 119 Interface 5 6 3 6 Host terminating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device os tu DMACK host tack tre fee a STOP Y dios I nnm 4 wit tack HDMARDY MEUS host NE EIS tioRDvz DSTROBE device aN tcvs gt 000150 KIX XXXXKKKY QUU ROGER DAO DA DA2 CSO CS1 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Host terminating an Ultra DMA data in burst 5 120 C141 E120 02EN 5 6 Timing 5 6 3 7 Initiating an Ultra DMA data out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host STOP host 7777777777777 tzioRDY DDMARDY device HSTROBE host DD 15 0 host DAO DA1 DA2 CSO0 CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ DMACK are asserted Figure 5 16 Initiating an Ultra DMA data out burst
67. DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed C141 E120 02EN 5 11 Interface Bit5 The Device Write Fault DF bit This bit indicates that a device fault write fault condition has been detected If a write fault is detected during command execution this bit is latched and retained until the device accepts the next command or reset Bit4 Device Seek Complete DSC bit This bit indicates that the device heads are positioned over a track In the IDD this bit is always set to 1 after the spin up control is completed Bit3 Data Request DRQ bit This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device Bit2 Always 0 Bit 1 Always 0 0 Error ERR bit This bit indicates that an error was detected while the previous command was being executed The Error register indicates the additional information of the cause for the error 10 Command register X 1F7 The Command register contains a command code being sent to the device After this register is written the command execution starts immediately Table 5 3 lists the executable commands and their
68. Defective sector Head 0 zu 0 1 2 3 unused 4 5 6 656 657 658 Sector logical Note If an access request to logical sector 4 is specified the device accesses physical sector 5 instead of sector 4 Figure 6 5 Sector slip processing 2 Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder This processing is performed when the alternate assignment is specified in the FORMAT TRACK command or when the automatic alternate processing is performed at read error occurrence Figure 6 8 shows an example where logical sector 4 is detective on head 0 in cylinder 0 6 10 C141 E120 02EN 6 4 Read Ahead Cache Cylinder 0 Defective sector Head 0 0 1 2 3 5 6 658 659 Alternate cylinder Head 0 Defective sector is assigned to unassigned sector Notes 1 4 alternate cylinders are provided for each head in zone 14 inner side 2 When an access request to logical sector 4 is specified the device accesses the alternated sector in the alternate cylinder instead of sector 4 When an access request to sectors next to logical sector 5 is specified the device seeks to cylinder head 0 and continues the processing Figure 6 6 Alternate cylinder assignment 3 Automatic alternate assignment The device performs the automatic alternate assignment when ECC correction performance is increased during read error retry a read error is recovered Before automatic
69. E command The DRQ bit of the Status register is required to set only at the start of the data block not on each sector The number of sectors per block is defined by a successful SET MULTIPLE MODE command The SET MULTIPLE MODE command should be executed prior to the WRITE MULTIPLE command If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error Disk errors encountered during execution of the WRITE MULTIPLE command are posted after attempting to write the block or the partial block that was transferred Write operation ends at the sector where the error was encountered even if the sector is in the middle of a block If an error occurs the subsequent block shall not be transferred Interrupts are generated when the DRQ bit of the Status register is set at the beginning of each block or partial block The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined To obtain a valid error inform
70. F3 SN Start sector No LBA LSB 1F2 SC Transfer sector count 1F1 FR XX At command completion I O registers contents to be read 1F6 DH End head No LBA MSB IF5 CH End cylinder No MSB LBA 1F4 CL End cylinder No LSB LBA 1F3 SN End sector No LBA LSB 1F2 SC 00 1 1F1 Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 5 WRITE SECTOR S X 30 or X 31 5 22 This command writes data of sectors from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified from 1 to 256 sectors A sector count of 0 requests 256 sectors Data transfer begins at the sector specified in the Sector Number register For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 2 If the head is not on the track specified by the host the device performs an implied seek After the head reaches to the specified track the device writes the target sector If an error occurs when writing to the target sector retries are attempted irrespectively of the R bit setting The data stored in the buffer and CRC code and ECC bytes are written to the data field of the corresponding sector s Upon the completion of the command execution the command block registe
71. K host tu tss tu gt lioRDYz DDMARDY device tack HSTROBE 7 host MINNIE tevs tev DD 15 0 7 LOS OS ONS ES EON host KOKO OOOO BOO ROC tack DAO DA1 DA2 50 CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Host terminating an Ultra DMA data out burst 5 124 C141 E120 02EN 5 6 Timing 5 6 3 11 Device terminating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host tack STOP ES um host trp tlorpyz DDMARDY device fers tu tack HSTROBE host 4 tcvs tcvH SM DD 15 0 AENEA AF host XXKK KOO tack DAO DA1 DA2 CS0 CS1 Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Device terminating an Ultra DMA data out burst C141 E120 02EN 5 125 Interface 5 6 4 Power on and reset Figure 5 21 shows power on and reset hardware and software reset timing 1 Only master device is present V Clear Reset 1 Power on Eti RESET lt tM gt Software reset Reset means including Power on Reset Hardware Reset RESET and Software Reset 2 Master and slave devices are present 2 drives configuration
72. LIZE DEVICE PARAMETERS 5 4 1 PIO Data transferring commands from device to host 5 90 The execution of the following commands involves data transfer from the device to the host e IDENTIFY DEVICE e READ SECTOR S e READ LONG e READ BUFFER e SMART READ DATA e SMART READ LOG SECTOR The execution of these commands includes the transfer one or more sectors of data from the device to the host In the READ LONG command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector of data is available for transfer to the host the device sets DRQ bit and clears BSY bit The drive then asserts INTRQ signal e After detecting the INTRQ signal assertion the host reads the Status register The host reads one sector of data via the Data register In response to the Status register being read the device negates the INTRQ signal f The drive clears DRQ bit to 0 If transfer of another sector is requested the device sets the BSY bit and steps d and after are repeated Even if an error is encountered the device prepares for data transfer by setting the DRQ bit Whether or not to transfer the data 1s determined for each host In other C141
73. ROZEN MODE Table 5 13 Contents of security password Control word Bit 0 Identifier 0 Compares the user passwords 1 Compares the master passwords Bits 1 to 15 Reserved Password 32 bytes At command issuance I O register contents 1F7 CM 1 1 1 1 0 1 1 0 ao XX 1F5 CH 1F4 CL XX 1F3 SN XX 1F2 SC XX IF1 FR XX 1F5 CH XX 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information C141 E120 02EN 5 77 Interface 31 SECURITY ERASE PREPARE F3h The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command Issuing this command during FROZEN MODE returns the Aborted Command error At command issuance I O register contents 1F7 CM 1 1 1 1 0 0 1 1 XX 1F5 CH IFA CL xx 1F3 SN 1F2 SC xx IFL FR xx At command completion I O register contents XX 1F5 CH 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 32 SECURITY ERASE UNIT F4h 5 78 This command erases all user data This command also invalidates the user password and releases the lock function The host transfers the 512 byte data shown in Table 5 13 to the device The device compares the user password or master password in the transferred data with the user password or maste
74. Retry At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1F5 CH End cylinder No MSB LBA 1F4 CL End cylinder No LSB LBA 1F3 SN End sector No LBA LSB 1F2 SC 00 1 1F1 ER Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 2 READ MULTIPLE X C4 5 18 The READ MULTIPLE Command performs the same as the READ SECTOR S Command except that when the device is ready to transfer data for a block of sectors and enters the interrupt pending state only before the data transfer for the first sector of the block sectors In the READ MULTIPLE command operation the DRQ bit of the Status register is set only at the start of the data block and is not set on each sector The number of sectors per block is defined by a successful SET MULTIPLE MODE Command The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a C141 E120 02EN 5 3 Host Commands final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued before the SET MULTIPLE MODE comm
75. When the BSY bit is 1 other bits of this register are invalid When the host system reads this register while an interrupt is pending it is considered to be the Interrupt Acknowledge the host system acknowledges the interrupt Any pending interrupt is cleared negating INTRQ signal whenever this register is read Bit7 Busy BSY bit This bit is set whenever the Command register is accessed Then this bit is cleared when the command is completed However even if a command is being executed this bit is 0 while data transfer is being requested DRQ bit 1 When BSY bit is 1 the host system should not write the command block registers If the host system reads any command block register when BSY bit is 1 the contents of the Status register are posted This bit is set by the device under following conditions a Within 400 ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is set for no longer than 15 seconds after the IDD accepts reset b Within 400 ns from the host system starts writing to the Command register c Within 5 us following transfer of 512 bytes data during execution of the READ SECTOR S WRITE SECTOR S or WRITE BUFFER command Within 5 us following transfer of 512 bytes of data and the appropriate number of ECC bytes during execution of READ LONG or WRITE LONG command Bit6 Device Ready
76. Y FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal devices and household appliances This product is not intended for special uses atomic controls aeronautic or space systems mass transport vehicle operating controls medical devices for life support or weapons firing controls where particularly high reliability requirements exist where the pertinent levels of safety are not guaranteed or where a failure or operational error could threaten a life or cause a physical injury hereafter referred to as mission critical use Customers considering the use of these products for mission critical applications must have safety assurance measures in place beforehand Moreover they are requested to consult our sales representative before embarking on such specialized use The contents of this manual may be revised without prior notice The contents of this manual shall not be disclosed in any way or reproduced in any media without the express written permission of Fujitsu Limited All Rights Reserved Copyright FUJITSU LIMITED 2001 C141 E120 02EN Revision History Edition Date Revised section 1 Details Added rns 2001 02 28 02 28 EM 2001 09 03 1 2 No was added Table 1 3 Current and power dissipation were changed Tab
77. a DMA burst has three mandatory phases of operation the initiation phase the data transfer phase and the Ultra DMA burst termination phase In addition an Ultra DMA burst may be paused during the data transfer phase see 5 5 3 and 5 5 4 for the detailed protocol descriptions for each of these phases 5 6 defines the specific timing requirements In the following rules DMARDY is used in cases that could apply to either DDMARDY or HDMARDY and STROBE is used in cases that could apply to either DSTROBE or HSTROBE The following are general Ultra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst 5 5 3 Ultra DMA data in commands 5 5 3 1 Initiating an Ultra DMA data in burst 5 100 The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 1 and 5 6 3 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE 3 Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP 4 The host shall negate HDMARDY 5 The
78. a access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Master slave The disk drives the MHN Series can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device 5 Error correction and retry by ECC If a recoverable error occurs the disk drives the MHN Series themselves attempt error recovery The ECC has improved buffer error correction for correctable data errors 6 Self diagnosis The disk drives the MHN Series have a diagnostic function to check operation of the controller and disk drives Executing the diagnostic command invokes self diagnosis 7 Write cache When the disk drives the MHN Series receive a write command the disk drives post the command completion at completion of transferring data to the data buffer completion of writing to the disk media This feature reduces the access time at writing C141 E120 02EN 1 3 Device Overview 1 2 Device Specifications 1 2 1 Specifications summary Table 1 1 shows the specifications of the disk drives MHN Series Table 1 1 Specifications 1 2 wisasoosr wann Positioning time read and seek Minimum Track to Track 1 5 ms typ Average Read 12 ms typ Maximum Full 22 ms typ Start Stop time
79. a has been written normally or an error has occurred The device performs every error recovery so that the data are read correctly When executing this command the reading of the data may take several seconds if much data are to be read In case a non recoverable error has occurred while the data is being read the error generation address is put into the command block register before ending the command This error sector is deleted from the write cache data and the remaining cache data is written into the medium by the execution of the next Flush Cache command C141 E120 02EN 5 83 Interface At command issuance I O register contents 1F7 CM 1 1 1 0 0 1 1 1 1 5 XX 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 FR XX 1F5 CH 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 37 DEVICE CONFIGURATION B1 Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register The following table shows these Features register values If this command sets with the reserved value of Features register an aborted error is posted COh DEVICE CONFIGURATION RESTORE DEVICE CONFIGURATION FREEZE C2h DEVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET 5 84 C141 E120 02EN 5 3 Host Commands At command issuance I O register contents may t o 1 1 o o 9 1 mem i x x Jovy 1F5 CH IFA CL xx IFA SN
80. able the word 88 Bit 1 1 Enable the word 64 70 Bit 0 1 Enable the word 54 58 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bit 15 9 Reserved Bit 8 1 Enable the multiple sector transfer Bit 7 0 Transfer sector count currently set by READ WRITE MULTIPLE command without interrupt supports 2 4 8 and 16 sectors Word 63 Multiword DMA transfer mode Bit 15 8 Currently used multiword DMA transfer mode Bit 7 0 Supportable multiword DMA transfer mode Bit 2 1 Mode 2 Bit 1 1 Mode 1 Bit 0 1 Mode 0 Word 64 Advance PIO transfer mode support status Bit 15 8 Reserved Bit 7 0 Advance PIO transfer mode 5 35 Interface Bit 1 1 Mode 4 Bit 0 1 Mode 3 9 WORD 80 Bit 15 7 Reserved Bit 6 1 ATA ATAPI 6 supported Bit 5 1 ATA ATAPI 5 supported Bit 4 1 ATA ATAPI 4 supported Bit 3 1 ATA 3 supported Bit 2 1 ATA 2 supported Bit 1 0 Undefined 10 WORD 82 Bit 15 Undefined Bit 14 Supports the NOP command Bit 13 Supports the READ BUFFER command Bit 12 Supports the WRITE BUFFER command Bit 11 Undefined Bit 10 Supports the Host Protected Area feature set Bit 9 Supports the DEVICE RESET command Bit 8 Supports the SERVICE interrupt Bit 7 2 Supports the release interrupt Bit 6 2 Supports the read cache function Bit 5 2 Supports the write cache function Bit 4 Supports the PACKET command feature
81. ace 5 6 5 2 1 TO registers 5 7 5 2 2 Command block registers 5 8 5 2 3 Control block registers 5 13 5 3 Host Commands 5 13 5 3 1 Command code and parameters 5 14 5 3 2 Command descriptions 5 16 5 3 3 Error posting 5 88 5 4 Command Protocol 5 90 5 4 1 PIO Data transferring commands from device to host 5 90 5 4 2 PIO Data transferring commands from host to device 5 92 5 4 3 Commands without data transfer 5 94 5 4 4 Othercommands 5 96 5 4 5 DMA data transfer commands 5 96 5 5 Ultra DMA Feature Set 5 99 5 5 1 Overview 5 99 5 5 2 Phases of operation 5 100 5 5 3 Ultra DMA data in commands 5 100 xi Contents CHAPTER 6 xil 5 5 3 1 Initiating an Ultra DMA data in burst 5 100 5 5 3 2 The data in transfer 5 101 5 5 3 3 Pausing an Ultra DMA data in burst 5 101 5 5 3 4 Terminating an Ultra DMA data in burst 5 102 5 54 Ultra DMA data out commands 5 105 5 5 4 1 Initiating an Ultra DMA data out burst 5 105 5 5 4 2 The data out transfer 5 105 5 5 4 3 Pausing an Ultra DMA data out burst 5 106 5 5 4 4 Terminating an Ultra DMA data out burst 5 107 5 5 5 Ultra CRC rules 5 109 5 5 6 Series termination required for Ultra DMA 5 110 5 6 Timing 5 111 5 6 1 PIO data transfer 5 111 5 6 2 Multiword data transfer 5 112 5 6 3 Ultra DMA data transfer 5 113 5 6 3 1 Initiating an Ultra DMA data in burst 5 113 5 6 3 2 Ultra DMA data burst timing requirements 5 114 5 6 3 3 Sustained Ultra DMA data in burst 5 117 5 6 3 4 Host pa
82. additional data words If the device negates DDMARDY greater than t after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and t timing for the host The device shall negate DMARQ no sooner than t after negating DDMARDY The device shall not assert DMARQ again until after the Ultra DMA burst is terminated The host shall assert STOP with t after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated If HSTROBE is negated the host shall assert HSTROBE with t after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition of HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 The host shall negate DMACK no sooner than t after the host has asserted HSTROBE and STOP and the device has negated DMARQ and DDMARDY and no sooner than t after placing the result of its CRC calculation on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for a
83. aintained even when the device is turned off and then on When the device receives this subcommand it asserts the BSY bit disables the failure prediction feature then clears the BSY bit C141 E120 02EN 5 3 Host Commands Table 5 7 Features Register values subcommands and functions 3 of 3 Features Resister Function SMART Return Status When the device receives this subcommand it asserts the BSY bit and saves the current device attribute values Then the device compares the device attribute values with insurance failure threshold values If there is an attribute value exceeding the threshold F4h and 2Ch are loaded into the CL and CH registers If there are no attribute values exceeding the thresholds 4Fh and C2h are loaded into the CL and CH registers After the settings for the CL and CH registers have been determined the device clears the BSY bit SMART Enable Disable Auto Off line This sets automatic off line data collection in the enabled when the SC register specification 00h or disabled when the SC register specification 00 state This setting is preserved whether the drive s power is switched on or off If 24 hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART Read Attribute Values subcommand FR register
84. and timings C141 E120 02EN 5 1 Interface 5 1 Physical Interface 5 1 1 Interface signals Figure 5 1 shows the interface signals DATA 0 15 DATA BUS OO DMACK DMAACKNOWIEDGE gt gt DMA ACKNOWLEDGE DMARQ DMA REQUEST INTRO INTERRUPT REQUEST DIOW IOWRIE STOP STOP DURING ULTRA DMA DATA BURSTS DIOR I O READ HDMARDY DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE DATA STROBE DURING ULTRA DMA DATA OUT BURST PDIAG PASSED DIAGNOSTICS CBLID CABLE TYPE IDENTIFIER DASP DEVICE ACTIVE SLAVE PRESENT IORDY I O READY DDMARDY DMA READY DURING ULTRA DMA DATA OUT BURSTS DSTROBE DATA STROBE DURING ULTRA DMA DATA IN BURSTS DA 0 2 DEVICE ADDRESS CS0 CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT MSTR Master ENCSEL ENABLE CSEL GND GROUND Figure 5 1 Interface signals C141 E120 02EN 5 1 2 Signal assignment on the connector 5 1 Physical Interface Table 5 1 shows the signal assignment on the interface connector Table 5 1 Signal assignment on the interface connector C141 E120 02EN MSTR unused KEY RESET DATA7 5 4 DATA2 DATAI DATAO GND DMARQ DIOW STOP DIOR HDMRDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DAI DAO CS0 DASP 5 VDC GND MSTR ENCSEL ENCSEL KEY GND DATA8 DATA9 DATAIO DATAII DATAI2 DATAI13 DATAI4 15 GND GND GND CSEL
85. and adapter board ATA AT Attachment standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors Interfaces based on this standard are called ATA interfaces BIOS standard for drives The BIOS standard collectively refers to the parameters defined by the host which for example include the number of cylinders the number of heads and the number of sectors per track in the drive The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command registers Data block A data block is the unit used to transfer data A data block normally indicates a single sector DE Disk enclosure The DE includes the disks built in spindle motor actuator heads and air filter The DE is sealed to protect these components from dust Master Device 0 The master is the first drive that can operate on the AT bus The master is daisy chained with the second drive which can operate in conformity with the ATA standard C141 E120 02EN GL 1 Glossary MTBF Mean time between failures The MTBF is calculated by dividing the total oper
86. and is executed or when the READ MULTIPLE command is disabled the device rejects the READ MULTIPLE command with an ABORTED COMMAND error Figure 5 2 shows an example of the execution of the READ MULTIPLE command e Block count specified by SET MULTIPLE MODE command 4 number of sectors in a block e READ MULTIPLE command specifies Number of requested sectors 9 Sector Count register 9 Command Issue Parameter v Write V Status read V Status read V Status read VeV Sector 1j2i3i4 516 718 9 tranferred lt gt gt gt Partial Block Block block Figure 5 2 Execution example of READ MULTIPLE command At command issuance I O registers setting contents 1 0 0 1 9 0 1F6 y Es Start head No LBA MSB IF5 CH Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1F3 SN Start sector No LBA LSB 1F2 SC Transfer sector count IFI FR XX C141 E120 02EN 5 19 Interface At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 165 End cylinder No MSB LBA 1F4 End cylinder No LSB LBA 1F3 SN End sector No LBA LSB 1F2 SC 00 1F1 Error information command is terminated due to an error the remaining number of sectors for which data was not transferred is set in this register 3 READ DMA X C8 or X C9 5 20 This command operates similarly
87. asing IORDY Minimum time before driving IORDY 4 Setup and hold times for DMACK before assertion or negation Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst Except for some instances of t that apply to host signals only the parameters ty and t indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent respond with a signal before proceeding t is an unlimited interlock that has no maximum time value t is a limited time out that has a defined minimum t is a limited time out that has a defined maximum 80 conductor cabling shall be required in order to meet setup tps tes and hold t Timing for tpv tevs and teyp shall be met for lumped capacitive loads of 15 and 40 pf at the connector where all signals Data and STROBE have the same capacitive load value Due to reflections on the cable the measurement of these timings is not valid in a normally functioning system Ds py toy times in modes greater than 2 For all modes the parameter torony may be greater than t due to the fact that the host has a pull up on IORDY giving it a known state when not actively driven The parameters t end of the cable and t for mode 5 is defined for a recipient at the end of the cable only in a configuration with one device at the DS Note All timing measureme
88. ation the host should retry data transfer as an individual request C141 E120 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F6 OH Sogn Start head No LBA MSB 1 5 CH 1 4 CL 1F3 SN 1F2 SC 1F1 FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count XX At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1 5 184 CL 1F3 SN 1F2 SC 1 1 End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 Error information 7 WRITE DMA X CA or X CB This command operates similarly to the WRITE SECTOR S command except for following events e data transfer starts at the timing of DMARQ signal assertion e device controls the assertion or negation timing of the DMARQ signal e device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device e device posts a status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and post
89. ation time total power on time by the number of failures in the disk drive during operation MTTR Mean time to repair The MTTR is the average time required for a service person to diagnose and repair a faulty drive PIO Programmed input output Mode to transfer data under control of the host CPU Positioning Sum of the seek time and mean rotational delay Power save mode The power save modes are idle mode standby mode and sleep mode In idle mode the drive is neither reading writing nor seeking data In standby mode the spindle motor is stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean delay is the average time required for a head to reach a sector after the head is positioned on a track Seek time The seek time is the time required for a head to move from the current track to another track The seek time does not include the mean rotational delay Slave Device 1 The slave is a second drive that can operate on the AT bus The slave is daisy chained with the first drive operating in conformity with the ATA standard GL 2 C141 E120 02EN Glossary Status The status is a piece
90. buffer for read command When all data requested by the read command are stored in the data buffer for write command hit all the device transfers data from the data buffer for write command At this time the read ahead operation to the data subsequent to the requested data is not performed Even if a part of data requested by the read command are stored in the data buffer for write command hit partially all data are read from the disk medium without transferring from the data buffer for write command 3 Invalidating caching data Caching data in the data buffer is invalidated in the following case 1 2 3 4 5 C141 E120 02EN Following command is issued to the same data block as caching data WRITE SECTOR S WRITE DMA WRITE MULTIPLE Command other than following commands is issued all caching data are invalidated READ SECTOR S READ DMA READ MULTIPLE WRITE SECTOR S WRITE MULTIPLE WRITE VERIFY SECTOR S Caching operation is inhibited by the SET FEATURES command Issued command is terminated with an error Soft reset or hard reset occurs or power is turned off Operations 6 The device enters the sleep mode 7 Under the state that the write data 1s kept in the data buffer for write command as a caching data new write command is issued write data kept until now are invalidated 6 4 3 Usage of read segment This subsection explains the usage of the rea
91. ch of the Ultra DMA Modes 5 6 3 1 Initiating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device tu DMACK host T tack Pu STOP d host 4 w tack tes HDMARDY 777777777777777 Y ps host gt tzioRDY ii ters gt DSTROBE device ipzrs ws lt gt DEIRO SO SCC OG eot CX __ AAA tack lt DAO DA1 DA2 CS0 CS1 Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 11 Initiating an Ultra DMA data in burst C141 E120 02EN 5 113 Interface 5 6 3 2 Ultra DMA data burst timing requirements Table 5 18 Ultra DMA data burst timing requirements 1 of 2 MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 in ns in ns in ns in ns in ns in ns COMMENT pss sso fo he pp KHA Typical sustained average two cycle time 3 t 7 Cycle time allowing for CYC ae asymmetry and clock variations from STROBE edge to STROBE edge Two cycle time allowing for clock variations from rising edge to next rising edge or from falling edge to next falling edge of STROBE Data setup time at recipient from data valid until STROBE edge 2 5 Data hold time at recipient from STROBE edge until data may become invalid 2 5 Data valid setup time at sender from data valid until STROBE e
92. command is a sequential write data to be written by a command is physically sequent to data of previous command the drive starts data transfer and receives data of sectors requested by the host system At this time if the write operation of the previous command is still been executed the drive continuously executes the write operation of the next command from the sector next to the last sector of the previous write operation Thus the latency time for detecting a target sector of the next command is eliminated This shortens the access time The drive generates an interrupt of command complete after completion of data transfer requested by the host system as same as at previous command When the write operation of the previous command had been completed the latency time occurs to search the target sector If the received command is not a sequential write the drive receives data of sectors requested by the host system as same as sequential write The drive generates the interrupt of command complete after completion of data transfer requested by the host system Received data is processed after completion of the write operation to the disk medium of the previous command Even if a hard reset or soft reset 1s received or the write cache function is disabled by the SET FEATURES command during unwritten data is kept the instruction is not enabled until remaining unwritten data is written onto the disk medium 6 20 C141 E120 02EN 6
93. contents to be read Dmm fs Ps Ps ove 1F5 Rom 184 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information C141 E120 02EN 5 31 Interface At command issuance I O registers setting contents 1F5 FS 1F4 CL 1F3 SN 1F2 SC IF1 FR At command completion I O registers contents to be read mm s 1F5 P 1 4 CL XX 1F3 SN XX IF2 SC XX 1F1 ER Error information Table 5 4 Information to be read by IDENTIFY DEVICE command 1 of 3 EUN ie ES X 1000 Buffer Size 1 LSB 512 Byte X 0004 Number of ECC bytes transferred at READ LONG or WRITE LONG command 5 32 C141 E120 02EN 5 3 Host Commands Table 5 4 Information to be read by IDENTIFY DEVICE command 2 of 3 Word READ WRITE MULTIPLE command 6 Transfer sector count currently set by READ WRITE MULTIPLE command 6 2 47 48 49 50 51 52 53 54 55 56 EE Total number of user addressable sectors LBA mode only 2 Multiword DMA transfer mode 7 X 0003 Advance PIO transfer mode support status 8 X 0078 Minimum multiword DMA transfer cycle time per word 120 ns X 0078 Manufacturer s recommended DMA transfer cycle time 120 ns X 00F0 Minimum PIO transfer cycle time without IORDY flow control 240 ns X 0078 Minimum PIO transfer cycle time with IORDY flow control 120 ns 2 Support of command sets 10 83 Support of command set
94. crements the Unlock counter and remains in the Set Max Lock state On the acceptance of the SET MAX LOCK command the Unlock counter is set to a value of five When this counter reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the password compare matches then the device makes a transition to the Set Max Unlocked state and all SET MAX commands will be accepted The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed C141 E120 02EN 5 49 Interface 5 50 At command issuance I O registers setting contents 1F7 CM 1 11 1 0 0 1 IF2 SC IF1 FR IFS CH IFA CL xx At command completion I O registers contents to be read 1F6 DH xx 1F5 CH 1F4 CL xx IFA SN xx 1F2 SC xx e SET MAX FREEZE LOCK FR 04h The Set MAX FREEZE LOCK command sets the device to SET MAX Frozen state After the device made a transition to the Set Max Freeze Lock state the following SET MAX commands are rejected then the device returns command aborted SET MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK If the Device is in the SET MAX UNLOCK state with the SET MAX FREEZE LOCK command then the device returns command aborted The READ NATIVE MAX ADDRESS command is not executed just before this command
95. ct is designed to be used in offices or computer rooms For details regarding the operating environment of use refer to the Cnnn Xnnn and the Cnnn Xnnn Please forward any comments you may have regarding this manual To make this manual easier for users to understand opinions from readers are needed Please write your opinions or requests on the Comment at the back of this manual and forward it to the address described in the sheet C141 E120 02EN Preface Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive C141 E120 02EN iii This page is intentionally left blank Important Alert Items Important Alert Messages The important alert messages in this manual are as follows A hazardous situation could result in minor or moderate personal AC AUTI injury if the user does not perform the procedure correctly Also damage to the product or other property may occur if the user does not perform the procedure correctly Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields
96. d see 5 6 3 7 and 5 6 3 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 10 11 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated The device shall assert DMARQ to initiate an Ultra DMA burst Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP The host shall assert HSTROBE The host shall negate 50 51 DA2 DAI and DAO The host shall keep 80 CS1 DA2 DAI and DAO negated until after negating DMACK at the end of the burst Steps 3 4 and 5 shall have occurred at least t before the host asserts DMACK The host shall keep DMACK asserted until the end of an Ultra DMA burst The device may negate DDMARDY t after the host has asserted DMACK Once the device has negated DDMARDY the device shall not release DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst The host shall negate STOP within t after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE The device shall assert DDMARDY within t after the host has negated STOP After asserting DMARQ and DDMARDY the device shall not negate either signal until after the first negation of HSTROBE by the host The host shall drive the first word of the data transfer onto DD 15 0 This step may occur any time during Ultra DMA burst initiation To transfer th
97. d Head Me 3 gas 2 ES NN 2 Ncc d 1 1 1 0 co 0 LL 0 Em Mnt MHN2300AT MHN2200AT MHN2150AT Either of head or MHN2100AT head 3 is mounted Figure 2 2 Configuration of disk media heads 3 Spindle motor 4 Actuator The disks are rotated by a direct drive Hall less DC motor The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays on the ramp out of the disk and is fixed by a mechanical lock 5 Air circulation system The disk enclosure DE is sealed to prevent dust and dirt from entering The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure 6 Read write circuit 7 Controller circuit C141 E120 02EN The read write circuit uses a LSI chip for the read write preamplifier It improves data reliability by preventing errors caused by external noise The controller circuit consists of an LSI chip to improve reliability The high speed microprocessor unit MPU achieves a high performance AT controller De
98. d segment buffer at following cases 6 4 3 1 Mis hit no hit A lead block of the read requested data is not stored in the data buffer The requested data is read from the disk media The read ahead operation is performed only when the last sector address of the previous read command and the lead sector address of this read command is sequential see item 2 1 Sets the host address pointer HAP and the disk address pointer DAP to the lead of segment HAP v Segment only for read A DAP 2 Transfers the requested data that already read to the host system with reading the requested data from the disk media Stores the read requested HAP data upto this point v DAP 6 14 C141 E120 02EN 6 4 Read Ahead Cache 3 After reading the requested data and transferring the requested data to the host system had been completed the disk drive stops command execution without performing the read ahead operation HAP stopped 1 aus tum stopped DAP 4 Following shows the cache enabled data for next read command Cache enabled data Empty area Start LBA Last LBA 6 4 3 2 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command the disk drive starts the read ahead operation a Sequential command just after non sequential command When the previo
99. data format is the same as that in byte 02 to 19 1 1 FA IFB Vendor unique 1FC Self test index FD Reserved 1 F F Check sum e Self test log 1 to 21 When executes self test the self test index value is incremented and the self test execution result is recorded in the self log test area specified by this value When the self test index exceeds 21 it returns to 01 e Self test index Indicates the latest self test log number If the self test has not been executed 00h is displayed 30 SECURITY DISABLE PASSWORD F6h 5 76 This command invalidates the user password already set and releases the lock function The host transfers the 512 byte data shown in Table 5 13 to the device The device compares the user password or master password in the transferred data with the user password or master password already set and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned C141 E120 02EN 5 3 Host Commands Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error The section about the SECURITY FREEZE LOCK command describes LOCKED MODE and F
100. de Comprehensive self test captive mode C141 E120 02EN 5 65 Interface Table 5 7 Features Register values subcommands and functions 2 of 3 Features Resister Function X D9 5 66 SMART Read Log Sector A device which receives this sub command asserts the BSY bit then reads the log sector specified in the SN register Next it clears the BSY bit and transmits the log sector to the host computer SN Log sector 00 SMART log directory 01h SMART error log 06h SMART self test log 80h 9Fh Host vendor log See Table 5 10 concerning the SMART error log data format See Table 5 11 concerning the SMART self test log data format SMART Write Log Sector A device which receives this sub command asserts the BSY bit and when it has prepared to receive data from the host computer it sets DRQ and clears the BSY bit Next it receives data from the host computer and writes the specified log sector in the SN register SN Log sector 80h 9Fh Host vendor log host can write any desired data in the host vendor log SMART Enable Operations This subcommand enables the failure prediction feature The setting is maintained even when the device is turned off and then on When the device receives this subcommand it asserts the BSY bit enables the failure prediction feature then clears the BSY bit SMART Disable Operations This subcommand disables the failure prediction feature The setting is m
101. de When the host system specifies the LBA mode by setting bit 6 in the Device Head register to 1 HS3 to HSO bits of the Device Head register indicates the head No under the LBA mode and all bits of the Cylinder High Cylinder Low and Sector Number registers are LBA bits The sector No under the LBA mode proceeds in the ascending order with the start point of LBAO defined as follows LBAO z Cylinder 0 Head 0 Sector 1 Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command the sector LBA address is not changed LBA Cylinder No x Number of head Head No x Number of sector track Sector No 1 C141 E120 02EN 5 2 Logical Interface 5 2 1 I O registers Communication between the host system and the device is done through input output I O registers of the device These I O registers can be selected by the coded signals 0 CS1 and DAO to DA2 from the host system Table 5 2 shows the coding address and the function of I O registers Table 5 2 1 O registers registers cso CSI DAI DAO 8 Host I O xin i 2 8 seres reme LL o x s i sere sesto LL a a sector its oir xir Ue E E mimm mimm H H L Devicemead Device tead H H status Commana X T
102. desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the difference speed error between the specified target position and the current position for each sampling timing during head moving The MPU then feeds the VCM drive current by setting the calculated result into the D A converter The calculation is digitally executed by the firmware When the head arrives at the target cylinder the track is followed 3 Track following operation Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed the MPU does track following control To position the head at the center of a track the DSP drives the VCM by feeding micro current For each sampling time the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware 4 7 5 Spindle motor control 1 Start mode 4 22 Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC hereafter The firmware operates on the MPU manufactured by Fujitsu The spindle motor is controlled by sending several signals from the MPU to the SVC There are three modes for the spindl
103. dge 3 Data valid hold time at sender from STROBE edge until data may become invalid 3 CRC word setup time at device 2 CRC word hold time device 2 CRC word valid setup time at host from CRC valid until DMACK negation 3 CRC word valid hold time at sender from DMACK negation until CRC may become invalid 3 Time from STROBE output released to driving until the first transition of critical timing Time from data output released to driving until the first transition of critical timing First STROBE time for device to first negate DSTROBE from STOP during a data in burst 5 114 C141 E120 02EN 5 6 Timing Table 5 18 Ultra DMA data burst timing requirements 2 of 2 NAME MODE 0 MODE 1 MODE2 MODE 3 MODE 4 MODE 5 in ns in ns in ns in ns in ns in ns COMMENT pepe pepe pepe pe e p 2 Interlock time with minimum 1 Unlimited interlock time 1 Maximum time allowed for output drivers to release from asserted or negated Minimum delay time required for output Drivers to assert or negate from released Envelope time from DMACK to STOP and HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation Ready to final STROBE time no STROBE edges shall be sent this long after negation of DMARDY Ready to pause time that recipient shall wait to pause after negating DMARDY Maximum time before rele
104. diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal X 3F6 Reg X 0C TT X 00 Master device or X 04 Status Reg m AN BSY bit Max 31 sec If the slave device is preset PDIAG is checked for up to 31 seconds Slave device BSY bit ms PDIAG Max 30 sec DASP LLCO y Figure 6 3 Response to software reset C141 E120 02EN 6 5 Operations 6 1 4 Response to diagnostic command 1 7 Reg Write When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present the master device checks the PDIAG signal for up to 6 seconds to see if the slave device has completed the self diagnosis successfully The master device does not check the DASP signal After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting
105. disk enclosure DE is zero The mounting frame is connected to SG IMPORTANT Use MG screw for the mounting screw and the screw length should satisfy the specification in Figure 3 3 The tightening torque must be 0 49N m 5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us 2 5 Side surface _ 2 5 mounting 2 5 P om d Frame of system cabinet ae Bottom surface mounting 25 3 0 or less SS Screw 3 0 or less Screw Details of A Details of B Figure 3 3 Mounting frame structure 3 4 C141 E120 02EN C141 E120 02EN 3 2 Mounting IMPORTANT Because of breather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 4 For breather hole of Figure 3 4 at least do not allow its around 3 to block MODEL XXXXXXXXX 10 PART NO XXXXXXX XXXX SER NO DATE XXXX XX RATING XXX XXXXX REV N0 012345618939 e E he ER ARO lt JUMPER gt ASS BE 66 Figure 3 4 Location of breather 3 5 Installation Conditions 4 Ambient temperature The temperature conditions for a disk drive mounted in a cabinet
106. drive setting Master drive disk drive 0 or slave drive disk drive 1 is selected Hu Open 1 C A 1 C A C Oe OA Open Short c e 2 2 D B Open a Master drive b Slave drive Figure 3 13 Jumper setting of master or slave drive Note Pins A and C should be open 3 12 C141 E120 02EN 3 4 Jumper Settings 3 4 4 CSEL setting Figure 3 14 shows the cable select CSEL setting Open 1 C A X 2 D B Short Note The CSEL setting is not depended on setting between pins Band D Figure 3 14 CSEL setting Figure 3 15 and 3 16 show examples of cable selection using unique interface cables By connecting the CSEL of the master drive to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The drive is identified as a master drive At this time the CSEL of the slave drive does not have a conductor Thus since the slave drive is not connected to the CSEL conductor the CSEL is set to high level The drive is identified as a slave drive Figure 3 15 Example 1 of Cable Select C141 E120 02EN 3 13 Installation Conditions Master drive Figure 3 16 Example 2 of Cable Select 3 14 C141 E120 02EN CHAPTER 4 Theory of Device Operation 4 1 4 2 4 3 4 4 4 5 4 6 4 7 Outline Subassemblies Circuit Configuration
107. e After completion of power on sequence e After completion of the command execution other than SLEEP and STANDBY commands e After completion of the reset sequence 3 Standby mode In this mode the VCM circuit is turned off and the spindle motor is stopped The device can receive commands through the interface However if a command with disk access is issued response time to the command under the standby mode C141 E120 02EN 6 7 Operations 4 Sleep mode takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately The drive enters the standby mode under the following conditions ASTANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode When automatic power down sequence is enabled the timer has elapsed e reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode e Reset hardware or software e STANDBY command e STANDBY IMMEDIATE command e INITIALIZE DEVICE PARAMETERS command e CHECK POWER MODE command The power consumption of the drive is minimal in this mode The drive enters only the standby mode from the sleep mode The only method to return from the standby mode is to execute a software or hardware reset The drive enters the sleep mode under the following condition e ASLEEP command is issued Issued commands are invalid
108. e as that shown in the sub section a 6 4 3 3 Full hit hit all All requested data are stored in the data buffer The disk drive starts transferring the requested data from the address of which the requested data is stored After completion of command a previously existed cache data before the full hit reading are still kept in the buffer and the disk drive does not perform the read ahead operation 1 Inthe case that the contents of the data buffer is as follows for example and the previous command is a sequential read command the disk drive sets the HAP to the address of which the hit data is stored position at previous read command HAP HAP set to hit position for data transfer DAP Last position at previous read command 0 2 The disk drive transfers the requested data but does not perform the read ahead operation HAP gt stopped a 6 18 C141 E120 02EN 6 4 Read Ahead Cache 3 The cache data for next read command is as follows gt Start LBA Last LBA 6 4 3 4 Partially hit A part of requested data including a lead sector are stored in the data buffer The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data and reads remaining requested data from the disk media directly The disk drive does not perform the read ahead operation after data transfer Following is an example of partially
109. e control start mode acceleration mode and stable rotation mode When power is supplied the spindle motor is started in the following sequence a After the power is turned on the MPU sends a signal to the SVC to charge the charge pump capacitor of the SVC The charged amount defines the current that flows in the spindle motor b When the charge pump capacitor is charged enough the MPU sets the SVC to the motor start mode Then a current approx 0 7 A flows into the spindle motor c The SVC generates a phase switching signal by itself and changes the phase of the current flowed in the motor in the order of V phase to U phase W phase to U phase W phase to V phase U phase to V phase U phase to W phase and V phase to W phase after that repeating this order C141 E120 02EN 4 7 Servo Control d During phase switching the spindle motor starts rotating in low speed and generates a counter electromotive force The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection e The MPU is waiting for a PHASE signal When no phase signal is sent for a specific period the MPU resets the SVC and starts from the beginning When a PHASE signal is sent the SVC enters the acceleration mode 2 Acceleration mode In this mode the MPU stops to send the phase switching signal to the SVC The SVC starts a phase switching by itself based on the counter electromotive f
110. e device in a daisy chain configuration This signal indicates that the slave device has been completed self diagnostics This signal is pulled up to 5 V through 10 kQ resistor at each device This signal is used to detect the type of cable installed in the system This signal is pulled up to 5 V through 10 kQ resistor at each device This is a time multiplexed signal that indicates that the device is active and a slave device is present This signal is pulled up to 5 V through 10 kQ resistor at each device This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system Flow control signal for Ultra DMA data Out transfer WRITE DMA command This signal is asserted by the device to inform the host that the device is ready to receive the Ultra DMA data Out transfer The device can negate the DDMARD Y signal to suspend the Ultra DMA data Out transfer Data In Strobe signal from the device during Ultra DMA data In transfer Both the rising and falling edges of the DSTROBE signal latch data from Data 15 0 into the host The device can suspend the inversion of the DSTROBE signal to suspend the Ultra DMA data In transfer This signal to configure the device as a master or a slave device When CSEL signal is grounded the IDD is a master device When CSEL signal is open the IDD is a slave device This signal is pulled up with 240 kQ resisto
111. e first word of data the host shall negate HSTROBE no sooner than t after the device has asserted DDMARDY The host shall negate HSTROBE no sooner than t after the driving the first word of data onto DD 15 0 5 5 4 2 The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 8 and 5 6 3 2 for specific timing requirements 1 2 C141 E120 02EN The host shall drive a data word onto DD 15 0 The host shall generate an HSTROBE edge to latch the new word no sooner than tys after changing the state of DD 15 0 The host shall generate an HSTROBE edge no more frequently than t for the selected Ultra DMA 5 105 Interface 3 4 Mode The host shall not generate two rising or falling HSTROBE edges more frequently than 2 t for the selected Ultra DMA mode The host shall not change the state of DD 15 0 until at least 1 after generating an HSTROBE edge to latch the data The host shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first 5 5 4 3 Pausing an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 9 and 5 6 3 2 for specific timing requirements a Host pausing an Ultra DMA data out burst b 5 106 1 2 3 The host shall not pause an Ultra DMA burst until at lea
112. ed C141 E120 02EN 5 41 Interface At command issuance I O registers setting contents RITIRO 5 42 1F5 FS 1F4 CL 1F3 SN 1F2 SC IF1 FR XX XX xx or 1 3 See Table 5 5 At command completion I O registers contents to be read IIS 1 5 1F4 CL 1F3 SN 1 2 SC IF1 ER XX XX XX Error information 1 Data Transfer Mode The host sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is posted PIO default transfer mode 00000 000 X 00 PIO flow control transfer mode X 00001 000 X 08 Mode 0 00001 001 X 09 Mode 1 00001 010 Mode 2 00001 011 X 0B Mode 3 00001 100 X OC Mode 4 C141 E120 02EN Multiword DMA transfer mode X Ultra DMA transfer mode X 2 Advanced Power Management APM 00100 000 20 00100 001 21 00100 010 22 01000 000 X 40 01000 001 X 41 01000 010 X 42 01000 011 X 43 01000 100 X44 01000 101 X 45 5 3 Host Commands Mode 0 Mode 1 Mode 2 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 The host writes
113. ed Thus when the command involving a seek such as the READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting contents mmm fa p 1F5 ap 1F4 CL XX IF3 SN XX 1F2 SC Period of timer FR XX At command completion I O registers contents to be read Dmm s 1F5 1F4 CL XX IF3 SN XX 1F2 SC XX 1F1 Error information C141 E120 02EN 5 3 Host Commands 26 STANDBY IMMEDIATE X 94 or X EO Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt This command does not support the automatic power down sequence At command issuance I O registers setting contents 1 7 X 94 or X EO fs Tx x 1F5 1 4 CL 1F3 SN 1F2 SC IF1 FR At command completion I O registers contents to be read Px 1F5 P 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information C141 E120 02EN 5 61 Interface 27 SLEEP X 99 or X E67 This command is the only way to make the device enter the sleep mode Upon receipt of this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an
114. eek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt In the LBA mode this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address 5 28 C141 E120 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F6 T IEEE Head No LBA MSB 1F5 CH Cylinder No MSB LBA 1F4 CL Cylinder No LSB LBA 1F3 SN Sector No LBA LSB 1F2 SC xx IFL FR xx At command completion I O registers contents to be read 1F6 DH Head No LBA MSB 1F5 CH Cylinder No MSB LBA 1FA CL Cylinder No LSB LBA 1F3 SN Sector No LBA LSB 1F2 SC XX 1F1 ER Error information 11 INITIALIZE DEVICE PARAMETERS X917 The host system can set the number of sectors per track and the maximum head number maximum head number is number of heads minus 1 per cylinder with this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is posted Other than X 00 is specified this command terminates normally The parameters set by this command are retained even after reset
115. eleases its own power on reset state the slave device shall report its presence and the result of power on diagnostics to the master device as described below DASP signal Asserted within 400 ms PDIAG signal Negated within 1 ms and asserted within 30 seconds C141 E120 02EN 6 1 Device Response to the Reset V Power on Master device 1 Power On Reset EO Status Reg BSY bit Max 31 sec gt 4 gt i Checks DASP forupto If presence of a slave device is 450 ms confirmed PDIAG is checked for up to 31 seconds Slave device Power On Reset M BSY bit gt 1 ms ENS 1 PDIAG 1 Max 30 sec 1 DASP 2 lt p gt Max 400 ms Figure 6 1 Response to Note Figure 6 1 has a assumption that the device is kept on the power off condition for more than 5 sec before the device power is turned on 6 1 2 Response to hardware reset Response to RESET hardware reset through the interface is similar to the power on reset Upon receipt of hardware reset the master device checks a DASP signal for up to 450 ms to confirm presence of a slave device The master device recognizes the presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully co
116. etting contents 1F7 IEL CM x 5 Tov eae n 1F5 CH Start cylinder address MSB LBA 124 CL Start cylinder address LSB LBA 1F3 SN Start sector No LBA LSB At command completion I O registers contents to be read m ft tots 1F7 ST Status information 1F5 CH End cylinder address MSB LBA 5 16 C141 E120 02EN 5 3 Host Commands CM Command register FR Features register DH Device Head register ST Status register CH Cylinder High register Error register CL Cylinder Low register L LBA logical block address setting bit SN Sector Number register DV Device address bit SC Sector Count register x xx Do not care no necessary to set Note 1 When the L bit is specified to 1 the lower 4 bits of the DH register and all bits of the CH CL and SN registers indicate the LBA bits bits of the DH register are the MSB most significant bit and bits of the SN register are the LSB least significant bit 2 At error occurrence the SC register indicates the remaining sector count of data transfer 3 In the table indicating I O registers contents in this subsection bit indication is omitted 1 READ SECTOR S X 20 or X 21 This command reads data of sectors specified in the Sector Count register from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers Number of sectors can be specified from 1 to 256
117. executed Therefore the number of Emergency other than Normal Unload is specified C141 E120 02EN 1 11 This page is intentionally left blank CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate C141 E120 02EN Device Configuration 2 1 Device Configuration 1 Disk 2 Head Figure 2 1 shows the disk drive The disk drive consists of a disk enclosure DE read write preamplifier and controller PCA The disk enclosure contains the disk media heads spindle motors actuators and a circulating air filter MHN Series Figure 2 1 Disk drive outerview The outer diameter of the disk is 65 mm The inner diameter is 20 mm The number of disks used varies with the model as described below MHN2300AT 2 disks MHM2200AT 2 disks MHM2150AT 1 disk MHM2100AT 1 disk The heads are of the load unload L UL type The head unloads the disk out of while the disk is not rotating and loads on the disk when the disk starts Figure 2 2 illustrates the configuration of the disks and heads of each model In the disk surface servo information necessary for controlling positioning and read write and user data are written Numerals 0 to 3 indicate read write heads C141 E120 02EN 2 1 Device Configuration Hea
118. g table 5 8 The host can access this data using the SMART Read Attribute Thresholds subcommand FR register D1h 5 68 C141 E120 02EN 5 3 Host Commands Table 5 8 Format of device attribute value data 00 Data format version number Roc em 02 03 04 05 OEto 169 Attribute 2 to attribute 30 as that of bytes 02 to OD 16E Reserved Vendoruiqe 07 to 0C 173 Vendor unique 174 Simple self test execution time min 175 Comprehensive self test execution time min 176to 181 Reserved 182 to IFE Vendor unique 1FF Check sum Table 5 9 Format of insurance failure threshold value data Byte Item 01 02 Threshold 1 Attribute ID 03 Insurance failure threshold to 169 Threshold 2 to The format of each threshold value is the same as Threshold 30 that of bytes 02 to OD 16A to 17B Reserved 17C to IFE Vendor unique 1FF Check sum C141 E120 02EN 5 69 Interface e Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds The data format version numbers of the device attribute values and insurance failure thresholds are the same When a data format is changed the data format version numbers are updated e Attribute ID The attribute ID is defined as follows i 2 HDA Tempere SSS 194 HDA Temperature 196 Reallocated Event Count 19 19 Current Pendi
119. ge of a motor and controls the motor speed comparing target speed 4 Controller circuit 4 4 Major functions are listed below e Data buffer 2 MB management interface control and data transfer control e Sector format control e Defect management control e Error recovery and self diagnosis C141 E120 02EN 4 3 Circuit Configuration 5 0V Figure 4 2 Power Supply Configuration C141 E120 02EN 4 5 Theory of Device Operation Data Buffer Flash ROM FROM ATA Interface MCU amp HDC CL E d e neni Pre Am Figure 4 3 Circuit Configuration C141 E120 02EN 4 3 Circuit Configuration 4 4 Power on Sequence Figure 4 4 describes the operation sequence of the disk drive at power on The outline is described below a b c d e After the power is turned on the disk drive executes the MPU bus test internal register read write test and work RAM read write test When the self diagnosis terminates successfully the disk drive starts the spindle motor The disk drive executes self diagnosis data buffer read write test after enabling response to the ATA bus After confirming that the spindle motor has reached rated speed the head assembly is loaded on the disk The disk drive positions the heads onto the SA area and reads out the system information The disk drive executes self seek calibration This collects data for VCM torque and mechanical
120. he Command register The device can accept the command when the BSY bit is 0 the device is not in the busy status The host system can halt the uncompleted command execution only at execution of hardware or software reset C141 E120 02EN 5 13 Interface When the BSY bit is 1 or the DRQ bit is 1 the device is requesting the data transfer and the host system writes to the command register the correct device operation is not guaranteed 5 3 1 Command code and parameters Table 5 3 lists the supported commands command code and the registers that needed parameters are written Table 5 3 Command code and parameters 1 of 2 Command code Bit Parameters used pets fats fata fe bales reste fe fe e EIER SESE EE EIE app vervon wameowa v v v Y wareverny for wamesecrorsy oo sx io fe miauizeevicerarawwenans 0 v 1 nn nn v Ez Command name lt Y lt sms fa fa sermax execute pevicepisewosnic 1 o o o e e r o v wemis ope aom WRITE BUFFER E 5 14 C141 E120 02EN N x n lt lt 2 ES EY Lo X x ER ET Bu Eg EW 2 2 afe ofo nnr ofo ofi EX Ed ed gd a nT e Ed ed eg nT Ed
121. he data buffer of the device by issuing this command Upon receipt of this command the device sets the BSY bit of Status register and sets up for a read operation Then the device sets the DRQ bit of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data from the buffer At command issuance I O registers setting contents 1 7 1F5 p 1F4 CL 1F3 SN 1F2 SC 1F1 FR At command completion I O registers contents to be read Dmm Ts Ps Ps ove 1F5 Y 1F4 CL XX IF3 SN XX 1F2 SC XX 1F1 ER Error information 5 56 C141 E120 02EN 5 3 Host Commands 22 WRITE BUFFER X E8 The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command Upon receipt of this command the device sets the BSY bit of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the buffer then generates an interrupt At command issuance I O registers setting contents iro bi CTT rs 1F5 Ran 1F4 CL 1F3 SN 1F2 SC IF1 FR At command completion I O registers contents to be read eon f e 1F5 cn 184 1F3 SN XX 1F2 SC XX 1F1 ER E
122. hit to the cache data Start LBA Last LBA 1 The disk drive sets the HAP to the address where the partially hit data is stored and sets the DAP to the address just after the partially hit data 587 DAP 2 The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time However the disk drive does not perform the read ahead operation newly HAP Requested data to be transferred stopped gt gt DAP stopped C141 E120 02EN 6 19 Operations 3 The cache data for next read command is as follows Cache data Start LBA Last LBA 6 5 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is physically sequent the data of previous command and random write operation is performed When the drive receives a write command the drive starts transferring data of sectors requested by the host system and writing on the disk medium After transferring data of sectors requested by the host system the drive generates the interrupt of command complete Also the drive sets the normal end status in the Status register The drive continues writing data on the disk medium When all data requested by the host are written on the disk medium actual write operation is completed The drive receives the next command continuously If the received
123. host shall negate CSO CS1 DA2 DAI and DAO The host shall keep 50 CS1 DA2 DAT and DAO negated until after negating DMACK at the end of the burst 6 Steps 3 4 and 5 shall have occurred at least t before the host asserts ACK DMACK The host shall keep DMACK asserted until the end of an Ultra DMA burst 7 The host shall release DD 15 0 within t after asserting DMACK C141 E120 02EN 8 9 10 11 12 5 5 Ultra DMA Feature Set The device may assert DSTROBE t after the host has asserted DMACK Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK at the end of an Ultra DMA burst The host shall negate STOP and assert HDMARDY within t after asserting DMACK After negating STOP and asserting HDMARDY the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device 1 after the first data word has been received The device shall drive DD 15 0 no sooner than t after the host has ZAD asserted DMACK negated STOP and asserted HDMARDY The device shall drive the first word of the data transfer onto DD 15 0 This step may occur when the device first drives DD 15 0 in step 10 To transfer the first word of data the device shall negate DSTROBE within t s after the host has negated STOP and asserted HDMARDY The device shall negate DSTROBE no sooner than
124. ies Terminology This section explains the special terminology used in this manual Abbreviation This section gives the meanings of the definitions used in this manual C141 E120 02EN 1 Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages An alert message consists of an alert signal and alert statements The alert signal consists of an alert symbol and a signal word or just a signal word The following are the alert signals and their meanings A C AUTI ON This indicates a hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly This alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly This indicates information that could help the user IMPORTANT use the product more efficiently In the text the alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example A CAUTION Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages in the text are also listed in the Important Alert Items Operating Environment Attention This produ
125. ignored in this mode 6 2 2 Power commands The following commands are available as power commands e DLE e IDLE IMMEDIATE e STANDBY e STANDBY IMMEDIATE e SLEEP e CHECK POWER MODE C141 E120 02EN 6 3 Defect Management 6 3 Defect Management Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatting at the factory shipment All the user space area are formatted at shipment from the factory based on the default parameters listed in Table 6 1 6 3 1 Spare area Following two types of spare area are provided for every physical head 1 Spare cylinder for sector slip used for alternating defective sectors at formatting in shipment 2 Sparecylinder for alternative assignment used for automatic alternative assignment at read error occurrence 6 3 2 Alternating defective sectors The two alternating methods described below are available 1 Sector slip processing A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in the formatting Figure 6 7 shows an example where physical sector 4 is defective on head 0 in cylinder 0 C141 E120 02EN 6 9 Operations Index er _ sd Sector physical 0 1 0 4 5 6 7 657 658 659 Cylinder 0 TEES
126. in the data buffer e sectors to be processed by the command part of data including load sector to be processed by the command When a part of data to be processed exist in the data buffer remaining data are read from the medium and are transferred to the host system 1 Commands that are object of caching operation Follow commands are object of caching operation e READ SECTOR S e READ MULTIPLE e READDMA When caching operation is disabled by the SET FEATURES command no caching operation is performed 2 Data that are object of caching operation Follow data are object of caching operation 6 12 C141 E120 02EN 1 2 3 6 4 Read Ahead Cache Read ahead data read from the medium to the data buffer after completion of the command that are object of caching operation Data transferred to the host system once by requesting with the command that are object of caching operation except for the cache invalid data by some reasons Remaining data in the data buffer for write command transferred from the host system by the command that writes data onto the disk medium such as the WRITE SECTOR S WRITE DMA WRITE MULTIPLE Followings are definition of in case that the write data is treated as a cache data However since the hit check at issuance of read command is performed to the data buffer for read command preferentially caching write data is limited to the case that the hit check is missed at the data
127. inder are divided into 16 partitions at calibration in the factory and the compensation data is measured for representative cylinder of each partition This measured value is stored in the SA area The compensation value at self calibration is calculated using the value in the SA area 4 5 2 Execution timing of self calibration Self calibration is executed when e power is turned on e disk drive receives the RECALIBRATE command from the host disk drive temperature changes by more than 10 degrees C141 E120 02EN 4 9 Theory of Device Operation 4 5 3 Command processing during self calibration If the disk drive receives a command execution request from the host while executing self calibration according to the timechart the disk drive terminates self calibration and starts executing the command precedingly In other words if a disk read or write service is necessary the disk drive positions the head to the track requested by the host reads or writes data and restarts calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 40 ms 4 6 Read write Circuit The read write circuit consists of the read write preamplifier HDIC the write circuit the read circuit and the time base generator in the read channel RDC Figure 4 4 is a block diagram of the read write circui
128. interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents 1F7 CM X 99 or X E6 OO So fa a x Toe 1F5 y 1F4 CL 1F3 SN 1F2 SC 1F1 FR At command completion I O registers contents to be read Dmm fs Ps Ps ove 1F5 Ten 1F4 CL XX IF3 SN XX 1F2 SC XX 1F1 ER Error information 5 62 C141 E120 02EN 5 3 Host Commands 28 CHECK POWER MODE X 98 or X ES The host checks the power mode of the device with this command The host system can confirm the power save mode of the device by the contents of the Sector Count register The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt Sector Count Sector Count register During moving to standby mode X 00 During returning from the standby mode At command issuance I O setting contents Standby mode 1F7 1F7 CM _ x X98 or XES or X ES mee fa Ts x 1 5 p 1F4 CL 1F3 SN 1F2 SC 1F1 FR At command completion I O registers contents to be read Dmm fs Ps Ps ov 1F5 Ne 1 4
129. isters contents to be read 1F6 me 1F5 CH 1F4 CL 1F3 SN 1 2 8 Password information Words Contents 0 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved e SET MAX LOCK 02h The SET MAX LOCK command sets the device into SET MAX LOCK state After this command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected And the device returns command aborted The device remains in the SET MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed 5 48 C141 E120 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F7 CM 1 1 1 1 1 0 0 1 1F5 CH xx 1F4 CL xx 1F2 SC IF1 FR At command completion I O registers contents to be read 1F6 DH 185 xx 1F4 CL xx IFA SN xx 1F2 SC xx e SET MAX UNLOCK FR 03h This command requests a transfer of single sector of data from the host and defines the contents of SET MAX ADDRESS password The password supplied in the sector of data transferred shall be compared with the stored password If the password compare fails the device returns command aborted and de
130. it indicates that the automatic off line data collection function is enabled Status Byte Meaning 0 Off line data collection is not started 2 Off line data collection has been completed normally 4 Off line data collection has been suspended by a command interrupt 5 Off line data collection has been aborted by a command interrupt 6 Off line data collection has been aborted by a fatal error e Self test execution status Bits 0 to 3 Indicates the rest of self test in 0 to 9 corresponding 0 to 90 Bits 4 to 7 Indicates the self test execution status at the following table C141 E120 02EN 5 71 Interface 5 72 Self test execution status 0 8 to 14 15 Meaning Self test has been completed normally or has not been executed Self test has been stopped by the host computer Self test has been suspended by hard or soft reset Self test has been aborted by a fatal error Self test has been completed abnormally by an unknown meaning Self test has been completed abnormally by write test Self test has been completed abnormally by serbo test Self test has been completed abnormally by read test Reserved Self test is in progress e Off line data collection capability Indicates the method of off line data collection carried out by the drive If the off line data collection capability is 0 it indicates that off line data collection is not supported Bit 0 Meaning Indicates that Execute Off
131. le 1 6 Condition and specification were corrected Section s with asterisk refer to the previous edition when those were deleted C141 E120 02EN This page is intentionally left blank Preface This manual describes the MHN Series 2 5 inch hard disk drives These drives have a built in controller that is compatible with the ATA interface This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems This manual consists of seven chapters and sections explaining the special terminology and abbreviations used in this manual Overview of Manual CHAPTER 1 Device Overview This chapter gives an overview of the MHN Series and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the MHN Series and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the MHN Series 4 Theory of Device Operation This chapter describes the operation theory of the MHN Series CHAPTER 5 Interface This chapter describes the interface specifications of the MHN Series CHAPTER6 Operations This chapter describes the operations of the MHN Ser
132. length between the HA and the disk drive should be as short as possible No need to push the top cover of the disk drive If the over power worked the cover could be contacted with the spindle motor Thus that could be made it the cause of failure This page is intentionally left blank CHAPTER 3 Installation Conditions 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections 3 4 Jumper Settings This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives For information about handling this hard disk drive and the system installation procedure refer to the following Integration Guide C141 E144 C141 E120 02EN 3 1 Installation Conditions 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm 100 0 4 90 6 0 25 3 99 0 25 14 0 26 69 85t0 25 10 Figure 3 1 Dimensions 3 2 C141 E120 02EN 3 2 Mounting 3 2 Mounting 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive gravity Y gravity Y gravity e Vertical 3 f Vertical 4 Figure 3 2 Orientation C141 E120 02EN 3 3 Installation Conditions 2 Frame The MR head bias of the HDD
133. master password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the security level in LOCKED MODE is set to the highest level the Aborted Command error is always returned When the user password is selected The password is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the 5 82 C141 E120 02EN 5 3 Host Commands UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT command causes the Aborted Command error until the device is turned off and then on or until a hardware reset is executed Issuing this command with LOCKED MODE canceled in UNLOCK MODE has no affect on the UNLOCK counter Issuing this command in FROZEN MODE returns the Aborted Command error At command issuance I O register contents may t 1 1 1 0 o 1 9 mem i x 1F5 CH 1F4 CL 1F3 SN 1F2 SC 1F1 FR At command completion I O register contents fs Ps x pee 1F5 6 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 36 FLUSH CACHE E7 This command is used to order to write every write cache data stored by the device into the medium BSY bit is held at 1 until every dat
134. mber Table 5 15 Relationship between combination of Identifier and Security level and operation of the lock function User High The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password or the master password already set Master High The specified password is saved as a new master password The lock function is not enabled User Maximum The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password only The master password already set cannot cancel LOCKED MODE Master Maximum The specified password is saved as a new master password The lock function is not enabled C141 E120 02EN 5 81 Interface At command issuance I O register contents 1F7 CM 1 1 1 1 0 0 0 1 1 5 xx IFA CL xx 183 SN xx 1F2 SC xx IFL FR xx 1F5 CH xx 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 35 SECURITY UNLOCK This command cancels LOCKED MODE The host transfers the 512 byte data shown in Table 5 12 to the device Operation of the device varies as follows depending on whether the host specifies the master password When the master password is selected When the security level is LOCKED MODE is high the password is compared with the
135. mpleted the self diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected C141 E120 02EN 6 3 Operations After the slave device receives the hardware reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below DASP signal Asserted within 400 ms PDIAG signal Negated within 1 ms and asserted within 30 seconds Reset Master device Status Reg BSY bit Max 31 sec m uu 4 gt fpresence of a slave device is Checks DASP for up to confirmed PDIAG is checked for 1450 mS up to 31 seconds Slave device BSY bit 1 1 ms 1 PDIAG Max 30 sec DASP um RN RC gt Max 400 ms Y Figure 6 2 Response to hardware reset Note Master Device does not check the DASP signal assertion for 2ms upon receipt of hardware reset 6 4 C141 E120 02EN 6 1 Device Response to the Reset 6 1 3 Response to software reset The master device does not check the DASP signal for a software reset If a slave device is present the master device checks the PDIAG signal for up to 15 seconds to see if the slave device has completed the self diagnosis successfully After the slave device receives the software reset the slave device shall report its presence and the result of the self
136. n the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at which the system operates The Ultra DMA Mode selected by a host shall be less than or equal to the fastest mode of which the device is capable Only the Ultra DMA Mode shall be selected at any given time All timing requirements for a selected Ultra DMA Mode shall be satisfied Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and 1 Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA Mode 0 An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after executing a Software reset sequence An Ultra DMA capable device shall clear any previously selected Ultra DMA Mode and revert to its default non Ultra DMA Modes after executing a Power on or hardware reset Both the host and device perform a CRC function during an Ultra DMA burst At the end of an Ultra DMA burst the host sends the its CRC data to the device The C141 E120 02EN 5 99 Interface device compares its CRC data to the data sent from the host If the two values do not match the device reports an error in the error register at the end of the command If an error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred 5 5 2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts Each Ultr
137. ng Sector Count 9 9 6 i Ou oo 20 e Status Flag If this bit 1 it indicates that if the attribute exceeds the threshold it is the attribute covered by the drive warranty If this bit is 1 0 it indicates the attribute only updated by an on line test off line test If this bit 1 it indicates the attribute that represents performance 5 70 C141 E120 02EN 5 3 Host Commands If this bit 1 it indicates the attribute that represents an error rate If this bit 1 it indicates the attribute that can be collected saved even if the drive fault prediction function is disabled Current attribute value 4 If this bit 1 it indicates the attribute that represents the number of occurrences The current attribute value is the normalized raw attribute data The value varies between O1h and 64h The closer the value gets to O1h the higher the possibility of a failure The device compares the attribute values with thresholds When the attribute values are larger than the thresholds the device is operating normally e Attribute value for the worst case so far This is the worst attribute value among the attribute values collected to date This value indicates the state nearest to a failure so far e Raw attribute value Raw attributes data is retained e Off line data collection status Bits 0 to 6 Indicates the situation of off line data collection according to the table below Bit 7 If this bit is 1
138. nt switching points low to high and high to low shall be taken at 1 5V C141 E120 02EN 5 115 Interface Table 5 19 Ultra DMA sender and recipient timing requirements MODEO MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 in ns in ns in ns in ns in ns in ns NAME COMMENT ties 14 7 9 7 4 8 2 3 Recipient IC data setup time from data valid until STROBE edge ED Luc 4 8 4 8 4 8 4 8 4 8 2 8 Recipient IC data hold time from STROBE edge until data may become invalid 1 72 9 50 9 33 9 22 6 9 5 Sender IC data valid setup time from data valid until STROBE edge 2 Eus Sender IC data valid hold time from STROBE edge until data may become invalid 2 The correct data value shall be captured by the recipient given input data with a slew rate of 0 4 V ns rising and falling and the input STROBE with a slew rate of 0 4 V ns rising and falling at t and t timing as measured through 1 5V 2 The parameters and t shall be met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the same capacitive load value Noise that may couple onto the output signals from external sources in a normally functioning system has not been included in these values Note All timing measurement switching points low to high and high to low shall be taken at 1 5V 5 116 C141 E120 02EN 5 6 Timing 5 6 3 3 Sustained Ultra DMA data in burst 5 6 3 2 contains the values for the timing
139. ny one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DDMARDY within t DMACK after the host has negated IORDYZ C141 E120 02EN 5 5 Ultra DMA Feature Set 13 The host shall neither negate STOP nor HSTROBE until at least t after negating DMACK 14 The host shall not assert DIOW CSO CS1 DA2 DAI or DAO until at least after negating DMACK 5 5 5 Ultra DMA CRC rules The following is a list of rules for calculating CRC determining if a CRC error has occurred during an Ultra DMA burst and reporting any error that occurs at the end of a command a b d g h C141 E120 02EN Both the host and the device shall have a 16 bit CRC calculation function Both the host and the device shall calculate a CRC value for each Ultra DMA burst The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred For each STROBE transition used for data transfer both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged At the end of any Ultra DMA burst the host shall send
140. of one byte information posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly C141 E120 02EN GL 3 This page is intentionally left blank ABRT AIC AMNF ATA AWG BBK BIOS CORR CH CL CM CSR CSS CY dBA DE DH DRDY DRQ DSC DWF ECC ER ERR FR HA Acronyms and Abbreviations A Aborted command Automatic idle control Address mark not found AT attachment American wire gage B Bad block detected Basic input output system C Corrected data Cylinder high register Cylinder low register Command register Current sense register Current start stop Cylinder register D dB A scale weighting Disk enclosure Device head register Drive ready Ddata request bit Drive seek complete Drive write fault E Error checking and correction Error register Error F Feature register H Host adapter C141 E120 02EN HDD IDNF 18014 LED MB MB S MPU PCA PIO RLL SA 5 SG SN ST TPI TRONF Typ UNC VCM Hard disk drive ID not found Interrupt request 14 L Light emitting diode Mega byte Mega byte per seconds Micro processor unit P Printed circuit assembly Programmed input output R Run length limited S System area Sector coun
141. on on DD 15 0 The device shall latch the host s CRC data from DD 15 0 on the negating edge of DMACK The device shall compare the CRC data received from the host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 The device shall release DDMARDY within t negated DMACK after the host has IORDYZ The host shall neither negate STOP nor negate HSTROBE until at least t 4 after negating DMACK The host shall not assert DIOW CSO 1 DA2 DAI or DAO until at least after negating DMACK 5 107 Interface 5 108 b Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 11 and 5 6 3 2 for specific timing requirements 1 2 3 4 5 6 7 8 9 10 11 12 The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred The device shall initiate Ultra DMA burst termination by negating DDMARDY The host shall stop generating an HSTROBE edges within t of the device negating DDMARDY If the device negates DDMARDY within t after the host has generated an HSTROBE edge then the device shall be prepared to receive zero or one
142. oning speed The average positioning time is 12 ms at read 1 1 2 Adaptability 1 Power save mode The power save mode feature for idle operation stand by and sleep modes makes The disk drives the MHN Series ideal for applications where power consumption is a factor 2 Wide temperature range The disk drives the MHN Series can be used over a wide temperature range 5 C to 55 C 3 Low noise and vibration In Ready status the noise of the disk drives the MHN Series is only about 24 dBA measured at 1 m apart from the drive under the idle mode 4 High resistance against shock The Load Unload mechanism is highly resistant against non operation shock up to 7840 m s 800G 1 2 C141 E120 02EN 1 1 Features 1 1 3 Interface 1 Connection to interface With the built in ATA interface controller the disk drives the MHN Series can be connected to an ATA interface of a personal computer 2 2 MB data buffer The disk drives the MHN Series use a 2 MB data buffer to transfer data between the host and the disk media In combination with the read ahead cache system described in item 3 and the write cache described in item 7 the buffer contributes to efficient I O processing 3 Read ahead cache system After the execution of a disk read command the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system enables fast dat
143. oop air cycle system operated by a blower on the rotating disk C141 E120 02EN 4 3 Theory of Device Operation 4 3 Circuit Configuration Figure 4 2 shows the power supply configuration of the disk drive and Figure 4 3 shows the disk drive circuit configuration 1 Read write circuit The read write circuit consists of two LSIs read write preamplifier PreAMP and read channel RDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Modified Extended Partial Response MEEPR and contains the Viterbi detector programmable filter adaptable transversal filter times base generator data separator circuits 16 17 MTR Maximum Transitions Limited encoder Run Length and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coil motor The MPU precisely sets each head on the track according on the servo information on the media surface 3 Spindle motor driver circuit The circuit measures the interval of a PHASE signal generated by counter electromotive volta
144. or power save operation regardless of the setting of disabling the reverting to default setting The device ignores the L bit specification and operates with only CHS mode specification C141 E120 02EN 5 29 Interface At command issuance I O registers setting contents TT Ter Med No 1F5 FS 1F4 CL XX 1F3 SN XX IF2 SC Number of sectors track 1F1 FR XX At command completion I O registers contents to be read mum a e bv Mina 1F5 ap 1F4 CL XX 1F3 SN XX IF2 SC Number of sectors track 1F1 ER Error information 12 IDENTIFY DEVICE X EC The host system issues the IDENTIFY DEVICE command to read parameter information from the device Upon receipt of this command the drive sets the BSY bit to one prepares to transfer the 256 words of device identification data to the host sets the DRQ bit to one clears the BSY bit to zero and generates an interrupt After that the host system reads the information out of the sector buffer Table 5 4 shows the values of the parameter words and the meaning in the buffer 5 30 C141 E120 02EN 5 3 Host Commands 13 IDENTIFY DEVICE DMA X EE When this command is not used to transfer data to the host in DMA mode this command functions in the same way as the Identify Device command At command issuance I O registers setting contents ire bu III 1F5 XH 1 4 CL 1F3 SN 1F2 SC 1F1 FR At command completion I O registers
145. orce Then rotation of the spindle motor accelerates The MPU calculates a rotational speed of the spindle motor based on the PHASE signal from the SVC and waits till the rotational speed reaches 4 200 rpm When the rotational speed reaches 4 200 rpm the SVC enters the stable rotation mode 3 Stable rotation mode The SVC calculates a time for one revolution of the spindle motor based on the PHASE signal The MPU takes a difference between the current time and a time for one revolution at 4 200 rpm that the MPU already recognized Then the MPU keeps the rotational speed to 4 200 rpm by charging or discharging the charge pump for the different time For example when the actual rotational speed is 4 000 rpm the time for one revolution is 15 000 ms And the time for one revolution at 4 200 rpm is 14 286 ms Therefore the MPU charges the charge pump for 0 714 ms x k constant value This makes the flowed current into the motor higher and the rotational speed up When the actual rotational speed is faster than 4 200 rpm the MPU discharges the pump the other way This control charging discharging is performed every 1 revolution C141 E120 02EN 4 23 This page is intentionally left blank CHAPTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 3 5 Ultra DMA Feature Set 5 6 Timing This chapter gives details about the interface and the interface commands
146. r a hard reset occurs and the maximum address returns to the value default value if not set most lately set when VV bit 1 After power on and the occurrence of a hard reset the host can issue this command only once when VV bit 1 If this command with VV bit 1 is issued twice or more any command following the first time will result in an Aborted Command error At command issuance I O registers setting contents 1F7 CM 1 1 1 1 1 0 0 1 Martes M 1F5 CH Max cylinder MSB Max LBA IFA CL Max cylinder LSB Max LBA 1F3 SN Max sector Max LBA LSB 5 46 C141 E120 02EN 5 3 Host Commands At command completion I O registers contents to be read 1F6 DH Max head LBA MSB 1F5 CH Max cylinder MSB Max LBA 1FA CL Max cylinder LSB Max LBA 1F3 SN Max sector Max LBA LSB e SET MAX SET PASSWORD FR 01h This command requests a transfer of 1 sector of data from the host and defines the contents of SET MAX password The password is retained by the device until the next power cycle The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed At command issuance I O registers setting contents 1F7 CM 1 1 1 1 1 0 0 1 1F2 SC IF1 FR IFS CH IFA CL xx C141 E120 02EN 5 47 Interface At command completion I O reg
147. r occurred during Ultra DMA transfer Bit6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found This bit indicates an error except for bad sector uncorrectable error and SB not found Bit 3 Unused Bit 2 Aborted Command ABRT This bit indicates that the requested command was aborted due to a device status error e g Not Ready Write Fault or the command code was invalid Bit 1 Track 0 Not Found TKONF This bit indicates that track 0 was not found during RECALIBRATE command execution 0 Address Mark Not Found AMNF This bit indicates that the SB Not Found error occurred 5 8 C141 E120 02EN 5 2 Logical Interface Diagnostic code X 01 No Error Detected X 02 Register Compare Error X 03 Data Buffer Compare Error X 05 ROM Sum Check Error X 80 Device 1 slave device Failed Error register of the master device is valid under two devices master and slave configuration If the slave device fails the master device posts X 80 OR the diagnostic code with its own status X 01 to X 05 However when the host system selects the slave device the diagnostic code of the slave device is posted 3 Features register X 1F1 The Features register provides specific feature to a command For instance it is used with SET FEATURES command to enable
148. r at each device The host system asserts this signal as a response that the host system receive data or to indicate that data is valid 5 5 Interface signal Description DMARQ O This signal is used for DMA transfer between the host system and the device The device asserts this signal when the device completes the preparation of DMA data transfer to the host system at reading or from the host system at writing The direction of data transfer is controlled by the DIOR and DIOW signals This signal hand shakes with the DMACK signal In other words the device negates the DMARQ signal after the host system asserts the DMACK signal When there is other data to be transferred the device asserts the DMARQ signal again When the DMA data transfer is performed IOCS16 CSO and CS1 signals are not asserted The DMA data transfer is 16 bit data transfer 5 VDC I 5 VDC power supplying to the device GND Grounded signal at each signal wire Note indicates input signal from the host to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device 5 2 Logical Interface 5 6 The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports the LBA mo
149. r by the interrupt generated periodically compares with the target revolution speed then flows the current into the motor coil according to the differentiation aberration 6 Driver circuit The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor 7 VCM current sense resistor CSR This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back C141 E120 02EN 4 17 Theory of Device Operation 4 7 2 Data surface servo format Figure 4 8 describes the physical layout of the servo frame The three areas indicated by 1 to 3 in Figure 4 8 are described below 1 Inner guard band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving 4 18 C141 E120 02EN CYLn 1 CYLn CYLn 1 n even number W R Recovery W R Recovery W R Recovery Servo Mark Servo Mark Servo Mark Gray Code Gray Code Gray Code Erase Servo A Erase Servo A Servo B Erase Servo B Erase Servo C Erase Servo C Erase Servo D Erase PAD
150. r password already set The device erases user data invalidates the user password and releases the lock function if the passwords are the same C141 E120 02EN 5 3 Host Commands Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued the Aborted Command error is returned Issuing this command while in FROZEN MODE returns the Aborted Command error At command issuance I O register contents Len S T T3 Tee 1F5 D 1F4 CL 1F3 SN 1F2 SC 1 1 At command completion I O register contents rooms Ps Ps pvp 1F5 p 1F4 CL XX 1F3 SN XX 1F2 SC XX 1F1 ER Error information 33 SECURITY FREEZE LOCK F5h This command puts the device into FROZEN MODE The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE e SECURITY SET PASSWORD e SECURITY UNLOCK e SECURITY DISABLE PASSWORD e SECURITY ERASE PREPARE C141 E120 02EN 5 79 Interface e SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off or when hardware is reseted If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged Issuing this command during LOCKED MODE returns
151. refer to the ambient temperature at a point 3 cm from the disk drive The ambient temperature must satisfy the temperature conditions described in Section 1 4 and the airflow must be considered to prevent the DE surface temperature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperature measurement points Table 3 1 Surface temperature measurement points and standard values Measurement point 3 6 C141 E120 02EN 3 2 Mounting 5 Service area Figure 3 6 shows how the drive must be accessed service areas during and after installation Mounting screw hole Cable connection Mounting screw hole Figure 3 6 Service area A CAUTION Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kQ or greater Do not touch the printed circuit board but hold it
152. ress of the received read command the disk drive transfers the hit data in the buffer to the host system The disk drive performs the read ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system 6 16 C141 E120 02EN 6 4 Read Ahead Cache 1 Inthe case that the contents of buffer is as follows at receiving a read command HAP Continued from the previous read request data DAP 5 Last LBA Start LBA exe 2 The disk drive starts the read ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring E a 5 DAP 3 After completion of data transfer of hit data the disk drive performs the read ahead operation for the data area of which the disk drive transferred hit data 2 aS C141 E120 02EN 6 17 Operations 4 Finally the cache data in the buffer is as follows Start LBA Last LBA c Non sequential command immediately after sequential command When a sequential read command first read has been executed the first read operation should be stopped if a non sequential read command has been received and then ten or more of the non sequential read commands have been received Refer to 6 5 3 1 The figure that describes the first read operation is the sam
153. rocessing for the DMA transfer differs the following point The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register The host initializes the DMA channel The host writes a command code in the Command register The device sets the BSY bit of the Status register The device asserts the DMARQ signal after completing the preparation of data transfer The device asserts either the BSY bit or DRQ bit during DMA data transfer When the command execution is completed the device clears both BSY and DRQ bits and asserts the INTRQ signal Then the host reads the Status register The host resets the DMA channel Figure 5 7 shows the correct DMA data transfer protocol C141 E120 02EN 5 97 Interface Parameter write v Command Status read V transfer Expanded Multiword DMA transfer DRQ d Lo DMARQ _ _ _ md DMACK e a IOR SUV or IOW LI L Word 0 n 1 n Figure 5 7 Normal DMA data transfer 5 98 C141 E120 02EN 5 5 Ultra DMA Feature Set 5 5 Ultra DMA Feature Set 5 5 1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host This protocol applies to the Ultra DMA data burst only When this protocol is used there are no changes to other element
154. rror information C141 E120 02EN 5 57 Interface 23 IDLE X 977 or X E3 5 58 Upon receipt of this command the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the idle mode If the spindle of the device is already rotating the spin up sequence shall not be implemented By using this command the automatic power down function is enabled and the timer immediately starts the countdown When the timer reaches the specified value the device enters standby mode Enabling the automatic power down function means that the device automatically enters the standby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts countdown after completion of the command execution The period of timer count is set depending on the value of the Sector Count register as shown below At command issuance I O registers setting contents 1F7 CM X 9T or X E3 XX 5 1F4 XX IF3 SN XX 1F2 SC Period of timer C141 E120 02EN 5 3 Host Commands A
155. rs contain the cylinder head and sector addresses of the last sector written C141 E120 02EN 5 3 Host Commands If an error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Command block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred At command issuance I O registers setting contents 1 6 DID Start head No LBA MSB 1 5 1F4 CL 1F3 SN 1F2 SC IF1 FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count XX At command completion I O registers contents to be read IF6 DH End head No LBA MSB 1 5 1F4 CL 1F3 SN 1 2 8 IF1 ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register C141 E120 02EN 5 23 Interface 6 WRITE MULTIPLE X C5 5 24 This command is similar to the WRITE SECTOR S command The device does not generate interrupts assertion of the INTRQ signal on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MOD
156. s 11 84 Support of command sets function 12 59 62 63 64 65 67 Werd 2536 ki 4s EA 50 st O5 NN DT 22 E 6 ON C141 E120 02EN 5 33 Interface Table 5 4 Information to be read by IDENTIFY DEVICE command 3 of 8 Wor 8 8 8 9 9 9 1 5 7 8 1 2 Variablo 9 T 129 159 X 0000 Undefined 255 5 Check sum The 2 complement of the lower order byte resulting from summing bits 7 to 0 of word 0 to 254 and word 255 in byte units Word 0 General configuration Bit 15 ATA device 0 ATAPI device 1 Bit 14 8 Undefined Bit 7 Removable disk drive 1 Bit 6 Fixed drive 1 Bit 5 3 Undefined Bit 2 IDENTIFY DEVICE Valid 0 Bit 1 0 Reserved 2 Word 1 3 6 60 61 MHN2100AT Word 01 X 3FFF Word 03 xo Word 06 Word 60 61 X I2BB230 3 Word 49 Capabilities Bit 15 14 Reserved 5 34 C141 E120 02EN 4 gt 6 7 8 C141 E120 02EN 5 3 Host Commands Bit 13 Standby timer value Factory default is 0 ATA spec is 1 Bit 12 Reserved Bit 11 1 Supported Bit 10 0 Disable inhibition Bit 7 0 Undefined Bit 8 1 LBA Supported Bit 9 1 DMA Supported Word 51 PIO data transfer mode Bit 15 8 PIO data transfer mode X 02 PIO mode 2 Bit 7 0 Undefined Word 53 Enable disable setting of word 54 58 and 64 70 Bit 15 3 Reserved Bit 2 1 En
157. s a status to the host system The format of the error information is the same as the WRITE SECTOR S command C141 E120 02EN 5 25 Interface A host system can select the following transfer mode using the SET FEATURES command e Multiword DMA transfer mode 0 to 2 e Ultra DMA transfer mode 0 to 5 At command issuance registers setting contents i 1 1F6 on Start head No LBA MSB 5 Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1F3 SN Start sector No LBA LSB 1F2 SC Transfer sector count IFL FR At command completion I O registers contents to be read 1F6 DH End head No LBA MSB 1 5 End cylinder No MSB LBA 1F4 CL End cylinder No LSB LBA 1F3 SN End sector No LBA LSB 1F2 SC 00 1 1F1 ER Error information command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command except that the device verifies each sector immediately after being written The verify operation is a read and check for data errors without data transfer Any error that is detected during the verify operation is posted After all sectors are verified the last interruption INTRQ for command termination is generated 5 26 C141 E120 02EN 5 3 Host Commands
158. s for each of the Ultra DMA Modes DSTROBE at device DD 15 0 at device DSTROBE at host tou tps tonic 00 15 0 at host Note DD 15 0 and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 12 Sustained Ultra DMA data in burst C141 E120 02EN 5 117 Interface 5 6 3 4 Host pausing an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device DMACK host STOP host HDMARDY host DSTROBE device Ga X XX Notes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY is negated 2 After negating HDMARDY the host may receive zero one two or three more data words from the device Figure 5 13 Host pausing an Ultra DMA data in burst 5 118 C141 E120 02EN 5 6 Timing 5 6 3 5 Device terminating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes DMARQ device tui DMACK host tack ae STOP h qe host tack HDMARDY host 2 DSTROBE device gt 7 CRO DD 15 0
159. s of the ATA protocol e g Command Block Register access Several signal lines are redefined to provide new functions during an Ultra DMA burst These lines assume these definitions when 1 an Ultra DMA Mode is selected and 2 a host issues a READ DMA or a WRITE DMA command requiring data transfer and 3 the host asserts DMACK These signal lines revert back to the definitions used for non Ultra DMA transfers upon the negation of DMACK by the host at the termination of an Ultra DMA burst All of the control signals are unidirectional DMARQ DMACK retain their standard definitions With the Ultra DMA protocol the control signal STROBE that latches data from DD 15 0 is generated by the same agent either host or device that drives the data onto the bus Ownership of DD 15 0 and this data strobe signal are given either to the device during an Ultra DMA data in burst or to the host for an Ultra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is capable of supporting The Set transfer mode subcommand i
160. set Bit 3 2 Supports the power management feature set Bit 2 Supports the Removable Media feature set Bit 1 Supports the Security Mode feature set Bit 0 2 Supports the SMART feature set 11 WORD 83 Bits 15 14 Undefined Bit 13 1 FLUSH CACHE EXT command supported 5 36 C141 E120 02EN 12 WORD 84 13 WORD 85 C141 E120 02EN Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 5 3 Host Commands 1 FLUSH CACHE command supported Device Configuration Overlay feature set supported 1 48 bit LBA feature set Automatic Acoustic Management feature set Supports the SET MAX Security extending command Reserved When the power is turned on spin is started by the SET FEATURES sub command Supports the Power Up In Standby set Supports the Removable Media Status Notification feature set 2 Supports the Advanced Power Management feature set Supports the CFA Compact Flash Association feature set Supports the READ WRITE DMA QUEUED command 1 Supports the DOWNLOAD MICROCODE command Undefined Supports the Media Serial Number Supports the SMART SELF TEST Supports the SMART Error Logging Undefined Enables the NOP command
161. specified by this value When the error log index exceeds 05 it returns to 01 Command data 1 to 5 Indicates five commands data in order received by the device until the error occurs Commands for which an error occurred are included in Command Data 5 e Error data Indicates the I O register values when the error is reported e Status Bits O to 3 Indicates the drive status when received error commands according to the following table Bits 4 to 7 Vendor unique Status Meaning 0 Unclear status 1 Sleep status 2 Standby status 3 Active status or idle status BSY bit 0 4 Off line data collection being executed ct o Reserved e SMART Self Test The host computer can issue the SMART Execute Off line Immediate sub command FR Register D4h and cause the device to execute a self test When the self test is completed the device saves the SMART self test log to the disk medium The host computer can issue the SMART Read Log Sector sub command FR Register D5h SN Register 06h and can read the SMART self test log C141 E120 02EN 5 75 Interface Byte Table 5 12 SMART self test log data format 00 01 Self test log data format version number 0 0 2 3 Self test log 1 Self test mode SN Register Value 04 05 Total power on time until the self test is completed hours Self test error No 07 to OA Error LBA OB to 19 Vendor unique to 1F9 Self test log 2 to 21 Each log
162. st one data word of an Ultra DMA burst has been transferred The host shall pause an Ultra DMA burst by not generating an HSTROBE edge Note The device shall not immediately negate DMARQ to initiate Ultra burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait t before negating DMARQ The host shall resume an Ultra DMA burst by generating an HSTROBE edge Device pausing an Ultra DMA data out burst 1 2 3 4 5 The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred The device shall pause an Ultra DMA burst by negating DDMARDY The host shall stop generating HSTROBE edges within t of the device negating DDMARDY If the device negates DDMARDY within t after the host has generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than t x after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and t timing for the host The device shall resume an Ultra DMA burst by asserting DDMARDY C141 E120 02EN 5 5 Ultra DMA Feature Set 5 5 4 4 Terminating an Ultra DMA data out burst a
163. t 4 6 1 Read write preamplifier HDIC HDIC equips a read preamplifier and a write current switch that sets the bias current to the MR device and the current in writing Each channel is connected to each data head and HDIC switches channel by serial I O HDIC generates a write unsafe signal WUS when a write error occurs due to head short circuits or head disconnection that avoids error writing 4 6 2 Write circuit The write data is output from the hard disk controller HDC with the NRZ data format and sent to the encoder circuit in the RDC The NRZ write data 1s converted from 16 bit data to 17 bit data by the encoder circuit then sent to the HDIC and the data is written onto the media 1 16 17 MTR MEEPRML This device converts data using the 16 17 MTR Maximum Transitions Run Length Limited algorithm This code is converted so that a maximum of three 1 s are placed continuously and so that there are two or fewer 1 s in a 17 bit border 2 Write precompensation Write precompensation compensates during a write process for write non linearity generated at reading Table 4 1 shows the write precompensation algorithm 4 10 C141 E120 02EN C141 E120 02EN Table 4 1 Write precompensation algorithm 111001 111010 111111 000000 000001 010000 100000 4 6 Read write Circuit Theory of Device Operation HDIC WDX WDY RDX RDY pem IO Lr Write Lr PreCompen sation
164. t command completion I O registers contents to be read mes Ip IIS 1 5 en 1F4 CL 1F3 SN 1F2 SC IF1 ER XX XX XX Error information 24 IDLE IMMEDIATE X 95 or X ET Upon receipt of this command the device sets the BSY bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance I O registers setting contents X 95 or XEL mon fa a 1F5 E 1F4 CL 1F3 SN 1F2 SC IF1 FR At command completion I O registers contents to be read Ps Tx Px 1 5 NS 1F4 CL 1F3 SN 1F2 SC 1F1 C141 E120 02EN XX XX XX Error information 5 59 Interface 25 STANDBY X 96 or X E2 5 60 Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the standby mode If the device has already spun down the spin down sequence is not implemented By using this command the automatic power down function is enabled and the timer starts the countdown when the device returns to idle mode When the timer value reaches 0 a specified time has padded the device enters standby mode Under the standby mode the spindle motor is stopp
165. t numbers 1 5 Current and power dissipation 1 6 Environmental specifications 1 7 Acoustic noise specification 1 8 Shock and vibration specification 1 8 Surface temperature measurement points and standard values 3 6 Cable connector specifications 3 10 Write precompensation algorithm 4 11 XV Contents xvi Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Table 5 10 Table 5 11 Table 5 12 Table 5 13 Table 5 14 Table 5 15 Table 5 16 Table 5 17 Table 5 18 Table 5 19 Signal assignment on the interface connector 5 3 VO registers 5 7 Command code and parameters 5 14 Information to be read by IDENTIFY DEVICE command 5 32 Features register values and settable modes 5 41 Diagnostic code 5 53 Features Register values subcommands and functions 5 65 Format of device attribute value data 5 69 Format of insurance failure threshold value data 5 69 Log Directory Data Format 5 73 SMART error log data format 5 74 SMART self test log data format 5 76 Contents of security password 5 77 Contents of SECURITY SET PASSWORD data 5 81 Relationship between combination of Identifier and Security level and operation of the lock function 5 81 DEVICE CONFIGURATION IDENTIFY data structure 5 87 Command code and parameters 5 88 Ultra DMA data burst timing requirements 5 114 Ultra DMA sender and recipient timing requirements 5 116 C141 E120 02EN CHAPTER 1 Device Overview
166. t register Signal ground Sector number register Status register T Track per inches Track 0 not found Typical U Uncorrectable ECC error V Voice coil motor AB 1 This page is intentionally left blank Comment Form We would appreciate your comments and suggestions regarding this manual Manual code C141 E120 02EN MHN2300AT MHN2200AT MHN2150AT MHN2100AT DISK DRIVES PRODUCT MANUAL Please mark each item E Excellent G Good F Fair P Poor Illustration Technical level Glossary Organization Acronyms amp Abbreviations General appearance Clarity Index Accuracy Comments amp Suggestions List any errors or suggestions for improvement Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 22 7 Minami Ooi 6 Chome Shinagawa Ku Tokyo 140 0013 JAPAN Fax 81 3 5762 8073 Organization Name C141 E120 02EN This page is intentionally left blank MHN2300AT MHN2200AT MHN2150AT MHN2100AT EE DISK DRIVES PRODUCT MANUAL x MHN2300AT MHN2200AT MHN2150AT MHN2100AT TERES DISK DRIVES PRODUCT MANUAL This page is intentionally left blank co FUJITSU
167. tars selection stp tie for DIOR DOW 23 c recovery s 9 s 2 4 Daanoia sme torpiow s is Time from DIOR assertion to read 50 os 6 aoaeeoo __ 5 19 Data register selection hold ine for DIORDOW w Time from DIOR DIOW assertion to IORDY low level X Time from validity of read data to IORDY high level E GEEWE us 1050 ss Figure 5 9 PIO data transfer timing C141 E120 02EN 5 111 Interface 5 6 2 Multiword data transfer Figure 5 10 shows the multiword DMA data transfer timing between the device and the host system 0 lt gt DMARQ DMACK A A AE tK DIOR DIOW a ae tb A Write data l N DD0 DD15 uc WO Read data S 200 0015 N s foam Det ine om DMACK accion MARI pam e Joe Ce pemuaempos we pacera ime Domow Figure 5 10 Multiword data transfer timing mode 2 5 112 C141 E120 02EN 5 6 Timing 5 6 3 Ultra DMA data transfer Figures 5 11 through 5 20 define the timings associated with all phases of Ultra DMA bursts Table 5 20 contains the values for the timings for ea
168. th devices execute self diagnosis If device 1 is present e Both devices shall execute self diagnosis e device 0 waits for up to 5 seconds until device 1 asserts the PDIAG signal e Ifthe device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status e The device 0 clears the BSY bit of the Status register and generates interrupt The device 1 does not generate an interrupt e diagnostic status of the device 0 is read by the host system When a diagnostic failure of the device 1 is detected the host system can read a status of the device 1 by setting the DV bit selecting the device 1 When device 1 is not present e device 0 posts only the results of its own self diagnosis e The device 0 clears the BSY bit of the Status register and generates an interrupt Table 5 6 lists the diagnostic code written in the Error register which is 8 bit code If the device 1 fails the self diagnosis the device 0 ORs X 80 with its own status and sets that code to the Error register C141 E120 02EN 5 3 Host Commands Table 5 6 Diagnostic code Result of diagnostic No error detected Data buffer compare error ROM sum check error Failure of device 1 attention The device responds to this command with the result of power on diagnostic test At command issuance I O registers setting contents Ts Ts To 1F
169. the Sector Count register with the desired power management level and executes this command with the Features register X 05 and then Advanced Power Management is enabled The drive automatically shifts to power saving mode up to the specified APM level when the drive does not receive any command for a specific time The power management level is shifted from Active Idle and Low power Idle to Standby The Mode 3 takes the maximum shifting time in the APM level The APM level setting is preserved by the drive across power on hardware and software resets APM Level Mode 0 Low Power Idle Mode 1 Low Power Idle Mode 2 Standby Mode 3 Reserved Standby Active Idle Low Power Idle Sector Count register COh FEh 80h BFh 40h 7Fh 01h 3Fh FFh 00h from the ramp Standby unloaded from the ramp 3 Automatic Acoustic Management AAM The spindle motor is rotating and heads are loaded on the medium The spindle motor is rotating and heads are unloaded The spindle motor is not rotating and heads are The host writes to the Sector Count register with the requested acoustic management level and executes this command with subcommand code 42h and C141 E120 02EN 5 43 Interface then Automatic Acoustic Management is enabled The AAM level setting is preserved by the drive across power on hardware and software resets Sector Count register Standard Seek COh FEh 00h Slow Seek 80h BFh Reserved
170. the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMa burst in the same command If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred For READ DMA or WRITE DMA commands When a CRC error is detected it shall be reported by setting both ICRC and ABRT bit 7 and bit 2 in the Error register to one ICRC is defined as the Interface CRC Error bit The host shall respond to this error by re issuing the command A host may send extra data words on the last Ultra DMA burst of a data out command If a device determines that all data has been transferred for a command the device shall terminate the burst A device may have already received more data words than were required for the command These extra words are used by both the host and the device to calculate the CRC but on an Ultra DMA data out burst the extra words shall be discarded by the device 5 109 Interface i The CRC generator polynomial is G X X16 X12 X5
171. to the READ SECTOR S command except for following events data transfer starts at the timing of DMARQ signal assertion device controls the assertion or negation timing of the DMARQ signal e device posts a status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode are set The host system can select the DMA transfer mode by using the SET FEATURES command e Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 5 C141 E120 02EN 5 3 Host Commands At command issuance I O registers setting contents 1F6 OH Start head No LBA MSB 1F5 CH Start cylinder No MSB LBA 1F4 CL Start cylinder No LSB LBA 1F3 SN Start sector No LBA LSB 1F2 SC Transfer sector count IFI FR XX
172. tup data SD SC to the RDC that includes the Digital PLL circuit to change the data transfer rate 4 14 C141 E120 02EN 4 7 Servo Control 4 7 Servo Control The actuator motor and the spindle motor are submitted to servo control The actuator motor is controlled for moving and positioning the head to the track containing the desired data To turn the disk at a constant velocity the actuator motor is controlled according to the servo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 7 is the block diagram of the servo control circuit The following describes the functions of the blocks 1 2 Head Servo burst capture VCM current Position Sense Spindle motor CSR Current Sense Resister control VCM Voice Coil Motor Figure 4 7 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU includes the DSP unit and the MPU starts the spindle motor moves the heads to the reference cylinders seeks the specified cylinder and executes calibration according to the internal operations of the MPU Main internal operation of the MPU are shown below C141 E120 02EN 4 15 Theory of Device Operation 4 16 The major internal operations are listed below a Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied Move head to reference cylinder Drives the VCM to position the head at the any c
173. uch as damage caused by handling inappropriate operating environments defects in the power supply host system or interface cable 2 Mean time to repair MTTR 3 Service life The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occurs first Refer to item 3 in Subsection 3 2 for the measurement point of the DE surface temperature Also the operating conditions except the environment temperature are based on the MTBF conditions 4 Data assurance in the event of power failure Except for the data block being written to the data on the disk media is assured in the event of any power supply abnormalities This does not include power supply abnormalities during disk media initialization formatting or processing of defects alternative block assignment C141 E120 02EN 1 9 Device Overview 1 8 Error Rate Known defects for which alternative blocks can be assigned are not included in the error rate count below It is assumed that the data blocks to be accessed are evenly distributed on the disk media 1 Unrecoverable read error Read errors that cannot be recovered by maximum
174. using an Ultra DMA data in burst 5 118 5 6 3 5 Device terminating an Ultra DMA data in burst 5 119 5 6 3 6 Host terminating an Ultra DMA data in burst 5 120 5 6 3 7 Initiating an Ultra DMA data out burst 5 121 5 6 3 8 Sustained Ultra DMA data out burst 5 122 5 6 3 9 Device pausing an Ultra DMA data out burst 5 123 5 6 3 10 Host terminating an Ultra DMA data out burst 5 124 5 6 3 11 Device terminating an Ultra DMA data in burst 5 125 5 6 4 Power on reset 5 126 Operations siisii ennont aano aeaa 6 1 6 1 Device Response to the Reset 6 2 6 1 1 Response to power on 6 2 6 1 2 Response to hardware reset 6 3 6 1 3 Response to software reset 6 5 6 1 4 Response to diagnostic command 6 6 C141 E120 02EN Contents Glossary 6 2 Power Save 6 7 6 2 1 Power save mode 6 7 6 2 2 Powercommands 6 8 6 3 Defect Management 6 9 6 3 1 Sparearea 6 9 6 3 2 Alternating defective sectors 6 9 6 4 Read Ahead Cache 6 11 6 4 1 Data buffer configuration 6 12 6 4 2 Caching operation 6 12 6 4 3 Usage ofread segment 6 14 6 4 3 1 Mis hit no hit 6 14 6 4 3 2 Sequential read 6 15 6 4 3 3 Fullhit hitall 6 18 6 4 3 4 Partially hit 6 19 6 5 Write Cache 6 20 Acronyms and AB 1 C141 E120 02EN xiii Contents Figures XIV Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3
175. usly executed read command is an non sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command the disk drive assumes the received command is a sequential command and performs the read ahead operation after reading the requested data 1 Atreceiving the sequential read command the disk drive sets the DAP and HAP to the start address of the segment and reads the requested data from the load of the segment HAP Mis hit data Empty area DAP C141 E120 02EN 6 15 Operations 2 The disk drive transfers the requested data that is already read to the host system with reading the requested data HAP TH Mis hit data Empty area DAP 3 After completion of the reading and transferring the requested data to the host system the disk drive performs the read ahead operation continuously HAP Completion of transferring requested data TZ Saket J d DAP 4 The disk drive performs the read ahead operation for all area of segment with overwriting the requested data Finally the cache data in the buffer is as follows HAP C S Last LBA Start LBA b Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector add
176. ut off frequency and boost up gain according to the transfer frequency of each zone Figure 4 6 shows the frequency characteristic sample of the programmable filter Gain D dB 20 15 Fb control Boost volume Fc control 1 2 4 5 10 20 30 40 50 100 Log Frequency MHz Figure 4 6 Frequency characteristic of programmable filter C141 E120 02EN 4 13 Theory of Device Operation 3 Flash digitizer circuit This circuit is 10 tap sampled analog transversal filter circuit that cosine equalizes the head read signal to the Modified Extended Partial Response MEEPR waveform 4 Viterbi detection circuit The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit The Viterbi detection circuit demodulates data according to the survivor path sequence 5 MEEPRM This circuit converts the 17 bit read data into the 16 bit NRZ data 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant The drive divides data area into 15 zones to set the data transfer rate The MPU transfers the data transfer rate se
177. vice Configuration 2 2 System Configuration 2 2 1 ATA interface Figures 2 3 and 2 4 show the ATA interface system configuration The drive has a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16 6 MB s Multiword DMA mode 2 transfer at 16 6 MB s and also U DMA mode 5 transfer at 100 MB s 2 2 2 1 drive connection MHN2300AT MHN2200AT MHN2150AT MHN2100AT Host AT bus ATA interface Host interface Figure 2 3 1 drive system configuration 2 2 3 2 drives connection MHN2300AT MHN2200AT MHN2150AT MHN2100AT MHN2300AT MHN2200AT MHN2150AT MHN2100AT AT bus Host interface ATA interface Note When the drive that is not conformed to ATA is connected to the disk drive above configuration the operation is not guaranteed Figure 2 4 2 drives configuration 2 4 C141 E120 02EN C141 E120 02EN 2 2 System Configuration IMPORTANT HA host adaptor consists of address decoder driver and receiver 15 an abbreviation of attachment The disk drive is conformed to the ATA 5 interface At high speed data transfer PIO mode 4 or DMA mode 2 U DMA mode 5 occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 5 standard and the cable
178. ylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 Seek to specified cylinder Drives the VCM to position the head to the specified cylinder Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration value C141 E120 02EN 4 7 Servo Control 2 Servo burst capture circuit The servo burst capture circuit reproduces signals position signals that indicate the head position from the servo data on the data surface SERVO A SERVO B SERVO C and SERVO D burst signals shown in Figure 4 9 followed the servo mark cylinder gray and index information are output from the servo area on the data surface via the data head The servo signals do A D convert by Fourier demodulator in the servo burst capture circuit At that time the AGC circuit is in hold mode The A D converted data is recognized by the MPU as position information with A B and C D processed 3 D A converter DAC The D A converter DAC converts the VCM drive current value digital value calculated by the DSP unit into analog values and transfers them to the power amplifier 4 Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM 5 Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor This circuit detects number of revolution of the moto

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