Fujitsu MB3773 User's Manual
Contents
1. MB3773 1 These dimensions include resin protrusion 2 These dimensions do not include resin protrusion Note 3 Pins width and pins thickness include plating thickness Note 4 Pins width do not include tie bar cutting remainder lt 16 35 520 250 0 17 S04 007 0 ry m INDEX 25 30 0 30 7 80 0 40 209 012 307 016 Details of part 40 25 OI Mounting height S MAL gn 0 25 010 1 27 050 0 8 te 0791 919121005 AE 0 50 0 20 0 10 005 020 008 004 tee 0 60 0 15 Stand off 024 006 L O 0 10 004 2002 FUJITSU LIMITED F08002S c 6 7 Dimensions in mm inches Note The values in parentheses are reference values Continued MB3773 A n Continued 8 pin plastic SIP SIP 8P M03 3 26 0 25 19 65 215 128 010 74 6 20 0 25 9 244 010 8 20 0 30 INDEX 2 323 012 0 99920 T EMI E 4 00 0 30 039 157 012 Sey UJ 2 54 100 1 52 10 0 50 0 08 2 1 0 25z0 05 TYP 060 20 020 003 010 002 INDEX 1 1994 FUJITSU LIMITED 5080105 30 2 Dimensions in mm inches Note2. FUJITSU SEMICONDUCTOR DS04 27401 7E ASSP Power Supply Monitor with Watch Dog Timer MB3773 DESCRIPTION MB3773 generates the reset signal to protect an arbitrary system when the power supply voltage momentarily is intercepted or decreased It is for the power supply voltage watch and Power on reset is generated at the normal return of the power supply MB3773 sends the microprocessor the reset signal when decreasing more than the voltage which the power supply of the system specified and the computer data is protected from an accidental deletion In addition the watchdog timer for the operation diagnosis of the system is built into and various microprocessor systems can provide the fail safe function If MB3773 does not receive the clock pulse from the processor for an specified period MB3773 generates the reset signal FEATURES Precision voltage detection Vs 4 2 V 2 5 Detection threshold voltage has hysteresis function Low voltage output for reset signal Vcc 0 8 V Typ Precision reference voltage output Vr 1 245 V 1 5 With built in watchdog timer of edge trigger input External parts are few 1 piece in capacity The reset signal outputs the positive and negative both theories reason PACKAGES DIP 8P M01 SIP 8P M03 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields However it
3. Logic circuit b Using PNP transistor Vcc 5 V Logic circuit Continued 19 MB3773 Continued c Using NPN transistor Vcc 5 V Logic circuit d Using PNP transistor Logic circuit 20 MB3773 EXAMPLE 9 Reducing Reset Hold Time Voc 25 V O MB3773 Ter reduction method b Standard usage Notes e RESET is the only output that can be used e Standard Ten Two and value can be found using the following formulas Formulas Tea ms 100 x CT uF Two ms 100 x CT uF Twr ms 16 x CT uF e The above formulas become standard values in determining Ter Two and Twa Reset hold time is compared below between the reduction circuit and the standard circuit Ter reduction circuit Standard circuit 21 MB3773 EXAMPLE 10 Circuit for Monitoring Multiple Microprocessor Di CK Qi CK Q EE MB3773 connects from FF1 and FF2 outputs Q and Qe to the NOR input Depending on timing these connections may not be necessary e Example R R22 2 2 KQ C12 0 1 uF NOR Output 22 Figure 1 Figure 2 MB3773 I a I Description of Application Circuits Using one MB3773 this application circuit monitors multiple microprocessor in one system Signals from each microprocessor sent to FF1 2 FF3 clock inputs Figure 2 shows these timings Each flip flop operates using signals sent from microprocessor as
4. 1 0 V High level output voltage Output saturation voltage Vs open 5 uA Vs 0 V Irneset 5 uA Vs 0 V Ineser 3 mA Vs 0 V Ineser 10 mA Vs open 3 mA Vs open 10 mA Output sink current Vs 0 V Vneser 1 0 V Vs open 1 0 V Cr charge current Power on reset operating 1 0 V Min supply voltage for RESET Vneser 0 4 V IRESET 0 2 mA Min supply voltage for RESET Vreset Vcc 0 1 V R pin 2 GND 1 MQ 2 Characteristics Parameter Vcc input pulse width Condition 5V Voc 4v __ MB3773 Vcc 5 V 25 C CK input pulse width ck 91 CK input frequency Watch dog timer watching time Cr 0 1 uF Watch dog timer reset time C1 2 0 1 uF Rising reset hold time C1 2 0 1 uF a d Output propagation delay time from Vcc RESET R 2 2 C 100 pF RESET Ri 2 2 C 100 pF Output rising time R 2 2 C 100 pF Output falling time Ri 2 2 C 100 pF Output rising falling time are measured at 10 to 90 of voltage MB3773 TYPICAL CHARACTERISTIC CURVES Supply current vs Supply voltage 0 75 Ta 425 C 85 NA 0 65 0 55 CT 0 1 pF 0 45 0
5. 35 Supply current mA 0 20 40 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 Supply voltage Vcc V Output voltage vs Supply voltage RESET terminal Pull up 2 2 6 0 Output voltage Vreset V 0 10 20 30 40 50 60 70 Supply voltage Vcc V Output saturation voltage vs Output sink current RESET terminal T T Ta 40 C 400 300 200 100 Output saturation voltage Vor mV 0 20 40 60 80 10 0 12 0 14 0 16 0 18 0 Output sink current lor mA Detection voltage Va V Output voltage Vneser Output saturation voltage mV Output voltage vs Supply voltage RESET terminal 6 0 Pull up 2 2 5 0 Ta 40 C 25 C 85 C 4 0 3 0 2 0 1 0 0 1 0 20 30 40 50 60 70 Supply voltage Vcc Detection voltage vs Temperature RESET RESET terminal 4 50 4 44 4 30 Le 4 20 4 10 4 00 40 20 0 20 40 60 80 100 Temperature C Output saturation voltage vs Output sink current RESET terminal Cr 0 1uF 400 300 200 100 0 20 40 6 0 8 0 10 0 12 0 14 0 16 0 18 0 Output sink current lots mA 1
6. is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit cO FUJITSU MB3773 mU L PIN ASSIGNMENT FRONT VIEW TOP VIEW DIP 8P M01 FPT 8P M01 SIP 8P M03 MB3773 BLOCK DIAGRAM MB3773 SSS FUNCTIONAL DESCRIPTIONS Comp S is comparator including hysteresis it compare the reference voltage and the voltage of Vs so that when the voltage of Vs terminal falls below approximately 1 23 V reset signal outputs Instantaneous breaks or drops in the power be detected as abnormal conditions by the MB3773 within a 2 us interval However because momentary breaks or drops of this duration do not cause problems in actual systems in some cases a delayed trigger function can be created by connecting capacitors to the Vs terminal Comp O is comparator for turning on off the output and compare the voltage of the Cr terminal and the threshold voltage Because the RESET RESET outputs have built in pull up circuit there is no need to connect to external pull up resistor when connected to a high impedance load such as CMOS logic IC It corresponds to 500 at Vcc 5 V when the voltage of the CK terminal changes from the high level into the Low level pulse generator is sent to the watch dog timer by generating the pulse momentarily at the time of drop from the thresh
7. this time the output is being reset 3 When begins charging RESET goes High and RESET goes Low After reset of the output is released Reset hold time Ter ms 1000 x Cr uF After releasing reset the discharge of Cr starts and watch dog timer operation starts Ten is not influenced by the CK input 4 changes from the discharge into the charge if the clock Negative edge is input to the CK terminal while discharging C 5 changes from the charge into the discharge when the voltage of Cr reaches a constant threshold 1 4 V 4 and 5 are repeated while a normal clock is input by the logic system When the clock is cut off gets and the voltage of Cr falls on threshold 0 4 V of reset on RESET goes Low and RESET goes High Discharge time of Cr until reset is output Two is watch dog timer monitoring time Two ms 100 x Cr uF Because the charging time of Cr is added at accurate time from stop of the clock and getting to the output of reset of the clock Two becomes maximum Two Twr by minimum Two O 3 Reset time in operating watch dog timer Twa is charging time where the voltage of Cr goes up to off threshold 1 4 V for reset ms 20 x Cr uF Reset of the output is released after Cr reaches an off threshold for reset and Cr starts the discharge after that if the clock is normally input operation repeats 4 and 5 when the clock is cut off
8. 0 Continued MB3773 High level output voltage vs High level output current High level output voltage vs High level output current RESET terminal Sa RESET terminal c 50 gt 5 Cr 0 1 uF Cr 0 1 uF N 5 5 2 25 F Ta 25 C 5 A Ta 85 C S 45 Ta 40 C gt ae 40 i 85 C a Q 2 8 gt 8 5 E UG 5 10 15 5 10 15 High level output current lou uA High level output current lons Reference voltage Reference voltage vs Supply voltage vs Reference current 1 246 1 255 Ta 425 C Cr 0 1 uF S 1 244 ae wi gt 1 242 et S u 1 250 ie Ta 40 C Cr 0 1 uF Varta 1238 124 e 245 Ta 485 C gt 1236 Ta 40 1 234 5 1240 2 c 0 80 50 70 9 0 11 0 13 0 15 0 17 0 19 0 21 0 O 0 80 120 160 200 240 Supply voltage Vcc V Reference current uA Reference voltage Rising reset hold time vs Temperature vs Temperature 1 27 160 p 5 S 1 26 m 140 Cr 0 1 pF S 124 100 5 Q 2 80 8 1 23 E P 60 122 g 2 D 40 Ez Y 1 21 T 2 Ma 40 20 0 20 40 60 80 100 40 20 0
9. 20 40 60 80 100 Temperature Ta C Temperature Ta C Continued 11 MB3773 Continued time vs Watchdog timer watching time emperature vs At watch dog timer Temperature 16 r 3 Vec 5V Vcc 5V 0 1 uF 14 Cr 0 1 uF 5 12 E s g 7 10 go o GE lt 8 D a 1 C 44 ol 0 2 40 20 0 20 40 60 80 100 40 20 0 20 40 60 80 100 Temperature C Temperature Ta C Cr terminal capacitance VS Cr terminal capacitance Cr terminal capacitance Watchdog timer watching time vs Reset time vs Rising reset hold time at watch dog timer 105 106 102 105 105 m 104 104 10 z 103 25 C p 10 g 385902 D 102 p 10 102 5 g di E 2 10 co 85 10 1 5 10 9 10 w c D 107 ina 5 107 102 102 10 3 22 10 3 ds 10 3 00 10 3 10 2 10 1 10 10 102 103 107 107 109 101 10 10 3 10 210 10 101 102 Cr terminal capacitance uF Cr terminal capacitance uF terminal capacitance uF 12 MB3773 APPLICATION CIRCUIT EXAMPLE 1 Monitoring 5V Supply Voltage and Watchdog Timer MB3773 Logic circuit Not
10. For semiconductors use antistatic or conductive containers When storing or carrying a printed circuit board after chip mounting put it in a conductive bag or container The work table tools and measuring instruments must be grounded The worker must put on a grounding device containing 250 to 1 MQ resistors in series Do not apply a negative voltage Applying a negative voltage of 0 3 V or less to an LSI may generate a parasitic transistor resulting in malfunction ORDERING INFORMATION Part number Package Remarks 8 pin plastic DIP DIP 8P M01 8 pin plastic SIP VOS SIP 8P M03 8 pin plastic SOP MBO FPT 8P MO1 25 26 MB3773 PACKAGE DIMENSIONS 8 pin plastic DIP DIP 8P M01 9 40 0 370708 1 PIN INDEX 6 20 0 25 244 010 PY SS 4 36 172 MAX 0 51 020 MIN e 0 25 0 05 3 00 118 MIN J 0 46 0 08 1 018 003 010 002 L J 0 99 5 1525 7 62 300 TOPMAN TYP 039 12 060 2 0 89 55 _ 2 54 100 s 035 2012 1994 FUJITSU LIMITED D08006S 2C 3 Dimensions in mm inches Note The values in parentheses are reference values Continued 8 pin plastic FPT 8P M01 Note 1 Note 2
11. The values in parentheses are reference values MB3773 rau FUJITSU LIMITED Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device Fujitsu does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporating the device based on such information you must assume any responsibility arising out of such use of the information Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of Fujitsu or any third party or does Fujitsu warrant non infringement of any third party s intellectual property right or other right by using such information Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein The product
12. age is approximately 9 2 V 9 4 V and has a hysteresis width of approximately 0 2 V Vcce detection voltage and hysteresis width be found using the following formulas Detection voltage Rs Rs x VREF Rs Approximately 9 4 V in the above illustration Rs Rs V uS C od Approximately 9 2 V in the above illustration Hysteresis width Vuvs 15 MB3773 EXAMPLE 5 Monitoring Two Supply Voltages with hysteresis and reset output Voce 12 V Voc 5 V EN GEN TT 20 kQ RE 30 Diode SI Example Comp 1 Comp 2 MB4204 MB47393 Notes e When either 5 V or 12 V supply voltage decreases below its detection voltage Vs the MB3773 RESET terminal is set to High and the MB3773 RESET terminal is set to Low e Use Vcci 5 V to power the comparators Comp 1 and Comp 2 in the external circuit shown above e The detection voltage of the Vcc2 12 V supply voltage is approximately 9 2 V 9 4 V and has a hysteresis width of approximately 0 2 V For the formulas for finding hysteresis width and detection voltage see section 4 16 MB3773 EXAMPLE 6 Monitoring Low voltage and Overvoltage Monitoring with hysteresis Example Comp 1 Comp 2 4204 MB47393 RESET V Vi Var ix Notes e Comp 1 and Comp 2 are used to monitor for overvoltage while the MB3773 is used to monitor for low voltage Detection vol
13. es e Supply voltage is monitored using Vs e Detection voltage are Vs and Vs EXAMPLE 2 5V Supply Voltage Monitoring external fine tuning type MB3773 Notes e Vs detection voltage can be adjusted externally Based on selecting R and Re values that are sufficiently lower than the resistance of the IC s internal voltage divider the detection voltage can be set according to the resistance ratio of R and Re See the table below R kQ R2 Detection voltage Vs V Detection voltage V 9 4 4 4 5 10 3 9 1 3 9 4 1 4 2 13 MB3773 EXAMPLE 3 With Forced Reset with reset hold MB3773 Logic circuit Note Grounding pin 7 at the time of SW ON sets RESET pin 8 to Low and RESET pin 2 to High MB3773 Logic circuit Note Feeding the signal to terminal RESIN and turning on Tr sets the RESET terminal to Low and the RESET terminal to High 14 MB3773 EXAMPLE 4 Monitoring Two Supply Voltages with hysteresis reset output and NMI Logic circuit Example Comp 1 Comp 2 MB4204 MB47393 Notes e The 5 V supply voltage is monitored by the MB3773 e The 12 V supply voltage is monitored by the external circuit Its output is connected to the NMI terminal and when voltage drops Comp 2 interrupts the logic circuit e Use Vcc 5 V to power the comparators Comp 1 and Comp 2 in the external circuit shown above e The detection voltage of the Vcc2 12 V supply volt
14. ing time trc trac Terminal capacitance Operating ambient temperature Ta WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand MB3773 ELECTORICAL CHARACTERISTICS 1 DC Characteristics Parameter Supply current Condition Watch dog timer operating Vcc 5 V Ta 25 Detection voltage Vcc NM Ta 40 to 85 C Vcc Pa 40 to 85 C Hysteresis width Reference voltage Ta 40 to 85 C Reference voltage change rate Vec 3 5V to 16 V Reference voltage output loading change rate CK threshold voltage lour 200 pA to 5 pA Ta 40 to 85 C Vek 5 0 V Vck 0 0 V Cr discharge current Watch dog timer operating
15. its clock pulse When even one signal stops the relevant receiving flip flop stops operating As a result cyclical pulses are not generated at output Qs Since the clock pulse stops arriving at the CK terminal of the MB3773 the MB3773 generates a reset signal Note that output Qs frequency f will be in the following range where the clock frequencies of CK1 CK2 and CK3 are f f2 and fs respectively where fo is the lowest frequency among fi fe and fs MB3773 EXAMPLE 11 Circuit for Limiting Upper Clock Input Frequency Notes e This is an example application to limit upper frequency fH of clock pulses sent from the microprocessor If the CK cycle sent from the microprocessor exceeds fH the circuit generates a reset signal The lower frequency has already been set using Cr e When a clock pulse such as shown below is sent to terminal a short T2 prevents voltage from reaching the CK input threshold level 1 25 V and will cause a reset signal to be output The value can be found using the following formula T1 0 3 2 2 where Vcc 5 V Ta gt 3 0 us T2 gt 20 us Ta CK waveform _ Ts Ce voltage 4 l Example Setting C and R allow the upper value to be set See the table below 24 MB3773 NOTES ON USE Take account of common impedance when designing the earth line on a printed wiring board Take measures against static electricity
16. old level When power supply voltages fall more than detecting voltages the watch dog timer becomes a interdiction The Reference amplifier is a op amp to output the reference voltage If the comparator is put up outside two or more power supply voltage monitor and overvoltage monitor can be done If it uses a comparator of the open collector output and the output of the comparator is connected with the Vs terminal of MB3773 without the pull up resistor it is possible to voltage monitor with reset hold time MB3773 2 RRR saa SR pP LL LL LL e6o0 Add PTN ak See eee eme aa ooo 8S8 Wise z It lk E s nana ee cea ace DEREN EEE B per PED III III III III cot ass FFF z FE t PO o s 4 EN MD pepe ARTES ORENSE Y A O d O I WN 1l qd 0 4 E rem o 6 a e IT tc 11 12 10 8 9 6 7 MB3773 OPERATION SEQUENCE 1 When Vcc rises to about 0 8 V RESET goes Low and RESET goes High The pull up current of approximately 1 Vcc 0 8 V is output from RESET 2 When Vcc rises to Vsu 4 3V the charge with Cr starts At
17. operation repeats 6 and 7 C When Vcc falls on Va 4 2 reset is output Cr is rapidly discharged of at the same time When Vcc goes up to Vsr the charge with Cr is started When Vcc is momentarily low After falling Vs or less Vcc the time to going up is the standard value of the Vcc input pulse width or more After the charge of Cr is discharged the charge is started if it is more 10 Reset of the output is released after Ter after Vcc becomes Vsr or more and the watch dog timer starts After that when Vcc becomes Vs or less 8 to 10 is repeated 11 While power supply is off when Vcc becomes Vs or less reset is output 12 The reset output is maintained until Vcc becomes 0 8 V when Vcc falls 0 V MB3773 I iBOOOU U ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage i 18 Vcc 0 3 lt 18 Input voltage 18 RESET RESET Supply voltage Vcc 0 3 lt 18 Power dissipation Ta lt 85 C 200 Storage temperature 125 WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage RESET RESET sink current VREF output current Watch clock setting time CK Rising fall
18. or authorization by Japanese government will be required for export of those products from Japan F0308 FUJITSU LIMITED Printed in Japan
19. s described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that Fujitsu will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the pri
20. tages Viu Vir at the time of low voltage are approximately 4 2 V 4 3 V Detection voltages V2 Vzx at the time of overvoltage are approximately 6 0 V 6 1 V For the formulas for finding hysteresis width and detection voltage see EXAMPLE 4 e Use Vcc 5 V to power the comparators Comp 1 and Comp 2 in the external circuit shown above 17 MB3773 EXAMPLE 7 Monitoring Supply Voltage Using Delayed Trigger Logic circuit Note Adding voltage such as shown in the figure to Vcc increases the minimum input pulse width by 50 us C1 1000 pF 18 MB3773 EXAMPLE 8 Stopping Watch dog Timer Monitoring only supply voltage These are example application circuits in which the MB3773 monitors supply voltage alone without resetting the microprocessor even if the latter used in standby mode stops sending the clock pulse to the MB3773 watch dog timer is inhibited by clamping the Cr terminal voltage to Vrer The supply voltage is constantly monitored even while the watch dog timer is inhibited For this reason a reset signal is output at the occurrence of either instantaneous disruption or a sudden drop to low voltage Note that in application examples a and b the hold signal is inactive when the watch dog timer is inhibited at the time of resetting If the hold signal is active when tie microprocessor is reset the solution is to add a gate as in examples c and a Using NPN transistor Vcc 5 V O
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