Fujitsu MB15F74UV User's Manual
Contents
1. 1 5mAmode 6 0 mA mode Charge pump output current loo mA Charge pump output current loo mA Ibo Vpo Charge pump output voltage Voo V Ibo VDo 0 00 2 00 4 00 6 00 8 00 0 0 0 5 1 0 1 5 2 0 2 5 Charge pump output voltage Voo V 17 18 MB15F74UV ee 4 fin input impedance fin input impedance START 100 000 000 MHz 4 30 266 Q 102 92 Q 773 21 fF 2 000 000 000 MHz 1 494 28 Q 874 84 Q 200 MHz IN 58 094 2 216 47 Q 1 GHz STOP 2 000 000 000 MHz finnr input impedance START 2 000 000 000 MHz _4 20 93 O 39 352 O 1 0111 pF 4 000 000 000 MHz 1 37 563 Q 109 96 O 2 GHz IN 26 125 Q 71 227 Q 3 GHz 22 848 Q 54 025 O 3 5 GHz W STOP 4 000 000 000 MHz MB15F74UV 5 OSCn input impedance OSCw input impedance 4 278 69 Q 1 0537 kQ 3 7761 pF 40 000 000 MHz 1 2 25kQ 2 2373 kQ 10 MHz 2 881 622 1 8299 KQ 20 MHz 3 448 75 Q 1 353 kQ 30 MHz START 3 000 000 MHz STOP 40 000 000 MHz 19 MB15F74UV H REFERENCE INFORMATION for Lock up Time Phase Noise and Reference Leakage Test Circuit Spectrum m Analyzer fvco 2113 6 MHz Vcc 3 0 V Kv 50 MHz V Ta 25 C fr 50 kHz CP 6 mA mode fosc 19 2 MHz LPF 7 5 KQ AAN To VCO li 1 6 kQ li 0 01 uF 3300 pF ai2. counter RF PLL DI 7bitlatch 11 bit latch 23 bit shift register trigger circuit 1 GND 11 12 Vccnr GNDnF 6 Doir 8 LD fout 10 DoRF MB15F74UV SSS EEE SSS H ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage LD fout Doir Dorr Output voltage Storage temperature WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings H RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage i i Vconr Vccir Input voltage Operating temperature Note e Vccar and Vccie must supply equal voltage Even if either RF PLL or IF PLL is not used power must be supplied to Vccar and Vccir to keep them equal It is recommended that the non use PLL is controlled by power saving function Although this device contains an anti static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection observe the following precautions when handling the device When storing and transporting the device put it in a conductive case Before handling the device confirm the jigs and tools to be used have been uncharged grounded as well as yourself Use a conductive sheet on working bench Before fitting th
3. FUJITSU SEMICONDUCTOR DS04213811E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F74UV H DESCRIPTION The Fujitsu MB15F74UV is a serial input Phase Locked Loop PLL freguency synthesizer with a 4000 MHz and a 2000 MHz prescalers A 64 65 or a 128 129 for the 4000 MHz prescaler and a 32 33 or a 64 65 for the 2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation The BICMOS process is used as a result a supply current is typically 9 0 mA at 3 0 V The supply voltage range is from 2 7 V to 3 6 V A refined charge pump supplies well balanced output current with 1 5 mA and 6 mA selectable by serial date The serial data formatis the same as MB15F74UL Fast locking is achieved for adopting the new circuit MB15F74UV is in the small package BCC18 which decreases a mount area of MB15F74UV about 50 com paring with the former BCC20 for dual PLL H FEATURES High freguency operation RF synthesizer 4000 MHz Max IF synthesizer 2000 MHz Max Low power supply voltage Vcc 2 7 V to 3 6 V Ultra low power supply current Icc 9 0 mA Typ Vcc 3 0 V Ta 25 C SWir SWar 0 in IF RF locking state Continued H PACKAGE 18 pin plastic BCC LCC 18P M05 CO FUJITSU MB15F74UV EE EE SS SSS Continued Direct power saving function Power supply current in power saving mode Typ 0 1 uA Vcc 3 0 V Ta 25 C at 1 system Dual modulus pr
4. 0 1 pF e PLL Reference Leakage ATTEN 10 dB VAVG 16 RL 0 dBm 10 dB AMKR 80 83 dB AMKR 50 0 kHz 80 83 dB CENTER 2 1136000 GHz PLL Phase Noise SPAN 200 0 kHz RBW 1 0 kHz VBW 1 0 kHz SWP 500 ms ATTEN 10 dB VAVG 16 RL 0 dBm 10 dB AMKR 65 34 dB Hz AMKR 1 00 kHz 65 34 dB Hz CENTER 2 11360000 GHz RBW 30 Hz VBW 30 Hz SPAN 10 00 kHz SWP 1 92 s 20 Continued MB15F74UV aa Continued PLL Lock Up time 2113 6 MHz 2173 6 MHz within 1 kHz Lch gt H ch 1 47 ms A Mkr x 439 99764 us y 50 0009 MHz 2 173604000 GHz 2 173600000 GHz 2 173596000 GHz 500 us 2 000 ms 4 500 ms 500 us div PLL Lock Up time 2173 6 MHz gt 2113 6 MHz within 1 kHz H ch L ch 1 56 ms A Mkr x 400 00146 us y 50 0013 MHz 2 113604000 GHz i i 2 113600000 GHz 2 113596000 GHz 500 us 2 000 ms 4 500 ms 500 us div 21 22 MB15F74UV H APPLICATION EXAMPLE 1000 pF TCXO Controller divide ratio setting Data A
5. Note Data input with MSB first 2 Data setting Binary 14 bit Programmable Reference Counter Data Setting Divide ratio R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 Note Divide ratio less than 3 is prohibited Binary 11 bit Programmable Counter Data Setting Divide ratio Note Divide ratio less than 3 is prohibited e Binary 7 bit Swallow Counter Data Setting Divide ratio MB15F74UV E e Prescaler Data Setting o a GN E aa Prescaler divide ratio IF PLL 32 33 64 65 Prescaler divide ratio RF PLL 64 65 128 129 Charge Pump Current Setting 6 0 mA 1 1 5 mA 0 LD fout output Selectable Bit Setting LD fout pin state LD output e Phase Comparator Phase Switching Data Setting FCir nr 1 FCrr nr 0 Dorr Dorr Dorr Dorr Phase comparator input Z High impedance Depending upon the VCO and LPF polarity FC bit should be set High 1 VCO polarity FC 1 2 VCO polarity FC 0 2 y VCO Output Frequency LPF Output voltage Max Note Give attention to the polarity for using active type LPF 10 MB15F74UV 3 Power Saving Mode Intermittent Mode Control Circuit Normal mode Power saving mode The intermittent mode control circuit reduces the PLL power cons
6. P Mount height HEER F 2 01 079 mH F jy INDEXAREA g403040 a Th EL 0 90 035 094 004 H A si 1 90 075 0 45 018 ON n r BE h TYP ate Eo i i H r l JH m T Fi a 0 075 0 025 sj 1 35 053 1 7775 0035 001 REF Stand off 2 28 090 REF Details of A part Details of B part Details of C part 0 14 006 0 25 0 06 020 0 06 O 05000 am Ve 0102 002 C0 10 004 0142 002 0142 002 iy EE 0 25 0 06 0 28 0 06 0 2840 06 010 002 0112 002 011 002 Dimensions in mm inches Note The values in parentheses are reference values MB15F74UV EE EE EE FUJITSU LIMITED All Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device Fujitsu does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporating the device based on such information you must assume any responsibility arising out of such use of the information Fujitsu assumes no liability for any damages whatsoever arising o
7. edge of Clock one bit of the serial data is transferred into the shift register On a rising edge of load enable signal the data stored in the shift register is transferred to one of latches depending upon the control bit data setting The programmable The programmable The programmable The programmable reference counter reference counter counter and the swallow counter and the swallow for the IF PLL for the RF PLL counter for the IF PLL counter for the RF PLL 1 Shift Register Configuration Programmable Reference Counter LSB Data Flow MSB B RN gm eje ee ease CS Charge pump current select bit RitoR14 Divide ratio setting bits for the programmable reference counter 3 to 16 383 T1 T2 LD fout output setting bit CN1 CN2 Control bit X Dummy bits Set 0 or 1 Note Data input with MSB first MB15F74UV Programmable Counter Lyr LSB Data Flow MSB CN1 CN2 LDS ar FOr atl 22 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N9 N10 N11 SWar FCnr A1 to A7 Divide ratio setting bits for the swallow counter 0 to 127 N1 to N11 Divide ratio setting bits for the programmable counter 3 to 2 047 LDS LD fout signal select bit SWir SWrr _ Divide ratio setting bit for the prescaler IF SWir RF SWnr FCir FCnr Phase control bit for the phase detector IF FCir RF FCrr CN1 CN2 Control bit
8. voltage Schmitt trigger input Schmitt trigger input H level input current L level input current H Ievel output voltage L level output voltage Vec 3 0 V lon 1 mA Vec 3 0 V lou 1 mA H level output voltage L level output voltage Vcc 3 0 V Ibon 0 5 mA Vcc 3 0 V Idol 0 5 mA High impedance cutoff current Vec 3 0 V Vorr 0 5 V to Vec 0 5 V H Ievel output current L level output current Vcc 3 0 V Vcc 3 0 V H level output current Vec 3 0 V CS bit 1 VpoH Vec 2 Ta 25 C CS bit 0 L level output current Vec 3 0 V CS bit 1 Vool Vcc 2 Ta 25 C CS bit 0 Continued MB15F74UV Continued Charge pump vs Vpo lpovD 10 5 V lt Voo lt Vec 0 5 V current rate 40 C lt Ta lt 85 C 1 2 3 4 B 6 7 8 Vcc 2 7 V to 3 6 V Ta 40 C to 85 C Parameter Condition poL IpoH IDomt po Vcc lou 5 V Vcc 2 7 vs Ta IDOTA Voo Vec 2 Conditions fosc 12 8 MHz Ta 25 C SW 0 in locking state Veer Vccnr 3 0 V fosc 12 8 MHz Ta 25 C in power saving mode PSr PSnr GND Vin Vcc Vu GND at CLK Data LE AC coupling 1000 pF capacitor is connected under the co
9. 2 7 V 3 0 V 3 6 V Vcc Vcc Vcc r r r r i i 1 i i 1 i i H i i H i i i i i i i i N EE N EE EN A pise i amp i i i i 1 i i i i i i H i i H i i i i H L 1 f L 1 i 1 i 1 1 i i i i i i i i i i H i i H N EN i Bh i 1 1 od aain faak doia panig ts kaini ad i H i i H h i i i i i i i i i i i i T r T r T T i 1 i i 1 i H i i H i i i i i i i EA EE HR SE ee fee EE imela ze i 1 H i 1 i i i i H i i H i i i H 1 L f 1 1 i 1 1 i i i i i i i i i i 1 i i H i i i FT rr RIESE eal ci 177177 i i i i i H i i i i i i i i i i 1 i i i i i H i i H i i H i i H i i i i i i raven NU Bid foe D i a i i 1 i i 1 i i i i i i H i i H i i i f L M M f 1 i i h 1 i 1 i i i f i i i i i i i i i H Lo i i Ea EE IE y i i i i H i i i i i i i i i i i i H r T i i i H D 1 1 1 1 oD 1 1 1 o 1 1 i 1 Emi je oj i i i i i i H 1 1 1 1 gt L L L o 1 1 1 o i i i i i i So 1 1 1 i i i r mehr F FT im r GI i i H Os i i i i i i 7 i i i o o o o o o m N n s LO 10 uigp osoA HAILISU S 1Ndul 160 140 120 100 80 60 40 20 Input frequency fosc MHz 16 3 RF IF PLL Do output current MB15F74UV
10. A N OUTPUT HI 1000 pF F 1000 pF e INRF finiF XfiniF VCO ORO DE T MB15F74UV LPF Vccir O1UF CO Lock Detect Note Clock Data LE The schmitt trigger circuit is provided insert a pull down or pull up registor to prevent oscillation when open circuit in the input MB15F74UV H USAGE PRECAUTIONS 1 Vccnr and Vecir must be equal voltage Even if either RF PLL or IF PLL is not used power must be supplied to Vccnr and Vccir to keep them equal It is recommended that the non use PLL is controlled by power saving function 2 To protect against damage by electrostatic discharge note the following handling precautions e Store and transport devices in conductive containers Use properly grounded workstations tools and equipment Turn off power before inserting or removing this device into or from a socket Protect leads with conductive sheet when transporting a board mounted device H ORDERING INFORMATION a Rees ee 18 pin plastic BCC 23 MB15F74UV H PACKAGE DIMENSION 15 18 pin plastic BCC LCC 18P MO5 0 05 002 2003 FUJITSU LIMITED C18058S c 1 1 2 31 090 2 70 0 10 0 45 0 05 we 018 106 004 018 002 m aa
11. IF ref counter IF prog counter RF ref counter RF prog counter according to the control bit in a serial data 17 Clock Clock input pin for the 23 bit shift register with the schmitt trigger circuit One bit data is shifted into the shift register on a rising edge of the clock 18 OSC The programmable reference divider input pin TCXO should be connected with an AC coupling capacitor MB15F74UV H BLOCK DIAGRAM Intermittent 3 bit latch 7 bit latch 11 bit latch PSIF 7 mode control IF PLL finiF 2 Prescaler IF PLL XfiniF 3 32 33 64 65 Binary 7 bit Binary 11 bit swallow counter programmable IF PLL counter IF PLL VeciF GNDIF 4 Phase Fast comp lock IF PLL Tuning Charge i Current pump Switch F PLL Sto 14 bit latch grammable ref counter IF PLL OSCiN 18 Prescaler Binary 14 bit pro grammable ref counter RF PLL counter 14bitlatch Y1 bit latch finRF 14 7 XfinRF 13 a 64 65 128 129 Lock Det RF PLL Intermittent mode control PSRF 9 RF PLL Schmitt trigger circuit LE 15 Schmitt trigger Data 16 cireuit Clock 17 Schmitt Latch selector Binary 7 bit Binary 11 bit swallow counter programmable 3 bit latch RF PLL
12. depend on OSCw input frequency as follows twu gt 2 fosc e g twu gt 156 3 ns when fosc 12 8 MHz twu lt 4 fosc e g tm lt 312 5 ns when fosc 12 8 MHz 13 MB15F74UV H TEST CIRCUIT for Measuring Input Sensitivity fin OSCw SG 1000 pF 50 Q Vccir 0 1 uF S G 1000 pF GND 1 VCCRF SAS 1000 pF FV 50 Q 1000 pF P Controller divide ratio setting 502 OSCIN Clock Data LE finRF 1000 pF Xfi L MB15F74UV ee GNDar 0 1 uF H Lo Oscilloscope 14 H TYPICAL CHARACTERISTICS 1 fin input sensitivity MB15F74UV Pfinir dBm Pfinnr dBm RF PLL input sensitivity vs Input freguency 10 Ta 25 C 0 Catalog guaranteed range Vec 2 7 V 10 Vcc 3 0 V 20 k Vcc 3 6 V SPEC 30 40 50 1500 2000 2500 3000 3500 4000 4500 5000 finnF MHz IF PLL input sensitivity vs Input frequency Ta 25 C Catalog guaranteed range a Vcc 2 7 V Vec 3 0 V k Vcc 3 6 V SPEC 50 500 1000 1500 finir MHz 2000 2500 3000 15 MB15F74UV 2 OSCw input sensitivity Input sensitivity vs Input freguency
13. e device into or removing it from the socket turn the power supply off When handling such as transporting the device mounted board protect the leads with a conductive sheet WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand MB15F74UV H ELECTRICAL CHARACTERISTICS Parameter Power supply current Vcc 2 7 V to 3 6 V Ta 40 C to 85 C Condition finr 2000 MHz Vccir 3 0 V finnr 2500 MHz Vccnr 3 0 V Power saving current PSir PSnr L PSir PSnr L finir 8 IF PLL Operating frequency finnr 3 fosc RF PLL Pfinir IF PLL 50 Q system Input sensitivity Pfinnr RF PLL 50 O system Input available voltage Vosc H level input voltage L level input voltage H level input voltage L level input
14. escaler 4000 MHz prescaler 64 65 or128 129 2000 MHz prescaler 32 33 or 64 65 23 bit shift register Serial input binary 14 bit programmable reference divider R 3 to 16 383 Max 10 uA Vcc 3 0 V at 1 system Software selectable charge pump current 1 5 mA 6 0 mA Typ Serial input programmable divider consisting of Binary 7 bit swallow counter 0 to 127 Binary 11 bit programmable counter 3 to 2 047 Built in high speed tuning low noise phase comparator current switching type constant current circuit On chip phase control for phase comparator On chip phase comparator for fast lock and low noise e Built in digital locking detector circuit to detect PLL locking and unlocking Operating temperature Ta 40 C to 85 C Serial data format compatible with MB15F74UL Ultra small package BCC18 2 4 mm x 2 7 mm x 0 45 mm m PIN ASSIGNMENTS GND finiF XfiniF GNDIF Vccir DOIF TOP VIEW Clock OSCIN Data LE finRF XfinRF GNDRF VCCRF DORF PSr PSRF LD fout LCC 18P M05 MB15F74UV i PIN DESCRIPTION Descriptions Ground pin for OSC input buffer and the shift register circuit Prescaler input pin for the IF PLL Connection to an external VCO should be AC coupling Prescaler complimentary input for the IF PLL section This pin should be grounded via a capacitor Ground pin for the IF PLL section Power supply voltage input pin for
15. l data 11 12 MB15F74UV 4 Serial Data Data Input Timing Divide ratio is performed through a serial interface using the Data pin Clock pin and LE pin Setting data is read into the shift register at the rise of the Clock signal and transferred to a latch at the rise of the LE signal The following diagram shows the data input timing 1st data 2nd data gt Control bit Invalid data V V oes dj die da da ASNA ti t2 t3 t4 t5 ts 100 ns te 20 ns e o Note LE should be L when the data is transferred into the shift register MB15F74UV _ _ SS H PHASE COMPARATOR OUTPUT WAVEFORM friF RF fpIF RF FC bit 1 H DOIF RF i a L FC bit 0 H DOIF RF L LD Output Logic Locking state Power saving state IF PLL section RF PLL section LD ia Locking state Power saving state Locking state Power saving state Unlocking state Unlocking state Locking state Power saving state Unlocking state Unlocking state Notes e Phase error detection range 27 to 27 e Pulses on Dorr signals during locking state are output to prevent dead zone LD output becomes low when phase error is twu or more LD output becomes high when phase error is tm or less and continues to be so for three cycles or more e twu and tw
16. liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan FO401 FUJITSU LIMITED Printed in Japan
17. ndition of Min operating frequency The symbol minus means the direction of current flow Vec 3 0 V Ta 25 C Illa lall lla la 2 x 100 Vcc 3 0 V Ta 25 C Illa II 2 LL ll2l 2 x 100 Applied to both Idol and Ipon Vec 3 0 V Ipo 85 C Ivo 40 C 2 Ipo 85 C Ipo 40 C 2 x 100 Applied to both Idol and IpoH When Charge pump current is measured set LDS 0 T1 O and T2 1 IpoL IDoH 0 5 Vcc 2 Vec 0 5 Vcc Charge pump output voltage V MB15F74UV H FUNCTIONAL DESCRIPTION 1 Pulse swallow function fvco P x N A x fosc R fvco Output frequency of external voltage controlled oscillator VCO P Preset divide ratio of dual modulus prescaler 32 or 64 for IF PLL 64or 128 for RF PLL N Preset divide ratio of binary 11 bit programmable counter 3 to 2 047 A Preset divide ratio of binary 7 bit swallow counter 0 lt A lt 127 A lt N fosc Reference oscillation frequency OSCw input frequency R Preset divide ratio of binary 14 bit programmable reference counter 3 to 16 383 2 Serial Data Input The serial data is entered using three pins Data pin Clock pin and LE pin Programmable dividers of IF RF PLL sections programmable reference dividers of IF RF PLL sections are controlled individually The serial data of binary data is entered through Data pin On rising
18. the IF PLL section the shift register and the oscillator input buffer Charge pump output for the IF PLL section Power saving mode control pin for the IF PLL section This pin must be set at L when the power supply is started up Open is prohibited PSr H Normal mode PSir L Power saving mode LD fout Lock detect signal output LD phase comparator monitoring output fout pin The out put signal is selected by LDS bit in a serial data LDS bit H outputs fout signal LDS bit L outputs LD signal Power saving mode control for the RF PLL section This pin must be set at L when the power supply is started up Open is prohibited PSnr H Normal mode PSnr L Power saving mode Charge pump output for the RF PLL section Power supply voltage input pin for the RF PLL section Ground pin for the RF PLL section Prescaler complimentary input pin for the RF PLL section ANE This pin should be grounded via a capacitor 14 fin Prescaler input pin for the RF PLL a Connection to an external VCO should be via AC coupling Load enable signal input pin with the schmitt trigger circuit 15 LE When LE is set H data in the shift register is transferred to the corresponding latch ac cording to the control bit in a serial data Serial data input pin with the schmitt trigger circuit 16 Data Data is transferred to the corresponding latch
19. umption By setting the PS pin low the device enters into the power saving mode reducing the current consumption See the Electrical Characteristics chart for the specific value The phase detector output Do becomes high impedance For the dual PLL the lock detector LD is as shown in the LD Output Logic table Setting the PS pin high releases the power saving mode and the device works normally The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation When the PLL is returned to normal operation the phase comparator output signal is unpredictable This is because of the unknown relationship between the comparison frequency fp and the reference frequency fr which can cause a major change in the comparaor output resulting in a VCO frequency jump and an increase in lockup time To prevent a major VCO frequency jump the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation Notes e When power VCC is first applied the device must be in standby mode PS pin must be set L at Power ON OFF ON Vec tv gt 1 us Clock Data LE PS i trs gt 100 ns 1 PS L power saving mode at Power ON 2 Set serial data at least 1 us after the power supply becomes stable Vcc gt 2 2 V 3 Release power saving mode PS1 PSrr L gt H at least 100 ns later after setting seria
20. ut of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of Fujitsu or any third party or does Fujitsu warrant non infringement of any third party s intellectual property right or other right by using such information Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that Fujitsu will not be
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