Cypress STK14C88-5 User's Manual
Contents
1. Logic Block Diagram me N Quantum Trap EG oap 512X51 aj 4 f POWER As D STORE CONTROL Ag x Az m As o RECALL l STORE Ag Q cae a we RECALL lt gt HSB A a lt 1 CONTROL a 512 X 512 AA 12 o 7 Aug a Ang SOFTWARE __ DETECT A13 Ao AKA DAJ COLUMN I O TP g COLUMN DEC DQ wi Da r E Da H Ik DQ t a Ao Ax Ag Ag A4 Ato NI DQ H v DO gt H mn 1 OE lt q u p Ge Noo p WE Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document Number 001 51038 Rev Revised March 02 2009 Feedback CYPRESS Pin Configurations Figure 1 Pin Diagram 32 Pin DIP STK14C88 5 Figure 2 Pin Diagram 32 Pin LCC Voap m Ang HSB lt lt gt gt T TASTAIN I Ne ai A yz we 432 4 32 31 30 Ay A 13 Ag 5 5 5 Ais Ag As As 6 280 As As As As 7 270 As Ag Ass As 26 C An As OE NC 9 TOP 25 COE NC Top View NC A2 10 24 NC A2 Not To Scale Aso A 11 23 C Ato Ae CE Ao 12 22 CE Ag DQ DO 3 13 21C DO DO C 14 15 16 17 18 19 20 J Da DQ gdgadddg DQ DO aa aaqaqaa Vs DO Pin Definitions Pin Name Alt IO Type Description A2. a Z ene SN CYPRESS STK14C88 5 PERFORM 256 Kbit 82K x 8 AutoStore nvSRAM Features m 35 ns and 45 ns access times m Hands off automatic STORE on power down with external 68 uF capacitor m STORE to QuantumTrap nonvolatile elements is initiated by software hardware or AutoStore on power down m RECALL to SRAM initiated by software or power up m Unlimited READ WRITE and RECALL cycles m 1 000 000 STORE cycles to QuantumTrap m 100 year data retention to QuantumTrap m Single 5V 10 operation m Military temperature m 32 pin 300 mil CDIP and LCC 450 mil packages Functional Description The Cypress STK14C88 5 is a fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory Both the STORE and RECALL operations are also available under software control A hardware STORE is initiated with the HSB pin
3. mode inhibiting all operations until HSB rises CE and OE LOW and WE HIGH for output behavior Cree ej Document Number 001 51038 Rev V O state assumes OE lt V Activation of nonvolatile cycles does not depend on state of OE HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle After the STORE if any completes the part goes into standby The six consecutive addresses must be in the order listed WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle While there are 15 addresses on the STK14C88 5 only the lower 14 are used to control software modes Page 6 of 17 Feedback CYPRESS STK14C88 5 Maximum Ratings Voltage on DQo 7 or HSB eeeeeeeeeeee 0 5V to Vec 0 5V Power Dissipation oooooonnnnnnnnnncnnnnnn nn 1 0W Exceeding maximum ratings may shorten the useful life of the device These user guidelines are not tested DC output Current 1 output at a time 1s duration 15 mA Storage Temperature cece 65 C to 150 C Operating Range Temperature under Bias s e 55 C to 125 C Voltage on Input Relative to GND 0 5V to 7 0V Range Ambient Temperature Vec Voltage on Input Relative to Vss 0 6V to Voc 0 5V Military 55 C to 125 C FOV IGS DC Electrical Cha
4. After the treca cycle time the SRAM is once again ready for READ and WRITE operations The RECALL operation does not alter the data in the nonvolatile elements The nonvolatile data can be recalled an unlimited number of times ar ON 0 A VO V Page 4 of 17 Feedback CYPRESS Data Protection The STK14C88 5 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations The low voltage condition is detected when Vcc is less than Vsgwitcy If the STK14C88 5 is in a WRITE mode both CE and WE are low at power up after a RECALL or after a STORE the WRITE is inhibited until a negative transition on CE or WE is detected This protects against inadvertent writes during power up or brown out condi tions Noise Considerations The STK14C88 5 is a high speed memory It must have a high frequency bypass capacitor of approximately 0 1 uF connected between Vcc and Vss using leads and traces that are as short as possible As with all high speed CMOS ICs careful routing of power ground and signals reduce circuit noise Hardware Protect The STK14C88 5 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low voltage condi tions When Vcap lt VswiTcH all externally initiated STORE operations and SRAM WRITEs are inhibited AutoStore can be completely disabled by tying VCC to ground and applying 5V to Vcap This is the AutoStore I
5. Input and Output Timing Reference Levels 1 5V Note 8 These parameters are guaranteed by design and are not tested Document Number 001 51038 Rev Page 8 of 17 Feedback CYPRESS STK14C88 5 AC Switching Characteristics SRAM Read Cycle Parameter 35 ns 45 ns Cypress Description x Unit Parameter Alt Min Max Min Max ACE TELOV Chip Enable Access Time 35 45 ns tac P tavav ELEH Read Cycle Time 35 45 ns tan 10 tavav Address Access Time 35 45 ns tpoE teLav Output Enable to Data Valid 15 20 ns oHa 10 taxax Output Hold After Address Change ns tice H TELOX Chip Enable to Output Active ns tuzce TEHOZ Chip Disable to Output Inactive 13 15 ns LZOE 1 aLax Output Enable to Output Active 0 0 ns tuzog teHaz Output Disable to Output Inactive 13 15 ns py 8 tELICCH Chip Enable to Power Active 0 0 ns tpp TEHICCL Chip Disable to Power Standby 35 45 ns Switching Waveforms Figure 8 SRAM Read Cycle 1 Address Controlled 1 trc ADDRESS Tax gt tona DQ DATA OUT DATA VALID gt lt gt lt Figure 9 SRAM Read Cycle 2 CE and OE Controlled 9 trc gt ADDRESS lt tace gt k trp gt CE lt tizce gt lt tuzce gt OE t too N HZOE gt tizoe DQ DATA OUT j DATA VALID lt try ACTIVE ICC STANDB
6. sequence is aborted and no STORE or RECALL takes place To initiate the software STORE cycle the following READ sequence is performed Read address 0x0E38 Valid READ Read address 0x31C7 Valid READ Read address 0x03E0 Valid READ Read address 0x3C1F Valid READ Read address 0x303F Valid READ 6 Read address 0x0FCO Initiate STORE cycle The software sequence is clocked with CE controlled READs When the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled It is important that READ cycles and not WRITE cycles are used in the sequence It is not necessary that OE is LOW for a valid sequence After the tstore cycle time is fulfilled the SRAM is again activated for READ and WRITE operation Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation To initiate the RECALL cycle the following sequence of CE controlled READ operations is performed 1 Read address 0x0E38 Valid READ Read address 0x31C7 Valid READ Read address 0x03E0 Valid READ Read address 0x3C1F Valid READ Read address 0x303F Valid READ 6 Read address 0x0C63 Initiate RECALL cycle Internally RECALL is a two step procedure First the SRAM data is cleared and then the nonvolatile information is transferred into the SRAM cells
7. DQ o 7 are written into the memory if it has valid tgp before the end of a WE controlled WRITE or before the end of an CE controlled WRITE Keep OE HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tuzwe_ after WE goes LOW AutoStore Operation The STK14C88 5 stores data to nvSRAM using one of three storage operations 1 Hardware store activated by HSB 2 Software store activated by an address sequence 3 AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK14C88 5 During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vewitcu the part automatically disconnects the Vcap pin from Voc A STORE operation is initiated with power provided by the Vcap capacitor Figure 3 shows the proper connection of the storage capacitor Vcap for automatic store operation A charge storage capacitor Document Number 001 51038 Rev STK14C88 5 having a capacitor of between 68uF and 220uF 20 rated at 6V should be provided The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip A pull up is placed on WE to hold it inactive during power up Figure 3 AutoStore M
8. 14C88 5C45M 001 51694 32 pin CDIP 300 mil STK14C88 5K45M 001 51694 32 pin CDIP 300 mil STK14C88 5L45M 51 80068 32 pin LCC 450mil The above table contains Final information Please contact your local Cypress sales representative for availability of these parts Document Number 001 51038 Rev Page 14 of 17 Feedback CYPRESS STK14C88 5 Package Diagram Figure 15 32 Pin 300 Mil Side Braze DIL 001 51694 40 26 1 585 ooo 1 615 ql 128 aan PIN 1 INDEX i a 1 52 PIN 16 a Bat spag i A TAR 38 048 12 38 052 1 32 mie 110 2 79 1 ALL DIMENSIONS ARE IN MILLIMETERS AND INCHS MIN MAX 2 PACKAGE WEIGHT TBD 001 51694 Document Number 001 51038 Rev Page 15 of 17 Feedback PERFORM STK14C88 5 Package Diagram continued Figure 16 32 Pad 450 Mil LCC 51 80068 al Ul Ul ae PIN 1 055 C Ann n om 0e ZEE See Te a fo e 045 3 055 aa ad K 32 PLACES _ mla e ojo 440 i 458 Document Number 001 51038 Rev DIMENSIONS IN INCHES MIN MAX 064 090 060 080 51 80068 Page 16 of 17 Feedback E A CYPRESS STK14C88 5 PERFORM Document History Page Document Title STK14C88 5 256 Kbit 32K x 8 AutoStore nvSRAM Document Number 001 51038 Orig of Submission in
9. 20 us at the onset of a STORE When the STK14C88 5 is connected for AutoStore operation system Vcc connected to Vcc and a 68 uF capacitor on Vcap and Vcc crosses Vswitcy 0n the way down the STK14C88 5 attempts to pull HSB LOW If HSB does not actually get below Vj the part stops trying to pull HSB LOW and abort the STORE attempt Page 5 of 17 Feedback E L CYPRESS Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the produc s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices m The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprogram these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration cold or warm boot status and so on should always program a unique NV pattern for example complex 4 byte pattern of 46 E6 49 53 hex or more random bytes as part of the final system Table 1 Hardware Mode Selection STK14C88 5 manufacturing test to ensure these system routines work consistently m Power up boot firmware routines should r
10. DATA VALID Page 12 of 17 Feedback oF CYPRESS IFPRI STK14C88 5 Hardware STORE Cycle STK14C88 5 Parameter Alt Description Unit Min Max DHSB 16 20 tRECOVER tuHax Hardware STORE High to Inhibit Off 700 ns tpHsB tuLHx Hardware STORE Pulse Width 15 ns tuLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveforms HSB IN TN lt tense buse gt HSB OUT DQ DATA OUT Note Figure 14 Hardware STORE Cycle tstore lt thee gt HIGH IMPEDANCE lt toeLay gt HIGH IMPEDANCE DATA VALID 20 tnHsg is only applicable after tstore is complete Document Number 001 51038 Rev K X DATA VALID Page 13 of 17 Feedback CYPRESS STK14C88 5 Part Numbering Nomenclature STK14C88 5 C 35 M Temperature Range M Military 55 to 125 C Speed 35 35 ns 45 45 ns Package C Ceramic 32 pin 300 mil DIP K Ceramic 32 pin 300 mil DIP Solder dip finish L Ceramic 32 pin LLC Retention Endurance 5 Military 10 years or 10 cycles Ordering Information ee Ordering Code Package Diagram Package Type San 35 STK14C88 5C35M 001 51694 32 pin CDIP 300 mil Military STK14C88 5K35M 001 51694 32 pin CDIP 300 mil STK14C88 5L35M 51 80068 32 pin LCC 450 mil 45 STK
11. LOW Vreser BELOW Vereset ABOVE VSWITCH Notes 15 tHBECALL Starts from the time Vcc rises above VsWiTCH 16 CE and OE low and WE high for output behavior 17 HSB is asserted low for 1us when Vcap drops through VswiTcH If an SRAM WRITE has not taken place since the last nonvolatile cycle HSB is released and no store takes place Document Number 001 51038 Rev Page 11 of 17 Feedback CYPRESS STK14C88 5 Software Controlled STORE RECALL Cycle The software controlled STORE RECALL cycle follows 91 35 ns 45 ns Parameter Alt Description Unit Min Max Min Max rcl 6l AVAV STORE RECALL lnitiation Cycle Time 35 45 ns tsal 191 AVEL Address Setup Time 0 0 ns toy 191 TELEH Clock Pulse Width 25 30 ns tHacE 19 teLax Address Hold Time 20 20 ns TRECALL RECALL Duration 20 20 us Switching Waveforms ADDRESS Figure 13 CE Controlled Software STORE RECALL Cycle 9 tre gt tre ADDRESS 1 X j ADDRESS 6 iia A aN J coco Notes 18 The software sequence is clocked on the falling edge of CE without involving OE double clocking aborts the sequence 19 The six consecutive addresses must be read in the order listed in the Mode Selection table WE must be HIGH during all six consecutive cycles Document Number 001 51038 Rev a lt T gt TT tstore RECALL HIGH IMPEDANCE lt
12. Y 4 Notes _ 9 WE and HSB must be HIGH during SRAM Read cycles 10 Device is continuously selected with CE and OE both Low 11 Measured 200 mV from steady state output voltage Document Number 001 51038 Rev Page 9 of 17 Feedback a cypress STK14C88 5 SRAM Write Cycle Parameter 35 ns 45 ns Description ni ee ieee Alt Sonu Min Max Min Max pat twe tavav Write Cycle Time 35 45 ns tpwe WLWH tWLEH Write Pulse Width 25 30 ns tsce ELWH tELEH Chip Enable To End of Write 25 30 ns tsp TDVWH DVEH Data Setup to End of Write 12 15 ns THD tWHDx EHDX Data Hold After End of Write 0 0 ns taw AVWH AVEH Address Setup to End of Write 25 30 ns tsa tavw_ AVEL Address Setup to Start of Write 0 0 ns THA twHax TEHAX Address Hold After End of Write 0 0 ns tuzwe 1 twLaz Write Enable to Output Disable 13 15 ns we TWHOX Output Active After End of Write 5 5 ns Switching Waveforms Figure 10 SRAM Write Cycle 1 WE Controlled 14 I lt tc ADDRESS lt tua n lt tsce CE lt taw gt k tg lt tewe gt WE lt tsp gt lt tho gt DATA IN j DATA VALID gt lt tuzwe i lt tiae DATA OUT PREVIOUS DATA Figure 11 SRAM Write Cycle 2 CE Controlled 3 14 lt tw
13. cted to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circ
14. d Vss 6V rated 68 uF 20 nom 54 260 uF Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 100 Years NV Nonvolatile STORE Operations 1 000 K Notes 6 Voc reference levels throughout this data sheet refer to Vag if that is where the power supply connection is made or Vcap if Voc is connected to ground 7 CE gt Viy does not produce standby current levels until any nonvolatile cycle in progress has timed out Document Number 001 51038 Rev Page 7 of 17 CYPRESS STK14C88 5 Capacitance In the following table the capacitance parameters are listed 8 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ty 25 C f 1 MHz 5 pF Cout Output Capacitance Vcc 0 to 3 0V 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed Parameter Description Test Conditions 32 CDIP 32 LCC Unit Oja Thermal Resistance Test conditions follow standard test methods TBD TBD C W Junction to Ambient and procedures for measuring thermal Ojc Thermal Resistance impedance per EIA JESD51 TBD TBD C W Junction to Case Figure 7 AC Test Loads R1 9630 R1 9630 For Tri state Specs 5 0V 5 0V Output Output 30 pF R2 5 pF R2 5120 5120 AC Test Conditions Input Pulse Levels o ooronnnonnnnnonn nn OV to 3V Input Rise and Fall Times 10 90 ooensrrnnnncm lt 5 ns
15. e on page 5 It is not permissible to change between these three options on the fly Page 3 of 17 Feedback CYPRESS Figure 4 AutoStore Inhibit Mode NT al os 10k Ohm Vow Z Vec HSB 10k Ohm WE C LI Hardware STORE HSB Operation The STK14088 5 provides the HSB pin for controlling and acknowledging the STORE operations The HSB pin is used to request a hardware STORE cycle When the HSB pin is driven LOW the STK14C88 5 conditionally initiates a STORE operation after tpg ay An actual STORE cycle only begins if a WRITE to the SRAM takes place since the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE initiated by any means is in progress Pull up this pin with an external 10K ohm resistor to Vcap if HSB is used as a driver SRAM READ and WRITE operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated After HSB goes LOW the STK14C88 5 continues SRAM operations for tngL ay During tpeLay Multiple SRAM READ operations take place If a WRITE is in progress when HSB is pulled LOW it allows a time tpg ay to complete However any SRAM WRITE cycles requested after HSB goes LOW are inhibited until HSB returns HIGH During any STORE operation regardless of how it is initiat
16. e gt ADDRESS lt tsa tsce gt lt tha gt CE lt taw gt WE x tewe gt tso gt lt tho DATA IN DATA VALID DATA OUT HIGH IMPEDANCE Notes 12 If WE is Low when CE goes Low the outputs remain in the high impedance state 13 HSB must be high during SRAM WRITE cycles 14 CE or WE must be greater than Vj during address transitions Document Number 001 51038 Rev Page 10 of 17 Feedback E CYPRES STK14C88 5 PERFORM AutoStore or Power Up RECALL Parameter Alt Description S picid Unit Min Max tHRECALL 15 tRESTORE Power up RECALL Duration 550 HS tsTORE 16 tHLHz STORE Cycle Duration 10 ms tpeiay HLOZ IBLOZ Time Allowed to Complete SRAM Cycle 1 HS VSWITCH Low Voltage Trigger Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 6 V tvccRISE Vec Rise Time 150 HS tvsau Low Voltage Trigger VswiTcH to HSB low 300 ns Switching Waveforms Figure 12 AutoStore Power Up RECALL Voc VRESET AutoStore POWER UP RECALL y P RECALL tyssi m gee tstor HSB toevay WE DQ DATA OUT gt gt lt gt lt lt POWER UP BROWN OUT BROWN OUT BROWN OUT RECALL NO STORE AutoStore AutoStore NO SRAM WRITES NO RECALL NO RECALL RECALL WHEN Vec DID NOT GO Vec DID NOT GO Vcc RETURNS BE
17. ed the STK14C88 5 continues to drive the HSB pin LOW releasing it only when the STORE is complete After completing the STORE operation the STK14C88 5 remains disabled until the HSB pin returns HIGH If HSB is not used it is left unconnected Hardware RECALL Power Up During power up or after any low power condition Vcc lt VRESET an internal RECALL request is latched When Vcc once again exceeds the sense voltage of Vewitcy a RECALL cycle is automatically initiated and takes tHRECALL to complete Document Number 001 51038 Rev STK14C88 5 If the STK14C88 5 is in a WRITE state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm resistor is connected either between WE and system Vcc or between CE and system Vcc Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The STK14C88 5 software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements When a STORE cycle is initiated input and output are disabled until the cycle is completed Because a sequence of READs from specific addresses is used for STORE initiation itis important that no other READ or WRITE accesses intervene in the sequence If they intervene the
18. erates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation This unique architecture enables the storage and recall of all cells in parallel During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited The STK14C88 5 supports unlimited reads and writes similar to atypical SRAM In addition it provides unlimited RECALL opera tions from the nonvolatile cells and up to one million STORE operations SRAM Read The STK14C88 5 performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH The address specified on pins Ag 14 determines the 32 768 data bytes accessed When the READ is initiated by an address transition the outputs are valid after a delay of taa READ cycle 1 If the READ is initiated by CE or OE the outputs are valid at tace or at tpog whichever is later READ cycle 2 The data outputs repeatedly respond to address changes within the ta access time without the need for transitions on any control input_pins and remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle The data on the common IO pins
19. ewrite the nvSRAM into the desired state While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently program bugs incoming inspection routines and so on m The Vcap value specified in this data sheet includes a minimum and a maximum value size Best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor Customers that want to use a larger Vcap value to make sure there is extra store charge should discuss their Vcap size selection with Cypress to understand any impact on the Vcap voltage level at the end of A tRecaLL period CE WE HSB A13 A0 Mode IO Power H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Activel L L H X Write SRAM Input Data Active X X L X Nonvolatile STORE Output High Z leo L H H 0x0E 38 Read SRAM Output Data Active lccol 3 5l 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data 0x3C1F Read SRAM Output Data 0x303F Read SRAM Output Data 0x0FCO Nonvolatile STORE Output High Z L H H 0x0E 38 Read SRAM Output Data Activel1 3 4 5 0x31C7 Read SRAM Output Data 0x03E0 Read SRAM Output Data 0x3C1F Read SRAM Output Data 0x303F Read SRAM Output Data 0x0C63 Nonvolatile RECALL Output High Z Notes
20. nhibit mode in this mode STOREs are only initiated_by explicit request using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the STK14C88 5 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns Figure 5 and Figure 6 shows the relationship between Ice and READ or WRITE cycle time Worst case current consumption is shown for both CMOS and TTL input levels commercial temperature range VCC 5 5V 100 duty cycle on chip enable Only standby current is drawn when the chip is disabled The overall average current drawn by the STK14C88 5 depends on the following items m The duty cycle of chip enable m The overall cycle rate for accesses m The ratio of READs to WRITEs m CMOS versus TTL input levels m The operating temperature m The Vcc level m IO loading Document Number 001 51038 Rev STK14C88 5 Figure 5 Current Versus Cycle Time READ 100 TTL Average Active Current mA CMOS o so 100 150 200 Cycle Time ns Figure 6 Current Versus Cycle Time WRITE 100 o lt E z 60 o on lt 40 gt g CMOS S lt 20 0 50 100 150 200 Cycle Time ns Preventing Store The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a Voy of at least 2 2V because it has to overpower the internal pull down device This device drives HSB LOW for
21. o A14 Input Address Inputs Used to select one of the 32 768 bytes of the nvSRAM DQ 9 DQ7 Input or Output Bidirectional Data IO Lines Used as input or output lines depending on operation WE W Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselecis the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state Vss Ground Ground for the Device The device is connected to ground of the system Vec Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin high if not connected connection optional VCGAP Power Supply AutoStore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements Document Number 001 51038 Rev Page 2 of 17 Feedback CYPRESS Device Operation The STK14C88 5 nvSRAM is made up of two functional compo nents paired in the same physical cell These are an SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell op
22. ode In system power mode both Vcc and Vcap are connected to the 5V power supply without the 68 uF capacitor In this mode the AutoStore function of the STK14C88 5 operates on the stored system charge as power goes down The user must however guarantee that Vcc does not drop below 3 6V during the 10 ms STORE cycle To reduce unnecessary nonvolatile stores AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place An optional pull up resistor is shown connected to HSB The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress If the power supply drops faster than 20 us volt before Vcc reaches VswiTCH then a 2 2 ohm resistor should be connected between Vcc and the system supply to avoid momentary excess of current between Vec and Vcap AutoStore Inhibit mode If an automatic STORE on power loss is not required then Voc is tied to ground and 5V is applied to Veap Figure 4 This is the AutoStore Inhibit mode where the AutoStore function is disabled If the STK14C88 5 is operated in this configuration references to Vcc are changed to Vcap throughout this data sheet In this mode STORE operations are triggered through software control or the HSB pin To enable or disable Autostore using an I O port pin se
23. racteristics Over the operating range Vcc 4 5V to 5 5V el Parameter Description Test Conditions Min Max Unit loci Average Vcc Current trac 35 ns 85 mA tRC 45ns 70 mA Dependent on output loading and cycle rate Values obtained without output loads lout s O MA loce Average Vcc Current All Inputs Do Not Care Voc Max 3 mA during STORE Average current for duration tsTORE locg Average Vcc Current at WE gt Vcc 0 2V All other inputs cycling 10 mA trc 200 ns 5V 25 C Dependent on output loading and cycle rate Values obtained Typical without output loads loca Average Vcap Current All Inputs Do Not Care Voc Max 2 mA during AutoStore Cycle Average current for duration tsTORE Isg Vcc Standby Current trc 35 ns CE gt Viy 26 mA Standby Cycling TTL trc 45 ns CE gt Viy 23 mA Input Levels Isg2 Vcc Standby Current CE gt Voc 0 2V All others Viy lt 0 2V or gt Vec 0 2V 1 5 mA Standby current level after nonvolatile cycle is complete Inputs are static f 0 MHZ lix Input Leakage Current Vec Max Vss lt Vins Voc 1 1 pA loz Off State Output Leakage Vcc Max Vss lt Vin lt Vec CE or OE gt Vip or WE lt Vil 5 5 uA Current Vin Input HIGH Voltage 2 2 Voc V 0 5 Vit Input LOW Voltage Vss 0 8 V 0 5 VOH Output HIGH Voltage lout gt 4 MA 2 4 V VoL Output LOW Voltage lout 8 MA 0 4 V VBL Logic 0 Voltage on HSB lour gt 3 MA 0 4 V Output VGAP Storage Capacitor Between Vcap pin an
24. ti Rev ECN No Change Date Description of Change mt 2666844 GVCH PYRS 03 02 09 New data sheet Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expe
25. uit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 51038 Rev Revised March 02 2009 Page 17 of 17 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
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